Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.57 97.84 93.74 97.44 75.00 96.25 98.17 96.58


Total test records in report: 2617
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T263 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2258016245 Jun 25 04:47:16 PM PDT 24 Jun 25 04:47:23 PM PDT 24 284889437 ps
T279 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2567544667 Jun 25 04:47:29 PM PDT 24 Jun 25 04:47:32 PM PDT 24 35656418 ps
T264 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.463820602 Jun 25 04:47:15 PM PDT 24 Jun 25 04:47:20 PM PDT 24 297250349 ps
T2523 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.638790326 Jun 25 04:47:29 PM PDT 24 Jun 25 04:47:34 PM PDT 24 432579314 ps
T2524 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.4125991194 Jun 25 04:47:14 PM PDT 24 Jun 25 04:47:19 PM PDT 24 54853653 ps
T283 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2622148962 Jun 25 04:47:29 PM PDT 24 Jun 25 04:47:32 PM PDT 24 59114311 ps
T287 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3177094787 Jun 25 04:47:13 PM PDT 24 Jun 25 04:47:18 PM PDT 24 537603313 ps
T2525 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3216736432 Jun 25 04:47:26 PM PDT 24 Jun 25 04:47:29 PM PDT 24 94812381 ps
T248 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2173249246 Jun 25 04:47:01 PM PDT 24 Jun 25 04:47:04 PM PDT 24 81275706 ps
T2526 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2953144481 Jun 25 04:47:27 PM PDT 24 Jun 25 04:47:30 PM PDT 24 42139623 ps
T265 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1294174028 Jun 25 04:47:16 PM PDT 24 Jun 25 04:47:26 PM PDT 24 1473025009 ps
T2527 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2418147402 Jun 25 04:46:57 PM PDT 24 Jun 25 04:46:59 PM PDT 24 224061519 ps
T2528 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3011955955 Jun 25 04:47:30 PM PDT 24 Jun 25 04:47:33 PM PDT 24 43524789 ps
T2529 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2193155041 Jun 25 04:47:27 PM PDT 24 Jun 25 04:47:30 PM PDT 24 76589790 ps
T2530 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3628966035 Jun 25 04:47:26 PM PDT 24 Jun 25 04:47:30 PM PDT 24 135473312 ps
T285 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.1987154097 Jun 25 04:47:31 PM PDT 24 Jun 25 04:47:33 PM PDT 24 56650136 ps
T2531 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.3466828676 Jun 25 04:47:28 PM PDT 24 Jun 25 04:47:31 PM PDT 24 49076131 ps
T231 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.400708397 Jun 25 04:47:17 PM PDT 24 Jun 25 04:47:22 PM PDT 24 96973193 ps
T2532 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1000330775 Jun 25 04:47:16 PM PDT 24 Jun 25 04:47:22 PM PDT 24 214953822 ps
T2533 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1825618915 Jun 25 04:46:52 PM PDT 24 Jun 25 04:46:55 PM PDT 24 73198067 ps
T2534 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.929272607 Jun 25 04:47:16 PM PDT 24 Jun 25 04:47:22 PM PDT 24 197548022 ps
T249 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2154862584 Jun 25 04:47:02 PM PDT 24 Jun 25 04:47:12 PM PDT 24 1702425736 ps
T2535 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2412407247 Jun 25 04:47:13 PM PDT 24 Jun 25 04:47:15 PM PDT 24 104636397 ps
T2536 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3918951642 Jun 25 04:47:13 PM PDT 24 Jun 25 04:47:16 PM PDT 24 80223946 ps
T2537 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.468675709 Jun 25 04:46:58 PM PDT 24 Jun 25 04:47:03 PM PDT 24 342114122 ps
T2538 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1623172174 Jun 25 04:47:04 PM PDT 24 Jun 25 04:47:07 PM PDT 24 72273199 ps
T2539 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.2661466251 Jun 25 04:47:31 PM PDT 24 Jun 25 04:47:33 PM PDT 24 43479330 ps
T2540 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.620515132 Jun 25 04:47:01 PM PDT 24 Jun 25 04:47:06 PM PDT 24 103790351 ps
T2541 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.905495438 Jun 25 04:47:28 PM PDT 24 Jun 25 04:47:31 PM PDT 24 58380134 ps
T2542 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.4183283636 Jun 25 04:47:26 PM PDT 24 Jun 25 04:47:28 PM PDT 24 32395218 ps
T2543 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.590478824 Jun 25 04:47:24 PM PDT 24 Jun 25 04:47:27 PM PDT 24 168478468 ps
T2544 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.4219030439 Jun 25 04:47:30 PM PDT 24 Jun 25 04:47:33 PM PDT 24 35377913 ps
T250 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3453938725 Jun 25 04:46:49 PM PDT 24 Jun 25 04:46:54 PM PDT 24 130894705 ps
T2545 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1091898790 Jun 25 04:46:59 PM PDT 24 Jun 25 04:47:01 PM PDT 24 105743437 ps
T2546 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3588418101 Jun 25 04:47:14 PM PDT 24 Jun 25 04:47:20 PM PDT 24 146804079 ps
T2547 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.876244360 Jun 25 04:46:48 PM PDT 24 Jun 25 04:46:52 PM PDT 24 138194942 ps
T2548 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2255581880 Jun 25 04:47:23 PM PDT 24 Jun 25 04:47:26 PM PDT 24 70635818 ps
T290 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.3176712931 Jun 25 04:47:03 PM PDT 24 Jun 25 04:47:09 PM PDT 24 504055717 ps
T288 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1270378158 Jun 25 04:47:26 PM PDT 24 Jun 25 04:47:34 PM PDT 24 960420698 ps
T2549 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3791272217 Jun 25 04:47:15 PM PDT 24 Jun 25 04:47:19 PM PDT 24 48907598 ps
T2550 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.785595302 Jun 25 04:47:29 PM PDT 24 Jun 25 04:47:32 PM PDT 24 43707036 ps
T2551 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.111151220 Jun 25 04:47:07 PM PDT 24 Jun 25 04:47:10 PM PDT 24 154239634 ps
T2552 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.739367454 Jun 25 04:47:03 PM PDT 24 Jun 25 04:47:06 PM PDT 24 110207490 ps
T2553 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3869922223 Jun 25 04:47:00 PM PDT 24 Jun 25 04:47:03 PM PDT 24 274550505 ps
T2554 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.1667920947 Jun 25 04:46:58 PM PDT 24 Jun 25 04:47:00 PM PDT 24 40983414 ps
T2555 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2810191982 Jun 25 04:47:24 PM PDT 24 Jun 25 04:47:27 PM PDT 24 68964696 ps
T2556 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.4236234999 Jun 25 04:47:02 PM PDT 24 Jun 25 04:47:05 PM PDT 24 104650563 ps
T2557 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1613913734 Jun 25 04:46:44 PM PDT 24 Jun 25 04:46:49 PM PDT 24 155059031 ps
T291 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.672764057 Jun 25 04:47:14 PM PDT 24 Jun 25 04:47:22 PM PDT 24 815147658 ps
T2558 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1583702191 Jun 25 04:46:59 PM PDT 24 Jun 25 04:47:03 PM PDT 24 155153630 ps
T2559 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.995186619 Jun 25 04:47:25 PM PDT 24 Jun 25 04:47:29 PM PDT 24 126352722 ps
T2560 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.687661793 Jun 25 04:47:26 PM PDT 24 Jun 25 04:47:28 PM PDT 24 54576644 ps
T2561 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.228815093 Jun 25 04:47:28 PM PDT 24 Jun 25 04:47:32 PM PDT 24 37088125 ps
T2562 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.445237461 Jun 25 04:46:59 PM PDT 24 Jun 25 04:47:01 PM PDT 24 60572183 ps
T2563 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.3071105601 Jun 25 04:47:16 PM PDT 24 Jun 25 04:47:20 PM PDT 24 39522849 ps
T251 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.950680434 Jun 25 04:46:51 PM PDT 24 Jun 25 04:47:05 PM PDT 24 1651318809 ps
T2564 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3413523017 Jun 25 04:47:11 PM PDT 24 Jun 25 04:47:16 PM PDT 24 111566533 ps
T252 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3662773610 Jun 25 04:47:03 PM PDT 24 Jun 25 04:47:08 PM PDT 24 337851645 ps
T253 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3384968793 Jun 25 04:46:55 PM PDT 24 Jun 25 04:46:58 PM PDT 24 173124265 ps
T2565 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3255138880 Jun 25 04:47:26 PM PDT 24 Jun 25 04:47:29 PM PDT 24 77865204 ps
T2566 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.287238471 Jun 25 04:46:53 PM PDT 24 Jun 25 04:46:56 PM PDT 24 71316946 ps
T292 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.898706630 Jun 25 04:47:15 PM PDT 24 Jun 25 04:47:23 PM PDT 24 503874227 ps
T2567 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1808373484 Jun 25 04:47:24 PM PDT 24 Jun 25 04:47:27 PM PDT 24 151651266 ps
T2568 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.4039610985 Jun 25 04:47:27 PM PDT 24 Jun 25 04:47:30 PM PDT 24 93787449 ps
T2569 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.624092777 Jun 25 04:47:05 PM PDT 24 Jun 25 04:47:07 PM PDT 24 68354670 ps
T2570 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2251348733 Jun 25 04:47:16 PM PDT 24 Jun 25 04:47:21 PM PDT 24 210231243 ps
T2571 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.4225646500 Jun 25 04:47:09 PM PDT 24 Jun 25 04:47:12 PM PDT 24 189069485 ps
T2572 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1152614942 Jun 25 04:47:18 PM PDT 24 Jun 25 04:47:21 PM PDT 24 43174436 ps
T2573 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.297951575 Jun 25 04:47:29 PM PDT 24 Jun 25 04:47:32 PM PDT 24 54425750 ps
T2574 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3636909236 Jun 25 04:47:14 PM PDT 24 Jun 25 04:47:19 PM PDT 24 188965623 ps
T255 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3843256869 Jun 25 04:46:49 PM PDT 24 Jun 25 04:46:56 PM PDT 24 374263791 ps
T289 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.757632344 Jun 25 04:47:19 PM PDT 24 Jun 25 04:47:27 PM PDT 24 810883286 ps
T2575 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3474621531 Jun 25 04:47:02 PM PDT 24 Jun 25 04:47:07 PM PDT 24 259751298 ps
T254 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3273396878 Jun 25 04:46:43 PM PDT 24 Jun 25 04:46:49 PM PDT 24 240120477 ps
T2576 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3383240923 Jun 25 04:47:14 PM PDT 24 Jun 25 04:47:19 PM PDT 24 120188986 ps
T2577 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2454559150 Jun 25 04:47:04 PM PDT 24 Jun 25 04:47:06 PM PDT 24 207386681 ps
T2578 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1201411424 Jun 25 04:47:08 PM PDT 24 Jun 25 04:47:10 PM PDT 24 138466065 ps
T2579 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2389617783 Jun 25 04:47:14 PM PDT 24 Jun 25 04:47:18 PM PDT 24 68471825 ps
T2580 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3423230423 Jun 25 04:46:49 PM PDT 24 Jun 25 04:46:53 PM PDT 24 59509450 ps
T2581 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.501275679 Jun 25 04:46:55 PM PDT 24 Jun 25 04:47:00 PM PDT 24 463845557 ps
T2582 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.1603150139 Jun 25 04:47:28 PM PDT 24 Jun 25 04:47:31 PM PDT 24 45321372 ps
T2583 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.1595836442 Jun 25 04:47:16 PM PDT 24 Jun 25 04:47:21 PM PDT 24 146153390 ps
T2584 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3154314218 Jun 25 04:47:05 PM PDT 24 Jun 25 04:47:09 PM PDT 24 252339598 ps
T2585 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.563898021 Jun 25 04:47:12 PM PDT 24 Jun 25 04:47:16 PM PDT 24 270255430 ps
T2586 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2208125649 Jun 25 04:46:45 PM PDT 24 Jun 25 04:46:54 PM PDT 24 527430798 ps
T2587 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3025725742 Jun 25 04:47:11 PM PDT 24 Jun 25 04:47:14 PM PDT 24 169002740 ps
T2588 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2251753589 Jun 25 04:47:27 PM PDT 24 Jun 25 04:47:29 PM PDT 24 55968539 ps
T2589 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.306370021 Jun 25 04:47:14 PM PDT 24 Jun 25 04:47:20 PM PDT 24 148469972 ps
T293 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1974761657 Jun 25 04:47:14 PM PDT 24 Jun 25 04:47:24 PM PDT 24 1604222302 ps
T2590 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.4026904161 Jun 25 04:47:29 PM PDT 24 Jun 25 04:47:32 PM PDT 24 85928984 ps
T2591 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3053164662 Jun 25 04:47:29 PM PDT 24 Jun 25 04:47:32 PM PDT 24 42054745 ps
T2592 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.714972365 Jun 25 04:47:07 PM PDT 24 Jun 25 04:47:09 PM PDT 24 80031998 ps
T2593 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2682477612 Jun 25 04:47:15 PM PDT 24 Jun 25 04:47:20 PM PDT 24 96161634 ps
T2594 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2753067701 Jun 25 04:47:15 PM PDT 24 Jun 25 04:47:22 PM PDT 24 1243037795 ps
T2595 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.392877156 Jun 25 04:46:57 PM PDT 24 Jun 25 04:46:59 PM PDT 24 91782337 ps
T2596 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2293667993 Jun 25 04:46:49 PM PDT 24 Jun 25 04:47:00 PM PDT 24 1268495149 ps
T2597 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.118477857 Jun 25 04:47:13 PM PDT 24 Jun 25 04:47:16 PM PDT 24 60716596 ps
T2598 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2388998350 Jun 25 04:47:22 PM PDT 24 Jun 25 04:47:26 PM PDT 24 107723802 ps
T2599 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2588552516 Jun 25 04:46:53 PM PDT 24 Jun 25 04:46:56 PM PDT 24 77982696 ps
T2600 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.651016110 Jun 25 04:46:57 PM PDT 24 Jun 25 04:47:00 PM PDT 24 94475583 ps
T2601 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1572344753 Jun 25 04:47:24 PM PDT 24 Jun 25 04:47:26 PM PDT 24 48560568 ps
T2602 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2954959567 Jun 25 04:47:18 PM PDT 24 Jun 25 04:47:22 PM PDT 24 89854907 ps
T2603 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2564672301 Jun 25 04:46:48 PM PDT 24 Jun 25 04:46:56 PM PDT 24 525383896 ps
T2604 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3115346253 Jun 25 04:46:48 PM PDT 24 Jun 25 04:46:53 PM PDT 24 118471374 ps
T2605 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1976004043 Jun 25 04:47:17 PM PDT 24 Jun 25 04:47:21 PM PDT 24 68795857 ps
T2606 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.689691127 Jun 25 04:46:48 PM PDT 24 Jun 25 04:46:53 PM PDT 24 112106729 ps
T2607 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.4049876027 Jun 25 04:46:58 PM PDT 24 Jun 25 04:47:00 PM PDT 24 59429214 ps
T2608 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2163703991 Jun 25 04:47:15 PM PDT 24 Jun 25 04:47:20 PM PDT 24 109623365 ps
T2609 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.835738047 Jun 25 04:47:16 PM PDT 24 Jun 25 04:47:20 PM PDT 24 60374808 ps
T2610 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3846412123 Jun 25 04:47:13 PM PDT 24 Jun 25 04:47:15 PM PDT 24 99972185 ps
T2611 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1777694049 Jun 25 04:47:21 PM PDT 24 Jun 25 04:47:25 PM PDT 24 169277390 ps
T2612 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2260424864 Jun 25 04:47:24 PM PDT 24 Jun 25 04:47:30 PM PDT 24 695338571 ps
T2613 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1484046433 Jun 25 04:47:17 PM PDT 24 Jun 25 04:47:22 PM PDT 24 145088940 ps
T2614 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.907272418 Jun 25 04:47:14 PM PDT 24 Jun 25 04:47:17 PM PDT 24 50768317 ps
T2615 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.4252043448 Jun 25 04:47:27 PM PDT 24 Jun 25 04:47:31 PM PDT 24 41076362 ps
T2616 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.2665710951 Jun 25 04:47:23 PM PDT 24 Jun 25 04:47:26 PM PDT 24 72483969 ps
T2617 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1581348379 Jun 25 04:47:25 PM PDT 24 Jun 25 04:47:27 PM PDT 24 33017916 ps

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.2641071575
Short name T4
Test name
Test status
Simulation time 6552139262 ps
CPU time 63.66 seconds
Started Jun 25 05:03:37 PM PDT 24
Finished Jun 25 05:04:44 PM PDT 24
Peak memory 206932 kb
Host smart-4d6494ba-d36c-4017-b9b0-24f90b025c2f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2641071575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.2641071575
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.563271027
Short name T202
Test name
Test status
Simulation time 75760642 ps
CPU time 0.74 seconds
Started Jun 25 04:47:14 PM PDT 24
Finished Jun 25 04:47:18 PM PDT 24
Peak memory 205844 kb
Host smart-0b87f387-0332-4418-9d18-d003a7d88820
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=563271027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.563271027
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.3907594749
Short name T7
Test name
Test status
Simulation time 23326808490 ps
CPU time 23.42 seconds
Started Jun 25 04:58:14 PM PDT 24
Finished Jun 25 04:58:38 PM PDT 24
Peak memory 206716 kb
Host smart-8340bec1-2908-4313-8437-1b1e6d53c808
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3907594749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.3907594749
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2310367574
Short name T194
Test name
Test status
Simulation time 976119591 ps
CPU time 5.24 seconds
Started Jun 25 04:47:03 PM PDT 24
Finished Jun 25 04:47:10 PM PDT 24
Peak memory 206328 kb
Host smart-704f8e22-0176-46ed-972c-02baccbce9fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2310367574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.2310367574
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.3100153004
Short name T35
Test name
Test status
Simulation time 14036076262 ps
CPU time 28.82 seconds
Started Jun 25 05:02:31 PM PDT 24
Finished Jun 25 05:03:01 PM PDT 24
Peak memory 206872 kb
Host smart-a25bc0d6-8f15-4fad-a00a-a3a9c04ba8c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31001
53004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.3100153004
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.1599975626
Short name T36
Test name
Test status
Simulation time 196598466 ps
CPU time 0.88 seconds
Started Jun 25 04:59:38 PM PDT 24
Finished Jun 25 04:59:40 PM PDT 24
Peak memory 206572 kb
Host smart-b4bd0021-1cb0-4212-bc3b-46d637718b7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15999
75626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.1599975626
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.62841435
Short name T24
Test name
Test status
Simulation time 324223704 ps
CPU time 1.17 seconds
Started Jun 25 04:56:24 PM PDT 24
Finished Jun 25 04:56:27 PM PDT 24
Peak memory 206544 kb
Host smart-52df2667-a2c1-49f7-b30f-ef00ceeeb0d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62841
435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.62841435
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3224059688
Short name T205
Test name
Test status
Simulation time 75737978 ps
CPU time 0.72 seconds
Started Jun 25 04:47:28 PM PDT 24
Finished Jun 25 04:47:31 PM PDT 24
Peak memory 205836 kb
Host smart-56d7a9f9-02eb-49fa-83da-9325e02cc8c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3224059688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.3224059688
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.3934977167
Short name T112
Test name
Test status
Simulation time 182617198 ps
CPU time 0.85 seconds
Started Jun 25 05:02:23 PM PDT 24
Finished Jun 25 05:02:25 PM PDT 24
Peak memory 206596 kb
Host smart-6e374829-195f-42a2-9b1a-6a9629d10a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39349
77167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.3934977167
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.449834251
Short name T43
Test name
Test status
Simulation time 144955577 ps
CPU time 0.76 seconds
Started Jun 25 05:00:43 PM PDT 24
Finished Jun 25 05:00:45 PM PDT 24
Peak memory 206480 kb
Host smart-fb34eaab-5d56-416b-8db9-09bc05b057fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44983
4251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.449834251
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.2878997681
Short name T23
Test name
Test status
Simulation time 207417809 ps
CPU time 0.91 seconds
Started Jun 25 05:01:11 PM PDT 24
Finished Jun 25 05:01:13 PM PDT 24
Peak memory 206572 kb
Host smart-fae7ddc4-23b9-4af3-8794-9583a625274f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28789
97681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.2878997681
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.1544993853
Short name T13
Test name
Test status
Simulation time 13305480619 ps
CPU time 11.58 seconds
Started Jun 25 04:56:23 PM PDT 24
Finished Jun 25 04:56:37 PM PDT 24
Peak memory 206864 kb
Host smart-b38585dd-2828-4a19-9ec0-727b0c3d5085
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1544993853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.1544993853
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.644758181
Short name T218
Test name
Test status
Simulation time 221381869 ps
CPU time 2.86 seconds
Started Jun 25 04:47:17 PM PDT 24
Finished Jun 25 04:47:23 PM PDT 24
Peak memory 206328 kb
Host smart-f3f99999-510c-41eb-80ba-016a54e3f0a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=644758181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.644758181
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.3560591303
Short name T95
Test name
Test status
Simulation time 17102336980 ps
CPU time 117.14 seconds
Started Jun 25 04:56:10 PM PDT 24
Finished Jun 25 04:58:09 PM PDT 24
Peak memory 207032 kb
Host smart-5c981106-c835-4b0e-bce0-d56874813fe0
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3560591303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.3560591303
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.4161121516
Short name T177
Test name
Test status
Simulation time 248720353 ps
CPU time 0.97 seconds
Started Jun 25 04:57:18 PM PDT 24
Finished Jun 25 04:57:20 PM PDT 24
Peak memory 206576 kb
Host smart-a2490ae3-d7e9-4cd0-86f8-0dc10bdbad7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41611
21516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.4161121516
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.2925307050
Short name T26
Test name
Test status
Simulation time 61182156 ps
CPU time 0.69 seconds
Started Jun 25 05:02:39 PM PDT 24
Finished Jun 25 05:02:41 PM PDT 24
Peak memory 206492 kb
Host smart-ab65cbdc-9cc1-4d12-b1d9-52af34b93fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29253
07050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.2925307050
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.2395156220
Short name T192
Test name
Test status
Simulation time 534242788 ps
CPU time 1.35 seconds
Started Jun 25 04:56:03 PM PDT 24
Finished Jun 25 04:56:07 PM PDT 24
Peak memory 224264 kb
Host smart-37b08842-bbda-404a-b17d-b5d68036cfe1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2395156220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.2395156220
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.351344752
Short name T268
Test name
Test status
Simulation time 62872808 ps
CPU time 0.69 seconds
Started Jun 25 04:46:52 PM PDT 24
Finished Jun 25 04:46:55 PM PDT 24
Peak memory 206324 kb
Host smart-eb1b8f60-1b08-4387-ac3b-5caf3eb961d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=351344752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.351344752
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.1366671114
Short name T82
Test name
Test status
Simulation time 383609720 ps
CPU time 1.11 seconds
Started Jun 25 04:56:05 PM PDT 24
Finished Jun 25 04:56:08 PM PDT 24
Peak memory 206492 kb
Host smart-4c80f05d-f6a9-407f-bc0a-443eed195941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13666
71114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.1366671114
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.1559995246
Short name T46
Test name
Test status
Simulation time 8645023703 ps
CPU time 81.77 seconds
Started Jun 25 04:56:46 PM PDT 24
Finished Jun 25 04:58:10 PM PDT 24
Peak memory 206884 kb
Host smart-3687034b-53eb-41e0-9324-b64cdcef5feb
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1559995246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.1559995246
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.552618963
Short name T48
Test name
Test status
Simulation time 20169626116 ps
CPU time 18.52 seconds
Started Jun 25 04:56:04 PM PDT 24
Finished Jun 25 04:56:25 PM PDT 24
Peak memory 206684 kb
Host smart-bc642c71-e971-4269-9571-44ff44a0387c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55261
8963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.552618963
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.1454183339
Short name T110
Test name
Test status
Simulation time 387661125 ps
CPU time 1.27 seconds
Started Jun 25 05:01:31 PM PDT 24
Finished Jun 25 05:01:35 PM PDT 24
Peak memory 206524 kb
Host smart-18f303ea-37b6-4d03-98bd-c33e03b0c828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14541
83339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.1454183339
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.4224744260
Short name T243
Test name
Test status
Simulation time 202551477 ps
CPU time 2.37 seconds
Started Jun 25 04:46:51 PM PDT 24
Finished Jun 25 04:46:56 PM PDT 24
Peak memory 214372 kb
Host smart-975129b8-9751-4fdf-b1f9-e38a35c1c617
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4224744260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.4224744260
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.375883557
Short name T270
Test name
Test status
Simulation time 35497274 ps
CPU time 0.67 seconds
Started Jun 25 04:47:05 PM PDT 24
Finished Jun 25 04:47:07 PM PDT 24
Peak memory 206320 kb
Host smart-47090b25-c56e-471c-952e-0a36339ac6ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=375883557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.375883557
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.4024620306
Short name T83
Test name
Test status
Simulation time 196541688 ps
CPU time 0.9 seconds
Started Jun 25 04:57:58 PM PDT 24
Finished Jun 25 04:58:01 PM PDT 24
Peak memory 206600 kb
Host smart-b7c77f27-a9e9-4c9f-9361-4bb61d550406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40246
20306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.4024620306
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.1517975206
Short name T592
Test name
Test status
Simulation time 188994347 ps
CPU time 0.81 seconds
Started Jun 25 04:58:14 PM PDT 24
Finished Jun 25 04:58:16 PM PDT 24
Peak memory 206572 kb
Host smart-07cec545-681a-4842-983b-eb883b0a1566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15179
75206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.1517975206
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1294174028
Short name T265
Test name
Test status
Simulation time 1473025009 ps
CPU time 6.36 seconds
Started Jun 25 04:47:16 PM PDT 24
Finished Jun 25 04:47:26 PM PDT 24
Peak memory 206228 kb
Host smart-88dce17c-580b-4b1b-b65b-99a32a03bfd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1294174028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.1294174028
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/24.usbdev_device_address.2579175554
Short name T84
Test name
Test status
Simulation time 8287680081 ps
CPU time 16.05 seconds
Started Jun 25 05:00:02 PM PDT 24
Finished Jun 25 05:00:19 PM PDT 24
Peak memory 206872 kb
Host smart-4c31e912-33a6-441c-8396-0c210d712f42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25791
75554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.2579175554
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1825618915
Short name T2533
Test name
Test status
Simulation time 73198067 ps
CPU time 0.73 seconds
Started Jun 25 04:46:52 PM PDT 24
Finished Jun 25 04:46:55 PM PDT 24
Peak memory 205932 kb
Host smart-8e9cbdd2-89f9-4a66-9cc6-8ce0f8092b7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1825618915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.1825618915
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.2343520688
Short name T72
Test name
Test status
Simulation time 465511082 ps
CPU time 1.3 seconds
Started Jun 25 04:55:54 PM PDT 24
Finished Jun 25 04:55:57 PM PDT 24
Peak memory 206748 kb
Host smart-bbfc676b-373e-454c-a7d7-0fd44d5177dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23435
20688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.2343520688
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3460522210
Short name T236
Test name
Test status
Simulation time 446609016 ps
CPU time 2.65 seconds
Started Jun 25 04:47:15 PM PDT 24
Finished Jun 25 04:47:22 PM PDT 24
Peak memory 206288 kb
Host smart-0a9a719c-22ca-4006-b57e-34af94f6acfb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3460522210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.3460522210
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.3853066473
Short name T12
Test name
Test status
Simulation time 4295773079 ps
CPU time 5.26 seconds
Started Jun 25 05:01:52 PM PDT 24
Finished Jun 25 05:01:58 PM PDT 24
Peak memory 206676 kb
Host smart-d92bdb02-d3e8-4aa1-af3b-149a3db036e6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3853066473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.3853066473
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.1661543139
Short name T56
Test name
Test status
Simulation time 326679395 ps
CPU time 1 seconds
Started Jun 25 04:56:03 PM PDT 24
Finished Jun 25 04:56:07 PM PDT 24
Peak memory 206572 kb
Host smart-a2601522-86b3-4d2e-af56-360c2e45bc5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16615
43139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.1661543139
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.4274390490
Short name T67
Test name
Test status
Simulation time 149741044 ps
CPU time 0.78 seconds
Started Jun 25 04:55:56 PM PDT 24
Finished Jun 25 04:55:58 PM PDT 24
Peak memory 206512 kb
Host smart-a9effc2d-e8ea-4b60-ba71-ec370a4828fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42743
90490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.4274390490
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.287238471
Short name T2566
Test name
Test status
Simulation time 71316946 ps
CPU time 0.77 seconds
Started Jun 25 04:46:53 PM PDT 24
Finished Jun 25 04:46:56 PM PDT 24
Peak memory 205780 kb
Host smart-b73a2d36-0e78-400e-b6b2-c1d372a851b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=287238471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.287238471
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.757632344
Short name T289
Test name
Test status
Simulation time 810883286 ps
CPU time 5.13 seconds
Started Jun 25 04:47:19 PM PDT 24
Finished Jun 25 04:47:27 PM PDT 24
Peak memory 206312 kb
Host smart-aba19b0c-c37d-41c0-b2d0-c2a83550b967
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=757632344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.757632344
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.898706630
Short name T292
Test name
Test status
Simulation time 503874227 ps
CPU time 3.17 seconds
Started Jun 25 04:47:15 PM PDT 24
Finished Jun 25 04:47:23 PM PDT 24
Peak memory 206296 kb
Host smart-f39bd2c6-c4c8-4c82-bbaa-ab61e659df56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=898706630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.898706630
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.2059716725
Short name T164
Test name
Test status
Simulation time 16545678107 ps
CPU time 91.15 seconds
Started Jun 25 04:57:09 PM PDT 24
Finished Jun 25 04:58:41 PM PDT 24
Peak memory 206960 kb
Host smart-6afdfb81-da23-49c3-bad7-f5eb701487f9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2059716725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.2059716725
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.492476427
Short name T230
Test name
Test status
Simulation time 336928604 ps
CPU time 3.02 seconds
Started Jun 25 04:47:03 PM PDT 24
Finished Jun 25 04:47:08 PM PDT 24
Peak memory 206224 kb
Host smart-5152d88b-9e3b-401f-97cd-c4e696e8728d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=492476427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.492476427
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.3041263762
Short name T58
Test name
Test status
Simulation time 180114689 ps
CPU time 0.95 seconds
Started Jun 25 04:55:55 PM PDT 24
Finished Jun 25 04:55:58 PM PDT 24
Peak memory 206580 kb
Host smart-d4472987-677f-4868-88fc-d58b1c154aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30412
63762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.3041263762
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.3867042380
Short name T163
Test name
Test status
Simulation time 13929303720 ps
CPU time 30.63 seconds
Started Jun 25 05:01:11 PM PDT 24
Finished Jun 25 05:01:43 PM PDT 24
Peak memory 206920 kb
Host smart-e7401a62-021d-4083-a3a1-df28e2f19ed5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38670
42380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.3867042380
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.3489840748
Short name T493
Test name
Test status
Simulation time 152850744 ps
CPU time 0.79 seconds
Started Jun 25 04:56:11 PM PDT 24
Finished Jun 25 04:56:13 PM PDT 24
Peak memory 206568 kb
Host smart-eaccea7d-280e-4d7c-9761-e374a71ff4cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34898
40748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.3489840748
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.1291071522
Short name T186
Test name
Test status
Simulation time 23348305315 ps
CPU time 22.36 seconds
Started Jun 25 04:58:58 PM PDT 24
Finished Jun 25 04:59:22 PM PDT 24
Peak memory 206580 kb
Host smart-6673c177-0385-4464-8c15-325336e93dbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12910
71522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.1291071522
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.2586420406
Short name T65
Test name
Test status
Simulation time 139233234 ps
CPU time 0.8 seconds
Started Jun 25 04:56:02 PM PDT 24
Finished Jun 25 04:56:05 PM PDT 24
Peak memory 206572 kb
Host smart-2a48771b-c7a8-43b9-a36d-7f453d67e918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25864
20406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.2586420406
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.4091379284
Short name T502
Test name
Test status
Simulation time 425657387 ps
CPU time 2.66 seconds
Started Jun 25 04:58:55 PM PDT 24
Finished Jun 25 04:59:00 PM PDT 24
Peak memory 206756 kb
Host smart-ccf71462-d0b3-491e-92ef-a6c0b7d07a06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40913
79284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.4091379284
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.1183335202
Short name T339
Test name
Test status
Simulation time 3998844524 ps
CPU time 37.33 seconds
Started Jun 25 05:01:03 PM PDT 24
Finished Jun 25 05:01:42 PM PDT 24
Peak memory 206848 kb
Host smart-57fbbd89-7d8d-4825-b8f0-f2a37b10711d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11833
35202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.1183335202
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.4194351844
Short name T68
Test name
Test status
Simulation time 4224020256 ps
CPU time 8.31 seconds
Started Jun 25 04:55:54 PM PDT 24
Finished Jun 25 04:56:03 PM PDT 24
Peak memory 206800 kb
Host smart-14b85d30-14a1-4c1d-8df2-dac88c4e343e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41943
51844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.4194351844
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.2463186454
Short name T69
Test name
Test status
Simulation time 204830840 ps
CPU time 0.81 seconds
Started Jun 25 04:55:55 PM PDT 24
Finished Jun 25 04:55:57 PM PDT 24
Peak memory 206496 kb
Host smart-8fe4866c-706d-4d4c-a331-4d6f6216ba3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24631
86454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.2463186454
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.1089953588
Short name T2098
Test name
Test status
Simulation time 234085841 ps
CPU time 0.87 seconds
Started Jun 25 04:56:01 PM PDT 24
Finished Jun 25 04:56:02 PM PDT 24
Peak memory 206504 kb
Host smart-8334e0cb-22e5-40c1-8d1b-5669d016f645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10899
53588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.1089953588
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.2954779755
Short name T27
Test name
Test status
Simulation time 58822266 ps
CPU time 0.71 seconds
Started Jun 25 04:57:57 PM PDT 24
Finished Jun 25 04:58:00 PM PDT 24
Peak memory 206512 kb
Host smart-9a8df513-a7ea-4b14-ad8c-bc345fd443fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29547
79755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.2954779755
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.2058920075
Short name T53
Test name
Test status
Simulation time 192019626 ps
CPU time 0.82 seconds
Started Jun 25 04:56:23 PM PDT 24
Finished Jun 25 04:56:25 PM PDT 24
Peak memory 206500 kb
Host smart-a8075e8d-a2bc-42e3-809d-cc8e8d74c2fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20589
20075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.2058920075
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.3763997566
Short name T171
Test name
Test status
Simulation time 18988259419 ps
CPU time 39.18 seconds
Started Jun 25 05:01:30 PM PDT 24
Finished Jun 25 05:02:11 PM PDT 24
Peak memory 206916 kb
Host smart-3e80dfe2-fef9-4b46-a4ad-c37c36310cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37639
97566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.3763997566
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.1566630515
Short name T158
Test name
Test status
Simulation time 25619636467 ps
CPU time 161.61 seconds
Started Jun 25 04:57:20 PM PDT 24
Finished Jun 25 05:00:04 PM PDT 24
Peak memory 206928 kb
Host smart-26c9a9ac-2c39-4593-a2da-a8ee3b9dbfcc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1566630515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.1566630515
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.2839657768
Short name T118
Test name
Test status
Simulation time 185101421 ps
CPU time 0.83 seconds
Started Jun 25 04:55:52 PM PDT 24
Finished Jun 25 04:55:54 PM PDT 24
Peak memory 206596 kb
Host smart-f673e157-09d1-4317-8921-db9d91444f00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28396
57768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.2839657768
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.2109818238
Short name T21
Test name
Test status
Simulation time 234853098 ps
CPU time 0.89 seconds
Started Jun 25 04:56:08 PM PDT 24
Finished Jun 25 04:56:10 PM PDT 24
Peak memory 206520 kb
Host smart-6bde33ca-0f76-477a-a83d-ad61bfc71868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21098
18238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.2109818238
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.2735536143
Short name T42
Test name
Test status
Simulation time 16453601720 ps
CPU time 99.84 seconds
Started Jun 25 04:56:03 PM PDT 24
Finished Jun 25 04:57:46 PM PDT 24
Peak memory 206928 kb
Host smart-1111da5e-9318-40f1-bca4-d67efb3ed130
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2735536143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.2735536143
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.1755965537
Short name T55
Test name
Test status
Simulation time 418261587 ps
CPU time 1.31 seconds
Started Jun 25 04:56:02 PM PDT 24
Finished Jun 25 04:56:06 PM PDT 24
Peak memory 206572 kb
Host smart-e25361ab-fc80-49c5-88d8-b2709e8f3e0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17559
65537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.1755965537
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.1518082144
Short name T1248
Test name
Test status
Simulation time 165388596 ps
CPU time 0.91 seconds
Started Jun 25 04:56:10 PM PDT 24
Finished Jun 25 04:56:13 PM PDT 24
Peak memory 206584 kb
Host smart-9b86c97e-b437-46c6-8d9a-2ee8e7201f96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15180
82144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.1518082144
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.1090957878
Short name T123
Test name
Test status
Simulation time 163669736 ps
CPU time 0.84 seconds
Started Jun 25 04:57:57 PM PDT 24
Finished Jun 25 04:57:59 PM PDT 24
Peak memory 206504 kb
Host smart-9a6feb41-4e28-463b-8ea0-82d2bb949a77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10909
57878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.1090957878
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.1728557569
Short name T137
Test name
Test status
Simulation time 245056097 ps
CPU time 0.87 seconds
Started Jun 25 04:58:04 PM PDT 24
Finished Jun 25 04:58:07 PM PDT 24
Peak memory 206588 kb
Host smart-8ed1786a-dbc1-42e6-a3c3-e87296d279dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17285
57569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.1728557569
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.2839687339
Short name T94
Test name
Test status
Simulation time 18172599016 ps
CPU time 44.89 seconds
Started Jun 25 04:58:06 PM PDT 24
Finished Jun 25 04:58:53 PM PDT 24
Peak memory 206924 kb
Host smart-52bdc814-52a7-4d4f-9695-c6d1f15d68ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28396
87339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.2839687339
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.2018054592
Short name T2100
Test name
Test status
Simulation time 263290152 ps
CPU time 0.92 seconds
Started Jun 25 04:58:15 PM PDT 24
Finished Jun 25 04:58:18 PM PDT 24
Peak memory 206592 kb
Host smart-0a4d7fe7-3e36-4d77-86d3-b194283c3b24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20180
54592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.2018054592
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.781811706
Short name T1175
Test name
Test status
Simulation time 188567916 ps
CPU time 0.83 seconds
Started Jun 25 04:58:23 PM PDT 24
Finished Jun 25 04:58:26 PM PDT 24
Peak memory 206544 kb
Host smart-1ea414fe-e22e-4c64-ab9d-d3d7b1475f25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78181
1706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.781811706
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.1115523436
Short name T2417
Test name
Test status
Simulation time 240917162 ps
CPU time 0.89 seconds
Started Jun 25 04:58:47 PM PDT 24
Finished Jun 25 04:58:49 PM PDT 24
Peak memory 206556 kb
Host smart-f9ba6c7e-dab9-4565-8950-5d0beff8d5e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11155
23436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.1115523436
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.1989242652
Short name T121
Test name
Test status
Simulation time 219493308 ps
CPU time 0.92 seconds
Started Jun 25 04:59:21 PM PDT 24
Finished Jun 25 04:59:23 PM PDT 24
Peak memory 206496 kb
Host smart-0c39812f-f838-4ff4-847e-caaea6801e72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19892
42652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.1989242652
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.2309364563
Short name T136
Test name
Test status
Simulation time 220593059 ps
CPU time 0.99 seconds
Started Jun 25 04:59:52 PM PDT 24
Finished Jun 25 04:59:53 PM PDT 24
Peak memory 206600 kb
Host smart-53ec3856-d6ae-4a23-bcc4-3457735471dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23093
64563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.2309364563
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.1822895904
Short name T128
Test name
Test status
Simulation time 204404322 ps
CPU time 0.86 seconds
Started Jun 25 05:00:21 PM PDT 24
Finished Jun 25 05:00:23 PM PDT 24
Peak memory 206580 kb
Host smart-91cb380e-7154-4df9-b72e-419258dda823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18228
95904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.1822895904
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.3271373048
Short name T131
Test name
Test status
Simulation time 217797803 ps
CPU time 0.86 seconds
Started Jun 25 05:00:29 PM PDT 24
Finished Jun 25 05:00:32 PM PDT 24
Peak memory 206488 kb
Host smart-f35c6e83-0aba-45fe-9b2f-ce89e24f4dde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32713
73048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.3271373048
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3662773610
Short name T252
Test name
Test status
Simulation time 337851645 ps
CPU time 3.56 seconds
Started Jun 25 04:47:03 PM PDT 24
Finished Jun 25 04:47:08 PM PDT 24
Peak memory 206240 kb
Host smart-50125065-69d2-455e-b108-0456801f6cb0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3662773610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.3662773610
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2154862584
Short name T249
Test name
Test status
Simulation time 1702425736 ps
CPU time 7.98 seconds
Started Jun 25 04:47:02 PM PDT 24
Finished Jun 25 04:47:12 PM PDT 24
Peak memory 206248 kb
Host smart-61b59c77-9010-44b0-a3bf-8d5ffe6646ec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2154862584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.2154862584
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2454559150
Short name T2577
Test name
Test status
Simulation time 207386681 ps
CPU time 0.95 seconds
Started Jun 25 04:47:04 PM PDT 24
Finished Jun 25 04:47:06 PM PDT 24
Peak memory 205936 kb
Host smart-bd472a09-656d-47a5-a986-79394a21f3ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2454559150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.2454559150
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.876244360
Short name T2547
Test name
Test status
Simulation time 138194942 ps
CPU time 1.35 seconds
Started Jun 25 04:46:48 PM PDT 24
Finished Jun 25 04:46:52 PM PDT 24
Peak memory 214584 kb
Host smart-be3970b1-9456-4afe-972f-f6fd43ee6f4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876244360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev
_csr_mem_rw_with_rand_reset.876244360
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.4049876027
Short name T2607
Test name
Test status
Simulation time 59429214 ps
CPU time 1.08 seconds
Started Jun 25 04:46:58 PM PDT 24
Finished Jun 25 04:47:00 PM PDT 24
Peak memory 205932 kb
Host smart-d19a20cc-0315-43f5-84ac-3f05c767a913
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4049876027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.4049876027
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3273396878
Short name T254
Test name
Test status
Simulation time 240120477 ps
CPU time 2.38 seconds
Started Jun 25 04:46:43 PM PDT 24
Finished Jun 25 04:46:49 PM PDT 24
Peak memory 215564 kb
Host smart-c2acab32-1627-4fd4-a438-a39bbb1d40b6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3273396878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.3273396878
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2208125649
Short name T2586
Test name
Test status
Simulation time 527430798 ps
CPU time 4.66 seconds
Started Jun 25 04:46:45 PM PDT 24
Finished Jun 25 04:46:54 PM PDT 24
Peak memory 206144 kb
Host smart-34b20325-203c-4a94-9841-f8a0b41ebd60
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2208125649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.2208125649
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.4236234999
Short name T2556
Test name
Test status
Simulation time 104650563 ps
CPU time 1.19 seconds
Started Jun 25 04:47:02 PM PDT 24
Finished Jun 25 04:47:05 PM PDT 24
Peak memory 206280 kb
Host smart-759c8f7f-04cc-4f76-b771-c114e129c1a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4236234999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.4236234999
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1613913734
Short name T2557
Test name
Test status
Simulation time 155059031 ps
CPU time 1.82 seconds
Started Jun 25 04:46:44 PM PDT 24
Finished Jun 25 04:46:49 PM PDT 24
Peak memory 206308 kb
Host smart-2047c28e-7518-472f-b338-29341c2b03d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1613913734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.1613913734
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.3176712931
Short name T290
Test name
Test status
Simulation time 504055717 ps
CPU time 4.08 seconds
Started Jun 25 04:47:03 PM PDT 24
Finished Jun 25 04:47:09 PM PDT 24
Peak memory 206192 kb
Host smart-b292399b-4a6f-40d8-9a4f-3578adc63e68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3176712931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.3176712931
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.4069215205
Short name T228
Test name
Test status
Simulation time 171160835 ps
CPU time 2.07 seconds
Started Jun 25 04:46:50 PM PDT 24
Finished Jun 25 04:46:55 PM PDT 24
Peak memory 206180 kb
Host smart-15ed60ac-ab2a-4719-91ec-c51a438f5edd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4069215205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.4069215205
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.950680434
Short name T251
Test name
Test status
Simulation time 1651318809 ps
CPU time 11.31 seconds
Started Jun 25 04:46:51 PM PDT 24
Finished Jun 25 04:47:05 PM PDT 24
Peak memory 205796 kb
Host smart-36ce684e-e210-4a08-9279-4a45f8efc796
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=950680434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.950680434
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1201411424
Short name T2578
Test name
Test status
Simulation time 138466065 ps
CPU time 0.99 seconds
Started Jun 25 04:47:08 PM PDT 24
Finished Jun 25 04:47:10 PM PDT 24
Peak memory 206024 kb
Host smart-b9712b42-3cf5-469f-8e2e-28b7248356c1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1201411424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.1201411424
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.830676595
Short name T2522
Test name
Test status
Simulation time 102348356 ps
CPU time 2.37 seconds
Started Jun 25 04:46:59 PM PDT 24
Finished Jun 25 04:47:02 PM PDT 24
Peak memory 214172 kb
Host smart-fd3ad17c-f20b-4d71-b286-761b57f8a1c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830676595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev
_csr_mem_rw_with_rand_reset.830676595
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.445237461
Short name T2562
Test name
Test status
Simulation time 60572183 ps
CPU time 0.87 seconds
Started Jun 25 04:46:59 PM PDT 24
Finished Jun 25 04:47:01 PM PDT 24
Peak memory 205888 kb
Host smart-32c1a988-c539-4228-b332-0d12dabdae68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=445237461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.445237461
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1583702191
Short name T2558
Test name
Test status
Simulation time 155153630 ps
CPU time 2.33 seconds
Started Jun 25 04:46:59 PM PDT 24
Finished Jun 25 04:47:03 PM PDT 24
Peak memory 205904 kb
Host smart-02493493-471c-4112-88f3-db869cafd058
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1583702191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.1583702191
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3973903216
Short name T2518
Test name
Test status
Simulation time 228427339 ps
CPU time 1.85 seconds
Started Jun 25 04:47:03 PM PDT 24
Finished Jun 25 04:47:06 PM PDT 24
Peak memory 206260 kb
Host smart-7a19ad19-fbd3-4eb7-95ee-635e7811836d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3973903216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.3973903216
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3474621531
Short name T2575
Test name
Test status
Simulation time 259751298 ps
CPU time 2.51 seconds
Started Jun 25 04:47:02 PM PDT 24
Finished Jun 25 04:47:07 PM PDT 24
Peak memory 206248 kb
Host smart-662b54b5-dd2f-4051-ac87-6c0210ac4a1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3474621531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.3474621531
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2412407247
Short name T2535
Test name
Test status
Simulation time 104636397 ps
CPU time 1.2 seconds
Started Jun 25 04:47:13 PM PDT 24
Finished Jun 25 04:47:15 PM PDT 24
Peak memory 214352 kb
Host smart-89a67a1a-3082-49ce-9dac-da6b84736e53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412407247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.2412407247
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3791272217
Short name T2549
Test name
Test status
Simulation time 48907598 ps
CPU time 0.84 seconds
Started Jun 25 04:47:15 PM PDT 24
Finished Jun 25 04:47:19 PM PDT 24
Peak memory 206072 kb
Host smart-9e3eabd7-aa24-4421-83e6-b9256d86757a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3791272217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.3791272217
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3700153377
Short name T280
Test name
Test status
Simulation time 34235804 ps
CPU time 0.73 seconds
Started Jun 25 04:47:19 PM PDT 24
Finished Jun 25 04:47:22 PM PDT 24
Peak memory 205908 kb
Host smart-d7b64bba-abc3-4010-bd29-05a61a2ae7c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3700153377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.3700153377
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2163703991
Short name T2608
Test name
Test status
Simulation time 109623365 ps
CPU time 1.18 seconds
Started Jun 25 04:47:15 PM PDT 24
Finished Jun 25 04:47:20 PM PDT 24
Peak memory 206292 kb
Host smart-a3dc397c-ef57-4830-b93b-a236371baa22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2163703991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.2163703991
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.929272607
Short name T2534
Test name
Test status
Simulation time 197548022 ps
CPU time 2.33 seconds
Started Jun 25 04:47:16 PM PDT 24
Finished Jun 25 04:47:22 PM PDT 24
Peak memory 206228 kb
Host smart-ef4abf79-7bab-43f1-972a-68a56faa6f5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=929272607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.929272607
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2251348733
Short name T2570
Test name
Test status
Simulation time 210231243 ps
CPU time 1.91 seconds
Started Jun 25 04:47:16 PM PDT 24
Finished Jun 25 04:47:21 PM PDT 24
Peak memory 218316 kb
Host smart-130fad4e-5286-49df-aa24-17d090395513
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251348733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.2251348733
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3324614943
Short name T256
Test name
Test status
Simulation time 79498557 ps
CPU time 1.06 seconds
Started Jun 25 04:47:16 PM PDT 24
Finished Jun 25 04:47:20 PM PDT 24
Peak memory 206196 kb
Host smart-1ec16aea-19db-4b40-84eb-4df3594c8712
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3324614943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3324614943
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2250374168
Short name T273
Test name
Test status
Simulation time 56085381 ps
CPU time 0.78 seconds
Started Jun 25 04:47:19 PM PDT 24
Finished Jun 25 04:47:23 PM PDT 24
Peak memory 205900 kb
Host smart-e020d19f-69ff-4c3a-8fd0-6fdcefa65371
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2250374168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.2250374168
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1777694049
Short name T2611
Test name
Test status
Simulation time 169277390 ps
CPU time 1.38 seconds
Started Jun 25 04:47:21 PM PDT 24
Finished Jun 25 04:47:25 PM PDT 24
Peak memory 206260 kb
Host smart-58af538b-6142-45f3-acfa-edd653d4e810
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1777694049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.1777694049
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.936743060
Short name T227
Test name
Test status
Simulation time 118940939 ps
CPU time 1.42 seconds
Started Jun 25 04:47:13 PM PDT 24
Finished Jun 25 04:47:16 PM PDT 24
Peak memory 206164 kb
Host smart-baecc8b5-598a-4f02-bd56-1c6242722c8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=936743060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.936743060
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2753067701
Short name T2594
Test name
Test status
Simulation time 1243037795 ps
CPU time 4.06 seconds
Started Jun 25 04:47:15 PM PDT 24
Finished Jun 25 04:47:22 PM PDT 24
Peak memory 206228 kb
Host smart-648751de-d598-4abb-bc98-94de5c8a2f01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2753067701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.2753067701
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3157231946
Short name T2520
Test name
Test status
Simulation time 98001652 ps
CPU time 2.34 seconds
Started Jun 25 04:47:14 PM PDT 24
Finished Jun 25 04:47:20 PM PDT 24
Peak memory 214336 kb
Host smart-510969aa-30c8-48b5-928d-5c454c607484
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157231946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.3157231946
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2682477612
Short name T2593
Test name
Test status
Simulation time 96161634 ps
CPU time 0.9 seconds
Started Jun 25 04:47:15 PM PDT 24
Finished Jun 25 04:47:20 PM PDT 24
Peak memory 205964 kb
Host smart-a6d8bd17-006d-4c45-b512-15b7af87c92d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2682477612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.2682477612
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.3071105601
Short name T2563
Test name
Test status
Simulation time 39522849 ps
CPU time 0.7 seconds
Started Jun 25 04:47:16 PM PDT 24
Finished Jun 25 04:47:20 PM PDT 24
Peak memory 205904 kb
Host smart-664be964-1318-40b1-9f18-114446a37cd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3071105601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.3071105601
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3383240923
Short name T2576
Test name
Test status
Simulation time 120188986 ps
CPU time 1.13 seconds
Started Jun 25 04:47:14 PM PDT 24
Finished Jun 25 04:47:19 PM PDT 24
Peak memory 206252 kb
Host smart-3e35954b-62ff-463d-8bda-c72ace487523
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3383240923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3383240923
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3588418101
Short name T2546
Test name
Test status
Simulation time 146804079 ps
CPU time 1.88 seconds
Started Jun 25 04:47:14 PM PDT 24
Finished Jun 25 04:47:20 PM PDT 24
Peak memory 206212 kb
Host smart-18434590-6250-40a8-b92a-99308c42b53d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3588418101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.3588418101
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.306370021
Short name T2589
Test name
Test status
Simulation time 148469972 ps
CPU time 2.05 seconds
Started Jun 25 04:47:14 PM PDT 24
Finished Jun 25 04:47:20 PM PDT 24
Peak memory 218632 kb
Host smart-0a1559f7-8f37-4c6b-8699-e180995b46c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306370021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbde
v_csr_mem_rw_with_rand_reset.306370021
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1512511792
Short name T258
Test name
Test status
Simulation time 67268856 ps
CPU time 0.96 seconds
Started Jun 25 04:47:17 PM PDT 24
Finished Jun 25 04:47:22 PM PDT 24
Peak memory 206112 kb
Host smart-99847119-5c8a-4e5e-a857-fa9f0fd9aaf6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1512511792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.1512511792
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.860088747
Short name T203
Test name
Test status
Simulation time 35382927 ps
CPU time 0.68 seconds
Started Jun 25 04:47:17 PM PDT 24
Finished Jun 25 04:47:21 PM PDT 24
Peak memory 205944 kb
Host smart-9a9a06ff-48b2-42b4-912d-ec4ca7c430ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=860088747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.860088747
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2221216436
Short name T260
Test name
Test status
Simulation time 73200646 ps
CPU time 1.21 seconds
Started Jun 25 04:47:14 PM PDT 24
Finished Jun 25 04:47:16 PM PDT 24
Peak memory 206256 kb
Host smart-96c15e00-3436-465b-b3a7-6833c642935c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2221216436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.2221216436
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.1595836442
Short name T2583
Test name
Test status
Simulation time 146153390 ps
CPU time 1.89 seconds
Started Jun 25 04:47:16 PM PDT 24
Finished Jun 25 04:47:21 PM PDT 24
Peak memory 221872 kb
Host smart-07bd4592-0ea4-4dee-889f-199ecaba7f70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1595836442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.1595836442
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1974761657
Short name T293
Test name
Test status
Simulation time 1604222302 ps
CPU time 6.23 seconds
Started Jun 25 04:47:14 PM PDT 24
Finished Jun 25 04:47:24 PM PDT 24
Peak memory 206324 kb
Host smart-229fd9ca-022c-4ca4-822e-659ee03ff56e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1974761657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.1974761657
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.367002520
Short name T198
Test name
Test status
Simulation time 194231896 ps
CPU time 2.02 seconds
Started Jun 25 04:47:14 PM PDT 24
Finished Jun 25 04:47:20 PM PDT 24
Peak memory 214540 kb
Host smart-365407f6-bcad-4e21-b545-32545ac06792
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367002520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbde
v_csr_mem_rw_with_rand_reset.367002520
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3918951642
Short name T2536
Test name
Test status
Simulation time 80223946 ps
CPU time 1.04 seconds
Started Jun 25 04:47:13 PM PDT 24
Finished Jun 25 04:47:16 PM PDT 24
Peak memory 206228 kb
Host smart-fd962b92-79ca-46dd-8e08-2d08af8f3ee5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3918951642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.3918951642
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2954959567
Short name T2602
Test name
Test status
Simulation time 89854907 ps
CPU time 1.21 seconds
Started Jun 25 04:47:18 PM PDT 24
Finished Jun 25 04:47:22 PM PDT 24
Peak memory 206328 kb
Host smart-231b9dfa-45af-4305-a00c-0835e7c2bf2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2954959567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.2954959567
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2637773904
Short name T229
Test name
Test status
Simulation time 107367159 ps
CPU time 2.06 seconds
Started Jun 25 04:47:18 PM PDT 24
Finished Jun 25 04:47:23 PM PDT 24
Peak memory 214528 kb
Host smart-b7e805ac-f1c5-4250-a011-f914dce8b241
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637773904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.2637773904
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2389617783
Short name T2579
Test name
Test status
Simulation time 68471825 ps
CPU time 0.97 seconds
Started Jun 25 04:47:14 PM PDT 24
Finished Jun 25 04:47:18 PM PDT 24
Peak memory 206236 kb
Host smart-ddf1ce49-fd37-40a9-8c3b-a71a0669fe57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2389617783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.2389617783
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1152614942
Short name T2572
Test name
Test status
Simulation time 43174436 ps
CPU time 0.71 seconds
Started Jun 25 04:47:18 PM PDT 24
Finished Jun 25 04:47:21 PM PDT 24
Peak memory 205904 kb
Host smart-b9ab7dbf-96a2-4de7-91d3-68132307818a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1152614942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.1152614942
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.463820602
Short name T264
Test name
Test status
Simulation time 297250349 ps
CPU time 2.05 seconds
Started Jun 25 04:47:15 PM PDT 24
Finished Jun 25 04:47:20 PM PDT 24
Peak memory 206224 kb
Host smart-3b13fcfb-0e46-4854-92e6-705384e5d958
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=463820602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.463820602
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2258016245
Short name T263
Test name
Test status
Simulation time 284889437 ps
CPU time 3.21 seconds
Started Jun 25 04:47:16 PM PDT 24
Finished Jun 25 04:47:23 PM PDT 24
Peak memory 222092 kb
Host smart-b2a00efa-2371-4401-af17-1843b018a781
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2258016245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.2258016245
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3628966035
Short name T2530
Test name
Test status
Simulation time 135473312 ps
CPU time 1.39 seconds
Started Jun 25 04:47:26 PM PDT 24
Finished Jun 25 04:47:30 PM PDT 24
Peak memory 214424 kb
Host smart-311113f0-bbdd-467e-ad52-f563bf6371c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628966035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.3628966035
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2193155041
Short name T2529
Test name
Test status
Simulation time 76589790 ps
CPU time 0.94 seconds
Started Jun 25 04:47:27 PM PDT 24
Finished Jun 25 04:47:30 PM PDT 24
Peak memory 205964 kb
Host smart-cfa7e4e4-dd89-42b8-b273-3b1d03c8753d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2193155041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2193155041
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.4183283636
Short name T2542
Test name
Test status
Simulation time 32395218 ps
CPU time 0.72 seconds
Started Jun 25 04:47:26 PM PDT 24
Finished Jun 25 04:47:28 PM PDT 24
Peak memory 205916 kb
Host smart-7e12ee23-c4c6-49a2-96b9-c7db71c85fb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4183283636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.4183283636
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2255581880
Short name T2548
Test name
Test status
Simulation time 70635818 ps
CPU time 1.07 seconds
Started Jun 25 04:47:23 PM PDT 24
Finished Jun 25 04:47:26 PM PDT 24
Peak memory 206320 kb
Host smart-855c88fa-007f-4d0c-8319-1030227dad31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2255581880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.2255581880
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.400708397
Short name T231
Test name
Test status
Simulation time 96973193 ps
CPU time 2.15 seconds
Started Jun 25 04:47:17 PM PDT 24
Finished Jun 25 04:47:22 PM PDT 24
Peak memory 214492 kb
Host smart-ed75e4b0-c55c-4228-a42f-4e332a6850ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=400708397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.400708397
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.638790326
Short name T2523
Test name
Test status
Simulation time 432579314 ps
CPU time 2.78 seconds
Started Jun 25 04:47:29 PM PDT 24
Finished Jun 25 04:47:34 PM PDT 24
Peak memory 206352 kb
Host smart-ffba3d48-04f2-48f9-ba83-c11dc0295c7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=638790326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.638790326
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3216736432
Short name T2525
Test name
Test status
Simulation time 94812381 ps
CPU time 1.73 seconds
Started Jun 25 04:47:26 PM PDT 24
Finished Jun 25 04:47:29 PM PDT 24
Peak memory 214524 kb
Host smart-86edd6d1-2814-4347-813f-af8d0eb47ab3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216736432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.3216736432
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3255138880
Short name T2565
Test name
Test status
Simulation time 77865204 ps
CPU time 0.98 seconds
Started Jun 25 04:47:26 PM PDT 24
Finished Jun 25 04:47:29 PM PDT 24
Peak memory 206188 kb
Host smart-f16c2a6b-9403-447f-9c93-b68d5a595e48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3255138880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.3255138880
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.2665710951
Short name T2616
Test name
Test status
Simulation time 72483969 ps
CPU time 0.74 seconds
Started Jun 25 04:47:23 PM PDT 24
Finished Jun 25 04:47:26 PM PDT 24
Peak memory 205932 kb
Host smart-906fe0d6-2f11-4a12-99bb-beb61a30b99b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2665710951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.2665710951
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2388998350
Short name T2598
Test name
Test status
Simulation time 107723802 ps
CPU time 1.51 seconds
Started Jun 25 04:47:22 PM PDT 24
Finished Jun 25 04:47:26 PM PDT 24
Peak memory 206360 kb
Host smart-80a9dfee-fb5f-44b6-81c5-e49fa9c9dcb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2388998350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.2388998350
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.995186619
Short name T2559
Test name
Test status
Simulation time 126352722 ps
CPU time 3.1 seconds
Started Jun 25 04:47:25 PM PDT 24
Finished Jun 25 04:47:29 PM PDT 24
Peak memory 222088 kb
Host smart-1f2c9ab2-061f-4884-86ff-7010d798d629
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=995186619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.995186619
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3717574950
Short name T223
Test name
Test status
Simulation time 769301221 ps
CPU time 2.98 seconds
Started Jun 25 04:47:24 PM PDT 24
Finished Jun 25 04:47:29 PM PDT 24
Peak memory 206316 kb
Host smart-0fed9757-da08-4a8b-8a12-0f5218de4e64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3717574950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.3717574950
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.4138155735
Short name T196
Test name
Test status
Simulation time 131976967 ps
CPU time 2.06 seconds
Started Jun 25 04:47:30 PM PDT 24
Finished Jun 25 04:47:34 PM PDT 24
Peak memory 214508 kb
Host smart-ed5d063b-d521-4376-8c4d-4dac707e2f17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138155735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.4138155735
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.687661793
Short name T2560
Test name
Test status
Simulation time 54576644 ps
CPU time 1.02 seconds
Started Jun 25 04:47:26 PM PDT 24
Finished Jun 25 04:47:28 PM PDT 24
Peak memory 206208 kb
Host smart-3669d509-1b61-48b9-bf12-6745034dbba2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=687661793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.687661793
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.1253945555
Short name T272
Test name
Test status
Simulation time 50229950 ps
CPU time 0.71 seconds
Started Jun 25 04:47:25 PM PDT 24
Finished Jun 25 04:47:27 PM PDT 24
Peak memory 205904 kb
Host smart-9e3bafb3-1d98-41b5-b2d9-8edbee44d344
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1253945555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.1253945555
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.590478824
Short name T2543
Test name
Test status
Simulation time 168478468 ps
CPU time 1.72 seconds
Started Jun 25 04:47:24 PM PDT 24
Finished Jun 25 04:47:27 PM PDT 24
Peak memory 206256 kb
Host smart-1bd53ba8-2e91-4896-a603-e185841cc98a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=590478824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.590478824
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1023336029
Short name T226
Test name
Test status
Simulation time 75725651 ps
CPU time 2.02 seconds
Started Jun 25 04:47:29 PM PDT 24
Finished Jun 25 04:47:33 PM PDT 24
Peak memory 222136 kb
Host smart-dcd7417c-9af6-419b-984d-eb3fa9c7fe0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1023336029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.1023336029
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2260424864
Short name T2612
Test name
Test status
Simulation time 695338571 ps
CPU time 4.94 seconds
Started Jun 25 04:47:24 PM PDT 24
Finished Jun 25 04:47:30 PM PDT 24
Peak memory 206084 kb
Host smart-7cd37a2f-229c-4f38-b20f-f9834e0ea15e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2260424864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.2260424864
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3881781009
Short name T232
Test name
Test status
Simulation time 66412721 ps
CPU time 1.17 seconds
Started Jun 25 04:47:24 PM PDT 24
Finished Jun 25 04:47:26 PM PDT 24
Peak memory 216392 kb
Host smart-43260481-9747-4d0e-8889-d631570d63e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881781009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.3881781009
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.4204279406
Short name T241
Test name
Test status
Simulation time 46442302 ps
CPU time 0.91 seconds
Started Jun 25 04:47:28 PM PDT 24
Finished Jun 25 04:47:32 PM PDT 24
Peak memory 206276 kb
Host smart-2e8241d3-2402-4105-aa89-b24e3f0700a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4204279406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.4204279406
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2109130046
Short name T267
Test name
Test status
Simulation time 61043677 ps
CPU time 0.72 seconds
Started Jun 25 04:47:24 PM PDT 24
Finished Jun 25 04:47:26 PM PDT 24
Peak memory 205944 kb
Host smart-eafa9555-0d90-4cbe-a235-2fe91a608026
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2109130046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.2109130046
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.4039610985
Short name T2568
Test name
Test status
Simulation time 93787449 ps
CPU time 1.13 seconds
Started Jun 25 04:47:27 PM PDT 24
Finished Jun 25 04:47:30 PM PDT 24
Peak memory 206316 kb
Host smart-c7929bc4-af23-4606-bd69-e987d9bfcf4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4039610985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.4039610985
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1808373484
Short name T2567
Test name
Test status
Simulation time 151651266 ps
CPU time 1.73 seconds
Started Jun 25 04:47:24 PM PDT 24
Finished Jun 25 04:47:27 PM PDT 24
Peak memory 206220 kb
Host smart-e01e9ac8-ba28-46e0-b043-bfdd3f700391
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1808373484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.1808373484
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1270378158
Short name T288
Test name
Test status
Simulation time 960420698 ps
CPU time 5.19 seconds
Started Jun 25 04:47:26 PM PDT 24
Finished Jun 25 04:47:34 PM PDT 24
Peak memory 206288 kb
Host smart-943dbbc2-fa8c-4ed7-b867-e16dabd4b620
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1270378158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.1270378158
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3843256869
Short name T255
Test name
Test status
Simulation time 374263791 ps
CPU time 3.7 seconds
Started Jun 25 04:46:49 PM PDT 24
Finished Jun 25 04:46:56 PM PDT 24
Peak memory 206224 kb
Host smart-736fa81c-f5f2-4edb-afee-0d062fbda424
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3843256869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.3843256869
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2293667993
Short name T2596
Test name
Test status
Simulation time 1268495149 ps
CPU time 7.94 seconds
Started Jun 25 04:46:49 PM PDT 24
Finished Jun 25 04:47:00 PM PDT 24
Peak memory 206200 kb
Host smart-1d3bb5bb-d232-47c8-851f-e7dcb3a28df3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2293667993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.2293667993
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1200121506
Short name T247
Test name
Test status
Simulation time 99040627 ps
CPU time 1.03 seconds
Started Jun 25 04:46:49 PM PDT 24
Finished Jun 25 04:46:53 PM PDT 24
Peak memory 206028 kb
Host smart-356eff60-6579-4602-8a16-d898aad1bfab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1200121506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.1200121506
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3115346253
Short name T2604
Test name
Test status
Simulation time 118471374 ps
CPU time 1.45 seconds
Started Jun 25 04:46:48 PM PDT 24
Finished Jun 25 04:46:53 PM PDT 24
Peak memory 214448 kb
Host smart-60b4f6fa-641b-4728-849c-1f62c91b5656
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115346253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.3115346253
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3423230423
Short name T2580
Test name
Test status
Simulation time 59509450 ps
CPU time 0.83 seconds
Started Jun 25 04:46:49 PM PDT 24
Finished Jun 25 04:46:53 PM PDT 24
Peak memory 205932 kb
Host smart-56467fe7-dc54-4ea2-9590-572e6d95c3c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3423230423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.3423230423
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.1667920947
Short name T2554
Test name
Test status
Simulation time 40983414 ps
CPU time 0.73 seconds
Started Jun 25 04:46:58 PM PDT 24
Finished Jun 25 04:47:00 PM PDT 24
Peak memory 205856 kb
Host smart-0f9d920f-a929-4abe-a039-2a8d66ef04cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1667920947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.1667920947
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3384968793
Short name T253
Test name
Test status
Simulation time 173124265 ps
CPU time 2.43 seconds
Started Jun 25 04:46:55 PM PDT 24
Finished Jun 25 04:46:58 PM PDT 24
Peak memory 215460 kb
Host smart-de766b48-f76f-448d-b84f-bdd857045ba9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3384968793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.3384968793
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2174813152
Short name T2516
Test name
Test status
Simulation time 176601179 ps
CPU time 4.09 seconds
Started Jun 25 04:46:49 PM PDT 24
Finished Jun 25 04:46:56 PM PDT 24
Peak memory 206096 kb
Host smart-19c1956b-0213-4eb6-9226-c33f5a7783ee
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2174813152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.2174813152
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3705101351
Short name T259
Test name
Test status
Simulation time 100033549 ps
CPU time 1.05 seconds
Started Jun 25 04:46:59 PM PDT 24
Finished Jun 25 04:47:01 PM PDT 24
Peak memory 205936 kb
Host smart-5f6b2109-c2e6-4f82-b65e-7aae5bad4843
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3705101351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.3705101351
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.689691127
Short name T2606
Test name
Test status
Simulation time 112106729 ps
CPU time 2.06 seconds
Started Jun 25 04:46:48 PM PDT 24
Finished Jun 25 04:46:53 PM PDT 24
Peak memory 214324 kb
Host smart-c9f8d869-fd45-4e7d-87ab-c64d8a52443c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=689691127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.689691127
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.297951575
Short name T2573
Test name
Test status
Simulation time 54425750 ps
CPU time 0.67 seconds
Started Jun 25 04:47:29 PM PDT 24
Finished Jun 25 04:47:32 PM PDT 24
Peak memory 205952 kb
Host smart-39eab9cf-e5b0-45c5-a07c-6a8e459c431d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=297951575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.297951575
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1572344753
Short name T2601
Test name
Test status
Simulation time 48560568 ps
CPU time 0.71 seconds
Started Jun 25 04:47:24 PM PDT 24
Finished Jun 25 04:47:26 PM PDT 24
Peak memory 205944 kb
Host smart-2bfd94d6-b5de-4bbc-bc7f-fe0551192010
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1572344753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.1572344753
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2044999738
Short name T284
Test name
Test status
Simulation time 86737405 ps
CPU time 0.73 seconds
Started Jun 25 04:47:26 PM PDT 24
Finished Jun 25 04:47:29 PM PDT 24
Peak memory 205908 kb
Host smart-ec15d6f0-1b58-4a75-a036-e353f918ab9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2044999738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.2044999738
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.370899704
Short name T269
Test name
Test status
Simulation time 78967774 ps
CPU time 0.78 seconds
Started Jun 25 04:47:26 PM PDT 24
Finished Jun 25 04:47:28 PM PDT 24
Peak memory 205860 kb
Host smart-ff687664-bdae-4451-8af9-710fd656916c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=370899704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.370899704
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.4234709065
Short name T278
Test name
Test status
Simulation time 33356706 ps
CPU time 0.71 seconds
Started Jun 25 04:47:27 PM PDT 24
Finished Jun 25 04:47:30 PM PDT 24
Peak memory 205956 kb
Host smart-52c08427-d6f5-4725-9f4c-16979794fd27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4234709065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.4234709065
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1581348379
Short name T2617
Test name
Test status
Simulation time 33017916 ps
CPU time 0.68 seconds
Started Jun 25 04:47:25 PM PDT 24
Finished Jun 25 04:47:27 PM PDT 24
Peak memory 205904 kb
Host smart-b86fe613-ac93-4b37-bb55-e72b631b1cdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1581348379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.1581348379
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.504958808
Short name T277
Test name
Test status
Simulation time 50106042 ps
CPU time 0.72 seconds
Started Jun 25 04:47:27 PM PDT 24
Finished Jun 25 04:47:30 PM PDT 24
Peak memory 205968 kb
Host smart-8f12b29d-4edb-4ae3-bb30-25d5e8f8aaa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=504958808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.504958808
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1896922473
Short name T282
Test name
Test status
Simulation time 31773775 ps
CPU time 0.66 seconds
Started Jun 25 04:47:26 PM PDT 24
Finished Jun 25 04:47:28 PM PDT 24
Peak memory 205936 kb
Host smart-998c2b5b-c71a-41d3-8917-faecc53155b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1896922473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.1896922473
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2810191982
Short name T2555
Test name
Test status
Simulation time 68964696 ps
CPU time 0.73 seconds
Started Jun 25 04:47:24 PM PDT 24
Finished Jun 25 04:47:27 PM PDT 24
Peak memory 205872 kb
Host smart-1d14da05-8002-42a5-922e-0ac45ab83794
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2810191982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.2810191982
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2251753589
Short name T2588
Test name
Test status
Simulation time 55968539 ps
CPU time 0.71 seconds
Started Jun 25 04:47:27 PM PDT 24
Finished Jun 25 04:47:29 PM PDT 24
Peak memory 205948 kb
Host smart-1c93e904-1cc2-4573-b1ba-c1c9ce084ec6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2251753589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.2251753589
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2788676901
Short name T240
Test name
Test status
Simulation time 129566717 ps
CPU time 3.24 seconds
Started Jun 25 04:46:59 PM PDT 24
Finished Jun 25 04:47:03 PM PDT 24
Peak memory 205788 kb
Host smart-a4059448-bf85-4705-b989-9594e57c5658
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2788676901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.2788676901
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2563799046
Short name T242
Test name
Test status
Simulation time 431836530 ps
CPU time 7.35 seconds
Started Jun 25 04:46:47 PM PDT 24
Finished Jun 25 04:46:58 PM PDT 24
Peak memory 206044 kb
Host smart-fd3698dd-3e8b-4f37-860f-fa60b0cd2ba0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2563799046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.2563799046
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2148240849
Short name T2519
Test name
Test status
Simulation time 59570543 ps
CPU time 0.86 seconds
Started Jun 25 04:46:49 PM PDT 24
Finished Jun 25 04:46:53 PM PDT 24
Peak memory 205808 kb
Host smart-6f1fe637-200c-4f85-9cf9-7af81b67afcc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2148240849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.2148240849
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2418147402
Short name T2527
Test name
Test status
Simulation time 224061519 ps
CPU time 1.86 seconds
Started Jun 25 04:46:57 PM PDT 24
Finished Jun 25 04:46:59 PM PDT 24
Peak memory 214420 kb
Host smart-095a5b2d-a0b5-47d2-a6c3-cda98613a4da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418147402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.2418147402
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2929366007
Short name T261
Test name
Test status
Simulation time 82403119 ps
CPU time 1.11 seconds
Started Jun 25 04:47:01 PM PDT 24
Finished Jun 25 04:47:03 PM PDT 24
Peak memory 206224 kb
Host smart-d92ad5bd-a8de-423c-8f4a-ad6b9c2a393b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2929366007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2929366007
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3453938725
Short name T250
Test name
Test status
Simulation time 130894705 ps
CPU time 2.39 seconds
Started Jun 25 04:46:49 PM PDT 24
Finished Jun 25 04:46:54 PM PDT 24
Peak memory 214488 kb
Host smart-fcc58257-1e26-41be-9997-d4cd019582f1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3453938725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.3453938725
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2564672301
Short name T2603
Test name
Test status
Simulation time 525383896 ps
CPU time 4.69 seconds
Started Jun 25 04:46:48 PM PDT 24
Finished Jun 25 04:46:56 PM PDT 24
Peak memory 206180 kb
Host smart-781b4f98-f495-4598-b009-288d2f121591
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2564672301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.2564672301
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1091898790
Short name T2545
Test name
Test status
Simulation time 105743437 ps
CPU time 1 seconds
Started Jun 25 04:46:59 PM PDT 24
Finished Jun 25 04:47:01 PM PDT 24
Peak memory 206124 kb
Host smart-2fa3dbe8-2250-41be-9076-150689cce647
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1091898790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.1091898790
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.4025696062
Short name T225
Test name
Test status
Simulation time 216619498 ps
CPU time 2.55 seconds
Started Jun 25 04:47:01 PM PDT 24
Finished Jun 25 04:47:05 PM PDT 24
Peak memory 214480 kb
Host smart-fe5e537e-a648-44c2-bef2-4470d9fa44af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4025696062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.4025696062
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.74588793
Short name T262
Test name
Test status
Simulation time 824660534 ps
CPU time 4.59 seconds
Started Jun 25 04:47:02 PM PDT 24
Finished Jun 25 04:47:09 PM PDT 24
Peak memory 206296 kb
Host smart-b287773b-8432-411e-bd7c-fa1dd985c890
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=74588793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.74588793
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3008913119
Short name T281
Test name
Test status
Simulation time 38027598 ps
CPU time 0.72 seconds
Started Jun 25 04:47:30 PM PDT 24
Finished Jun 25 04:47:33 PM PDT 24
Peak memory 205944 kb
Host smart-63dc31ab-b26f-462a-a54a-350fc516f16b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3008913119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.3008913119
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2955647687
Short name T271
Test name
Test status
Simulation time 57581982 ps
CPU time 0.69 seconds
Started Jun 25 04:47:27 PM PDT 24
Finished Jun 25 04:47:30 PM PDT 24
Peak memory 205888 kb
Host smart-6b9130b5-584a-46af-8bae-38113331fe6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2955647687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.2955647687
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.4252043448
Short name T2615
Test name
Test status
Simulation time 41076362 ps
CPU time 0.71 seconds
Started Jun 25 04:47:27 PM PDT 24
Finished Jun 25 04:47:31 PM PDT 24
Peak memory 205948 kb
Host smart-f42d7191-4f6e-4917-87a3-dcc009340ae4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4252043448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.4252043448
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.4219030439
Short name T2544
Test name
Test status
Simulation time 35377913 ps
CPU time 0.73 seconds
Started Jun 25 04:47:30 PM PDT 24
Finished Jun 25 04:47:33 PM PDT 24
Peak memory 205904 kb
Host smart-32207926-1615-45c4-867a-a0aa6975310f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4219030439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.4219030439
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3011955955
Short name T2528
Test name
Test status
Simulation time 43524789 ps
CPU time 0.72 seconds
Started Jun 25 04:47:30 PM PDT 24
Finished Jun 25 04:47:33 PM PDT 24
Peak memory 205900 kb
Host smart-b3fae87b-060f-4e2e-a9a2-3af30b0cbba4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3011955955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.3011955955
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.1938005761
Short name T276
Test name
Test status
Simulation time 104607540 ps
CPU time 0.73 seconds
Started Jun 25 04:47:28 PM PDT 24
Finished Jun 25 04:47:31 PM PDT 24
Peak memory 205904 kb
Host smart-ff836b23-fa80-4691-a7a2-809532bc32e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1938005761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.1938005761
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.2953144481
Short name T2526
Test name
Test status
Simulation time 42139623 ps
CPU time 0.68 seconds
Started Jun 25 04:47:27 PM PDT 24
Finished Jun 25 04:47:30 PM PDT 24
Peak memory 205944 kb
Host smart-c6d44081-06e9-4bb6-acd9-ec66ef8166bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2953144481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.2953144481
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3053164662
Short name T2591
Test name
Test status
Simulation time 42054745 ps
CPU time 0.69 seconds
Started Jun 25 04:47:29 PM PDT 24
Finished Jun 25 04:47:32 PM PDT 24
Peak memory 205776 kb
Host smart-3415ff88-5c5f-4501-9f65-7374c7bb4c07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3053164662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.3053164662
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2622148962
Short name T283
Test name
Test status
Simulation time 59114311 ps
CPU time 0.69 seconds
Started Jun 25 04:47:29 PM PDT 24
Finished Jun 25 04:47:32 PM PDT 24
Peak memory 205704 kb
Host smart-e84c3c3b-0e9c-4bad-86a5-4213c1b6d187
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2622148962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.2622148962
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.952163810
Short name T244
Test name
Test status
Simulation time 306720543 ps
CPU time 3.51 seconds
Started Jun 25 04:47:04 PM PDT 24
Finished Jun 25 04:47:09 PM PDT 24
Peak memory 206192 kb
Host smart-650ea7c3-bbab-4539-aaeb-633b29033473
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=952163810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.952163810
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.468675709
Short name T2537
Test name
Test status
Simulation time 342114122 ps
CPU time 4 seconds
Started Jun 25 04:46:58 PM PDT 24
Finished Jun 25 04:47:03 PM PDT 24
Peak memory 206244 kb
Host smart-06e05f50-3e11-496f-b36c-8781175d196a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=468675709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.468675709
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2588552516
Short name T2599
Test name
Test status
Simulation time 77982696 ps
CPU time 0.89 seconds
Started Jun 25 04:46:53 PM PDT 24
Finished Jun 25 04:46:56 PM PDT 24
Peak memory 205952 kb
Host smart-7e232f4d-088b-4e4e-8715-eb5da7e72976
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2588552516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.2588552516
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.651016110
Short name T2600
Test name
Test status
Simulation time 94475583 ps
CPU time 1.28 seconds
Started Jun 25 04:46:57 PM PDT 24
Finished Jun 25 04:47:00 PM PDT 24
Peak memory 214492 kb
Host smart-b14d3ec7-40da-4d9b-aba1-8d1d01b0df22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651016110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev
_csr_mem_rw_with_rand_reset.651016110
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2173249246
Short name T248
Test name
Test status
Simulation time 81275706 ps
CPU time 1.15 seconds
Started Jun 25 04:47:01 PM PDT 24
Finished Jun 25 04:47:04 PM PDT 24
Peak memory 206068 kb
Host smart-49731a16-3609-4d19-b754-387e16ab48a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2173249246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.2173249246
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1974505095
Short name T246
Test name
Test status
Simulation time 65566258 ps
CPU time 1.4 seconds
Started Jun 25 04:46:56 PM PDT 24
Finished Jun 25 04:46:58 PM PDT 24
Peak memory 214344 kb
Host smart-2c5a4326-0e43-4304-9279-a801b2063ffc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1974505095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.1974505095
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3869922223
Short name T2553
Test name
Test status
Simulation time 274550505 ps
CPU time 2.59 seconds
Started Jun 25 04:47:00 PM PDT 24
Finished Jun 25 04:47:03 PM PDT 24
Peak memory 206116 kb
Host smart-701a4cf6-12ef-46f1-8dcf-e34f6ee97f30
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3869922223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.3869922223
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.392877156
Short name T2595
Test name
Test status
Simulation time 91782337 ps
CPU time 1.12 seconds
Started Jun 25 04:46:57 PM PDT 24
Finished Jun 25 04:46:59 PM PDT 24
Peak memory 206348 kb
Host smart-45ff58a8-89b7-4452-a74f-39339e722fe3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=392877156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.392877156
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.620515132
Short name T2540
Test name
Test status
Simulation time 103790351 ps
CPU time 2.61 seconds
Started Jun 25 04:47:01 PM PDT 24
Finished Jun 25 04:47:06 PM PDT 24
Peak memory 222228 kb
Host smart-06e99f33-e976-4d50-94c3-f618f65c30e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=620515132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.620515132
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.501275679
Short name T2581
Test name
Test status
Simulation time 463845557 ps
CPU time 4.1 seconds
Started Jun 25 04:46:55 PM PDT 24
Finished Jun 25 04:47:00 PM PDT 24
Peak memory 206292 kb
Host smart-0696f6f8-0d38-42eb-93d8-3b9edbdbe2ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=501275679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.501275679
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2567544667
Short name T279
Test name
Test status
Simulation time 35656418 ps
CPU time 0.68 seconds
Started Jun 25 04:47:29 PM PDT 24
Finished Jun 25 04:47:32 PM PDT 24
Peak memory 205904 kb
Host smart-080ea3d9-1835-4772-82fe-6a3018ac1282
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2567544667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.2567544667
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.228815093
Short name T2561
Test name
Test status
Simulation time 37088125 ps
CPU time 0.72 seconds
Started Jun 25 04:47:28 PM PDT 24
Finished Jun 25 04:47:32 PM PDT 24
Peak memory 205944 kb
Host smart-1f16b611-89b7-481b-8a0e-5d46f157197d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=228815093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.228815093
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.3466828676
Short name T2531
Test name
Test status
Simulation time 49076131 ps
CPU time 0.67 seconds
Started Jun 25 04:47:28 PM PDT 24
Finished Jun 25 04:47:31 PM PDT 24
Peak memory 205888 kb
Host smart-953683e5-d311-42e9-9a73-300fdfd7d3d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3466828676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.3466828676
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.1603150139
Short name T2582
Test name
Test status
Simulation time 45321372 ps
CPU time 0.71 seconds
Started Jun 25 04:47:28 PM PDT 24
Finished Jun 25 04:47:31 PM PDT 24
Peak memory 205892 kb
Host smart-8f73d228-be74-4a9d-a4c3-279de35ffe5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1603150139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.1603150139
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.4026904161
Short name T2590
Test name
Test status
Simulation time 85928984 ps
CPU time 0.75 seconds
Started Jun 25 04:47:29 PM PDT 24
Finished Jun 25 04:47:32 PM PDT 24
Peak memory 205908 kb
Host smart-ef188b6e-d360-46d8-867a-83d3869b7af4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4026904161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.4026904161
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.1987154097
Short name T285
Test name
Test status
Simulation time 56650136 ps
CPU time 0.7 seconds
Started Jun 25 04:47:31 PM PDT 24
Finished Jun 25 04:47:33 PM PDT 24
Peak memory 205888 kb
Host smart-2a8c82d7-4637-43da-91f5-581749838880
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1987154097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.1987154097
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.785595302
Short name T2550
Test name
Test status
Simulation time 43707036 ps
CPU time 0.71 seconds
Started Jun 25 04:47:29 PM PDT 24
Finished Jun 25 04:47:32 PM PDT 24
Peak memory 205908 kb
Host smart-2eb3b78c-bc3e-415f-b93a-a148f204cc40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=785595302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.785595302
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.2661466251
Short name T2539
Test name
Test status
Simulation time 43479330 ps
CPU time 0.68 seconds
Started Jun 25 04:47:31 PM PDT 24
Finished Jun 25 04:47:33 PM PDT 24
Peak memory 205888 kb
Host smart-b93e3bdb-2724-4b71-bb44-3405fb707521
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2661466251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.2661466251
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.905495438
Short name T2541
Test name
Test status
Simulation time 58380134 ps
CPU time 0.72 seconds
Started Jun 25 04:47:28 PM PDT 24
Finished Jun 25 04:47:31 PM PDT 24
Peak memory 205940 kb
Host smart-6d6bbacd-b783-4401-bdde-108fbe478573
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=905495438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.905495438
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1580638312
Short name T266
Test name
Test status
Simulation time 79522926 ps
CPU time 0.81 seconds
Started Jun 25 04:47:30 PM PDT 24
Finished Jun 25 04:47:33 PM PDT 24
Peak memory 205908 kb
Host smart-5ed694d3-c131-40ff-90a7-e3276abd0f03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1580638312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.1580638312
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.4225646500
Short name T2571
Test name
Test status
Simulation time 189069485 ps
CPU time 2.27 seconds
Started Jun 25 04:47:09 PM PDT 24
Finished Jun 25 04:47:12 PM PDT 24
Peak memory 214388 kb
Host smart-33bd459d-40d9-4481-a050-1ccbe405bbe7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225646500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.4225646500
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.624092777
Short name T2569
Test name
Test status
Simulation time 68354670 ps
CPU time 0.87 seconds
Started Jun 25 04:47:05 PM PDT 24
Finished Jun 25 04:47:07 PM PDT 24
Peak memory 206072 kb
Host smart-e47da532-0ad6-45d5-bae9-c101701f66c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=624092777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.624092777
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2399689381
Short name T204
Test name
Test status
Simulation time 53463156 ps
CPU time 0.7 seconds
Started Jun 25 04:47:06 PM PDT 24
Finished Jun 25 04:47:08 PM PDT 24
Peak memory 205940 kb
Host smart-18e9f84b-0eaf-48fe-87f5-9e70c70ff8d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2399689381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.2399689381
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.688940687
Short name T2517
Test name
Test status
Simulation time 104566309 ps
CPU time 1.48 seconds
Started Jun 25 04:47:06 PM PDT 24
Finished Jun 25 04:47:08 PM PDT 24
Peak memory 206576 kb
Host smart-5a7b6ec5-966b-4369-9a9c-6b6f78017860
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=688940687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.688940687
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3413523017
Short name T2564
Test name
Test status
Simulation time 111566533 ps
CPU time 3.38 seconds
Started Jun 25 04:47:11 PM PDT 24
Finished Jun 25 04:47:16 PM PDT 24
Peak memory 222956 kb
Host smart-1c6249ce-c612-4434-b0af-d3a9f9a6a711
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3413523017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.3413523017
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2161264197
Short name T286
Test name
Test status
Simulation time 827306767 ps
CPU time 5.12 seconds
Started Jun 25 04:47:06 PM PDT 24
Finished Jun 25 04:47:12 PM PDT 24
Peak memory 206336 kb
Host smart-a1188f33-2c9a-4f50-99cb-374e32725282
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2161264197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.2161264197
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3025725742
Short name T2587
Test name
Test status
Simulation time 169002740 ps
CPU time 1.75 seconds
Started Jun 25 04:47:11 PM PDT 24
Finished Jun 25 04:47:14 PM PDT 24
Peak memory 214408 kb
Host smart-aca11de7-e8e4-4fde-8a9d-d58019dcf8f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025725742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.3025725742
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.454733010
Short name T245
Test name
Test status
Simulation time 54121707 ps
CPU time 0.85 seconds
Started Jun 25 04:47:10 PM PDT 24
Finished Jun 25 04:47:12 PM PDT 24
Peak memory 205812 kb
Host smart-cbae98fa-f6f2-49f1-af5c-a6d3c03af4ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=454733010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.454733010
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.739367454
Short name T2552
Test name
Test status
Simulation time 110207490 ps
CPU time 0.77 seconds
Started Jun 25 04:47:03 PM PDT 24
Finished Jun 25 04:47:06 PM PDT 24
Peak memory 205936 kb
Host smart-f390123b-0ab4-4320-9f1d-7660722ea843
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=739367454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.739367454
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1623172174
Short name T2538
Test name
Test status
Simulation time 72273199 ps
CPU time 1.44 seconds
Started Jun 25 04:47:04 PM PDT 24
Finished Jun 25 04:47:07 PM PDT 24
Peak memory 206132 kb
Host smart-65a726e1-9213-452c-9f2b-a20e51cf7b9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1623172174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.1623172174
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1625606261
Short name T195
Test name
Test status
Simulation time 406721385 ps
CPU time 3.84 seconds
Started Jun 25 04:47:10 PM PDT 24
Finished Jun 25 04:47:16 PM PDT 24
Peak memory 214352 kb
Host smart-5b0ecdab-a230-45b5-b4b1-03249812111e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1625606261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1625606261
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3177094787
Short name T287
Test name
Test status
Simulation time 537603313 ps
CPU time 4.11 seconds
Started Jun 25 04:47:13 PM PDT 24
Finished Jun 25 04:47:18 PM PDT 24
Peak memory 206284 kb
Host smart-0dead2d8-3cc8-4488-bfb2-55ee89ea07f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3177094787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.3177094787
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.111151220
Short name T2551
Test name
Test status
Simulation time 154239634 ps
CPU time 1.91 seconds
Started Jun 25 04:47:07 PM PDT 24
Finished Jun 25 04:47:10 PM PDT 24
Peak memory 214484 kb
Host smart-713b6495-47a9-4498-bcf0-f193f7da798e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111151220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev
_csr_mem_rw_with_rand_reset.111151220
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.118477857
Short name T2597
Test name
Test status
Simulation time 60716596 ps
CPU time 0.99 seconds
Started Jun 25 04:47:13 PM PDT 24
Finished Jun 25 04:47:16 PM PDT 24
Peak memory 206272 kb
Host smart-0ac88986-8032-4c0f-95ce-bbfedf2b6d02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=118477857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.118477857
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.714972365
Short name T2592
Test name
Test status
Simulation time 80031998 ps
CPU time 0.69 seconds
Started Jun 25 04:47:07 PM PDT 24
Finished Jun 25 04:47:09 PM PDT 24
Peak memory 205896 kb
Host smart-056a1473-6a2c-4dc5-a32c-fea3bc28be3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=714972365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.714972365
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1143838059
Short name T257
Test name
Test status
Simulation time 104534777 ps
CPU time 1.5 seconds
Started Jun 25 04:47:04 PM PDT 24
Finished Jun 25 04:47:07 PM PDT 24
Peak memory 206204 kb
Host smart-7a61a257-2a9c-434f-8e5a-17936ebcb0b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1143838059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.1143838059
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3154314218
Short name T2584
Test name
Test status
Simulation time 252339598 ps
CPU time 2.12 seconds
Started Jun 25 04:47:05 PM PDT 24
Finished Jun 25 04:47:09 PM PDT 24
Peak memory 221808 kb
Host smart-ac06e3ce-ba73-426d-961b-e3d22870aa49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3154314218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.3154314218
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.563898021
Short name T2585
Test name
Test status
Simulation time 270255430 ps
CPU time 2.57 seconds
Started Jun 25 04:47:12 PM PDT 24
Finished Jun 25 04:47:16 PM PDT 24
Peak memory 206288 kb
Host smart-ba003878-f154-43ce-979e-fb2424f739da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=563898021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.563898021
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3846412123
Short name T2610
Test name
Test status
Simulation time 99972185 ps
CPU time 1.28 seconds
Started Jun 25 04:47:13 PM PDT 24
Finished Jun 25 04:47:15 PM PDT 24
Peak memory 214520 kb
Host smart-1d6e4f78-1c01-4dfc-b094-30907b149b1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846412123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.3846412123
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.45580513
Short name T219
Test name
Test status
Simulation time 57608867 ps
CPU time 0.85 seconds
Started Jun 25 04:47:17 PM PDT 24
Finished Jun 25 04:47:21 PM PDT 24
Peak memory 205900 kb
Host smart-695a8f1a-8d01-4f5f-9b33-3ad94adb43ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=45580513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.45580513
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.835738047
Short name T2609
Test name
Test status
Simulation time 60374808 ps
CPU time 0.73 seconds
Started Jun 25 04:47:16 PM PDT 24
Finished Jun 25 04:47:20 PM PDT 24
Peak memory 205872 kb
Host smart-0c89a4cf-2cef-4db3-a6a5-80f7e8acfbeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=835738047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.835738047
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1484046433
Short name T2613
Test name
Test status
Simulation time 145088940 ps
CPU time 1.49 seconds
Started Jun 25 04:47:17 PM PDT 24
Finished Jun 25 04:47:22 PM PDT 24
Peak memory 206332 kb
Host smart-b9394ed4-1941-4cf9-b955-0f2188a746cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1484046433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.1484046433
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3636909236
Short name T2574
Test name
Test status
Simulation time 188965623 ps
CPU time 2.05 seconds
Started Jun 25 04:47:14 PM PDT 24
Finished Jun 25 04:47:19 PM PDT 24
Peak memory 221792 kb
Host smart-5af1341b-d0d1-4bb9-baf2-48826ad2b9c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3636909236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.3636909236
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.2483521710
Short name T224
Test name
Test status
Simulation time 475048157 ps
CPU time 3.12 seconds
Started Jun 25 04:47:17 PM PDT 24
Finished Jun 25 04:47:23 PM PDT 24
Peak memory 206220 kb
Host smart-d987c38f-38f2-496b-adb9-05841deb7b67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2483521710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.2483521710
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1405143992
Short name T2521
Test name
Test status
Simulation time 108070154 ps
CPU time 2.68 seconds
Started Jun 25 04:47:18 PM PDT 24
Finished Jun 25 04:47:24 PM PDT 24
Peak memory 214444 kb
Host smart-94ec5e25-15c2-48cc-b1e6-2ecee6d213f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405143992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.1405143992
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.907272418
Short name T2614
Test name
Test status
Simulation time 50768317 ps
CPU time 0.94 seconds
Started Jun 25 04:47:14 PM PDT 24
Finished Jun 25 04:47:17 PM PDT 24
Peak memory 206176 kb
Host smart-b0143535-3d26-40fe-869f-4b7ddc7d0157
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=907272418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.907272418
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1976004043
Short name T2605
Test name
Test status
Simulation time 68795857 ps
CPU time 0.71 seconds
Started Jun 25 04:47:17 PM PDT 24
Finished Jun 25 04:47:21 PM PDT 24
Peak memory 205904 kb
Host smart-d9f9cf5d-3cca-4c89-94dd-1599ce7bc2ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1976004043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.1976004043
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.4125991194
Short name T2524
Test name
Test status
Simulation time 54853653 ps
CPU time 1.13 seconds
Started Jun 25 04:47:14 PM PDT 24
Finished Jun 25 04:47:19 PM PDT 24
Peak memory 206288 kb
Host smart-89df196f-e03f-4511-861a-f33e22515758
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4125991194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.4125991194
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1000330775
Short name T2532
Test name
Test status
Simulation time 214953822 ps
CPU time 2.81 seconds
Started Jun 25 04:47:16 PM PDT 24
Finished Jun 25 04:47:22 PM PDT 24
Peak memory 223064 kb
Host smart-4eaaca62-31c4-4a79-8a7b-ef124f6297a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1000330775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.1000330775
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.672764057
Short name T291
Test name
Test status
Simulation time 815147658 ps
CPU time 4.88 seconds
Started Jun 25 04:47:14 PM PDT 24
Finished Jun 25 04:47:22 PM PDT 24
Peak memory 206340 kb
Host smart-584ac1ce-18ea-4817-bc89-92e133340859
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=672764057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.672764057
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.4185187673
Short name T1610
Test name
Test status
Simulation time 4263981895 ps
CPU time 5.27 seconds
Started Jun 25 04:55:54 PM PDT 24
Finished Jun 25 04:56:01 PM PDT 24
Peak memory 206724 kb
Host smart-e09044bd-5d06-4cf9-8e25-7025f6cbdb10
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4185187673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.4185187673
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.525836378
Short name T745
Test name
Test status
Simulation time 13348410296 ps
CPU time 13.05 seconds
Started Jun 25 04:55:51 PM PDT 24
Finished Jun 25 04:56:06 PM PDT 24
Peak memory 206704 kb
Host smart-8cea29f3-7cb1-4a10-97a4-925b54588928
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=525836378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.525836378
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.4267177331
Short name T1862
Test name
Test status
Simulation time 23337313861 ps
CPU time 22.72 seconds
Started Jun 25 04:55:55 PM PDT 24
Finished Jun 25 04:56:19 PM PDT 24
Peak memory 206836 kb
Host smart-054021c9-b3bb-481e-8112-6e511b20470f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4267177331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.4267177331
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.3908348432
Short name T1929
Test name
Test status
Simulation time 168411813 ps
CPU time 0.77 seconds
Started Jun 25 04:55:52 PM PDT 24
Finished Jun 25 04:55:54 PM PDT 24
Peak memory 206584 kb
Host smart-2ca9d7c7-82f5-4333-b00f-7717c60a8b86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39083
48432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.3908348432
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.2096209021
Short name T2267
Test name
Test status
Simulation time 151281400 ps
CPU time 0.77 seconds
Started Jun 25 04:55:55 PM PDT 24
Finished Jun 25 04:55:57 PM PDT 24
Peak memory 206476 kb
Host smart-4405cdbe-7738-4675-bffb-18c2aa43d2b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20962
09021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.2096209021
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.1847342140
Short name T1831
Test name
Test status
Simulation time 297971186 ps
CPU time 1.03 seconds
Started Jun 25 04:55:56 PM PDT 24
Finished Jun 25 04:55:59 PM PDT 24
Peak memory 206568 kb
Host smart-7dca8c44-fce7-481e-b089-0dbac9a54164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18473
42140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.1847342140
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.421710613
Short name T2454
Test name
Test status
Simulation time 861874541 ps
CPU time 2.25 seconds
Started Jun 25 04:55:54 PM PDT 24
Finished Jun 25 04:55:57 PM PDT 24
Peak memory 206760 kb
Host smart-52ad0c2d-1af4-4da4-b484-66a67c6397e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42171
0613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.421710613
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.3952506141
Short name T524
Test name
Test status
Simulation time 16238093178 ps
CPU time 30.37 seconds
Started Jun 25 04:55:53 PM PDT 24
Finished Jun 25 04:56:25 PM PDT 24
Peak memory 206972 kb
Host smart-8be05bfc-3ef4-4e56-a8bb-b56a2d267e50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39525
06141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.3952506141
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.2410941685
Short name T1964
Test name
Test status
Simulation time 542728586 ps
CPU time 1.55 seconds
Started Jun 25 04:55:53 PM PDT 24
Finished Jun 25 04:55:56 PM PDT 24
Peak memory 206512 kb
Host smart-1a3a6323-6754-4613-bced-79a269afec24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24109
41685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.2410941685
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.1513776027
Short name T324
Test name
Test status
Simulation time 167103711 ps
CPU time 0.79 seconds
Started Jun 25 04:55:55 PM PDT 24
Finished Jun 25 04:55:57 PM PDT 24
Peak memory 206512 kb
Host smart-3e7b5b0a-a508-4ff6-9760-0c6193e670f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15137
76027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.1513776027
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.472632933
Short name T1948
Test name
Test status
Simulation time 5155599703 ps
CPU time 44.77 seconds
Started Jun 25 04:55:55 PM PDT 24
Finished Jun 25 04:56:41 PM PDT 24
Peak memory 206940 kb
Host smart-26dd5a06-e19b-444d-b69b-db3247a0f1f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47263
2933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.472632933
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_enable.2694552377
Short name T1510
Test name
Test status
Simulation time 44468005 ps
CPU time 0.68 seconds
Started Jun 25 04:55:53 PM PDT 24
Finished Jun 25 04:55:55 PM PDT 24
Peak memory 206560 kb
Host smart-8cd04669-a5a0-464c-b0c7-7f62553639e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26945
52377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.2694552377
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.3796806464
Short name T1070
Test name
Test status
Simulation time 877509315 ps
CPU time 2.14 seconds
Started Jun 25 04:55:55 PM PDT 24
Finished Jun 25 04:55:58 PM PDT 24
Peak memory 206776 kb
Host smart-08d117f8-1fd1-4489-8b28-cf471ab8c795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37968
06464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.3796806464
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.1247562706
Short name T1195
Test name
Test status
Simulation time 197127803 ps
CPU time 1.6 seconds
Started Jun 25 04:55:54 PM PDT 24
Finished Jun 25 04:55:57 PM PDT 24
Peak memory 206712 kb
Host smart-cab68c4b-54f3-4626-946e-ace8c71c5bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12475
62706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.1247562706
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.575842935
Short name T732
Test name
Test status
Simulation time 165048197 ps
CPU time 0.79 seconds
Started Jun 25 04:56:09 PM PDT 24
Finished Jun 25 04:56:11 PM PDT 24
Peak memory 206528 kb
Host smart-8272b40d-0277-4ae0-a124-277fc1bc8777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57584
2935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.575842935
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.81047240
Short name T389
Test name
Test status
Simulation time 162607493 ps
CPU time 0.81 seconds
Started Jun 25 04:56:04 PM PDT 24
Finished Jun 25 04:56:07 PM PDT 24
Peak memory 206176 kb
Host smart-7e802900-3bb5-4bc7-99cf-0fcfed99ad1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81047
240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.81047240
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.3872255987
Short name T1167
Test name
Test status
Simulation time 220972112 ps
CPU time 0.87 seconds
Started Jun 25 04:55:53 PM PDT 24
Finished Jun 25 04:55:55 PM PDT 24
Peak memory 206512 kb
Host smart-f101b030-ad9f-4e94-8e21-84da7aa1f1ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38722
55987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.3872255987
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.2184373693
Short name T963
Test name
Test status
Simulation time 165556045 ps
CPU time 0.79 seconds
Started Jun 25 04:55:53 PM PDT 24
Finished Jun 25 04:55:55 PM PDT 24
Peak memory 206496 kb
Host smart-54248d83-2d57-47d2-a228-32ea9cfcc837
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21843
73693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.2184373693
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.491911224
Short name T73
Test name
Test status
Simulation time 461243114 ps
CPU time 1.3 seconds
Started Jun 25 04:55:51 PM PDT 24
Finished Jun 25 04:55:54 PM PDT 24
Peak memory 206500 kb
Host smart-2130c0c1-2836-46eb-b651-3ae367e761f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49191
1224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.491911224
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.634933949
Short name T1943
Test name
Test status
Simulation time 23279363397 ps
CPU time 23.01 seconds
Started Jun 25 04:55:55 PM PDT 24
Finished Jun 25 04:56:19 PM PDT 24
Peak memory 206620 kb
Host smart-b1e3b86d-c2c8-462a-8b1c-8abbce2b20b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63493
3949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.634933949
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.558877582
Short name T590
Test name
Test status
Simulation time 3388934062 ps
CPU time 3.92 seconds
Started Jun 25 04:55:56 PM PDT 24
Finished Jun 25 04:56:01 PM PDT 24
Peak memory 206692 kb
Host smart-35fa8a28-5473-4be9-9524-65beee42d573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55887
7582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.558877582
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.3460134090
Short name T595
Test name
Test status
Simulation time 10728938800 ps
CPU time 301.05 seconds
Started Jun 25 04:55:57 PM PDT 24
Finished Jun 25 05:00:59 PM PDT 24
Peak memory 206860 kb
Host smart-50771dcd-bd6f-4439-8c94-340b874a134f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3460134090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.3460134090
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.365000559
Short name T1804
Test name
Test status
Simulation time 244108220 ps
CPU time 0.93 seconds
Started Jun 25 04:56:04 PM PDT 24
Finished Jun 25 04:56:07 PM PDT 24
Peak memory 206260 kb
Host smart-d0a5548d-4396-420d-a0d3-c8ea425c2e13
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=365000559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.365000559
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.3810805362
Short name T404
Test name
Test status
Simulation time 209710112 ps
CPU time 0.87 seconds
Started Jun 25 04:55:54 PM PDT 24
Finished Jun 25 04:55:56 PM PDT 24
Peak memory 206576 kb
Host smart-8f6c3dc9-7097-4d88-af23-f55eba6f3617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38108
05362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.3810805362
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.62586377
Short name T815
Test name
Test status
Simulation time 6099603706 ps
CPU time 56.88 seconds
Started Jun 25 04:55:57 PM PDT 24
Finished Jun 25 04:56:55 PM PDT 24
Peak memory 206780 kb
Host smart-572ab3c2-fb04-4209-bc86-fba8ad546a4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62586
377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.62586377
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.1676280044
Short name T1485
Test name
Test status
Simulation time 10337560598 ps
CPU time 287.41 seconds
Started Jun 25 04:55:56 PM PDT 24
Finished Jun 25 05:00:45 PM PDT 24
Peak memory 206880 kb
Host smart-2b892c70-cc9b-4ad2-a399-84c3b4d73f3f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1676280044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.1676280044
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.1133921734
Short name T1761
Test name
Test status
Simulation time 197714586 ps
CPU time 0.83 seconds
Started Jun 25 04:56:01 PM PDT 24
Finished Jun 25 04:56:03 PM PDT 24
Peak memory 206516 kb
Host smart-0b9a213e-37f4-489e-9557-a6589dbce925
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1133921734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.1133921734
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.223429403
Short name T1719
Test name
Test status
Simulation time 215534822 ps
CPU time 0.83 seconds
Started Jun 25 04:55:52 PM PDT 24
Finished Jun 25 04:55:54 PM PDT 24
Peak memory 206580 kb
Host smart-de58c50e-9d0c-4416-9f25-bfbff243479a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22342
9403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.223429403
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.907765635
Short name T74
Test name
Test status
Simulation time 498978660 ps
CPU time 1.45 seconds
Started Jun 25 04:55:55 PM PDT 24
Finished Jun 25 04:55:58 PM PDT 24
Peak memory 206592 kb
Host smart-0a94d723-8c73-4c10-9e2c-d5f3da803fb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90776
5635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.907765635
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.269022418
Short name T1123
Test name
Test status
Simulation time 154514683 ps
CPU time 0.77 seconds
Started Jun 25 04:55:57 PM PDT 24
Finished Jun 25 04:55:59 PM PDT 24
Peak memory 206476 kb
Host smart-1e6788a7-d05d-4645-b54f-d645bc564849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26902
2418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.269022418
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.3439215369
Short name T1297
Test name
Test status
Simulation time 197695072 ps
CPU time 0.89 seconds
Started Jun 25 04:55:56 PM PDT 24
Finished Jun 25 04:55:58 PM PDT 24
Peak memory 206576 kb
Host smart-7c04854b-83cd-4948-bc3e-ac2f4bc9c741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34392
15369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.3439215369
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.3518564010
Short name T2391
Test name
Test status
Simulation time 193271234 ps
CPU time 0.82 seconds
Started Jun 25 04:55:54 PM PDT 24
Finished Jun 25 04:55:56 PM PDT 24
Peak memory 206576 kb
Host smart-8acf18ae-a5fa-4e8f-b11e-9d25a11a57b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35185
64010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.3518564010
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.2428248486
Short name T856
Test name
Test status
Simulation time 161581219 ps
CPU time 0.78 seconds
Started Jun 25 04:56:02 PM PDT 24
Finished Jun 25 04:56:05 PM PDT 24
Peak memory 206568 kb
Host smart-0295e3f2-149f-414c-83f0-50b69d755190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24282
48486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.2428248486
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.2181252762
Short name T2294
Test name
Test status
Simulation time 207061520 ps
CPU time 0.88 seconds
Started Jun 25 04:55:53 PM PDT 24
Finished Jun 25 04:55:55 PM PDT 24
Peak memory 206576 kb
Host smart-6b725bf3-132e-42e5-9abd-c70ca5c9e27f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21812
52762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.2181252762
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.3987594841
Short name T1633
Test name
Test status
Simulation time 261611081 ps
CPU time 0.99 seconds
Started Jun 25 04:56:01 PM PDT 24
Finished Jun 25 04:56:03 PM PDT 24
Peak memory 206524 kb
Host smart-0e94b97a-9c5c-40c8-9150-4e8ebf0e6d57
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3987594841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.3987594841
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.4272588624
Short name T2341
Test name
Test status
Simulation time 216036039 ps
CPU time 0.93 seconds
Started Jun 25 04:56:08 PM PDT 24
Finished Jun 25 04:56:10 PM PDT 24
Peak memory 206540 kb
Host smart-66deccc0-1695-47bf-996c-ef439f11c7d2
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4272588624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.4272588624
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.1964838765
Short name T201
Test name
Test status
Simulation time 192310243 ps
CPU time 0.88 seconds
Started Jun 25 04:55:59 PM PDT 24
Finished Jun 25 04:56:01 PM PDT 24
Peak memory 206600 kb
Host smart-f9f1aab5-da06-4e0b-9c13-ed494d79f899
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1964838765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.1964838765
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.915188636
Short name T2225
Test name
Test status
Simulation time 166255250 ps
CPU time 0.8 seconds
Started Jun 25 04:56:02 PM PDT 24
Finished Jun 25 04:56:06 PM PDT 24
Peak memory 206508 kb
Host smart-4f7919e4-77f4-4d61-b6b1-97817751f957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91518
8636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.915188636
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.1399266096
Short name T1066
Test name
Test status
Simulation time 88169042 ps
CPU time 0.74 seconds
Started Jun 25 04:56:02 PM PDT 24
Finished Jun 25 04:56:05 PM PDT 24
Peak memory 206596 kb
Host smart-8edd66c6-0eb2-4e23-bad3-39479e94482b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13992
66096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.1399266096
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.839737481
Short name T1133
Test name
Test status
Simulation time 10234121750 ps
CPU time 22.22 seconds
Started Jun 25 04:56:00 PM PDT 24
Finished Jun 25 04:56:24 PM PDT 24
Peak memory 206884 kb
Host smart-a430b1cb-1762-4b16-87fb-2810ff0a188b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83973
7481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.839737481
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.3927184312
Short name T2458
Test name
Test status
Simulation time 164506854 ps
CPU time 0.89 seconds
Started Jun 25 04:56:03 PM PDT 24
Finished Jun 25 04:56:06 PM PDT 24
Peak memory 206500 kb
Host smart-f25be06e-be97-4026-87b8-b098e6edd5d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39271
84312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.3927184312
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.2272050304
Short name T2385
Test name
Test status
Simulation time 207516393 ps
CPU time 0.86 seconds
Started Jun 25 04:56:02 PM PDT 24
Finished Jun 25 04:56:05 PM PDT 24
Peak memory 206580 kb
Host smart-f4b33209-fd9b-4692-a65d-207befdf74cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22720
50304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.2272050304
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.3990095425
Short name T2376
Test name
Test status
Simulation time 16417534360 ps
CPU time 469.24 seconds
Started Jun 25 04:56:01 PM PDT 24
Finished Jun 25 05:03:53 PM PDT 24
Peak memory 206988 kb
Host smart-4da0065b-77f4-4d0b-88b6-85ff4c1b9a37
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3990095425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.3990095425
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.3228653248
Short name T2091
Test name
Test status
Simulation time 13895875734 ps
CPU time 101.32 seconds
Started Jun 25 04:56:04 PM PDT 24
Finished Jun 25 04:57:48 PM PDT 24
Peak memory 206840 kb
Host smart-ab1c6bb1-79c9-4935-b32b-7784b4399e4e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3228653248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.3228653248
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.350316442
Short name T1650
Test name
Test status
Simulation time 229255655 ps
CPU time 0.91 seconds
Started Jun 25 04:56:04 PM PDT 24
Finished Jun 25 04:56:07 PM PDT 24
Peak memory 206512 kb
Host smart-303a4e8f-4d9e-41fa-a7cf-1ab3eaabf940
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35031
6442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.350316442
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.1774246199
Short name T605
Test name
Test status
Simulation time 145429009 ps
CPU time 0.79 seconds
Started Jun 25 04:56:01 PM PDT 24
Finished Jun 25 04:56:03 PM PDT 24
Peak memory 206456 kb
Host smart-c8234e96-5329-4473-a5bd-a1ad2e3e3d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17742
46199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.1774246199
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.1722871552
Short name T606
Test name
Test status
Simulation time 138531441 ps
CPU time 0.77 seconds
Started Jun 25 04:56:09 PM PDT 24
Finished Jun 25 04:56:10 PM PDT 24
Peak memory 206520 kb
Host smart-c806fc7a-eea3-4604-899f-112707794bf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17228
71552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.1722871552
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.3034733825
Short name T2495
Test name
Test status
Simulation time 155933450 ps
CPU time 0.81 seconds
Started Jun 25 04:56:02 PM PDT 24
Finished Jun 25 04:56:05 PM PDT 24
Peak memory 206568 kb
Host smart-d91ea959-47c7-4911-9169-ad5a751cdd75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30347
33825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.3034733825
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.3993999614
Short name T598
Test name
Test status
Simulation time 196579251 ps
CPU time 0.89 seconds
Started Jun 25 04:56:00 PM PDT 24
Finished Jun 25 04:56:02 PM PDT 24
Peak memory 206512 kb
Host smart-a1426d2b-3b15-4fc3-be4b-2cd2a87c156f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39939
99614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.3993999614
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.3657578521
Short name T457
Test name
Test status
Simulation time 289611339 ps
CPU time 0.95 seconds
Started Jun 25 04:56:09 PM PDT 24
Finished Jun 25 04:56:11 PM PDT 24
Peak memory 206520 kb
Host smart-5d99e446-c4b8-4f50-98e2-14bca9ca709b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36575
78521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.3657578521
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.10655049
Short name T1383
Test name
Test status
Simulation time 4273413963 ps
CPU time 121.02 seconds
Started Jun 25 04:56:02 PM PDT 24
Finished Jun 25 04:58:05 PM PDT 24
Peak memory 206872 kb
Host smart-b9ade468-d40d-46d0-9e98-724d905e65c4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=10655049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.10655049
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.949893509
Short name T2456
Test name
Test status
Simulation time 161466426 ps
CPU time 0.82 seconds
Started Jun 25 04:56:02 PM PDT 24
Finished Jun 25 04:56:06 PM PDT 24
Peak memory 206528 kb
Host smart-8fa12f34-20d1-4108-9094-62f7e6146dff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94989
3509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.949893509
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.3475281251
Short name T581
Test name
Test status
Simulation time 170315572 ps
CPU time 0.85 seconds
Started Jun 25 04:56:02 PM PDT 24
Finished Jun 25 04:56:05 PM PDT 24
Peak memory 206508 kb
Host smart-28b29ded-04b0-40f1-b939-453a1de60dfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34752
81251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.3475281251
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.892578213
Short name T2013
Test name
Test status
Simulation time 6001922297 ps
CPU time 42.6 seconds
Started Jun 25 04:56:02 PM PDT 24
Finished Jun 25 04:56:46 PM PDT 24
Peak memory 206860 kb
Host smart-ee0f2aaa-0842-41e4-8efe-8c112411d52e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89257
8213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.892578213
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.2000843473
Short name T103
Test name
Test status
Simulation time 24920439387 ps
CPU time 679.96 seconds
Started Jun 25 04:56:03 PM PDT 24
Finished Jun 25 05:07:26 PM PDT 24
Peak memory 206912 kb
Host smart-e6fdba11-1ba3-42e0-a441-1080b9e818ba
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2000843473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.2000843473
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.4095472163
Short name T1409
Test name
Test status
Simulation time 4242277948 ps
CPU time 4.5 seconds
Started Jun 25 04:56:03 PM PDT 24
Finished Jun 25 04:56:10 PM PDT 24
Peak memory 206888 kb
Host smart-63185c2e-3529-46e8-9acc-df23af2697c3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4095472163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.4095472163
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.380641206
Short name T483
Test name
Test status
Simulation time 13371615563 ps
CPU time 11.93 seconds
Started Jun 25 04:56:01 PM PDT 24
Finished Jun 25 04:56:14 PM PDT 24
Peak memory 206816 kb
Host smart-86a7fb8e-2d3c-4885-bafd-f4be9544a4b5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=380641206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.380641206
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.884998515
Short name T1700
Test name
Test status
Simulation time 23332189773 ps
CPU time 25.4 seconds
Started Jun 25 04:56:01 PM PDT 24
Finished Jun 25 04:56:29 PM PDT 24
Peak memory 206716 kb
Host smart-2b7e7f02-8040-4d11-b5d0-e557408f0de3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=884998515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.884998515
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.1881872605
Short name T701
Test name
Test status
Simulation time 192098828 ps
CPU time 0.88 seconds
Started Jun 25 04:56:04 PM PDT 24
Finished Jun 25 04:56:08 PM PDT 24
Peak memory 206576 kb
Host smart-055468d6-2b53-4b9e-bcc8-0b99f090b645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18818
72605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.1881872605
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.4163897437
Short name T59
Test name
Test status
Simulation time 173501517 ps
CPU time 0.86 seconds
Started Jun 25 04:56:02 PM PDT 24
Finished Jun 25 04:56:06 PM PDT 24
Peak memory 206512 kb
Host smart-27494fe7-067b-466a-add2-4653589c0ad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41638
97437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.4163897437
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.858514302
Short name T816
Test name
Test status
Simulation time 144662632 ps
CPU time 0.78 seconds
Started Jun 25 04:56:01 PM PDT 24
Finished Jun 25 04:56:03 PM PDT 24
Peak memory 206572 kb
Host smart-94f3b19c-4d9d-4f70-a57c-754fb1003b75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85851
4302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.858514302
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.2122483965
Short name T2235
Test name
Test status
Simulation time 194670039 ps
CPU time 0.81 seconds
Started Jun 25 04:56:03 PM PDT 24
Finished Jun 25 04:56:06 PM PDT 24
Peak memory 206572 kb
Host smart-b49d346c-a73c-43fb-b53a-6523b2c04e7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21224
83965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.2122483965
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.1990444681
Short name T1968
Test name
Test status
Simulation time 1375625901 ps
CPU time 3.12 seconds
Started Jun 25 04:56:02 PM PDT 24
Finished Jun 25 04:56:08 PM PDT 24
Peak memory 206672 kb
Host smart-5f4506f9-dd57-4b60-a2cd-6ea3b62f4ce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19904
44681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.1990444681
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.3587853384
Short name T1800
Test name
Test status
Simulation time 21558476812 ps
CPU time 37.84 seconds
Started Jun 25 04:56:03 PM PDT 24
Finished Jun 25 04:56:44 PM PDT 24
Peak memory 206932 kb
Host smart-751ef25a-7bf9-4d39-8af1-001da34585a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35878
53384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.3587853384
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.567613276
Short name T1514
Test name
Test status
Simulation time 424008995 ps
CPU time 1.39 seconds
Started Jun 25 04:56:01 PM PDT 24
Finished Jun 25 04:56:03 PM PDT 24
Peak memory 206544 kb
Host smart-9f114919-0193-4d4f-95aa-cde670e8ea85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56761
3276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.567613276
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.3188918714
Short name T1203
Test name
Test status
Simulation time 175326734 ps
CPU time 0.76 seconds
Started Jun 25 04:56:01 PM PDT 24
Finished Jun 25 04:56:04 PM PDT 24
Peak memory 206500 kb
Host smart-1e44b9a0-15db-45ec-936c-4867f4caa103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31889
18714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.3188918714
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.2626321990
Short name T834
Test name
Test status
Simulation time 73684424 ps
CPU time 0.7 seconds
Started Jun 25 04:56:10 PM PDT 24
Finished Jun 25 04:56:13 PM PDT 24
Peak memory 206520 kb
Host smart-afa04ca0-1931-40e0-b645-ae0422f811fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26263
21990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.2626321990
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.1357563318
Short name T1298
Test name
Test status
Simulation time 850485083 ps
CPU time 1.97 seconds
Started Jun 25 04:56:05 PM PDT 24
Finished Jun 25 04:56:09 PM PDT 24
Peak memory 206688 kb
Host smart-3aabcf4d-a4eb-4614-a601-4f9deedf9658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13575
63318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.1357563318
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.3754243
Short name T874
Test name
Test status
Simulation time 243667828 ps
CPU time 1.69 seconds
Started Jun 25 04:56:14 PM PDT 24
Finished Jun 25 04:56:17 PM PDT 24
Peak memory 206676 kb
Host smart-885d6ce5-d58a-4a46-87ac-57b5a1a81c5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37542
43 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.3754243
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.2408801009
Short name T2163
Test name
Test status
Simulation time 197725598 ps
CPU time 0.88 seconds
Started Jun 25 04:56:12 PM PDT 24
Finished Jun 25 04:56:15 PM PDT 24
Peak memory 206584 kb
Host smart-43b19478-0891-4cd8-9aed-708dac604e3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24088
01009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.2408801009
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.3643694257
Short name T1279
Test name
Test status
Simulation time 138207081 ps
CPU time 0.78 seconds
Started Jun 25 04:56:15 PM PDT 24
Finished Jun 25 04:56:17 PM PDT 24
Peak memory 206468 kb
Host smart-d0a0117e-e24e-4b3c-8a5b-448ff901fae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36436
94257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.3643694257
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.1278448758
Short name T2397
Test name
Test status
Simulation time 153290092 ps
CPU time 0.8 seconds
Started Jun 25 04:56:10 PM PDT 24
Finished Jun 25 04:56:12 PM PDT 24
Peak memory 206496 kb
Host smart-8cbbeeab-2165-485e-8ef4-64ca2c932f68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12784
48758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.1278448758
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.3331891167
Short name T1496
Test name
Test status
Simulation time 162175090 ps
CPU time 0.8 seconds
Started Jun 25 04:56:10 PM PDT 24
Finished Jun 25 04:56:13 PM PDT 24
Peak memory 206572 kb
Host smart-d573c6d6-0d2c-4f60-887c-e26707f0e923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33318
91167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.3331891167
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.2214856924
Short name T325
Test name
Test status
Simulation time 23306179956 ps
CPU time 26.54 seconds
Started Jun 25 04:56:15 PM PDT 24
Finished Jun 25 04:56:43 PM PDT 24
Peak memory 206584 kb
Host smart-7e24fe15-1240-4665-bc90-ad63d0006c0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22148
56924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.2214856924
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.1279836151
Short name T2022
Test name
Test status
Simulation time 3290110845 ps
CPU time 3.53 seconds
Started Jun 25 04:56:10 PM PDT 24
Finished Jun 25 04:56:16 PM PDT 24
Peak memory 206580 kb
Host smart-d8098f2e-0a7d-47d0-94a2-f232819987ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12798
36151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.1279836151
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.1962023877
Short name T685
Test name
Test status
Simulation time 4652958381 ps
CPU time 33.01 seconds
Started Jun 25 04:56:13 PM PDT 24
Finished Jun 25 04:56:48 PM PDT 24
Peak memory 206900 kb
Host smart-a5560c7a-de10-4b4e-8f79-0bbf54007a4a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1962023877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.1962023877
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.1914297619
Short name T422
Test name
Test status
Simulation time 248742419 ps
CPU time 1.01 seconds
Started Jun 25 04:56:12 PM PDT 24
Finished Jun 25 04:56:16 PM PDT 24
Peak memory 206576 kb
Host smart-90fa3e13-850e-4979-9378-74683c56182b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1914297619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.1914297619
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.2776163845
Short name T1276
Test name
Test status
Simulation time 194223455 ps
CPU time 0.88 seconds
Started Jun 25 04:56:11 PM PDT 24
Finished Jun 25 04:56:15 PM PDT 24
Peak memory 206576 kb
Host smart-5db2bf42-fc71-4e78-a83e-bef2d90f395b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27761
63845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.2776163845
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.9064938
Short name T884
Test name
Test status
Simulation time 8878105817 ps
CPU time 88.16 seconds
Started Jun 25 04:56:13 PM PDT 24
Finished Jun 25 04:57:43 PM PDT 24
Peak memory 206812 kb
Host smart-98c9d9a3-aceb-45d3-9bf3-c73658dcc597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90649
38 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.9064938
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.1054925001
Short name T1373
Test name
Test status
Simulation time 9165993696 ps
CPU time 66.3 seconds
Started Jun 25 04:56:13 PM PDT 24
Finished Jun 25 04:57:21 PM PDT 24
Peak memory 206768 kb
Host smart-f94d1edf-f50d-4b22-9437-58619cc18b2e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1054925001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.1054925001
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.1850412197
Short name T1426
Test name
Test status
Simulation time 151231921 ps
CPU time 0.79 seconds
Started Jun 25 04:56:15 PM PDT 24
Finished Jun 25 04:56:17 PM PDT 24
Peak memory 206476 kb
Host smart-f948f606-dffb-4ee4-9510-bd2567f184de
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1850412197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.1850412197
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.841026272
Short name T1224
Test name
Test status
Simulation time 150749668 ps
CPU time 0.77 seconds
Started Jun 25 04:56:11 PM PDT 24
Finished Jun 25 04:56:14 PM PDT 24
Peak memory 206508 kb
Host smart-92c0432a-2ff2-4ed9-b95a-70d9e0d75ba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84102
6272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.841026272
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.3460886821
Short name T469
Test name
Test status
Simulation time 157593693 ps
CPU time 0.79 seconds
Started Jun 25 04:56:08 PM PDT 24
Finished Jun 25 04:56:10 PM PDT 24
Peak memory 206592 kb
Host smart-97de7bbb-3f45-40b3-8882-ae80124360f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34608
86821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.3460886821
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.2799386898
Short name T28
Test name
Test status
Simulation time 158114827 ps
CPU time 0.82 seconds
Started Jun 25 04:56:11 PM PDT 24
Finished Jun 25 04:56:14 PM PDT 24
Peak memory 206464 kb
Host smart-69d76488-b997-4ade-87d7-618b85d504b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27993
86898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.2799386898
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.1713486518
Short name T1988
Test name
Test status
Simulation time 176687965 ps
CPU time 0.85 seconds
Started Jun 25 04:56:11 PM PDT 24
Finished Jun 25 04:56:14 PM PDT 24
Peak memory 206572 kb
Host smart-528ffa2d-915d-4e45-84f6-8a5d6e3a29f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17134
86518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.1713486518
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.309743333
Short name T1726
Test name
Test status
Simulation time 176915957 ps
CPU time 0.83 seconds
Started Jun 25 04:56:10 PM PDT 24
Finished Jun 25 04:56:13 PM PDT 24
Peak memory 206492 kb
Host smart-6b8ea872-32c1-40d7-8b3b-bc8e690d49c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30974
3333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.309743333
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.2265896979
Short name T1641
Test name
Test status
Simulation time 206393313 ps
CPU time 0.98 seconds
Started Jun 25 04:56:11 PM PDT 24
Finished Jun 25 04:56:15 PM PDT 24
Peak memory 206532 kb
Host smart-f5c2ec46-1117-4ce6-b501-0a2adc30800a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2265896979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.2265896979
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.1273468184
Short name T200
Test name
Test status
Simulation time 260914921 ps
CPU time 0.96 seconds
Started Jun 25 04:56:10 PM PDT 24
Finished Jun 25 04:56:12 PM PDT 24
Peak memory 206560 kb
Host smart-479849cd-7b5e-402e-8d9a-f64d5b6fccfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12734
68184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.1273468184
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.618964700
Short name T2384
Test name
Test status
Simulation time 34876924 ps
CPU time 0.63 seconds
Started Jun 25 04:56:13 PM PDT 24
Finished Jun 25 04:56:16 PM PDT 24
Peak memory 206500 kb
Host smart-96f02e5c-e075-40cd-9d38-57afd515f747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61896
4700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.618964700
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.3317654445
Short name T1892
Test name
Test status
Simulation time 9773307695 ps
CPU time 22.95 seconds
Started Jun 25 04:56:10 PM PDT 24
Finished Jun 25 04:56:34 PM PDT 24
Peak memory 215024 kb
Host smart-37032d1a-d9ac-45c9-9f54-4df3bb0e8765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33176
54445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.3317654445
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.2733270968
Short name T1301
Test name
Test status
Simulation time 187813587 ps
CPU time 0.83 seconds
Started Jun 25 04:56:13 PM PDT 24
Finished Jun 25 04:56:16 PM PDT 24
Peak memory 206504 kb
Host smart-7e6f8b01-b895-4300-9120-8b6efddad0a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27332
70968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.2733270968
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.406784822
Short name T1674
Test name
Test status
Simulation time 221215340 ps
CPU time 0.87 seconds
Started Jun 25 04:56:12 PM PDT 24
Finished Jun 25 04:56:15 PM PDT 24
Peak memory 206584 kb
Host smart-94ffc9cf-8170-4193-bf2b-6f7fa5bd841c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40678
4822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.406784822
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.2813758824
Short name T1384
Test name
Test status
Simulation time 14000983101 ps
CPU time 126.09 seconds
Started Jun 25 04:56:13 PM PDT 24
Finished Jun 25 04:58:21 PM PDT 24
Peak memory 206916 kb
Host smart-ba451ad5-34d6-438d-808a-0bd1282fd2a6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2813758824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.2813758824
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.1785663405
Short name T2254
Test name
Test status
Simulation time 16572500776 ps
CPU time 455.05 seconds
Started Jun 25 04:56:13 PM PDT 24
Finished Jun 25 05:03:50 PM PDT 24
Peak memory 206908 kb
Host smart-0689353b-d442-457a-8698-fc187c44187f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1785663405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.1785663405
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.1196504227
Short name T148
Test name
Test status
Simulation time 19434993124 ps
CPU time 460.42 seconds
Started Jun 25 04:56:10 PM PDT 24
Finished Jun 25 05:03:53 PM PDT 24
Peak memory 207100 kb
Host smart-a1642468-94f9-469b-8ab5-73313daf16b7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1196504227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.1196504227
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.3287539543
Short name T861
Test name
Test status
Simulation time 229733641 ps
CPU time 0.88 seconds
Started Jun 25 04:56:11 PM PDT 24
Finished Jun 25 04:56:14 PM PDT 24
Peak memory 206592 kb
Host smart-4c45eb31-0370-4a88-9695-7cb75fd3434f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32875
39543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.3287539543
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.771795075
Short name T2480
Test name
Test status
Simulation time 242267002 ps
CPU time 0.93 seconds
Started Jun 25 04:56:11 PM PDT 24
Finished Jun 25 04:56:15 PM PDT 24
Peak memory 206512 kb
Host smart-57dc8d7e-47dd-4679-8791-6be628605850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77179
5075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.771795075
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.763975685
Short name T1706
Test name
Test status
Simulation time 148840577 ps
CPU time 0.75 seconds
Started Jun 25 04:56:14 PM PDT 24
Finished Jun 25 04:56:16 PM PDT 24
Peak memory 206508 kb
Host smart-214bdd4f-c2cf-4b8e-8333-d932e70111f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76397
5685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.763975685
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.2938861165
Short name T79
Test name
Test status
Simulation time 176589448 ps
CPU time 0.79 seconds
Started Jun 25 04:56:10 PM PDT 24
Finished Jun 25 04:56:13 PM PDT 24
Peak memory 206520 kb
Host smart-b2f633a8-b4c4-4b9b-ae22-4ad259d9818b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29388
61165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.2938861165
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.3688937563
Short name T207
Test name
Test status
Simulation time 263949199 ps
CPU time 1.07 seconds
Started Jun 25 04:56:24 PM PDT 24
Finished Jun 25 04:56:28 PM PDT 24
Peak memory 224388 kb
Host smart-b8618546-b096-49b5-aa1e-ed08c2a04e92
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3688937563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.3688937563
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.2128155520
Short name T1736
Test name
Test status
Simulation time 414219198 ps
CPU time 1.36 seconds
Started Jun 25 04:56:09 PM PDT 24
Finished Jun 25 04:56:11 PM PDT 24
Peak memory 206576 kb
Host smart-697888a4-3bcb-414c-a037-a6b450bfb41a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21281
55520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.2128155520
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.4232149100
Short name T2302
Test name
Test status
Simulation time 146868537 ps
CPU time 0.76 seconds
Started Jun 25 04:56:13 PM PDT 24
Finished Jun 25 04:56:16 PM PDT 24
Peak memory 206492 kb
Host smart-f7df0395-6255-454d-88a5-98bdeca8b5d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42321
49100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.4232149100
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.1717839044
Short name T2101
Test name
Test status
Simulation time 154046546 ps
CPU time 0.8 seconds
Started Jun 25 04:56:10 PM PDT 24
Finished Jun 25 04:56:12 PM PDT 24
Peak memory 206508 kb
Host smart-87be9f00-1cb4-4243-95a3-91cba805e9dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17178
39044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.1717839044
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.3998573097
Short name T1720
Test name
Test status
Simulation time 199950543 ps
CPU time 0.96 seconds
Started Jun 25 04:56:12 PM PDT 24
Finished Jun 25 04:56:16 PM PDT 24
Peak memory 206584 kb
Host smart-ea8a5b1e-b3a0-474f-a865-de9cc810ea3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39985
73097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.3998573097
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.32396149
Short name T800
Test name
Test status
Simulation time 13587181337 ps
CPU time 98.69 seconds
Started Jun 25 04:56:12 PM PDT 24
Finished Jun 25 04:57:53 PM PDT 24
Peak memory 206896 kb
Host smart-fc32b27a-28ef-4c48-a5d6-8f4695fd3e9d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=32396149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.32396149
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.1194557577
Short name T1623
Test name
Test status
Simulation time 203311694 ps
CPU time 0.83 seconds
Started Jun 25 04:56:11 PM PDT 24
Finished Jun 25 04:56:15 PM PDT 24
Peak memory 206548 kb
Host smart-012eeeb5-6232-43d8-b19b-c927472f8241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11945
57577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.1194557577
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.3190448615
Short name T2352
Test name
Test status
Simulation time 155081591 ps
CPU time 0.78 seconds
Started Jun 25 04:56:11 PM PDT 24
Finished Jun 25 04:56:15 PM PDT 24
Peak memory 206576 kb
Host smart-588d17b0-cf9f-4bf8-acfc-92b777af7135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31904
48615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.3190448615
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.959043901
Short name T2054
Test name
Test status
Simulation time 10346430170 ps
CPU time 275.15 seconds
Started Jun 25 04:56:10 PM PDT 24
Finished Jun 25 05:00:48 PM PDT 24
Peak memory 206844 kb
Host smart-dd3892e2-d9b6-438e-aa54-95622cfa91e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95904
3901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.959043901
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.3020288324
Short name T1053
Test name
Test status
Simulation time 4164288015 ps
CPU time 5.29 seconds
Started Jun 25 04:57:47 PM PDT 24
Finished Jun 25 04:57:53 PM PDT 24
Peak memory 206856 kb
Host smart-3a2e6814-d6e7-4908-9295-bb3d28a819d0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3020288324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.3020288324
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.3259808104
Short name T1820
Test name
Test status
Simulation time 13489428357 ps
CPU time 12.45 seconds
Started Jun 25 04:57:51 PM PDT 24
Finished Jun 25 04:58:05 PM PDT 24
Peak memory 206924 kb
Host smart-e990f361-da0f-4f26-bca0-2f136d7135ee
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3259808104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.3259808104
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.4146921150
Short name T633
Test name
Test status
Simulation time 23343522823 ps
CPU time 23.79 seconds
Started Jun 25 04:57:54 PM PDT 24
Finished Jun 25 04:58:20 PM PDT 24
Peak memory 206860 kb
Host smart-158bd730-4d40-4f43-970a-645eb676142e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4146921150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.4146921150
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.2656195055
Short name T2314
Test name
Test status
Simulation time 246757571 ps
CPU time 0.9 seconds
Started Jun 25 04:57:46 PM PDT 24
Finished Jun 25 04:57:48 PM PDT 24
Peak memory 206572 kb
Host smart-7442c2c8-62e1-4de4-8a69-b40d4212c3a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26561
95055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.2656195055
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.2828770252
Short name T2301
Test name
Test status
Simulation time 168876466 ps
CPU time 0.78 seconds
Started Jun 25 04:57:48 PM PDT 24
Finished Jun 25 04:57:50 PM PDT 24
Peak memory 206592 kb
Host smart-64dc1fc5-7411-4799-8208-6a0198f0b449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28287
70252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.2828770252
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.1471777715
Short name T749
Test name
Test status
Simulation time 469809087 ps
CPU time 1.42 seconds
Started Jun 25 04:57:50 PM PDT 24
Finished Jun 25 04:57:54 PM PDT 24
Peak memory 206568 kb
Host smart-2b7f174e-afd4-4c43-b89e-09f36f00505f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14717
77715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.1471777715
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.2704881435
Short name T2317
Test name
Test status
Simulation time 399974140 ps
CPU time 1.13 seconds
Started Jun 25 04:57:51 PM PDT 24
Finished Jun 25 04:57:54 PM PDT 24
Peak memory 206516 kb
Host smart-19784f3d-bb78-421c-aa83-297d8fd94001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27048
81435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.2704881435
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.2008306366
Short name T2116
Test name
Test status
Simulation time 21146144145 ps
CPU time 40.26 seconds
Started Jun 25 04:57:50 PM PDT 24
Finished Jun 25 04:58:32 PM PDT 24
Peak memory 206844 kb
Host smart-6d9cb128-86e1-4ce5-a455-78480612c383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20083
06366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.2008306366
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.2380081218
Short name T1073
Test name
Test status
Simulation time 346561247 ps
CPU time 1.16 seconds
Started Jun 25 04:57:50 PM PDT 24
Finished Jun 25 04:57:54 PM PDT 24
Peak memory 206572 kb
Host smart-2789065f-26cd-46dd-b506-eb964c9e8e71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23800
81218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.2380081218
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.719095177
Short name T2104
Test name
Test status
Simulation time 161701823 ps
CPU time 0.76 seconds
Started Jun 25 04:57:51 PM PDT 24
Finished Jun 25 04:57:54 PM PDT 24
Peak memory 206496 kb
Host smart-cfa3a5dd-2f16-409a-9ad1-203edb9120ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71909
5177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.719095177
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.3591924702
Short name T1145
Test name
Test status
Simulation time 50468994 ps
CPU time 0.67 seconds
Started Jun 25 04:57:54 PM PDT 24
Finished Jun 25 04:57:57 PM PDT 24
Peak memory 206508 kb
Host smart-58898566-e65e-4da9-a103-000c6ef49f4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35919
24702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.3591924702
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.135265856
Short name T1052
Test name
Test status
Simulation time 836992719 ps
CPU time 1.94 seconds
Started Jun 25 04:57:51 PM PDT 24
Finished Jun 25 04:57:56 PM PDT 24
Peak memory 206796 kb
Host smart-206777a2-38c6-46d5-9329-ad7b06efd5bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13526
5856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.135265856
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.1938918015
Short name T1996
Test name
Test status
Simulation time 239267287 ps
CPU time 1.67 seconds
Started Jun 25 04:57:51 PM PDT 24
Finished Jun 25 04:57:55 PM PDT 24
Peak memory 206728 kb
Host smart-e1a9ea06-8590-41fb-aedb-f6df20ee672a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19389
18015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.1938918015
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.1956611649
Short name T2067
Test name
Test status
Simulation time 172515841 ps
CPU time 0.8 seconds
Started Jun 25 04:57:57 PM PDT 24
Finished Jun 25 04:58:00 PM PDT 24
Peak memory 206592 kb
Host smart-e828e6a7-8a86-44c0-b0da-3c911f371408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19566
11649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.1956611649
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.3771545706
Short name T636
Test name
Test status
Simulation time 137897495 ps
CPU time 0.8 seconds
Started Jun 25 04:57:57 PM PDT 24
Finished Jun 25 04:58:00 PM PDT 24
Peak memory 206508 kb
Host smart-c5de310f-e8f2-436b-850a-f3f712ba23ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37715
45706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.3771545706
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.1594871682
Short name T2001
Test name
Test status
Simulation time 248620396 ps
CPU time 0.99 seconds
Started Jun 25 04:57:49 PM PDT 24
Finished Jun 25 04:57:51 PM PDT 24
Peak memory 206508 kb
Host smart-27d03a8c-8609-4aad-8e59-b1b79e7ef31a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15948
71682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.1594871682
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.314793716
Short name T1278
Test name
Test status
Simulation time 204778367 ps
CPU time 0.81 seconds
Started Jun 25 04:57:51 PM PDT 24
Finished Jun 25 04:57:54 PM PDT 24
Peak memory 206572 kb
Host smart-e5c7c67f-221a-4aaf-b4ae-ac6bfd59ed04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31479
3716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.314793716
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.1101360892
Short name T1636
Test name
Test status
Simulation time 23400503217 ps
CPU time 23.32 seconds
Started Jun 25 04:57:51 PM PDT 24
Finished Jun 25 04:58:16 PM PDT 24
Peak memory 206620 kb
Host smart-3d5e6fef-f674-4c52-bab9-9799ed3dcd21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11013
60892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.1101360892
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.4236429317
Short name T2049
Test name
Test status
Simulation time 3318151699 ps
CPU time 3.98 seconds
Started Jun 25 04:57:50 PM PDT 24
Finished Jun 25 04:57:56 PM PDT 24
Peak memory 206720 kb
Host smart-3fac10b6-af32-47aa-ae18-47586079e2d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42364
29317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.4236429317
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.2816507568
Short name T2131
Test name
Test status
Simulation time 15495038556 ps
CPU time 153.15 seconds
Started Jun 25 04:57:57 PM PDT 24
Finished Jun 25 05:00:32 PM PDT 24
Peak memory 206876 kb
Host smart-3ea9a567-2105-4b27-adba-02ac4294af59
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2816507568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.2816507568
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.1364622097
Short name T1231
Test name
Test status
Simulation time 243663547 ps
CPU time 0.9 seconds
Started Jun 25 04:57:55 PM PDT 24
Finished Jun 25 04:57:58 PM PDT 24
Peak memory 206572 kb
Host smart-4a6ced66-6942-4620-a682-80d03df0c464
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1364622097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.1364622097
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.983874756
Short name T991
Test name
Test status
Simulation time 198099416 ps
CPU time 0.88 seconds
Started Jun 25 04:57:48 PM PDT 24
Finished Jun 25 04:57:49 PM PDT 24
Peak memory 206604 kb
Host smart-d0a611dd-0dcc-44e7-bedc-d3c9b8e4446d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98387
4756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.983874756
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.3979037187
Short name T1105
Test name
Test status
Simulation time 7457110946 ps
CPU time 75.46 seconds
Started Jun 25 04:57:49 PM PDT 24
Finished Jun 25 04:59:05 PM PDT 24
Peak memory 206916 kb
Host smart-143c677a-16a8-4029-9561-92859e5e6adf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39790
37187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.3979037187
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.1600025358
Short name T2398
Test name
Test status
Simulation time 8494230041 ps
CPU time 58.51 seconds
Started Jun 25 04:57:57 PM PDT 24
Finished Jun 25 04:58:58 PM PDT 24
Peak memory 206908 kb
Host smart-cd389486-3c6f-40e6-a45c-5f7ca0e6d51a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1600025358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.1600025358
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.1989718151
Short name T1909
Test name
Test status
Simulation time 157135697 ps
CPU time 0.81 seconds
Started Jun 25 04:57:58 PM PDT 24
Finished Jun 25 04:58:01 PM PDT 24
Peak memory 206524 kb
Host smart-2f1f1a7e-e5bb-44fd-9af5-6fbd9cf7dcf2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1989718151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.1989718151
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.3819118748
Short name T296
Test name
Test status
Simulation time 140667799 ps
CPU time 0.77 seconds
Started Jun 25 04:57:51 PM PDT 24
Finished Jun 25 04:57:55 PM PDT 24
Peak memory 206576 kb
Host smart-3e664cc5-7109-4062-8440-7aece022b512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38191
18748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.3819118748
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.2237078618
Short name T946
Test name
Test status
Simulation time 189671199 ps
CPU time 0.9 seconds
Started Jun 25 04:57:57 PM PDT 24
Finished Jun 25 04:57:59 PM PDT 24
Peak memory 206568 kb
Host smart-985bae50-b2d1-47ce-b1f9-e6dc666198de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22370
78618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.2237078618
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.2465971956
Short name T1387
Test name
Test status
Simulation time 171560270 ps
CPU time 0.78 seconds
Started Jun 25 04:57:56 PM PDT 24
Finished Jun 25 04:57:58 PM PDT 24
Peak memory 206592 kb
Host smart-49932753-c926-40fe-855b-eeab55278fcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24659
71956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.2465971956
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.981817441
Short name T1095
Test name
Test status
Simulation time 189381010 ps
CPU time 0.83 seconds
Started Jun 25 04:57:55 PM PDT 24
Finished Jun 25 04:57:58 PM PDT 24
Peak memory 206580 kb
Host smart-7da627a9-a245-4e13-9470-8c9e62fbf9cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98181
7441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.981817441
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.1957415573
Short name T1806
Test name
Test status
Simulation time 168827913 ps
CPU time 0.8 seconds
Started Jun 25 04:57:59 PM PDT 24
Finished Jun 25 04:58:02 PM PDT 24
Peak memory 205652 kb
Host smart-cf17957f-572b-4e2a-a827-0fbfc470c5b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19574
15573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.1957415573
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.746365490
Short name T1780
Test name
Test status
Simulation time 217203198 ps
CPU time 0.95 seconds
Started Jun 25 04:57:56 PM PDT 24
Finished Jun 25 04:57:59 PM PDT 24
Peak memory 206732 kb
Host smart-cd37ae19-e208-42d9-a9a2-53e79492a540
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=746365490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.746365490
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.1192490829
Short name T2359
Test name
Test status
Simulation time 165464831 ps
CPU time 0.78 seconds
Started Jun 25 04:58:01 PM PDT 24
Finished Jun 25 04:58:03 PM PDT 24
Peak memory 206480 kb
Host smart-6e9457c9-c26b-4d99-a377-a55ca0b6fb4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11924
90829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.1192490829
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.3393492511
Short name T239
Test name
Test status
Simulation time 20596045466 ps
CPU time 49.99 seconds
Started Jun 25 04:58:00 PM PDT 24
Finished Jun 25 04:58:52 PM PDT 24
Peak memory 206976 kb
Host smart-76693b0e-46a1-48a7-8139-45d6f5c798fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33934
92511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.3393492511
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.1036685505
Short name T1439
Test name
Test status
Simulation time 221506879 ps
CPU time 0.93 seconds
Started Jun 25 04:58:01 PM PDT 24
Finished Jun 25 04:58:03 PM PDT 24
Peak memory 206504 kb
Host smart-1b6510a8-e06f-4a6b-b897-5a56231ec380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10366
85505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.1036685505
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.3407140596
Short name T2347
Test name
Test status
Simulation time 183229343 ps
CPU time 0.9 seconds
Started Jun 25 04:58:01 PM PDT 24
Finished Jun 25 04:58:03 PM PDT 24
Peak memory 206524 kb
Host smart-a19406ee-93d7-41e6-bf3d-0edc19caf60c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34071
40596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.3407140596
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.3150552440
Short name T1798
Test name
Test status
Simulation time 203217855 ps
CPU time 0.94 seconds
Started Jun 25 04:57:57 PM PDT 24
Finished Jun 25 04:58:00 PM PDT 24
Peak memory 206576 kb
Host smart-4c2fa4dd-d17e-4fb1-8ff1-2aa396e1bd51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31505
52440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.3150552440
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.1400972236
Short name T1769
Test name
Test status
Simulation time 171610607 ps
CPU time 0.78 seconds
Started Jun 25 04:57:58 PM PDT 24
Finished Jun 25 04:58:01 PM PDT 24
Peak memory 206596 kb
Host smart-95cb97a4-3117-40b5-b684-2359decdc71c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14009
72236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.1400972236
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.2468054286
Short name T1092
Test name
Test status
Simulation time 163144425 ps
CPU time 0.83 seconds
Started Jun 25 04:57:55 PM PDT 24
Finished Jun 25 04:57:58 PM PDT 24
Peak memory 206540 kb
Host smart-59239229-0435-455a-b47f-bb62397c3c1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24680
54286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.2468054286
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.1365590693
Short name T2460
Test name
Test status
Simulation time 145547470 ps
CPU time 0.81 seconds
Started Jun 25 04:57:59 PM PDT 24
Finished Jun 25 04:58:02 PM PDT 24
Peak memory 206756 kb
Host smart-1df92473-54dd-4132-83ae-691c719fccdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13655
90693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.1365590693
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.3005108521
Short name T647
Test name
Test status
Simulation time 264197169 ps
CPU time 0.95 seconds
Started Jun 25 04:57:56 PM PDT 24
Finished Jun 25 04:57:59 PM PDT 24
Peak memory 206580 kb
Host smart-a9fb3046-4601-4b22-b49e-b9be306b9034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30051
08521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.3005108521
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.1310213306
Short name T1091
Test name
Test status
Simulation time 11434065465 ps
CPU time 324.34 seconds
Started Jun 25 04:57:58 PM PDT 24
Finished Jun 25 05:03:25 PM PDT 24
Peak memory 206952 kb
Host smart-52f56414-9d11-4a9a-9624-cac7d2e9a460
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1310213306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.1310213306
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.2477927981
Short name T2504
Test name
Test status
Simulation time 158378620 ps
CPU time 0.82 seconds
Started Jun 25 04:57:58 PM PDT 24
Finished Jun 25 04:58:01 PM PDT 24
Peak memory 206580 kb
Host smart-86d5aa7e-5065-41be-bbd6-26385356789d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24779
27981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.2477927981
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.2012746882
Short name T1795
Test name
Test status
Simulation time 184591108 ps
CPU time 0.81 seconds
Started Jun 25 04:57:55 PM PDT 24
Finished Jun 25 04:57:58 PM PDT 24
Peak memory 206576 kb
Host smart-afde96cc-b72b-4ac6-bbe6-00b647def4da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20127
46882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.2012746882
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.1905929851
Short name T1651
Test name
Test status
Simulation time 10833440034 ps
CPU time 296.05 seconds
Started Jun 25 04:58:01 PM PDT 24
Finished Jun 25 05:02:58 PM PDT 24
Peak memory 206952 kb
Host smart-10bef6f2-64bc-4574-84d4-9d0cfd1d795d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19059
29851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.1905929851
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.222587080
Short name T2180
Test name
Test status
Simulation time 3437544502 ps
CPU time 4.42 seconds
Started Jun 25 04:57:54 PM PDT 24
Finished Jun 25 04:58:01 PM PDT 24
Peak memory 206716 kb
Host smart-19f144b3-c091-43f3-8dda-20aa2ab5f744
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=222587080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.222587080
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.930163196
Short name T2412
Test name
Test status
Simulation time 13474748455 ps
CPU time 12.3 seconds
Started Jun 25 04:58:01 PM PDT 24
Finished Jun 25 04:58:14 PM PDT 24
Peak memory 206764 kb
Host smart-068d68fe-e69d-4be7-8ee1-501da8241bea
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=930163196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.930163196
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.1299713699
Short name T912
Test name
Test status
Simulation time 23353441174 ps
CPU time 22.93 seconds
Started Jun 25 04:57:57 PM PDT 24
Finished Jun 25 04:58:22 PM PDT 24
Peak memory 206628 kb
Host smart-98a6af94-213d-4345-90c7-c0063ffe491e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1299713699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.1299713699
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.488903977
Short name T778
Test name
Test status
Simulation time 159628619 ps
CPU time 0.89 seconds
Started Jun 25 04:58:01 PM PDT 24
Finished Jun 25 04:58:03 PM PDT 24
Peak memory 206504 kb
Host smart-6578f127-29a6-4ba6-86ab-ab3208654ef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48890
3977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.488903977
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.1113449193
Short name T1106
Test name
Test status
Simulation time 138573985 ps
CPU time 0.78 seconds
Started Jun 25 04:57:59 PM PDT 24
Finished Jun 25 04:58:02 PM PDT 24
Peak memory 205644 kb
Host smart-94dbdfda-0b90-4c29-9ba1-6e5056d76e58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11134
49193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.1113449193
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.4075029930
Short name T31
Test name
Test status
Simulation time 157405252 ps
CPU time 0.88 seconds
Started Jun 25 04:57:57 PM PDT 24
Finished Jun 25 04:58:00 PM PDT 24
Peak memory 206564 kb
Host smart-5144b68f-d8e2-4c24-8be0-78ff6ba71252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40750
29930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.4075029930
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.146155698
Short name T1064
Test name
Test status
Simulation time 1043118817 ps
CPU time 2.3 seconds
Started Jun 25 04:57:55 PM PDT 24
Finished Jun 25 04:57:59 PM PDT 24
Peak memory 206804 kb
Host smart-6dc9d040-0784-450a-b814-73171508d3c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14615
5698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.146155698
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.3587322450
Short name T558
Test name
Test status
Simulation time 7649124429 ps
CPU time 15.42 seconds
Started Jun 25 04:57:58 PM PDT 24
Finished Jun 25 04:58:15 PM PDT 24
Peak memory 206892 kb
Host smart-53a2f715-8d77-478a-8778-782a195be3ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35873
22450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.3587322450
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.1857127863
Short name T1215
Test name
Test status
Simulation time 438225027 ps
CPU time 1.34 seconds
Started Jun 25 04:58:01 PM PDT 24
Finished Jun 25 04:58:03 PM PDT 24
Peak memory 206600 kb
Host smart-2a42c32b-9908-435a-991c-351e9add4369
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18571
27863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.1857127863
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.2926013826
Short name T1348
Test name
Test status
Simulation time 145823663 ps
CPU time 0.81 seconds
Started Jun 25 04:57:56 PM PDT 24
Finished Jun 25 04:57:58 PM PDT 24
Peak memory 206568 kb
Host smart-5af1c134-5de9-4528-9bc7-fb2bfb00b7e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29260
13826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.2926013826
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.931996683
Short name T2181
Test name
Test status
Simulation time 51448144 ps
CPU time 0.69 seconds
Started Jun 25 04:58:08 PM PDT 24
Finished Jun 25 04:58:11 PM PDT 24
Peak memory 206596 kb
Host smart-05b579b8-5023-4777-98e8-dd91019e1894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93199
6683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.931996683
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.303319811
Short name T1933
Test name
Test status
Simulation time 827708450 ps
CPU time 1.95 seconds
Started Jun 25 04:57:59 PM PDT 24
Finished Jun 25 04:58:03 PM PDT 24
Peak memory 206792 kb
Host smart-a2ae5d2a-b5e1-472f-9376-7c4d838ac732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30331
9811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.303319811
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.510791969
Short name T1264
Test name
Test status
Simulation time 225399551 ps
CPU time 1.52 seconds
Started Jun 25 04:58:06 PM PDT 24
Finished Jun 25 04:58:09 PM PDT 24
Peak memory 206744 kb
Host smart-790d2951-f16e-42b3-81af-387b67f013d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51079
1969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.510791969
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.3431674633
Short name T433
Test name
Test status
Simulation time 256940818 ps
CPU time 0.93 seconds
Started Jun 25 04:58:06 PM PDT 24
Finished Jun 25 04:58:09 PM PDT 24
Peak memory 206528 kb
Host smart-e28f577c-273b-4f88-a7be-69386a112c38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34316
74633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.3431674633
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.4224881134
Short name T1474
Test name
Test status
Simulation time 152495236 ps
CPU time 0.83 seconds
Started Jun 25 04:58:05 PM PDT 24
Finished Jun 25 04:58:08 PM PDT 24
Peak memory 206576 kb
Host smart-9ed96ac1-11de-4333-a133-662bfbefbe51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42248
81134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.4224881134
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.1838472883
Short name T1779
Test name
Test status
Simulation time 254034102 ps
CPU time 0.91 seconds
Started Jun 25 04:58:10 PM PDT 24
Finished Jun 25 04:58:12 PM PDT 24
Peak memory 206456 kb
Host smart-8b7410dc-c65e-48b5-ac03-ae93f249f323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18384
72883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.1838472883
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_invalid_sync.3979892235
Short name T217
Test name
Test status
Simulation time 13812597784 ps
CPU time 94.47 seconds
Started Jun 25 04:58:07 PM PDT 24
Finished Jun 25 04:59:43 PM PDT 24
Peak memory 206884 kb
Host smart-b469ca70-241a-4446-b153-2d267e28af0a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3979892235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_invalid_sync.3979892235
Directory /workspace/11.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.3718130711
Short name T1291
Test name
Test status
Simulation time 194311747 ps
CPU time 0.85 seconds
Started Jun 25 04:58:07 PM PDT 24
Finished Jun 25 04:58:10 PM PDT 24
Peak memory 206508 kb
Host smart-0df90779-5009-4a00-8ad5-59f487b0817a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37181
30711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.3718130711
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.3068138245
Short name T1339
Test name
Test status
Simulation time 23293545406 ps
CPU time 22.03 seconds
Started Jun 25 04:58:07 PM PDT 24
Finished Jun 25 04:58:31 PM PDT 24
Peak memory 206600 kb
Host smart-c65c10bc-bc8f-4b66-b0b5-e3dbd15170cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30681
38245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.3068138245
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.1304328390
Short name T2432
Test name
Test status
Simulation time 3299399001 ps
CPU time 4.68 seconds
Started Jun 25 04:58:06 PM PDT 24
Finished Jun 25 04:58:12 PM PDT 24
Peak memory 206684 kb
Host smart-5ac8fee2-15da-4d5d-8a90-f1234dbe00a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13043
28390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.1304328390
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.2993121746
Short name T368
Test name
Test status
Simulation time 9186024212 ps
CPU time 267.62 seconds
Started Jun 25 04:58:04 PM PDT 24
Finished Jun 25 05:02:34 PM PDT 24
Peak memory 206948 kb
Host smart-db0cb40c-3395-4f92-8d1b-8d4be0f5392f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2993121746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.2993121746
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.555771676
Short name T1543
Test name
Test status
Simulation time 270724091 ps
CPU time 0.97 seconds
Started Jun 25 04:58:04 PM PDT 24
Finished Jun 25 04:58:07 PM PDT 24
Peak memory 206576 kb
Host smart-57d73f49-9e21-41e7-87d3-4cd1276e10ec
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=555771676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.555771676
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.1626483150
Short name T358
Test name
Test status
Simulation time 191259932 ps
CPU time 0.87 seconds
Started Jun 25 04:58:06 PM PDT 24
Finished Jun 25 04:58:09 PM PDT 24
Peak memory 206604 kb
Host smart-53b044f0-904e-4d67-a18a-6f8d394ac3ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16264
83150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.1626483150
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.2457374823
Short name T768
Test name
Test status
Simulation time 5932917525 ps
CPU time 169.83 seconds
Started Jun 25 04:58:05 PM PDT 24
Finished Jun 25 05:00:56 PM PDT 24
Peak memory 206944 kb
Host smart-5a6d27e4-e45c-4392-a923-222e8c355261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24573
74823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.2457374823
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.1593328198
Short name T712
Test name
Test status
Simulation time 5928855271 ps
CPU time 164.8 seconds
Started Jun 25 04:58:06 PM PDT 24
Finished Jun 25 05:00:52 PM PDT 24
Peak memory 206892 kb
Host smart-3d6ce5ed-186b-430a-a7c3-dfb39abe67e0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1593328198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.1593328198
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.2583365040
Short name T1034
Test name
Test status
Simulation time 171529377 ps
CPU time 0.8 seconds
Started Jun 25 04:58:06 PM PDT 24
Finished Jun 25 04:58:09 PM PDT 24
Peak memory 206536 kb
Host smart-636cc232-ed8b-43f7-8c12-6e641cea0a4f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2583365040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.2583365040
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.1307787601
Short name T302
Test name
Test status
Simulation time 151061965 ps
CPU time 0.78 seconds
Started Jun 25 04:58:05 PM PDT 24
Finished Jun 25 04:58:07 PM PDT 24
Peak memory 206592 kb
Host smart-d639ee2d-7288-4a64-9dbf-3c139181e45c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13077
87601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.1307787601
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.2822689424
Short name T2110
Test name
Test status
Simulation time 179115470 ps
CPU time 0.9 seconds
Started Jun 25 04:58:08 PM PDT 24
Finished Jun 25 04:58:11 PM PDT 24
Peak memory 206752 kb
Host smart-37e523e0-0edd-4218-8c35-9e13a8c709fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28226
89424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.2822689424
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.1642894922
Short name T1130
Test name
Test status
Simulation time 177568461 ps
CPU time 0.87 seconds
Started Jun 25 04:58:06 PM PDT 24
Finished Jun 25 04:58:10 PM PDT 24
Peak memory 206580 kb
Host smart-5e89b535-2869-4ed5-8540-de6f1212a425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16428
94922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.1642894922
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.1514616562
Short name T2026
Test name
Test status
Simulation time 150073938 ps
CPU time 0.76 seconds
Started Jun 25 04:58:05 PM PDT 24
Finished Jun 25 04:58:07 PM PDT 24
Peak memory 206504 kb
Host smart-1f3d7d76-56cf-43a1-bf31-504ead3d53de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15146
16562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.1514616562
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.3483018202
Short name T418
Test name
Test status
Simulation time 147522930 ps
CPU time 0.76 seconds
Started Jun 25 04:58:07 PM PDT 24
Finished Jun 25 04:58:09 PM PDT 24
Peak memory 206576 kb
Host smart-d8c2c53e-e060-4e56-be55-303b2b3a350c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34830
18202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.3483018202
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.2152922128
Short name T466
Test name
Test status
Simulation time 254305819 ps
CPU time 1 seconds
Started Jun 25 04:58:07 PM PDT 24
Finished Jun 25 04:58:10 PM PDT 24
Peak memory 206500 kb
Host smart-d9759c2a-5635-484f-8ac7-57b99431f1b0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2152922128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.2152922128
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.3445234869
Short name T546
Test name
Test status
Simulation time 140515511 ps
CPU time 0.76 seconds
Started Jun 25 04:58:09 PM PDT 24
Finished Jun 25 04:58:12 PM PDT 24
Peak memory 206464 kb
Host smart-3215b3fa-106a-460d-b452-e10f88f2dd60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34452
34869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.3445234869
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.1434715317
Short name T2166
Test name
Test status
Simulation time 53267067 ps
CPU time 0.67 seconds
Started Jun 25 04:58:06 PM PDT 24
Finished Jun 25 04:58:08 PM PDT 24
Peak memory 206572 kb
Host smart-8e83dbc4-d878-4f4c-b73e-74364e254a40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14347
15317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.1434715317
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.441646817
Short name T1900
Test name
Test status
Simulation time 198828226 ps
CPU time 0.9 seconds
Started Jun 25 04:58:08 PM PDT 24
Finished Jun 25 04:58:11 PM PDT 24
Peak memory 206520 kb
Host smart-87cf9575-e6aa-4056-8b76-257e0f0b4453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44164
6817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.441646817
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.4105537416
Short name T304
Test name
Test status
Simulation time 217437798 ps
CPU time 0.91 seconds
Started Jun 25 04:58:06 PM PDT 24
Finished Jun 25 04:58:09 PM PDT 24
Peak memory 206568 kb
Host smart-e1a7dcad-3e7c-4baa-981e-ce826d802dd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41055
37416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.4105537416
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.1415852421
Short name T1205
Test name
Test status
Simulation time 161052292 ps
CPU time 0.77 seconds
Started Jun 25 04:58:04 PM PDT 24
Finished Jun 25 04:58:07 PM PDT 24
Peak memory 206880 kb
Host smart-4b8d4a35-4901-487a-8d10-f50911924c30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14158
52421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.1415852421
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.2770879609
Short name T1272
Test name
Test status
Simulation time 214497651 ps
CPU time 0.9 seconds
Started Jun 25 04:58:05 PM PDT 24
Finished Jun 25 04:58:08 PM PDT 24
Peak memory 206500 kb
Host smart-70ae2376-63f9-465c-9a8d-c5ef628dca3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27708
79609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.2770879609
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.3914855877
Short name T2106
Test name
Test status
Simulation time 147704505 ps
CPU time 0.79 seconds
Started Jun 25 04:58:06 PM PDT 24
Finished Jun 25 04:58:09 PM PDT 24
Peak memory 206576 kb
Host smart-d5f628dd-6de6-469d-948f-06ae08d1d1b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39148
55877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.3914855877
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.1894273086
Short name T519
Test name
Test status
Simulation time 153221613 ps
CPU time 0.77 seconds
Started Jun 25 04:58:05 PM PDT 24
Finished Jun 25 04:58:08 PM PDT 24
Peak memory 206572 kb
Host smart-b402dd83-1116-4a8b-8428-5d682b9ba3b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18942
73086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.1894273086
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.758024702
Short name T49
Test name
Test status
Simulation time 152259011 ps
CPU time 0.77 seconds
Started Jun 25 04:58:06 PM PDT 24
Finished Jun 25 04:58:08 PM PDT 24
Peak memory 206592 kb
Host smart-88e72698-6d6b-4623-abb7-ce4bf3834e2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75802
4702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.758024702
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.3250504925
Short name T341
Test name
Test status
Simulation time 206397396 ps
CPU time 0.88 seconds
Started Jun 25 04:58:06 PM PDT 24
Finished Jun 25 04:58:09 PM PDT 24
Peak memory 206528 kb
Host smart-c8d0ec14-cad7-4cd5-90df-56df7ee508b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32505
04925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.3250504925
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.1182138363
Short name T1005
Test name
Test status
Simulation time 5070295595 ps
CPU time 34.73 seconds
Started Jun 25 04:58:09 PM PDT 24
Finished Jun 25 04:58:46 PM PDT 24
Peak memory 206748 kb
Host smart-c15bf125-bd15-43f4-875d-76da859ad8a7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1182138363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.1182138363
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.2438049705
Short name T105
Test name
Test status
Simulation time 182840931 ps
CPU time 0.82 seconds
Started Jun 25 04:58:06 PM PDT 24
Finished Jun 25 04:58:09 PM PDT 24
Peak memory 206604 kb
Host smart-7dbdb632-72cb-4879-8d88-bbc182a8b325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24380
49705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.2438049705
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.702392593
Short name T1982
Test name
Test status
Simulation time 215460226 ps
CPU time 0.84 seconds
Started Jun 25 04:58:10 PM PDT 24
Finished Jun 25 04:58:12 PM PDT 24
Peak memory 206552 kb
Host smart-d7241321-7eba-4375-98c4-6ecbc4796036
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70239
2593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.702392593
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.1101703467
Short name T2251
Test name
Test status
Simulation time 7858716841 ps
CPU time 74.48 seconds
Started Jun 25 04:58:10 PM PDT 24
Finished Jun 25 04:59:26 PM PDT 24
Peak memory 206884 kb
Host smart-c89a3e8f-81c3-43dd-87c0-4dc4d88edb11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11017
03467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.1101703467
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.4038558979
Short name T363
Test name
Test status
Simulation time 3829259372 ps
CPU time 5.35 seconds
Started Jun 25 04:58:05 PM PDT 24
Finished Jun 25 04:58:13 PM PDT 24
Peak memory 206692 kb
Host smart-42dc661b-8a91-48af-90ba-ca91fb86ec9e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4038558979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.4038558979
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.2531432470
Short name T1287
Test name
Test status
Simulation time 13333556292 ps
CPU time 12.26 seconds
Started Jun 25 04:58:08 PM PDT 24
Finished Jun 25 04:58:22 PM PDT 24
Peak memory 206860 kb
Host smart-7d090025-c2d3-4c8d-8bed-9eec4e22f782
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2531432470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.2531432470
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.1070698929
Short name T2291
Test name
Test status
Simulation time 23319167887 ps
CPU time 22.56 seconds
Started Jun 25 04:58:08 PM PDT 24
Finished Jun 25 04:58:33 PM PDT 24
Peak memory 206716 kb
Host smart-3be6d4c9-1c89-482b-9b54-22d67ea524c4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1070698929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.1070698929
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.421557224
Short name T2312
Test name
Test status
Simulation time 158094280 ps
CPU time 0.8 seconds
Started Jun 25 04:58:05 PM PDT 24
Finished Jun 25 04:58:07 PM PDT 24
Peak memory 206520 kb
Host smart-d00b0dba-5837-4a8e-859b-b26cb22d52e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42155
7224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.421557224
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.2242913965
Short name T2170
Test name
Test status
Simulation time 174234426 ps
CPU time 0.79 seconds
Started Jun 25 04:58:10 PM PDT 24
Finished Jun 25 04:58:12 PM PDT 24
Peak memory 206460 kb
Host smart-429372c2-08df-41ab-b151-af203749237e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22429
13965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.2242913965
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.3394260926
Short name T2255
Test name
Test status
Simulation time 180593017 ps
CPU time 0.78 seconds
Started Jun 25 04:58:06 PM PDT 24
Finished Jun 25 04:58:09 PM PDT 24
Peak memory 206596 kb
Host smart-a4fcf544-d665-438b-a230-75fbed275bde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33942
60926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.3394260926
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.641766028
Short name T1258
Test name
Test status
Simulation time 400224483 ps
CPU time 1.2 seconds
Started Jun 25 04:58:06 PM PDT 24
Finished Jun 25 04:58:10 PM PDT 24
Peak memory 206516 kb
Host smart-cc1d8b2f-f23a-4506-9fa8-f6d1286b657c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64176
6028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.641766028
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.1341038256
Short name T673
Test name
Test status
Simulation time 9330222088 ps
CPU time 17.23 seconds
Started Jun 25 04:58:06 PM PDT 24
Finished Jun 25 04:58:25 PM PDT 24
Peak memory 206864 kb
Host smart-91fb8d24-ac79-473a-9309-d8cbbff06467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13410
38256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.1341038256
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.4045367178
Short name T338
Test name
Test status
Simulation time 423894229 ps
CPU time 1.29 seconds
Started Jun 25 04:58:06 PM PDT 24
Finished Jun 25 04:58:09 PM PDT 24
Peak memory 206572 kb
Host smart-7f06cdef-54bf-4a24-87ae-af6a38720615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40453
67178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.4045367178
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.3471002450
Short name T653
Test name
Test status
Simulation time 156526364 ps
CPU time 0.8 seconds
Started Jun 25 04:58:10 PM PDT 24
Finished Jun 25 04:58:12 PM PDT 24
Peak memory 206456 kb
Host smart-424a51c1-fbf7-447e-a256-07e028e9132e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34710
02450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.3471002450
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.1601999623
Short name T2136
Test name
Test status
Simulation time 75252482 ps
CPU time 0.7 seconds
Started Jun 25 04:58:15 PM PDT 24
Finished Jun 25 04:58:17 PM PDT 24
Peak memory 206564 kb
Host smart-b65d7e8a-0cd3-4db9-9608-b0e43b43f8b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16019
99623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.1601999623
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.1907377725
Short name T2426
Test name
Test status
Simulation time 862130039 ps
CPU time 2.14 seconds
Started Jun 25 04:58:04 PM PDT 24
Finished Jun 25 04:58:07 PM PDT 24
Peak memory 206672 kb
Host smart-e244b81c-6c60-4049-bd9e-f772f2d05f3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19073
77725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.1907377725
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.3300225123
Short name T2329
Test name
Test status
Simulation time 187961267 ps
CPU time 1.34 seconds
Started Jun 25 04:58:16 PM PDT 24
Finished Jun 25 04:58:20 PM PDT 24
Peak memory 206756 kb
Host smart-3403e6c1-8051-4526-b49c-080269679701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33002
25123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.3300225123
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.4083235903
Short name T1346
Test name
Test status
Simulation time 204302037 ps
CPU time 0.91 seconds
Started Jun 25 04:58:17 PM PDT 24
Finished Jun 25 04:58:20 PM PDT 24
Peak memory 206496 kb
Host smart-690aa285-ec50-4f17-a77d-e931287ec3cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40832
35903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.4083235903
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.560821333
Short name T1549
Test name
Test status
Simulation time 138569809 ps
CPU time 0.76 seconds
Started Jun 25 04:58:16 PM PDT 24
Finished Jun 25 04:58:19 PM PDT 24
Peak memory 206588 kb
Host smart-25653eab-45a9-48bc-ad37-a4d6215d5336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56082
1333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.560821333
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.3183257988
Short name T2379
Test name
Test status
Simulation time 247252004 ps
CPU time 0.97 seconds
Started Jun 25 04:58:16 PM PDT 24
Finished Jun 25 04:58:19 PM PDT 24
Peak memory 206580 kb
Host smart-205c8dc5-b392-4a4d-9fdd-32e956e061a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31832
57988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.3183257988
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.3148645150
Short name T1471
Test name
Test status
Simulation time 220119972 ps
CPU time 0.84 seconds
Started Jun 25 04:58:15 PM PDT 24
Finished Jun 25 04:58:17 PM PDT 24
Peak memory 206572 kb
Host smart-bb74cf84-e8e2-4d77-88a1-f1adae03b4c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31486
45150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.3148645150
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.185084857
Short name T1014
Test name
Test status
Simulation time 23363702625 ps
CPU time 21.55 seconds
Started Jun 25 04:58:13 PM PDT 24
Finished Jun 25 04:58:35 PM PDT 24
Peak memory 206672 kb
Host smart-b2a9ecb7-00c8-4f72-ab2f-a2995ad29722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18508
4857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.185084857
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.2502106762
Short name T1822
Test name
Test status
Simulation time 3317767926 ps
CPU time 3.86 seconds
Started Jun 25 04:58:15 PM PDT 24
Finished Jun 25 04:58:21 PM PDT 24
Peak memory 206712 kb
Host smart-9a767f14-c733-44a3-8569-90bb9ec27441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25021
06762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.2502106762
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.1279084367
Short name T512
Test name
Test status
Simulation time 8994770278 ps
CPU time 244.03 seconds
Started Jun 25 04:58:17 PM PDT 24
Finished Jun 25 05:02:23 PM PDT 24
Peak memory 206876 kb
Host smart-0f325301-9037-4482-a373-85ef935295ad
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1279084367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.1279084367
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.3495238632
Short name T416
Test name
Test status
Simulation time 240455051 ps
CPU time 0.94 seconds
Started Jun 25 04:58:18 PM PDT 24
Finished Jun 25 04:58:21 PM PDT 24
Peak memory 206504 kb
Host smart-b6880aff-6baf-4408-8835-22aba2808a85
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3495238632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.3495238632
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.3489599260
Short name T1416
Test name
Test status
Simulation time 207590668 ps
CPU time 0.9 seconds
Started Jun 25 04:58:15 PM PDT 24
Finished Jun 25 04:58:18 PM PDT 24
Peak memory 206604 kb
Host smart-6dbac86e-add4-4ecb-af3e-57e9a59ece66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34895
99260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.3489599260
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.1604827052
Short name T1198
Test name
Test status
Simulation time 8521290405 ps
CPU time 63.62 seconds
Started Jun 25 04:58:14 PM PDT 24
Finished Jun 25 04:59:20 PM PDT 24
Peak memory 206888 kb
Host smart-4b8362c1-19cc-4fb6-a234-dced073f9822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16048
27052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.1604827052
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.1737446524
Short name T1851
Test name
Test status
Simulation time 10348625818 ps
CPU time 299.55 seconds
Started Jun 25 04:58:14 PM PDT 24
Finished Jun 25 05:03:15 PM PDT 24
Peak memory 206892 kb
Host smart-e9deea52-56c8-4be9-8cdb-b7ff60271dfd
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1737446524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.1737446524
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.251870469
Short name T307
Test name
Test status
Simulation time 156925384 ps
CPU time 0.88 seconds
Started Jun 25 04:58:16 PM PDT 24
Finished Jun 25 04:58:19 PM PDT 24
Peak memory 206572 kb
Host smart-bdc1b805-72d7-4d4e-a019-6cfff78a84bb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=251870469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.251870469
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.472747206
Short name T1368
Test name
Test status
Simulation time 136919350 ps
CPU time 0.74 seconds
Started Jun 25 04:58:13 PM PDT 24
Finished Jun 25 04:58:14 PM PDT 24
Peak memory 206484 kb
Host smart-cbce642c-a508-4238-9214-5f89a6ea4e72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47274
7206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.472747206
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.358397455
Short name T1308
Test name
Test status
Simulation time 191623187 ps
CPU time 0.81 seconds
Started Jun 25 04:58:16 PM PDT 24
Finished Jun 25 04:58:18 PM PDT 24
Peak memory 206484 kb
Host smart-b4d17102-0045-41e0-a474-6c30fb7ac526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35839
7455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.358397455
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.2337581895
Short name T2253
Test name
Test status
Simulation time 163039205 ps
CPU time 0.82 seconds
Started Jun 25 04:58:14 PM PDT 24
Finished Jun 25 04:58:17 PM PDT 24
Peak memory 206500 kb
Host smart-cd063cbe-673d-4f41-8549-cba1f6a7f297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23375
81895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.2337581895
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.1677844581
Short name T420
Test name
Test status
Simulation time 196196976 ps
CPU time 0.81 seconds
Started Jun 25 04:58:17 PM PDT 24
Finished Jun 25 04:58:19 PM PDT 24
Peak memory 206576 kb
Host smart-9f839feb-6b93-428c-a478-910549accd6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16778
44581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.1677844581
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.2521369411
Short name T1941
Test name
Test status
Simulation time 152350901 ps
CPU time 0.8 seconds
Started Jun 25 04:58:15 PM PDT 24
Finished Jun 25 04:58:18 PM PDT 24
Peak memory 206592 kb
Host smart-1e886d0c-dec2-444b-b7fe-b3f10aa8892b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25213
69411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.2521369411
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.746345328
Short name T2396
Test name
Test status
Simulation time 199299754 ps
CPU time 0.88 seconds
Started Jun 25 04:58:12 PM PDT 24
Finished Jun 25 04:58:14 PM PDT 24
Peak memory 206572 kb
Host smart-664b5eb3-8d9f-424d-84fa-eb44eda8fa3e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=746345328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.746345328
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.1834415338
Short name T601
Test name
Test status
Simulation time 182082487 ps
CPU time 0.75 seconds
Started Jun 25 04:58:14 PM PDT 24
Finished Jun 25 04:58:16 PM PDT 24
Peak memory 206524 kb
Host smart-36678574-c17b-4d37-a9b5-1019b3414a9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18344
15338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.1834415338
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.1699247572
Short name T1084
Test name
Test status
Simulation time 42918764 ps
CPU time 0.67 seconds
Started Jun 25 04:58:14 PM PDT 24
Finished Jun 25 04:58:16 PM PDT 24
Peak memory 206568 kb
Host smart-dcd03531-a516-492a-88de-421762146d75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16992
47572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.1699247572
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.462737757
Short name T175
Test name
Test status
Simulation time 11571499801 ps
CPU time 27.81 seconds
Started Jun 25 04:58:16 PM PDT 24
Finished Jun 25 04:58:46 PM PDT 24
Peak memory 206980 kb
Host smart-6ff293ef-5c5b-4d21-87be-6b7769e946bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46273
7757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.462737757
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.106416715
Short name T1898
Test name
Test status
Simulation time 204049915 ps
CPU time 0.88 seconds
Started Jun 25 04:58:14 PM PDT 24
Finished Jun 25 04:58:17 PM PDT 24
Peak memory 206480 kb
Host smart-6ae4ab71-b608-4256-abfb-e81d1daff67e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10641
6715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.106416715
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.1212597569
Short name T671
Test name
Test status
Simulation time 162302407 ps
CPU time 0.77 seconds
Started Jun 25 04:58:16 PM PDT 24
Finished Jun 25 04:58:19 PM PDT 24
Peak memory 206508 kb
Host smart-6cba875a-dbec-4cb7-92ad-9544ffef8e0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12125
97569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.1212597569
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.3537215458
Short name T830
Test name
Test status
Simulation time 233153125 ps
CPU time 0.93 seconds
Started Jun 25 04:58:16 PM PDT 24
Finished Jun 25 04:58:19 PM PDT 24
Peak memory 206596 kb
Host smart-8148dc37-d02f-49bc-b979-d8f5cc1a8b63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35372
15458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.3537215458
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.4164318900
Short name T529
Test name
Test status
Simulation time 158089674 ps
CPU time 0.77 seconds
Started Jun 25 04:58:16 PM PDT 24
Finished Jun 25 04:58:18 PM PDT 24
Peak memory 206520 kb
Host smart-60bad378-8afb-4671-a7f0-adb2efafdcb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41643
18900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.4164318900
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.3344678146
Short name T1986
Test name
Test status
Simulation time 140967466 ps
CPU time 0.83 seconds
Started Jun 25 04:58:15 PM PDT 24
Finished Jun 25 04:58:18 PM PDT 24
Peak memory 206504 kb
Host smart-a2b44032-47d6-45e4-b2ee-701c1efcef4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33446
78146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.3344678146
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.3601545240
Short name T2375
Test name
Test status
Simulation time 163672495 ps
CPU time 0.79 seconds
Started Jun 25 04:58:13 PM PDT 24
Finished Jun 25 04:58:15 PM PDT 24
Peak memory 206572 kb
Host smart-571f0208-cfec-44a6-9b02-5e6480df41e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36015
45240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.3601545240
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.1446061656
Short name T1427
Test name
Test status
Simulation time 230993337 ps
CPU time 0.9 seconds
Started Jun 25 04:58:18 PM PDT 24
Finished Jun 25 04:58:21 PM PDT 24
Peak memory 206584 kb
Host smart-ba9a28a9-e20a-4c08-bd4d-aadb0bc80f82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14460
61656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.1446061656
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.1922936304
Short name T326
Test name
Test status
Simulation time 8340515992 ps
CPU time 236.59 seconds
Started Jun 25 04:58:14 PM PDT 24
Finished Jun 25 05:02:12 PM PDT 24
Peak memory 206972 kb
Host smart-5388b439-89b0-4a1c-a0cc-1a09dffd1e37
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1922936304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.1922936304
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.1594454044
Short name T1847
Test name
Test status
Simulation time 202837806 ps
CPU time 0.89 seconds
Started Jun 25 04:58:15 PM PDT 24
Finished Jun 25 04:58:18 PM PDT 24
Peak memory 206508 kb
Host smart-35f417d1-a166-4579-98e0-ad25618d1662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15944
54044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.1594454044
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.1459596266
Short name T314
Test name
Test status
Simulation time 171633537 ps
CPU time 0.91 seconds
Started Jun 25 04:58:18 PM PDT 24
Finished Jun 25 04:58:21 PM PDT 24
Peak memory 206572 kb
Host smart-e28bb11f-b7f0-452d-8bc1-0bc32daadebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14595
96266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.1459596266
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.2258071672
Short name T931
Test name
Test status
Simulation time 11175171610 ps
CPU time 103.3 seconds
Started Jun 25 04:58:15 PM PDT 24
Finished Jun 25 05:00:00 PM PDT 24
Peak memory 206916 kb
Host smart-65c7f095-2724-420a-af1e-0e173603f382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22580
71672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.2258071672
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.2806268673
Short name T998
Test name
Test status
Simulation time 3826778495 ps
CPU time 4.32 seconds
Started Jun 25 04:58:19 PM PDT 24
Finished Jun 25 04:58:24 PM PDT 24
Peak memory 206856 kb
Host smart-43c14706-5e0c-4e78-ae6c-6f460a5e74bc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2806268673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.2806268673
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.1458991247
Short name T1262
Test name
Test status
Simulation time 13418069881 ps
CPU time 12.9 seconds
Started Jun 25 04:58:13 PM PDT 24
Finished Jun 25 04:58:27 PM PDT 24
Peak memory 206884 kb
Host smart-1bde0351-c60a-47d8-9e5b-544a0113e6fb
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1458991247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.1458991247
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.3372215563
Short name T432
Test name
Test status
Simulation time 210025570 ps
CPU time 0.85 seconds
Started Jun 25 04:58:16 PM PDT 24
Finished Jun 25 04:58:19 PM PDT 24
Peak memory 206596 kb
Host smart-aadb1d29-8dc4-454f-a578-36c59e66d8c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33722
15563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.3372215563
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.3542196568
Short name T431
Test name
Test status
Simulation time 162161013 ps
CPU time 0.78 seconds
Started Jun 25 04:58:18 PM PDT 24
Finished Jun 25 04:58:21 PM PDT 24
Peak memory 206572 kb
Host smart-a4b63558-cefc-4001-a9a1-765fd9906c9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35421
96568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.3542196568
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.2771858445
Short name T155
Test name
Test status
Simulation time 236110597 ps
CPU time 0.93 seconds
Started Jun 25 04:58:14 PM PDT 24
Finished Jun 25 04:58:16 PM PDT 24
Peak memory 206568 kb
Host smart-b3e8bf68-4063-42a9-938e-4eaa9316ee32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27718
58445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.2771858445
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.684190665
Short name T1889
Test name
Test status
Simulation time 420378721 ps
CPU time 1.17 seconds
Started Jun 25 04:58:14 PM PDT 24
Finished Jun 25 04:58:16 PM PDT 24
Peak memory 206588 kb
Host smart-03c04f7b-9869-4ea6-a6bf-1a3f6091261b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68419
0665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.684190665
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.1480613376
Short name T890
Test name
Test status
Simulation time 13664338869 ps
CPU time 27.06 seconds
Started Jun 25 04:58:15 PM PDT 24
Finished Jun 25 04:58:44 PM PDT 24
Peak memory 206836 kb
Host smart-3eccee2e-54b5-4501-8e1a-4211f46fc6ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14806
13376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.1480613376
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.2061892573
Short name T488
Test name
Test status
Simulation time 411676917 ps
CPU time 1.28 seconds
Started Jun 25 04:58:18 PM PDT 24
Finished Jun 25 04:58:21 PM PDT 24
Peak memory 206560 kb
Host smart-7345ec15-563e-4a81-904a-900ec79e43ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20618
92573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.2061892573
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.3745594013
Short name T1955
Test name
Test status
Simulation time 137123907 ps
CPU time 0.76 seconds
Started Jun 25 04:58:16 PM PDT 24
Finished Jun 25 04:58:19 PM PDT 24
Peak memory 206492 kb
Host smart-83644f7b-a55e-4e8c-aa57-237b322ab606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37455
94013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.3745594013
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.625931585
Short name T2479
Test name
Test status
Simulation time 32616463 ps
CPU time 0.64 seconds
Started Jun 25 04:58:16 PM PDT 24
Finished Jun 25 04:58:18 PM PDT 24
Peak memory 206604 kb
Host smart-6a071e1e-86e1-4ca2-b84e-ec0fd0c55a31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62593
1585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.625931585
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.2490028479
Short name T2073
Test name
Test status
Simulation time 878493832 ps
CPU time 2 seconds
Started Jun 25 04:58:16 PM PDT 24
Finished Jun 25 04:58:20 PM PDT 24
Peak memory 206752 kb
Host smart-9faadfa4-21b8-4950-8b00-790b20089789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24900
28479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.2490028479
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.2089728535
Short name T1938
Test name
Test status
Simulation time 301251156 ps
CPU time 1.81 seconds
Started Jun 25 04:58:13 PM PDT 24
Finished Jun 25 04:58:16 PM PDT 24
Peak memory 206788 kb
Host smart-da92ba97-3baa-48db-8f7e-100b98c3bfc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20897
28535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.2089728535
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.407511538
Short name T728
Test name
Test status
Simulation time 251327032 ps
CPU time 0.89 seconds
Started Jun 25 04:58:25 PM PDT 24
Finished Jun 25 04:58:27 PM PDT 24
Peak memory 206604 kb
Host smart-f866fb8e-47bd-4b44-8699-460e9bb6bab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40751
1538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.407511538
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.2560521347
Short name T2126
Test name
Test status
Simulation time 158438376 ps
CPU time 0.75 seconds
Started Jun 25 04:58:23 PM PDT 24
Finished Jun 25 04:58:25 PM PDT 24
Peak memory 206568 kb
Host smart-7a4f9151-9f03-49e3-a764-04a0903e6b6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25605
21347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.2560521347
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.480722576
Short name T331
Test name
Test status
Simulation time 162009357 ps
CPU time 0.86 seconds
Started Jun 25 04:58:14 PM PDT 24
Finished Jun 25 04:58:17 PM PDT 24
Peak memory 206596 kb
Host smart-5aa595fe-12ba-40f0-ae9c-2710fcec8235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48072
2576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.480722576
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.1206783431
Short name T994
Test name
Test status
Simulation time 210130121 ps
CPU time 0.87 seconds
Started Jun 25 04:58:15 PM PDT 24
Finished Jun 25 04:58:17 PM PDT 24
Peak memory 206504 kb
Host smart-e65f1a58-f2e7-448d-945e-ebbc961b38bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12067
83431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.1206783431
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.3064074307
Short name T1015
Test name
Test status
Simulation time 23325606443 ps
CPU time 27.87 seconds
Started Jun 25 04:58:13 PM PDT 24
Finished Jun 25 04:58:42 PM PDT 24
Peak memory 206688 kb
Host smart-47b4ce15-4f5f-4994-ac05-01e47ebb801f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30640
74307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.3064074307
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.2649824833
Short name T708
Test name
Test status
Simulation time 3364220738 ps
CPU time 3.71 seconds
Started Jun 25 04:58:17 PM PDT 24
Finished Jun 25 04:58:23 PM PDT 24
Peak memory 206628 kb
Host smart-38411c77-a123-4a0c-9d9b-83d3eefcb75a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26498
24833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.2649824833
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.532862712
Short name T917
Test name
Test status
Simulation time 9544028640 ps
CPU time 71.77 seconds
Started Jun 25 04:58:21 PM PDT 24
Finished Jun 25 04:59:34 PM PDT 24
Peak memory 206884 kb
Host smart-e226319b-d7a6-4e6a-9777-16dd20f8a5da
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=532862712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.532862712
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.2158358860
Short name T2361
Test name
Test status
Simulation time 264665745 ps
CPU time 1.03 seconds
Started Jun 25 04:58:22 PM PDT 24
Finished Jun 25 04:58:25 PM PDT 24
Peak memory 206572 kb
Host smart-72a98930-0339-4727-88df-82720f0f2caa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2158358860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.2158358860
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.4292351443
Short name T1977
Test name
Test status
Simulation time 269772752 ps
CPU time 0.97 seconds
Started Jun 25 04:58:17 PM PDT 24
Finished Jun 25 04:58:20 PM PDT 24
Peak memory 206512 kb
Host smart-5207a018-3dec-4323-bbde-96dfbc93619e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42923
51443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.4292351443
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.3908871294
Short name T565
Test name
Test status
Simulation time 8570453677 ps
CPU time 61.93 seconds
Started Jun 25 04:58:22 PM PDT 24
Finished Jun 25 04:59:26 PM PDT 24
Peak memory 206860 kb
Host smart-f61d95e5-c8b0-412a-b9a2-47d83bc56ac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39088
71294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.3908871294
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.4190171866
Short name T1454
Test name
Test status
Simulation time 12764466165 ps
CPU time 115.06 seconds
Started Jun 25 04:58:23 PM PDT 24
Finished Jun 25 05:00:20 PM PDT 24
Peak memory 206944 kb
Host smart-e1a06b66-fe9c-4246-bc9e-b6d44ff88037
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4190171866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.4190171866
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.2277473480
Short name T750
Test name
Test status
Simulation time 159666098 ps
CPU time 0.89 seconds
Started Jun 25 04:58:22 PM PDT 24
Finished Jun 25 04:58:24 PM PDT 24
Peak memory 206520 kb
Host smart-9ae8e049-b50e-4295-aa00-8a011a30acf0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2277473480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.2277473480
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.4021016162
Short name T1848
Test name
Test status
Simulation time 148392385 ps
CPU time 0.8 seconds
Started Jun 25 04:58:16 PM PDT 24
Finished Jun 25 04:58:19 PM PDT 24
Peak memory 206508 kb
Host smart-7fb78f52-cf6f-4e90-9bc4-228853c29638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40210
16162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.4021016162
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.852392901
Short name T497
Test name
Test status
Simulation time 216026519 ps
CPU time 0.87 seconds
Started Jun 25 04:58:23 PM PDT 24
Finished Jun 25 04:58:26 PM PDT 24
Peak memory 206476 kb
Host smart-25df3744-1fde-456a-b672-cdac760c6beb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85239
2901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.852392901
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.251350623
Short name T1606
Test name
Test status
Simulation time 181011269 ps
CPU time 0.8 seconds
Started Jun 25 04:58:23 PM PDT 24
Finished Jun 25 04:58:26 PM PDT 24
Peak memory 206600 kb
Host smart-2267bc7a-49eb-405c-9a92-1a787024915c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25135
0623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.251350623
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.3203843731
Short name T682
Test name
Test status
Simulation time 170444275 ps
CPU time 0.84 seconds
Started Jun 25 04:58:26 PM PDT 24
Finished Jun 25 04:58:28 PM PDT 24
Peak memory 206572 kb
Host smart-6850aee2-cd20-4d25-816e-a100772374de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32038
43731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.3203843731
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.2039680102
Short name T1351
Test name
Test status
Simulation time 151948922 ps
CPU time 0.78 seconds
Started Jun 25 04:58:23 PM PDT 24
Finished Jun 25 04:58:26 PM PDT 24
Peak memory 206592 kb
Host smart-7aa26730-f44c-4d46-95c5-3a16d0856bc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20396
80102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.2039680102
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.3896823459
Short name T898
Test name
Test status
Simulation time 235859828 ps
CPU time 0.98 seconds
Started Jun 25 04:58:20 PM PDT 24
Finished Jun 25 04:58:22 PM PDT 24
Peak memory 206508 kb
Host smart-1dbc5ddc-a038-473d-839f-687717f05fc2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3896823459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.3896823459
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.3170227863
Short name T875
Test name
Test status
Simulation time 175585481 ps
CPU time 0.83 seconds
Started Jun 25 04:58:23 PM PDT 24
Finished Jun 25 04:58:26 PM PDT 24
Peak memory 206508 kb
Host smart-4a807a57-fe19-4559-a83f-c6440861ee25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31702
27863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.3170227863
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.2733496090
Short name T40
Test name
Test status
Simulation time 32030346 ps
CPU time 0.64 seconds
Started Jun 25 04:58:21 PM PDT 24
Finished Jun 25 04:58:23 PM PDT 24
Peak memory 206492 kb
Host smart-8b7a57f9-bd15-4736-a4b6-a8aed96c1a9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27334
96090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.2733496090
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.2501523185
Short name T1114
Test name
Test status
Simulation time 19050528201 ps
CPU time 42.05 seconds
Started Jun 25 04:58:21 PM PDT 24
Finished Jun 25 04:59:05 PM PDT 24
Peak memory 206952 kb
Host smart-c257095e-79a4-4d43-a22f-1dfd8d7e606b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25015
23185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.2501523185
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.220319966
Short name T1083
Test name
Test status
Simulation time 165656466 ps
CPU time 0.84 seconds
Started Jun 25 04:58:27 PM PDT 24
Finished Jun 25 04:58:29 PM PDT 24
Peak memory 206480 kb
Host smart-5cb8849e-3020-4bb5-bd2b-0028c5c3f556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22031
9966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.220319966
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.901745021
Short name T1120
Test name
Test status
Simulation time 200853989 ps
CPU time 0.83 seconds
Started Jun 25 04:58:27 PM PDT 24
Finished Jun 25 04:58:29 PM PDT 24
Peak memory 206568 kb
Host smart-decfb309-fdcb-407b-89bc-241a0029763f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90174
5021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.901745021
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.1803005423
Short name T310
Test name
Test status
Simulation time 205101514 ps
CPU time 0.84 seconds
Started Jun 25 04:58:27 PM PDT 24
Finished Jun 25 04:58:29 PM PDT 24
Peak memory 206524 kb
Host smart-aaf71a8e-e34d-44b0-8275-8f7be9bab6b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18030
05423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.1803005423
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.2409978342
Short name T2278
Test name
Test status
Simulation time 153221241 ps
CPU time 0.82 seconds
Started Jun 25 04:58:23 PM PDT 24
Finished Jun 25 04:58:26 PM PDT 24
Peak memory 206508 kb
Host smart-72c0fd7c-34a8-474b-af62-d9e01c524fa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24099
78342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.2409978342
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.73358356
Short name T1217
Test name
Test status
Simulation time 219698470 ps
CPU time 0.9 seconds
Started Jun 25 04:58:23 PM PDT 24
Finished Jun 25 04:58:26 PM PDT 24
Peak memory 206596 kb
Host smart-bc80543c-b546-4e5b-881e-ed7b0cad96f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73358
356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.73358356
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.468316427
Short name T2403
Test name
Test status
Simulation time 150482216 ps
CPU time 0.8 seconds
Started Jun 25 04:58:22 PM PDT 24
Finished Jun 25 04:58:24 PM PDT 24
Peak memory 206508 kb
Host smart-c15f3225-61de-448d-96f0-b7207d68940c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46831
6427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.468316427
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.2202189595
Short name T2105
Test name
Test status
Simulation time 159954589 ps
CPU time 0.86 seconds
Started Jun 25 04:58:22 PM PDT 24
Finished Jun 25 04:58:25 PM PDT 24
Peak memory 206580 kb
Host smart-d074b9e5-fb44-4f9b-a1b6-5358a8172284
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22021
89595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.2202189595
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.4045698509
Short name T915
Test name
Test status
Simulation time 274219590 ps
CPU time 1.01 seconds
Started Jun 25 04:58:26 PM PDT 24
Finished Jun 25 04:58:29 PM PDT 24
Peak memory 206604 kb
Host smart-ba8c6882-2b44-407a-9fc8-80e0520404ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40456
98509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.4045698509
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.949794469
Short name T1659
Test name
Test status
Simulation time 3122474606 ps
CPU time 23.28 seconds
Started Jun 25 04:58:26 PM PDT 24
Finished Jun 25 04:58:50 PM PDT 24
Peak memory 206864 kb
Host smart-4c5b182b-ba8e-45fc-9233-3e51516f9129
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=949794469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.949794469
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.772788562
Short name T1573
Test name
Test status
Simulation time 184808887 ps
CPU time 0.85 seconds
Started Jun 25 04:58:22 PM PDT 24
Finished Jun 25 04:58:25 PM PDT 24
Peak memory 206580 kb
Host smart-98d8bc83-3109-4c19-b5ea-1968f4bfd77d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77278
8562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.772788562
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.1534601671
Short name T926
Test name
Test status
Simulation time 167754984 ps
CPU time 0.77 seconds
Started Jun 25 04:58:24 PM PDT 24
Finished Jun 25 04:58:27 PM PDT 24
Peak memory 206484 kb
Host smart-6dfa8e74-6c0e-4831-9657-104dce033e11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15346
01671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.1534601671
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.3524529822
Short name T2421
Test name
Test status
Simulation time 10627913967 ps
CPU time 106.03 seconds
Started Jun 25 04:58:23 PM PDT 24
Finished Jun 25 05:00:11 PM PDT 24
Peak memory 206804 kb
Host smart-d6a6af2d-617c-43f8-b8fa-2db36db36647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35245
29822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.3524529822
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.3347629760
Short name T511
Test name
Test status
Simulation time 3847742390 ps
CPU time 5.13 seconds
Started Jun 25 04:58:22 PM PDT 24
Finished Jun 25 04:58:30 PM PDT 24
Peak memory 206700 kb
Host smart-056f2350-5307-4715-b817-800a0a445ccc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3347629760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.3347629760
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.2242806555
Short name T1949
Test name
Test status
Simulation time 13358643109 ps
CPU time 15.62 seconds
Started Jun 25 04:58:22 PM PDT 24
Finished Jun 25 04:58:40 PM PDT 24
Peak memory 206872 kb
Host smart-feaaa0a3-0b33-4492-9391-3ce93848f45d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2242806555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.2242806555
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.2975319619
Short name T2503
Test name
Test status
Simulation time 23368398155 ps
CPU time 25.79 seconds
Started Jun 25 04:58:22 PM PDT 24
Finished Jun 25 04:58:50 PM PDT 24
Peak memory 206796 kb
Host smart-44a5b1bc-7d4b-43e3-9b24-36df668c3aec
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2975319619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.2975319619
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.1264654102
Short name T2500
Test name
Test status
Simulation time 144612797 ps
CPU time 0.76 seconds
Started Jun 25 04:58:22 PM PDT 24
Finished Jun 25 04:58:25 PM PDT 24
Peak memory 206496 kb
Host smart-3a4e832a-c53d-414c-9499-67655ccd2878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12646
54102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.1264654102
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.3333840920
Short name T1313
Test name
Test status
Simulation time 173357438 ps
CPU time 0.8 seconds
Started Jun 25 04:58:21 PM PDT 24
Finished Jun 25 04:58:24 PM PDT 24
Peak memory 206748 kb
Host smart-51c82550-c1f8-4f19-90a3-da31f3b37408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33338
40920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.3333840920
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.2126805864
Short name T975
Test name
Test status
Simulation time 360942843 ps
CPU time 1.24 seconds
Started Jun 25 04:58:22 PM PDT 24
Finished Jun 25 04:58:26 PM PDT 24
Peak memory 206524 kb
Host smart-00fc26e2-b9eb-44b9-b46f-08eaf1793880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21268
05864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.2126805864
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.496849461
Short name T775
Test name
Test status
Simulation time 1027557591 ps
CPU time 2.28 seconds
Started Jun 25 04:58:22 PM PDT 24
Finished Jun 25 04:58:26 PM PDT 24
Peak memory 206792 kb
Host smart-a3a3e06a-cd17-4adc-a0d7-dbe2e3be75a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49684
9461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.496849461
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.847215176
Short name T1464
Test name
Test status
Simulation time 15096161129 ps
CPU time 26.22 seconds
Started Jun 25 04:58:23 PM PDT 24
Finished Jun 25 04:58:51 PM PDT 24
Peak memory 206804 kb
Host smart-13b27a48-5b19-441c-8ea3-e6ce7898f8e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84721
5176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.847215176
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.3429865730
Short name T213
Test name
Test status
Simulation time 395210734 ps
CPU time 1.19 seconds
Started Jun 25 04:58:23 PM PDT 24
Finished Jun 25 04:58:26 PM PDT 24
Peak memory 206492 kb
Host smart-30f5122f-d2f8-44ec-97bd-fad4198dbd4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34298
65730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.3429865730
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.3621514636
Short name T1687
Test name
Test status
Simulation time 145559378 ps
CPU time 0.85 seconds
Started Jun 25 04:58:34 PM PDT 24
Finished Jun 25 04:58:36 PM PDT 24
Peak memory 206596 kb
Host smart-9a7c483e-aa47-4344-88c7-aec208c0d09d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36215
14636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.3621514636
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.1616007564
Short name T984
Test name
Test status
Simulation time 42281714 ps
CPU time 0.68 seconds
Started Jun 25 04:58:33 PM PDT 24
Finished Jun 25 04:58:35 PM PDT 24
Peak memory 206552 kb
Host smart-ceae4702-696e-4e50-8578-8e6db5740641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16160
07564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.1616007564
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.645491059
Short name T1194
Test name
Test status
Simulation time 999880663 ps
CPU time 2.13 seconds
Started Jun 25 04:58:33 PM PDT 24
Finished Jun 25 04:58:37 PM PDT 24
Peak memory 206740 kb
Host smart-dfc25952-1e37-48b4-9c9d-fa8fd06ad605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64549
1059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.645491059
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.2318692072
Short name T1096
Test name
Test status
Simulation time 348564454 ps
CPU time 2.08 seconds
Started Jun 25 04:58:34 PM PDT 24
Finished Jun 25 04:58:38 PM PDT 24
Peak memory 206756 kb
Host smart-cb7bc0e2-37fb-43b7-a4e5-703a2f39db4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23186
92072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.2318692072
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.830637002
Short name T1681
Test name
Test status
Simulation time 250045557 ps
CPU time 0.89 seconds
Started Jun 25 04:58:47 PM PDT 24
Finished Jun 25 04:58:50 PM PDT 24
Peak memory 206604 kb
Host smart-0d3e2d6a-2965-4071-94d0-2784c467b677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83063
7002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.830637002
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.1180818631
Short name T2206
Test name
Test status
Simulation time 164404025 ps
CPU time 0.81 seconds
Started Jun 25 04:58:45 PM PDT 24
Finished Jun 25 04:58:47 PM PDT 24
Peak memory 206748 kb
Host smart-b8d1efcc-a25b-4c0c-9200-38d53bcb557b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11808
18631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.1180818631
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.1031427242
Short name T731
Test name
Test status
Simulation time 195473103 ps
CPU time 0.88 seconds
Started Jun 25 04:58:33 PM PDT 24
Finished Jun 25 04:58:36 PM PDT 24
Peak memory 206504 kb
Host smart-760e9221-f171-4ab6-afe9-8e565cb6b448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10314
27242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.1031427242
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.1257740120
Short name T1000
Test name
Test status
Simulation time 162377858 ps
CPU time 0.82 seconds
Started Jun 25 04:58:33 PM PDT 24
Finished Jun 25 04:58:35 PM PDT 24
Peak memory 206496 kb
Host smart-1902ece3-d6d5-4373-97f1-5a51dc90f351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12577
40120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.1257740120
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.3577577127
Short name T1
Test name
Test status
Simulation time 23310418652 ps
CPU time 21.89 seconds
Started Jun 25 04:58:33 PM PDT 24
Finished Jun 25 04:58:56 PM PDT 24
Peak memory 206692 kb
Host smart-823162ab-0f61-485c-8844-058c48812ecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35775
77127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.3577577127
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.219296303
Short name T322
Test name
Test status
Simulation time 3312726795 ps
CPU time 4.03 seconds
Started Jun 25 04:58:35 PM PDT 24
Finished Jun 25 04:58:41 PM PDT 24
Peak memory 206636 kb
Host smart-3be96065-dbbd-4ff2-a960-dda35cb169ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21929
6303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.219296303
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.3229627639
Short name T2499
Test name
Test status
Simulation time 6729398540 ps
CPU time 47.75 seconds
Started Jun 25 04:58:33 PM PDT 24
Finished Jun 25 04:59:22 PM PDT 24
Peak memory 206988 kb
Host smart-acfb5e35-9349-4d49-a08d-115fbc9f2a4d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3229627639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.3229627639
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.1801196191
Short name T306
Test name
Test status
Simulation time 279725951 ps
CPU time 0.96 seconds
Started Jun 25 04:58:44 PM PDT 24
Finished Jun 25 04:58:46 PM PDT 24
Peak memory 206520 kb
Host smart-1e2f8c90-b490-4e9d-88a5-bb11c3099abf
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1801196191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.1801196191
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.1789349492
Short name T1693
Test name
Test status
Simulation time 216243546 ps
CPU time 0.9 seconds
Started Jun 25 04:58:32 PM PDT 24
Finished Jun 25 04:58:34 PM PDT 24
Peak memory 206596 kb
Host smart-3fe14259-b2b9-4cd7-a5ec-56ba262a7db3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17893
49492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.1789349492
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.2045144212
Short name T2025
Test name
Test status
Simulation time 4817665871 ps
CPU time 133.51 seconds
Started Jun 25 04:58:33 PM PDT 24
Finished Jun 25 05:00:48 PM PDT 24
Peak memory 206976 kb
Host smart-0ac1824c-dfef-4ae9-b0e9-91cb87f8e29f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20451
44212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.2045144212
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.190756873
Short name T2268
Test name
Test status
Simulation time 3898749922 ps
CPU time 37.21 seconds
Started Jun 25 04:58:34 PM PDT 24
Finished Jun 25 04:59:13 PM PDT 24
Peak memory 206936 kb
Host smart-2b900631-2282-43ff-b296-2a91c25d80c5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=190756873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.190756873
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.458728905
Short name T2292
Test name
Test status
Simulation time 176547880 ps
CPU time 0.82 seconds
Started Jun 25 04:58:46 PM PDT 24
Finished Jun 25 04:58:48 PM PDT 24
Peak memory 206596 kb
Host smart-d0bdb9ae-e162-42ac-86b4-a97467ab1e7a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=458728905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.458728905
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.3263929931
Short name T2260
Test name
Test status
Simulation time 148616665 ps
CPU time 0.75 seconds
Started Jun 25 04:58:35 PM PDT 24
Finished Jun 25 04:58:37 PM PDT 24
Peak memory 206544 kb
Host smart-caffcf2d-4f2f-43c3-bc64-3d996021529a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32639
29931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.3263929931
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.3886563101
Short name T138
Test name
Test status
Simulation time 214599191 ps
CPU time 0.84 seconds
Started Jun 25 04:58:36 PM PDT 24
Finished Jun 25 04:58:38 PM PDT 24
Peak memory 206516 kb
Host smart-3c02c34e-9c11-4cc5-abfd-3ced4bf7ae13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38865
63101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.3886563101
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.2755417168
Short name T992
Test name
Test status
Simulation time 178457558 ps
CPU time 0.82 seconds
Started Jun 25 04:58:35 PM PDT 24
Finished Jun 25 04:58:38 PM PDT 24
Peak memory 206560 kb
Host smart-8da17f68-db88-4cf6-99a2-b364819f6a6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27554
17168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.2755417168
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.3126643699
Short name T576
Test name
Test status
Simulation time 198479180 ps
CPU time 0.88 seconds
Started Jun 25 04:58:34 PM PDT 24
Finished Jun 25 04:58:37 PM PDT 24
Peak memory 206572 kb
Host smart-06223cac-b339-4590-833f-79b985f05fe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31266
43699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.3126643699
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.2613060012
Short name T2311
Test name
Test status
Simulation time 215195682 ps
CPU time 0.83 seconds
Started Jun 25 04:58:32 PM PDT 24
Finished Jun 25 04:58:33 PM PDT 24
Peak memory 206532 kb
Host smart-d609642d-8319-49d9-ad60-d109c3f12534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26130
60012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.2613060012
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.4236116189
Short name T160
Test name
Test status
Simulation time 150134237 ps
CPU time 0.8 seconds
Started Jun 25 04:58:34 PM PDT 24
Finished Jun 25 04:58:36 PM PDT 24
Peak memory 206504 kb
Host smart-a4157f17-d0af-4fbe-ba09-f2acd4d8a1fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42361
16189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.4236116189
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.2551084549
Short name T940
Test name
Test status
Simulation time 248336103 ps
CPU time 1.09 seconds
Started Jun 25 04:58:34 PM PDT 24
Finished Jun 25 04:58:36 PM PDT 24
Peak memory 206572 kb
Host smart-cbec66a3-b042-43b8-a99c-a99cf7035d25
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2551084549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.2551084549
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.2742276167
Short name T411
Test name
Test status
Simulation time 145283443 ps
CPU time 0.76 seconds
Started Jun 25 04:58:35 PM PDT 24
Finished Jun 25 04:58:37 PM PDT 24
Peak memory 206576 kb
Host smart-a2b879f0-0ab3-4460-a5e2-65050cbd5a1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27422
76167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.2742276167
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.2913020903
Short name T1927
Test name
Test status
Simulation time 37742790 ps
CPU time 0.66 seconds
Started Jun 25 04:58:34 PM PDT 24
Finished Jun 25 04:58:36 PM PDT 24
Peak memory 206552 kb
Host smart-939edc57-a424-4d53-abd5-30fda637a82b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29130
20903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.2913020903
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.3398504867
Short name T1956
Test name
Test status
Simulation time 17130293672 ps
CPU time 38.74 seconds
Started Jun 25 04:58:32 PM PDT 24
Finished Jun 25 04:59:12 PM PDT 24
Peak memory 206892 kb
Host smart-df7dd2a9-93f8-47b6-aeff-1c92ed69e0b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33985
04867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.3398504867
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.2318619723
Short name T534
Test name
Test status
Simulation time 201187388 ps
CPU time 0.88 seconds
Started Jun 25 04:58:35 PM PDT 24
Finished Jun 25 04:58:37 PM PDT 24
Peak memory 206600 kb
Host smart-df0263d9-c838-4424-8a35-61a774974906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23186
19723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.2318619723
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.2042163792
Short name T491
Test name
Test status
Simulation time 225739827 ps
CPU time 0.92 seconds
Started Jun 25 04:58:35 PM PDT 24
Finished Jun 25 04:58:37 PM PDT 24
Peak memory 206600 kb
Host smart-a16ff8d3-e601-4a16-9b82-01296cc253fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20421
63792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.2042163792
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.3551159522
Short name T1868
Test name
Test status
Simulation time 243456810 ps
CPU time 0.89 seconds
Started Jun 25 04:58:45 PM PDT 24
Finished Jun 25 04:58:47 PM PDT 24
Peak memory 206584 kb
Host smart-257008a6-a689-43f8-815d-39b2c6c34746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35511
59522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.3551159522
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.3120481840
Short name T1435
Test name
Test status
Simulation time 184659599 ps
CPU time 0.83 seconds
Started Jun 25 04:58:34 PM PDT 24
Finished Jun 25 04:58:36 PM PDT 24
Peak memory 206572 kb
Host smart-58c70f5e-892b-4926-a62a-0d331c8e5b3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31204
81840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.3120481840
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.2722334791
Short name T962
Test name
Test status
Simulation time 150648266 ps
CPU time 0.75 seconds
Started Jun 25 04:58:35 PM PDT 24
Finished Jun 25 04:58:38 PM PDT 24
Peak memory 206568 kb
Host smart-2b8aa9e7-e617-4cb4-be46-79bcdcb600c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27223
34791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.2722334791
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.1802519191
Short name T1345
Test name
Test status
Simulation time 158668220 ps
CPU time 0.76 seconds
Started Jun 25 04:58:35 PM PDT 24
Finished Jun 25 04:58:37 PM PDT 24
Peak memory 206476 kb
Host smart-51a7f69a-172e-4bc9-8f78-0aee2f47644d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18025
19191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.1802519191
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.3455182717
Short name T820
Test name
Test status
Simulation time 149615964 ps
CPU time 0.8 seconds
Started Jun 25 04:58:33 PM PDT 24
Finished Jun 25 04:58:35 PM PDT 24
Peak memory 206500 kb
Host smart-2eb4bc6d-b0f2-4aa6-b070-255f85d5fbca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34551
82717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.3455182717
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.680993636
Short name T797
Test name
Test status
Simulation time 242865572 ps
CPU time 0.95 seconds
Started Jun 25 04:58:35 PM PDT 24
Finished Jun 25 04:58:37 PM PDT 24
Peak memory 206584 kb
Host smart-fcca3211-9195-4820-b8fa-43bfb11e1ee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68099
3636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.680993636
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.1456856662
Short name T2135
Test name
Test status
Simulation time 7017154833 ps
CPU time 66.89 seconds
Started Jun 25 04:58:33 PM PDT 24
Finished Jun 25 04:59:41 PM PDT 24
Peak memory 206960 kb
Host smart-8ed45f0c-46f0-4d3f-9e93-dd0b45014e62
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1456856662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.1456856662
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.18132585
Short name T1512
Test name
Test status
Simulation time 150838981 ps
CPU time 0.77 seconds
Started Jun 25 04:58:35 PM PDT 24
Finished Jun 25 04:58:37 PM PDT 24
Peak memory 206588 kb
Host smart-b810c46a-79a7-45bd-a2ba-3525cd0d9970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18132
585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.18132585
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.1364006879
Short name T1639
Test name
Test status
Simulation time 160952637 ps
CPU time 0.8 seconds
Started Jun 25 04:58:33 PM PDT 24
Finished Jun 25 04:58:35 PM PDT 24
Peak memory 206600 kb
Host smart-c0b393e8-c9e3-4de4-80d2-878a0bc9a8a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13640
06879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.1364006879
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.3512518341
Short name T1230
Test name
Test status
Simulation time 3845094740 ps
CPU time 27.73 seconds
Started Jun 25 04:58:32 PM PDT 24
Finished Jun 25 04:59:01 PM PDT 24
Peak memory 206872 kb
Host smart-c15cc799-70b5-455c-bcc2-159affc4c9a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35125
18341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.3512518341
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.2209989609
Short name T1827
Test name
Test status
Simulation time 4340943401 ps
CPU time 5.19 seconds
Started Jun 25 04:58:48 PM PDT 24
Finished Jun 25 04:58:55 PM PDT 24
Peak memory 206596 kb
Host smart-76663080-e1c7-47ff-9901-d9f42ba34aaa
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2209989609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.2209989609
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.2361586556
Short name T2203
Test name
Test status
Simulation time 13387683734 ps
CPU time 15.7 seconds
Started Jun 25 04:58:49 PM PDT 24
Finished Jun 25 04:59:06 PM PDT 24
Peak memory 206916 kb
Host smart-c94ffcff-cdd1-4e9b-90ee-3e8f5e0d7710
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2361586556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.2361586556
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.790932657
Short name T506
Test name
Test status
Simulation time 23397850492 ps
CPU time 22.81 seconds
Started Jun 25 04:58:48 PM PDT 24
Finished Jun 25 04:59:12 PM PDT 24
Peak memory 206604 kb
Host smart-111971cc-38c1-4079-a2b5-94c5d0e59515
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=790932657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.790932657
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.1351275298
Short name T1290
Test name
Test status
Simulation time 179898095 ps
CPU time 0.86 seconds
Started Jun 25 04:58:45 PM PDT 24
Finished Jun 25 04:58:48 PM PDT 24
Peak memory 206576 kb
Host smart-aad71f02-469d-47d6-a0e7-fc82beb5e812
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13512
75298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.1351275298
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.4275074226
Short name T660
Test name
Test status
Simulation time 152110914 ps
CPU time 0.76 seconds
Started Jun 25 04:58:42 PM PDT 24
Finished Jun 25 04:58:44 PM PDT 24
Peak memory 206580 kb
Host smart-d73a6ce0-ef74-4dec-9186-0c5f3c924e0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42750
74226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.4275074226
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.1310212500
Short name T1631
Test name
Test status
Simulation time 352101832 ps
CPU time 1.32 seconds
Started Jun 25 04:58:46 PM PDT 24
Finished Jun 25 04:58:49 PM PDT 24
Peak memory 206596 kb
Host smart-ae32ca00-ab3b-4eac-9661-89e5c334aacf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13102
12500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.1310212500
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.2764342454
Short name T1715
Test name
Test status
Simulation time 1382349110 ps
CPU time 2.97 seconds
Started Jun 25 04:58:49 PM PDT 24
Finished Jun 25 04:58:53 PM PDT 24
Peak memory 206800 kb
Host smart-72d46697-7403-42f7-b4be-a44b95983f9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27643
42454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.2764342454
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.655522926
Short name T1410
Test name
Test status
Simulation time 16411598188 ps
CPU time 31.95 seconds
Started Jun 25 04:58:43 PM PDT 24
Finished Jun 25 04:59:15 PM PDT 24
Peak memory 206912 kb
Host smart-a14ce5be-122a-4642-bec3-72a539bee958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65552
2926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.655522926
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.3552079898
Short name T1587
Test name
Test status
Simulation time 315530093 ps
CPU time 1.11 seconds
Started Jun 25 04:58:44 PM PDT 24
Finished Jun 25 04:58:46 PM PDT 24
Peak memory 206572 kb
Host smart-425590c6-65bb-4326-9e49-e225813609d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35520
79898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.3552079898
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.2177511395
Short name T1879
Test name
Test status
Simulation time 178269125 ps
CPU time 0.78 seconds
Started Jun 25 04:58:44 PM PDT 24
Finished Jun 25 04:58:46 PM PDT 24
Peak memory 206596 kb
Host smart-9726e497-47d9-4145-90ff-bffd6da55aeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21775
11395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.2177511395
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.1434719138
Short name T684
Test name
Test status
Simulation time 38943911 ps
CPU time 0.66 seconds
Started Jun 25 04:58:44 PM PDT 24
Finished Jun 25 04:58:46 PM PDT 24
Peak memory 206552 kb
Host smart-5fc89693-b797-45af-bc13-ddb23f65bebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14347
19138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.1434719138
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.1943669812
Short name T1586
Test name
Test status
Simulation time 1007615169 ps
CPU time 2.36 seconds
Started Jun 25 04:58:48 PM PDT 24
Finished Jun 25 04:58:52 PM PDT 24
Peak memory 206656 kb
Host smart-6af5d3e8-68fa-4113-b256-a6e54a57f4b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19436
69812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.1943669812
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.2603723490
Short name T2096
Test name
Test status
Simulation time 302706567 ps
CPU time 2.31 seconds
Started Jun 25 04:58:44 PM PDT 24
Finished Jun 25 04:58:47 PM PDT 24
Peak memory 206756 kb
Host smart-18a3cf1d-8ade-4e9c-b53e-402a38d1fd88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26037
23490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.2603723490
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.3553447711
Short name T494
Test name
Test status
Simulation time 234945511 ps
CPU time 0.88 seconds
Started Jun 25 04:58:51 PM PDT 24
Finished Jun 25 04:58:54 PM PDT 24
Peak memory 206576 kb
Host smart-400d1607-3cf8-47e2-bc67-b5e234534a72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35534
47711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.3553447711
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.1121276718
Short name T1043
Test name
Test status
Simulation time 181386866 ps
CPU time 0.79 seconds
Started Jun 25 04:58:51 PM PDT 24
Finished Jun 25 04:58:53 PM PDT 24
Peak memory 206564 kb
Host smart-ff464dfb-6958-4c7d-b399-8bee8c6d0a5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11212
76718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.1121276718
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.585442149
Short name T1341
Test name
Test status
Simulation time 179686354 ps
CPU time 0.88 seconds
Started Jun 25 04:58:48 PM PDT 24
Finished Jun 25 04:58:50 PM PDT 24
Peak memory 206572 kb
Host smart-3e24df1e-428b-4783-b75d-fbeaa609e3b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58544
2149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.585442149
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.609589462
Short name T2171
Test name
Test status
Simulation time 172219245 ps
CPU time 0.84 seconds
Started Jun 25 04:58:45 PM PDT 24
Finished Jun 25 04:58:48 PM PDT 24
Peak memory 206752 kb
Host smart-59c68d69-0b96-477d-bcb4-95cddab21535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60958
9462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.609589462
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.1654586518
Short name T1192
Test name
Test status
Simulation time 23326659063 ps
CPU time 22.74 seconds
Started Jun 25 04:58:48 PM PDT 24
Finished Jun 25 04:59:12 PM PDT 24
Peak memory 206696 kb
Host smart-97840f68-92ed-4d42-97fe-196dd968b0af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16545
86518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.1654586518
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.2544692115
Short name T1967
Test name
Test status
Simulation time 3314630243 ps
CPU time 4.6 seconds
Started Jun 25 04:58:46 PM PDT 24
Finished Jun 25 04:58:52 PM PDT 24
Peak memory 206680 kb
Host smart-4daa2952-8cc0-4ea1-95a4-edbedb935a03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25446
92115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.2544692115
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.3157617569
Short name T2020
Test name
Test status
Simulation time 11128686106 ps
CPU time 106.25 seconds
Started Jun 25 04:58:48 PM PDT 24
Finished Jun 25 05:00:36 PM PDT 24
Peak memory 206888 kb
Host smart-b28b863b-76c8-482e-808a-19441dfc035a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3157617569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.3157617569
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.47993303
Short name T1001
Test name
Test status
Simulation time 270081142 ps
CPU time 0.95 seconds
Started Jun 25 04:58:49 PM PDT 24
Finished Jun 25 04:58:52 PM PDT 24
Peak memory 206492 kb
Host smart-482a60b2-e290-43bd-960b-e95da8546999
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=47993303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.47993303
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.3799615458
Short name T867
Test name
Test status
Simulation time 197363828 ps
CPU time 0.87 seconds
Started Jun 25 04:58:46 PM PDT 24
Finished Jun 25 04:58:49 PM PDT 24
Peak memory 206512 kb
Host smart-50300263-7185-40d1-a40e-5237dedf39de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37996
15458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.3799615458
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.2760554436
Short name T700
Test name
Test status
Simulation time 4037792595 ps
CPU time 111.33 seconds
Started Jun 25 04:58:45 PM PDT 24
Finished Jun 25 05:00:38 PM PDT 24
Peak memory 206884 kb
Host smart-46c832f5-17bb-48fe-a49e-59ccd66c83d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27605
54436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.2760554436
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.1166027942
Short name T1709
Test name
Test status
Simulation time 4926104527 ps
CPU time 46.69 seconds
Started Jun 25 04:58:45 PM PDT 24
Finished Jun 25 04:59:33 PM PDT 24
Peak memory 206888 kb
Host smart-c51a234c-1f19-4cf9-a10c-8c66f2b89a3d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1166027942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.1166027942
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.2276249925
Short name T2213
Test name
Test status
Simulation time 191971574 ps
CPU time 0.9 seconds
Started Jun 25 04:58:52 PM PDT 24
Finished Jun 25 04:58:55 PM PDT 24
Peak memory 206384 kb
Host smart-96e729cc-5e4d-4307-be50-e0a5e7d26f9b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2276249925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.2276249925
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.1719094219
Short name T935
Test name
Test status
Simulation time 175631439 ps
CPU time 0.78 seconds
Started Jun 25 04:58:52 PM PDT 24
Finished Jun 25 04:58:54 PM PDT 24
Peak memory 206396 kb
Host smart-37f3afd4-e87f-481e-a9ee-93457951627d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17190
94219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.1719094219
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.2928951512
Short name T1037
Test name
Test status
Simulation time 164548519 ps
CPU time 0.79 seconds
Started Jun 25 04:58:50 PM PDT 24
Finished Jun 25 04:58:52 PM PDT 24
Peak memory 206504 kb
Host smart-1adffe1f-e76a-403c-9f46-119d7f626349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29289
51512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.2928951512
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.2003888203
Short name T484
Test name
Test status
Simulation time 188217158 ps
CPU time 0.84 seconds
Started Jun 25 04:58:45 PM PDT 24
Finished Jun 25 04:58:47 PM PDT 24
Peak memory 206516 kb
Host smart-5f770da9-5260-429c-8913-7d7cc15002bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20038
88203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.2003888203
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.45252079
Short name T985
Test name
Test status
Simulation time 162631546 ps
CPU time 0.8 seconds
Started Jun 25 04:58:46 PM PDT 24
Finished Jun 25 04:58:48 PM PDT 24
Peak memory 206576 kb
Host smart-bf05b4cb-b4fb-4554-a377-fcdb0386f867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45252
079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.45252079
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.4269652716
Short name T1521
Test name
Test status
Simulation time 146033650 ps
CPU time 0.77 seconds
Started Jun 25 04:58:50 PM PDT 24
Finished Jun 25 04:58:52 PM PDT 24
Peak memory 206516 kb
Host smart-b197791a-529b-42f7-a5cb-50908ba02bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42696
52716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.4269652716
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.4144213078
Short name T2420
Test name
Test status
Simulation time 235559782 ps
CPU time 0.95 seconds
Started Jun 25 04:58:55 PM PDT 24
Finished Jun 25 04:58:59 PM PDT 24
Peak memory 206572 kb
Host smart-68e33afb-633b-4e63-8bb9-6a5c4c59e155
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4144213078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.4144213078
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.90721523
Short name T1026
Test name
Test status
Simulation time 189865234 ps
CPU time 0.89 seconds
Started Jun 25 04:58:46 PM PDT 24
Finished Jun 25 04:58:48 PM PDT 24
Peak memory 206568 kb
Host smart-1ed626c2-69d9-4bef-8bf0-5474e7fc3377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90721
523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.90721523
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.642871057
Short name T2514
Test name
Test status
Simulation time 53218247 ps
CPU time 0.68 seconds
Started Jun 25 04:58:45 PM PDT 24
Finished Jun 25 04:58:47 PM PDT 24
Peak memory 206548 kb
Host smart-87f10221-11a9-4ad7-bbdf-80e295e324ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64287
1057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.642871057
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.2206049160
Short name T1107
Test name
Test status
Simulation time 14599430554 ps
CPU time 33.92 seconds
Started Jun 25 04:58:45 PM PDT 24
Finished Jun 25 04:59:21 PM PDT 24
Peak memory 206924 kb
Host smart-098dec3d-2841-40e8-9948-6c072e4b583b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22060
49160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.2206049160
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.1014993042
Short name T275
Test name
Test status
Simulation time 219455925 ps
CPU time 0.85 seconds
Started Jun 25 04:58:42 PM PDT 24
Finished Jun 25 04:58:44 PM PDT 24
Peak memory 206576 kb
Host smart-01059559-4a81-4daf-a967-3fef41c5246b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10149
93042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.1014993042
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.268232905
Short name T2258
Test name
Test status
Simulation time 209227086 ps
CPU time 0.87 seconds
Started Jun 25 04:58:44 PM PDT 24
Finished Jun 25 04:58:47 PM PDT 24
Peak memory 206504 kb
Host smart-a453a440-324b-4be2-a222-a6351d2bd829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26823
2905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.268232905
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.4030021061
Short name T495
Test name
Test status
Simulation time 245655193 ps
CPU time 0.9 seconds
Started Jun 25 04:58:47 PM PDT 24
Finished Jun 25 04:58:49 PM PDT 24
Peak memory 206580 kb
Host smart-3e6976e3-8704-4b07-b156-a429f4b9f76d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40300
21061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.4030021061
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.359272594
Short name T808
Test name
Test status
Simulation time 219413527 ps
CPU time 0.84 seconds
Started Jun 25 04:58:51 PM PDT 24
Finished Jun 25 04:58:53 PM PDT 24
Peak memory 206572 kb
Host smart-576a7b33-1417-4c7e-8896-49a0b1b579d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35927
2594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.359272594
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.1843421920
Short name T2489
Test name
Test status
Simulation time 133795621 ps
CPU time 0.78 seconds
Started Jun 25 04:58:51 PM PDT 24
Finished Jun 25 04:58:54 PM PDT 24
Peak memory 206600 kb
Host smart-1005e3d1-a367-47b6-9197-d7ea2035ca3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18434
21920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.1843421920
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.2649955343
Short name T1462
Test name
Test status
Simulation time 170537942 ps
CPU time 0.84 seconds
Started Jun 25 04:58:52 PM PDT 24
Finished Jun 25 04:58:54 PM PDT 24
Peak memory 206568 kb
Host smart-19bb4230-119e-44be-aba3-7fb39583b708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26499
55343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.2649955343
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.1521885661
Short name T456
Test name
Test status
Simulation time 154641500 ps
CPU time 0.83 seconds
Started Jun 25 04:58:46 PM PDT 24
Finished Jun 25 04:58:49 PM PDT 24
Peak memory 206600 kb
Host smart-573b2665-01cc-41cc-ab3f-86759922554c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15218
85661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.1521885661
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.2496295988
Short name T2360
Test name
Test status
Simulation time 257507755 ps
CPU time 1.07 seconds
Started Jun 25 04:58:45 PM PDT 24
Finished Jun 25 04:58:48 PM PDT 24
Peak memory 206592 kb
Host smart-ffb100da-3a5e-4179-9ad6-2508b1f66b92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24962
95988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.2496295988
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.1389741711
Short name T2350
Test name
Test status
Simulation time 9607299732 ps
CPU time 275.28 seconds
Started Jun 25 04:58:45 PM PDT 24
Finished Jun 25 05:03:22 PM PDT 24
Peak memory 206932 kb
Host smart-6a8fea76-19e1-4e53-9be4-9afecc676bff
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1389741711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.1389741711
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.1779697232
Short name T542
Test name
Test status
Simulation time 167960277 ps
CPU time 0.79 seconds
Started Jun 25 04:58:49 PM PDT 24
Finished Jun 25 04:58:51 PM PDT 24
Peak memory 206580 kb
Host smart-9cf82833-8be8-443c-84f8-12ed10bb5690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17796
97232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.1779697232
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.1838603678
Short name T1240
Test name
Test status
Simulation time 181102451 ps
CPU time 0.82 seconds
Started Jun 25 04:58:46 PM PDT 24
Finished Jun 25 04:58:49 PM PDT 24
Peak memory 206508 kb
Host smart-47122365-2292-491c-8d3c-1ec461ec0961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18386
03678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.1838603678
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.3061449050
Short name T1459
Test name
Test status
Simulation time 8947327290 ps
CPU time 244.21 seconds
Started Jun 25 04:58:47 PM PDT 24
Finished Jun 25 05:02:53 PM PDT 24
Peak memory 206924 kb
Host smart-c0de01c8-40e4-4d81-b861-49450590de75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30614
49050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.3061449050
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.3510177741
Short name T2389
Test name
Test status
Simulation time 3973333797 ps
CPU time 4.64 seconds
Started Jun 25 04:58:51 PM PDT 24
Finished Jun 25 04:58:57 PM PDT 24
Peak memory 206928 kb
Host smart-85bc39e0-8459-4803-bf17-8602dea66f4a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3510177741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.3510177741
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.311541701
Short name T833
Test name
Test status
Simulation time 13392305048 ps
CPU time 14.07 seconds
Started Jun 25 04:58:46 PM PDT 24
Finished Jun 25 04:59:02 PM PDT 24
Peak memory 206736 kb
Host smart-de7ec8df-4d95-4937-afa7-ab1a2e52da17
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=311541701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.311541701
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.3148812133
Short name T1999
Test name
Test status
Simulation time 23383766535 ps
CPU time 25.11 seconds
Started Jun 25 04:58:52 PM PDT 24
Finished Jun 25 04:59:19 PM PDT 24
Peak memory 206716 kb
Host smart-467329bb-11cf-401a-900c-c163e2981485
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3148812133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.3148812133
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.869697499
Short name T824
Test name
Test status
Simulation time 149647474 ps
CPU time 0.77 seconds
Started Jun 25 04:58:52 PM PDT 24
Finished Jun 25 04:58:54 PM PDT 24
Peak memory 206568 kb
Host smart-57c982d9-1113-4e5f-a941-54e0087e2478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86969
7499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.869697499
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.590000089
Short name T63
Test name
Test status
Simulation time 161509663 ps
CPU time 0.77 seconds
Started Jun 25 04:58:52 PM PDT 24
Finished Jun 25 04:58:55 PM PDT 24
Peak memory 206472 kb
Host smart-0184d074-f452-4294-9d56-8fb10cb57b3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59000
0089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.590000089
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.3470116523
Short name T2355
Test name
Test status
Simulation time 368757756 ps
CPU time 1.23 seconds
Started Jun 25 04:58:55 PM PDT 24
Finished Jun 25 04:58:58 PM PDT 24
Peak memory 206492 kb
Host smart-729d6722-7102-4a87-81b0-b953395a988c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34701
16523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.3470116523
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.908850103
Short name T2399
Test name
Test status
Simulation time 418202587 ps
CPU time 1.21 seconds
Started Jun 25 04:58:58 PM PDT 24
Finished Jun 25 04:59:01 PM PDT 24
Peak memory 206572 kb
Host smart-aa1129cc-902e-436b-9a99-7c70ed6326c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90885
0103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.908850103
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.1505889117
Short name T109
Test name
Test status
Simulation time 17575124899 ps
CPU time 35.8 seconds
Started Jun 25 04:58:56 PM PDT 24
Finished Jun 25 04:59:35 PM PDT 24
Peak memory 206812 kb
Host smart-5016d7c4-f37d-4cb3-8097-97a90c357665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15058
89117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.1505889117
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.1306879379
Short name T2147
Test name
Test status
Simulation time 335448515 ps
CPU time 1.16 seconds
Started Jun 25 04:58:54 PM PDT 24
Finished Jun 25 04:58:57 PM PDT 24
Peak memory 206532 kb
Host smart-18dae642-5acc-40f2-ad81-68188a308f3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13068
79379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.1306879379
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.1520973624
Short name T508
Test name
Test status
Simulation time 174386771 ps
CPU time 0.77 seconds
Started Jun 25 04:58:53 PM PDT 24
Finished Jun 25 04:58:55 PM PDT 24
Peak memory 206512 kb
Host smart-199a55ed-8238-4975-baf2-02424cc431f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15209
73624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.1520973624
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.1423490406
Short name T2287
Test name
Test status
Simulation time 44664926 ps
CPU time 0.66 seconds
Started Jun 25 04:58:55 PM PDT 24
Finished Jun 25 04:58:58 PM PDT 24
Peak memory 206488 kb
Host smart-896707af-2f25-4107-876c-2690d984c6b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14234
90406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.1423490406
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.2091253513
Short name T1400
Test name
Test status
Simulation time 929094454 ps
CPU time 2.19 seconds
Started Jun 25 04:58:52 PM PDT 24
Finished Jun 25 04:58:56 PM PDT 24
Peak memory 206740 kb
Host smart-c6577ebb-9ed0-4667-ad78-fc25996ec8ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20912
53513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.2091253513
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.3255469951
Short name T215
Test name
Test status
Simulation time 155855168 ps
CPU time 0.8 seconds
Started Jun 25 04:58:56 PM PDT 24
Finished Jun 25 04:58:59 PM PDT 24
Peak memory 206788 kb
Host smart-0190b2fb-aa28-4308-b622-9270252a154e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32554
69951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.3255469951
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.3087073413
Short name T2340
Test name
Test status
Simulation time 157648963 ps
CPU time 0.77 seconds
Started Jun 25 04:58:54 PM PDT 24
Finished Jun 25 04:58:58 PM PDT 24
Peak memory 206748 kb
Host smart-1dc4a746-915c-42fe-b82b-010d66487be5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30870
73413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.3087073413
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.4223647265
Short name T1467
Test name
Test status
Simulation time 223317744 ps
CPU time 0.93 seconds
Started Jun 25 04:58:55 PM PDT 24
Finished Jun 25 04:58:59 PM PDT 24
Peak memory 206520 kb
Host smart-f6393bc2-885f-4b26-8317-399e6513ad4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42236
47265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.4223647265
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.2025795438
Short name T1572
Test name
Test status
Simulation time 197452872 ps
CPU time 0.93 seconds
Started Jun 25 04:58:54 PM PDT 24
Finished Jun 25 04:58:56 PM PDT 24
Peak memory 206592 kb
Host smart-31b79aa7-1026-480d-b460-180e3883da2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20257
95438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.2025795438
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.2946043961
Short name T2165
Test name
Test status
Simulation time 3299104876 ps
CPU time 3.82 seconds
Started Jun 25 04:58:56 PM PDT 24
Finished Jun 25 04:59:03 PM PDT 24
Peak memory 206616 kb
Host smart-e8d3e12a-776b-47c3-ba69-3d1045542ed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29460
43961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.2946043961
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.4040013686
Short name T1656
Test name
Test status
Simulation time 3841390395 ps
CPU time 108.05 seconds
Started Jun 25 04:58:53 PM PDT 24
Finished Jun 25 05:00:42 PM PDT 24
Peak memory 206956 kb
Host smart-8c92063d-5d91-4728-9e29-5515f02006df
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4040013686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.4040013686
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.1187636201
Short name T2471
Test name
Test status
Simulation time 255968491 ps
CPU time 0.95 seconds
Started Jun 25 04:58:56 PM PDT 24
Finished Jun 25 04:59:00 PM PDT 24
Peak memory 206520 kb
Host smart-0c81b9b7-96bd-4be0-96a1-058afd10ed51
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1187636201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.1187636201
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.1492552387
Short name T2047
Test name
Test status
Simulation time 230331967 ps
CPU time 0.9 seconds
Started Jun 25 04:58:53 PM PDT 24
Finished Jun 25 04:58:55 PM PDT 24
Peak memory 206572 kb
Host smart-0402549b-41d8-49a3-95e1-afefd0361cd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14925
52387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.1492552387
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.1570039582
Short name T1359
Test name
Test status
Simulation time 3230234387 ps
CPU time 30.75 seconds
Started Jun 25 04:58:54 PM PDT 24
Finished Jun 25 04:59:27 PM PDT 24
Peak memory 206776 kb
Host smart-51ccdc85-8256-4e0f-b81e-cf485d4affbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15700
39582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.1570039582
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.2885379113
Short name T967
Test name
Test status
Simulation time 9663691453 ps
CPU time 66.1 seconds
Started Jun 25 04:58:54 PM PDT 24
Finished Jun 25 05:00:02 PM PDT 24
Peak memory 206888 kb
Host smart-b1f43bff-a219-4570-98a7-3b744a305e96
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2885379113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.2885379113
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.2540555891
Short name T591
Test name
Test status
Simulation time 158032405 ps
CPU time 0.79 seconds
Started Jun 25 04:58:54 PM PDT 24
Finished Jun 25 04:58:57 PM PDT 24
Peak memory 206584 kb
Host smart-f625c8ca-a010-4d61-89e1-a16e5b03018e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2540555891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.2540555891
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.1288914582
Short name T1959
Test name
Test status
Simulation time 159774678 ps
CPU time 0.74 seconds
Started Jun 25 04:58:56 PM PDT 24
Finished Jun 25 04:58:59 PM PDT 24
Peak memory 206564 kb
Host smart-f492c41e-cf71-4ffb-a725-043e8a3d5be4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12889
14582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.1288914582
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.3405311195
Short name T134
Test name
Test status
Simulation time 215880793 ps
CPU time 0.91 seconds
Started Jun 25 04:58:54 PM PDT 24
Finished Jun 25 04:58:57 PM PDT 24
Peak memory 206580 kb
Host smart-2197e450-a75e-4e12-9bd5-3498991083b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34053
11195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.3405311195
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.2143331737
Short name T1042
Test name
Test status
Simulation time 158756733 ps
CPU time 0.78 seconds
Started Jun 25 04:58:54 PM PDT 24
Finished Jun 25 04:58:57 PM PDT 24
Peak memory 206588 kb
Host smart-426891f3-9eac-46ec-8589-15b27df0f887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21433
31737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.2143331737
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.3215050287
Short name T2286
Test name
Test status
Simulation time 175064522 ps
CPU time 0.8 seconds
Started Jun 25 04:58:55 PM PDT 24
Finished Jun 25 04:58:59 PM PDT 24
Peak memory 206532 kb
Host smart-4b14933f-f1e1-4342-8c3c-a34d4b264f7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32150
50287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.3215050287
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.778492400
Short name T327
Test name
Test status
Simulation time 161345959 ps
CPU time 0.84 seconds
Started Jun 25 04:58:57 PM PDT 24
Finished Jun 25 04:59:00 PM PDT 24
Peak memory 206500 kb
Host smart-d8014a2c-baea-4b0d-9eeb-742032b41890
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77849
2400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.778492400
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.990030387
Short name T2445
Test name
Test status
Simulation time 160126551 ps
CPU time 0.83 seconds
Started Jun 25 04:58:56 PM PDT 24
Finished Jun 25 04:59:00 PM PDT 24
Peak memory 206876 kb
Host smart-6220e7ea-aca8-4a9e-adf3-e3b03936b171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99003
0387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.990030387
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.1876425536
Short name T1616
Test name
Test status
Simulation time 207192565 ps
CPU time 0.94 seconds
Started Jun 25 04:58:58 PM PDT 24
Finished Jun 25 04:59:01 PM PDT 24
Peak memory 206592 kb
Host smart-90f2316c-1162-4ea9-ae37-3783bba00466
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1876425536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.1876425536
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.446020946
Short name T2490
Test name
Test status
Simulation time 160255613 ps
CPU time 0.79 seconds
Started Jun 25 04:58:54 PM PDT 24
Finished Jun 25 04:58:57 PM PDT 24
Peak memory 206592 kb
Host smart-e87fdb4d-e708-4f89-a58e-14b87748a3e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44602
0946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.446020946
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.987369076
Short name T2269
Test name
Test status
Simulation time 37337907 ps
CPU time 0.69 seconds
Started Jun 25 04:58:54 PM PDT 24
Finished Jun 25 04:58:57 PM PDT 24
Peak memory 206528 kb
Host smart-02a84aa9-efed-433c-9f6e-ab07d2cf7d5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98736
9076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.987369076
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.3385381948
Short name T93
Test name
Test status
Simulation time 11186234954 ps
CPU time 24.97 seconds
Started Jun 25 04:58:58 PM PDT 24
Finished Jun 25 04:59:25 PM PDT 24
Peak memory 206784 kb
Host smart-f8e15b8f-5d6e-4d41-9e76-44ba237ed365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33853
81948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.3385381948
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.3645304604
Short name T1695
Test name
Test status
Simulation time 176255589 ps
CPU time 0.84 seconds
Started Jun 25 04:58:54 PM PDT 24
Finished Jun 25 04:58:57 PM PDT 24
Peak memory 206492 kb
Host smart-d3530eba-aabb-4cae-a8c4-306b8d755f1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36453
04604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.3645304604
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.713254417
Short name T2247
Test name
Test status
Simulation time 220982666 ps
CPU time 0.92 seconds
Started Jun 25 04:58:54 PM PDT 24
Finished Jun 25 04:58:57 PM PDT 24
Peak memory 206596 kb
Host smart-e86df686-aef2-433e-9996-0f9075772c24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71325
4417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.713254417
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.930082233
Short name T1069
Test name
Test status
Simulation time 183460949 ps
CPU time 0.83 seconds
Started Jun 25 04:58:55 PM PDT 24
Finished Jun 25 04:58:59 PM PDT 24
Peak memory 206592 kb
Host smart-10a2b45a-01a7-42fe-b5cc-974a0b07c6e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93008
2233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.930082233
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.1316912223
Short name T1741
Test name
Test status
Simulation time 178173662 ps
CPU time 0.87 seconds
Started Jun 25 04:58:59 PM PDT 24
Finished Jun 25 04:59:01 PM PDT 24
Peak memory 206500 kb
Host smart-a284bb2e-7ca3-47ba-834f-dae9401e7271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13169
12223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.1316912223
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.3165354542
Short name T1283
Test name
Test status
Simulation time 169299653 ps
CPU time 0.84 seconds
Started Jun 25 04:58:54 PM PDT 24
Finished Jun 25 04:58:57 PM PDT 24
Peak memory 206580 kb
Host smart-9f87bbf0-8b7a-4550-8b44-4b1b8b4b6917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31653
54542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.3165354542
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.3443614631
Short name T569
Test name
Test status
Simulation time 179529086 ps
CPU time 0.85 seconds
Started Jun 25 04:58:55 PM PDT 24
Finished Jun 25 04:58:58 PM PDT 24
Peak memory 206500 kb
Host smart-ec03b19b-c449-423a-b66b-48609dd67f88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34436
14631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.3443614631
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.1601615018
Short name T1722
Test name
Test status
Simulation time 175381521 ps
CPU time 0.82 seconds
Started Jun 25 04:58:52 PM PDT 24
Finished Jun 25 04:58:55 PM PDT 24
Peak memory 206580 kb
Host smart-a7fe8548-7570-460d-acb5-49e6d42f1c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16016
15018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.1601615018
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.693838963
Short name T1563
Test name
Test status
Simulation time 215998908 ps
CPU time 0.89 seconds
Started Jun 25 04:58:56 PM PDT 24
Finished Jun 25 04:58:59 PM PDT 24
Peak memory 206808 kb
Host smart-a3c81dff-7ca7-437b-9c6f-70465a7b47c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69383
8963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.693838963
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.3870956511
Short name T1911
Test name
Test status
Simulation time 12113260467 ps
CPU time 110.62 seconds
Started Jun 25 04:58:52 PM PDT 24
Finished Jun 25 05:00:44 PM PDT 24
Peak memory 206860 kb
Host smart-87529783-6fa8-46fe-bf6f-2d761cda8195
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3870956511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.3870956511
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.4038886012
Short name T1154
Test name
Test status
Simulation time 189529619 ps
CPU time 0.82 seconds
Started Jun 25 04:58:58 PM PDT 24
Finished Jun 25 04:59:01 PM PDT 24
Peak memory 206580 kb
Host smart-273272dd-3f58-4ae9-873b-e20133a626d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40388
86012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.4038886012
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.2986702031
Short name T1536
Test name
Test status
Simulation time 220498453 ps
CPU time 0.87 seconds
Started Jun 25 04:58:55 PM PDT 24
Finished Jun 25 04:58:58 PM PDT 24
Peak memory 206572 kb
Host smart-a5dbdafa-4b96-42d3-8f67-b2f71f807cb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29867
02031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.2986702031
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.264760990
Short name T1893
Test name
Test status
Simulation time 7082658260 ps
CPU time 49.7 seconds
Started Jun 25 04:58:55 PM PDT 24
Finished Jun 25 04:59:48 PM PDT 24
Peak memory 206896 kb
Host smart-cd390666-af0d-4b15-a3cb-f01c8fd31fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26476
0990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.264760990
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.2147519752
Short name T356
Test name
Test status
Simulation time 3897596471 ps
CPU time 4.68 seconds
Started Jun 25 04:58:57 PM PDT 24
Finished Jun 25 04:59:04 PM PDT 24
Peak memory 206792 kb
Host smart-3593b616-f13e-4084-9978-4815f7a143fc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2147519752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.2147519752
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.996023444
Short name T2463
Test name
Test status
Simulation time 13326511773 ps
CPU time 13.22 seconds
Started Jun 25 04:58:55 PM PDT 24
Finished Jun 25 04:59:10 PM PDT 24
Peak memory 206876 kb
Host smart-a25a060c-6360-4f16-902d-f967eb93acc5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=996023444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.996023444
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.1396452663
Short name T1399
Test name
Test status
Simulation time 23398633999 ps
CPU time 23.97 seconds
Started Jun 25 04:58:56 PM PDT 24
Finished Jun 25 04:59:23 PM PDT 24
Peak memory 206652 kb
Host smart-eeac1537-8d60-43d1-8a0b-9d496b9f7818
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1396452663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.1396452663
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.2383996799
Short name T2266
Test name
Test status
Simulation time 187274543 ps
CPU time 0.86 seconds
Started Jun 25 04:58:53 PM PDT 24
Finished Jun 25 04:58:56 PM PDT 24
Peak memory 206508 kb
Host smart-ed45821e-4117-4a5e-8b13-31d12df4608f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23839
96799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.2383996799
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.381498495
Short name T486
Test name
Test status
Simulation time 169709386 ps
CPU time 0.86 seconds
Started Jun 25 04:58:55 PM PDT 24
Finished Jun 25 04:58:59 PM PDT 24
Peak memory 206492 kb
Host smart-cbd11aa4-4790-450a-a358-a195ee9606cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38149
8495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.381498495
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.608898490
Short name T2045
Test name
Test status
Simulation time 264969555 ps
CPU time 1.01 seconds
Started Jun 25 04:58:54 PM PDT 24
Finished Jun 25 04:58:58 PM PDT 24
Peak memory 206560 kb
Host smart-3c26ba3f-c655-4b03-96aa-1fa7d4c81b0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60889
8490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.608898490
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.4018766965
Short name T762
Test name
Test status
Simulation time 1473695920 ps
CPU time 3.61 seconds
Started Jun 25 04:59:01 PM PDT 24
Finished Jun 25 04:59:06 PM PDT 24
Peak memory 206708 kb
Host smart-41bdaaa5-f83d-4582-8fa4-8b3202690ac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40187
66965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.4018766965
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.2751130247
Short name T2083
Test name
Test status
Simulation time 15610128046 ps
CPU time 27.63 seconds
Started Jun 25 04:59:04 PM PDT 24
Finished Jun 25 04:59:34 PM PDT 24
Peak memory 206864 kb
Host smart-de1849a9-c051-4413-a419-61d5c2e41533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27511
30247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.2751130247
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.484570800
Short name T2078
Test name
Test status
Simulation time 449375886 ps
CPU time 1.37 seconds
Started Jun 25 04:59:04 PM PDT 24
Finished Jun 25 04:59:07 PM PDT 24
Peak memory 206572 kb
Host smart-3ba9ecc5-1f15-4c1a-9aeb-899d4199e690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48457
0800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.484570800
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.2018491611
Short name T2427
Test name
Test status
Simulation time 137397661 ps
CPU time 0.79 seconds
Started Jun 25 04:59:03 PM PDT 24
Finished Jun 25 04:59:06 PM PDT 24
Peak memory 206576 kb
Host smart-fba09cfc-831f-4a21-b71a-d3fbb9722c7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20184
91611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.2018491611
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.3533482886
Short name T713
Test name
Test status
Simulation time 40425106 ps
CPU time 0.68 seconds
Started Jun 25 04:59:05 PM PDT 24
Finished Jun 25 04:59:08 PM PDT 24
Peak memory 206576 kb
Host smart-8c6ecea8-5157-4912-b920-6b344c258540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35334
82886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.3533482886
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.292823717
Short name T2097
Test name
Test status
Simulation time 911426747 ps
CPU time 2.15 seconds
Started Jun 25 04:59:01 PM PDT 24
Finished Jun 25 04:59:04 PM PDT 24
Peak memory 206684 kb
Host smart-d0587d27-b3af-4ccc-a39c-a1f5f5783fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29282
3717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.292823717
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.604681919
Short name T965
Test name
Test status
Simulation time 292627701 ps
CPU time 2.17 seconds
Started Jun 25 04:59:04 PM PDT 24
Finished Jun 25 04:59:08 PM PDT 24
Peak memory 206720 kb
Host smart-18a832ef-c129-49b8-829b-78e8cf37a62b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60468
1919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.604681919
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.1851260418
Short name T2010
Test name
Test status
Simulation time 237883557 ps
CPU time 0.9 seconds
Started Jun 25 04:59:07 PM PDT 24
Finished Jun 25 04:59:10 PM PDT 24
Peak memory 206592 kb
Host smart-82cf29ce-865d-415c-8c2d-1e86aa170810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18512
60418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.1851260418
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.3989930839
Short name T886
Test name
Test status
Simulation time 200446620 ps
CPU time 0.8 seconds
Started Jun 25 04:59:04 PM PDT 24
Finished Jun 25 04:59:07 PM PDT 24
Peak memory 206508 kb
Host smart-337fc4ec-c517-46f0-a3de-7b3895e92530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39899
30839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.3989930839
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.2207158972
Short name T1061
Test name
Test status
Simulation time 192635813 ps
CPU time 0.89 seconds
Started Jun 25 04:59:04 PM PDT 24
Finished Jun 25 04:59:07 PM PDT 24
Peak memory 206600 kb
Host smart-6cf01146-e959-40b2-9247-dcf726bc6d04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22071
58972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.2207158972
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.1189464800
Short name T1638
Test name
Test status
Simulation time 251332954 ps
CPU time 0.91 seconds
Started Jun 25 04:59:06 PM PDT 24
Finished Jun 25 04:59:10 PM PDT 24
Peak memory 206508 kb
Host smart-c652f0d6-9ca5-43c1-8f3b-e09af0f3989f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11894
64800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.1189464800
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.3724032952
Short name T827
Test name
Test status
Simulation time 23278976049 ps
CPU time 22.44 seconds
Started Jun 25 04:59:04 PM PDT 24
Finished Jun 25 04:59:29 PM PDT 24
Peak memory 206616 kb
Host smart-277fb4a5-df1b-4171-a40a-7d4ce34cd22d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37240
32952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.3724032952
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.2303961669
Short name T1441
Test name
Test status
Simulation time 3317769032 ps
CPU time 4.06 seconds
Started Jun 25 04:59:03 PM PDT 24
Finished Jun 25 04:59:09 PM PDT 24
Peak memory 206692 kb
Host smart-ecf6f2fe-006b-43fc-857e-f7e36e7523d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23039
61669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.2303961669
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.2210441095
Short name T845
Test name
Test status
Simulation time 6548953973 ps
CPU time 46.35 seconds
Started Jun 25 04:59:05 PM PDT 24
Finished Jun 25 04:59:54 PM PDT 24
Peak memory 206916 kb
Host smart-2d2b4e69-f322-4ff1-88f6-0dcb8baeab73
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2210441095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.2210441095
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.3768766874
Short name T1871
Test name
Test status
Simulation time 253247550 ps
CPU time 0.9 seconds
Started Jun 25 04:59:02 PM PDT 24
Finished Jun 25 04:59:04 PM PDT 24
Peak memory 206596 kb
Host smart-b4a22317-a375-4055-966a-c90d5b82527e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3768766874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.3768766874
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.4212708797
Short name T1643
Test name
Test status
Simulation time 203051645 ps
CPU time 0.9 seconds
Started Jun 25 04:59:11 PM PDT 24
Finished Jun 25 04:59:13 PM PDT 24
Peak memory 206576 kb
Host smart-d709bfa3-3de0-4f95-90e1-49d9fc62c7a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42127
08797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.4212708797
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.1007574548
Short name T1331
Test name
Test status
Simulation time 5251815803 ps
CPU time 46.99 seconds
Started Jun 25 04:59:01 PM PDT 24
Finished Jun 25 04:59:49 PM PDT 24
Peak memory 206792 kb
Host smart-ca9c10da-1a73-45c7-9a4b-70d253caef89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10075
74548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.1007574548
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.1396339921
Short name T319
Test name
Test status
Simulation time 8049796853 ps
CPU time 60.15 seconds
Started Jun 25 04:59:05 PM PDT 24
Finished Jun 25 05:00:07 PM PDT 24
Peak memory 206824 kb
Host smart-bfb4941d-15c7-4bb0-9787-ed22b41cfffa
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1396339921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.1396339921
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.1426179059
Short name T1945
Test name
Test status
Simulation time 159125321 ps
CPU time 0.86 seconds
Started Jun 25 04:59:04 PM PDT 24
Finished Jun 25 04:59:08 PM PDT 24
Peak memory 206500 kb
Host smart-ebae9230-17f4-4b3f-926d-acf4a472a76b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1426179059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.1426179059
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.2084174791
Short name T916
Test name
Test status
Simulation time 143046996 ps
CPU time 0.77 seconds
Started Jun 25 04:59:03 PM PDT 24
Finished Jun 25 04:59:05 PM PDT 24
Peak memory 206596 kb
Host smart-b3efeae6-6b50-48a9-b265-61266e5e0084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20841
74791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.2084174791
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.2447222231
Short name T133
Test name
Test status
Simulation time 203536401 ps
CPU time 0.82 seconds
Started Jun 25 04:59:06 PM PDT 24
Finished Jun 25 04:59:10 PM PDT 24
Peak memory 206572 kb
Host smart-c17fd73d-e5df-4eb8-8772-53da07447e48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24472
22231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.2447222231
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.1396448096
Short name T1266
Test name
Test status
Simulation time 165967851 ps
CPU time 0.81 seconds
Started Jun 25 04:59:10 PM PDT 24
Finished Jun 25 04:59:13 PM PDT 24
Peak memory 206568 kb
Host smart-5141cf5d-32da-49f9-a87e-54ab38b17ac2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13964
48096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.1396448096
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.809349744
Short name T303
Test name
Test status
Simulation time 217927500 ps
CPU time 0.89 seconds
Started Jun 25 04:59:04 PM PDT 24
Finished Jun 25 04:59:07 PM PDT 24
Peak memory 206556 kb
Host smart-f418e86d-222f-4324-a64f-5b9916146592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80934
9744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.809349744
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.3045022625
Short name T1244
Test name
Test status
Simulation time 157098580 ps
CPU time 0.88 seconds
Started Jun 25 04:59:10 PM PDT 24
Finished Jun 25 04:59:12 PM PDT 24
Peak memory 206244 kb
Host smart-8bcacb52-b1fa-40df-b1e7-adf87d1de8fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30450
22625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.3045022625
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.1548015917
Short name T1784
Test name
Test status
Simulation time 151390852 ps
CPU time 0.79 seconds
Started Jun 25 04:59:03 PM PDT 24
Finished Jun 25 04:59:05 PM PDT 24
Peak memory 206580 kb
Host smart-6f128839-2f71-4426-b8ad-44319134b1ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15480
15917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.1548015917
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.4193726220
Short name T631
Test name
Test status
Simulation time 231974435 ps
CPU time 1.13 seconds
Started Jun 25 04:59:02 PM PDT 24
Finished Jun 25 04:59:04 PM PDT 24
Peak memory 206580 kb
Host smart-3ebe869b-ef43-4a7c-9ec2-61ee2a2bea9b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4193726220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.4193726220
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.455274467
Short name T853
Test name
Test status
Simulation time 147143227 ps
CPU time 0.77 seconds
Started Jun 25 04:59:04 PM PDT 24
Finished Jun 25 04:59:07 PM PDT 24
Peak memory 206600 kb
Host smart-ceb916e3-9307-4731-873a-69ab1d18aedb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45527
4467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.455274467
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.2930085892
Short name T504
Test name
Test status
Simulation time 36223987 ps
CPU time 0.68 seconds
Started Jun 25 04:59:04 PM PDT 24
Finished Jun 25 04:59:08 PM PDT 24
Peak memory 206456 kb
Host smart-183bb17e-643f-43f4-ac84-1f551a1fabda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29300
85892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.2930085892
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.3334389077
Short name T1663
Test name
Test status
Simulation time 12372477962 ps
CPU time 32.05 seconds
Started Jun 25 04:59:02 PM PDT 24
Finished Jun 25 04:59:36 PM PDT 24
Peak memory 206984 kb
Host smart-c67659dc-daff-49af-af91-f6a729e5a41c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33343
89077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.3334389077
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.2444737530
Short name T2298
Test name
Test status
Simulation time 211597176 ps
CPU time 0.92 seconds
Started Jun 25 04:59:10 PM PDT 24
Finished Jun 25 04:59:13 PM PDT 24
Peak memory 206544 kb
Host smart-d0b15510-6d65-4c54-864d-3c56ab3bcb1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24447
37530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.2444737530
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.2841833446
Short name T1406
Test name
Test status
Simulation time 226821631 ps
CPU time 0.9 seconds
Started Jun 25 04:59:02 PM PDT 24
Finished Jun 25 04:59:04 PM PDT 24
Peak memory 206576 kb
Host smart-cdf8dd47-fdb4-4b20-a242-b19dae0682d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28418
33446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.2841833446
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.1615018160
Short name T1520
Test name
Test status
Simulation time 248383662 ps
CPU time 0.9 seconds
Started Jun 25 04:59:05 PM PDT 24
Finished Jun 25 04:59:09 PM PDT 24
Peak memory 206500 kb
Host smart-add0d815-d323-4efb-8e5e-a13697fb06bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16150
18160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.1615018160
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.3033982249
Short name T1819
Test name
Test status
Simulation time 215668724 ps
CPU time 0.96 seconds
Started Jun 25 04:59:07 PM PDT 24
Finished Jun 25 04:59:10 PM PDT 24
Peak memory 206576 kb
Host smart-c4335d42-fa4b-4638-9424-2b5e56cef660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30339
82249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.3033982249
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.853804127
Short name T77
Test name
Test status
Simulation time 141974291 ps
CPU time 0.81 seconds
Started Jun 25 04:59:01 PM PDT 24
Finished Jun 25 04:59:03 PM PDT 24
Peak memory 206604 kb
Host smart-0a0233e3-356c-4982-b01b-bbfd4f2328ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85380
4127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.853804127
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.257525706
Short name T1263
Test name
Test status
Simulation time 181181311 ps
CPU time 0.8 seconds
Started Jun 25 04:59:06 PM PDT 24
Finished Jun 25 04:59:10 PM PDT 24
Peak memory 206596 kb
Host smart-e7cc320f-628d-4ff5-904f-4c9a4e682e78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25752
5706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.257525706
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.121118248
Short name T460
Test name
Test status
Simulation time 213679189 ps
CPU time 0.86 seconds
Started Jun 25 04:59:08 PM PDT 24
Finished Jun 25 04:59:11 PM PDT 24
Peak memory 206572 kb
Host smart-22a824e0-0874-4ebb-91a3-b26694569d26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12111
8248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.121118248
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.1317128466
Short name T880
Test name
Test status
Simulation time 245527212 ps
CPU time 0.92 seconds
Started Jun 25 04:59:04 PM PDT 24
Finished Jun 25 04:59:08 PM PDT 24
Peak memory 206604 kb
Host smart-7a23eb4a-c078-4722-9ce8-eb3c05f7bce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13171
28466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.1317128466
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.1377116395
Short name T2265
Test name
Test status
Simulation time 6216829328 ps
CPU time 176.46 seconds
Started Jun 25 04:59:02 PM PDT 24
Finished Jun 25 05:02:00 PM PDT 24
Peak memory 206888 kb
Host smart-5bd5e96f-7730-41e4-8107-95f5e60c514f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1377116395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.1377116395
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.2304636682
Short name T746
Test name
Test status
Simulation time 182470507 ps
CPU time 0.81 seconds
Started Jun 25 04:59:06 PM PDT 24
Finished Jun 25 04:59:10 PM PDT 24
Peak memory 206512 kb
Host smart-441d3b58-f332-41e5-9e7a-dc9f34cf8c99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23046
36682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.2304636682
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.205148696
Short name T2453
Test name
Test status
Simulation time 213793410 ps
CPU time 0.87 seconds
Started Jun 25 04:59:07 PM PDT 24
Finished Jun 25 04:59:10 PM PDT 24
Peak memory 206572 kb
Host smart-9426b0db-1086-4974-ac5d-074e8f27b425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20514
8696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.205148696
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.1671185319
Short name T1917
Test name
Test status
Simulation time 4959898849 ps
CPU time 37.48 seconds
Started Jun 25 04:59:02 PM PDT 24
Finished Jun 25 04:59:41 PM PDT 24
Peak memory 206864 kb
Host smart-cc0be816-d716-4b12-a017-fcd24393a507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16711
85319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.1671185319
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.3181172287
Short name T395
Test name
Test status
Simulation time 3694692227 ps
CPU time 4.35 seconds
Started Jun 25 04:59:05 PM PDT 24
Finished Jun 25 04:59:12 PM PDT 24
Peak memory 206788 kb
Host smart-2bd008b4-a567-42ad-9477-9b8327e89ea9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3181172287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.3181172287
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.4011739624
Short name T533
Test name
Test status
Simulation time 13363015632 ps
CPU time 13.23 seconds
Started Jun 25 04:59:02 PM PDT 24
Finished Jun 25 04:59:17 PM PDT 24
Peak memory 206720 kb
Host smart-9f9ebdc9-fba1-491e-a869-7cdcdfee6047
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4011739624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.4011739624
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.2404295524
Short name T603
Test name
Test status
Simulation time 23390697470 ps
CPU time 21.34 seconds
Started Jun 25 04:59:03 PM PDT 24
Finished Jun 25 04:59:26 PM PDT 24
Peak memory 206972 kb
Host smart-b3e807e8-d350-464b-b05f-d78165a01515
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2404295524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.2404295524
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.874565825
Short name T2149
Test name
Test status
Simulation time 199820405 ps
CPU time 0.86 seconds
Started Jun 25 04:59:06 PM PDT 24
Finished Jun 25 04:59:09 PM PDT 24
Peak memory 206496 kb
Host smart-a8bc223a-34aa-49c4-bc32-779a9f5eb5dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87456
5825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.874565825
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.3944689795
Short name T1834
Test name
Test status
Simulation time 170203741 ps
CPU time 0.84 seconds
Started Jun 25 04:59:03 PM PDT 24
Finished Jun 25 04:59:06 PM PDT 24
Peak memory 206580 kb
Host smart-63f4bd63-3dc1-4085-a43e-032c34aa9fce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39446
89795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.3944689795
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.2740573364
Short name T548
Test name
Test status
Simulation time 631804102 ps
CPU time 1.69 seconds
Started Jun 25 04:59:03 PM PDT 24
Finished Jun 25 04:59:06 PM PDT 24
Peak memory 206788 kb
Host smart-16f113d3-cdc1-4070-a9c7-d11a2eb92988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27405
73364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.2740573364
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.2997892801
Short name T990
Test name
Test status
Simulation time 1336141522 ps
CPU time 3.08 seconds
Started Jun 25 04:59:10 PM PDT 24
Finished Jun 25 04:59:15 PM PDT 24
Peak memory 206716 kb
Host smart-46076cb1-40c6-42d8-900c-35d842438221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29978
92801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.2997892801
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.236186242
Short name T1045
Test name
Test status
Simulation time 14138191536 ps
CPU time 28.26 seconds
Started Jun 25 04:59:10 PM PDT 24
Finished Jun 25 04:59:40 PM PDT 24
Peak memory 206692 kb
Host smart-c80944b3-6703-4fdf-ae10-0ceed0866c56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23618
6242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.236186242
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.586351146
Short name T371
Test name
Test status
Simulation time 472011012 ps
CPU time 1.56 seconds
Started Jun 25 04:59:04 PM PDT 24
Finished Jun 25 04:59:08 PM PDT 24
Peak memory 206580 kb
Host smart-1879f09d-aee5-4537-802a-30841ae90d56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58635
1146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.586351146
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.710591334
Short name T2275
Test name
Test status
Simulation time 139499551 ps
CPU time 0.78 seconds
Started Jun 25 04:59:07 PM PDT 24
Finished Jun 25 04:59:10 PM PDT 24
Peak memory 206572 kb
Host smart-8e1ab4b7-325d-44e6-931f-068a9749c4a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71059
1334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.710591334
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.2585940572
Short name T896
Test name
Test status
Simulation time 44184821 ps
CPU time 0.68 seconds
Started Jun 25 04:59:04 PM PDT 24
Finished Jun 25 04:59:08 PM PDT 24
Peak memory 206488 kb
Host smart-dfcb0c31-e95d-4102-b570-2582c87597fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25859
40572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.2585940572
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.2804811441
Short name T993
Test name
Test status
Simulation time 789368654 ps
CPU time 2.05 seconds
Started Jun 25 04:59:05 PM PDT 24
Finished Jun 25 04:59:10 PM PDT 24
Peak memory 206680 kb
Host smart-781f6238-0055-4d9d-a389-5819be30f8e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28048
11441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.2804811441
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.3222391007
Short name T1583
Test name
Test status
Simulation time 266635226 ps
CPU time 1.84 seconds
Started Jun 25 04:59:06 PM PDT 24
Finished Jun 25 04:59:10 PM PDT 24
Peak memory 206712 kb
Host smart-600418c7-789e-4195-bc08-ae82654f01ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32223
91007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.3222391007
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.1055494103
Short name T2415
Test name
Test status
Simulation time 201152495 ps
CPU time 0.83 seconds
Started Jun 25 04:59:13 PM PDT 24
Finished Jun 25 04:59:15 PM PDT 24
Peak memory 206568 kb
Host smart-4017f909-a6aa-4bd0-9eac-d513c6dfd212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10554
94103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.1055494103
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.4046287292
Short name T1413
Test name
Test status
Simulation time 138559032 ps
CPU time 0.79 seconds
Started Jun 25 04:59:12 PM PDT 24
Finished Jun 25 04:59:15 PM PDT 24
Peak memory 206540 kb
Host smart-f3404d40-386b-48cf-9ed0-7114dfac9e7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40462
87292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.4046287292
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.2003347281
Short name T724
Test name
Test status
Simulation time 170608173 ps
CPU time 0.81 seconds
Started Jun 25 04:59:06 PM PDT 24
Finished Jun 25 04:59:09 PM PDT 24
Peak memory 206496 kb
Host smart-1855e89b-6051-48a2-9893-a4f4aa2185c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20033
47281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.2003347281
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_invalid_sync.2879406635
Short name T235
Test name
Test status
Simulation time 7943527742 ps
CPU time 226.96 seconds
Started Jun 25 04:59:05 PM PDT 24
Finished Jun 25 05:02:54 PM PDT 24
Peak memory 206988 kb
Host smart-c1d1e436-fa95-46f4-9674-7743cff6c4ce
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2879406635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.2879406635
Directory /workspace/18.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.2822224876
Short name T299
Test name
Test status
Simulation time 205890405 ps
CPU time 0.88 seconds
Started Jun 25 04:59:10 PM PDT 24
Finished Jun 25 04:59:12 PM PDT 24
Peak memory 206568 kb
Host smart-8e329c2e-e145-4856-8c3d-636b7541abfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28222
24876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.2822224876
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.1685319570
Short name T2187
Test name
Test status
Simulation time 23297370013 ps
CPU time 22.4 seconds
Started Jun 25 04:59:12 PM PDT 24
Finished Jun 25 04:59:36 PM PDT 24
Peak memory 206628 kb
Host smart-270c7238-3c1c-49fc-bbf3-83e866b8b929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16853
19570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.1685319570
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.702620889
Short name T30
Test name
Test status
Simulation time 3289948964 ps
CPU time 3.99 seconds
Started Jun 25 04:59:12 PM PDT 24
Finished Jun 25 04:59:18 PM PDT 24
Peak memory 206616 kb
Host smart-a4c6131a-3f77-40d8-ba49-02b9aefc2012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70262
0889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.702620889
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.1337966583
Short name T891
Test name
Test status
Simulation time 11561854748 ps
CPU time 106.23 seconds
Started Jun 25 04:59:10 PM PDT 24
Finished Jun 25 05:00:58 PM PDT 24
Peak memory 206944 kb
Host smart-e4ba587c-d2bb-4474-8b48-33fb1d7321e2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1337966583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.1337966583
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.3918862888
Short name T1920
Test name
Test status
Simulation time 244639705 ps
CPU time 0.9 seconds
Started Jun 25 04:59:22 PM PDT 24
Finished Jun 25 04:59:24 PM PDT 24
Peak memory 206432 kb
Host smart-78e30263-c2ff-42a4-9129-1f78e2360a1c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3918862888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.3918862888
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.147702596
Short name T1370
Test name
Test status
Simulation time 190400053 ps
CPU time 0.97 seconds
Started Jun 25 04:59:13 PM PDT 24
Finished Jun 25 04:59:15 PM PDT 24
Peak memory 206576 kb
Host smart-ded52d44-7327-4129-b906-d42066fd6617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14770
2596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.147702596
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.2424319211
Short name T2189
Test name
Test status
Simulation time 11276586148 ps
CPU time 77.09 seconds
Started Jun 25 04:59:09 PM PDT 24
Finished Jun 25 05:00:28 PM PDT 24
Peak memory 206924 kb
Host smart-5137dc7c-3938-4301-a60e-e556d5f06339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24243
19211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.2424319211
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.1223539179
Short name T1432
Test name
Test status
Simulation time 5535994555 ps
CPU time 145.95 seconds
Started Jun 25 04:59:12 PM PDT 24
Finished Jun 25 05:01:40 PM PDT 24
Peak memory 206980 kb
Host smart-fab1c78d-175f-4c1e-8c4a-f1061474aa31
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1223539179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.1223539179
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.4077255449
Short name T1678
Test name
Test status
Simulation time 163929948 ps
CPU time 0.79 seconds
Started Jun 25 04:59:11 PM PDT 24
Finished Jun 25 04:59:13 PM PDT 24
Peak memory 206576 kb
Host smart-3859e8d7-bbcc-4ae9-9c53-96e4c6afd2d9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4077255449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.4077255449
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.2767366315
Short name T364
Test name
Test status
Simulation time 150187962 ps
CPU time 0.74 seconds
Started Jun 25 04:59:23 PM PDT 24
Finished Jun 25 04:59:26 PM PDT 24
Peak memory 206452 kb
Host smart-1799da08-f4af-412c-abb5-847334c477bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27673
66315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.2767366315
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.2538939340
Short name T119
Test name
Test status
Simulation time 195957615 ps
CPU time 0.88 seconds
Started Jun 25 04:59:14 PM PDT 24
Finished Jun 25 04:59:16 PM PDT 24
Peak memory 206508 kb
Host smart-231ca186-08a8-42d3-9002-8073c73795af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25389
39340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.2538939340
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.2457011378
Short name T1342
Test name
Test status
Simulation time 185865212 ps
CPU time 0.89 seconds
Started Jun 25 04:59:11 PM PDT 24
Finished Jun 25 04:59:14 PM PDT 24
Peak memory 206496 kb
Host smart-7f234b78-99c4-4cd6-af74-c74128345cd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24570
11378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.2457011378
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.4002217253
Short name T1689
Test name
Test status
Simulation time 176901246 ps
CPU time 0.82 seconds
Started Jun 25 04:59:13 PM PDT 24
Finished Jun 25 04:59:16 PM PDT 24
Peak memory 206572 kb
Host smart-2745c334-6ca5-49cd-b5ee-3bbcea161fe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40022
17253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.4002217253
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.3490587533
Short name T2080
Test name
Test status
Simulation time 165581069 ps
CPU time 0.78 seconds
Started Jun 25 04:59:13 PM PDT 24
Finished Jun 25 04:59:15 PM PDT 24
Peak memory 206572 kb
Host smart-e00d9a86-06c8-4617-a0a7-1c7d37114af3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34905
87533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.3490587533
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.2703670615
Short name T152
Test name
Test status
Simulation time 158839685 ps
CPU time 0.84 seconds
Started Jun 25 04:59:14 PM PDT 24
Finished Jun 25 04:59:16 PM PDT 24
Peak memory 206572 kb
Host smart-960e640c-6262-41d2-9d58-bead4faa0523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27036
70615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.2703670615
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.4073752883
Short name T234
Test name
Test status
Simulation time 285890237 ps
CPU time 0.99 seconds
Started Jun 25 04:59:12 PM PDT 24
Finished Jun 25 04:59:15 PM PDT 24
Peak memory 206596 kb
Host smart-5e6599e9-06e5-4d1f-8400-401f8cb10ab6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4073752883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.4073752883
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.3413774065
Short name T1721
Test name
Test status
Simulation time 145083009 ps
CPU time 0.8 seconds
Started Jun 25 04:59:13 PM PDT 24
Finished Jun 25 04:59:16 PM PDT 24
Peak memory 206596 kb
Host smart-62a31160-39a3-47bf-b5f5-3ecdccc27001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34137
74065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.3413774065
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.3550866018
Short name T852
Test name
Test status
Simulation time 40073444 ps
CPU time 0.67 seconds
Started Jun 25 04:59:22 PM PDT 24
Finished Jun 25 04:59:24 PM PDT 24
Peak memory 206472 kb
Host smart-6a70490b-1a72-4d0a-b96b-54df5f3a3349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35508
66018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.3550866018
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.895679059
Short name T1942
Test name
Test status
Simulation time 17766142956 ps
CPU time 42.69 seconds
Started Jun 25 04:59:11 PM PDT 24
Finished Jun 25 04:59:55 PM PDT 24
Peak memory 206860 kb
Host smart-93862aca-5b5e-48ad-8571-70748def8352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89567
9059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.895679059
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.2666409598
Short name T1452
Test name
Test status
Simulation time 181236419 ps
CPU time 0.86 seconds
Started Jun 25 04:59:10 PM PDT 24
Finished Jun 25 04:59:12 PM PDT 24
Peak memory 206592 kb
Host smart-d511a6ed-7fed-4ab0-8e77-d1a9af955bd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26664
09598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.2666409598
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.1770450208
Short name T1566
Test name
Test status
Simulation time 201852207 ps
CPU time 0.85 seconds
Started Jun 25 04:59:11 PM PDT 24
Finished Jun 25 04:59:13 PM PDT 24
Peak memory 206476 kb
Host smart-0330f87e-ea0a-4170-bff1-42588b02a8a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17704
50208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.1770450208
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.282071672
Short name T934
Test name
Test status
Simulation time 198998013 ps
CPU time 0.86 seconds
Started Jun 25 04:59:11 PM PDT 24
Finished Jun 25 04:59:13 PM PDT 24
Peak memory 206508 kb
Host smart-aeb37153-02b2-4199-b4f1-d48ac71dcda6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28207
1672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.282071672
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.2951906023
Short name T1596
Test name
Test status
Simulation time 166018787 ps
CPU time 0.85 seconds
Started Jun 25 04:59:13 PM PDT 24
Finished Jun 25 04:59:16 PM PDT 24
Peak memory 206576 kb
Host smart-e7bc13f8-c185-40ae-b61c-fc95b4265b95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29519
06023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.2951906023
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.3592323479
Short name T1379
Test name
Test status
Simulation time 145026085 ps
CPU time 0.82 seconds
Started Jun 25 04:59:12 PM PDT 24
Finished Jun 25 04:59:14 PM PDT 24
Peak memory 206592 kb
Host smart-813f1b87-4fc2-4c8f-9f12-34de6f033582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35923
23479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.3592323479
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.1775998959
Short name T1188
Test name
Test status
Simulation time 152519870 ps
CPU time 0.74 seconds
Started Jun 25 04:59:23 PM PDT 24
Finished Jun 25 04:59:26 PM PDT 24
Peak memory 206456 kb
Host smart-7acd5c97-99f6-44b4-aea9-f584a92615f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17759
98959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.1775998959
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.1104789996
Short name T1153
Test name
Test status
Simulation time 230373178 ps
CPU time 0.92 seconds
Started Jun 25 04:59:09 PM PDT 24
Finished Jun 25 04:59:12 PM PDT 24
Peak memory 206756 kb
Host smart-0b1a8b25-95be-42fb-854b-b11033b1503b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11047
89996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.1104789996
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.241165375
Short name T346
Test name
Test status
Simulation time 239243010 ps
CPU time 0.93 seconds
Started Jun 25 04:59:10 PM PDT 24
Finished Jun 25 04:59:12 PM PDT 24
Peak memory 206496 kb
Host smart-24f55266-49af-451c-84a0-1e042ccf78ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24116
5375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.241165375
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.1116499500
Short name T2200
Test name
Test status
Simulation time 13225883463 ps
CPU time 92.2 seconds
Started Jun 25 04:59:13 PM PDT 24
Finished Jun 25 05:00:47 PM PDT 24
Peak memory 206860 kb
Host smart-c0592057-a68e-4eaa-a88a-6fe069fceeb9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1116499500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.1116499500
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.3106661875
Short name T2226
Test name
Test status
Simulation time 185960550 ps
CPU time 0.82 seconds
Started Jun 25 04:59:12 PM PDT 24
Finished Jun 25 04:59:15 PM PDT 24
Peak memory 206508 kb
Host smart-7103e2e6-5ed9-4276-beb0-077cb91d45bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31066
61875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.3106661875
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.3919921214
Short name T1389
Test name
Test status
Simulation time 171594594 ps
CPU time 0.81 seconds
Started Jun 25 04:59:22 PM PDT 24
Finished Jun 25 04:59:24 PM PDT 24
Peak memory 206480 kb
Host smart-28f0ed8b-cf7c-44d2-a6fb-557d8405dd6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39199
21214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.3919921214
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.1080041987
Short name T1972
Test name
Test status
Simulation time 7400313578 ps
CPU time 196.62 seconds
Started Jun 25 04:59:10 PM PDT 24
Finished Jun 25 05:02:28 PM PDT 24
Peak memory 206932 kb
Host smart-dbc73851-2741-43a4-8f09-44bd5621d36b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10800
41987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.1080041987
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.2923558333
Short name T465
Test name
Test status
Simulation time 4193917436 ps
CPU time 5.1 seconds
Started Jun 25 04:59:12 PM PDT 24
Finished Jun 25 04:59:19 PM PDT 24
Peak memory 206868 kb
Host smart-cc3c290b-f60d-4d4c-8a35-1c9075ac7263
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2923558333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.2923558333
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.4128490208
Short name T780
Test name
Test status
Simulation time 13453865448 ps
CPU time 13.01 seconds
Started Jun 25 04:59:22 PM PDT 24
Finished Jun 25 04:59:36 PM PDT 24
Peak memory 206796 kb
Host smart-54d3c734-c119-401c-b4a3-08dd75070887
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4128490208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.4128490208
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.4283940086
Short name T541
Test name
Test status
Simulation time 23397285580 ps
CPU time 21.32 seconds
Started Jun 25 04:59:15 PM PDT 24
Finished Jun 25 04:59:37 PM PDT 24
Peak memory 206960 kb
Host smart-a41cd250-64fd-4fc0-88ba-d2693552c0b5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4283940086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.4283940086
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.1969250146
Short name T317
Test name
Test status
Simulation time 150773463 ps
CPU time 0.78 seconds
Started Jun 25 04:59:16 PM PDT 24
Finished Jun 25 04:59:17 PM PDT 24
Peak memory 206592 kb
Host smart-a89de08e-5ed5-4eaa-9abb-5ad6568721d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19692
50146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.1969250146
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.840044636
Short name T1570
Test name
Test status
Simulation time 148580414 ps
CPU time 0.78 seconds
Started Jun 25 04:59:19 PM PDT 24
Finished Jun 25 04:59:21 PM PDT 24
Peak memory 206596 kb
Host smart-43ef6448-ae87-4a7e-87e4-128ddad1de0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84004
4636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.840044636
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.3952296452
Short name T1268
Test name
Test status
Simulation time 298012578 ps
CPU time 1.11 seconds
Started Jun 25 04:59:22 PM PDT 24
Finished Jun 25 04:59:25 PM PDT 24
Peak memory 206512 kb
Host smart-540a803b-3471-4ea6-9bed-42cd4a66926d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39522
96452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.3952296452
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.660917272
Short name T167
Test name
Test status
Simulation time 376647930 ps
CPU time 1.16 seconds
Started Jun 25 04:59:23 PM PDT 24
Finished Jun 25 04:59:25 PM PDT 24
Peak memory 206572 kb
Host smart-2c33f42b-87e7-4be5-bde3-83e6df042999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66091
7272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.660917272
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.2857995590
Short name T1829
Test name
Test status
Simulation time 15498392795 ps
CPU time 27.88 seconds
Started Jun 25 04:59:20 PM PDT 24
Finished Jun 25 04:59:49 PM PDT 24
Peak memory 206860 kb
Host smart-65426c75-d8e8-4c3f-b049-d14b06f75e36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28579
95590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.2857995590
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.1640340437
Short name T454
Test name
Test status
Simulation time 452990402 ps
CPU time 1.42 seconds
Started Jun 25 04:59:20 PM PDT 24
Finished Jun 25 04:59:23 PM PDT 24
Peak memory 206580 kb
Host smart-a35b8705-bc4c-4f91-b451-da130ab687f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16403
40437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.1640340437
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.2162320855
Short name T611
Test name
Test status
Simulation time 145259961 ps
CPU time 0.8 seconds
Started Jun 25 04:59:19 PM PDT 24
Finished Jun 25 04:59:21 PM PDT 24
Peak memory 206588 kb
Host smart-098fc448-b550-4dde-b56b-bb03e6812695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21623
20855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.2162320855
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.4020337029
Short name T1980
Test name
Test status
Simulation time 30521583 ps
CPU time 0.66 seconds
Started Jun 25 04:59:21 PM PDT 24
Finished Jun 25 04:59:23 PM PDT 24
Peak memory 206560 kb
Host smart-3327fc01-6270-4d16-af12-6208b4ce30b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40203
37029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.4020337029
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.1933678041
Short name T1326
Test name
Test status
Simulation time 839396293 ps
CPU time 2.22 seconds
Started Jun 25 04:59:21 PM PDT 24
Finished Jun 25 04:59:24 PM PDT 24
Peak memory 206780 kb
Host smart-cf156ed5-994f-4992-ae00-362226d309f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19336
78041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.1933678041
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.3776747295
Short name T899
Test name
Test status
Simulation time 316460298 ps
CPU time 2.02 seconds
Started Jun 25 04:59:21 PM PDT 24
Finished Jun 25 04:59:25 PM PDT 24
Peak memory 206756 kb
Host smart-b1876917-82f7-451c-b9ef-a2fcc0d1ae9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37767
47295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.3776747295
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.3406911782
Short name T2062
Test name
Test status
Simulation time 239704324 ps
CPU time 0.9 seconds
Started Jun 25 04:59:28 PM PDT 24
Finished Jun 25 04:59:30 PM PDT 24
Peak memory 206496 kb
Host smart-90925788-0537-4b49-a00a-b7703753e33d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34069
11782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.3406911782
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.192693436
Short name T1200
Test name
Test status
Simulation time 144087112 ps
CPU time 0.77 seconds
Started Jun 25 04:59:32 PM PDT 24
Finished Jun 25 04:59:36 PM PDT 24
Peak memory 206592 kb
Host smart-728da19c-8172-4e0c-bd02-cd4087daee95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19269
3436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.192693436
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.4017125274
Short name T1242
Test name
Test status
Simulation time 194299372 ps
CPU time 0.86 seconds
Started Jun 25 04:59:21 PM PDT 24
Finished Jun 25 04:59:24 PM PDT 24
Peak memory 206532 kb
Host smart-b6038057-f990-449d-a8b7-81ea688f1f41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40171
25274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.4017125274
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.1886151911
Short name T507
Test name
Test status
Simulation time 238682711 ps
CPU time 0.96 seconds
Started Jun 25 04:59:22 PM PDT 24
Finished Jun 25 04:59:24 PM PDT 24
Peak memory 206600 kb
Host smart-c4ea7365-1289-4f2d-88c7-f290cfcf8b92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18861
51911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.1886151911
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.1503009721
Short name T850
Test name
Test status
Simulation time 23265747192 ps
CPU time 22.44 seconds
Started Jun 25 04:59:20 PM PDT 24
Finished Jun 25 04:59:44 PM PDT 24
Peak memory 206664 kb
Host smart-d4c687be-0aa5-419d-af2e-16689aa4c0dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15030
09721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.1503009721
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.3851327627
Short name T2024
Test name
Test status
Simulation time 3343687626 ps
CPU time 4.35 seconds
Started Jun 25 04:59:20 PM PDT 24
Finished Jun 25 04:59:25 PM PDT 24
Peak memory 206688 kb
Host smart-65da905d-ed83-4fb6-a52d-d629d4544800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38513
27627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.3851327627
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.1242883893
Short name T638
Test name
Test status
Simulation time 5980829848 ps
CPU time 53.54 seconds
Started Jun 25 04:59:19 PM PDT 24
Finished Jun 25 05:00:13 PM PDT 24
Peak memory 206888 kb
Host smart-e3155d9b-9da2-4131-b4ab-87bf8b8aad05
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1242883893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.1242883893
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.2920216998
Short name T1946
Test name
Test status
Simulation time 239219251 ps
CPU time 0.88 seconds
Started Jun 25 04:59:29 PM PDT 24
Finished Jun 25 04:59:33 PM PDT 24
Peak memory 206576 kb
Host smart-a17a4ad5-5e1e-4fc5-8ef9-e1d4817e9028
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2920216998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.2920216998
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.1332012357
Short name T1236
Test name
Test status
Simulation time 194641735 ps
CPU time 0.88 seconds
Started Jun 25 04:59:23 PM PDT 24
Finished Jun 25 04:59:25 PM PDT 24
Peak memory 206576 kb
Host smart-9a9168bf-6010-4d60-a45d-69484468cbca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13320
12357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.1332012357
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.3614798138
Short name T1768
Test name
Test status
Simulation time 9767010661 ps
CPU time 68.53 seconds
Started Jun 25 04:59:20 PM PDT 24
Finished Jun 25 05:00:30 PM PDT 24
Peak memory 206920 kb
Host smart-609a7278-b064-4723-b853-3b865fea434c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36147
98138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.3614798138
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.1864132107
Short name T401
Test name
Test status
Simulation time 13803548721 ps
CPU time 98.87 seconds
Started Jun 25 04:59:22 PM PDT 24
Finished Jun 25 05:01:03 PM PDT 24
Peak memory 206956 kb
Host smart-71617486-d68c-4951-91a1-15bc81c28aec
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1864132107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.1864132107
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.634374405
Short name T759
Test name
Test status
Simulation time 190435189 ps
CPU time 0.85 seconds
Started Jun 25 04:59:31 PM PDT 24
Finished Jun 25 04:59:35 PM PDT 24
Peak memory 206516 kb
Host smart-6e38bbbe-d89e-4612-9896-959a0bbd21ce
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=634374405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.634374405
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.3884815290
Short name T1489
Test name
Test status
Simulation time 166632346 ps
CPU time 0.79 seconds
Started Jun 25 04:59:20 PM PDT 24
Finished Jun 25 04:59:22 PM PDT 24
Peak memory 206576 kb
Host smart-e937f342-2274-4c44-86c7-e4be274301be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38848
15290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.3884815290
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.3158554057
Short name T2224
Test name
Test status
Simulation time 242752859 ps
CPU time 0.92 seconds
Started Jun 25 04:59:23 PM PDT 24
Finished Jun 25 04:59:25 PM PDT 24
Peak memory 206512 kb
Host smart-320b2250-a0f2-4637-8459-d31faf853641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31585
54057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.3158554057
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.1822986020
Short name T414
Test name
Test status
Simulation time 179087744 ps
CPU time 0.81 seconds
Started Jun 25 04:59:24 PM PDT 24
Finished Jun 25 04:59:27 PM PDT 24
Peak memory 206480 kb
Host smart-f6c24370-2759-4fdd-aafc-956dfdd8bdda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18229
86020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.1822986020
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.2052374241
Short name T672
Test name
Test status
Simulation time 219984578 ps
CPU time 0.84 seconds
Started Jun 25 04:59:21 PM PDT 24
Finished Jun 25 04:59:23 PM PDT 24
Peak memory 206544 kb
Host smart-bc5f9e35-b866-4d70-8993-f46d30816025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20523
74241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.2052374241
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.867334603
Short name T610
Test name
Test status
Simulation time 150180673 ps
CPU time 0.76 seconds
Started Jun 25 04:59:31 PM PDT 24
Finished Jun 25 04:59:35 PM PDT 24
Peak memory 206384 kb
Host smart-c8062fbd-a649-4c35-9018-7d3dcd705118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86733
4603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.867334603
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.859551268
Short name T385
Test name
Test status
Simulation time 206218373 ps
CPU time 0.92 seconds
Started Jun 25 04:59:22 PM PDT 24
Finished Jun 25 04:59:25 PM PDT 24
Peak memory 206508 kb
Host smart-c58ad497-89bf-4e1a-b757-f87e21d8574b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=859551268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.859551268
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.2443554663
Short name T779
Test name
Test status
Simulation time 150131407 ps
CPU time 0.73 seconds
Started Jun 25 04:59:20 PM PDT 24
Finished Jun 25 04:59:22 PM PDT 24
Peak memory 206504 kb
Host smart-228bfe6a-2b20-4463-bba3-8566a8e469ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24435
54663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.2443554663
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.1405876707
Short name T1394
Test name
Test status
Simulation time 82282092 ps
CPU time 0.68 seconds
Started Jun 25 04:59:31 PM PDT 24
Finished Jun 25 04:59:35 PM PDT 24
Peak memory 206372 kb
Host smart-88798851-b8a3-42f5-a41a-b9f8a2d544f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14058
76707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.1405876707
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.198542549
Short name T1755
Test name
Test status
Simulation time 7264412579 ps
CPU time 16.89 seconds
Started Jun 25 04:59:20 PM PDT 24
Finished Jun 25 04:59:37 PM PDT 24
Peak memory 206980 kb
Host smart-9132b5b3-630f-42e2-9bc2-03db33f86786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19854
2549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.198542549
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.3892249958
Short name T500
Test name
Test status
Simulation time 142943521 ps
CPU time 0.74 seconds
Started Jun 25 04:59:19 PM PDT 24
Finished Jun 25 04:59:20 PM PDT 24
Peak memory 206500 kb
Host smart-afe35a79-f6ab-44d4-98c9-5de3e0c9614f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38922
49958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.3892249958
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.3223185136
Short name T468
Test name
Test status
Simulation time 192119288 ps
CPU time 0.86 seconds
Started Jun 25 04:59:20 PM PDT 24
Finished Jun 25 04:59:22 PM PDT 24
Peak memory 206484 kb
Host smart-defbcbfa-a06b-4c18-8934-6b8c2e026dd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32231
85136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.3223185136
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.787173764
Short name T2057
Test name
Test status
Simulation time 226845491 ps
CPU time 0.92 seconds
Started Jun 25 04:59:31 PM PDT 24
Finished Jun 25 04:59:35 PM PDT 24
Peak memory 206620 kb
Host smart-4e7cc289-8084-497c-ac8d-7b23fca670e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78717
3764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.787173764
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.3733636158
Short name T463
Test name
Test status
Simulation time 161692173 ps
CPU time 0.78 seconds
Started Jun 25 04:59:20 PM PDT 24
Finished Jun 25 04:59:22 PM PDT 24
Peak memory 206504 kb
Host smart-39905e08-18d1-4c58-a8e3-b596475d7093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37336
36158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.3733636158
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.854694995
Short name T1786
Test name
Test status
Simulation time 166453810 ps
CPU time 0.81 seconds
Started Jun 25 04:59:21 PM PDT 24
Finished Jun 25 04:59:23 PM PDT 24
Peak memory 206508 kb
Host smart-eab246cc-25e7-462d-b7c8-0cb4881193db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85469
4995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.854694995
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.278090851
Short name T1375
Test name
Test status
Simulation time 152787992 ps
CPU time 0.91 seconds
Started Jun 25 04:59:20 PM PDT 24
Finished Jun 25 04:59:22 PM PDT 24
Peak memory 206600 kb
Host smart-b08041e4-5d57-4443-8914-f14868374251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27809
0851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.278090851
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.1433394842
Short name T399
Test name
Test status
Simulation time 154702636 ps
CPU time 0.79 seconds
Started Jun 25 04:59:22 PM PDT 24
Finished Jun 25 04:59:24 PM PDT 24
Peak memory 206572 kb
Host smart-7973becf-7d10-48c0-a6ee-cdf03b51bf5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14333
94842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.1433394842
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.2085827288
Short name T1086
Test name
Test status
Simulation time 234993265 ps
CPU time 0.88 seconds
Started Jun 25 04:59:19 PM PDT 24
Finished Jun 25 04:59:21 PM PDT 24
Peak memory 206512 kb
Host smart-090b5085-e4dc-4bfb-ad2a-b7436f03319d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20858
27288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.2085827288
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.2737589709
Short name T2303
Test name
Test status
Simulation time 4461457554 ps
CPU time 124.9 seconds
Started Jun 25 04:59:20 PM PDT 24
Finished Jun 25 05:01:26 PM PDT 24
Peak memory 206948 kb
Host smart-aa06b21d-2b6b-4be7-8ae8-b7d0140e73e2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2737589709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.2737589709
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.1934455166
Short name T2033
Test name
Test status
Simulation time 186112394 ps
CPU time 0.87 seconds
Started Jun 25 04:59:20 PM PDT 24
Finished Jun 25 04:59:22 PM PDT 24
Peak memory 206580 kb
Host smart-156597fe-1fbc-4328-a62e-56e06ace8a1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19344
55166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.1934455166
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.666623785
Short name T516
Test name
Test status
Simulation time 149546052 ps
CPU time 0.81 seconds
Started Jun 25 04:59:22 PM PDT 24
Finished Jun 25 04:59:24 PM PDT 24
Peak memory 206448 kb
Host smart-8acb3744-b397-4667-984e-9bbc7ec7ac3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66662
3785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.666623785
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.3053398476
Short name T597
Test name
Test status
Simulation time 4283449090 ps
CPU time 31.37 seconds
Started Jun 25 04:59:23 PM PDT 24
Finished Jun 25 04:59:55 PM PDT 24
Peak memory 206860 kb
Host smart-9285bd4d-05b1-4c12-972e-c44dc418d854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30533
98476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.3053398476
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.2737236020
Short name T1828
Test name
Test status
Simulation time 4225136658 ps
CPU time 5.29 seconds
Started Jun 25 04:56:23 PM PDT 24
Finished Jun 25 04:56:30 PM PDT 24
Peak memory 206716 kb
Host smart-d394e204-ab0d-461e-a404-cfae2d3e4f79
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2737236020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.2737236020
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.348474267
Short name T187
Test name
Test status
Simulation time 23418400309 ps
CPU time 25.01 seconds
Started Jun 25 04:56:22 PM PDT 24
Finished Jun 25 04:56:48 PM PDT 24
Peak memory 206928 kb
Host smart-61f1d6d3-9c18-4f8a-b63d-5e2c324783cf
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=348474267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.348474267
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.2674427801
Short name T2129
Test name
Test status
Simulation time 158312585 ps
CPU time 0.82 seconds
Started Jun 25 04:56:24 PM PDT 24
Finished Jun 25 04:56:27 PM PDT 24
Peak memory 206496 kb
Host smart-38165aed-b8db-4c46-b213-5c9f597be7b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26744
27801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.2674427801
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.3177361891
Short name T66
Test name
Test status
Simulation time 155572652 ps
CPU time 0.79 seconds
Started Jun 25 04:56:23 PM PDT 24
Finished Jun 25 04:56:26 PM PDT 24
Peak memory 206568 kb
Host smart-bfa4bc64-7bd2-4833-b20f-7ff42fa296b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31773
61891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.3177361891
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.2102276663
Short name T2354
Test name
Test status
Simulation time 143868910 ps
CPU time 0.8 seconds
Started Jun 25 04:56:25 PM PDT 24
Finished Jun 25 04:56:29 PM PDT 24
Peak memory 206520 kb
Host smart-3fe7af9f-a894-4608-8adb-098ca29f2367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21022
76663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.2102276663
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.3001235087
Short name T2323
Test name
Test status
Simulation time 341678575 ps
CPU time 1.21 seconds
Started Jun 25 04:56:24 PM PDT 24
Finished Jun 25 04:56:27 PM PDT 24
Peak memory 206568 kb
Host smart-645fabf4-b71b-4deb-ae74-af785dcb6fc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30012
35087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.3001235087
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.982839321
Short name T1658
Test name
Test status
Simulation time 523033575 ps
CPU time 1.4 seconds
Started Jun 25 04:56:24 PM PDT 24
Finished Jun 25 04:56:27 PM PDT 24
Peak memory 206588 kb
Host smart-a22806c7-0a5b-4abc-9a9e-3ec9c160bb3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98283
9321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.982839321
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.3550779488
Short name T1814
Test name
Test status
Simulation time 7363734410 ps
CPU time 16.12 seconds
Started Jun 25 04:56:23 PM PDT 24
Finished Jun 25 04:56:40 PM PDT 24
Peak memory 206864 kb
Host smart-7aefc920-3847-460c-a942-c38eba63f54c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35507
79488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.3550779488
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.2853270003
Short name T568
Test name
Test status
Simulation time 189102811 ps
CPU time 0.81 seconds
Started Jun 25 04:56:25 PM PDT 24
Finished Jun 25 04:56:28 PM PDT 24
Peak memory 206476 kb
Host smart-36a05d53-eb8f-46db-a4a1-d1a632296ad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28532
70003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.2853270003
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.3611939248
Short name T1654
Test name
Test status
Simulation time 38345497 ps
CPU time 0.65 seconds
Started Jun 25 04:56:24 PM PDT 24
Finished Jun 25 04:56:27 PM PDT 24
Peak memory 206556 kb
Host smart-8b4ecb07-3704-43b1-856f-32c3a6c7b0d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36119
39248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.3611939248
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.1123565154
Short name T1552
Test name
Test status
Simulation time 1023363363 ps
CPU time 2.2 seconds
Started Jun 25 04:56:24 PM PDT 24
Finished Jun 25 04:56:28 PM PDT 24
Peak memory 206824 kb
Host smart-7f7395c3-91b1-4c90-a77b-5d9d33e2e434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11235
65154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.1123565154
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.1950950813
Short name T1050
Test name
Test status
Simulation time 246195248 ps
CPU time 1.51 seconds
Started Jun 25 04:56:25 PM PDT 24
Finished Jun 25 04:56:29 PM PDT 24
Peak memory 206824 kb
Host smart-e9d867f3-5d3a-437d-9c74-fc5d25b9d48a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19509
50813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.1950950813
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.4123322982
Short name T721
Test name
Test status
Simulation time 187751144 ps
CPU time 0.85 seconds
Started Jun 25 04:56:40 PM PDT 24
Finished Jun 25 04:56:42 PM PDT 24
Peak memory 206520 kb
Host smart-393e9634-2dc9-438f-83bd-39e4664317ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41233
22982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.4123322982
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.1738936948
Short name T2383
Test name
Test status
Simulation time 163941341 ps
CPU time 0.79 seconds
Started Jun 25 04:56:34 PM PDT 24
Finished Jun 25 04:56:35 PM PDT 24
Peak memory 206588 kb
Host smart-31be8133-e6cd-4f3b-a02c-9ba4ba23da6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17389
36948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.1738936948
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.1695277685
Short name T723
Test name
Test status
Simulation time 216007965 ps
CPU time 0.92 seconds
Started Jun 25 04:56:27 PM PDT 24
Finished Jun 25 04:56:30 PM PDT 24
Peak memory 206504 kb
Host smart-742d5bae-92e8-4b87-8cc9-c17fbcb37f2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16952
77685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.1695277685
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.1350704159
Short name T1728
Test name
Test status
Simulation time 203886645 ps
CPU time 0.85 seconds
Started Jun 25 04:56:23 PM PDT 24
Finished Jun 25 04:56:25 PM PDT 24
Peak memory 206600 kb
Host smart-fb37033a-2a20-41f5-a966-b2dce55892b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13507
04159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.1350704159
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.2062616732
Short name T821
Test name
Test status
Simulation time 23276894087 ps
CPU time 23.17 seconds
Started Jun 25 04:56:25 PM PDT 24
Finished Jun 25 04:56:50 PM PDT 24
Peak memory 206608 kb
Host smart-916b80fc-898a-41eb-a0d4-eab238ea3fcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20626
16732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.2062616732
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.1154747067
Short name T2176
Test name
Test status
Simulation time 3342995202 ps
CPU time 3.47 seconds
Started Jun 25 04:56:24 PM PDT 24
Finished Jun 25 04:56:29 PM PDT 24
Peak memory 206604 kb
Host smart-fe17e9ba-d772-4bd5-a416-6c8e1193ffcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11547
47067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.1154747067
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.429621049
Short name T1976
Test name
Test status
Simulation time 3231665865 ps
CPU time 22.34 seconds
Started Jun 25 04:56:25 PM PDT 24
Finished Jun 25 04:56:51 PM PDT 24
Peak memory 206880 kb
Host smart-268c4245-71f7-42af-8edb-92f2af2b719c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=429621049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.429621049
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.2411493906
Short name T455
Test name
Test status
Simulation time 250280538 ps
CPU time 0.88 seconds
Started Jun 25 04:56:34 PM PDT 24
Finished Jun 25 04:56:36 PM PDT 24
Peak memory 206520 kb
Host smart-359e3423-8a88-4029-9777-fb5bfcbc5268
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2411493906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.2411493906
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.3840662370
Short name T1877
Test name
Test status
Simulation time 227005651 ps
CPU time 0.92 seconds
Started Jun 25 04:56:23 PM PDT 24
Finished Jun 25 04:56:26 PM PDT 24
Peak memory 206524 kb
Host smart-ae5add34-823e-4e95-959f-9bc758bc85f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38406
62370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.3840662370
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.1402253213
Short name T1206
Test name
Test status
Simulation time 5516553664 ps
CPU time 152.39 seconds
Started Jun 25 04:56:28 PM PDT 24
Finished Jun 25 04:59:02 PM PDT 24
Peak memory 206892 kb
Host smart-2653226a-26f2-46e8-9c86-e347277e378f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14022
53213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.1402253213
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.3041416673
Short name T2285
Test name
Test status
Simulation time 8758839131 ps
CPU time 223.66 seconds
Started Jun 25 04:56:25 PM PDT 24
Finished Jun 25 05:00:11 PM PDT 24
Peak memory 206892 kb
Host smart-ec3fc551-2dcb-4683-bcd4-4bd9d3bd5d18
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3041416673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.3041416673
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.1411998424
Short name T888
Test name
Test status
Simulation time 186499101 ps
CPU time 0.84 seconds
Started Jun 25 04:56:36 PM PDT 24
Finished Jun 25 04:56:38 PM PDT 24
Peak memory 206576 kb
Host smart-a719e2d6-0864-42d9-b796-fb73209c10f7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1411998424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.1411998424
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.648508211
Short name T2392
Test name
Test status
Simulation time 202233905 ps
CPU time 0.84 seconds
Started Jun 25 04:56:23 PM PDT 24
Finished Jun 25 04:56:25 PM PDT 24
Peak memory 206576 kb
Host smart-9f80e569-9825-4f00-9de6-23e3bfa3cacc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64850
8211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.648508211
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.2172297328
Short name T144
Test name
Test status
Simulation time 173150924 ps
CPU time 0.83 seconds
Started Jun 25 04:56:24 PM PDT 24
Finished Jun 25 04:56:27 PM PDT 24
Peak memory 206512 kb
Host smart-f3e68053-ba53-409e-8cc8-2e77be057250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21722
97328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.2172297328
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.3351495239
Short name T102
Test name
Test status
Simulation time 157796779 ps
CPU time 0.79 seconds
Started Jun 25 04:56:26 PM PDT 24
Finished Jun 25 04:56:30 PM PDT 24
Peak memory 206504 kb
Host smart-21810940-3530-4d10-a3a5-3b39996ab004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33514
95239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.3351495239
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.3979717923
Short name T428
Test name
Test status
Simulation time 161472210 ps
CPU time 0.83 seconds
Started Jun 25 04:56:26 PM PDT 24
Finished Jun 25 04:56:29 PM PDT 24
Peak memory 206560 kb
Host smart-f016138c-3108-43bc-9d10-cbe084524597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39797
17923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.3979717923
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.862582287
Short name T907
Test name
Test status
Simulation time 181831179 ps
CPU time 0.81 seconds
Started Jun 25 04:56:25 PM PDT 24
Finished Jun 25 04:56:29 PM PDT 24
Peak memory 206512 kb
Host smart-3a1d6b96-a066-4804-8167-b97b6291d3ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86258
2287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.862582287
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.632438685
Short name T461
Test name
Test status
Simulation time 149369716 ps
CPU time 0.78 seconds
Started Jun 25 04:56:36 PM PDT 24
Finished Jun 25 04:56:38 PM PDT 24
Peak memory 206496 kb
Host smart-1bf35436-6eed-4829-8f53-b8cf55b42a66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63243
8685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.632438685
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.2194359340
Short name T490
Test name
Test status
Simulation time 231765372 ps
CPU time 0.9 seconds
Started Jun 25 04:56:25 PM PDT 24
Finished Jun 25 04:56:28 PM PDT 24
Peak memory 206516 kb
Host smart-3d0d58de-0396-42a1-829b-79f932de3d92
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2194359340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.2194359340
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.4187247775
Short name T2470
Test name
Test status
Simulation time 276560543 ps
CPU time 1.02 seconds
Started Jun 25 04:56:28 PM PDT 24
Finished Jun 25 04:56:31 PM PDT 24
Peak memory 206504 kb
Host smart-fa1ad653-cfd7-4c2b-8ea1-cf24dd2f32fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41872
47775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.4187247775
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.3581406491
Short name T1006
Test name
Test status
Simulation time 143396687 ps
CPU time 0.82 seconds
Started Jun 25 04:56:24 PM PDT 24
Finished Jun 25 04:56:27 PM PDT 24
Peak memory 206584 kb
Host smart-029cf6f5-f6cc-4c2a-a09d-1cbeddb46c9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35814
06491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.3581406491
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.2693969335
Short name T1320
Test name
Test status
Simulation time 55881559 ps
CPU time 0.69 seconds
Started Jun 25 04:56:39 PM PDT 24
Finished Jun 25 04:56:42 PM PDT 24
Peak memory 206368 kb
Host smart-7dda0f46-ee0f-4bb5-ac9f-1dd096f0b3b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26939
69335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.2693969335
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.2629374624
Short name T1965
Test name
Test status
Simulation time 17474862561 ps
CPU time 37.79 seconds
Started Jun 25 04:56:26 PM PDT 24
Finished Jun 25 04:57:06 PM PDT 24
Peak memory 206908 kb
Host smart-edd812f1-e43c-47d6-a9fb-3c2fef3e029f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26293
74624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.2629374624
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.1344112327
Short name T1628
Test name
Test status
Simulation time 214087244 ps
CPU time 0.91 seconds
Started Jun 25 04:56:27 PM PDT 24
Finished Jun 25 04:56:30 PM PDT 24
Peak memory 206596 kb
Host smart-04883774-1ac2-401d-af8f-45549932af56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13441
12327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.1344112327
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.3420337989
Short name T1498
Test name
Test status
Simulation time 199880629 ps
CPU time 0.84 seconds
Started Jun 25 04:56:24 PM PDT 24
Finished Jun 25 04:56:27 PM PDT 24
Peak memory 206568 kb
Host smart-9b547186-90f5-4b07-a1a7-b1b65af886bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34203
37989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.3420337989
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.4272744929
Short name T47
Test name
Test status
Simulation time 32864470248 ps
CPU time 792.7 seconds
Started Jun 25 04:56:26 PM PDT 24
Finished Jun 25 05:09:42 PM PDT 24
Peak memory 206920 kb
Host smart-eff61688-a957-402c-a89b-70a95794dab6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4272744929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.4272744929
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.3432868567
Short name T769
Test name
Test status
Simulation time 24301664167 ps
CPU time 184.78 seconds
Started Jun 25 04:56:25 PM PDT 24
Finished Jun 25 04:59:32 PM PDT 24
Peak memory 206928 kb
Host smart-ed4f2cdc-c2a1-4f6f-a03e-00c31096e061
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3432868567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.3432868567
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.2349961636
Short name T1677
Test name
Test status
Simulation time 12771472842 ps
CPU time 71.25 seconds
Started Jun 25 04:56:25 PM PDT 24
Finished Jun 25 04:57:39 PM PDT 24
Peak memory 207008 kb
Host smart-e16b55b4-6981-47a3-9718-ee0212f970a2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2349961636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.2349961636
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.1587164992
Short name T2019
Test name
Test status
Simulation time 233676369 ps
CPU time 0.93 seconds
Started Jun 25 04:56:35 PM PDT 24
Finished Jun 25 04:56:37 PM PDT 24
Peak memory 206488 kb
Host smart-c38cc7d5-2b40-49dd-9d2b-385c646d900f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15871
64992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.1587164992
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.39601866
Short name T1349
Test name
Test status
Simulation time 214702557 ps
CPU time 0.88 seconds
Started Jun 25 04:56:24 PM PDT 24
Finished Jun 25 04:56:28 PM PDT 24
Peak memory 206508 kb
Host smart-234d9b2d-25c6-4b41-9b72-9cefddbf3a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39601
866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.39601866
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.393034659
Short name T78
Test name
Test status
Simulation time 189306577 ps
CPU time 0.85 seconds
Started Jun 25 04:56:27 PM PDT 24
Finished Jun 25 04:56:30 PM PDT 24
Peak memory 206600 kb
Host smart-f7208c88-66dc-4f20-b678-f2d02cf472a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39303
4659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.393034659
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.1782613128
Short name T80
Test name
Test status
Simulation time 236317701 ps
CPU time 0.9 seconds
Started Jun 25 04:56:25 PM PDT 24
Finished Jun 25 04:56:29 PM PDT 24
Peak memory 206576 kb
Host smart-384dd1c3-40b5-4967-8aac-a6f52ea64d2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17826
13128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.1782613128
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.753574624
Short name T191
Test name
Test status
Simulation time 250051879 ps
CPU time 1.12 seconds
Started Jun 25 04:56:37 PM PDT 24
Finished Jun 25 04:56:40 PM PDT 24
Peak memory 224332 kb
Host smart-91c9da20-0d11-43d7-afd1-42ec0e9db1e1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=753574624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.753574624
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.495858389
Short name T57
Test name
Test status
Simulation time 396738718 ps
CPU time 1.28 seconds
Started Jun 25 04:56:25 PM PDT 24
Finished Jun 25 04:56:29 PM PDT 24
Peak memory 206576 kb
Host smart-da582deb-be43-450f-afc7-63883e67ff2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49585
8389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.495858389
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.925492640
Short name T2241
Test name
Test status
Simulation time 186605090 ps
CPU time 0.84 seconds
Started Jun 25 04:56:34 PM PDT 24
Finished Jun 25 04:56:36 PM PDT 24
Peak memory 206504 kb
Host smart-a7434c9b-aa92-4c01-a145-f0bcc6efbbe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92549
2640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.925492640
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.1576892943
Short name T2068
Test name
Test status
Simulation time 157595663 ps
CPU time 0.81 seconds
Started Jun 25 04:56:39 PM PDT 24
Finished Jun 25 04:56:42 PM PDT 24
Peak memory 206492 kb
Host smart-9bfe400e-f378-435f-8e7a-b4a8986a3597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15768
92943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.1576892943
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.2148204248
Short name T1682
Test name
Test status
Simulation time 194409415 ps
CPU time 0.87 seconds
Started Jun 25 04:56:36 PM PDT 24
Finished Jun 25 04:56:39 PM PDT 24
Peak memory 206524 kb
Host smart-65be942e-59fe-491e-b216-9fadd2f93a67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21482
04248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.2148204248
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.2743940503
Short name T1419
Test name
Test status
Simulation time 11861514264 ps
CPU time 327.95 seconds
Started Jun 25 04:56:36 PM PDT 24
Finished Jun 25 05:02:05 PM PDT 24
Peak memory 206940 kb
Host smart-872280ba-dede-4d70-9fc2-16f0f01faa53
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2743940503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.2743940503
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.3024400234
Short name T2058
Test name
Test status
Simulation time 162361397 ps
CPU time 0.82 seconds
Started Jun 25 04:56:34 PM PDT 24
Finished Jun 25 04:56:36 PM PDT 24
Peak memory 206476 kb
Host smart-81daa143-902b-4bdd-a449-b4335116a0b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30244
00234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.3024400234
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.1400377525
Short name T334
Test name
Test status
Simulation time 157326266 ps
CPU time 0.78 seconds
Started Jun 25 04:56:39 PM PDT 24
Finished Jun 25 04:56:42 PM PDT 24
Peak memory 206436 kb
Host smart-19f4cd51-8e86-4032-a5d3-bd7b4105e4eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14003
77525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.1400377525
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.2358932970
Short name T1422
Test name
Test status
Simulation time 8717040342 ps
CPU time 249.9 seconds
Started Jun 25 04:56:34 PM PDT 24
Finished Jun 25 05:00:46 PM PDT 24
Peak memory 206872 kb
Host smart-5d7d64ef-0f0b-4c0a-ac3c-8c288f25a9cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23589
32970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.2358932970
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.2451940401
Short name T829
Test name
Test status
Simulation time 4122010253 ps
CPU time 4.55 seconds
Started Jun 25 04:59:30 PM PDT 24
Finished Jun 25 04:59:38 PM PDT 24
Peak memory 206884 kb
Host smart-12076944-2915-48b5-85af-9809d2a025a5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2451940401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.2451940401
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.2231740344
Short name T381
Test name
Test status
Simulation time 13396412035 ps
CPU time 12.3 seconds
Started Jun 25 04:59:30 PM PDT 24
Finished Jun 25 04:59:45 PM PDT 24
Peak memory 206640 kb
Host smart-d25fca8f-d4de-4952-b32e-ac648b0f88d3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2231740344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.2231740344
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.738355214
Short name T557
Test name
Test status
Simulation time 23393479310 ps
CPU time 26.58 seconds
Started Jun 25 04:59:31 PM PDT 24
Finished Jun 25 05:00:01 PM PDT 24
Peak memory 206948 kb
Host smart-7a01d993-b6b1-47b6-bccf-f59fe097c149
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=738355214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.738355214
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.949534139
Short name T702
Test name
Test status
Simulation time 150134361 ps
CPU time 0.81 seconds
Started Jun 25 04:59:28 PM PDT 24
Finished Jun 25 04:59:31 PM PDT 24
Peak memory 206600 kb
Host smart-8ea6f4ad-fe7a-43e3-b334-fbef77584184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94953
4139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.949534139
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.1970862347
Short name T1756
Test name
Test status
Simulation time 148094876 ps
CPU time 0.79 seconds
Started Jun 25 04:59:32 PM PDT 24
Finished Jun 25 04:59:36 PM PDT 24
Peak memory 206380 kb
Host smart-043af390-6b8b-435f-a3f4-87d739365258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19708
62347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.1970862347
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.2440328256
Short name T1013
Test name
Test status
Simulation time 272682758 ps
CPU time 1 seconds
Started Jun 25 04:59:31 PM PDT 24
Finished Jun 25 04:59:35 PM PDT 24
Peak memory 206576 kb
Host smart-f0f11676-5887-46a2-b18b-399bdf4a3db5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24403
28256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.2440328256
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.1587915602
Short name T162
Test name
Test status
Simulation time 1436110498 ps
CPU time 3.06 seconds
Started Jun 25 04:59:31 PM PDT 24
Finished Jun 25 04:59:37 PM PDT 24
Peak memory 206732 kb
Host smart-61d092dd-6612-42d4-bf5d-0603157dd1b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15879
15602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.1587915602
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.1684280918
Short name T1906
Test name
Test status
Simulation time 17838453735 ps
CPU time 36.55 seconds
Started Jun 25 04:59:29 PM PDT 24
Finished Jun 25 05:00:07 PM PDT 24
Peak memory 206932 kb
Host smart-14c4036c-109c-4f14-9d57-9bf8c10ad692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16842
80918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.1684280918
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.3128252556
Short name T3
Test name
Test status
Simulation time 488887712 ps
CPU time 1.47 seconds
Started Jun 25 04:59:29 PM PDT 24
Finished Jun 25 04:59:33 PM PDT 24
Peak memory 206572 kb
Host smart-08d4b090-d157-47a7-93dc-574c93e5f654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31282
52556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.3128252556
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.1977021953
Short name T690
Test name
Test status
Simulation time 141707733 ps
CPU time 0.76 seconds
Started Jun 25 04:59:27 PM PDT 24
Finished Jun 25 04:59:30 PM PDT 24
Peak memory 206576 kb
Host smart-4651b7e9-c688-4ab9-8d1c-8be0d69702e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19770
21953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.1977021953
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.3985729460
Short name T835
Test name
Test status
Simulation time 28455027 ps
CPU time 0.67 seconds
Started Jun 25 04:59:32 PM PDT 24
Finished Jun 25 04:59:36 PM PDT 24
Peak memory 206392 kb
Host smart-eb1a0b08-8a10-4e83-be30-3817b626ec19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39857
29460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.3985729460
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.1813535360
Short name T1502
Test name
Test status
Simulation time 825990688 ps
CPU time 2.21 seconds
Started Jun 25 04:59:31 PM PDT 24
Finished Jun 25 04:59:36 PM PDT 24
Peak memory 206812 kb
Host smart-3432205c-eeee-4eed-a554-f15f8708e4c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18135
35360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.1813535360
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.2794641989
Short name T1056
Test name
Test status
Simulation time 179486743 ps
CPU time 1.33 seconds
Started Jun 25 04:59:28 PM PDT 24
Finished Jun 25 04:59:31 PM PDT 24
Peak memory 206728 kb
Host smart-3426bc14-4501-446e-87cc-f76411635304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27946
41989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.2794641989
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.314596354
Short name T556
Test name
Test status
Simulation time 289214016 ps
CPU time 0.95 seconds
Started Jun 25 04:59:38 PM PDT 24
Finished Jun 25 04:59:41 PM PDT 24
Peak memory 206512 kb
Host smart-17a6ffeb-9c01-4aa6-81b0-bcdd36fe76f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31459
6354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.314596354
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.2529746542
Short name T928
Test name
Test status
Simulation time 143403413 ps
CPU time 0.76 seconds
Started Jun 25 04:59:38 PM PDT 24
Finished Jun 25 04:59:40 PM PDT 24
Peak memory 206492 kb
Host smart-4f451276-036f-4b37-8695-a36bc50fb607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25297
46542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.2529746542
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.491186607
Short name T1113
Test name
Test status
Simulation time 170959273 ps
CPU time 0.84 seconds
Started Jun 25 04:59:28 PM PDT 24
Finished Jun 25 04:59:31 PM PDT 24
Peak memory 206568 kb
Host smart-5597cdff-6760-4fc8-adad-a37a8d7ff3e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49118
6607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.491186607
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.267049718
Short name T2322
Test name
Test status
Simulation time 277817960 ps
CPU time 0.99 seconds
Started Jun 25 04:59:28 PM PDT 24
Finished Jun 25 04:59:30 PM PDT 24
Peak memory 206460 kb
Host smart-bb936d83-36c3-477c-aa06-8881d363968a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26704
9718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.267049718
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.314032560
Short name T1901
Test name
Test status
Simulation time 23379609720 ps
CPU time 21.58 seconds
Started Jun 25 04:59:30 PM PDT 24
Finished Jun 25 04:59:54 PM PDT 24
Peak memory 206632 kb
Host smart-58121cb9-4f83-4a26-af17-5a6b8300f588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31403
2560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.314032560
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.3873269620
Short name T2362
Test name
Test status
Simulation time 3314057921 ps
CPU time 3.81 seconds
Started Jun 25 04:59:29 PM PDT 24
Finished Jun 25 04:59:35 PM PDT 24
Peak memory 206628 kb
Host smart-d0a9fc4d-bb2c-4d85-b88c-dcf66922c6fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38732
69620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.3873269620
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.3132490164
Short name T370
Test name
Test status
Simulation time 9173860826 ps
CPU time 264.07 seconds
Started Jun 25 04:59:29 PM PDT 24
Finished Jun 25 05:03:56 PM PDT 24
Peak memory 206920 kb
Host smart-62ed430d-a6ef-4aad-a7de-fbb2081f84a6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3132490164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.3132490164
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.1981692940
Short name T705
Test name
Test status
Simulation time 262518200 ps
CPU time 0.91 seconds
Started Jun 25 04:59:37 PM PDT 24
Finished Jun 25 04:59:39 PM PDT 24
Peak memory 206492 kb
Host smart-e82fed7a-5de4-4fec-bf12-f8017362744b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1981692940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.1981692940
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.2467865906
Short name T2055
Test name
Test status
Simulation time 191243713 ps
CPU time 0.88 seconds
Started Jun 25 04:59:28 PM PDT 24
Finished Jun 25 04:59:30 PM PDT 24
Peak memory 206536 kb
Host smart-041b6153-496c-475a-a631-3dbf8951a378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24678
65906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.2467865906
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.2858507347
Short name T1534
Test name
Test status
Simulation time 7703978206 ps
CPU time 54.77 seconds
Started Jun 25 04:59:32 PM PDT 24
Finished Jun 25 05:00:30 PM PDT 24
Peak memory 206964 kb
Host smart-98183e5c-32e5-485a-9e49-f85c623297f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28585
07347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.2858507347
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.2227197958
Short name T1669
Test name
Test status
Simulation time 3115735197 ps
CPU time 83.7 seconds
Started Jun 25 04:59:31 PM PDT 24
Finished Jun 25 05:00:57 PM PDT 24
Peak memory 206968 kb
Host smart-639b03bf-984c-4527-a1e5-28ae72fe6caa
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2227197958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.2227197958
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.2870166272
Short name T1960
Test name
Test status
Simulation time 156363366 ps
CPU time 0.82 seconds
Started Jun 25 04:59:40 PM PDT 24
Finished Jun 25 04:59:44 PM PDT 24
Peak memory 206584 kb
Host smart-93679243-9f69-434c-aa85-7893fb8864a1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2870166272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.2870166272
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.2505326575
Short name T1311
Test name
Test status
Simulation time 175451656 ps
CPU time 0.87 seconds
Started Jun 25 04:59:29 PM PDT 24
Finished Jun 25 04:59:32 PM PDT 24
Peak memory 206576 kb
Host smart-4745a9d3-a60a-4046-b8ed-f31837615d91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25053
26575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.2505326575
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.2871990214
Short name T141
Test name
Test status
Simulation time 187024970 ps
CPU time 0.89 seconds
Started Jun 25 04:59:27 PM PDT 24
Finished Jun 25 04:59:29 PM PDT 24
Peak memory 206500 kb
Host smart-32f98d4f-e112-446a-b625-ea603eb3a375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28719
90214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.2871990214
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.3579464062
Short name T2334
Test name
Test status
Simulation time 167652558 ps
CPU time 0.82 seconds
Started Jun 25 04:59:30 PM PDT 24
Finished Jun 25 04:59:34 PM PDT 24
Peak memory 206568 kb
Host smart-e0e1ebd8-29c7-4309-8243-ba09256dbede
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35794
64062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.3579464062
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.3081631699
Short name T873
Test name
Test status
Simulation time 166494731 ps
CPU time 0.81 seconds
Started Jun 25 04:59:31 PM PDT 24
Finished Jun 25 04:59:35 PM PDT 24
Peak memory 206600 kb
Host smart-0140a02f-7412-48e8-b8f1-356f454b60f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30816
31699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.3081631699
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.44613384
Short name T900
Test name
Test status
Simulation time 153632474 ps
CPU time 0.81 seconds
Started Jun 25 04:59:30 PM PDT 24
Finished Jun 25 04:59:33 PM PDT 24
Peak memory 206504 kb
Host smart-5bdbec97-c9f0-4233-8477-c5bd22b986f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44613
384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.44613384
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.3062452010
Short name T1118
Test name
Test status
Simulation time 156159149 ps
CPU time 0.84 seconds
Started Jun 25 04:59:41 PM PDT 24
Finished Jun 25 04:59:46 PM PDT 24
Peak memory 206504 kb
Host smart-1f0f6adf-8e2b-4c8e-8f40-4f5259c222ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30624
52010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.3062452010
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.1574329747
Short name T1875
Test name
Test status
Simulation time 292219282 ps
CPU time 1.05 seconds
Started Jun 25 04:59:34 PM PDT 24
Finished Jun 25 04:59:38 PM PDT 24
Peak memory 206600 kb
Host smart-dea8267b-83cc-4d58-b59d-70305da89c90
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1574329747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.1574329747
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.1786249252
Short name T626
Test name
Test status
Simulation time 152746607 ps
CPU time 0.82 seconds
Started Jun 25 04:59:30 PM PDT 24
Finished Jun 25 04:59:33 PM PDT 24
Peak memory 206576 kb
Host smart-a0230908-ed99-49e1-905f-b9e0d0de215a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17862
49252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.1786249252
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.1761269813
Short name T39
Test name
Test status
Simulation time 111292527 ps
CPU time 0.72 seconds
Started Jun 25 04:59:39 PM PDT 24
Finished Jun 25 04:59:43 PM PDT 24
Peak memory 206564 kb
Host smart-bf71b48f-e514-4026-a7a1-82a3de0a3b15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17612
69813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.1761269813
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.1419116634
Short name T92
Test name
Test status
Simulation time 14649140062 ps
CPU time 35.47 seconds
Started Jun 25 04:59:30 PM PDT 24
Finished Jun 25 05:00:09 PM PDT 24
Peak memory 206904 kb
Host smart-9d212763-3836-46bf-9bb3-57b4751d3760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14191
16634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.1419116634
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.2674748286
Short name T1944
Test name
Test status
Simulation time 157936564 ps
CPU time 0.8 seconds
Started Jun 25 04:59:38 PM PDT 24
Finished Jun 25 04:59:40 PM PDT 24
Peak memory 206492 kb
Host smart-20208f0d-6db9-46c1-8dee-53734fde0a2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26747
48286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.2674748286
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.1532377499
Short name T520
Test name
Test status
Simulation time 245216726 ps
CPU time 0.94 seconds
Started Jun 25 04:59:38 PM PDT 24
Finished Jun 25 04:59:40 PM PDT 24
Peak memory 206516 kb
Host smart-e5673cb6-c342-47ba-977a-0780228b4ed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15323
77499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.1532377499
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.3288807641
Short name T1472
Test name
Test status
Simulation time 200836677 ps
CPU time 0.85 seconds
Started Jun 25 04:59:40 PM PDT 24
Finished Jun 25 04:59:44 PM PDT 24
Peak memory 206540 kb
Host smart-687f6857-4799-4dbb-91e6-c3856986e8de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32888
07641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.3288807641
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.3454115282
Short name T822
Test name
Test status
Simulation time 152510185 ps
CPU time 0.77 seconds
Started Jun 25 04:59:43 PM PDT 24
Finished Jun 25 04:59:46 PM PDT 24
Peak memory 206484 kb
Host smart-45eae951-6c3d-4afe-b4b1-943d50d9ac7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34541
15282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.3454115282
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.2983283724
Short name T1690
Test name
Test status
Simulation time 146415705 ps
CPU time 0.76 seconds
Started Jun 25 04:59:37 PM PDT 24
Finished Jun 25 04:59:39 PM PDT 24
Peak memory 206468 kb
Host smart-dfeab49f-07f0-4522-bc7f-26e10377e939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29832
83724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.2983283724
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.341503369
Short name T2140
Test name
Test status
Simulation time 149331142 ps
CPU time 0.86 seconds
Started Jun 25 04:59:38 PM PDT 24
Finished Jun 25 04:59:41 PM PDT 24
Peak memory 206588 kb
Host smart-48fb46fd-12ed-4639-b0c9-fc6c182b7fd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34150
3369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.341503369
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.2281082116
Short name T1104
Test name
Test status
Simulation time 224221402 ps
CPU time 0.79 seconds
Started Jun 25 04:59:40 PM PDT 24
Finished Jun 25 04:59:44 PM PDT 24
Peak memory 206556 kb
Host smart-4159038a-e967-49be-9850-0d971b54d10e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22810
82116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.2281082116
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.2997830511
Short name T589
Test name
Test status
Simulation time 209035919 ps
CPU time 0.9 seconds
Started Jun 25 04:59:41 PM PDT 24
Finished Jun 25 04:59:45 PM PDT 24
Peak memory 206612 kb
Host smart-33070152-6084-49d3-a7b0-8b5602052b81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29978
30511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.2997830511
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.1942908503
Short name T1097
Test name
Test status
Simulation time 10409178083 ps
CPU time 290.68 seconds
Started Jun 25 04:59:39 PM PDT 24
Finished Jun 25 05:04:32 PM PDT 24
Peak memory 206876 kb
Host smart-1b869dee-e82b-4303-b5c5-41e4adec9bfe
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1942908503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.1942908503
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.1719645314
Short name T1442
Test name
Test status
Simulation time 170416425 ps
CPU time 0.77 seconds
Started Jun 25 04:59:39 PM PDT 24
Finished Jun 25 04:59:43 PM PDT 24
Peak memory 206584 kb
Host smart-149d2ae2-31cb-4cb8-bcfe-83797c5158ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17196
45314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.1719645314
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.296935218
Short name T450
Test name
Test status
Simulation time 161052585 ps
CPU time 0.84 seconds
Started Jun 25 04:59:40 PM PDT 24
Finished Jun 25 04:59:44 PM PDT 24
Peak memory 206508 kb
Host smart-99a3f9ab-b614-4152-af05-0cbaaa336a57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29693
5218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.296935218
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.1190798479
Short name T5
Test name
Test status
Simulation time 5714916968 ps
CPU time 51.82 seconds
Started Jun 25 04:59:40 PM PDT 24
Finished Jun 25 05:00:35 PM PDT 24
Peak memory 206896 kb
Host smart-ca0d5cdc-0f68-4ba1-b306-90ae11a648e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11907
98479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.1190798479
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.3691075278
Short name T1842
Test name
Test status
Simulation time 3476969596 ps
CPU time 4.18 seconds
Started Jun 25 04:59:38 PM PDT 24
Finished Jun 25 04:59:44 PM PDT 24
Peak memory 206696 kb
Host smart-d059349d-ce9e-4da5-aa33-88714a9315de
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3691075278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.3691075278
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.3026566894
Short name T1255
Test name
Test status
Simulation time 13503759300 ps
CPU time 12.37 seconds
Started Jun 25 04:59:42 PM PDT 24
Finished Jun 25 04:59:57 PM PDT 24
Peak memory 207024 kb
Host smart-d076de2d-b520-4ef2-b38a-ae02cd602e96
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3026566894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.3026566894
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.1558944993
Short name T1529
Test name
Test status
Simulation time 23332696912 ps
CPU time 25.85 seconds
Started Jun 25 04:59:40 PM PDT 24
Finished Jun 25 05:00:09 PM PDT 24
Peak memory 206676 kb
Host smart-f09e61fc-77c5-4123-8243-aa57b98e0286
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1558944993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.1558944993
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.1177018407
Short name T599
Test name
Test status
Simulation time 167935744 ps
CPU time 0.85 seconds
Started Jun 25 04:59:42 PM PDT 24
Finished Jun 25 04:59:46 PM PDT 24
Peak memory 206600 kb
Host smart-d88c5044-99b0-43ba-afd8-f18cb310638b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11770
18407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.1177018407
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.832287728
Short name T1699
Test name
Test status
Simulation time 152530963 ps
CPU time 0.82 seconds
Started Jun 25 04:59:40 PM PDT 24
Finished Jun 25 04:59:44 PM PDT 24
Peak memory 206568 kb
Host smart-2dff02fd-21cc-4bf5-b40f-f46eccb5b88a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83228
7728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.832287728
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.1412071882
Short name T2465
Test name
Test status
Simulation time 164234769 ps
CPU time 0.81 seconds
Started Jun 25 04:59:39 PM PDT 24
Finished Jun 25 04:59:43 PM PDT 24
Peak memory 206572 kb
Host smart-d6eae6ec-fc0c-452b-a9fc-3a38cbe8cd7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14120
71882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.1412071882
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.3220621391
Short name T2434
Test name
Test status
Simulation time 1393871705 ps
CPU time 2.78 seconds
Started Jun 25 04:59:41 PM PDT 24
Finished Jun 25 04:59:47 PM PDT 24
Peak memory 206804 kb
Host smart-9e10aea6-38cb-40cc-a01f-4f15b04eca68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32206
21391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.3220621391
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.1885779758
Short name T1184
Test name
Test status
Simulation time 6506424734 ps
CPU time 13.07 seconds
Started Jun 25 04:59:42 PM PDT 24
Finished Jun 25 04:59:58 PM PDT 24
Peak memory 206944 kb
Host smart-445282c4-02f5-4811-8170-7c383243f2de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18857
79758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.1885779758
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.3193985819
Short name T1915
Test name
Test status
Simulation time 421899211 ps
CPU time 1.3 seconds
Started Jun 25 04:59:39 PM PDT 24
Finished Jun 25 04:59:42 PM PDT 24
Peak memory 206576 kb
Host smart-5f53d71c-aaa5-4b98-8c75-c56f4d3bf68c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31939
85819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.3193985819
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.2795539278
Short name T372
Test name
Test status
Simulation time 142743946 ps
CPU time 0.76 seconds
Started Jun 25 04:59:42 PM PDT 24
Finished Jun 25 04:59:46 PM PDT 24
Peak memory 206568 kb
Host smart-16567041-2b42-4e8c-8b0a-fedb8920e1a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27955
39278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.2795539278
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.315606961
Short name T2408
Test name
Test status
Simulation time 91700605 ps
CPU time 0.69 seconds
Started Jun 25 04:59:42 PM PDT 24
Finished Jun 25 04:59:46 PM PDT 24
Peak memory 206564 kb
Host smart-39c80799-e965-478b-adc5-7f60030eb83d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31560
6961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.315606961
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.449409160
Short name T1340
Test name
Test status
Simulation time 942499601 ps
CPU time 2.14 seconds
Started Jun 25 04:59:41 PM PDT 24
Finished Jun 25 04:59:47 PM PDT 24
Peak memory 206824 kb
Host smart-f55ca976-4414-432f-b959-b9fba1fa9d07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44940
9160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.449409160
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.3677752965
Short name T1897
Test name
Test status
Simulation time 244274559 ps
CPU time 1.35 seconds
Started Jun 25 04:59:41 PM PDT 24
Finished Jun 25 04:59:46 PM PDT 24
Peak memory 206836 kb
Host smart-33012b8a-82bd-49f7-81b8-3b229900b746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36777
52965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.3677752965
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.3368873258
Short name T2335
Test name
Test status
Simulation time 197249454 ps
CPU time 0.9 seconds
Started Jun 25 04:59:53 PM PDT 24
Finished Jun 25 04:59:55 PM PDT 24
Peak memory 206576 kb
Host smart-8ab74bfd-ecb6-4cad-92d4-1d47e1a6d6ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33688
73258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.3368873258
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.2246586410
Short name T2032
Test name
Test status
Simulation time 136254827 ps
CPU time 0.8 seconds
Started Jun 25 04:59:49 PM PDT 24
Finished Jun 25 04:59:51 PM PDT 24
Peak memory 206504 kb
Host smart-90e038ee-3f2f-4db6-869b-3fc51ffc6b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22465
86410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.2246586410
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.290938189
Short name T1020
Test name
Test status
Simulation time 240355854 ps
CPU time 0.92 seconds
Started Jun 25 04:59:40 PM PDT 24
Finished Jun 25 04:59:44 PM PDT 24
Peak memory 206528 kb
Host smart-2c032b7b-7994-4b35-bdaa-f3f2b0284a9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29093
8189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.290938189
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.3532004334
Short name T1727
Test name
Test status
Simulation time 263134247 ps
CPU time 0.98 seconds
Started Jun 25 04:59:38 PM PDT 24
Finished Jun 25 04:59:42 PM PDT 24
Peak memory 206572 kb
Host smart-1b8e0069-0105-4035-add4-c36adb70426a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35320
04334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.3532004334
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.228664196
Short name T423
Test name
Test status
Simulation time 23309008858 ps
CPU time 22.56 seconds
Started Jun 25 04:59:39 PM PDT 24
Finished Jun 25 05:00:04 PM PDT 24
Peak memory 206628 kb
Host smart-fdd4b06b-9bf5-414e-932f-1f3a392144eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22866
4196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.228664196
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.3370760229
Short name T2199
Test name
Test status
Simulation time 3307135574 ps
CPU time 3.95 seconds
Started Jun 25 04:59:39 PM PDT 24
Finished Jun 25 04:59:46 PM PDT 24
Peak memory 206684 kb
Host smart-27e1c2a6-16f9-448c-8e0e-f5980c6e731d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33707
60229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.3370760229
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.4592796
Short name T501
Test name
Test status
Simulation time 5168352333 ps
CPU time 36.01 seconds
Started Jun 25 04:59:39 PM PDT 24
Finished Jun 25 05:00:17 PM PDT 24
Peak memory 206924 kb
Host smart-0a541699-1830-441d-92bf-675443a89115
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4592796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.4592796
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.3799685213
Short name T2059
Test name
Test status
Simulation time 241759556 ps
CPU time 0.91 seconds
Started Jun 25 04:59:47 PM PDT 24
Finished Jun 25 04:59:49 PM PDT 24
Peak memory 206576 kb
Host smart-2c07eb7d-6258-4381-9aa4-7682e168a248
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3799685213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.3799685213
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.827763861
Short name T1180
Test name
Test status
Simulation time 192922136 ps
CPU time 0.81 seconds
Started Jun 25 04:59:40 PM PDT 24
Finished Jun 25 04:59:44 PM PDT 24
Peak memory 206560 kb
Host smart-a57f041b-ba93-43e3-a90f-c4c07ea0cd53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82776
3861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.827763861
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.3600848288
Short name T1229
Test name
Test status
Simulation time 13477591299 ps
CPU time 366.93 seconds
Started Jun 25 04:59:40 PM PDT 24
Finished Jun 25 05:05:51 PM PDT 24
Peak memory 207224 kb
Host smart-cc300aca-33ad-4162-951a-79153be3e601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36008
48288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.3600848288
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.4148620876
Short name T1093
Test name
Test status
Simulation time 9302693538 ps
CPU time 90.97 seconds
Started Jun 25 04:59:36 PM PDT 24
Finished Jun 25 05:01:09 PM PDT 24
Peak memory 206948 kb
Host smart-c484e559-8b1b-419d-8ac0-96e2be82d064
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4148620876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.4148620876
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.881555553
Short name T2435
Test name
Test status
Simulation time 148234570 ps
CPU time 0.77 seconds
Started Jun 25 04:59:47 PM PDT 24
Finished Jun 25 04:59:49 PM PDT 24
Peak memory 206580 kb
Host smart-08c77f97-3e54-4813-ae82-582d3c7fbc82
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=881555553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.881555553
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.1401515708
Short name T1890
Test name
Test status
Simulation time 148668763 ps
CPU time 0.75 seconds
Started Jun 25 04:59:38 PM PDT 24
Finished Jun 25 04:59:40 PM PDT 24
Peak memory 206516 kb
Host smart-555d42dd-2d04-47fd-a648-0d43352922f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14015
15708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.1401515708
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.3335704327
Short name T1121
Test name
Test status
Simulation time 178818841 ps
CPU time 0.83 seconds
Started Jun 25 04:59:41 PM PDT 24
Finished Jun 25 04:59:46 PM PDT 24
Peak memory 206516 kb
Host smart-ce9cb07f-c779-4e81-8257-789bc82bd21e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33357
04327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.3335704327
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.2044231450
Short name T1033
Test name
Test status
Simulation time 141434182 ps
CPU time 0.82 seconds
Started Jun 25 04:59:41 PM PDT 24
Finished Jun 25 04:59:45 PM PDT 24
Peak memory 206508 kb
Host smart-100e3db2-2e66-46cf-9f7a-e49102fa154b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20442
31450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.2044231450
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.73250813
Short name T71
Test name
Test status
Simulation time 194571424 ps
CPU time 0.88 seconds
Started Jun 25 04:59:38 PM PDT 24
Finished Jun 25 04:59:40 PM PDT 24
Peak memory 206572 kb
Host smart-7978fd1d-4eed-410f-b937-54be610eb96d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73250
813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.73250813
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.4122869463
Short name T209
Test name
Test status
Simulation time 166346211 ps
CPU time 0.8 seconds
Started Jun 25 04:59:38 PM PDT 24
Finished Jun 25 04:59:40 PM PDT 24
Peak memory 206572 kb
Host smart-9a1f1593-009d-4416-ad99-3ee35dcdf2ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41228
69463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.4122869463
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.1723819655
Short name T1863
Test name
Test status
Simulation time 182710646 ps
CPU time 0.84 seconds
Started Jun 25 04:59:39 PM PDT 24
Finished Jun 25 04:59:42 PM PDT 24
Peak memory 206568 kb
Host smart-80917bb0-e8b8-410f-960f-c11032c3b23c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1723819655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.1723819655
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.1976629645
Short name T1099
Test name
Test status
Simulation time 143004916 ps
CPU time 0.84 seconds
Started Jun 25 04:59:38 PM PDT 24
Finished Jun 25 04:59:40 PM PDT 24
Peak memory 206580 kb
Host smart-a4f530bc-895b-4228-8e0a-fe17d943c09c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19766
29645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.1976629645
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.1664125280
Short name T1304
Test name
Test status
Simulation time 81996419 ps
CPU time 0.69 seconds
Started Jun 25 04:59:39 PM PDT 24
Finished Jun 25 04:59:43 PM PDT 24
Peak memory 206500 kb
Host smart-4fa1a74a-18de-45e2-8c79-987f1d072eb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16641
25280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.1664125280
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.406749975
Short name T1803
Test name
Test status
Simulation time 22531900605 ps
CPU time 58.01 seconds
Started Jun 25 04:59:40 PM PDT 24
Finished Jun 25 05:00:42 PM PDT 24
Peak memory 206832 kb
Host smart-4024caab-dc66-46e1-b198-aaa6f5250f3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40674
9975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.406749975
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.338523561
Short name T1226
Test name
Test status
Simulation time 169604203 ps
CPU time 0.8 seconds
Started Jun 25 04:59:39 PM PDT 24
Finished Jun 25 04:59:43 PM PDT 24
Peak memory 206576 kb
Host smart-237c422c-6098-4d65-90a9-f99f6a3e88cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33852
3561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.338523561
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.1884744175
Short name T1501
Test name
Test status
Simulation time 234036287 ps
CPU time 0.92 seconds
Started Jun 25 04:59:39 PM PDT 24
Finished Jun 25 04:59:42 PM PDT 24
Peak memory 206568 kb
Host smart-a386774a-7108-48f7-b167-59fa3daddd7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18847
44175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.1884744175
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.1817506456
Short name T567
Test name
Test status
Simulation time 231845411 ps
CPU time 0.88 seconds
Started Jun 25 04:59:48 PM PDT 24
Finished Jun 25 04:59:51 PM PDT 24
Peak memory 206872 kb
Host smart-ad9bcd31-e4ac-4603-b249-cbd11f118c91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18175
06456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.1817506456
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.489171131
Short name T906
Test name
Test status
Simulation time 181896053 ps
CPU time 0.85 seconds
Started Jun 25 04:59:41 PM PDT 24
Finished Jun 25 04:59:45 PM PDT 24
Peak memory 206500 kb
Host smart-cdc05d1c-e622-4c67-85a8-63660c933a73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48917
1131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.489171131
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.1967157127
Short name T2304
Test name
Test status
Simulation time 166877459 ps
CPU time 0.82 seconds
Started Jun 25 04:59:40 PM PDT 24
Finished Jun 25 04:59:44 PM PDT 24
Peak memory 206588 kb
Host smart-d839d1fa-a94b-4fbd-9416-0b79dc47147b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19671
57127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.1967157127
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.4234351822
Short name T707
Test name
Test status
Simulation time 186248382 ps
CPU time 0.84 seconds
Started Jun 25 04:59:40 PM PDT 24
Finished Jun 25 04:59:44 PM PDT 24
Peak memory 206568 kb
Host smart-12319099-80da-47a3-83d1-3d73a7018deb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42343
51822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.4234351822
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.2765821396
Short name T1758
Test name
Test status
Simulation time 175275642 ps
CPU time 0.8 seconds
Started Jun 25 04:59:38 PM PDT 24
Finished Jun 25 04:59:40 PM PDT 24
Peak memory 206592 kb
Host smart-8e678fc9-89fc-4ce3-9bd5-a7eafbbb8981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27658
21396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.2765821396
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.1664867869
Short name T1770
Test name
Test status
Simulation time 219772614 ps
CPU time 0.9 seconds
Started Jun 25 04:59:42 PM PDT 24
Finished Jun 25 04:59:46 PM PDT 24
Peak memory 206576 kb
Host smart-10e582e1-0306-468a-9070-1995558a682b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16648
67869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.1664867869
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.2348754939
Short name T2048
Test name
Test status
Simulation time 8404574530 ps
CPU time 61.18 seconds
Started Jun 25 04:59:42 PM PDT 24
Finished Jun 25 05:00:46 PM PDT 24
Peak memory 207096 kb
Host smart-f0b43964-c346-4254-93b2-1d936cf57d2a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2348754939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.2348754939
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.2177820179
Short name T1282
Test name
Test status
Simulation time 165525219 ps
CPU time 0.82 seconds
Started Jun 25 04:59:39 PM PDT 24
Finished Jun 25 04:59:43 PM PDT 24
Peak memory 206564 kb
Host smart-5252af89-d146-4018-a1ca-cd2c68c0bbc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21778
20179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.2177820179
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.2545848940
Short name T2276
Test name
Test status
Simulation time 164459530 ps
CPU time 0.82 seconds
Started Jun 25 04:59:42 PM PDT 24
Finished Jun 25 04:59:46 PM PDT 24
Peak memory 206748 kb
Host smart-9ed40a3c-ff4f-4ecd-8820-663699717228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25458
48940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.2545848940
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.1468775133
Short name T2308
Test name
Test status
Simulation time 10008711100 ps
CPU time 281.16 seconds
Started Jun 25 04:59:39 PM PDT 24
Finished Jun 25 05:04:23 PM PDT 24
Peak memory 206932 kb
Host smart-949f3b85-eb80-4032-98bb-25440db76bfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14687
75133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.1468775133
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.1767443788
Short name T1679
Test name
Test status
Simulation time 4020820516 ps
CPU time 4.51 seconds
Started Jun 25 04:59:51 PM PDT 24
Finished Jun 25 04:59:57 PM PDT 24
Peak memory 206864 kb
Host smart-a246baaf-2ee2-4201-8677-614ea56f806b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1767443788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.1767443788
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.1748930605
Short name T446
Test name
Test status
Simulation time 13410184271 ps
CPU time 12.14 seconds
Started Jun 25 04:59:47 PM PDT 24
Finished Jun 25 05:00:00 PM PDT 24
Peak memory 206888 kb
Host smart-67929a8d-0543-4cea-a14d-1f78270d2713
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1748930605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.1748930605
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.1500363112
Short name T2459
Test name
Test status
Simulation time 23378170407 ps
CPU time 28.49 seconds
Started Jun 25 04:59:52 PM PDT 24
Finished Jun 25 05:00:21 PM PDT 24
Peak memory 206932 kb
Host smart-3496fece-0b5a-4e6c-9d33-b077dd1463e4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1500363112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.1500363112
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.3332388028
Short name T908
Test name
Test status
Simulation time 169125921 ps
CPU time 0.84 seconds
Started Jun 25 04:59:46 PM PDT 24
Finished Jun 25 04:59:48 PM PDT 24
Peak memory 206508 kb
Host smart-88407bbc-55c3-4606-b6f9-1cf2eefe0526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33323
88028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.3332388028
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.32440707
Short name T515
Test name
Test status
Simulation time 153122134 ps
CPU time 0.83 seconds
Started Jun 25 04:59:47 PM PDT 24
Finished Jun 25 04:59:50 PM PDT 24
Peak memory 206496 kb
Host smart-94ee5300-bc6f-4581-95f2-7e36f74c4143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32440
707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.32440707
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.2469456990
Short name T1335
Test name
Test status
Simulation time 521450312 ps
CPU time 1.49 seconds
Started Jun 25 04:59:46 PM PDT 24
Finished Jun 25 04:59:49 PM PDT 24
Peak memory 206492 kb
Host smart-4451ce12-beaa-476a-8799-050ff9577e5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24694
56990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.2469456990
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.3234659
Short name T1295
Test name
Test status
Simulation time 586173382 ps
CPU time 1.52 seconds
Started Jun 25 04:59:47 PM PDT 24
Finished Jun 25 04:59:49 PM PDT 24
Peak memory 206592 kb
Host smart-6d9dc560-1774-410e-97c8-3ae4d94f8947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32346
59 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.3234659
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.491513274
Short name T905
Test name
Test status
Simulation time 6556516843 ps
CPU time 12 seconds
Started Jun 25 04:59:45 PM PDT 24
Finished Jun 25 04:59:58 PM PDT 24
Peak memory 206804 kb
Host smart-3f4d31fc-38c8-4974-b6f6-5c4a3429c0aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49151
3274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.491513274
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.4239474438
Short name T1140
Test name
Test status
Simulation time 442065587 ps
CPU time 1.31 seconds
Started Jun 25 04:59:47 PM PDT 24
Finished Jun 25 04:59:49 PM PDT 24
Peak memory 206580 kb
Host smart-7de93316-f5dc-42cf-8616-7fb2bcb9ece7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42394
74438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.4239474438
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.3136411713
Short name T930
Test name
Test status
Simulation time 151160688 ps
CPU time 0.75 seconds
Started Jun 25 04:59:49 PM PDT 24
Finished Jun 25 04:59:51 PM PDT 24
Peak memory 206588 kb
Host smart-ae0ee6a4-3eca-47ce-81df-5d58b85359ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31364
11713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.3136411713
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.453926079
Short name T2300
Test name
Test status
Simulation time 31204086 ps
CPU time 0.68 seconds
Started Jun 25 04:59:46 PM PDT 24
Finished Jun 25 04:59:48 PM PDT 24
Peak memory 206572 kb
Host smart-425a0650-0ecb-4309-a38f-09d3a0ee1857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45392
6079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.453926079
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.2324421039
Short name T629
Test name
Test status
Simulation time 1132161008 ps
CPU time 2.71 seconds
Started Jun 25 04:59:45 PM PDT 24
Finished Jun 25 04:59:49 PM PDT 24
Peak memory 206672 kb
Host smart-81d5925a-c1d1-4187-8cc1-8b6f5944619e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23244
21039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.2324421039
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.3441046676
Short name T2119
Test name
Test status
Simulation time 359493669 ps
CPU time 2.25 seconds
Started Jun 25 04:59:52 PM PDT 24
Finished Jun 25 04:59:55 PM PDT 24
Peak memory 206764 kb
Host smart-2bda475e-03f1-41a8-9c27-8c5b7264f22c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34410
46676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.3441046676
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.1889645024
Short name T2143
Test name
Test status
Simulation time 212806808 ps
CPU time 0.86 seconds
Started Jun 25 04:59:54 PM PDT 24
Finished Jun 25 04:59:57 PM PDT 24
Peak memory 206504 kb
Host smart-92710614-559d-499f-8800-82f2a77354a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18896
45024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.1889645024
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.2636888976
Short name T1135
Test name
Test status
Simulation time 202216633 ps
CPU time 0.81 seconds
Started Jun 25 04:59:53 PM PDT 24
Finished Jun 25 04:59:55 PM PDT 24
Peak memory 206568 kb
Host smart-b5b931b1-44d6-416e-ab68-15f98819e9eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26368
88976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.2636888976
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.329039862
Short name T311
Test name
Test status
Simulation time 172579340 ps
CPU time 0.82 seconds
Started Jun 25 04:59:51 PM PDT 24
Finished Jun 25 04:59:53 PM PDT 24
Peak memory 206564 kb
Host smart-10dc2f67-4a46-404a-8b77-c820434f9674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32903
9862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.329039862
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_invalid_sync.980069408
Short name T2121
Test name
Test status
Simulation time 12340565677 ps
CPU time 341.5 seconds
Started Jun 25 04:59:49 PM PDT 24
Finished Jun 25 05:05:32 PM PDT 24
Peak memory 206904 kb
Host smart-046c8494-8cdd-4f74-801d-59fb861244e8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=980069408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.980069408
Directory /workspace/22.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.3082556564
Short name T61
Test name
Test status
Simulation time 240495157 ps
CPU time 0.87 seconds
Started Jun 25 04:59:50 PM PDT 24
Finished Jun 25 04:59:52 PM PDT 24
Peak memory 206568 kb
Host smart-34b8e658-2a16-413e-afec-edacd0c78eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30825
56564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.3082556564
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.2022209644
Short name T1703
Test name
Test status
Simulation time 23344813405 ps
CPU time 21.32 seconds
Started Jun 25 04:59:45 PM PDT 24
Finished Jun 25 05:00:08 PM PDT 24
Peak memory 206712 kb
Host smart-646908c9-3668-484b-a33d-4be0f28d02c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20222
09644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.2022209644
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.1139386335
Short name T366
Test name
Test status
Simulation time 3352176967 ps
CPU time 4.56 seconds
Started Jun 25 04:59:47 PM PDT 24
Finished Jun 25 04:59:53 PM PDT 24
Peak memory 206716 kb
Host smart-53549f4e-bca8-4efa-a02f-db7008e85e64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11393
86335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.1139386335
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.4133219500
Short name T2051
Test name
Test status
Simulation time 12460326711 ps
CPU time 344.97 seconds
Started Jun 25 04:59:49 PM PDT 24
Finished Jun 25 05:05:36 PM PDT 24
Peak memory 206920 kb
Host smart-6d068d0d-b489-4f91-9e60-c821002ecd1d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4133219500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.4133219500
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.3152303254
Short name T2413
Test name
Test status
Simulation time 244549800 ps
CPU time 0.96 seconds
Started Jun 25 04:59:57 PM PDT 24
Finished Jun 25 05:00:00 PM PDT 24
Peak memory 206752 kb
Host smart-dabfeab5-ce0d-4212-8bd0-b760b8c6ba39
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3152303254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.3152303254
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.1537632898
Short name T1935
Test name
Test status
Simulation time 218710234 ps
CPU time 0.92 seconds
Started Jun 25 04:59:48 PM PDT 24
Finished Jun 25 04:59:50 PM PDT 24
Peak memory 206580 kb
Host smart-db4ad018-61d9-4111-b076-c804810ac81d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15376
32898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.1537632898
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.2356591733
Short name T153
Test name
Test status
Simulation time 9741617271 ps
CPU time 71.85 seconds
Started Jun 25 04:59:48 PM PDT 24
Finished Jun 25 05:01:01 PM PDT 24
Peak memory 206880 kb
Host smart-d3be2334-90c9-4dd9-a50d-93fbbf25e863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23565
91733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.2356591733
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.1966975315
Short name T1021
Test name
Test status
Simulation time 5540512429 ps
CPU time 55.53 seconds
Started Jun 25 04:59:46 PM PDT 24
Finished Jun 25 05:00:43 PM PDT 24
Peak memory 206872 kb
Host smart-5fb90455-f51e-4b26-a33a-24fe549c23ca
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1966975315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.1966975315
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.2470815913
Short name T941
Test name
Test status
Simulation time 204199860 ps
CPU time 0.83 seconds
Started Jun 25 04:59:55 PM PDT 24
Finished Jun 25 04:59:58 PM PDT 24
Peak memory 206576 kb
Host smart-6c10267b-fefa-42c7-927e-4b0f18d228c0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2470815913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.2470815913
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.3637711202
Short name T1350
Test name
Test status
Simulation time 179316510 ps
CPU time 0.81 seconds
Started Jun 25 04:59:48 PM PDT 24
Finished Jun 25 04:59:51 PM PDT 24
Peak memory 206596 kb
Host smart-7e14efa9-ffd6-4e5c-bfa9-abc93d60e669
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36377
11202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.3637711202
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.335566953
Short name T143
Test name
Test status
Simulation time 216632617 ps
CPU time 0.93 seconds
Started Jun 25 04:59:48 PM PDT 24
Finished Jun 25 04:59:51 PM PDT 24
Peak memory 206576 kb
Host smart-d425246d-8b7f-4c74-8a16-d913c93e450c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33556
6953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.335566953
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.2683958155
Short name T2086
Test name
Test status
Simulation time 179319320 ps
CPU time 0.95 seconds
Started Jun 25 04:59:46 PM PDT 24
Finished Jun 25 04:59:48 PM PDT 24
Peak memory 206588 kb
Host smart-c2dfa46e-9609-42a4-8dea-28ac13079470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26839
58155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.2683958155
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.464680825
Short name T1245
Test name
Test status
Simulation time 169018808 ps
CPU time 0.86 seconds
Started Jun 25 04:59:45 PM PDT 24
Finished Jun 25 04:59:47 PM PDT 24
Peak memory 206592 kb
Host smart-7d3303db-3c8a-415b-99b0-55fbdcfc2c31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46468
0825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.464680825
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.3536646566
Short name T675
Test name
Test status
Simulation time 173768567 ps
CPU time 0.8 seconds
Started Jun 25 04:59:53 PM PDT 24
Finished Jun 25 04:59:56 PM PDT 24
Peak memory 206580 kb
Host smart-897247a2-9649-43f1-b352-adbda1a9e7c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35366
46566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.3536646566
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.3240052277
Short name T1172
Test name
Test status
Simulation time 163023998 ps
CPU time 0.78 seconds
Started Jun 25 04:59:55 PM PDT 24
Finished Jun 25 04:59:58 PM PDT 24
Peak memory 206572 kb
Host smart-3c25d12a-f11b-4108-a780-e3128253c4b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32400
52277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.3240052277
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.3536631277
Short name T1196
Test name
Test status
Simulation time 238648494 ps
CPU time 0.93 seconds
Started Jun 25 04:59:50 PM PDT 24
Finished Jun 25 04:59:52 PM PDT 24
Peak memory 206572 kb
Host smart-b792fcd9-8d14-48c8-8430-f70dab07bf90
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3536631277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.3536631277
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.2826671401
Short name T1873
Test name
Test status
Simulation time 163629654 ps
CPU time 0.77 seconds
Started Jun 25 04:59:48 PM PDT 24
Finished Jun 25 04:59:50 PM PDT 24
Peak memory 206600 kb
Host smart-fbf97b4e-ba9b-4cbf-be57-908d53969c4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28266
71401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.2826671401
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.2518401668
Short name T41
Test name
Test status
Simulation time 36625292 ps
CPU time 0.66 seconds
Started Jun 25 05:00:00 PM PDT 24
Finished Jun 25 05:00:02 PM PDT 24
Peak memory 206568 kb
Host smart-1d12a27d-35db-4fc1-8d2b-129bae72db08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25184
01668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.2518401668
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.1820668604
Short name T1605
Test name
Test status
Simulation time 16537467056 ps
CPU time 37.32 seconds
Started Jun 25 04:59:47 PM PDT 24
Finished Jun 25 05:00:26 PM PDT 24
Peak memory 215104 kb
Host smart-e37e1ed0-9581-468b-be76-c50940737ffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18206
68604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.1820668604
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.3423803779
Short name T1619
Test name
Test status
Simulation time 169716513 ps
CPU time 0.83 seconds
Started Jun 25 04:59:48 PM PDT 24
Finished Jun 25 04:59:51 PM PDT 24
Peak memory 206588 kb
Host smart-2c4958be-d13e-4c5e-a3e9-04e57278bfa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34238
03779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.3423803779
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.1282260510
Short name T1227
Test name
Test status
Simulation time 209864811 ps
CPU time 0.87 seconds
Started Jun 25 04:59:47 PM PDT 24
Finished Jun 25 04:59:49 PM PDT 24
Peak memory 206864 kb
Host smart-bebe8b30-9b4f-451f-a700-4a4f74c57317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12822
60510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.1282260510
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.997299696
Short name T2122
Test name
Test status
Simulation time 174113709 ps
CPU time 0.85 seconds
Started Jun 25 04:59:56 PM PDT 24
Finished Jun 25 04:59:59 PM PDT 24
Peak memory 206440 kb
Host smart-146652e5-441c-48d9-8683-f221d1cfe426
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99729
9696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.997299696
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.208003739
Short name T424
Test name
Test status
Simulation time 196855170 ps
CPU time 0.86 seconds
Started Jun 25 04:59:47 PM PDT 24
Finished Jun 25 04:59:50 PM PDT 24
Peak memory 206588 kb
Host smart-f2fbac46-131d-4138-84dd-e97934308341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20800
3739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.208003739
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.1771453525
Short name T2374
Test name
Test status
Simulation time 213058334 ps
CPU time 0.86 seconds
Started Jun 25 04:59:47 PM PDT 24
Finished Jun 25 04:59:50 PM PDT 24
Peak memory 206508 kb
Host smart-a4524e5a-005c-462e-873d-f07bd1c2ea1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17714
53525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.1771453525
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.3632610821
Short name T668
Test name
Test status
Simulation time 152212768 ps
CPU time 0.77 seconds
Started Jun 25 04:59:59 PM PDT 24
Finished Jun 25 05:00:00 PM PDT 24
Peak memory 206328 kb
Host smart-7652e7ca-e449-4167-ab99-2f75fa9bd0e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36326
10821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.3632610821
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.3667436300
Short name T950
Test name
Test status
Simulation time 146951253 ps
CPU time 0.84 seconds
Started Jun 25 04:59:54 PM PDT 24
Finished Jun 25 04:59:57 PM PDT 24
Peak memory 206576 kb
Host smart-fff05dd7-fc87-411a-9b33-8ce9daa2457b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36674
36300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.3667436300
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.528720774
Short name T1627
Test name
Test status
Simulation time 232766599 ps
CPU time 0.98 seconds
Started Jun 25 04:59:53 PM PDT 24
Finished Jun 25 04:59:55 PM PDT 24
Peak memory 206592 kb
Host smart-9fbc323b-39b6-4ac4-a725-88f39ce3b14f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52872
0774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.528720774
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.678983602
Short name T1234
Test name
Test status
Simulation time 11782798675 ps
CPU time 343.66 seconds
Started Jun 25 04:59:53 PM PDT 24
Finished Jun 25 05:05:38 PM PDT 24
Peak memory 206828 kb
Host smart-0a9f45f4-07a3-4b65-b31a-719162cfa633
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=678983602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.678983602
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.621130982
Short name T1136
Test name
Test status
Simulation time 193592016 ps
CPU time 0.9 seconds
Started Jun 25 04:59:54 PM PDT 24
Finished Jun 25 04:59:57 PM PDT 24
Peak memory 206592 kb
Host smart-df29320c-4a5f-4b6b-b95b-9ce2eb75534f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62113
0982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.621130982
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.2521177130
Short name T1241
Test name
Test status
Simulation time 241264931 ps
CPU time 0.89 seconds
Started Jun 25 04:59:53 PM PDT 24
Finished Jun 25 04:59:55 PM PDT 24
Peak memory 206504 kb
Host smart-85f4f7c1-00b9-4c94-9ca6-3f5042daa126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25211
77130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.2521177130
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.488383146
Short name T1319
Test name
Test status
Simulation time 12865866344 ps
CPU time 96.74 seconds
Started Jun 25 04:59:54 PM PDT 24
Finished Jun 25 05:01:33 PM PDT 24
Peak memory 206864 kb
Host smart-af426b09-ded6-4cce-ab81-3c16d6c3cd55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48838
3146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.488383146
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.2254596423
Short name T802
Test name
Test status
Simulation time 4164930429 ps
CPU time 5.03 seconds
Started Jun 25 04:59:54 PM PDT 24
Finished Jun 25 05:00:02 PM PDT 24
Peak memory 206700 kb
Host smart-f15728ea-7a28-4121-b93b-d015b4a39994
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2254596423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.2254596423
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.2984713305
Short name T379
Test name
Test status
Simulation time 13362628703 ps
CPU time 12.17 seconds
Started Jun 25 04:59:54 PM PDT 24
Finished Jun 25 05:00:08 PM PDT 24
Peak memory 206880 kb
Host smart-2ead66f3-a04d-4582-9bda-6488d781c591
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2984713305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.2984713305
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.1666161152
Short name T2095
Test name
Test status
Simulation time 23436036607 ps
CPU time 25.57 seconds
Started Jun 25 05:00:00 PM PDT 24
Finished Jun 25 05:00:27 PM PDT 24
Peak memory 206644 kb
Host smart-488d8973-cd88-4c76-b4c4-88f2b5b94a21
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1666161152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.1666161152
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.2488647382
Short name T150
Test name
Test status
Simulation time 155361295 ps
CPU time 0.78 seconds
Started Jun 25 04:59:52 PM PDT 24
Finished Jun 25 04:59:54 PM PDT 24
Peak memory 206592 kb
Host smart-b481c310-4fc5-4ca3-a91d-7a52febcfcea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24886
47382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.2488647382
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.215681806
Short name T1424
Test name
Test status
Simulation time 168902810 ps
CPU time 0.81 seconds
Started Jun 25 04:59:55 PM PDT 24
Finished Jun 25 04:59:57 PM PDT 24
Peak memory 206576 kb
Host smart-2bad0ab5-7be0-479a-9cf4-fe8ff32dedd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21568
1806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.215681806
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.3871193851
Short name T1790
Test name
Test status
Simulation time 141445383 ps
CPU time 0.85 seconds
Started Jun 25 04:59:54 PM PDT 24
Finished Jun 25 04:59:57 PM PDT 24
Peak memory 206500 kb
Host smart-9202cc16-28e8-47ce-b337-26f15b568671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38711
93851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.3871193851
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.1342911532
Short name T909
Test name
Test status
Simulation time 1159573779 ps
CPU time 2.99 seconds
Started Jun 25 04:59:55 PM PDT 24
Finished Jun 25 05:00:00 PM PDT 24
Peak memory 206680 kb
Host smart-2b62e9ca-79ca-4e26-9da7-2bf5b9762df8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13429
11532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.1342911532
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.2330904195
Short name T1539
Test name
Test status
Simulation time 19110541898 ps
CPU time 35.76 seconds
Started Jun 25 04:59:52 PM PDT 24
Finished Jun 25 05:00:29 PM PDT 24
Peak memory 206848 kb
Host smart-bd140e98-574a-4fe6-8383-3ab37e370596
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23309
04195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.2330904195
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.2193765108
Short name T1745
Test name
Test status
Simulation time 364883803 ps
CPU time 1.15 seconds
Started Jun 25 04:59:52 PM PDT 24
Finished Jun 25 04:59:54 PM PDT 24
Peak memory 206560 kb
Host smart-f2bf006a-5952-4dfe-a288-98c1b0428cf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21937
65108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.2193765108
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.3979194387
Short name T1849
Test name
Test status
Simulation time 162799800 ps
CPU time 0.81 seconds
Started Jun 25 04:59:59 PM PDT 24
Finished Jun 25 05:00:00 PM PDT 24
Peak memory 206568 kb
Host smart-90fa957a-4917-4067-bcd8-3bc1d9139fb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39791
94387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.3979194387
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.1318123063
Short name T2156
Test name
Test status
Simulation time 61140919 ps
CPU time 0.68 seconds
Started Jun 25 04:59:56 PM PDT 24
Finished Jun 25 04:59:58 PM PDT 24
Peak memory 206296 kb
Host smart-0ab79015-c63f-4db8-929a-631ea23cc9d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13181
23063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.1318123063
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.108671164
Short name T790
Test name
Test status
Simulation time 743792114 ps
CPU time 1.99 seconds
Started Jun 25 04:59:53 PM PDT 24
Finished Jun 25 04:59:56 PM PDT 24
Peak memory 206772 kb
Host smart-13ffded3-a43e-4b2c-bbee-c42bada5a82e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10867
1164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.108671164
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.2027500651
Short name T1676
Test name
Test status
Simulation time 295216554 ps
CPU time 1.94 seconds
Started Jun 25 04:59:55 PM PDT 24
Finished Jun 25 04:59:59 PM PDT 24
Peak memory 206736 kb
Host smart-0ff832b6-4bab-411c-8e24-45c373eb69fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20275
00651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.2027500651
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.1205854215
Short name T1397
Test name
Test status
Simulation time 157549626 ps
CPU time 0.88 seconds
Started Jun 25 05:00:03 PM PDT 24
Finished Jun 25 05:00:06 PM PDT 24
Peak memory 206568 kb
Host smart-3655050d-d21b-492e-a2e4-a7b147342c2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12058
54215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.1205854215
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.1555018765
Short name T719
Test name
Test status
Simulation time 174594268 ps
CPU time 0.79 seconds
Started Jun 25 05:00:03 PM PDT 24
Finished Jun 25 05:00:05 PM PDT 24
Peak memory 206540 kb
Host smart-d32cebe4-672f-48fd-a7c6-45d634b5db61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15550
18765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.1555018765
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.545219486
Short name T625
Test name
Test status
Simulation time 216266066 ps
CPU time 0.87 seconds
Started Jun 25 04:59:56 PM PDT 24
Finished Jun 25 04:59:59 PM PDT 24
Peak memory 206872 kb
Host smart-c4f2df47-c6fe-479b-9727-e400e5e12a51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54521
9486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.545219486
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_invalid_sync.3630805013
Short name T2029
Test name
Test status
Simulation time 11241873268 ps
CPU time 80.34 seconds
Started Jun 25 05:00:00 PM PDT 24
Finished Jun 25 05:01:22 PM PDT 24
Peak memory 206948 kb
Host smart-9ca2cb15-f78a-4b97-a9e4-cf9812400f90
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3630805013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.3630805013
Directory /workspace/23.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.3829654523
Short name T22
Test name
Test status
Simulation time 219778099 ps
CPU time 0.87 seconds
Started Jun 25 05:00:05 PM PDT 24
Finished Jun 25 05:00:07 PM PDT 24
Peak memory 206500 kb
Host smart-0f1f68d1-473c-4394-bdd2-c2cabdee6c78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38296
54523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.3829654523
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.101877374
Short name T2497
Test name
Test status
Simulation time 23338382518 ps
CPU time 26.38 seconds
Started Jun 25 04:59:54 PM PDT 24
Finished Jun 25 05:00:22 PM PDT 24
Peak memory 206628 kb
Host smart-8a4a8ecc-8caf-415f-a18d-78e8cb7a14f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10187
7374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.101877374
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.674456463
Short name T2214
Test name
Test status
Simulation time 3344177574 ps
CPU time 3.82 seconds
Started Jun 25 04:59:55 PM PDT 24
Finished Jun 25 05:00:00 PM PDT 24
Peak memory 206632 kb
Host smart-34272bb4-6567-4de8-afc2-ff1b32396b7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67445
6463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.674456463
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.2978607899
Short name T1367
Test name
Test status
Simulation time 8837953587 ps
CPU time 84.65 seconds
Started Jun 25 04:59:56 PM PDT 24
Finished Jun 25 05:01:22 PM PDT 24
Peak memory 206788 kb
Host smart-eab6941e-b479-466a-87fd-8623201321ca
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2978607899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.2978607899
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.2080136960
Short name T2448
Test name
Test status
Simulation time 245265384 ps
CPU time 0.92 seconds
Started Jun 25 05:00:05 PM PDT 24
Finished Jun 25 05:00:08 PM PDT 24
Peak memory 206456 kb
Host smart-62ddae13-e19f-484d-9e4c-af92f231580e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2080136960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.2080136960
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.4046156326
Short name T1625
Test name
Test status
Simulation time 219121708 ps
CPU time 0.88 seconds
Started Jun 25 04:59:55 PM PDT 24
Finished Jun 25 04:59:58 PM PDT 24
Peak memory 206596 kb
Host smart-49c90753-598f-416a-a343-784b7d46a43b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40461
56326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.4046156326
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.1693207045
Short name T1382
Test name
Test status
Simulation time 6837746214 ps
CPU time 66.5 seconds
Started Jun 25 05:00:01 PM PDT 24
Finished Jun 25 05:01:09 PM PDT 24
Peak memory 206600 kb
Host smart-c8743a52-6946-4954-9b21-df1207c84d2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16932
07045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.1693207045
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.742332539
Short name T1640
Test name
Test status
Simulation time 3049666271 ps
CPU time 85.95 seconds
Started Jun 25 04:59:53 PM PDT 24
Finished Jun 25 05:01:21 PM PDT 24
Peak memory 206944 kb
Host smart-28e27dea-4063-49da-bcd8-3060cbd658c8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=742332539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.742332539
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.1370098119
Short name T547
Test name
Test status
Simulation time 213115566 ps
CPU time 0.86 seconds
Started Jun 25 05:00:04 PM PDT 24
Finished Jun 25 05:00:06 PM PDT 24
Peak memory 206576 kb
Host smart-bcd22e07-68af-4c9c-96db-ba44d4758dd8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1370098119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.1370098119
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.1885757345
Short name T1396
Test name
Test status
Simulation time 152975234 ps
CPU time 0.81 seconds
Started Jun 25 04:59:56 PM PDT 24
Finished Jun 25 04:59:59 PM PDT 24
Peak memory 206508 kb
Host smart-c24754d9-771e-47c3-a952-ae627118c90a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18857
57345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.1885757345
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.4079995635
Short name T1004
Test name
Test status
Simulation time 154261797 ps
CPU time 0.84 seconds
Started Jun 25 05:00:00 PM PDT 24
Finished Jun 25 05:00:02 PM PDT 24
Peak memory 206496 kb
Host smart-4a89d978-dbf4-4b43-9055-d19e8a28b427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40799
95635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.4079995635
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.3445635060
Short name T1614
Test name
Test status
Simulation time 199544636 ps
CPU time 0.92 seconds
Started Jun 25 04:59:53 PM PDT 24
Finished Jun 25 04:59:55 PM PDT 24
Peak memory 206580 kb
Host smart-ff0ba839-4b1b-406d-9ba8-c47c1ea11497
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34456
35060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.3445635060
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.3950954596
Short name T1575
Test name
Test status
Simulation time 160800807 ps
CPU time 0.8 seconds
Started Jun 25 04:59:54 PM PDT 24
Finished Jun 25 04:59:57 PM PDT 24
Peak memory 206580 kb
Host smart-046e34c1-ca79-43a5-822e-c842e1ed9711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39509
54596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.3950954596
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.2745038823
Short name T1025
Test name
Test status
Simulation time 153308859 ps
CPU time 0.76 seconds
Started Jun 25 05:00:00 PM PDT 24
Finished Jun 25 05:00:02 PM PDT 24
Peak memory 206500 kb
Host smart-702ca224-3756-48d5-9c53-ec1fbe506497
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27450
38823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.2745038823
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.1909747829
Short name T386
Test name
Test status
Simulation time 225343953 ps
CPU time 0.94 seconds
Started Jun 25 04:59:54 PM PDT 24
Finished Jun 25 04:59:56 PM PDT 24
Peak memory 206504 kb
Host smart-1e2b3c0f-0c21-4f75-bdb0-6da0e9e84547
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1909747829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.1909747829
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.570831637
Short name T849
Test name
Test status
Simulation time 172412272 ps
CPU time 0.83 seconds
Started Jun 25 04:59:56 PM PDT 24
Finished Jun 25 04:59:59 PM PDT 24
Peak memory 206600 kb
Host smart-eca94363-83c7-4119-a8bb-1e5ffd29820b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57083
1637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.570831637
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.3917466939
Short name T37
Test name
Test status
Simulation time 34821464 ps
CPU time 0.66 seconds
Started Jun 25 04:59:59 PM PDT 24
Finished Jun 25 05:00:00 PM PDT 24
Peak memory 206284 kb
Host smart-a47684dd-ebfa-4883-bb0c-cb5e38ab6bd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39174
66939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.3917466939
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.3389957861
Short name T2402
Test name
Test status
Simulation time 5997970552 ps
CPU time 13.07 seconds
Started Jun 25 04:59:54 PM PDT 24
Finished Jun 25 05:00:09 PM PDT 24
Peak memory 206912 kb
Host smart-dccf56d1-df6d-4c72-91c0-233d56bdaa4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33899
57861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.3389957861
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.1247758748
Short name T1823
Test name
Test status
Simulation time 188195358 ps
CPU time 0.84 seconds
Started Jun 25 04:59:53 PM PDT 24
Finished Jun 25 04:59:55 PM PDT 24
Peak memory 206484 kb
Host smart-52ce373e-47eb-4e37-a6c3-65e597c56747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12477
58748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.1247758748
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.1019868122
Short name T837
Test name
Test status
Simulation time 157574487 ps
CPU time 0.81 seconds
Started Jun 25 04:59:54 PM PDT 24
Finished Jun 25 04:59:57 PM PDT 24
Peak memory 206576 kb
Host smart-8fe455f5-55e3-4061-9b86-8f1e74a25d52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10198
68122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.1019868122
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.10673273
Short name T419
Test name
Test status
Simulation time 263912268 ps
CPU time 1 seconds
Started Jun 25 05:00:04 PM PDT 24
Finished Jun 25 05:00:06 PM PDT 24
Peak memory 206616 kb
Host smart-8045693a-20fa-4e19-bbaa-506e0b73e99b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10673
273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.10673273
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.2491035304
Short name T2477
Test name
Test status
Simulation time 143989808 ps
CPU time 0.77 seconds
Started Jun 25 04:59:56 PM PDT 24
Finished Jun 25 04:59:58 PM PDT 24
Peak memory 206228 kb
Host smart-94d634fd-d2aa-4c38-bf91-23c84dfddbcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24910
35304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.2491035304
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.4037483490
Short name T696
Test name
Test status
Simulation time 167164402 ps
CPU time 0.78 seconds
Started Jun 25 04:59:55 PM PDT 24
Finished Jun 25 04:59:58 PM PDT 24
Peak memory 206600 kb
Host smart-82b518c6-7503-49e3-8461-3cbf637e18d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40374
83490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.4037483490
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.742994495
Short name T1916
Test name
Test status
Simulation time 198171861 ps
CPU time 0.81 seconds
Started Jun 25 05:00:00 PM PDT 24
Finished Jun 25 05:00:02 PM PDT 24
Peak memory 206496 kb
Host smart-244a2125-616a-46c8-bf5e-7a9521c88aa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74299
4495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.742994495
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.277850918
Short name T1626
Test name
Test status
Simulation time 163443838 ps
CPU time 0.79 seconds
Started Jun 25 05:00:01 PM PDT 24
Finished Jun 25 05:00:03 PM PDT 24
Peak memory 206372 kb
Host smart-e100127e-80d4-49a2-a8bc-4bb42e115a1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27785
0918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.277850918
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.3326151573
Short name T804
Test name
Test status
Simulation time 228857057 ps
CPU time 0.93 seconds
Started Jun 25 04:59:54 PM PDT 24
Finished Jun 25 04:59:57 PM PDT 24
Peak memory 206612 kb
Host smart-d96b27d4-f4b6-4b56-8044-4c05472d84dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33261
51573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.3326151573
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.3752555171
Short name T621
Test name
Test status
Simulation time 8754824193 ps
CPU time 83.09 seconds
Started Jun 25 04:59:54 PM PDT 24
Finished Jun 25 05:01:19 PM PDT 24
Peak memory 206944 kb
Host smart-2fb63350-263c-42ec-ad96-4f8ec68b7c51
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3752555171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.3752555171
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.3391383726
Short name T1571
Test name
Test status
Simulation time 193702736 ps
CPU time 0.82 seconds
Started Jun 25 04:59:56 PM PDT 24
Finished Jun 25 04:59:59 PM PDT 24
Peak memory 206880 kb
Host smart-cde8b058-96d9-4676-8ca4-2fe4ad3e85b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33913
83726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.3391383726
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.2792814226
Short name T1490
Test name
Test status
Simulation time 200977901 ps
CPU time 0.85 seconds
Started Jun 25 04:59:53 PM PDT 24
Finished Jun 25 04:59:55 PM PDT 24
Peak memory 206480 kb
Host smart-8a73488f-4bbd-480c-8868-ffd06f65eb85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27928
14226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.2792814226
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.3747400712
Short name T609
Test name
Test status
Simulation time 3396585039 ps
CPU time 96.36 seconds
Started Jun 25 04:59:54 PM PDT 24
Finished Jun 25 05:01:33 PM PDT 24
Peak memory 206932 kb
Host smart-e9fa2fce-12f4-4b21-ab06-388ff9f7279b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37474
00712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.3747400712
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.2034237880
Short name T945
Test name
Test status
Simulation time 4386681878 ps
CPU time 4.75 seconds
Started Jun 25 05:00:05 PM PDT 24
Finished Jun 25 05:00:12 PM PDT 24
Peak memory 206776 kb
Host smart-b5e98848-6ff6-4077-b89e-235b6c4dffc2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2034237880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.2034237880
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.1034699748
Short name T221
Test name
Test status
Simulation time 13363519492 ps
CPU time 13.37 seconds
Started Jun 25 05:00:01 PM PDT 24
Finished Jun 25 05:00:16 PM PDT 24
Peak memory 206884 kb
Host smart-ae67e56e-1059-4a5c-a654-f21f23cc366d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1034699748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.1034699748
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.1292628974
Short name T487
Test name
Test status
Simulation time 23358527307 ps
CPU time 23.67 seconds
Started Jun 25 05:00:05 PM PDT 24
Finished Jun 25 05:00:30 PM PDT 24
Peak memory 206716 kb
Host smart-0d6b93d9-7192-49bb-a740-995dd0dd8067
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1292628974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.1292628974
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.7424894
Short name T739
Test name
Test status
Simulation time 198382245 ps
CPU time 0.84 seconds
Started Jun 25 05:00:05 PM PDT 24
Finished Jun 25 05:00:07 PM PDT 24
Peak memory 206516 kb
Host smart-fef1f03d-0ce4-4a60-90a6-cc5f51125a1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74248
94 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.7424894
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.2299677432
Short name T1716
Test name
Test status
Simulation time 148387748 ps
CPU time 0.78 seconds
Started Jun 25 05:00:04 PM PDT 24
Finished Jun 25 05:00:06 PM PDT 24
Peak memory 206572 kb
Host smart-375620ef-0b2f-45b8-a5c7-d0f3a2b25243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22996
77432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.2299677432
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.16283782
Short name T1495
Test name
Test status
Simulation time 153971156 ps
CPU time 0.79 seconds
Started Jun 25 05:00:03 PM PDT 24
Finished Jun 25 05:00:05 PM PDT 24
Peak memory 206552 kb
Host smart-9916ab8c-e22e-444e-b2b2-a7b336e5040b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16283
782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.16283782
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.3729538656
Short name T2145
Test name
Test status
Simulation time 1097139497 ps
CPU time 2.37 seconds
Started Jun 25 05:00:06 PM PDT 24
Finished Jun 25 05:00:11 PM PDT 24
Peak memory 206728 kb
Host smart-054a2bc9-1b90-4793-9a2d-8a23c00a5c0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37295
38656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.3729538656
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.10565386
Short name T297
Test name
Test status
Simulation time 355149786 ps
CPU time 1.13 seconds
Started Jun 25 05:00:06 PM PDT 24
Finished Jun 25 05:00:08 PM PDT 24
Peak memory 206460 kb
Host smart-ac7cf52c-6cb5-4e1d-9a8a-e5b9b77ec049
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10565
386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.10565386
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.1820735852
Short name T1209
Test name
Test status
Simulation time 203564361 ps
CPU time 0.83 seconds
Started Jun 25 05:00:05 PM PDT 24
Finished Jun 25 05:00:07 PM PDT 24
Peak memory 206568 kb
Host smart-2d324891-996f-4bfb-8812-ecc70d76c63f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18207
35852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.1820735852
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.2312649113
Short name T1288
Test name
Test status
Simulation time 45785058 ps
CPU time 0.75 seconds
Started Jun 25 05:00:06 PM PDT 24
Finished Jun 25 05:00:09 PM PDT 24
Peak memory 206580 kb
Host smart-0e109cc7-4c08-4197-bf88-0a960a45a46e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23126
49113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.2312649113
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.276940947
Short name T1896
Test name
Test status
Simulation time 789240688 ps
CPU time 1.82 seconds
Started Jun 25 05:00:10 PM PDT 24
Finished Jun 25 05:00:13 PM PDT 24
Peak memory 206672 kb
Host smart-8910794d-5f7b-45be-9fb8-26377230ec9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27694
0947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.276940947
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.2842549419
Short name T979
Test name
Test status
Simulation time 214487222 ps
CPU time 1.41 seconds
Started Jun 25 05:00:03 PM PDT 24
Finished Jun 25 05:00:05 PM PDT 24
Peak memory 206736 kb
Host smart-20ef04d2-8611-4172-8961-7479f6779f71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28425
49419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.2842549419
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.4235961915
Short name T1577
Test name
Test status
Simulation time 191627046 ps
CPU time 0.85 seconds
Started Jun 25 05:00:17 PM PDT 24
Finished Jun 25 05:00:19 PM PDT 24
Peak memory 206476 kb
Host smart-37af2ad7-e70f-4c72-8b69-1bc7ebd998d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42359
61915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.4235961915
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.1531905956
Short name T2240
Test name
Test status
Simulation time 135668537 ps
CPU time 0.82 seconds
Started Jun 25 05:00:14 PM PDT 24
Finished Jun 25 05:00:17 PM PDT 24
Peak memory 206488 kb
Host smart-7c78bbe1-b954-44d7-a3b7-dd3aa6efb203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15319
05956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.1531905956
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.2630608446
Short name T1565
Test name
Test status
Simulation time 176261299 ps
CPU time 0.82 seconds
Started Jun 25 05:00:06 PM PDT 24
Finished Jun 25 05:00:09 PM PDT 24
Peak memory 206492 kb
Host smart-720bbdd0-6e46-4908-bd1c-bd3eeaa36be6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26306
08446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.2630608446
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.4188052851
Short name T1724
Test name
Test status
Simulation time 233803022 ps
CPU time 0.92 seconds
Started Jun 25 05:00:04 PM PDT 24
Finished Jun 25 05:00:06 PM PDT 24
Peak memory 206572 kb
Host smart-7563e0d9-b37c-435c-b699-e965ba08dae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41880
52851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.4188052851
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.3938483865
Short name T1261
Test name
Test status
Simulation time 23309807389 ps
CPU time 23.56 seconds
Started Jun 25 05:00:04 PM PDT 24
Finished Jun 25 05:00:29 PM PDT 24
Peak memory 206564 kb
Host smart-f079f031-759d-46c1-9759-38e4d2b0e312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39384
83865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.3938483865
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.198603105
Short name T1057
Test name
Test status
Simulation time 3361945024 ps
CPU time 3.89 seconds
Started Jun 25 05:00:03 PM PDT 24
Finished Jun 25 05:00:09 PM PDT 24
Peak memory 206620 kb
Host smart-01c05433-102e-4204-9a98-4cb692769303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19860
3105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.198603105
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.1929191955
Short name T1463
Test name
Test status
Simulation time 8216670936 ps
CPU time 77.37 seconds
Started Jun 25 05:00:03 PM PDT 24
Finished Jun 25 05:01:21 PM PDT 24
Peak memory 206876 kb
Host smart-77f60c5f-f6e9-4101-bcf5-df3b32730f00
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1929191955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.1929191955
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.2106071839
Short name T2222
Test name
Test status
Simulation time 236700103 ps
CPU time 0.93 seconds
Started Jun 25 05:00:14 PM PDT 24
Finished Jun 25 05:00:16 PM PDT 24
Peak memory 206596 kb
Host smart-2692c01e-0ae0-42a1-ac35-30e3ce4631fb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2106071839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.2106071839
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.265665194
Short name T1429
Test name
Test status
Simulation time 212253440 ps
CPU time 0.91 seconds
Started Jun 25 05:00:06 PM PDT 24
Finished Jun 25 05:00:09 PM PDT 24
Peak memory 206484 kb
Host smart-3116a11d-5723-401b-b96d-cc93e2a13d58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26566
5194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.265665194
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.1452400359
Short name T1098
Test name
Test status
Simulation time 12345721345 ps
CPU time 351.86 seconds
Started Jun 25 05:00:04 PM PDT 24
Finished Jun 25 05:05:58 PM PDT 24
Peak memory 206752 kb
Host smart-eabec72a-668a-4f8c-8af3-db9b4817664b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14524
00359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.1452400359
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.3077900907
Short name T980
Test name
Test status
Simulation time 5265706738 ps
CPU time 37.11 seconds
Started Jun 25 05:00:05 PM PDT 24
Finished Jun 25 05:00:44 PM PDT 24
Peak memory 206992 kb
Host smart-aaa74f8c-7aae-4bde-9aa1-cd6a9e135de9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3077900907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.3077900907
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.3973619166
Short name T2195
Test name
Test status
Simulation time 149003306 ps
CPU time 0.78 seconds
Started Jun 25 05:00:15 PM PDT 24
Finished Jun 25 05:00:18 PM PDT 24
Peak memory 206572 kb
Host smart-b6dfac22-d868-4132-be97-9ee72053afb8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3973619166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.3973619166
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.1744473588
Short name T1688
Test name
Test status
Simulation time 149992199 ps
CPU time 0.88 seconds
Started Jun 25 05:00:06 PM PDT 24
Finished Jun 25 05:00:09 PM PDT 24
Peak memory 206576 kb
Host smart-7b9065d4-5d9c-4700-a521-fa2885ba9f6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17444
73588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.1744473588
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.2568644454
Short name T2132
Test name
Test status
Simulation time 266739623 ps
CPU time 1.03 seconds
Started Jun 25 05:00:02 PM PDT 24
Finished Jun 25 05:00:04 PM PDT 24
Peak memory 206500 kb
Host smart-0dcc60c1-cfd1-4be7-b9b0-56c85b55585c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25686
44454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.2568644454
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.3816249430
Short name T754
Test name
Test status
Simulation time 198292328 ps
CPU time 0.93 seconds
Started Jun 25 05:00:03 PM PDT 24
Finished Jun 25 05:00:06 PM PDT 24
Peak memory 206528 kb
Host smart-d59ec172-9925-4932-9422-80ecddc9265a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38162
49430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.3816249430
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.3694543224
Short name T104
Test name
Test status
Simulation time 196609400 ps
CPU time 0.85 seconds
Started Jun 25 05:00:03 PM PDT 24
Finished Jun 25 05:00:05 PM PDT 24
Peak memory 206516 kb
Host smart-421597ec-b9e8-41b2-a1ee-c822e4d1cb85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36945
43224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.3694543224
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.244713160
Short name T583
Test name
Test status
Simulation time 162431616 ps
CPU time 0.81 seconds
Started Jun 25 05:00:05 PM PDT 24
Finished Jun 25 05:00:07 PM PDT 24
Peak memory 206600 kb
Host smart-1da122c5-456d-45ee-81d9-cfaa9efb0353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24471
3160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.244713160
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.1353966410
Short name T717
Test name
Test status
Simulation time 143263576 ps
CPU time 0.79 seconds
Started Jun 25 05:00:13 PM PDT 24
Finished Jun 25 05:00:15 PM PDT 24
Peak memory 206572 kb
Host smart-53f8f6e6-12a6-495a-8305-d9bb4c59c43b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13539
66410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.1353966410
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.3496300598
Short name T1124
Test name
Test status
Simulation time 244203738 ps
CPU time 1.01 seconds
Started Jun 25 05:00:02 PM PDT 24
Finished Jun 25 05:00:05 PM PDT 24
Peak memory 206568 kb
Host smart-644693f6-11ac-4a8d-b8cb-35b8f87a02d6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3496300598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.3496300598
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.2900587641
Short name T585
Test name
Test status
Simulation time 150698732 ps
CPU time 0.77 seconds
Started Jun 25 05:00:06 PM PDT 24
Finished Jun 25 05:00:08 PM PDT 24
Peak memory 206480 kb
Host smart-84e9c549-0549-48aa-a151-b119a140093a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29005
87641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.2900587641
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.303181832
Short name T1530
Test name
Test status
Simulation time 50197969 ps
CPU time 0.67 seconds
Started Jun 25 05:00:12 PM PDT 24
Finished Jun 25 05:00:14 PM PDT 24
Peak memory 206596 kb
Host smart-3238c49d-185a-41e8-ac05-9e2acb1b77d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30318
1832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.303181832
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.2291674216
Short name T1337
Test name
Test status
Simulation time 5968222452 ps
CPU time 12.99 seconds
Started Jun 25 05:00:05 PM PDT 24
Finished Jun 25 05:00:20 PM PDT 24
Peak memory 206820 kb
Host smart-f8b83c27-d9cd-4636-b6f1-4f470687504d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22916
74216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.2291674216
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.1506704436
Short name T1473
Test name
Test status
Simulation time 160635336 ps
CPU time 0.81 seconds
Started Jun 25 05:00:05 PM PDT 24
Finished Jun 25 05:00:07 PM PDT 24
Peak memory 206572 kb
Host smart-26814a9a-f0b2-48d4-892f-46deafe1f935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15067
04436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.1506704436
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.1273099400
Short name T1103
Test name
Test status
Simulation time 258198368 ps
CPU time 0.94 seconds
Started Jun 25 05:00:07 PM PDT 24
Finished Jun 25 05:00:09 PM PDT 24
Peak memory 206480 kb
Host smart-b4d0b51c-9dc3-4441-8b94-9c96cec99a2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12730
99400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.1273099400
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.4091353174
Short name T1684
Test name
Test status
Simulation time 198049117 ps
CPU time 0.85 seconds
Started Jun 25 05:00:13 PM PDT 24
Finished Jun 25 05:00:15 PM PDT 24
Peak memory 206520 kb
Host smart-08aa3d13-2c9b-4f21-9c17-625319ce9b2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40913
53174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.4091353174
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.2815727928
Short name T2450
Test name
Test status
Simulation time 228528887 ps
CPU time 0.9 seconds
Started Jun 25 05:00:06 PM PDT 24
Finished Jun 25 05:00:09 PM PDT 24
Peak memory 206512 kb
Host smart-b8c48f43-c4b8-42fc-864a-06d7b5f5cbaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28157
27928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.2815727928
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.1976861695
Short name T409
Test name
Test status
Simulation time 202520449 ps
CPU time 0.85 seconds
Started Jun 25 05:00:14 PM PDT 24
Finished Jun 25 05:00:16 PM PDT 24
Peak memory 206516 kb
Host smart-86de86fb-13fd-4133-8b66-4095bf97f2ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19768
61695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.1976861695
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.2592741863
Short name T1189
Test name
Test status
Simulation time 200646383 ps
CPU time 0.89 seconds
Started Jun 25 05:00:13 PM PDT 24
Finished Jun 25 05:00:15 PM PDT 24
Peak memory 206480 kb
Host smart-65693a22-b337-4b00-8cd7-3c14cf70ab4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25927
41863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.2592741863
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.3775820904
Short name T1450
Test name
Test status
Simulation time 162562516 ps
CPU time 0.77 seconds
Started Jun 25 05:00:17 PM PDT 24
Finished Jun 25 05:00:18 PM PDT 24
Peak memory 206572 kb
Host smart-508fd339-014b-4571-9fb2-a9517b27dc4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37758
20904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.3775820904
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.572214437
Short name T408
Test name
Test status
Simulation time 193366061 ps
CPU time 0.94 seconds
Started Jun 25 05:00:13 PM PDT 24
Finished Jun 25 05:00:15 PM PDT 24
Peak memory 206580 kb
Host smart-2fc7f679-3ac3-4c36-9190-c78fad6b4362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57221
4437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.572214437
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.1011295056
Short name T443
Test name
Test status
Simulation time 8007837338 ps
CPU time 76.31 seconds
Started Jun 25 05:00:14 PM PDT 24
Finished Jun 25 05:01:31 PM PDT 24
Peak memory 206844 kb
Host smart-52466d69-02b3-42e8-adc0-441e5bf1d7e9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1011295056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.1011295056
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.548726936
Short name T995
Test name
Test status
Simulation time 166991710 ps
CPU time 0.82 seconds
Started Jun 25 05:00:11 PM PDT 24
Finished Jun 25 05:00:13 PM PDT 24
Peak memory 206572 kb
Host smart-63046cc8-2598-46da-8702-6f9e6bb629fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54872
6936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.548726936
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.2583795298
Short name T1294
Test name
Test status
Simulation time 158457916 ps
CPU time 0.85 seconds
Started Jun 25 05:00:15 PM PDT 24
Finished Jun 25 05:00:17 PM PDT 24
Peak memory 206584 kb
Host smart-a0eb35cd-0f33-4e89-a77c-9f8670ffd8f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25837
95298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.2583795298
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.1339967000
Short name T640
Test name
Test status
Simulation time 6662202217 ps
CPU time 63.74 seconds
Started Jun 25 05:00:14 PM PDT 24
Finished Jun 25 05:01:20 PM PDT 24
Peak memory 206732 kb
Host smart-646492ee-2ae6-4cf0-8c9a-1a7a79219a3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13399
67000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.1339967000
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.1109871262
Short name T1581
Test name
Test status
Simulation time 3853548154 ps
CPU time 4.15 seconds
Started Jun 25 05:00:14 PM PDT 24
Finished Jun 25 05:00:19 PM PDT 24
Peak memory 206908 kb
Host smart-f0328b7a-d150-448d-82e0-57c1cdb6ff90
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1109871262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.1109871262
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.2348478273
Short name T859
Test name
Test status
Simulation time 13389676288 ps
CPU time 14.57 seconds
Started Jun 25 05:00:12 PM PDT 24
Finished Jun 25 05:00:28 PM PDT 24
Peak memory 206804 kb
Host smart-a8f0e73b-9a63-45dc-9e70-7849c013d47b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2348478273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.2348478273
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.1024730086
Short name T1887
Test name
Test status
Simulation time 23330390553 ps
CPU time 28.69 seconds
Started Jun 25 05:00:13 PM PDT 24
Finished Jun 25 05:00:44 PM PDT 24
Peak memory 206740 kb
Host smart-138ccfec-5ba1-4018-a49d-b16f5780ff5c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1024730086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.1024730086
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.874064163
Short name T2309
Test name
Test status
Simulation time 185485806 ps
CPU time 0.88 seconds
Started Jun 25 05:00:12 PM PDT 24
Finished Jun 25 05:00:14 PM PDT 24
Peak memory 206560 kb
Host smart-9e29e6ea-a630-45bc-b600-de179501c61a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87406
4163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.874064163
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.1602400060
Short name T2230
Test name
Test status
Simulation time 185488943 ps
CPU time 0.84 seconds
Started Jun 25 05:00:13 PM PDT 24
Finished Jun 25 05:00:16 PM PDT 24
Peak memory 206508 kb
Host smart-9879dffe-dd12-4cd2-add9-ceaabc0ebad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16024
00060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.1602400060
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.1120876534
Short name T1763
Test name
Test status
Simulation time 477526560 ps
CPU time 1.36 seconds
Started Jun 25 05:00:11 PM PDT 24
Finished Jun 25 05:00:13 PM PDT 24
Peak memory 206796 kb
Host smart-3775e640-e6cc-44b0-b677-590c3ca46422
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11208
76534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.1120876534
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.2209706106
Short name T1461
Test name
Test status
Simulation time 841489139 ps
CPU time 2.21 seconds
Started Jun 25 05:00:16 PM PDT 24
Finished Jun 25 05:00:19 PM PDT 24
Peak memory 206744 kb
Host smart-6498b160-5f18-4499-960f-a8eedfb90056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22097
06106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.2209706106
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.1365219319
Short name T1907
Test name
Test status
Simulation time 13073596342 ps
CPU time 26.86 seconds
Started Jun 25 05:00:12 PM PDT 24
Finished Jun 25 05:00:40 PM PDT 24
Peak memory 206848 kb
Host smart-2c45e3d3-272b-40b8-9532-bf1aa2d2ac4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13652
19319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.1365219319
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.1628934481
Short name T1557
Test name
Test status
Simulation time 418302318 ps
CPU time 1.18 seconds
Started Jun 25 05:00:11 PM PDT 24
Finished Jun 25 05:00:13 PM PDT 24
Peak memory 206580 kb
Host smart-a02695fd-8729-4d3f-a066-b7088e32f63c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16289
34481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.1628934481
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.1405251284
Short name T505
Test name
Test status
Simulation time 156642315 ps
CPU time 0.77 seconds
Started Jun 25 05:00:15 PM PDT 24
Finished Jun 25 05:00:17 PM PDT 24
Peak memory 206596 kb
Host smart-8f5c87b8-6ed4-4458-9fc5-6473a3d58c88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14052
51284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.1405251284
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.3638444720
Short name T1398
Test name
Test status
Simulation time 49875190 ps
CPU time 0.66 seconds
Started Jun 25 05:00:18 PM PDT 24
Finished Jun 25 05:00:20 PM PDT 24
Peak memory 206464 kb
Host smart-38bf1731-040c-4f64-8a42-832cf512faa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36384
44720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.3638444720
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.1798551954
Short name T2486
Test name
Test status
Simulation time 925842211 ps
CPU time 2.11 seconds
Started Jun 25 05:00:13 PM PDT 24
Finished Jun 25 05:00:17 PM PDT 24
Peak memory 206744 kb
Host smart-5b3e7846-7911-4af1-9194-c93e100c21bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17985
51954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.1798551954
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.1929536530
Short name T1371
Test name
Test status
Simulation time 183957102 ps
CPU time 1.29 seconds
Started Jun 25 05:00:13 PM PDT 24
Finished Jun 25 05:00:16 PM PDT 24
Peak memory 206768 kb
Host smart-864f3340-194f-4e67-ac03-49b8ce4592f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19295
36530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.1929536530
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.2303929980
Short name T1270
Test name
Test status
Simulation time 199526441 ps
CPU time 0.88 seconds
Started Jun 25 05:00:25 PM PDT 24
Finished Jun 25 05:00:27 PM PDT 24
Peak memory 206568 kb
Host smart-72018ce4-9a1e-4fc7-a57c-3814001fbf09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23039
29980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.2303929980
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.2601548269
Short name T1016
Test name
Test status
Simulation time 166221655 ps
CPU time 0.78 seconds
Started Jun 25 05:00:21 PM PDT 24
Finished Jun 25 05:00:23 PM PDT 24
Peak memory 206568 kb
Host smart-56c131a2-3422-4022-88af-3e6163b24122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26015
48269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.2601548269
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.3977961971
Short name T1815
Test name
Test status
Simulation time 238840726 ps
CPU time 0.91 seconds
Started Jun 25 05:00:12 PM PDT 24
Finished Jun 25 05:00:14 PM PDT 24
Peak memory 206500 kb
Host smart-28cfecb7-a070-4bf9-b0a9-1d6994356af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39779
61971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.3977961971
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_invalid_sync.4159385444
Short name T106
Test name
Test status
Simulation time 7653462022 ps
CPU time 73.59 seconds
Started Jun 25 05:00:11 PM PDT 24
Finished Jun 25 05:01:26 PM PDT 24
Peak memory 207012 kb
Host smart-9da1ff4a-eb34-4c61-bff8-09a8a32dac1c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4159385444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.4159385444
Directory /workspace/25.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.2138160736
Short name T1392
Test name
Test status
Simulation time 205077912 ps
CPU time 0.81 seconds
Started Jun 25 05:00:12 PM PDT 24
Finished Jun 25 05:00:13 PM PDT 24
Peak memory 206572 kb
Host smart-4188d70e-cbbb-47d3-a389-ad416a6be7e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21381
60736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.2138160736
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.950434515
Short name T383
Test name
Test status
Simulation time 23363603427 ps
CPU time 23.84 seconds
Started Jun 25 05:00:12 PM PDT 24
Finished Jun 25 05:00:38 PM PDT 24
Peak memory 206620 kb
Host smart-cf170ee7-4775-4357-9f1c-6c6df9ae7699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95043
4515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.950434515
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.4227637285
Short name T1632
Test name
Test status
Simulation time 3335982767 ps
CPU time 4.13 seconds
Started Jun 25 05:00:16 PM PDT 24
Finished Jun 25 05:00:21 PM PDT 24
Peak memory 206620 kb
Host smart-8d200560-09ed-4605-a8dd-991b9bb9de68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42276
37285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.4227637285
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.1987531306
Short name T1531
Test name
Test status
Simulation time 11052656213 ps
CPU time 79.24 seconds
Started Jun 25 05:00:13 PM PDT 24
Finished Jun 25 05:01:33 PM PDT 24
Peak memory 206888 kb
Host smart-194cef60-6470-499f-bd4b-df1f3e8208c8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1987531306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.1987531306
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.423850655
Short name T1251
Test name
Test status
Simulation time 246443938 ps
CPU time 0.96 seconds
Started Jun 25 05:00:19 PM PDT 24
Finished Jun 25 05:00:21 PM PDT 24
Peak memory 206492 kb
Host smart-66ecd03b-1514-450f-ad82-f71ce6660c65
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=423850655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.423850655
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.1923478343
Short name T1488
Test name
Test status
Simulation time 252739259 ps
CPU time 0.91 seconds
Started Jun 25 05:00:11 PM PDT 24
Finished Jun 25 05:00:13 PM PDT 24
Peak memory 206580 kb
Host smart-d8291be5-10e1-4989-b351-e5822abbe8cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19234
78343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.1923478343
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.253517241
Short name T2081
Test name
Test status
Simulation time 6591949069 ps
CPU time 44.5 seconds
Started Jun 25 05:00:12 PM PDT 24
Finished Jun 25 05:00:58 PM PDT 24
Peak memory 206940 kb
Host smart-d3b25b8e-d25f-4091-9bd3-2bb6387676f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25351
7241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.253517241
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.1921720435
Short name T954
Test name
Test status
Simulation time 10193043392 ps
CPU time 92.17 seconds
Started Jun 25 05:00:11 PM PDT 24
Finished Jun 25 05:01:44 PM PDT 24
Peak memory 206812 kb
Host smart-acfe2571-19d9-4ecb-932a-5b9195fe8582
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1921720435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.1921720435
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.3503847094
Short name T1904
Test name
Test status
Simulation time 162282383 ps
CPU time 0.79 seconds
Started Jun 25 05:00:20 PM PDT 24
Finished Jun 25 05:00:22 PM PDT 24
Peak memory 206596 kb
Host smart-7eccd3fd-0029-495e-946b-fb74a2947ad2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3503847094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.3503847094
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.400250336
Short name T669
Test name
Test status
Simulation time 147869675 ps
CPU time 0.8 seconds
Started Jun 25 05:00:14 PM PDT 24
Finished Jun 25 05:00:16 PM PDT 24
Peak memory 206592 kb
Host smart-e2b3363a-2f94-4e31-a122-a0d165649ba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40025
0336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.400250336
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.2449737150
Short name T135
Test name
Test status
Simulation time 268960897 ps
CPU time 1 seconds
Started Jun 25 05:00:18 PM PDT 24
Finished Jun 25 05:00:20 PM PDT 24
Peak memory 206484 kb
Host smart-36608f78-1241-4734-aec8-a1a737efade1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24497
37150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.2449737150
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.2331059350
Short name T1661
Test name
Test status
Simulation time 203692166 ps
CPU time 0.87 seconds
Started Jun 25 05:00:14 PM PDT 24
Finished Jun 25 05:00:16 PM PDT 24
Peak memory 206516 kb
Host smart-4d49b5a6-436f-499d-82bb-530ae6eaefc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23310
59350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.2331059350
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.1469759162
Short name T2179
Test name
Test status
Simulation time 166970252 ps
CPU time 0.79 seconds
Started Jun 25 05:00:20 PM PDT 24
Finished Jun 25 05:00:23 PM PDT 24
Peak memory 206500 kb
Host smart-20ab280c-c374-43b6-893d-3afd0d150b26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14697
59162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.1469759162
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.444028001
Short name T679
Test name
Test status
Simulation time 174333920 ps
CPU time 0.83 seconds
Started Jun 25 05:00:23 PM PDT 24
Finished Jun 25 05:00:25 PM PDT 24
Peak memory 206504 kb
Host smart-4e7fcd04-aa81-4dbc-bdb8-2897f174ea7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44402
8001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.444028001
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.1143849312
Short name T2249
Test name
Test status
Simulation time 164815918 ps
CPU time 0.88 seconds
Started Jun 25 05:00:19 PM PDT 24
Finished Jun 25 05:00:21 PM PDT 24
Peak memory 206528 kb
Host smart-601b9335-7635-4f61-8f43-bf82b6f26aac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11438
49312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.1143849312
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.3107968884
Short name T2370
Test name
Test status
Simulation time 201636745 ps
CPU time 0.87 seconds
Started Jun 25 05:00:19 PM PDT 24
Finished Jun 25 05:00:22 PM PDT 24
Peak memory 206500 kb
Host smart-c99d9f28-b5ca-42d8-8c02-0ddb134d946d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3107968884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.3107968884
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.2224332632
Short name T901
Test name
Test status
Simulation time 157783494 ps
CPU time 0.8 seconds
Started Jun 25 05:00:22 PM PDT 24
Finished Jun 25 05:00:25 PM PDT 24
Peak memory 206480 kb
Host smart-e8e4f8b9-8362-4ebb-bad0-df43a6b9c3e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22243
32632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.2224332632
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.2604360041
Short name T715
Test name
Test status
Simulation time 37596343 ps
CPU time 0.66 seconds
Started Jun 25 05:00:21 PM PDT 24
Finished Jun 25 05:00:23 PM PDT 24
Peak memory 206568 kb
Host smart-eaea88d4-43a1-4eb5-8c24-95a3aba8f927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26043
60041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.2604360041
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.728817413
Short name T2510
Test name
Test status
Simulation time 13646635463 ps
CPU time 28.22 seconds
Started Jun 25 05:00:18 PM PDT 24
Finished Jun 25 05:00:47 PM PDT 24
Peak memory 206828 kb
Host smart-3bbbc609-f409-4f9e-b164-7bcb73b23ad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72881
7413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.728817413
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.3242530277
Short name T1156
Test name
Test status
Simulation time 182098106 ps
CPU time 0.82 seconds
Started Jun 25 05:00:21 PM PDT 24
Finished Jun 25 05:00:23 PM PDT 24
Peak memory 206580 kb
Host smart-69b36dbf-7317-494b-be24-1bddd9f240ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32425
30277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.3242530277
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.1374625247
Short name T1585
Test name
Test status
Simulation time 263371732 ps
CPU time 0.96 seconds
Started Jun 25 05:00:23 PM PDT 24
Finished Jun 25 05:00:26 PM PDT 24
Peak memory 206600 kb
Host smart-cf9266af-b0c1-4883-9007-b0d6b3febf00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13746
25247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.1374625247
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.305892238
Short name T1002
Test name
Test status
Simulation time 181857978 ps
CPU time 0.86 seconds
Started Jun 25 05:00:22 PM PDT 24
Finished Jun 25 05:00:24 PM PDT 24
Peak memory 206612 kb
Host smart-61f2a87c-cb92-4907-8318-df39fe490f42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30589
2238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.305892238
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.35875485
Short name T1794
Test name
Test status
Simulation time 179130366 ps
CPU time 0.82 seconds
Started Jun 25 05:00:19 PM PDT 24
Finished Jun 25 05:00:21 PM PDT 24
Peak memory 206508 kb
Host smart-13a61b93-cba1-4c01-bf35-11a37585a321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35875
485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.35875485
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.261764847
Short name T584
Test name
Test status
Simulation time 178729353 ps
CPU time 0.81 seconds
Started Jun 25 05:00:21 PM PDT 24
Finished Jun 25 05:00:24 PM PDT 24
Peak memory 206596 kb
Host smart-35f2d5e2-db6e-4299-b152-e437bc0e1f17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26176
4847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.261764847
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.2837053632
Short name T1155
Test name
Test status
Simulation time 158667563 ps
CPU time 0.77 seconds
Started Jun 25 05:00:23 PM PDT 24
Finished Jun 25 05:00:25 PM PDT 24
Peak memory 206600 kb
Host smart-30be3b56-36ee-41d7-8dde-38ab69ff695b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28370
53632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.2837053632
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.3093480367
Short name T20
Test name
Test status
Simulation time 151848414 ps
CPU time 0.8 seconds
Started Jun 25 05:00:22 PM PDT 24
Finished Jun 25 05:00:24 PM PDT 24
Peak memory 206572 kb
Host smart-9d4e2de9-19f9-4beb-9c5a-a992b712a0a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30934
80367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.3093480367
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.2518473768
Short name T1127
Test name
Test status
Simulation time 233453545 ps
CPU time 0.96 seconds
Started Jun 25 05:00:21 PM PDT 24
Finished Jun 25 05:00:24 PM PDT 24
Peak memory 206604 kb
Host smart-30b3230f-9281-4bed-a52a-af97c3fb88d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25184
73768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.2518473768
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.3292754803
Short name T1260
Test name
Test status
Simulation time 4857968758 ps
CPU time 34.13 seconds
Started Jun 25 05:00:20 PM PDT 24
Finished Jun 25 05:00:56 PM PDT 24
Peak memory 206868 kb
Host smart-a3311286-d8da-4c58-be1f-18ba30482333
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3292754803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.3292754803
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.3233869246
Short name T2390
Test name
Test status
Simulation time 163647901 ps
CPU time 0.84 seconds
Started Jun 25 05:00:20 PM PDT 24
Finished Jun 25 05:00:22 PM PDT 24
Peak memory 206572 kb
Host smart-bc1dee0c-a668-4a92-a27f-a5390769e605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32338
69246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.3233869246
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.2735407223
Short name T332
Test name
Test status
Simulation time 152130370 ps
CPU time 0.79 seconds
Started Jun 25 05:00:23 PM PDT 24
Finished Jun 25 05:00:25 PM PDT 24
Peak memory 206492 kb
Host smart-46abd352-8b98-42f0-84d4-d09b82e93c46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27354
07223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.2735407223
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.648771528
Short name T1430
Test name
Test status
Simulation time 9821794854 ps
CPU time 285.25 seconds
Started Jun 25 05:00:22 PM PDT 24
Finished Jun 25 05:05:09 PM PDT 24
Peak memory 206860 kb
Host smart-8fb1fcd9-3e49-45bc-99bd-d428b256db30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64877
1528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.648771528
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.1016963275
Short name T1885
Test name
Test status
Simulation time 3988841768 ps
CPU time 4.29 seconds
Started Jun 25 05:00:23 PM PDT 24
Finished Jun 25 05:00:28 PM PDT 24
Peak memory 206764 kb
Host smart-f0a74d37-3d98-4b0d-9cbb-c1b291c510b8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1016963275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.1016963275
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.838898196
Short name T1285
Test name
Test status
Simulation time 13324701546 ps
CPU time 13 seconds
Started Jun 25 05:00:21 PM PDT 24
Finished Jun 25 05:00:36 PM PDT 24
Peak memory 206652 kb
Host smart-01e886b9-4d78-4de7-b363-0daee42e971b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=838898196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.838898196
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.4226107765
Short name T698
Test name
Test status
Simulation time 23410755267 ps
CPU time 26.22 seconds
Started Jun 25 05:00:22 PM PDT 24
Finished Jun 25 05:00:50 PM PDT 24
Peak memory 206716 kb
Host smart-6197cdda-bf2c-4da5-b9c0-93a3a4612807
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4226107765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.4226107765
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.1591920310
Short name T1621
Test name
Test status
Simulation time 179132430 ps
CPU time 0.86 seconds
Started Jun 25 05:00:24 PM PDT 24
Finished Jun 25 05:00:27 PM PDT 24
Peak memory 206496 kb
Host smart-ad29bce2-5d80-4eb9-a091-d728f29a26ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15919
20310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.1591920310
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.86672695
Short name T1309
Test name
Test status
Simulation time 146039725 ps
CPU time 0.74 seconds
Started Jun 25 05:00:21 PM PDT 24
Finished Jun 25 05:00:23 PM PDT 24
Peak memory 206464 kb
Host smart-c51fc822-d764-4531-bfd3-75383b3a2829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86672
695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.86672695
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.2656961077
Short name T766
Test name
Test status
Simulation time 411381041 ps
CPU time 1.34 seconds
Started Jun 25 05:00:21 PM PDT 24
Finished Jun 25 05:00:24 PM PDT 24
Peak memory 206576 kb
Host smart-8211b179-a7fb-4f65-8a99-780f9be1ee31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26569
61077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.2656961077
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.207090862
Short name T170
Test name
Test status
Simulation time 1479379015 ps
CPU time 2.89 seconds
Started Jun 25 05:00:18 PM PDT 24
Finished Jun 25 05:00:22 PM PDT 24
Peak memory 206748 kb
Host smart-34f616ad-b5f4-43ea-9d15-9927513c5318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20709
0862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.207090862
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.2451462318
Short name T844
Test name
Test status
Simulation time 15981396249 ps
CPU time 27.97 seconds
Started Jun 25 05:00:21 PM PDT 24
Finished Jun 25 05:00:51 PM PDT 24
Peak memory 206852 kb
Host smart-7769ef1d-cc89-4e61-a11f-030c810b045e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24514
62318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.2451462318
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.3831437257
Short name T1665
Test name
Test status
Simulation time 423141574 ps
CPU time 1.45 seconds
Started Jun 25 05:00:23 PM PDT 24
Finished Jun 25 05:00:26 PM PDT 24
Peak memory 206600 kb
Host smart-2f9792f5-4350-41ec-925c-605ec6efd0f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38314
37257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.3831437257
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.2608609291
Short name T740
Test name
Test status
Simulation time 140437569 ps
CPU time 0.78 seconds
Started Jun 25 05:00:20 PM PDT 24
Finished Jun 25 05:00:22 PM PDT 24
Peak memory 206576 kb
Host smart-9a0f47f6-71c1-472d-b1a0-3c99030463e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26086
09291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.2608609291
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.1109931335
Short name T574
Test name
Test status
Simulation time 65026710 ps
CPU time 0.67 seconds
Started Jun 25 05:00:23 PM PDT 24
Finished Jun 25 05:00:25 PM PDT 24
Peak memory 206552 kb
Host smart-6794430d-5b97-41c7-b258-6119951a10ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11099
31335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.1109931335
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.1498786882
Short name T840
Test name
Test status
Simulation time 906254146 ps
CPU time 2.32 seconds
Started Jun 25 05:00:23 PM PDT 24
Finished Jun 25 05:00:27 PM PDT 24
Peak memory 206736 kb
Host smart-23f95dea-3996-41b3-871a-0774198551f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14987
86882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.1498786882
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.1810996601
Short name T184
Test name
Test status
Simulation time 212067680 ps
CPU time 1.32 seconds
Started Jun 25 05:00:23 PM PDT 24
Finished Jun 25 05:00:26 PM PDT 24
Peak memory 206708 kb
Host smart-7740430b-c1ab-4a7c-bc2f-9c79fcd83e12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18109
96601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.1810996601
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.2310551010
Short name T1685
Test name
Test status
Simulation time 234511377 ps
CPU time 0.91 seconds
Started Jun 25 05:00:30 PM PDT 24
Finished Jun 25 05:00:33 PM PDT 24
Peak memory 206568 kb
Host smart-ce1f54ea-a64e-41a2-8e5b-ea993b94e9f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23105
51010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.2310551010
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.2319120854
Short name T2065
Test name
Test status
Simulation time 137683347 ps
CPU time 0.77 seconds
Started Jun 25 05:00:28 PM PDT 24
Finished Jun 25 05:00:30 PM PDT 24
Peak memory 206576 kb
Host smart-463390c8-91ba-4298-a52a-b917563929f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23191
20854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.2319120854
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.1066263289
Short name T1569
Test name
Test status
Simulation time 187511800 ps
CPU time 0.91 seconds
Started Jun 25 05:00:21 PM PDT 24
Finished Jun 25 05:00:24 PM PDT 24
Peak memory 206568 kb
Host smart-089c8495-35d9-494c-9ea5-f26401ffdf65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10662
63289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.1066263289
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.1587248171
Short name T1519
Test name
Test status
Simulation time 260593486 ps
CPU time 1.01 seconds
Started Jun 25 05:00:23 PM PDT 24
Finished Jun 25 05:00:25 PM PDT 24
Peak memory 206572 kb
Host smart-e4d60ddd-17ba-44c2-ba87-1e00b8c10d55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15872
48171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.1587248171
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.3888513601
Short name T2127
Test name
Test status
Simulation time 23327841772 ps
CPU time 23.39 seconds
Started Jun 25 05:00:22 PM PDT 24
Finished Jun 25 05:00:47 PM PDT 24
Peak memory 206720 kb
Host smart-3a22b516-6ee5-48aa-bf26-2e242d8ca81c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38885
13601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.3888513601
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.4176883862
Short name T564
Test name
Test status
Simulation time 3296413577 ps
CPU time 3.74 seconds
Started Jun 25 05:00:20 PM PDT 24
Finished Jun 25 05:00:26 PM PDT 24
Peak memory 206708 kb
Host smart-0a8618cc-d446-42e0-8dfc-9dcd6ce9697b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41768
83862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.4176883862
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.2301667581
Short name T1932
Test name
Test status
Simulation time 6556749962 ps
CPU time 47.37 seconds
Started Jun 25 05:00:22 PM PDT 24
Finished Jun 25 05:01:11 PM PDT 24
Peak memory 206896 kb
Host smart-0273341f-d74e-45bb-9dc9-321716d03d4a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2301667581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.2301667581
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.3800884077
Short name T1713
Test name
Test status
Simulation time 264058819 ps
CPU time 0.92 seconds
Started Jun 25 05:00:29 PM PDT 24
Finished Jun 25 05:00:31 PM PDT 24
Peak memory 206548 kb
Host smart-b8fa55bd-d089-430b-bb27-0d07f4da5e60
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3800884077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.3800884077
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.1989987591
Short name T1837
Test name
Test status
Simulation time 189371899 ps
CPU time 0.89 seconds
Started Jun 25 05:00:22 PM PDT 24
Finished Jun 25 05:00:24 PM PDT 24
Peak memory 206520 kb
Host smart-0a34d5b3-6606-4045-a653-aae325b743e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19899
87591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.1989987591
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.3212243938
Short name T550
Test name
Test status
Simulation time 3836079394 ps
CPU time 104.95 seconds
Started Jun 25 05:00:20 PM PDT 24
Finished Jun 25 05:02:06 PM PDT 24
Peak memory 206940 kb
Host smart-9e88b736-c844-48ed-b9cc-9fa31c0d0da4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32122
43938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.3212243938
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.2720744893
Short name T876
Test name
Test status
Simulation time 6590497424 ps
CPU time 45.67 seconds
Started Jun 25 05:00:24 PM PDT 24
Finished Jun 25 05:01:12 PM PDT 24
Peak memory 206888 kb
Host smart-ce32d4c9-e4a7-44d9-8c2d-cd92b1f0fac8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2720744893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.2720744893
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.263063683
Short name T2184
Test name
Test status
Simulation time 165577195 ps
CPU time 0.79 seconds
Started Jun 25 05:00:30 PM PDT 24
Finished Jun 25 05:00:34 PM PDT 24
Peak memory 206600 kb
Host smart-91683dfd-403b-4aaa-a303-3537ab732c1c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=263063683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.263063683
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.2706462686
Short name T1635
Test name
Test status
Simulation time 149856733 ps
CPU time 0.79 seconds
Started Jun 25 05:00:21 PM PDT 24
Finished Jun 25 05:00:23 PM PDT 24
Peak memory 206476 kb
Host smart-08575342-b013-4076-8d92-66f1ebdd796a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27064
62686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.2706462686
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.3823264743
Short name T922
Test name
Test status
Simulation time 149381382 ps
CPU time 0.78 seconds
Started Jun 25 05:00:27 PM PDT 24
Finished Jun 25 05:00:29 PM PDT 24
Peak memory 206496 kb
Host smart-1614ee43-cd6a-41e3-a88f-b4dad5efe0fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38232
64743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.3823264743
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.2136376005
Short name T392
Test name
Test status
Simulation time 199730624 ps
CPU time 0.82 seconds
Started Jun 25 05:00:29 PM PDT 24
Finished Jun 25 05:00:31 PM PDT 24
Peak memory 206580 kb
Host smart-73bbd2f5-9271-4502-acee-418b4c42921d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21363
76005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.2136376005
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.3436755393
Short name T1411
Test name
Test status
Simulation time 164721745 ps
CPU time 0.79 seconds
Started Jun 25 05:00:34 PM PDT 24
Finished Jun 25 05:00:37 PM PDT 24
Peak memory 206572 kb
Host smart-0cb7a4b4-c3ae-47c5-b7d3-9e6fa4e55357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34367
55393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.3436755393
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.4200230601
Short name T772
Test name
Test status
Simulation time 228439731 ps
CPU time 0.83 seconds
Started Jun 25 05:00:31 PM PDT 24
Finished Jun 25 05:00:34 PM PDT 24
Peak memory 206580 kb
Host smart-b4e363fe-249b-4a18-8195-19acd5391f54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42002
30601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.4200230601
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.474025620
Short name T1460
Test name
Test status
Simulation time 241669808 ps
CPU time 0.9 seconds
Started Jun 25 05:00:28 PM PDT 24
Finished Jun 25 05:00:30 PM PDT 24
Peak memory 206504 kb
Host smart-2010e1d8-0dd6-4961-888d-858806099612
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=474025620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.474025620
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.2774041435
Short name T1039
Test name
Test status
Simulation time 179157017 ps
CPU time 0.84 seconds
Started Jun 25 05:00:29 PM PDT 24
Finished Jun 25 05:00:31 PM PDT 24
Peak memory 206532 kb
Host smart-d9d10313-00b6-4bf2-9f9b-bfe9b6327e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27740
41435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.2774041435
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.2515623960
Short name T720
Test name
Test status
Simulation time 44766509 ps
CPU time 0.68 seconds
Started Jun 25 05:00:29 PM PDT 24
Finished Jun 25 05:00:32 PM PDT 24
Peak memory 206584 kb
Host smart-3fbe2349-ec5a-4d20-8203-753ff57aaf44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25156
23960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.2515623960
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.2770228162
Short name T1604
Test name
Test status
Simulation time 6732996394 ps
CPU time 15.38 seconds
Started Jun 25 05:00:30 PM PDT 24
Finished Jun 25 05:00:48 PM PDT 24
Peak memory 206876 kb
Host smart-9b84aaff-8d9d-4fd8-ac9f-e1bef7f732fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27702
28162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.2770228162
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.1089919008
Short name T2346
Test name
Test status
Simulation time 189890121 ps
CPU time 0.83 seconds
Started Jun 25 05:00:29 PM PDT 24
Finished Jun 25 05:00:31 PM PDT 24
Peak memory 206556 kb
Host smart-53e06fd2-1f60-4bba-b276-9cc351a2d62b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10899
19008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.1089919008
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.2287449704
Short name T2244
Test name
Test status
Simulation time 226657893 ps
CPU time 0.93 seconds
Started Jun 25 05:00:30 PM PDT 24
Finished Jun 25 05:00:34 PM PDT 24
Peak memory 206516 kb
Host smart-b650add4-3d58-4195-87d2-d60ac076b2d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22874
49704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.2287449704
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.3941891924
Short name T2211
Test name
Test status
Simulation time 237233537 ps
CPU time 0.91 seconds
Started Jun 25 05:00:33 PM PDT 24
Finished Jun 25 05:00:36 PM PDT 24
Peak memory 206532 kb
Host smart-887eda2c-9614-4b28-9ad1-627bb37adfb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39418
91924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.3941891924
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.3446415756
Short name T2061
Test name
Test status
Simulation time 183648825 ps
CPU time 0.85 seconds
Started Jun 25 05:00:32 PM PDT 24
Finished Jun 25 05:00:35 PM PDT 24
Peak memory 206568 kb
Host smart-3b18e44c-57d7-4ec5-89e8-680a7dd5666e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34464
15756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.3446415756
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.1775668550
Short name T526
Test name
Test status
Simulation time 190329805 ps
CPU time 0.84 seconds
Started Jun 25 05:00:30 PM PDT 24
Finished Jun 25 05:00:34 PM PDT 24
Peak memory 206600 kb
Host smart-e2240781-3d4d-440b-ad9a-560f84452d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17756
68550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.1775668550
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.3555657246
Short name T355
Test name
Test status
Simulation time 150478459 ps
CPU time 0.77 seconds
Started Jun 25 05:00:34 PM PDT 24
Finished Jun 25 05:00:37 PM PDT 24
Peak memory 206588 kb
Host smart-f54d1a1f-6b57-458b-84b2-3efe61a6c470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35556
57246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.3555657246
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.127249153
Short name T1404
Test name
Test status
Simulation time 155744608 ps
CPU time 0.81 seconds
Started Jun 25 05:00:31 PM PDT 24
Finished Jun 25 05:00:34 PM PDT 24
Peak memory 206572 kb
Host smart-6d390a4d-4073-4f3c-89e6-69e159e69681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12724
9153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.127249153
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.1452575182
Short name T1711
Test name
Test status
Simulation time 224003604 ps
CPU time 0.97 seconds
Started Jun 25 05:00:29 PM PDT 24
Finished Jun 25 05:00:32 PM PDT 24
Peak memory 206588 kb
Host smart-a45a4596-98dc-4350-8175-fe12dc6d74ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14525
75182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.1452575182
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.2848181232
Short name T2063
Test name
Test status
Simulation time 5486703706 ps
CPU time 52.91 seconds
Started Jun 25 05:00:30 PM PDT 24
Finished Jun 25 05:01:25 PM PDT 24
Peak memory 206932 kb
Host smart-f08df13c-ca5a-45e7-b093-7c952ee4dc20
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2848181232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.2848181232
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.3584395456
Short name T1762
Test name
Test status
Simulation time 201199661 ps
CPU time 0.8 seconds
Started Jun 25 05:00:30 PM PDT 24
Finished Jun 25 05:00:33 PM PDT 24
Peak memory 206520 kb
Host smart-4d9eb5da-5c8c-4d03-8a50-a77f1bde7661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35843
95456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.3584395456
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.2540600211
Short name T957
Test name
Test status
Simulation time 203955833 ps
CPU time 0.88 seconds
Started Jun 25 05:00:31 PM PDT 24
Finished Jun 25 05:00:34 PM PDT 24
Peak memory 206496 kb
Host smart-625d2ddb-1c15-417e-a219-c1334730e104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25406
00211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.2540600211
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.3959158597
Short name T435
Test name
Test status
Simulation time 5274659498 ps
CPU time 148.88 seconds
Started Jun 25 05:00:33 PM PDT 24
Finished Jun 25 05:03:04 PM PDT 24
Peak memory 206856 kb
Host smart-e1d435f2-6fd4-40aa-9f53-465c93aef637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39591
58597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.3959158597
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.1360458731
Short name T851
Test name
Test status
Simulation time 3513524857 ps
CPU time 4.1 seconds
Started Jun 25 05:00:29 PM PDT 24
Finished Jun 25 05:00:35 PM PDT 24
Peak memory 206688 kb
Host smart-2d3d1612-ff84-405a-98d8-373ac17503fa
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1360458731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.1360458731
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.1440239377
Short name T359
Test name
Test status
Simulation time 13419152951 ps
CPU time 12.84 seconds
Started Jun 25 05:00:30 PM PDT 24
Finished Jun 25 05:00:45 PM PDT 24
Peak memory 206724 kb
Host smart-fb52dc4a-95e4-44b0-8a90-32af51fd6235
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1440239377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.1440239377
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.4107435581
Short name T498
Test name
Test status
Simulation time 23420397362 ps
CPU time 26.91 seconds
Started Jun 25 05:00:30 PM PDT 24
Finished Jun 25 05:00:59 PM PDT 24
Peak memory 206860 kb
Host smart-a048e453-aa13-409e-9974-6815e5465553
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4107435581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.4107435581
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.2947450979
Short name T885
Test name
Test status
Simulation time 179334565 ps
CPU time 0.85 seconds
Started Jun 25 05:00:34 PM PDT 24
Finished Jun 25 05:00:37 PM PDT 24
Peak memory 206572 kb
Host smart-2c191de3-7044-4d99-a015-da7ae73b7189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29474
50979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.2947450979
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.2138414227
Short name T2407
Test name
Test status
Simulation time 152792033 ps
CPU time 0.8 seconds
Started Jun 25 05:00:35 PM PDT 24
Finished Jun 25 05:00:37 PM PDT 24
Peak memory 206508 kb
Host smart-3fe2a069-edee-4d4b-9f9b-d8613d8f530c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21384
14227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.2138414227
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.829487289
Short name T1648
Test name
Test status
Simulation time 404999328 ps
CPU time 1.3 seconds
Started Jun 25 05:00:29 PM PDT 24
Finished Jun 25 05:00:32 PM PDT 24
Peak memory 206752 kb
Host smart-7e1796a3-a860-4a2c-9341-f708683b6c30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82948
7289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.829487289
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.1035439996
Short name T1931
Test name
Test status
Simulation time 1306991303 ps
CPU time 2.69 seconds
Started Jun 25 05:00:31 PM PDT 24
Finished Jun 25 05:00:36 PM PDT 24
Peak memory 206676 kb
Host smart-9b9587b1-161d-4c1a-8ad6-d321ec4cc2c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10354
39996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.1035439996
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.872239709
Short name T1979
Test name
Test status
Simulation time 17470332623 ps
CPU time 40.98 seconds
Started Jun 25 05:00:29 PM PDT 24
Finished Jun 25 05:01:12 PM PDT 24
Peak memory 206908 kb
Host smart-d58666f9-0512-4c76-a366-7663e738c3db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87223
9709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.872239709
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.624626572
Short name T377
Test name
Test status
Simulation time 484831985 ps
CPU time 1.63 seconds
Started Jun 25 05:00:32 PM PDT 24
Finished Jun 25 05:00:36 PM PDT 24
Peak memory 206572 kb
Host smart-a056b3aa-9d9f-4161-b6f6-48ef23288869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62462
6572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.624626572
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.1437506881
Short name T2468
Test name
Test status
Simulation time 171858178 ps
CPU time 0.87 seconds
Started Jun 25 05:00:31 PM PDT 24
Finished Jun 25 05:00:34 PM PDT 24
Peak memory 206872 kb
Host smart-bdb7d5cd-3502-4b12-9c83-272f826dd783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14375
06881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.1437506881
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.3575330053
Short name T1048
Test name
Test status
Simulation time 28592938 ps
CPU time 0.66 seconds
Started Jun 25 05:00:29 PM PDT 24
Finished Jun 25 05:00:32 PM PDT 24
Peak memory 206484 kb
Host smart-432876bc-c057-441f-8872-d3dbedf9dca2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35753
30053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.3575330053
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.1724592541
Short name T1985
Test name
Test status
Simulation time 841368065 ps
CPU time 1.98 seconds
Started Jun 25 05:00:30 PM PDT 24
Finished Jun 25 05:00:34 PM PDT 24
Peak memory 206688 kb
Host smart-c9448451-34cb-4403-875c-9138b4842988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17245
92541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.1724592541
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.3867493167
Short name T2321
Test name
Test status
Simulation time 350108949 ps
CPU time 2.21 seconds
Started Jun 25 05:00:31 PM PDT 24
Finished Jun 25 05:00:35 PM PDT 24
Peak memory 207040 kb
Host smart-a697bc9f-5910-4aac-8bf9-79473aa6a18d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38674
93167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.3867493167
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.2184550291
Short name T2472
Test name
Test status
Simulation time 176135252 ps
CPU time 0.85 seconds
Started Jun 25 05:00:43 PM PDT 24
Finished Jun 25 05:00:45 PM PDT 24
Peak memory 206496 kb
Host smart-72eae70c-5791-4092-a050-ca388330109e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21845
50291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.2184550291
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.3075992440
Short name T2038
Test name
Test status
Simulation time 160374388 ps
CPU time 0.79 seconds
Started Jun 25 05:00:42 PM PDT 24
Finished Jun 25 05:00:44 PM PDT 24
Peak memory 206568 kb
Host smart-3ef9ec7a-8d6e-4d9b-8485-b7d7145709fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30759
92440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.3075992440
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.4001461080
Short name T1647
Test name
Test status
Simulation time 231115446 ps
CPU time 0.97 seconds
Started Jun 25 05:00:31 PM PDT 24
Finished Jun 25 05:00:34 PM PDT 24
Peak memory 206480 kb
Host smart-938ca28a-af11-40c8-a48e-9423a0203bea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40014
61080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.4001461080
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.2210602783
Short name T2369
Test name
Test status
Simulation time 247797501 ps
CPU time 0.88 seconds
Started Jun 25 05:00:33 PM PDT 24
Finished Jun 25 05:00:36 PM PDT 24
Peak memory 206572 kb
Host smart-40fd028b-3b2a-4d66-9874-1d83de025887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22106
02783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.2210602783
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.3243058471
Short name T472
Test name
Test status
Simulation time 23326579034 ps
CPU time 24.31 seconds
Started Jun 25 05:00:32 PM PDT 24
Finished Jun 25 05:00:59 PM PDT 24
Peak memory 206688 kb
Host smart-84b71fa7-7f6f-4852-8941-8d5addfb68c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32430
58471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.3243058471
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.377969037
Short name T350
Test name
Test status
Simulation time 3349212289 ps
CPU time 3.99 seconds
Started Jun 25 05:00:32 PM PDT 24
Finished Jun 25 05:00:39 PM PDT 24
Peak memory 206688 kb
Host smart-b8fb093d-073a-4891-9131-3abb2065753f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37796
9037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.377969037
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.463563036
Short name T1364
Test name
Test status
Simulation time 4848942060 ps
CPU time 46.26 seconds
Started Jun 25 05:00:33 PM PDT 24
Finished Jun 25 05:01:22 PM PDT 24
Peak memory 206880 kb
Host smart-c45ca438-8e9e-4384-999c-16f953542fd4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=463563036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.463563036
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.2995237157
Short name T887
Test name
Test status
Simulation time 242076058 ps
CPU time 0.88 seconds
Started Jun 25 05:00:39 PM PDT 24
Finished Jun 25 05:00:41 PM PDT 24
Peak memory 206516 kb
Host smart-edde189d-6e94-4e62-8688-a0fde7fde2e8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2995237157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.2995237157
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.719213709
Short name T818
Test name
Test status
Simulation time 199907113 ps
CPU time 0.84 seconds
Started Jun 25 05:00:32 PM PDT 24
Finished Jun 25 05:00:35 PM PDT 24
Peak memory 206584 kb
Host smart-4eb0c4b6-ab46-4454-a772-2d0c3c1b6134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71921
3709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.719213709
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.845775864
Short name T2438
Test name
Test status
Simulation time 6221290216 ps
CPU time 58.2 seconds
Started Jun 25 05:00:31 PM PDT 24
Finished Jun 25 05:01:31 PM PDT 24
Peak memory 206740 kb
Host smart-da71216f-cac0-424a-9e9b-6e5200218c4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84577
5864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.845775864
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.3803959752
Short name T1391
Test name
Test status
Simulation time 6825733058 ps
CPU time 191.05 seconds
Started Jun 25 05:00:32 PM PDT 24
Finished Jun 25 05:03:46 PM PDT 24
Peak memory 206976 kb
Host smart-1ed2226a-1be2-4d5e-abb3-ce16a367dbf9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3803959752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.3803959752
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.319316289
Short name T1601
Test name
Test status
Simulation time 155174653 ps
CPU time 0.83 seconds
Started Jun 25 05:00:42 PM PDT 24
Finished Jun 25 05:00:44 PM PDT 24
Peak memory 206480 kb
Host smart-04b046f0-f6ed-4878-9167-83b955c4a940
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=319316289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.319316289
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.4018033789
Short name T315
Test name
Test status
Simulation time 196417496 ps
CPU time 0.89 seconds
Started Jun 25 05:00:33 PM PDT 24
Finished Jun 25 05:00:36 PM PDT 24
Peak memory 206596 kb
Host smart-d8ea17fa-3029-485f-b5b2-164804a06338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40180
33789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.4018033789
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.4151092420
Short name T1609
Test name
Test status
Simulation time 160672533 ps
CPU time 0.83 seconds
Started Jun 25 05:00:35 PM PDT 24
Finished Jun 25 05:00:37 PM PDT 24
Peak memory 206560 kb
Host smart-c3b388f9-2c8f-4a2e-bc79-464ea4f49f3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41510
92420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.4151092420
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.88619888
Short name T2125
Test name
Test status
Simulation time 177401305 ps
CPU time 0.85 seconds
Started Jun 25 05:00:30 PM PDT 24
Finished Jun 25 05:00:33 PM PDT 24
Peak memory 206588 kb
Host smart-46905343-d253-49a2-a0d1-ddef2228cc73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88619
888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.88619888
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.2152337963
Short name T1487
Test name
Test status
Simulation time 180871134 ps
CPU time 0.82 seconds
Started Jun 25 05:00:33 PM PDT 24
Finished Jun 25 05:00:36 PM PDT 24
Peak memory 206572 kb
Host smart-ae25eab5-e095-4eed-9d2d-3e8c391d834c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21523
37963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.2152337963
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.1133725074
Short name T1812
Test name
Test status
Simulation time 154155530 ps
CPU time 0.81 seconds
Started Jun 25 05:00:32 PM PDT 24
Finished Jun 25 05:00:35 PM PDT 24
Peak memory 206568 kb
Host smart-cee3037c-dd66-45fa-86d7-c39131dd733b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11337
25074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.1133725074
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.606559445
Short name T1710
Test name
Test status
Simulation time 226623340 ps
CPU time 0.93 seconds
Started Jun 25 05:00:31 PM PDT 24
Finished Jun 25 05:00:34 PM PDT 24
Peak memory 206508 kb
Host smart-8cebf5f0-a2f7-4f87-9c13-1e5e3870d63e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=606559445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.606559445
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.347871601
Short name T551
Test name
Test status
Simulation time 250695975 ps
CPU time 0.81 seconds
Started Jun 25 05:00:29 PM PDT 24
Finished Jun 25 05:00:31 PM PDT 24
Peak memory 206576 kb
Host smart-f5493c5f-ecd9-4fa4-add8-a304250e37b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34787
1601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.347871601
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.2519976223
Short name T2234
Test name
Test status
Simulation time 48401085 ps
CPU time 0.67 seconds
Started Jun 25 05:00:29 PM PDT 24
Finished Jun 25 05:00:32 PM PDT 24
Peak memory 206588 kb
Host smart-40acae90-5199-456b-a0cd-2c0691fbed91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25199
76223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.2519976223
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.3233147828
Short name T2336
Test name
Test status
Simulation time 10805133179 ps
CPU time 24.48 seconds
Started Jun 25 05:00:33 PM PDT 24
Finished Jun 25 05:00:59 PM PDT 24
Peak memory 206952 kb
Host smart-302456d9-e7c0-4439-9d68-875ec1567efc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32331
47828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.3233147828
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.633658188
Short name T1477
Test name
Test status
Simulation time 155320018 ps
CPU time 0.8 seconds
Started Jun 25 05:00:29 PM PDT 24
Finished Jun 25 05:00:31 PM PDT 24
Peak memory 206564 kb
Host smart-83c8064e-561a-4a9e-8483-a66f6d99251b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63365
8188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.633658188
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.1765012851
Short name T1072
Test name
Test status
Simulation time 222800540 ps
CPU time 0.9 seconds
Started Jun 25 05:00:32 PM PDT 24
Finished Jun 25 05:00:36 PM PDT 24
Peak memory 206592 kb
Host smart-351b7868-0b01-4c80-85ee-13e2611d80ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17650
12851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.1765012851
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.350931509
Short name T2031
Test name
Test status
Simulation time 186906532 ps
CPU time 0.81 seconds
Started Jun 25 05:00:43 PM PDT 24
Finished Jun 25 05:00:46 PM PDT 24
Peak memory 206528 kb
Host smart-0ed0a241-11ac-42e7-8c3d-3ca8b0b2d541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35093
1509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.350931509
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.2148307130
Short name T2337
Test name
Test status
Simulation time 162337931 ps
CPU time 0.79 seconds
Started Jun 25 05:00:34 PM PDT 24
Finished Jun 25 05:00:37 PM PDT 24
Peak memory 206596 kb
Host smart-be4e9273-d048-4980-a591-037b47bddf15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21483
07130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.2148307130
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.3769717614
Short name T434
Test name
Test status
Simulation time 142319865 ps
CPU time 0.78 seconds
Started Jun 25 05:00:33 PM PDT 24
Finished Jun 25 05:00:36 PM PDT 24
Peak memory 206568 kb
Host smart-0604ecb8-ad09-43b5-a74d-851f6a058b62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37697
17614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.3769717614
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.311214864
Short name T1333
Test name
Test status
Simulation time 151655357 ps
CPU time 0.73 seconds
Started Jun 25 05:00:31 PM PDT 24
Finished Jun 25 05:00:34 PM PDT 24
Peak memory 206556 kb
Host smart-e961daa3-74d3-40f9-8be0-7ccb62d0df7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31121
4864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.311214864
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.2954608895
Short name T1672
Test name
Test status
Simulation time 148876084 ps
CPU time 0.75 seconds
Started Jun 25 05:00:30 PM PDT 24
Finished Jun 25 05:00:33 PM PDT 24
Peak memory 206556 kb
Host smart-61a8bcf2-4779-4a98-af76-3375fb37958d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29546
08895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.2954608895
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.2246897026
Short name T1302
Test name
Test status
Simulation time 253325021 ps
CPU time 0.96 seconds
Started Jun 25 05:00:32 PM PDT 24
Finished Jun 25 05:00:35 PM PDT 24
Peak memory 206584 kb
Host smart-68849da2-a7a5-4b5b-819e-4b12f4d978f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22468
97026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.2246897026
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.288813512
Short name T1642
Test name
Test status
Simulation time 11696871726 ps
CPU time 117.66 seconds
Started Jun 25 05:00:33 PM PDT 24
Finished Jun 25 05:02:33 PM PDT 24
Peak memory 206872 kb
Host smart-eac8c766-a4ec-45eb-8d68-3ef99d459c84
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=288813512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.288813512
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.1293831218
Short name T1759
Test name
Test status
Simulation time 161107773 ps
CPU time 0.82 seconds
Started Jun 25 05:00:33 PM PDT 24
Finished Jun 25 05:00:36 PM PDT 24
Peak memory 206584 kb
Host smart-b50048bb-3344-484f-aca3-6c5b93777284
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12938
31218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.1293831218
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.2571725072
Short name T2515
Test name
Test status
Simulation time 173512861 ps
CPU time 0.8 seconds
Started Jun 25 05:00:32 PM PDT 24
Finished Jun 25 05:00:35 PM PDT 24
Peak memory 206572 kb
Host smart-e05b744b-e625-4048-bd9a-9050bfdb4701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25717
25072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.2571725072
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.402947156
Short name T727
Test name
Test status
Simulation time 3812894387 ps
CPU time 27.16 seconds
Started Jun 25 05:00:28 PM PDT 24
Finished Jun 25 05:00:57 PM PDT 24
Peak memory 206892 kb
Host smart-4554683b-5a2e-463e-920b-d4021e70ddbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40294
7156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.402947156
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.769374236
Short name T2476
Test name
Test status
Simulation time 3986480107 ps
CPU time 5.13 seconds
Started Jun 25 05:00:42 PM PDT 24
Finished Jun 25 05:00:48 PM PDT 24
Peak memory 206652 kb
Host smart-14153eb2-43fe-4fde-aad3-5f622952af31
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=769374236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.769374236
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.175493374
Short name T1888
Test name
Test status
Simulation time 13337904421 ps
CPU time 12.4 seconds
Started Jun 25 05:00:42 PM PDT 24
Finished Jun 25 05:00:55 PM PDT 24
Peak memory 206968 kb
Host smart-5ab33652-1118-4656-802d-bd116a4617a5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=175493374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.175493374
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.342738961
Short name T1047
Test name
Test status
Simulation time 23383220976 ps
CPU time 28.9 seconds
Started Jun 25 05:00:43 PM PDT 24
Finished Jun 25 05:01:13 PM PDT 24
Peak memory 206644 kb
Host smart-74adcaf7-1029-44b3-ba18-6b4d73b505c0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=342738961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.342738961
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.1807335851
Short name T1860
Test name
Test status
Simulation time 146236053 ps
CPU time 0.82 seconds
Started Jun 25 05:00:43 PM PDT 24
Finished Jun 25 05:00:45 PM PDT 24
Peak memory 206500 kb
Host smart-dff92bd6-fb58-46c2-b4c7-4840efc9583f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18073
35851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.1807335851
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.3979030344
Short name T2220
Test name
Test status
Simulation time 154713573 ps
CPU time 0.87 seconds
Started Jun 25 05:00:42 PM PDT 24
Finished Jun 25 05:00:45 PM PDT 24
Peak memory 206580 kb
Host smart-66cef07a-8845-4e93-922c-6efafec93c14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39790
30344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.3979030344
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.2573893830
Short name T1750
Test name
Test status
Simulation time 519261201 ps
CPU time 1.47 seconds
Started Jun 25 05:00:40 PM PDT 24
Finished Jun 25 05:00:43 PM PDT 24
Peak memory 206772 kb
Host smart-3f49b197-641a-460e-9f6e-dad94bef730e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25738
93830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.2573893830
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.4060652731
Short name T562
Test name
Test status
Simulation time 539376378 ps
CPU time 1.38 seconds
Started Jun 25 05:00:41 PM PDT 24
Finished Jun 25 05:00:44 PM PDT 24
Peak memory 206500 kb
Host smart-222a158f-51e8-4520-a070-35d0efc63dd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40606
52731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.4060652731
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.2004198718
Short name T1880
Test name
Test status
Simulation time 6531806603 ps
CPU time 13.6 seconds
Started Jun 25 05:00:40 PM PDT 24
Finished Jun 25 05:00:54 PM PDT 24
Peak memory 206864 kb
Host smart-2cf53797-7e21-47e1-910d-dbe314de7593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20041
98718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.2004198718
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.3630961318
Short name T1390
Test name
Test status
Simulation time 427627847 ps
CPU time 1.39 seconds
Started Jun 25 05:00:42 PM PDT 24
Finished Jun 25 05:00:45 PM PDT 24
Peak memory 206572 kb
Host smart-63b5ed97-cba5-474e-bd3b-a978e900e11a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36309
61318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.3630961318
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_enable.32945692
Short name T1588
Test name
Test status
Simulation time 55675840 ps
CPU time 0.69 seconds
Started Jun 25 05:00:45 PM PDT 24
Finished Jun 25 05:00:47 PM PDT 24
Peak memory 206528 kb
Host smart-a824cef3-7d25-4cc8-9b92-496b3f86f3d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32945
692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.32945692
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.550435379
Short name T634
Test name
Test status
Simulation time 844843769 ps
CPU time 2.14 seconds
Started Jun 25 05:00:46 PM PDT 24
Finished Jun 25 05:00:49 PM PDT 24
Peak memory 206736 kb
Host smart-b8c77f44-db75-4de9-a0df-0bd89862ff7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55043
5379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.550435379
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.97853921
Short name T1338
Test name
Test status
Simulation time 193000433 ps
CPU time 1.31 seconds
Started Jun 25 05:00:44 PM PDT 24
Finished Jun 25 05:00:48 PM PDT 24
Peak memory 206816 kb
Host smart-c1521bb7-9ca2-4504-8b59-7f8702a092cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97853
921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.97853921
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.618861587
Short name T1469
Test name
Test status
Simulation time 221342543 ps
CPU time 0.88 seconds
Started Jun 25 05:00:43 PM PDT 24
Finished Jun 25 05:00:45 PM PDT 24
Peak memory 206588 kb
Host smart-9d414b35-a590-4186-83a5-4aa1c6a0fc5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61886
1587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.618861587
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.3293058583
Short name T1063
Test name
Test status
Simulation time 139176046 ps
CPU time 0.79 seconds
Started Jun 25 05:00:42 PM PDT 24
Finished Jun 25 05:00:44 PM PDT 24
Peak memory 206600 kb
Host smart-b3ecd67a-e3df-4c1e-a892-55c2996abb11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32930
58583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.3293058583
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.2132167853
Short name T2381
Test name
Test status
Simulation time 206107244 ps
CPU time 0.86 seconds
Started Jun 25 05:00:40 PM PDT 24
Finished Jun 25 05:00:42 PM PDT 24
Peak memory 206576 kb
Host smart-ee4841d8-ffbe-4064-a10f-c579508cd480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21321
67853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.2132167853
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.2108309880
Short name T2191
Test name
Test status
Simulation time 184143527 ps
CPU time 0.8 seconds
Started Jun 25 05:00:40 PM PDT 24
Finished Jun 25 05:00:42 PM PDT 24
Peak memory 206560 kb
Host smart-cccf3474-a642-4ceb-b36d-2eda4095341d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21083
09880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.2108309880
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.780282679
Short name T1415
Test name
Test status
Simulation time 23342540314 ps
CPU time 24.5 seconds
Started Jun 25 05:00:41 PM PDT 24
Finished Jun 25 05:01:07 PM PDT 24
Peak memory 206720 kb
Host smart-4fe78f6f-994b-4dbe-8f81-7be62ed3b2d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78028
2679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.780282679
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.3473108337
Short name T2099
Test name
Test status
Simulation time 3270640381 ps
CPU time 4.52 seconds
Started Jun 25 05:00:46 PM PDT 24
Finished Jun 25 05:00:51 PM PDT 24
Peak memory 206700 kb
Host smart-7a86148d-18fa-46f3-9fae-e1db89c2a62c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34731
08337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.3473108337
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.1222713156
Short name T1129
Test name
Test status
Simulation time 6434896342 ps
CPU time 183.1 seconds
Started Jun 25 05:00:45 PM PDT 24
Finished Jun 25 05:03:50 PM PDT 24
Peak memory 206872 kb
Host smart-e7d19019-4232-4cf5-9ca3-da2bae7f06bc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1222713156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.1222713156
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.523982764
Short name T2018
Test name
Test status
Simulation time 248173853 ps
CPU time 0.92 seconds
Started Jun 25 05:00:51 PM PDT 24
Finished Jun 25 05:00:53 PM PDT 24
Peak memory 206592 kb
Host smart-7ef1e2aa-4669-4d50-9ec5-f2afd1846113
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=523982764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.523982764
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.1401952902
Short name T1857
Test name
Test status
Simulation time 191120335 ps
CPU time 0.88 seconds
Started Jun 25 05:00:43 PM PDT 24
Finished Jun 25 05:00:46 PM PDT 24
Peak memory 206508 kb
Host smart-2e59d3ad-5ebc-4e6e-86f0-0a276109f920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14019
52902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.1401952902
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.2752862745
Short name T1228
Test name
Test status
Simulation time 8748244836 ps
CPU time 242.79 seconds
Started Jun 25 05:00:42 PM PDT 24
Finished Jun 25 05:04:46 PM PDT 24
Peak memory 206860 kb
Host smart-57f56a91-2156-4dcd-970a-a9cbdeb61578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27528
62745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.2752862745
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.166811460
Short name T2372
Test name
Test status
Simulation time 14767797245 ps
CPU time 435.3 seconds
Started Jun 25 05:00:44 PM PDT 24
Finished Jun 25 05:08:02 PM PDT 24
Peak memory 206948 kb
Host smart-e7d74e0a-b918-4fef-9fa8-a48d05cfb4c7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=166811460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.166811460
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.2480804120
Short name T1991
Test name
Test status
Simulation time 158723895 ps
CPU time 0.88 seconds
Started Jun 25 05:00:45 PM PDT 24
Finished Jun 25 05:00:47 PM PDT 24
Peak memory 206500 kb
Host smart-132292e1-2a21-417d-8af5-68d0aaa6460a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2480804120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.2480804120
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.3786729566
Short name T1844
Test name
Test status
Simulation time 147648419 ps
CPU time 0.81 seconds
Started Jun 25 05:00:43 PM PDT 24
Finished Jun 25 05:00:45 PM PDT 24
Peak memory 206576 kb
Host smart-4a30b9ca-7467-48c8-8b77-0b3ddaf523d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37867
29566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.3786729566
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.1125331257
Short name T129
Test name
Test status
Simulation time 211930830 ps
CPU time 0.89 seconds
Started Jun 25 05:00:44 PM PDT 24
Finished Jun 25 05:00:46 PM PDT 24
Peak memory 206592 kb
Host smart-46ce39d7-b0d6-4b5e-8093-f9f3358d9191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11253
31257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.1125331257
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.2138493026
Short name T2094
Test name
Test status
Simulation time 146889185 ps
CPU time 0.81 seconds
Started Jun 25 05:00:43 PM PDT 24
Finished Jun 25 05:00:45 PM PDT 24
Peak memory 206568 kb
Host smart-ab02c6fc-37d9-4a8b-be3d-197f342f5120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21384
93026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.2138493026
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.2289948750
Short name T2146
Test name
Test status
Simulation time 193443052 ps
CPU time 0.82 seconds
Started Jun 25 05:00:41 PM PDT 24
Finished Jun 25 05:00:43 PM PDT 24
Peak memory 206556 kb
Host smart-a30ac824-1962-4b52-830a-ed5beb521463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22899
48750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.2289948750
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.2489034889
Short name T2006
Test name
Test status
Simulation time 254039942 ps
CPU time 0.92 seconds
Started Jun 25 05:00:44 PM PDT 24
Finished Jun 25 05:00:47 PM PDT 24
Peak memory 206580 kb
Host smart-f098bcff-82cc-4cd0-8e2d-a44a6feac258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24890
34889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.2489034889
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.2662456513
Short name T2492
Test name
Test status
Simulation time 184668898 ps
CPU time 0.83 seconds
Started Jun 25 05:00:43 PM PDT 24
Finished Jun 25 05:00:45 PM PDT 24
Peak memory 206572 kb
Host smart-31401330-3196-4eb4-ab4a-2fb605b3c3ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26624
56513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.2662456513
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.1304234647
Short name T50
Test name
Test status
Simulation time 256009000 ps
CPU time 0.99 seconds
Started Jun 25 05:00:46 PM PDT 24
Finished Jun 25 05:00:48 PM PDT 24
Peak memory 206584 kb
Host smart-9252efd1-e49b-4baa-ae8e-3aedf89286d6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1304234647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.1304234647
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.1834822849
Short name T188
Test name
Test status
Simulation time 167181946 ps
CPU time 0.79 seconds
Started Jun 25 05:00:43 PM PDT 24
Finished Jun 25 05:00:45 PM PDT 24
Peak memory 206584 kb
Host smart-b1d9731d-a532-479e-93ce-ecf16c9a5cdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18348
22849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.1834822849
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.109747666
Short name T791
Test name
Test status
Simulation time 78148069 ps
CPU time 0.7 seconds
Started Jun 25 05:00:45 PM PDT 24
Finished Jun 25 05:00:47 PM PDT 24
Peak memory 206876 kb
Host smart-4335564a-20b3-4e3a-b493-ed70900ec983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10974
7666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.109747666
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.3749085787
Short name T1738
Test name
Test status
Simulation time 9405681285 ps
CPU time 20.95 seconds
Started Jun 25 05:00:44 PM PDT 24
Finished Jun 25 05:01:07 PM PDT 24
Peak memory 206836 kb
Host smart-4e9dfd6e-b09a-47ea-acfb-8f0151a0a367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37490
85787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.3749085787
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.4119995596
Short name T925
Test name
Test status
Simulation time 171420036 ps
CPU time 0.83 seconds
Started Jun 25 05:00:43 PM PDT 24
Finished Jun 25 05:00:45 PM PDT 24
Peak memory 206544 kb
Host smart-baae2cc0-1ab8-404a-af6d-13747a85c687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41199
95596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.4119995596
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.850894612
Short name T1324
Test name
Test status
Simulation time 234962839 ps
CPU time 0.93 seconds
Started Jun 25 05:00:44 PM PDT 24
Finished Jun 25 05:00:47 PM PDT 24
Peak memory 206572 kb
Host smart-05d5e176-4d6a-4541-8a05-90908004fb15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85089
4612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.850894612
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.667306003
Short name T1824
Test name
Test status
Simulation time 203494989 ps
CPU time 0.87 seconds
Started Jun 25 05:00:43 PM PDT 24
Finished Jun 25 05:00:45 PM PDT 24
Peak memory 206520 kb
Host smart-563de88e-ccba-4693-90c0-bf505dbbe5d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66730
6003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.667306003
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.550166083
Short name T1003
Test name
Test status
Simulation time 149563506 ps
CPU time 0.86 seconds
Started Jun 25 05:00:45 PM PDT 24
Finished Jun 25 05:00:47 PM PDT 24
Peak memory 206532 kb
Host smart-170d15c8-45eb-4e09-bf28-0da37cbdd2de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55016
6083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.550166083
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.2323487545
Short name T1420
Test name
Test status
Simulation time 164210660 ps
CPU time 0.82 seconds
Started Jun 25 05:00:43 PM PDT 24
Finished Jun 25 05:00:46 PM PDT 24
Peak memory 206600 kb
Host smart-8d48426e-e333-49eb-b6bd-661ad2d48513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23234
87545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.2323487545
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.671293359
Short name T1065
Test name
Test status
Simulation time 174476352 ps
CPU time 0.79 seconds
Started Jun 25 05:00:45 PM PDT 24
Finished Jun 25 05:00:47 PM PDT 24
Peak memory 206576 kb
Host smart-b93b39a8-5eea-4ddd-ab56-f46556e2ed49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67129
3359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.671293359
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.1216035715
Short name T1668
Test name
Test status
Simulation time 163964083 ps
CPU time 0.81 seconds
Started Jun 25 05:00:46 PM PDT 24
Finished Jun 25 05:00:48 PM PDT 24
Peak memory 206580 kb
Host smart-17914a2d-27b9-4900-9b4d-dad72451d91e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12160
35715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.1216035715
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.974682850
Short name T1062
Test name
Test status
Simulation time 210431906 ps
CPU time 0.92 seconds
Started Jun 25 05:00:45 PM PDT 24
Finished Jun 25 05:00:48 PM PDT 24
Peak memory 206504 kb
Host smart-a72ea476-6875-495d-bbf3-7262f889afa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97468
2850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.974682850
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.1354020190
Short name T743
Test name
Test status
Simulation time 13605450639 ps
CPU time 398.97 seconds
Started Jun 25 05:00:40 PM PDT 24
Finished Jun 25 05:07:19 PM PDT 24
Peak memory 206940 kb
Host smart-0255f02e-57cd-416d-8865-70ab01393b85
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1354020190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.1354020190
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.984224909
Short name T616
Test name
Test status
Simulation time 163563541 ps
CPU time 0.83 seconds
Started Jun 25 05:00:45 PM PDT 24
Finished Jun 25 05:00:47 PM PDT 24
Peak memory 206508 kb
Host smart-582e387e-1541-4c50-be46-b4437431b78b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98422
4909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.984224909
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.1855943732
Short name T894
Test name
Test status
Simulation time 224494626 ps
CPU time 0.9 seconds
Started Jun 25 05:00:42 PM PDT 24
Finished Jun 25 05:00:44 PM PDT 24
Peak memory 206568 kb
Host smart-9ee9d3f6-9dec-48f0-9ffb-537bd825e3af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18559
43732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.1855943732
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.2617711574
Short name T313
Test name
Test status
Simulation time 12145922110 ps
CPU time 334.95 seconds
Started Jun 25 05:00:44 PM PDT 24
Finished Jun 25 05:06:21 PM PDT 24
Peak memory 207228 kb
Host smart-2cb603f9-9c8c-48d7-af3a-b5b685100ca2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26177
11574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.2617711574
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.1996703267
Short name T1826
Test name
Test status
Simulation time 3660312973 ps
CPU time 4.46 seconds
Started Jun 25 05:00:52 PM PDT 24
Finished Jun 25 05:00:58 PM PDT 24
Peak memory 206932 kb
Host smart-fcf878d0-b3f6-4322-88f1-a5a96a2a47fd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1996703267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.1996703267
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.239574633
Short name T656
Test name
Test status
Simulation time 13330380956 ps
CPU time 12.21 seconds
Started Jun 25 05:00:54 PM PDT 24
Finished Jun 25 05:01:08 PM PDT 24
Peak memory 206672 kb
Host smart-e989dba6-346b-4bbd-bf1d-bf0a90896fc3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=239574633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.239574633
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.4230068272
Short name T1102
Test name
Test status
Simulation time 23493066207 ps
CPU time 21.63 seconds
Started Jun 25 05:00:51 PM PDT 24
Finished Jun 25 05:01:14 PM PDT 24
Peak memory 206900 kb
Host smart-8692a3ea-79a7-4ca4-9dce-e512773ccdf8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4230068272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.4230068272
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.486996975
Short name T2261
Test name
Test status
Simulation time 190272193 ps
CPU time 0.81 seconds
Started Jun 25 05:00:50 PM PDT 24
Finished Jun 25 05:00:51 PM PDT 24
Peak memory 206572 kb
Host smart-39800b38-6fcd-4956-be15-91204cfe5af3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48699
6975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.486996975
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.4247664150
Short name T1518
Test name
Test status
Simulation time 143334064 ps
CPU time 0.78 seconds
Started Jun 25 05:00:52 PM PDT 24
Finished Jun 25 05:00:55 PM PDT 24
Peak memory 206572 kb
Host smart-bd20d76e-5c78-48f0-a33d-ec3bbc5566e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42476
64150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.4247664150
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.2273192384
Short name T1910
Test name
Test status
Simulation time 469384598 ps
CPU time 1.56 seconds
Started Jun 25 05:00:53 PM PDT 24
Finished Jun 25 05:00:56 PM PDT 24
Peak memory 206512 kb
Host smart-b63d4c1b-e98e-4bea-bcdd-24d1d732a48a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22731
92384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.2273192384
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.4243932014
Short name T34
Test name
Test status
Simulation time 561369834 ps
CPU time 1.51 seconds
Started Jun 25 05:00:56 PM PDT 24
Finished Jun 25 05:00:59 PM PDT 24
Peak memory 206756 kb
Host smart-d0ad8105-8eae-46f2-822f-baa78af82d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42439
32014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.4243932014
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.1478976808
Short name T1213
Test name
Test status
Simulation time 20058612675 ps
CPU time 37.73 seconds
Started Jun 25 05:00:53 PM PDT 24
Finished Jun 25 05:01:32 PM PDT 24
Peak memory 206848 kb
Host smart-c97f21c0-4bcf-43f6-83d0-1946854c98e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14789
76808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.1478976808
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.508935009
Short name T664
Test name
Test status
Simulation time 398590089 ps
CPU time 1.23 seconds
Started Jun 25 05:00:52 PM PDT 24
Finished Jun 25 05:00:54 PM PDT 24
Peak memory 206572 kb
Host smart-9a6834da-6535-424b-a020-8ea2a4d80952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50893
5009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.508935009
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.1973632174
Short name T805
Test name
Test status
Simulation time 173224910 ps
CPU time 0.8 seconds
Started Jun 25 05:00:57 PM PDT 24
Finished Jun 25 05:00:59 PM PDT 24
Peak memory 206404 kb
Host smart-87bf9d50-378f-448f-8515-e6ef7bbc9868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19736
32174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.1973632174
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.4285760645
Short name T872
Test name
Test status
Simulation time 32945841 ps
CPU time 0.68 seconds
Started Jun 25 05:00:53 PM PDT 24
Finished Jun 25 05:00:55 PM PDT 24
Peak memory 206500 kb
Host smart-969dc143-d062-4baf-9afa-ea5a2e2ffa21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42857
60645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.4285760645
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.3818465557
Short name T1559
Test name
Test status
Simulation time 1013683603 ps
CPU time 2.47 seconds
Started Jun 25 05:00:50 PM PDT 24
Finished Jun 25 05:00:54 PM PDT 24
Peak memory 206788 kb
Host smart-49e008e2-2c71-4a7d-922a-67b96b735b86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38184
65557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.3818465557
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.2993585428
Short name T552
Test name
Test status
Simulation time 165644477 ps
CPU time 1.48 seconds
Started Jun 25 05:00:53 PM PDT 24
Finished Jun 25 05:00:56 PM PDT 24
Peak memory 206628 kb
Host smart-d8704af9-e95f-4be1-b9fe-2b9e66e42d1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29935
85428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.2993585428
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.1643964047
Short name T445
Test name
Test status
Simulation time 224677347 ps
CPU time 0.93 seconds
Started Jun 25 05:00:53 PM PDT 24
Finished Jun 25 05:00:55 PM PDT 24
Peak memory 206496 kb
Host smart-ad6cb4a6-acee-4e15-94bb-a693713e5d07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16439
64047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.1643964047
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.4157239369
Short name T1895
Test name
Test status
Simulation time 154606259 ps
CPU time 0.75 seconds
Started Jun 25 05:00:53 PM PDT 24
Finished Jun 25 05:00:55 PM PDT 24
Peak memory 206568 kb
Host smart-35f8a967-e496-4228-bee7-25953af9b723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41572
39369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.4157239369
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.2174125582
Short name T309
Test name
Test status
Simulation time 214844243 ps
CPU time 0.87 seconds
Started Jun 25 05:00:53 PM PDT 24
Finished Jun 25 05:00:56 PM PDT 24
Peak memory 206568 kb
Host smart-e4da826c-208e-404e-8be6-ed52e83d6d7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21741
25582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.2174125582
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_invalid_sync.235373387
Short name T1078
Test name
Test status
Simulation time 6000523538 ps
CPU time 55.74 seconds
Started Jun 25 05:00:52 PM PDT 24
Finished Jun 25 05:01:49 PM PDT 24
Peak memory 206944 kb
Host smart-34da1cea-ef80-4f6e-a11b-ac6b6d096764
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=235373387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_invalid_sync.235373387
Directory /workspace/29.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.3291182605
Short name T1662
Test name
Test status
Simulation time 205961393 ps
CPU time 0.85 seconds
Started Jun 25 05:00:51 PM PDT 24
Finished Jun 25 05:00:53 PM PDT 24
Peak memory 206572 kb
Host smart-4f497c6f-3f3f-43f5-8c37-41f86fa58699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32911
82605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.3291182605
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.2581735524
Short name T608
Test name
Test status
Simulation time 23308917836 ps
CPU time 25.77 seconds
Started Jun 25 05:00:52 PM PDT 24
Finished Jun 25 05:01:18 PM PDT 24
Peak memory 206620 kb
Host smart-24ac189c-a669-443e-ab57-0482409fd011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25817
35524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.2581735524
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.183304214
Short name T1630
Test name
Test status
Simulation time 3278608599 ps
CPU time 3.79 seconds
Started Jun 25 05:00:56 PM PDT 24
Finished Jun 25 05:01:02 PM PDT 24
Peak memory 206620 kb
Host smart-d326719d-1900-4da5-a190-5346797b69d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18330
4214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.183304214
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.3491210450
Short name T1212
Test name
Test status
Simulation time 5331823540 ps
CPU time 52.03 seconds
Started Jun 25 05:00:52 PM PDT 24
Finished Jun 25 05:01:46 PM PDT 24
Peak memory 206896 kb
Host smart-caebe7a1-b598-4299-8a28-704eb7b1c729
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3491210450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.3491210450
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.1479098897
Short name T2467
Test name
Test status
Simulation time 247669105 ps
CPU time 0.97 seconds
Started Jun 25 05:00:54 PM PDT 24
Finished Jun 25 05:00:57 PM PDT 24
Peak memory 206520 kb
Host smart-4bfd32af-c7cd-4f4f-a984-3da116bf8c0b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1479098897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.1479098897
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.2360697532
Short name T1142
Test name
Test status
Simulation time 220475748 ps
CPU time 0.92 seconds
Started Jun 25 05:00:53 PM PDT 24
Finished Jun 25 05:00:56 PM PDT 24
Peak memory 206576 kb
Host smart-155213aa-98d8-43b3-a05a-b1a3ccdebfec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23606
97532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.2360697532
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.1279442510
Short name T1115
Test name
Test status
Simulation time 12833265373 ps
CPU time 125.21 seconds
Started Jun 25 05:00:53 PM PDT 24
Finished Jun 25 05:03:00 PM PDT 24
Peak memory 206800 kb
Host smart-f6b03d20-dc36-433e-8d49-30650be4091b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12794
42510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.1279442510
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.671390801
Short name T810
Test name
Test status
Simulation time 3597088986 ps
CPU time 99.04 seconds
Started Jun 25 05:00:51 PM PDT 24
Finished Jun 25 05:02:31 PM PDT 24
Peak memory 206956 kb
Host smart-54e2cb50-ffa6-44e9-90c9-b242e3f3698b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=671390801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.671390801
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.2502746335
Short name T2023
Test name
Test status
Simulation time 159767804 ps
CPU time 0.82 seconds
Started Jun 25 05:00:55 PM PDT 24
Finished Jun 25 05:00:57 PM PDT 24
Peak memory 206576 kb
Host smart-a0f0a9f1-7eb4-4df1-bb0a-43119fb1c94b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2502746335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.2502746335
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.3788674589
Short name T474
Test name
Test status
Simulation time 145351302 ps
CPU time 0.76 seconds
Started Jun 25 05:00:52 PM PDT 24
Finished Jun 25 05:00:54 PM PDT 24
Peak memory 206568 kb
Host smart-81a3f9b7-eddc-42cd-9526-11610bc4f54a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37886
74589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.3788674589
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.1686831009
Short name T1541
Test name
Test status
Simulation time 173643472 ps
CPU time 0.82 seconds
Started Jun 25 05:00:51 PM PDT 24
Finished Jun 25 05:00:53 PM PDT 24
Peak memory 206544 kb
Host smart-9eb1bc31-2314-4cab-9589-05aeaebffed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16868
31009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.1686831009
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.1386137038
Short name T2484
Test name
Test status
Simulation time 181006709 ps
CPU time 0.85 seconds
Started Jun 25 05:00:54 PM PDT 24
Finished Jun 25 05:00:57 PM PDT 24
Peak memory 206596 kb
Host smart-623874d2-7e6d-464b-8553-8d8e89d993c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13861
37038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.1386137038
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.1657367051
Short name T1088
Test name
Test status
Simulation time 235940578 ps
CPU time 0.91 seconds
Started Jun 25 05:00:56 PM PDT 24
Finished Jun 25 05:00:58 PM PDT 24
Peak memory 206752 kb
Host smart-3f5bfa1b-86ec-4e61-b7cd-3289e934970b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16573
67051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.1657367051
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.1413620900
Short name T970
Test name
Test status
Simulation time 150803863 ps
CPU time 0.78 seconds
Started Jun 25 05:00:54 PM PDT 24
Finished Jun 25 05:00:57 PM PDT 24
Peak memory 206508 kb
Host smart-225cde95-c946-4c9e-b1f2-73ef7b8756cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14136
20900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.1413620900
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.2964178768
Short name T1522
Test name
Test status
Simulation time 160541690 ps
CPU time 0.78 seconds
Started Jun 25 05:00:53 PM PDT 24
Finished Jun 25 05:00:56 PM PDT 24
Peak memory 206572 kb
Host smart-b0f5f5f1-fccc-43cf-bfac-717a08650fd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29641
78768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.2964178768
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.4077598049
Short name T2123
Test name
Test status
Simulation time 231087834 ps
CPU time 0.95 seconds
Started Jun 25 05:00:54 PM PDT 24
Finished Jun 25 05:00:56 PM PDT 24
Peak memory 206560 kb
Host smart-74b12fec-f68c-4bdb-919e-5f1409f3caf8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4077598049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.4077598049
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.2337117005
Short name T1281
Test name
Test status
Simulation time 186466632 ps
CPU time 0.83 seconds
Started Jun 25 05:00:57 PM PDT 24
Finished Jun 25 05:00:59 PM PDT 24
Peak memory 206448 kb
Host smart-ee8c360d-b60d-47a1-a564-2a768b7a73d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23371
17005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.2337117005
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.3608119298
Short name T38
Test name
Test status
Simulation time 40806587 ps
CPU time 0.7 seconds
Started Jun 25 05:00:56 PM PDT 24
Finished Jun 25 05:00:58 PM PDT 24
Peak memory 206572 kb
Host smart-445c9af9-c9f8-4948-b9cd-5cc76913a1e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36081
19298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.3608119298
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.2688376851
Short name T2053
Test name
Test status
Simulation time 15388578880 ps
CPU time 36.35 seconds
Started Jun 25 05:00:51 PM PDT 24
Finished Jun 25 05:01:28 PM PDT 24
Peak memory 206896 kb
Host smart-efca00c5-1095-4f89-bc79-8a1673c73038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26883
76851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.2688376851
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.1809954093
Short name T2410
Test name
Test status
Simulation time 213843263 ps
CPU time 0.83 seconds
Started Jun 25 05:00:50 PM PDT 24
Finished Jun 25 05:00:52 PM PDT 24
Peak memory 206592 kb
Host smart-842c1516-6ce7-4159-b03c-7a6ad955640d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18099
54093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.1809954093
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.3846267020
Short name T2394
Test name
Test status
Simulation time 229605893 ps
CPU time 0.92 seconds
Started Jun 25 05:00:52 PM PDT 24
Finished Jun 25 05:00:54 PM PDT 24
Peak memory 206488 kb
Host smart-07412c43-b059-4ee6-9019-040e2620405b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38462
67020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.3846267020
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.2523944901
Short name T2320
Test name
Test status
Simulation time 217230529 ps
CPU time 0.93 seconds
Started Jun 25 05:00:57 PM PDT 24
Finished Jun 25 05:00:59 PM PDT 24
Peak memory 206520 kb
Host smart-a3d1705a-81c4-4b75-8d90-9b10fa1b6b1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25239
44901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.2523944901
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.1927463103
Short name T1274
Test name
Test status
Simulation time 192062433 ps
CPU time 0.86 seconds
Started Jun 25 05:00:54 PM PDT 24
Finished Jun 25 05:00:57 PM PDT 24
Peak memory 206500 kb
Host smart-0d0e1213-22f5-43c7-bad6-9d0af58b7bc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19274
63103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.1927463103
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.2959682083
Short name T2404
Test name
Test status
Simulation time 143710302 ps
CPU time 0.77 seconds
Started Jun 25 05:00:53 PM PDT 24
Finished Jun 25 05:00:55 PM PDT 24
Peak memory 206500 kb
Host smart-86008867-4794-4bec-a038-8afb96b858a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29596
82083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.2959682083
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.1950419048
Short name T1144
Test name
Test status
Simulation time 160662912 ps
CPU time 0.77 seconds
Started Jun 25 05:00:51 PM PDT 24
Finished Jun 25 05:00:53 PM PDT 24
Peak memory 206572 kb
Host smart-371a53de-c786-4126-9b57-1b396399831f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19504
19048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.1950419048
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.2604893545
Short name T2144
Test name
Test status
Simulation time 161829272 ps
CPU time 0.8 seconds
Started Jun 25 05:00:54 PM PDT 24
Finished Jun 25 05:00:57 PM PDT 24
Peak memory 206516 kb
Host smart-3962b698-f6e8-44e2-b321-84f6f5f23b3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26048
93545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.2604893545
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.350265436
Short name T839
Test name
Test status
Simulation time 210342381 ps
CPU time 0.91 seconds
Started Jun 25 05:00:57 PM PDT 24
Finished Jun 25 05:00:59 PM PDT 24
Peak memory 206436 kb
Host smart-2930def4-6bb5-4dff-9d83-970f5f3942ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35026
5436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.350265436
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.2976264787
Short name T2363
Test name
Test status
Simulation time 10320217908 ps
CPU time 99.75 seconds
Started Jun 25 05:00:54 PM PDT 24
Finished Jun 25 05:02:35 PM PDT 24
Peak memory 206812 kb
Host smart-60bbe404-cdb2-4a82-9321-c53bfe541ded
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2976264787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.2976264787
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.1310584241
Short name T1802
Test name
Test status
Simulation time 178882256 ps
CPU time 0.84 seconds
Started Jun 25 05:00:51 PM PDT 24
Finished Jun 25 05:00:53 PM PDT 24
Peak memory 206596 kb
Host smart-deb445d2-806d-483c-8632-7a8fb8911789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13105
84241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.1310584241
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.385044798
Short name T375
Test name
Test status
Simulation time 169140010 ps
CPU time 0.81 seconds
Started Jun 25 05:00:58 PM PDT 24
Finished Jun 25 05:01:00 PM PDT 24
Peak memory 206500 kb
Host smart-439c0f21-c1a9-4b7b-ad35-f1ed01251394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38504
4798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.385044798
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.1660762797
Short name T788
Test name
Test status
Simulation time 8347993599 ps
CPU time 59.66 seconds
Started Jun 25 05:00:54 PM PDT 24
Finished Jun 25 05:01:55 PM PDT 24
Peak memory 206776 kb
Host smart-8c4d9eff-1d9b-49da-a0af-d95196ee1660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16607
62797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.1660762797
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.500476919
Short name T560
Test name
Test status
Simulation time 3775611319 ps
CPU time 4.32 seconds
Started Jun 25 04:56:39 PM PDT 24
Finished Jun 25 04:56:46 PM PDT 24
Peak memory 206816 kb
Host smart-e617baf8-5e87-4db1-8bca-861f7d9ef2ed
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=500476919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.500476919
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.2126647604
Short name T197
Test name
Test status
Simulation time 13349179771 ps
CPU time 13.76 seconds
Started Jun 25 04:56:35 PM PDT 24
Finished Jun 25 04:56:50 PM PDT 24
Peak memory 206644 kb
Host smart-f381556f-4284-4193-b1dc-7aee81c05617
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2126647604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.2126647604
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.419897675
Short name T604
Test name
Test status
Simulation time 23351071046 ps
CPU time 26.76 seconds
Started Jun 25 04:56:38 PM PDT 24
Finished Jun 25 04:57:06 PM PDT 24
Peak memory 206712 kb
Host smart-b143a658-beb9-4259-9005-6ca5ad59d887
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=419897675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.419897675
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.3090149452
Short name T318
Test name
Test status
Simulation time 164642372 ps
CPU time 0.8 seconds
Started Jun 25 04:56:37 PM PDT 24
Finished Jun 25 04:56:40 PM PDT 24
Peak memory 206748 kb
Host smart-cfa631de-5202-4763-b5fd-ac83a88a9e99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30901
49452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.3090149452
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.1182942145
Short name T60
Test name
Test status
Simulation time 146528385 ps
CPU time 0.8 seconds
Started Jun 25 04:56:34 PM PDT 24
Finished Jun 25 04:56:35 PM PDT 24
Peak memory 206572 kb
Host smart-52a256e0-d47c-41dc-8197-91bf281b4131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11829
42145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.1182942145
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.1591351216
Short name T89
Test name
Test status
Simulation time 164057961 ps
CPU time 0.83 seconds
Started Jun 25 04:56:39 PM PDT 24
Finished Jun 25 04:56:42 PM PDT 24
Peak memory 206572 kb
Host smart-f0c8b69b-d2d4-42c2-bd05-3670f3c7eeb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15913
51216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.1591351216
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.690791393
Short name T378
Test name
Test status
Simulation time 150704099 ps
CPU time 0.74 seconds
Started Jun 25 04:56:35 PM PDT 24
Finished Jun 25 04:56:37 PM PDT 24
Peak memory 206500 kb
Host smart-772687a9-ab16-42c9-99bb-dbecb6dc7544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69079
1393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.690791393
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.3125081044
Short name T1550
Test name
Test status
Simulation time 338351041 ps
CPU time 1.18 seconds
Started Jun 25 04:56:40 PM PDT 24
Finished Jun 25 04:56:43 PM PDT 24
Peak memory 206512 kb
Host smart-17594e5b-9aa6-4216-93ce-d80eb6b0f3ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31250
81044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.3125081044
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.3786188799
Short name T662
Test name
Test status
Simulation time 939550269 ps
CPU time 2.47 seconds
Started Jun 25 04:56:39 PM PDT 24
Finished Jun 25 04:56:43 PM PDT 24
Peak memory 206628 kb
Host smart-70688959-430e-42ee-84f1-26b9627f1fae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37861
88799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.3786188799
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.1496193825
Short name T180
Test name
Test status
Simulation time 9025544200 ps
CPU time 16.44 seconds
Started Jun 25 04:56:35 PM PDT 24
Finished Jun 25 04:56:53 PM PDT 24
Peak memory 206860 kb
Host smart-dc7f4e34-9285-4eec-a701-340f692632be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14961
93825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.1496193825
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.4194415618
Short name T838
Test name
Test status
Simulation time 418532461 ps
CPU time 1.3 seconds
Started Jun 25 04:56:36 PM PDT 24
Finished Jun 25 04:56:39 PM PDT 24
Peak memory 206572 kb
Host smart-b0d1a1d5-ae64-493a-81e8-3c6dc10cf541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41944
15618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.4194415618
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.2792231453
Short name T1754
Test name
Test status
Simulation time 151857938 ps
CPU time 0.76 seconds
Started Jun 25 04:56:37 PM PDT 24
Finished Jun 25 04:56:40 PM PDT 24
Peak memory 206572 kb
Host smart-22b65cf6-1ab9-40bb-85c6-0052d7ca5a01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27922
31453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.2792231453
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.2736634943
Short name T1108
Test name
Test status
Simulation time 44049590 ps
CPU time 0.68 seconds
Started Jun 25 04:56:39 PM PDT 24
Finished Jun 25 04:56:41 PM PDT 24
Peak memory 206508 kb
Host smart-45821427-cb11-436b-ba3b-8fed04085948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27366
34943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.2736634943
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.793585554
Short name T587
Test name
Test status
Simulation time 817549630 ps
CPU time 1.97 seconds
Started Jun 25 04:56:37 PM PDT 24
Finished Jun 25 04:56:41 PM PDT 24
Peak memory 206796 kb
Host smart-62c69aa8-2ebc-4328-8a42-a7e42a667161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79358
5554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.793585554
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.3551579025
Short name T1027
Test name
Test status
Simulation time 155966175 ps
CPU time 1.51 seconds
Started Jun 25 04:56:34 PM PDT 24
Finished Jun 25 04:56:37 PM PDT 24
Peak memory 206812 kb
Host smart-22cb92cc-c2e0-437d-bb0f-0d9f7a0283e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35515
79025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.3551579025
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.3072406938
Short name T652
Test name
Test status
Simulation time 209659900 ps
CPU time 0.94 seconds
Started Jun 25 04:56:46 PM PDT 24
Finished Jun 25 04:56:49 PM PDT 24
Peak memory 206608 kb
Host smart-def8e97b-f9e8-4f43-898c-ec3f6d31f787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30724
06938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.3072406938
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.4074369679
Short name T2332
Test name
Test status
Simulation time 161635748 ps
CPU time 0.76 seconds
Started Jun 25 04:56:50 PM PDT 24
Finished Jun 25 04:56:52 PM PDT 24
Peak memory 206504 kb
Host smart-aa1ff966-04c8-4ca6-a52e-80ebf1cb2d43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40743
69679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.4074369679
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.1139468423
Short name T2002
Test name
Test status
Simulation time 235532109 ps
CPU time 0.91 seconds
Started Jun 25 04:56:37 PM PDT 24
Finished Jun 25 04:56:40 PM PDT 24
Peak memory 206572 kb
Host smart-dd384d37-dd3b-48d9-ab00-f12d614cba2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11394
68423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.1139468423
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.2450698285
Short name T741
Test name
Test status
Simulation time 210166238 ps
CPU time 0.89 seconds
Started Jun 25 04:56:36 PM PDT 24
Finished Jun 25 04:56:38 PM PDT 24
Peak memory 206580 kb
Host smart-91143197-8041-4da8-8cad-6dd5b8720ad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24506
98285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.2450698285
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.432782705
Short name T2393
Test name
Test status
Simulation time 23342743916 ps
CPU time 20.74 seconds
Started Jun 25 04:56:39 PM PDT 24
Finished Jun 25 04:57:01 PM PDT 24
Peak memory 206700 kb
Host smart-58080530-3e04-43a5-9855-d01aec560986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43278
2705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.432782705
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.2931065350
Short name T1185
Test name
Test status
Simulation time 3278419186 ps
CPU time 3.88 seconds
Started Jun 25 04:56:40 PM PDT 24
Finished Jun 25 04:56:45 PM PDT 24
Peak memory 206616 kb
Host smart-cbee24ae-522e-4f0c-b5b2-9815e4225d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29310
65350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.2931065350
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.4097251824
Short name T864
Test name
Test status
Simulation time 4900576659 ps
CPU time 137.63 seconds
Started Jun 25 04:56:40 PM PDT 24
Finished Jun 25 04:58:59 PM PDT 24
Peak memory 206892 kb
Host smart-2ee432f7-8fb6-4862-9f2e-19b96d10e9c3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4097251824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.4097251824
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.3496006144
Short name T2283
Test name
Test status
Simulation time 254411760 ps
CPU time 0.91 seconds
Started Jun 25 04:56:45 PM PDT 24
Finished Jun 25 04:56:47 PM PDT 24
Peak memory 206516 kb
Host smart-b28d286c-d987-40a2-b3f1-e4c126783ba2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3496006144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.3496006144
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.4179911499
Short name T1303
Test name
Test status
Simulation time 196664794 ps
CPU time 0.89 seconds
Started Jun 25 04:56:37 PM PDT 24
Finished Jun 25 04:56:40 PM PDT 24
Peak memory 206576 kb
Host smart-f005cf57-f01f-4a9b-906e-d9555e0b1a07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41799
11499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.4179911499
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.3141641941
Short name T938
Test name
Test status
Simulation time 11152747138 ps
CPU time 81.8 seconds
Started Jun 25 04:56:40 PM PDT 24
Finished Jun 25 04:58:04 PM PDT 24
Peak memory 206812 kb
Host smart-6844f114-1918-4524-9a4b-166a35b99d72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31416
41941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.3141641941
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.405682815
Short name T1993
Test name
Test status
Simulation time 13636949053 ps
CPU time 100.85 seconds
Started Jun 25 04:56:36 PM PDT 24
Finished Jun 25 04:58:18 PM PDT 24
Peak memory 206956 kb
Host smart-3aa60f30-a11e-4be8-ac55-5d069b83551e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=405682815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.405682815
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.3987281769
Short name T847
Test name
Test status
Simulation time 172373136 ps
CPU time 0.85 seconds
Started Jun 25 04:56:46 PM PDT 24
Finished Jun 25 04:56:48 PM PDT 24
Peak memory 206516 kb
Host smart-893ed91d-6a37-40cf-b4a4-91e90cea11eb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3987281769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.3987281769
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.1833786988
Short name T1937
Test name
Test status
Simulation time 144609993 ps
CPU time 0.76 seconds
Started Jun 25 04:56:34 PM PDT 24
Finished Jun 25 04:56:36 PM PDT 24
Peak memory 206592 kb
Host smart-1318c84c-db55-438a-b969-9e9db2633c5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18337
86988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.1833786988
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.4248987277
Short name T1657
Test name
Test status
Simulation time 220349534 ps
CPU time 0.95 seconds
Started Jun 25 04:56:37 PM PDT 24
Finished Jun 25 04:56:40 PM PDT 24
Peak memory 206564 kb
Host smart-0ff9253a-a493-47c1-8976-de1ed3c60536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42489
87277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.4248987277
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.3241580450
Short name T1478
Test name
Test status
Simulation time 206430597 ps
CPU time 0.84 seconds
Started Jun 25 04:56:36 PM PDT 24
Finished Jun 25 04:56:38 PM PDT 24
Peak memory 206508 kb
Host smart-761f5e82-6841-45e5-9a61-807ec7e2ca17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32415
80450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.3241580450
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.3682811232
Short name T981
Test name
Test status
Simulation time 165966624 ps
CPU time 0.8 seconds
Started Jun 25 04:56:37 PM PDT 24
Finished Jun 25 04:56:39 PM PDT 24
Peak memory 206488 kb
Host smart-29192387-1fcd-4c1d-b67c-1a1eb233cf8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36828
11232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.3682811232
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.1174862444
Short name T1458
Test name
Test status
Simulation time 161907725 ps
CPU time 0.8 seconds
Started Jun 25 04:56:35 PM PDT 24
Finished Jun 25 04:56:37 PM PDT 24
Peak memory 206496 kb
Host smart-33341897-ff86-4751-aced-ccca4dc9e9eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11748
62444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.1174862444
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.2575488638
Short name T657
Test name
Test status
Simulation time 152110866 ps
CPU time 0.81 seconds
Started Jun 25 04:56:47 PM PDT 24
Finished Jun 25 04:56:50 PM PDT 24
Peak memory 206516 kb
Host smart-439ac4e2-d9bf-4e4b-a984-f5044c938a00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25754
88638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.2575488638
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.155579280
Short name T2167
Test name
Test status
Simulation time 284577660 ps
CPU time 0.99 seconds
Started Jun 25 04:56:37 PM PDT 24
Finished Jun 25 04:56:40 PM PDT 24
Peak memory 206572 kb
Host smart-059048b4-b1ce-4cec-88de-d72a4b7c8181
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=155579280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.155579280
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.3935370157
Short name T2406
Test name
Test status
Simulation time 212113429 ps
CPU time 0.93 seconds
Started Jun 25 04:56:39 PM PDT 24
Finished Jun 25 04:56:42 PM PDT 24
Peak memory 206584 kb
Host smart-2780745b-3fa5-4dfa-9f93-69a1238fe026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39353
70157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.3935370157
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.3713796156
Short name T1590
Test name
Test status
Simulation time 171163082 ps
CPU time 0.82 seconds
Started Jun 25 04:56:40 PM PDT 24
Finished Jun 25 04:56:42 PM PDT 24
Peak memory 206460 kb
Host smart-88d96774-7d69-4c18-8669-df6b3eb429b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37137
96156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.3713796156
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.373766666
Short name T430
Test name
Test status
Simulation time 39000387 ps
CPU time 0.66 seconds
Started Jun 25 04:56:45 PM PDT 24
Finished Jun 25 04:56:47 PM PDT 24
Peak memory 206512 kb
Host smart-0d8ec70e-7632-45d1-b1b3-5b87ea11560f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37376
6666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.373766666
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.3013455331
Short name T168
Test name
Test status
Simulation time 20794938909 ps
CPU time 43.2 seconds
Started Jun 25 04:56:36 PM PDT 24
Finished Jun 25 04:57:22 PM PDT 24
Peak memory 215116 kb
Host smart-253be092-ccfb-4a77-a668-bbe46df62f14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30134
55331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.3013455331
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.486053095
Short name T1456
Test name
Test status
Simulation time 164278236 ps
CPU time 0.84 seconds
Started Jun 25 04:56:35 PM PDT 24
Finished Jun 25 04:56:37 PM PDT 24
Peak memory 206548 kb
Host smart-3da88b12-cd51-4d5d-83f9-cad44f2fc18c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48605
3095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.486053095
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.821128622
Short name T452
Test name
Test status
Simulation time 174329854 ps
CPU time 0.88 seconds
Started Jun 25 04:56:41 PM PDT 24
Finished Jun 25 04:56:43 PM PDT 24
Peak memory 206452 kb
Host smart-42d710b3-5242-4703-9d92-1b84e87a41bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82112
8622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.821128622
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.3473396999
Short name T1664
Test name
Test status
Simulation time 21134168866 ps
CPU time 157.29 seconds
Started Jun 25 04:56:36 PM PDT 24
Finished Jun 25 04:59:15 PM PDT 24
Peak memory 206892 kb
Host smart-48279f42-5b57-4d22-b5d2-e3dae6e8a9e9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3473396999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.3473396999
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.2076170324
Short name T2273
Test name
Test status
Simulation time 14820061797 ps
CPU time 109.77 seconds
Started Jun 25 04:56:36 PM PDT 24
Finished Jun 25 04:58:27 PM PDT 24
Peak memory 206848 kb
Host smart-accb1e65-fdf2-4aac-b32a-68bd48b9188b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2076170324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.2076170324
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.2105742323
Short name T2439
Test name
Test status
Simulation time 29784896686 ps
CPU time 700.35 seconds
Started Jun 25 04:56:37 PM PDT 24
Finished Jun 25 05:08:19 PM PDT 24
Peak memory 207008 kb
Host smart-802a619f-eefc-4e33-9583-da657f3f0487
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2105742323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.2105742323
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.3297241733
Short name T2218
Test name
Test status
Simulation time 227699499 ps
CPU time 0.97 seconds
Started Jun 25 04:56:49 PM PDT 24
Finished Jun 25 04:56:52 PM PDT 24
Peak memory 206600 kb
Host smart-bd76228a-8914-446a-8ed1-d1d150ffee61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32972
41733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.3297241733
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.1422324327
Short name T1486
Test name
Test status
Simulation time 200737728 ps
CPU time 0.84 seconds
Started Jun 25 04:56:38 PM PDT 24
Finished Jun 25 04:56:41 PM PDT 24
Peak memory 206572 kb
Host smart-fcdb062f-27cc-4e93-86a5-101c23d13353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14223
24327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.1422324327
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.3987581634
Short name T889
Test name
Test status
Simulation time 194646587 ps
CPU time 0.81 seconds
Started Jun 25 04:56:37 PM PDT 24
Finished Jun 25 04:56:40 PM PDT 24
Peak memory 206488 kb
Host smart-fa1a5c8d-f8c2-434e-a96e-09d47b443e35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39875
81634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.3987581634
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.4089282390
Short name T2044
Test name
Test status
Simulation time 162521568 ps
CPU time 0.8 seconds
Started Jun 25 04:56:39 PM PDT 24
Finished Jun 25 04:56:42 PM PDT 24
Peak memory 206500 kb
Host smart-85979085-ba21-4422-8eb9-82996d72c4d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40892
82390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.4089282390
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.4163376580
Short name T193
Test name
Test status
Simulation time 1508944559 ps
CPU time 2.34 seconds
Started Jun 25 04:56:45 PM PDT 24
Finished Jun 25 04:56:49 PM PDT 24
Peak memory 224312 kb
Host smart-e27b58f7-63c7-4673-82f1-c4584b0153de
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4163376580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.4163376580
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.3202103834
Short name T2154
Test name
Test status
Simulation time 406247672 ps
CPU time 1.22 seconds
Started Jun 25 04:56:39 PM PDT 24
Finished Jun 25 04:56:42 PM PDT 24
Peak memory 206516 kb
Host smart-07b0a1b7-3472-4acb-8df7-70a949d0024c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32021
03834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.3202103834
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.1530865381
Short name T955
Test name
Test status
Simulation time 193962882 ps
CPU time 0.83 seconds
Started Jun 25 04:56:45 PM PDT 24
Finished Jun 25 04:56:47 PM PDT 24
Peak memory 206556 kb
Host smart-4cefa0f6-f14f-4842-a54d-08402f323153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15308
65381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.1530865381
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.129167113
Short name T1881
Test name
Test status
Simulation time 151100731 ps
CPU time 0.79 seconds
Started Jun 25 04:56:44 PM PDT 24
Finished Jun 25 04:56:45 PM PDT 24
Peak memory 206540 kb
Host smart-eea5a9b3-910b-4edd-bce6-3735fcff5fb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12916
7113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.129167113
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.1637363350
Short name T2209
Test name
Test status
Simulation time 210786249 ps
CPU time 0.95 seconds
Started Jun 25 04:56:36 PM PDT 24
Finished Jun 25 04:56:39 PM PDT 24
Peak memory 206512 kb
Host smart-f9f0c48e-25c0-4946-8a08-73dd22458529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16373
63350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.1637363350
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.1795045813
Short name T2071
Test name
Test status
Simulation time 9322074257 ps
CPU time 86.62 seconds
Started Jun 25 04:56:45 PM PDT 24
Finished Jun 25 04:58:13 PM PDT 24
Peak memory 206852 kb
Host smart-2dddae9d-55d2-496e-9fb1-ac6fbf2e8854
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1795045813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.1795045813
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.652761441
Short name T1267
Test name
Test status
Simulation time 174496089 ps
CPU time 0.9 seconds
Started Jun 25 04:56:48 PM PDT 24
Finished Jun 25 04:56:50 PM PDT 24
Peak memory 206528 kb
Host smart-f53482c7-5f7d-4067-8e90-520bb28e98ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65276
1441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.652761441
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.2467990531
Short name T417
Test name
Test status
Simulation time 146540689 ps
CPU time 0.77 seconds
Started Jun 25 04:56:48 PM PDT 24
Finished Jun 25 04:56:50 PM PDT 24
Peak memory 206556 kb
Host smart-3b2f3105-fb0b-4f8c-a831-60e36010dac2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24679
90531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.2467990531
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.2847388616
Short name T1445
Test name
Test status
Simulation time 8243616015 ps
CPU time 226.9 seconds
Started Jun 25 04:56:44 PM PDT 24
Finished Jun 25 05:00:32 PM PDT 24
Peak memory 206944 kb
Host smart-efc70f15-51d1-4b23-938a-ec4d261ce404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28473
88616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.2847388616
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.2487075422
Short name T2082
Test name
Test status
Simulation time 4433951653 ps
CPU time 5.06 seconds
Started Jun 25 05:01:02 PM PDT 24
Finished Jun 25 05:01:09 PM PDT 24
Peak memory 206796 kb
Host smart-552f0f0b-c1a1-462d-a4c1-f49e64e5c1a9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2487075422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.2487075422
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.1369119891
Short name T665
Test name
Test status
Simulation time 13423783382 ps
CPU time 12.21 seconds
Started Jun 25 05:01:00 PM PDT 24
Finished Jun 25 05:01:14 PM PDT 24
Peak memory 206712 kb
Host smart-037f1e42-e986-4599-bfb5-ce40dc4b11e3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1369119891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.1369119891
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.584132768
Short name T1816
Test name
Test status
Simulation time 23505464795 ps
CPU time 28.38 seconds
Started Jun 25 05:01:00 PM PDT 24
Finished Jun 25 05:01:29 PM PDT 24
Peak memory 206896 kb
Host smart-b768ddf8-955d-4197-8359-83affa21f382
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=584132768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.584132768
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.521017635
Short name T2496
Test name
Test status
Simulation time 198305691 ps
CPU time 0.86 seconds
Started Jun 25 05:01:02 PM PDT 24
Finished Jun 25 05:01:04 PM PDT 24
Peak memory 206516 kb
Host smart-390ae93a-050e-4c08-a42a-247b29fe7169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52101
7635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.521017635
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.3838961447
Short name T62
Test name
Test status
Simulation time 203141707 ps
CPU time 0.85 seconds
Started Jun 25 05:01:02 PM PDT 24
Finished Jun 25 05:01:05 PM PDT 24
Peak memory 206500 kb
Host smart-8cb777a0-5244-46e7-9840-0a33372c6b75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38389
61447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.3838961447
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.2240908978
Short name T174
Test name
Test status
Simulation time 556935156 ps
CPU time 1.74 seconds
Started Jun 25 05:01:02 PM PDT 24
Finished Jun 25 05:01:05 PM PDT 24
Peak memory 206740 kb
Host smart-7e3298c5-e8d0-4951-8bd4-3b6931d1b6a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22409
08978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.2240908978
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.1708573902
Short name T1919
Test name
Test status
Simulation time 1467967281 ps
CPU time 3.22 seconds
Started Jun 25 05:01:02 PM PDT 24
Finished Jun 25 05:01:06 PM PDT 24
Peak memory 206736 kb
Host smart-bb23b116-b1b2-445e-8150-64b310b59d0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17085
73902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.1708573902
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.1951383204
Short name T1128
Test name
Test status
Simulation time 22944034169 ps
CPU time 41.82 seconds
Started Jun 25 05:01:00 PM PDT 24
Finished Jun 25 05:01:42 PM PDT 24
Peak memory 206788 kb
Host smart-a66f43e2-d363-4d49-a0a3-a1ffee95162d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19513
83204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.1951383204
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.2635796101
Short name T1930
Test name
Test status
Simulation time 431473922 ps
CPU time 1.3 seconds
Started Jun 25 05:01:06 PM PDT 24
Finished Jun 25 05:01:09 PM PDT 24
Peak memory 206456 kb
Host smart-e89a3995-1d8f-49b0-99cb-211ae1d5a0bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26357
96101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.2635796101
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.3534237785
Short name T1330
Test name
Test status
Simulation time 156277312 ps
CPU time 0.85 seconds
Started Jun 25 05:01:06 PM PDT 24
Finished Jun 25 05:01:08 PM PDT 24
Peak memory 206576 kb
Host smart-9b417307-1f9d-4352-8629-2604f5ffffd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35342
37785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.3534237785
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.2814537033
Short name T783
Test name
Test status
Simulation time 48768838 ps
CPU time 0.67 seconds
Started Jun 25 05:01:02 PM PDT 24
Finished Jun 25 05:01:04 PM PDT 24
Peak memory 206492 kb
Host smart-66c31575-d8c0-4915-9a0f-0867ab05ab04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28145
37033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.2814537033
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.3381301807
Short name T1617
Test name
Test status
Simulation time 862556184 ps
CPU time 2.18 seconds
Started Jun 25 05:01:00 PM PDT 24
Finished Jun 25 05:01:04 PM PDT 24
Peak memory 206752 kb
Host smart-13380324-25d7-4e43-80d9-d5b120c552b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33813
01807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.3381301807
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.1890058791
Short name T1517
Test name
Test status
Simulation time 188361683 ps
CPU time 1.98 seconds
Started Jun 25 05:01:03 PM PDT 24
Finished Jun 25 05:01:07 PM PDT 24
Peak memory 206736 kb
Host smart-00130199-fa16-445f-8f1d-2ce80ae6074f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18900
58791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.1890058791
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.507472145
Short name T1325
Test name
Test status
Simulation time 198674476 ps
CPU time 0.88 seconds
Started Jun 25 05:01:01 PM PDT 24
Finished Jun 25 05:01:04 PM PDT 24
Peak memory 206592 kb
Host smart-992aaa48-b6fd-4daf-9189-1d85a03939cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50747
2145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.507472145
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.1120557998
Short name T2232
Test name
Test status
Simulation time 189902602 ps
CPU time 0.87 seconds
Started Jun 25 05:01:11 PM PDT 24
Finished Jun 25 05:01:14 PM PDT 24
Peak memory 206600 kb
Host smart-fcd527d6-2e09-4cd2-8393-fb600b0f03bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11205
57998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.1120557998
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.2184369919
Short name T429
Test name
Test status
Simulation time 212799810 ps
CPU time 0.9 seconds
Started Jun 25 05:01:03 PM PDT 24
Finished Jun 25 05:01:05 PM PDT 24
Peak memory 206484 kb
Host smart-a4f98049-ff5c-4a31-8480-b5daa29ba4e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21843
69919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.2184369919
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.1817974575
Short name T1622
Test name
Test status
Simulation time 216850124 ps
CPU time 1.03 seconds
Started Jun 25 05:01:05 PM PDT 24
Finished Jun 25 05:01:08 PM PDT 24
Peak memory 206592 kb
Host smart-d564d1ed-c9a1-4e76-9937-becbb2ebc841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18179
74575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.1817974575
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.768110636
Short name T771
Test name
Test status
Simulation time 23332654515 ps
CPU time 23.78 seconds
Started Jun 25 05:01:02 PM PDT 24
Finished Jun 25 05:01:28 PM PDT 24
Peak memory 206628 kb
Host smart-f2f7f21b-9303-4da7-8993-2636395e1a9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76811
0636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.768110636
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.1789858057
Short name T2330
Test name
Test status
Simulation time 3321221029 ps
CPU time 3.72 seconds
Started Jun 25 05:01:01 PM PDT 24
Finished Jun 25 05:01:06 PM PDT 24
Peak memory 206716 kb
Host smart-e91ea27d-3e0b-4320-b244-b4f5f8f2aad6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17898
58057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.1789858057
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.4117294362
Short name T2238
Test name
Test status
Simulation time 11231308371 ps
CPU time 83.08 seconds
Started Jun 25 05:01:03 PM PDT 24
Finished Jun 25 05:02:28 PM PDT 24
Peak memory 206800 kb
Host smart-4bd41e99-8e28-4cbf-bfee-2702e5124c7a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4117294362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.4117294362
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.2423141020
Short name T1532
Test name
Test status
Simulation time 294866946 ps
CPU time 0.99 seconds
Started Jun 25 05:01:11 PM PDT 24
Finished Jun 25 05:01:14 PM PDT 24
Peak memory 206604 kb
Host smart-40b2de21-2a53-4f59-911a-6256b0367c4c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2423141020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.2423141020
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.2554073981
Short name T1975
Test name
Test status
Simulation time 196557878 ps
CPU time 0.97 seconds
Started Jun 25 05:01:06 PM PDT 24
Finished Jun 25 05:01:09 PM PDT 24
Peak memory 206484 kb
Host smart-54c68988-9d90-4c91-bb2e-7508d8e16480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25540
73981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.2554073981
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.668339376
Short name T1861
Test name
Test status
Simulation time 9735965645 ps
CPU time 71.15 seconds
Started Jun 25 05:01:04 PM PDT 24
Finished Jun 25 05:02:17 PM PDT 24
Peak memory 206960 kb
Host smart-09a605f8-0341-4ea8-95e3-897891d9f03e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=668339376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.668339376
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.3389960656
Short name T1466
Test name
Test status
Simulation time 173993476 ps
CPU time 0.81 seconds
Started Jun 25 05:01:03 PM PDT 24
Finished Jun 25 05:01:05 PM PDT 24
Peak memory 206584 kb
Host smart-6627e339-841a-41f7-84e6-b9e818100c99
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3389960656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.3389960656
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.79114442
Short name T1418
Test name
Test status
Simulation time 142539504 ps
CPU time 0.78 seconds
Started Jun 25 05:01:06 PM PDT 24
Finished Jun 25 05:01:09 PM PDT 24
Peak memory 206412 kb
Host smart-e8fe9ebe-83e6-474e-97af-0b3160384102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79114
442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.79114442
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.2843445808
Short name T125
Test name
Test status
Simulation time 208611235 ps
CPU time 0.9 seconds
Started Jun 25 05:01:01 PM PDT 24
Finished Jun 25 05:01:03 PM PDT 24
Peak memory 206472 kb
Host smart-efd30711-ee7c-4047-9b64-014a26ccb299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28434
45808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.2843445808
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.1950720436
Short name T1789
Test name
Test status
Simulation time 200988948 ps
CPU time 0.89 seconds
Started Jun 25 05:01:02 PM PDT 24
Finished Jun 25 05:01:04 PM PDT 24
Peak memory 206504 kb
Host smart-90970f24-8c45-4afb-8810-30eadfc6039d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19507
20436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.1950720436
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.3283412791
Short name T795
Test name
Test status
Simulation time 198679478 ps
CPU time 0.81 seconds
Started Jun 25 05:01:06 PM PDT 24
Finished Jun 25 05:01:09 PM PDT 24
Peak memory 206428 kb
Host smart-026c6f1b-b4bc-469c-b95a-fdf564c885fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32834
12791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.3283412791
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.886617487
Short name T1336
Test name
Test status
Simulation time 181423006 ps
CPU time 0.83 seconds
Started Jun 25 05:01:02 PM PDT 24
Finished Jun 25 05:01:04 PM PDT 24
Peak memory 206496 kb
Host smart-7d595f77-2c24-4208-8986-f6c3c144e769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88661
7487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.886617487
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.1341390314
Short name T953
Test name
Test status
Simulation time 166173941 ps
CPU time 0.85 seconds
Started Jun 25 05:01:02 PM PDT 24
Finished Jun 25 05:01:05 PM PDT 24
Peak memory 206596 kb
Host smart-f7bba8c5-aada-4c74-a27a-b3dc86863562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13413
90314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.1341390314
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.1272875639
Short name T1757
Test name
Test status
Simulation time 218445937 ps
CPU time 0.96 seconds
Started Jun 25 05:01:04 PM PDT 24
Finished Jun 25 05:01:07 PM PDT 24
Peak memory 206516 kb
Host smart-4bd0c330-0fb9-4a43-8573-e21cb0d98415
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1272875639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.1272875639
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.1316688380
Short name T1925
Test name
Test status
Simulation time 140802719 ps
CPU time 0.76 seconds
Started Jun 25 05:01:01 PM PDT 24
Finished Jun 25 05:01:03 PM PDT 24
Peak memory 206572 kb
Host smart-defc56d6-c968-47ce-aad9-6198c6e673c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13166
88380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.1316688380
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.1679684974
Short name T2351
Test name
Test status
Simulation time 42144076 ps
CPU time 0.69 seconds
Started Jun 25 05:01:05 PM PDT 24
Finished Jun 25 05:01:07 PM PDT 24
Peak memory 206588 kb
Host smart-5c15afab-c312-4f0f-a159-f7d869de4742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16796
84974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.1679684974
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.780596611
Short name T1908
Test name
Test status
Simulation time 15825391963 ps
CPU time 33.91 seconds
Started Jun 25 05:01:03 PM PDT 24
Finished Jun 25 05:01:39 PM PDT 24
Peak memory 206860 kb
Host smart-648a661b-2833-4a74-88bb-aa2c273facc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78059
6611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.780596611
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.2762705398
Short name T1141
Test name
Test status
Simulation time 171170878 ps
CPU time 0.86 seconds
Started Jun 25 05:01:06 PM PDT 24
Finished Jun 25 05:01:08 PM PDT 24
Peak memory 206456 kb
Host smart-a85d7999-6f55-4677-bb1c-daf3585e51fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27627
05398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.2762705398
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.2143344370
Short name T670
Test name
Test status
Simulation time 171121137 ps
CPU time 0.79 seconds
Started Jun 25 05:01:03 PM PDT 24
Finished Jun 25 05:01:05 PM PDT 24
Peak memory 206572 kb
Host smart-a34e152d-5292-4ad1-95e0-4d9d795c254b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21433
44370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.2143344370
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.1444223861
Short name T1792
Test name
Test status
Simulation time 241317611 ps
CPU time 0.98 seconds
Started Jun 25 05:01:05 PM PDT 24
Finished Jun 25 05:01:08 PM PDT 24
Peak memory 206520 kb
Host smart-73ade3ce-3ccc-4000-8158-2cf9163c7433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14442
23861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.1444223861
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.3244018616
Short name T1408
Test name
Test status
Simulation time 194427789 ps
CPU time 0.9 seconds
Started Jun 25 05:01:01 PM PDT 24
Finished Jun 25 05:01:04 PM PDT 24
Peak memory 206584 kb
Host smart-9d59c67f-d634-4574-9dc2-0b97ccd5ed83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32440
18616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.3244018616
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.383060375
Short name T914
Test name
Test status
Simulation time 169496809 ps
CPU time 0.82 seconds
Started Jun 25 05:01:03 PM PDT 24
Finished Jun 25 05:01:05 PM PDT 24
Peak memory 206604 kb
Host smart-a6f93fe0-a5e2-4a96-b7ea-e6c531b199fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38306
0375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.383060375
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.2990072701
Short name T2052
Test name
Test status
Simulation time 146656006 ps
CPU time 0.79 seconds
Started Jun 25 05:01:06 PM PDT 24
Finished Jun 25 05:01:09 PM PDT 24
Peak memory 206456 kb
Host smart-02467471-7891-4b9e-b749-0e33858760f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29900
72701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.2990072701
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.2350856192
Short name T2464
Test name
Test status
Simulation time 155525289 ps
CPU time 0.85 seconds
Started Jun 25 05:01:05 PM PDT 24
Finished Jun 25 05:01:07 PM PDT 24
Peak memory 206592 kb
Host smart-d6bf0297-92a7-494f-96c1-47385f98bbdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23508
56192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.2350856192
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.2653590194
Short name T1752
Test name
Test status
Simulation time 176322597 ps
CPU time 0.86 seconds
Started Jun 25 05:01:03 PM PDT 24
Finished Jun 25 05:01:05 PM PDT 24
Peak memory 206584 kb
Host smart-81400a6e-72fc-4316-b1eb-f12a25218da1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26535
90194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.2653590194
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.196390127
Short name T1179
Test name
Test status
Simulation time 8521168972 ps
CPU time 244.18 seconds
Started Jun 25 05:01:04 PM PDT 24
Finished Jun 25 05:05:09 PM PDT 24
Peak memory 206972 kb
Host smart-8e79f9af-5ce9-4f5b-8099-1d5682df6b7a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=196390127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.196390127
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.1430283452
Short name T2473
Test name
Test status
Simulation time 161932542 ps
CPU time 0.78 seconds
Started Jun 25 05:01:03 PM PDT 24
Finished Jun 25 05:01:05 PM PDT 24
Peak memory 206500 kb
Host smart-fda3c4cd-2d5d-4d22-b48b-5a7a14e706f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14302
83452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.1430283452
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.69228297
Short name T321
Test name
Test status
Simulation time 190417294 ps
CPU time 0.82 seconds
Started Jun 25 05:01:06 PM PDT 24
Finished Jun 25 05:01:08 PM PDT 24
Peak memory 206464 kb
Host smart-04d8c7ae-8baa-41b7-9f46-35350e86ec11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69228
297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.69228297
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.1481109762
Short name T298
Test name
Test status
Simulation time 13570924909 ps
CPU time 375.57 seconds
Started Jun 25 05:01:05 PM PDT 24
Finished Jun 25 05:07:22 PM PDT 24
Peak memory 206860 kb
Host smart-02b3be5a-941c-48aa-af06-9954ecdd424f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14811
09762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.1481109762
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.4171432818
Short name T9
Test name
Test status
Simulation time 4363235665 ps
CPU time 5.62 seconds
Started Jun 25 05:01:12 PM PDT 24
Finished Jun 25 05:01:19 PM PDT 24
Peak memory 206720 kb
Host smart-f84413a9-d20a-47e6-8a42-dc541989402e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4171432818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.4171432818
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.1411974686
Short name T1138
Test name
Test status
Simulation time 13343560120 ps
CPU time 12 seconds
Started Jun 25 05:01:12 PM PDT 24
Finished Jun 25 05:01:26 PM PDT 24
Peak memory 206744 kb
Host smart-86b73702-6727-49fc-a2f9-e30168e8f8ee
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1411974686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.1411974686
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.182195671
Short name T1589
Test name
Test status
Simulation time 23374107965 ps
CPU time 22.31 seconds
Started Jun 25 05:01:06 PM PDT 24
Finished Jun 25 05:01:30 PM PDT 24
Peak memory 206736 kb
Host smart-c721b491-6223-4581-be18-547e78f354f7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=182195671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.182195671
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.2939431348
Short name T360
Test name
Test status
Simulation time 182296944 ps
CPU time 0.82 seconds
Started Jun 25 05:01:03 PM PDT 24
Finished Jun 25 05:01:06 PM PDT 24
Peak memory 206572 kb
Host smart-40d06802-8140-46cb-b3fb-5cab654e1dd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29394
31348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.2939431348
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.2961884010
Short name T1612
Test name
Test status
Simulation time 227344832 ps
CPU time 0.94 seconds
Started Jun 25 05:01:11 PM PDT 24
Finished Jun 25 05:01:14 PM PDT 24
Peak memory 206484 kb
Host smart-9e2fa607-538e-43a0-98d1-7f0da925c5a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29618
84010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.2961884010
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.756164086
Short name T2079
Test name
Test status
Simulation time 493052294 ps
CPU time 1.62 seconds
Started Jun 25 05:01:18 PM PDT 24
Finished Jun 25 05:01:22 PM PDT 24
Peak memory 206572 kb
Host smart-e76c63cb-25e5-4a36-9c57-8ebae4801b76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75616
4086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.756164086
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.2848558489
Short name T1923
Test name
Test status
Simulation time 1374018123 ps
CPU time 3.09 seconds
Started Jun 25 05:01:11 PM PDT 24
Finished Jun 25 05:01:16 PM PDT 24
Peak memory 206672 kb
Host smart-0da5bc2f-c599-46f1-aef3-de67fc8f2694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28485
58489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.2848558489
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.3969253208
Short name T99
Test name
Test status
Simulation time 16389175693 ps
CPU time 29.3 seconds
Started Jun 25 05:01:16 PM PDT 24
Finished Jun 25 05:01:46 PM PDT 24
Peak memory 206960 kb
Host smart-f214bb58-dbe8-4e67-a206-1065a3f7263f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39692
53208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.3969253208
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.4263123847
Short name T1314
Test name
Test status
Simulation time 298992341 ps
CPU time 1.07 seconds
Started Jun 25 05:01:12 PM PDT 24
Finished Jun 25 05:01:14 PM PDT 24
Peak memory 206504 kb
Host smart-6da57829-06b5-4f52-8fbc-df7bf3bfd977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42631
23847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.4263123847
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.3458292171
Short name T951
Test name
Test status
Simulation time 134492892 ps
CPU time 0.79 seconds
Started Jun 25 05:01:13 PM PDT 24
Finished Jun 25 05:01:15 PM PDT 24
Peak memory 206596 kb
Host smart-9f1eb32c-c863-4c44-bcfa-020543bca7e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34582
92171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.3458292171
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.2992068530
Short name T937
Test name
Test status
Simulation time 44609616 ps
CPU time 0.69 seconds
Started Jun 25 05:01:10 PM PDT 24
Finished Jun 25 05:01:11 PM PDT 24
Peak memory 206532 kb
Host smart-1ac9a835-f500-449e-82ae-2a95a918c63f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29920
68530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.2992068530
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.325708519
Short name T1323
Test name
Test status
Simulation time 907887187 ps
CPU time 2.41 seconds
Started Jun 25 05:01:14 PM PDT 24
Finished Jun 25 05:01:18 PM PDT 24
Peak memory 206820 kb
Host smart-3b9c2bc8-8049-4b0b-9123-a906b94c7334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32570
8519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.325708519
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.2807618799
Short name T1082
Test name
Test status
Simulation time 282203722 ps
CPU time 1.78 seconds
Started Jun 25 05:01:16 PM PDT 24
Finished Jun 25 05:01:19 PM PDT 24
Peak memory 206820 kb
Host smart-799f2aa5-20d8-45c2-8709-5c41a58cc8fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28076
18799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.2807618799
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.4110255845
Short name T113
Test name
Test status
Simulation time 188468671 ps
CPU time 0.86 seconds
Started Jun 25 05:01:11 PM PDT 24
Finished Jun 25 05:01:13 PM PDT 24
Peak memory 206588 kb
Host smart-f0fc65a1-7a97-4fa7-b59c-86c897256210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41102
55845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.4110255845
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.238939875
Short name T448
Test name
Test status
Simulation time 151037718 ps
CPU time 0.77 seconds
Started Jun 25 05:01:12 PM PDT 24
Finished Jun 25 05:01:15 PM PDT 24
Peak memory 206500 kb
Host smart-febdaaa7-fce2-49c2-aaad-9db632135ddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23893
9875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.238939875
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.386300096
Short name T1455
Test name
Test status
Simulation time 210470313 ps
CPU time 0.94 seconds
Started Jun 25 05:01:12 PM PDT 24
Finished Jun 25 05:01:14 PM PDT 24
Peak memory 206748 kb
Host smart-7b9b83c0-d00a-4fbe-be7c-d47b1ada59c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38630
0096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.386300096
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_invalid_sync.917206466
Short name T958
Test name
Test status
Simulation time 7120875577 ps
CPU time 191.38 seconds
Started Jun 25 05:01:11 PM PDT 24
Finished Jun 25 05:04:23 PM PDT 24
Peak memory 206936 kb
Host smart-2acf9252-27bc-4c1a-b195-3bbd0f913377
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=917206466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.917206466
Directory /workspace/31.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.3201779643
Short name T1199
Test name
Test status
Simulation time 214644720 ps
CPU time 0.89 seconds
Started Jun 25 05:01:12 PM PDT 24
Finished Jun 25 05:01:15 PM PDT 24
Peak memory 206596 kb
Host smart-565fb469-b7fd-4285-b148-f28af1760524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32017
79643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.3201779643
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.3463288215
Short name T2349
Test name
Test status
Simulation time 23331747599 ps
CPU time 23.6 seconds
Started Jun 25 05:01:09 PM PDT 24
Finished Jun 25 05:01:34 PM PDT 24
Peak memory 206612 kb
Host smart-87146aa6-643c-4dcd-bd8b-71929af66d47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34632
88215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.3463288215
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.3037571287
Short name T444
Test name
Test status
Simulation time 3371240390 ps
CPU time 3.57 seconds
Started Jun 25 05:01:12 PM PDT 24
Finished Jun 25 05:01:18 PM PDT 24
Peak memory 206648 kb
Host smart-a174c6ff-4cd1-4c47-92d7-aff1e5339bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30375
71287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.3037571287
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.2810619224
Short name T1271
Test name
Test status
Simulation time 9939243729 ps
CPU time 90.99 seconds
Started Jun 25 05:01:14 PM PDT 24
Finished Jun 25 05:02:46 PM PDT 24
Peak memory 206816 kb
Host smart-90722052-effb-455d-b6e5-08fa543fe230
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2810619224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.2810619224
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.1925623538
Short name T1739
Test name
Test status
Simulation time 243940115 ps
CPU time 0.89 seconds
Started Jun 25 05:01:16 PM PDT 24
Finished Jun 25 05:01:18 PM PDT 24
Peak memory 206500 kb
Host smart-555efb34-f069-48cd-b92a-b8efc6d3d098
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1925623538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.1925623538
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.2827718976
Short name T650
Test name
Test status
Simulation time 198630987 ps
CPU time 1.01 seconds
Started Jun 25 05:01:16 PM PDT 24
Finished Jun 25 05:01:19 PM PDT 24
Peak memory 206524 kb
Host smart-4cfecbfd-4073-4e85-a717-3e02f30dbf65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28277
18976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.2827718976
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.1927389042
Short name T913
Test name
Test status
Simulation time 9552166442 ps
CPU time 90.43 seconds
Started Jun 25 05:01:14 PM PDT 24
Finished Jun 25 05:02:46 PM PDT 24
Peak memory 206772 kb
Host smart-b76a0aed-54e2-4c65-a560-60e1a50ffb54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19273
89042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.1927389042
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.848818970
Short name T1022
Test name
Test status
Simulation time 10336553873 ps
CPU time 81.51 seconds
Started Jun 25 05:01:14 PM PDT 24
Finished Jun 25 05:02:37 PM PDT 24
Peak memory 206884 kb
Host smart-5faf794d-420b-4b02-8456-39c8414b7f4b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=848818970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.848818970
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.2258816565
Short name T1760
Test name
Test status
Simulation time 186991804 ps
CPU time 0.84 seconds
Started Jun 25 05:01:12 PM PDT 24
Finished Jun 25 05:01:15 PM PDT 24
Peak memory 206584 kb
Host smart-53a269fc-f817-47a5-85d2-869a61062862
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2258816565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.2258816565
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.426264648
Short name T2197
Test name
Test status
Simulation time 211766431 ps
CPU time 0.8 seconds
Started Jun 25 05:01:11 PM PDT 24
Finished Jun 25 05:01:14 PM PDT 24
Peak memory 206880 kb
Host smart-06fba547-019f-486f-a25e-38c5ee815f0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42626
4648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.426264648
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.192154786
Short name T1833
Test name
Test status
Simulation time 202181584 ps
CPU time 0.87 seconds
Started Jun 25 05:01:12 PM PDT 24
Finished Jun 25 05:01:15 PM PDT 24
Peak memory 206444 kb
Host smart-e3c1c226-ce79-4181-a781-50ae4d845bf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19215
4786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.192154786
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.483319284
Short name T1151
Test name
Test status
Simulation time 189507626 ps
CPU time 0.81 seconds
Started Jun 25 05:01:09 PM PDT 24
Finished Jun 25 05:01:11 PM PDT 24
Peak memory 206504 kb
Host smart-eab98536-373e-44ba-ae8d-32801e735aeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48331
9284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.483319284
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.1497498920
Short name T2077
Test name
Test status
Simulation time 172969950 ps
CPU time 0.79 seconds
Started Jun 25 05:01:15 PM PDT 24
Finished Jun 25 05:01:17 PM PDT 24
Peak memory 206604 kb
Host smart-139524b0-1965-419f-9420-304f677f55fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14974
98920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.1497498920
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.2906125292
Short name T2423
Test name
Test status
Simulation time 152228090 ps
CPU time 0.8 seconds
Started Jun 25 05:01:18 PM PDT 24
Finished Jun 25 05:01:20 PM PDT 24
Peak memory 206572 kb
Host smart-7591d69a-ec65-422f-8155-bca46e6fdfdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29061
25292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.2906125292
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.4121145932
Short name T972
Test name
Test status
Simulation time 253169730 ps
CPU time 0.98 seconds
Started Jun 25 05:01:16 PM PDT 24
Finished Jun 25 05:01:18 PM PDT 24
Peak memory 206568 kb
Host smart-85be06c2-4e74-49f9-a81e-49e8e47c7a9f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4121145932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.4121145932
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.494644218
Short name T2509
Test name
Test status
Simulation time 165125168 ps
CPU time 0.75 seconds
Started Jun 25 05:01:10 PM PDT 24
Finished Jun 25 05:01:12 PM PDT 24
Peak memory 206516 kb
Host smart-79b2fae5-d859-420b-aa5d-e0be54299eb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49464
4218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.494644218
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.555299828
Short name T1481
Test name
Test status
Simulation time 39461555 ps
CPU time 0.68 seconds
Started Jun 25 05:01:18 PM PDT 24
Finished Jun 25 05:01:20 PM PDT 24
Peak memory 206568 kb
Host smart-a04f9e67-c0b2-4831-9cff-f10ce96f347b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55529
9828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.555299828
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.2894999233
Short name T730
Test name
Test status
Simulation time 151947878 ps
CPU time 0.81 seconds
Started Jun 25 05:01:10 PM PDT 24
Finished Jun 25 05:01:12 PM PDT 24
Peak memory 206496 kb
Host smart-0125f91e-0bdb-4202-9a3c-2690434671fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28949
99233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.2894999233
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.4037753924
Short name T1183
Test name
Test status
Simulation time 205006093 ps
CPU time 0.83 seconds
Started Jun 25 05:01:11 PM PDT 24
Finished Jun 25 05:01:13 PM PDT 24
Peak memory 206572 kb
Host smart-323b5e41-d3b9-46ca-9663-39d87d23d9cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40377
53924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.4037753924
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.3218811876
Short name T2475
Test name
Test status
Simulation time 221258763 ps
CPU time 0.89 seconds
Started Jun 25 05:01:11 PM PDT 24
Finished Jun 25 05:01:14 PM PDT 24
Peak memory 206616 kb
Host smart-6079e8cb-573d-4708-addf-f0ad7810c663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32188
11876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.3218811876
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.3950697738
Short name T999
Test name
Test status
Simulation time 156846395 ps
CPU time 0.8 seconds
Started Jun 25 05:01:12 PM PDT 24
Finished Jun 25 05:01:15 PM PDT 24
Peak memory 206572 kb
Host smart-d8839315-95da-4133-b8ba-1b2dfb5f4dd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39506
97738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.3950697738
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.3218100095
Short name T1809
Test name
Test status
Simulation time 181381076 ps
CPU time 0.83 seconds
Started Jun 25 05:01:16 PM PDT 24
Finished Jun 25 05:01:18 PM PDT 24
Peak memory 206496 kb
Host smart-dc311567-7603-4d66-a8a1-0d22bb2cb519
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32181
00095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.3218100095
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.1729905834
Short name T2507
Test name
Test status
Simulation time 155477907 ps
CPU time 0.78 seconds
Started Jun 25 05:01:11 PM PDT 24
Finished Jun 25 05:01:14 PM PDT 24
Peak memory 206568 kb
Host smart-cb7001dc-1aea-4225-9195-8ed204e56cfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17299
05834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.1729905834
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.3353158589
Short name T1465
Test name
Test status
Simulation time 149095167 ps
CPU time 0.75 seconds
Started Jun 25 05:01:12 PM PDT 24
Finished Jun 25 05:01:15 PM PDT 24
Peak memory 206496 kb
Host smart-92b8dfb4-98ee-46d1-a7ed-f26bb7962071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33531
58589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.3353158589
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.806065882
Short name T789
Test name
Test status
Simulation time 239998097 ps
CPU time 1.06 seconds
Started Jun 25 05:01:13 PM PDT 24
Finished Jun 25 05:01:16 PM PDT 24
Peak memory 206612 kb
Host smart-ad38553a-b5b1-490d-b956-78f860e3a85f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80606
5882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.806065882
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.3777179514
Short name T2076
Test name
Test status
Simulation time 4385246889 ps
CPU time 40.97 seconds
Started Jun 25 05:01:16 PM PDT 24
Finished Jun 25 05:01:58 PM PDT 24
Peak memory 206852 kb
Host smart-ce3267e1-12cf-47f8-aca3-4c7878a06eda
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3777179514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.3777179514
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.1897738952
Short name T1553
Test name
Test status
Simulation time 170333378 ps
CPU time 0.82 seconds
Started Jun 25 05:01:14 PM PDT 24
Finished Jun 25 05:01:16 PM PDT 24
Peak memory 206504 kb
Host smart-9724a722-9d11-49bb-9e4d-721814383e03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18977
38952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.1897738952
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.3533162080
Short name T1922
Test name
Test status
Simulation time 210896876 ps
CPU time 0.87 seconds
Started Jun 25 05:01:11 PM PDT 24
Finished Jun 25 05:01:14 PM PDT 24
Peak memory 206572 kb
Host smart-943ebe33-9874-40cb-bf38-a3ed313b8dcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35331
62080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.3533162080
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.121859141
Short name T2382
Test name
Test status
Simulation time 14439811122 ps
CPU time 99.64 seconds
Started Jun 25 05:01:11 PM PDT 24
Finished Jun 25 05:02:53 PM PDT 24
Peak memory 206868 kb
Host smart-a1ac9418-1a21-4709-8d3f-5582a82cad59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12185
9141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.121859141
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.3626587084
Short name T451
Test name
Test status
Simulation time 4335497982 ps
CPU time 5.31 seconds
Started Jun 25 05:01:11 PM PDT 24
Finished Jun 25 05:01:18 PM PDT 24
Peak memory 206848 kb
Host smart-b461b04c-ef4c-43f9-b471-e7cd349cbb55
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3626587084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.3626587084
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.496904073
Short name T1704
Test name
Test status
Simulation time 13329622231 ps
CPU time 15.74 seconds
Started Jun 25 05:01:14 PM PDT 24
Finished Jun 25 05:01:31 PM PDT 24
Peak memory 206888 kb
Host smart-d1880dfb-638e-48e3-8243-aeca3189fbe6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=496904073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.496904073
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.4024776799
Short name T932
Test name
Test status
Simulation time 23333631294 ps
CPU time 23.26 seconds
Started Jun 25 05:01:11 PM PDT 24
Finished Jun 25 05:01:36 PM PDT 24
Peak memory 206736 kb
Host smart-1b015204-992b-4526-a8b8-5ee52d9180e5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4024776799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.4024776799
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.859353105
Short name T2162
Test name
Test status
Simulation time 186370427 ps
CPU time 0.85 seconds
Started Jun 25 05:01:19 PM PDT 24
Finished Jun 25 05:01:21 PM PDT 24
Peak memory 206572 kb
Host smart-fa8fdc02-4803-4948-a14c-792e9e038f9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85935
3105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.859353105
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.71214931
Short name T1914
Test name
Test status
Simulation time 167687622 ps
CPU time 0.87 seconds
Started Jun 25 05:01:18 PM PDT 24
Finished Jun 25 05:01:21 PM PDT 24
Peak memory 206572 kb
Host smart-4986fd52-fcfb-4a31-9284-775cca831d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71214
931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.71214931
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.1457852144
Short name T1813
Test name
Test status
Simulation time 254779562 ps
CPU time 1.04 seconds
Started Jun 25 05:01:16 PM PDT 24
Finished Jun 25 05:01:18 PM PDT 24
Peak memory 206488 kb
Host smart-07bcafee-d5b6-4304-9c85-c7401b062b4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14578
52144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.1457852144
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.2399314784
Short name T1431
Test name
Test status
Simulation time 410921027 ps
CPU time 1.25 seconds
Started Jun 25 05:01:17 PM PDT 24
Finished Jun 25 05:01:20 PM PDT 24
Peak memory 206572 kb
Host smart-18a5edba-8501-4de0-9792-beef01ceb9fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23993
14784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.2399314784
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.2023899984
Short name T2115
Test name
Test status
Simulation time 12959110539 ps
CPU time 23.88 seconds
Started Jun 25 05:01:10 PM PDT 24
Finished Jun 25 05:01:36 PM PDT 24
Peak memory 206944 kb
Host smart-e173ae16-d9f5-4ad5-97f6-b1720044ce39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20238
99984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.2023899984
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.2801946798
Short name T2175
Test name
Test status
Simulation time 338445867 ps
CPU time 1.3 seconds
Started Jun 25 05:01:15 PM PDT 24
Finished Jun 25 05:01:18 PM PDT 24
Peak memory 206520 kb
Host smart-a2e1582e-b12c-4307-b1da-5acc08a75586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28019
46798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.2801946798
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.716208214
Short name T770
Test name
Test status
Simulation time 140250008 ps
CPU time 0.74 seconds
Started Jun 25 05:01:16 PM PDT 24
Finished Jun 25 05:01:18 PM PDT 24
Peak memory 206596 kb
Host smart-d4f6074d-6c8f-479a-b218-6176b75fa1cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71620
8214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.716208214
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.4006784802
Short name T1110
Test name
Test status
Simulation time 39683318 ps
CPU time 0.67 seconds
Started Jun 25 05:01:10 PM PDT 24
Finished Jun 25 05:01:12 PM PDT 24
Peak memory 206492 kb
Host smart-121e7c09-24c6-48fb-b5c3-97af8b5a5334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40067
84802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.4006784802
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.4154544758
Short name T1352
Test name
Test status
Simulation time 742053841 ps
CPU time 2.15 seconds
Started Jun 25 05:01:15 PM PDT 24
Finished Jun 25 05:01:18 PM PDT 24
Peak memory 206680 kb
Host smart-cedf94b3-9fa6-435e-bdb9-77a9fdf6609e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41545
44758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.4154544758
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.3426836662
Short name T2212
Test name
Test status
Simulation time 262154163 ps
CPU time 1.78 seconds
Started Jun 25 05:01:22 PM PDT 24
Finished Jun 25 05:01:26 PM PDT 24
Peak memory 206816 kb
Host smart-a8b925a6-5c45-4529-8d8b-e4f6694db39d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34268
36662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.3426836662
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.883558648
Short name T959
Test name
Test status
Simulation time 154281711 ps
CPU time 0.79 seconds
Started Jun 25 05:01:22 PM PDT 24
Finished Jun 25 05:01:25 PM PDT 24
Peak memory 206592 kb
Host smart-4768f614-f1e3-4e9f-9c2e-3dd7fe9f78be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88355
8648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.883558648
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.823909810
Short name T1936
Test name
Test status
Simulation time 153114155 ps
CPU time 0.79 seconds
Started Jun 25 05:01:22 PM PDT 24
Finished Jun 25 05:01:25 PM PDT 24
Peak memory 206572 kb
Host smart-b21758d4-bc83-4e56-b4e0-799817a70a9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82390
9810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.823909810
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.2379434904
Short name T857
Test name
Test status
Simulation time 197873375 ps
CPU time 0.84 seconds
Started Jun 25 05:01:21 PM PDT 24
Finished Jun 25 05:01:24 PM PDT 24
Peak memory 206496 kb
Host smart-8b0fc135-63bf-4643-9d4f-c78b0af77f1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23794
34904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.2379434904
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.1123583277
Short name T2219
Test name
Test status
Simulation time 170526023 ps
CPU time 0.88 seconds
Started Jun 25 05:01:20 PM PDT 24
Finished Jun 25 05:01:22 PM PDT 24
Peak memory 206600 kb
Host smart-07ca89f3-51df-4e89-b2bd-9e79f07557b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11235
83277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.1123583277
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.1802199586
Short name T1134
Test name
Test status
Simulation time 23295771435 ps
CPU time 24.08 seconds
Started Jun 25 05:01:19 PM PDT 24
Finished Jun 25 05:01:44 PM PDT 24
Peak memory 206616 kb
Host smart-70ac8e6b-484e-4c3a-8b2d-d691a542178b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18021
99586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.1802199586
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.1521235877
Short name T1686
Test name
Test status
Simulation time 3313583582 ps
CPU time 4.02 seconds
Started Jun 25 05:01:22 PM PDT 24
Finished Jun 25 05:01:28 PM PDT 24
Peak memory 206692 kb
Host smart-8f13603f-122c-4e5a-98ad-6a6397ec92d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15212
35877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.1521235877
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.3405046040
Short name T2142
Test name
Test status
Simulation time 12125351320 ps
CPU time 85.17 seconds
Started Jun 25 05:01:21 PM PDT 24
Finished Jun 25 05:02:48 PM PDT 24
Peak memory 206828 kb
Host smart-91a0398c-18c6-4f4c-b099-8d9c4d789162
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3405046040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.3405046040
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.289637399
Short name T1012
Test name
Test status
Simulation time 240142400 ps
CPU time 0.89 seconds
Started Jun 25 05:01:23 PM PDT 24
Finished Jun 25 05:01:26 PM PDT 24
Peak memory 206596 kb
Host smart-51bb02dd-8672-48f2-a6b0-93409eb3efcd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=289637399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.289637399
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.2071953221
Short name T2036
Test name
Test status
Simulation time 262220026 ps
CPU time 0.94 seconds
Started Jun 25 05:01:21 PM PDT 24
Finished Jun 25 05:01:24 PM PDT 24
Peak memory 206564 kb
Host smart-536e6f60-0d32-44f7-8ffa-ddf45cf3a305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20719
53221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.2071953221
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.1155217495
Short name T1576
Test name
Test status
Simulation time 4205849582 ps
CPU time 38.39 seconds
Started Jun 25 05:01:22 PM PDT 24
Finished Jun 25 05:02:03 PM PDT 24
Peak memory 206788 kb
Host smart-d56f6330-186d-4289-be31-efd800ac78c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11552
17495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.1155217495
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.1226397021
Short name T415
Test name
Test status
Simulation time 4419809876 ps
CPU time 32.02 seconds
Started Jun 25 05:01:19 PM PDT 24
Finished Jun 25 05:01:52 PM PDT 24
Peak memory 206816 kb
Host smart-2e1a12d3-ed6c-44e7-bce7-a3c1c9d0d4ac
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1226397021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.1226397021
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.1764206055
Short name T2418
Test name
Test status
Simulation time 184832250 ps
CPU time 0.8 seconds
Started Jun 25 05:01:24 PM PDT 24
Finished Jun 25 05:01:27 PM PDT 24
Peak memory 206572 kb
Host smart-5d94e16a-2df8-4989-9a5c-3de8271dee1f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1764206055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.1764206055
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.2633953981
Short name T580
Test name
Test status
Simulation time 189392524 ps
CPU time 0.83 seconds
Started Jun 25 05:01:19 PM PDT 24
Finished Jun 25 05:01:22 PM PDT 24
Peak memory 206604 kb
Host smart-d5dd4b2b-56be-41a7-874f-b73f16b7d382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26339
53981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.2633953981
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.1191642439
Short name T124
Test name
Test status
Simulation time 202451796 ps
CPU time 0.84 seconds
Started Jun 25 05:01:21 PM PDT 24
Finished Jun 25 05:01:24 PM PDT 24
Peak memory 206572 kb
Host smart-92ee4868-9eef-4545-926c-2b8e73ce9dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11916
42439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.1191642439
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.1622738129
Short name T1163
Test name
Test status
Simulation time 165866229 ps
CPU time 0.91 seconds
Started Jun 25 05:01:21 PM PDT 24
Finished Jun 25 05:01:24 PM PDT 24
Peak memory 206596 kb
Host smart-00ccf0c5-bdac-4178-832d-a4d56eb6efed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16227
38129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.1622738129
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.1346184964
Short name T982
Test name
Test status
Simulation time 187444439 ps
CPU time 0.83 seconds
Started Jun 25 05:01:20 PM PDT 24
Finished Jun 25 05:01:23 PM PDT 24
Peak memory 206572 kb
Host smart-615a7c7b-3578-4b2f-b7a2-33dd96651c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13461
84964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.1346184964
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.1575128851
Short name T814
Test name
Test status
Simulation time 171264152 ps
CPU time 0.83 seconds
Started Jun 25 05:01:31 PM PDT 24
Finished Jun 25 05:01:34 PM PDT 24
Peak memory 206520 kb
Host smart-1c5981fd-2e62-4d4f-86a9-f48b317905d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15751
28851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.1575128851
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.377879157
Short name T1355
Test name
Test status
Simulation time 245203680 ps
CPU time 0.88 seconds
Started Jun 25 05:01:19 PM PDT 24
Finished Jun 25 05:01:22 PM PDT 24
Peak memory 206876 kb
Host smart-f56a4abb-e6ee-4325-b384-bf1e2b55fb73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37787
9157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.377879157
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.1157418197
Short name T1836
Test name
Test status
Simulation time 227168407 ps
CPU time 0.96 seconds
Started Jun 25 05:01:24 PM PDT 24
Finished Jun 25 05:01:26 PM PDT 24
Peak memory 206572 kb
Host smart-af584529-17ad-43e9-a5e2-792576d7f6a6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1157418197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.1157418197
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.3309148883
Short name T1354
Test name
Test status
Simulation time 143744146 ps
CPU time 0.75 seconds
Started Jun 25 05:01:20 PM PDT 24
Finished Jun 25 05:01:23 PM PDT 24
Peak memory 206520 kb
Host smart-89ef8e4a-7835-4098-95fd-b26f8f341010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33091
48883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.3309148883
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.128144515
Short name T736
Test name
Test status
Simulation time 74024418 ps
CPU time 0.78 seconds
Started Jun 25 05:01:19 PM PDT 24
Finished Jun 25 05:01:21 PM PDT 24
Peak memory 206576 kb
Host smart-46cb1f15-e46e-4c55-98a3-ee38a1ef4bd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12814
4515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.128144515
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.2232251003
Short name T1060
Test name
Test status
Simulation time 19053683481 ps
CPU time 43.18 seconds
Started Jun 25 05:01:21 PM PDT 24
Finished Jun 25 05:02:07 PM PDT 24
Peak memory 206828 kb
Host smart-86d9df3d-5717-449f-a6f5-9976fc33a109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22322
51003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.2232251003
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.2439263874
Short name T807
Test name
Test status
Simulation time 156409177 ps
CPU time 0.81 seconds
Started Jun 25 05:01:22 PM PDT 24
Finished Jun 25 05:01:25 PM PDT 24
Peak memory 206592 kb
Host smart-d595d174-731b-4fae-b1a0-e4f252bfdb35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24392
63874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.2439263874
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.730418760
Short name T2424
Test name
Test status
Simulation time 159802024 ps
CPU time 0.82 seconds
Started Jun 25 05:01:22 PM PDT 24
Finished Jun 25 05:01:25 PM PDT 24
Peak memory 206564 kb
Host smart-b63d0d3f-9951-43ee-818b-c530b38ccddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73041
8760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.730418760
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.1134116769
Short name T1222
Test name
Test status
Simulation time 200629657 ps
CPU time 0.85 seconds
Started Jun 25 05:01:31 PM PDT 24
Finished Jun 25 05:01:33 PM PDT 24
Peak memory 206544 kb
Host smart-b903bc96-20c6-4762-955c-cdae39f2db10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11341
16769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.1134116769
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.1912620467
Short name T2259
Test name
Test status
Simulation time 210701276 ps
CPU time 0.82 seconds
Started Jun 25 05:01:20 PM PDT 24
Finished Jun 25 05:01:22 PM PDT 24
Peak memory 206536 kb
Host smart-16538890-d283-4a68-9fc0-ac0eb4cf5aee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19126
20467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.1912620467
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.4263791263
Short name T1511
Test name
Test status
Simulation time 191163970 ps
CPU time 0.82 seconds
Started Jun 25 05:01:22 PM PDT 24
Finished Jun 25 05:01:25 PM PDT 24
Peak memory 206496 kb
Host smart-33bb9df6-88e2-4a15-adbc-c92056c2b400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42637
91263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.4263791263
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.1499320389
Short name T943
Test name
Test status
Simulation time 187582555 ps
CPU time 0.8 seconds
Started Jun 25 05:01:22 PM PDT 24
Finished Jun 25 05:01:25 PM PDT 24
Peak memory 206568 kb
Host smart-e160e243-e833-44bc-ba3f-9d7b03ba4305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14993
20389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.1499320389
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.976280982
Short name T1275
Test name
Test status
Simulation time 175685799 ps
CPU time 0.85 seconds
Started Jun 25 05:01:22 PM PDT 24
Finished Jun 25 05:01:24 PM PDT 24
Peak memory 206508 kb
Host smart-3b8cd82b-cef6-4dce-a184-8fb851eef6da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97628
0982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.976280982
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.4021081795
Short name T1852
Test name
Test status
Simulation time 197257262 ps
CPU time 0.89 seconds
Started Jun 25 05:01:21 PM PDT 24
Finished Jun 25 05:01:24 PM PDT 24
Peak memory 206516 kb
Host smart-b2964334-5c3c-4381-9f8b-47592be1ad8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40210
81795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.4021081795
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.351199650
Short name T1785
Test name
Test status
Simulation time 3227343780 ps
CPU time 84.22 seconds
Started Jun 25 05:01:19 PM PDT 24
Finished Jun 25 05:02:45 PM PDT 24
Peak memory 206920 kb
Host smart-a135fe04-651b-49c1-ac32-a3543226b7f6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=351199650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.351199650
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.930187005
Short name T893
Test name
Test status
Simulation time 168594993 ps
CPU time 0.79 seconds
Started Jun 25 05:01:24 PM PDT 24
Finished Jun 25 05:01:27 PM PDT 24
Peak memory 206572 kb
Host smart-13384b49-f29d-4b90-9016-2671c89cda5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93018
7005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.930187005
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.57139405
Short name T1578
Test name
Test status
Simulation time 185312442 ps
CPU time 0.86 seconds
Started Jun 25 05:01:21 PM PDT 24
Finished Jun 25 05:01:24 PM PDT 24
Peak memory 206580 kb
Host smart-01a4e469-fb20-4a18-82df-96a7b27da9f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57139
405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.57139405
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.834072112
Short name T649
Test name
Test status
Simulation time 4349117869 ps
CPU time 44.14 seconds
Started Jun 25 05:01:23 PM PDT 24
Finished Jun 25 05:02:09 PM PDT 24
Peak memory 206848 kb
Host smart-9e8be1ea-ebe1-4667-b2dd-737ac277ed14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83407
2112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.834072112
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.580779856
Short name T2428
Test name
Test status
Simulation time 3836609933 ps
CPU time 4.2 seconds
Started Jun 25 05:01:20 PM PDT 24
Finished Jun 25 05:01:26 PM PDT 24
Peak memory 206620 kb
Host smart-05249e90-0e23-41c7-9871-e780fec06686
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=580779856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.580779856
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.275470534
Short name T1132
Test name
Test status
Simulation time 13330850010 ps
CPU time 12.95 seconds
Started Jun 25 05:01:18 PM PDT 24
Finished Jun 25 05:01:33 PM PDT 24
Peak memory 206656 kb
Host smart-784317d5-2deb-4c52-b6d7-46bb9049b5ad
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=275470534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.275470534
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.1229016300
Short name T2009
Test name
Test status
Simulation time 23400279360 ps
CPU time 26.75 seconds
Started Jun 25 05:01:21 PM PDT 24
Finished Jun 25 05:01:50 PM PDT 24
Peak memory 206628 kb
Host smart-b5577d9d-ec48-4ca7-9961-807fe042103b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1229016300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.1229016300
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.4070378288
Short name T1214
Test name
Test status
Simulation time 157020655 ps
CPU time 0.84 seconds
Started Jun 25 05:01:19 PM PDT 24
Finished Jun 25 05:01:21 PM PDT 24
Peak memory 206516 kb
Host smart-51ba2b64-9aaa-4608-82bf-ae3ac846b08d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40703
78288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.4070378288
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.2790281368
Short name T1749
Test name
Test status
Simulation time 150853291 ps
CPU time 0.79 seconds
Started Jun 25 05:01:30 PM PDT 24
Finished Jun 25 05:01:32 PM PDT 24
Peak memory 206520 kb
Host smart-78c7a5b2-5eef-415a-acb8-9f0d36f46eb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27902
81368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.2790281368
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.2605369854
Short name T1629
Test name
Test status
Simulation time 346218764 ps
CPU time 1.2 seconds
Started Jun 25 05:01:21 PM PDT 24
Finished Jun 25 05:01:24 PM PDT 24
Peak memory 206588 kb
Host smart-9f7f8920-5b71-4e68-bcff-7e24a808672d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26053
69854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.2605369854
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.3723344496
Short name T2233
Test name
Test status
Simulation time 1320957661 ps
CPU time 2.9 seconds
Started Jun 25 05:01:21 PM PDT 24
Finished Jun 25 05:01:26 PM PDT 24
Peak memory 206844 kb
Host smart-eacc7fbc-1bb9-4681-a757-5f394a095a4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37233
44496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.3723344496
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.4199796487
Short name T1182
Test name
Test status
Simulation time 9210207726 ps
CPU time 20.76 seconds
Started Jun 25 05:01:22 PM PDT 24
Finished Jun 25 05:01:45 PM PDT 24
Peak memory 206932 kb
Host smart-4af1da7a-425f-4074-b8eb-479d2c95aaf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41997
96487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.4199796487
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.1394573328
Short name T1963
Test name
Test status
Simulation time 496671933 ps
CPU time 1.48 seconds
Started Jun 25 05:01:21 PM PDT 24
Finished Jun 25 05:01:25 PM PDT 24
Peak memory 206572 kb
Host smart-41878062-f64c-45e9-9de4-77f67d84b11f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13945
73328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.1394573328
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.3011783655
Short name T2344
Test name
Test status
Simulation time 138666596 ps
CPU time 0.77 seconds
Started Jun 25 05:01:21 PM PDT 24
Finished Jun 25 05:01:24 PM PDT 24
Peak memory 206568 kb
Host smart-6326d1fb-713a-4e05-873f-a7a9303681fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30117
83655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.3011783655
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.99297569
Short name T348
Test name
Test status
Simulation time 43416429 ps
CPU time 0.72 seconds
Started Jun 25 05:01:35 PM PDT 24
Finished Jun 25 05:01:39 PM PDT 24
Peak memory 205620 kb
Host smart-71214ffc-4106-437e-a007-5b9466a1d520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99297
569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.99297569
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.378096855
Short name T680
Test name
Test status
Simulation time 961085142 ps
CPU time 2.39 seconds
Started Jun 25 05:01:21 PM PDT 24
Finished Jun 25 05:01:26 PM PDT 24
Peak memory 206764 kb
Host smart-9b3f3205-7dd1-4ee5-b045-ad3e72ec23f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37809
6855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.378096855
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.1999981021
Short name T390
Test name
Test status
Simulation time 413649281 ps
CPU time 2.5 seconds
Started Jun 25 05:01:24 PM PDT 24
Finished Jun 25 05:01:28 PM PDT 24
Peak memory 206648 kb
Host smart-b9329722-c95c-4b21-b517-1774612f0370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19999
81021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.1999981021
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.2773165167
Short name T1243
Test name
Test status
Simulation time 246970965 ps
CPU time 0.93 seconds
Started Jun 25 05:01:30 PM PDT 24
Finished Jun 25 05:01:32 PM PDT 24
Peak memory 206568 kb
Host smart-eb977d3d-ce5a-4b12-babe-a612c70687d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27731
65167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.2773165167
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.907400532
Short name T1645
Test name
Test status
Simulation time 227582451 ps
CPU time 0.85 seconds
Started Jun 25 05:01:29 PM PDT 24
Finished Jun 25 05:01:31 PM PDT 24
Peak memory 206872 kb
Host smart-e54e81b8-0777-4a9c-933c-e17b2c0f2e5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90740
0532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.907400532
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.2048248215
Short name T1059
Test name
Test status
Simulation time 160267089 ps
CPU time 0.84 seconds
Started Jun 25 05:01:24 PM PDT 24
Finished Jun 25 05:01:27 PM PDT 24
Peak memory 206504 kb
Host smart-71a8ea80-78df-4f22-9ffa-3e29cfdc7bd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20482
48215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.2048248215
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.3066585592
Short name T2433
Test name
Test status
Simulation time 198177985 ps
CPU time 0.86 seconds
Started Jun 25 05:01:30 PM PDT 24
Finished Jun 25 05:01:33 PM PDT 24
Peak memory 206520 kb
Host smart-2a5592ab-cf32-4722-9b3f-693b0eb4192f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30665
85592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.3066585592
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.1996460482
Short name T2353
Test name
Test status
Simulation time 23265185123 ps
CPU time 23.46 seconds
Started Jun 25 05:01:26 PM PDT 24
Finished Jun 25 05:01:50 PM PDT 24
Peak memory 206692 kb
Host smart-676c6ec9-b271-43cd-a85c-db12abdbafdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19964
60482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.1996460482
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.3819306575
Short name T1899
Test name
Test status
Simulation time 3263839184 ps
CPU time 3.76 seconds
Started Jun 25 05:01:39 PM PDT 24
Finished Jun 25 05:01:44 PM PDT 24
Peak memory 206448 kb
Host smart-4bf1473e-6f25-4f2e-8fb8-708229f11afe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38193
06575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.3819306575
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.820773831
Short name T1218
Test name
Test status
Simulation time 3955812642 ps
CPU time 29.19 seconds
Started Jun 25 05:01:31 PM PDT 24
Finished Jun 25 05:02:01 PM PDT 24
Peak memory 206984 kb
Host smart-54d460f8-cccc-4b21-aae0-ed24f16684a8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=820773831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.820773831
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.2088454224
Short name T1702
Test name
Test status
Simulation time 242087423 ps
CPU time 0.95 seconds
Started Jun 25 05:01:36 PM PDT 24
Finished Jun 25 05:01:38 PM PDT 24
Peak memory 206580 kb
Host smart-2d0054c6-9485-4e9c-af2e-ef75e35e8460
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2088454224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.2088454224
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.2770173013
Short name T2288
Test name
Test status
Simulation time 251222304 ps
CPU time 0.99 seconds
Started Jun 25 05:01:23 PM PDT 24
Finished Jun 25 05:01:26 PM PDT 24
Peak memory 206456 kb
Host smart-b66afdb2-8053-4280-aec0-86555408be72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27701
73013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.2770173013
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.1505973911
Short name T1902
Test name
Test status
Simulation time 5544501077 ps
CPU time 52.05 seconds
Started Jun 25 05:01:32 PM PDT 24
Finished Jun 25 05:02:27 PM PDT 24
Peak memory 206892 kb
Host smart-10cf6ec5-c826-4795-ba73-45c78a9351e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15059
73911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.1505973911
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.2387223780
Short name T960
Test name
Test status
Simulation time 12715313350 ps
CPU time 351.58 seconds
Started Jun 25 05:01:30 PM PDT 24
Finished Jun 25 05:07:24 PM PDT 24
Peak memory 206956 kb
Host smart-6a26249f-0859-4444-a3b4-4bccdd660e49
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2387223780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.2387223780
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.383423782
Short name T2004
Test name
Test status
Simulation time 193054507 ps
CPU time 0.82 seconds
Started Jun 25 05:01:32 PM PDT 24
Finished Jun 25 05:01:35 PM PDT 24
Peak memory 206440 kb
Host smart-919079f0-1dd1-4a83-85f5-f37d66a8fe4c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=383423782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.383423782
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.2068921754
Short name T1071
Test name
Test status
Simulation time 145433435 ps
CPU time 0.82 seconds
Started Jun 25 05:01:31 PM PDT 24
Finished Jun 25 05:01:34 PM PDT 24
Peak memory 206524 kb
Host smart-8ac0f40f-2e30-48a1-a352-3127bdd1358e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20689
21754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.2068921754
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.2477962723
Short name T127
Test name
Test status
Simulation time 220143581 ps
CPU time 0.9 seconds
Started Jun 25 05:01:29 PM PDT 24
Finished Jun 25 05:01:30 PM PDT 24
Peak memory 206572 kb
Host smart-22a5807a-5a04-41cb-986a-5d0946f7a727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24779
62723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.2477962723
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.2503233941
Short name T101
Test name
Test status
Simulation time 171445532 ps
CPU time 0.82 seconds
Started Jun 25 05:01:32 PM PDT 24
Finished Jun 25 05:01:36 PM PDT 24
Peak memory 206588 kb
Host smart-38efdde6-ca3d-4d69-bb4f-34bac7caa0dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25032
33941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.2503233941
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.3446770289
Short name T832
Test name
Test status
Simulation time 179803748 ps
CPU time 0.8 seconds
Started Jun 25 05:01:32 PM PDT 24
Finished Jun 25 05:01:36 PM PDT 24
Peak memory 206572 kb
Host smart-a13d66c3-f042-4727-8575-e2fee5d2f9e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34467
70289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.3446770289
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.2778314657
Short name T2014
Test name
Test status
Simulation time 179690133 ps
CPU time 0.84 seconds
Started Jun 25 05:01:30 PM PDT 24
Finished Jun 25 05:01:32 PM PDT 24
Peak memory 206496 kb
Host smart-e1973d88-b2dc-46c0-9205-68c5d7b9b29d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27783
14657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.2778314657
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.171403592
Short name T2060
Test name
Test status
Simulation time 184664179 ps
CPU time 0.83 seconds
Started Jun 25 05:01:29 PM PDT 24
Finished Jun 25 05:01:31 PM PDT 24
Peak memory 206540 kb
Host smart-dd92af2a-5e47-492a-ad06-5b3f680c8ed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17140
3592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.171403592
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.1583228403
Short name T2007
Test name
Test status
Simulation time 234463169 ps
CPU time 0.95 seconds
Started Jun 25 05:01:30 PM PDT 24
Finished Jun 25 05:01:33 PM PDT 24
Peak memory 206592 kb
Host smart-e663e89b-1eb5-4eca-a328-8f037fbbd577
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1583228403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.1583228403
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.1568805033
Short name T986
Test name
Test status
Simulation time 144766599 ps
CPU time 0.76 seconds
Started Jun 25 05:01:29 PM PDT 24
Finished Jun 25 05:01:31 PM PDT 24
Peak memory 206560 kb
Host smart-6af4dd48-db6d-46c5-8d66-250d2ee8a1fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15688
05033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.1568805033
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.207665470
Short name T1177
Test name
Test status
Simulation time 35411737 ps
CPU time 0.66 seconds
Started Jun 25 05:01:30 PM PDT 24
Finished Jun 25 05:01:32 PM PDT 24
Peak memory 206504 kb
Host smart-712995f5-200b-4dee-a25d-be9b1f4fcf00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20766
5470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.207665470
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.1172786994
Short name T464
Test name
Test status
Simulation time 151826232 ps
CPU time 0.81 seconds
Started Jun 25 05:01:31 PM PDT 24
Finished Jun 25 05:01:33 PM PDT 24
Peak memory 206572 kb
Host smart-67a6ed79-8a5e-4f5f-bdd1-51a834500aca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11727
86994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.1172786994
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.2936323922
Short name T1644
Test name
Test status
Simulation time 167303291 ps
CPU time 0.82 seconds
Started Jun 25 05:01:39 PM PDT 24
Finished Jun 25 05:01:42 PM PDT 24
Peak memory 206404 kb
Host smart-59dd1deb-588a-414a-a5b7-055029e95766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29363
23922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.2936323922
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.3621289094
Short name T918
Test name
Test status
Simulation time 229820067 ps
CPU time 0.96 seconds
Started Jun 25 05:01:40 PM PDT 24
Finished Jun 25 05:01:44 PM PDT 24
Peak memory 206448 kb
Host smart-f3599826-5de0-4865-9ec5-e9eabc8373df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36212
89094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.3621289094
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.2453470299
Short name T442
Test name
Test status
Simulation time 188570129 ps
CPU time 0.82 seconds
Started Jun 25 05:01:32 PM PDT 24
Finished Jun 25 05:01:35 PM PDT 24
Peak memory 206536 kb
Host smart-9a1c4757-d419-4fda-8100-c73ed5aaa295
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24534
70299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.2453470299
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.3410781775
Short name T1007
Test name
Test status
Simulation time 189142759 ps
CPU time 0.86 seconds
Started Jun 25 05:01:33 PM PDT 24
Finished Jun 25 05:01:37 PM PDT 24
Peak memory 206576 kb
Host smart-da423933-c99b-459c-8a09-967249515f2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34107
81775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.3410781775
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.1118256005
Short name T1117
Test name
Test status
Simulation time 155851783 ps
CPU time 0.77 seconds
Started Jun 25 05:01:35 PM PDT 24
Finished Jun 25 05:01:38 PM PDT 24
Peak memory 206576 kb
Host smart-f7c809fc-7306-4b9f-8f35-820b467ca7cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11182
56005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.1118256005
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.2475458076
Short name T2064
Test name
Test status
Simulation time 159256951 ps
CPU time 0.79 seconds
Started Jun 25 05:01:34 PM PDT 24
Finished Jun 25 05:01:38 PM PDT 24
Peak memory 206580 kb
Host smart-24c4b4cb-5611-4026-8533-ec350364f393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24754
58076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.2475458076
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.3226058042
Short name T2289
Test name
Test status
Simulation time 221786803 ps
CPU time 0.96 seconds
Started Jun 25 05:01:33 PM PDT 24
Finished Jun 25 05:01:37 PM PDT 24
Peak memory 206584 kb
Host smart-ccb6f98b-60bb-4a5a-b546-c508f7451802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32260
58042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.3226058042
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.1252682241
Short name T1691
Test name
Test status
Simulation time 13134229862 ps
CPU time 126.42 seconds
Started Jun 25 05:01:32 PM PDT 24
Finished Jun 25 05:03:42 PM PDT 24
Peak memory 206852 kb
Host smart-693ada79-55e8-4d8e-9402-5d4d9dc14be4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1252682241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.1252682241
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.3817017284
Short name T1874
Test name
Test status
Simulation time 191725275 ps
CPU time 0.88 seconds
Started Jun 25 05:01:32 PM PDT 24
Finished Jun 25 05:01:36 PM PDT 24
Peak memory 206576 kb
Host smart-2bb849a4-8446-461f-82f1-511956b1ac93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38170
17284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.3817017284
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.2636440913
Short name T841
Test name
Test status
Simulation time 146803728 ps
CPU time 0.75 seconds
Started Jun 25 05:01:32 PM PDT 24
Finished Jun 25 05:01:36 PM PDT 24
Peak memory 206572 kb
Host smart-e49154e3-23a5-42c3-8093-0d4375a1eaf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26364
40913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.2636440913
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.4077340426
Short name T1386
Test name
Test status
Simulation time 5830196769 ps
CPU time 55.16 seconds
Started Jun 25 05:01:29 PM PDT 24
Finished Jun 25 05:02:25 PM PDT 24
Peak memory 206764 kb
Host smart-090d69d3-b2a6-45b4-bc59-052a6f709b70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40773
40426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.4077340426
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.586809424
Short name T185
Test name
Test status
Simulation time 3569947612 ps
CPU time 4.01 seconds
Started Jun 25 05:01:32 PM PDT 24
Finished Jun 25 05:01:38 PM PDT 24
Peak memory 206564 kb
Host smart-480ac535-aebc-4d14-b193-600f1469e42a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=586809424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.586809424
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.510488681
Short name T220
Test name
Test status
Simulation time 13385128269 ps
CPU time 13.19 seconds
Started Jun 25 05:01:29 PM PDT 24
Finished Jun 25 05:01:43 PM PDT 24
Peak memory 206816 kb
Host smart-09d1b2ac-7137-4d0a-be29-d175d8faf83e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=510488681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.510488681
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.959372615
Short name T1737
Test name
Test status
Simulation time 23384254548 ps
CPU time 20.84 seconds
Started Jun 25 05:01:28 PM PDT 24
Finished Jun 25 05:01:50 PM PDT 24
Peak memory 206896 kb
Host smart-13932d36-3b17-4b53-8f23-3b83e36a4717
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=959372615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.959372615
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.1381081532
Short name T1921
Test name
Test status
Simulation time 166084770 ps
CPU time 0.83 seconds
Started Jun 25 05:01:30 PM PDT 24
Finished Jun 25 05:01:32 PM PDT 24
Peak memory 206580 kb
Host smart-815256f1-3857-478b-a857-9aa6af8b2bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13810
81532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.1381081532
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.2458669136
Short name T659
Test name
Test status
Simulation time 202791892 ps
CPU time 0.8 seconds
Started Jun 25 05:01:30 PM PDT 24
Finished Jun 25 05:01:32 PM PDT 24
Peak memory 206592 kb
Host smart-fcefbd77-272c-4239-9c60-a9587d27d324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24586
69136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.2458669136
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.3376042445
Short name T1995
Test name
Test status
Simulation time 482047616 ps
CPU time 1.61 seconds
Started Jun 25 05:01:33 PM PDT 24
Finished Jun 25 05:01:38 PM PDT 24
Peak memory 206596 kb
Host smart-2cb01133-9657-4f86-94e3-8e919368214e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33760
42445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.3376042445
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_device_address.3997779479
Short name T2017
Test name
Test status
Simulation time 10928376453 ps
CPU time 21.86 seconds
Started Jun 25 05:01:31 PM PDT 24
Finished Jun 25 05:01:55 PM PDT 24
Peak memory 206944 kb
Host smart-a160bf0a-5a90-4eb2-9c68-c6fdaec2846b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39977
79479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.3997779479
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.1366953720
Short name T1807
Test name
Test status
Simulation time 439903355 ps
CPU time 1.34 seconds
Started Jun 25 05:01:31 PM PDT 24
Finished Jun 25 05:01:35 PM PDT 24
Peak memory 206500 kb
Host smart-e079a4f5-291f-46a1-92aa-418f9fab1530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13669
53720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.1366953720
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.4131674273
Short name T1524
Test name
Test status
Simulation time 138378899 ps
CPU time 0.82 seconds
Started Jun 25 05:01:32 PM PDT 24
Finished Jun 25 05:01:35 PM PDT 24
Peak memory 206496 kb
Host smart-3cc8732b-90d0-4187-a4a9-d44d428ae71e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41316
74273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.4131674273
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.3496071999
Short name T752
Test name
Test status
Simulation time 40801456 ps
CPU time 0.68 seconds
Started Jun 25 05:01:32 PM PDT 24
Finished Jun 25 05:01:36 PM PDT 24
Peak memory 206556 kb
Host smart-e302f4df-f94e-402c-81c4-02e1b24b8b4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34960
71999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.3496071999
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.1770059232
Short name T426
Test name
Test status
Simulation time 946909296 ps
CPU time 2.15 seconds
Started Jun 25 05:01:34 PM PDT 24
Finished Jun 25 05:01:39 PM PDT 24
Peak memory 206720 kb
Host smart-83700eda-7127-49b7-8a38-8afeb7b04064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17700
59232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.1770059232
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.501432065
Short name T2210
Test name
Test status
Simulation time 341450809 ps
CPU time 2.18 seconds
Started Jun 25 05:01:30 PM PDT 24
Finished Jun 25 05:01:33 PM PDT 24
Peak memory 206760 kb
Host smart-aefa0714-0720-4d0d-8e7e-9bb0f3514c14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50143
2065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.501432065
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.2321605833
Short name T114
Test name
Test status
Simulation time 281524538 ps
CPU time 1.05 seconds
Started Jun 25 05:01:40 PM PDT 24
Finished Jun 25 05:01:43 PM PDT 24
Peak memory 206584 kb
Host smart-56ce4228-095f-4692-a00f-5d93111892f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23216
05833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.2321605833
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.1960345224
Short name T1235
Test name
Test status
Simulation time 168030120 ps
CPU time 0.79 seconds
Started Jun 25 05:01:39 PM PDT 24
Finished Jun 25 05:01:42 PM PDT 24
Peak memory 206568 kb
Host smart-37f0c8a1-f762-4966-a96d-871ac644ed85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19603
45224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.1960345224
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.1124696466
Short name T1017
Test name
Test status
Simulation time 240140266 ps
CPU time 0.97 seconds
Started Jun 25 05:01:31 PM PDT 24
Finished Jun 25 05:01:34 PM PDT 24
Peak memory 206572 kb
Host smart-e5569267-b708-4657-89a4-728fad885486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11246
96466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.1124696466
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.2244075763
Short name T1081
Test name
Test status
Simulation time 196150732 ps
CPU time 0.86 seconds
Started Jun 25 05:01:39 PM PDT 24
Finished Jun 25 05:01:42 PM PDT 24
Peak memory 206380 kb
Host smart-70d2c333-c4b9-4646-ad05-fc002d9b3b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22440
75763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.2244075763
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.310357541
Short name T1696
Test name
Test status
Simulation time 23272755871 ps
CPU time 22.94 seconds
Started Jun 25 05:01:34 PM PDT 24
Finished Jun 25 05:02:00 PM PDT 24
Peak memory 206692 kb
Host smart-1e889d8b-d24b-47ff-a04d-22c53cb6b51e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31035
7541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.310357541
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.1057814064
Short name T1031
Test name
Test status
Simulation time 3291490105 ps
CPU time 4.3 seconds
Started Jun 25 05:01:31 PM PDT 24
Finished Jun 25 05:01:37 PM PDT 24
Peak memory 206600 kb
Host smart-f1ad1b6f-1d39-4227-a112-915a01c627f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10578
14064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.1057814064
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.3443841039
Short name T2271
Test name
Test status
Simulation time 15053825157 ps
CPU time 421.69 seconds
Started Jun 25 05:01:32 PM PDT 24
Finished Jun 25 05:08:36 PM PDT 24
Peak memory 206860 kb
Host smart-690d80ba-42eb-4ef7-a405-cb83ac457598
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3443841039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.3443841039
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.3599925071
Short name T977
Test name
Test status
Simulation time 257113023 ps
CPU time 0.96 seconds
Started Jun 25 05:01:37 PM PDT 24
Finished Jun 25 05:01:39 PM PDT 24
Peak memory 206576 kb
Host smart-e4e3742e-4191-436a-a1fa-ff528a8b526d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3599925071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.3599925071
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.1306697734
Short name T349
Test name
Test status
Simulation time 193594837 ps
CPU time 0.85 seconds
Started Jun 25 05:01:32 PM PDT 24
Finished Jun 25 05:01:35 PM PDT 24
Peak memory 206536 kb
Host smart-7a97fba9-0367-4dab-87df-79312f4147eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13066
97734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.1306697734
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.87657113
Short name T151
Test name
Test status
Simulation time 10806964070 ps
CPU time 75.85 seconds
Started Jun 25 05:01:31 PM PDT 24
Finished Jun 25 05:02:50 PM PDT 24
Peak memory 206884 kb
Host smart-4588ec2c-bb03-4efb-910d-e9d3345dc06a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87657
113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.87657113
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.220870099
Short name T1718
Test name
Test status
Simulation time 6497289425 ps
CPU time 46.56 seconds
Started Jun 25 05:01:32 PM PDT 24
Finished Jun 25 05:02:21 PM PDT 24
Peak memory 206948 kb
Host smart-ea4b7a62-903a-4eaa-bd0b-b942bcd68682
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=220870099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.220870099
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.3168565579
Short name T1186
Test name
Test status
Simulation time 146496865 ps
CPU time 0.8 seconds
Started Jun 25 05:01:37 PM PDT 24
Finished Jun 25 05:01:40 PM PDT 24
Peak memory 206496 kb
Host smart-60113d13-416e-4673-914c-3666aec085f5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3168565579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.3168565579
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.4050764268
Short name T2066
Test name
Test status
Simulation time 156660573 ps
CPU time 0.76 seconds
Started Jun 25 05:01:34 PM PDT 24
Finished Jun 25 05:01:38 PM PDT 24
Peak memory 206580 kb
Host smart-14cc258f-23c1-4830-a2d3-1cf88a46b4dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40507
64268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.4050764268
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.3368349673
Short name T1731
Test name
Test status
Simulation time 209417809 ps
CPU time 0.87 seconds
Started Jun 25 05:01:32 PM PDT 24
Finished Jun 25 05:01:36 PM PDT 24
Peak memory 206580 kb
Host smart-c961547a-bf2e-4732-8793-531057eda35f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33683
49673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.3368349673
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.3876686411
Short name T462
Test name
Test status
Simulation time 194736829 ps
CPU time 0.83 seconds
Started Jun 25 05:01:39 PM PDT 24
Finished Jun 25 05:01:42 PM PDT 24
Peak memory 206428 kb
Host smart-74d2644e-c15b-4950-8d7b-40c6fdb0f686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38766
86411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.3876686411
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.1763337518
Short name T1315
Test name
Test status
Simulation time 163568385 ps
CPU time 0.8 seconds
Started Jun 25 05:01:32 PM PDT 24
Finished Jun 25 05:01:36 PM PDT 24
Peak memory 206572 kb
Host smart-78330c28-e5e7-46a4-9faf-20ca572c7c75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17633
37518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.1763337518
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.2167093823
Short name T300
Test name
Test status
Simulation time 201926105 ps
CPU time 0.82 seconds
Started Jun 25 05:01:33 PM PDT 24
Finished Jun 25 05:01:37 PM PDT 24
Peak memory 206752 kb
Host smart-939dffe0-d411-4bd0-9ab7-427c58f79142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21670
93823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.2167093823
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.460566416
Short name T2474
Test name
Test status
Simulation time 167868947 ps
CPU time 0.81 seconds
Started Jun 25 05:01:42 PM PDT 24
Finished Jun 25 05:01:44 PM PDT 24
Peak memory 206504 kb
Host smart-be9459bb-b3a6-4c19-968c-a7ce4f8bf183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46056
6416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.460566416
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.1221007722
Short name T545
Test name
Test status
Simulation time 207081369 ps
CPU time 0.92 seconds
Started Jun 25 05:01:33 PM PDT 24
Finished Jun 25 05:01:37 PM PDT 24
Peak memory 206604 kb
Host smart-37e3f048-b2e1-41ec-8a2d-f617c1ebcfd3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1221007722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.1221007722
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.1414573341
Short name T189
Test name
Test status
Simulation time 150678506 ps
CPU time 0.83 seconds
Started Jun 25 05:01:31 PM PDT 24
Finished Jun 25 05:01:34 PM PDT 24
Peak memory 206520 kb
Host smart-3e6ac410-43cd-4f34-a254-5362568b766f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14145
73341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.1414573341
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.4100057142
Short name T709
Test name
Test status
Simulation time 40011048 ps
CPU time 0.67 seconds
Started Jun 25 05:01:41 PM PDT 24
Finished Jun 25 05:01:44 PM PDT 24
Peak memory 206492 kb
Host smart-63d5d3d7-0cb1-41a0-8708-aa16f761fec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41000
57142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.4100057142
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.664924949
Short name T238
Test name
Test status
Simulation time 8465476004 ps
CPU time 17.78 seconds
Started Jun 25 05:01:32 PM PDT 24
Finished Jun 25 05:01:52 PM PDT 24
Peak memory 206972 kb
Host smart-40f99f54-497b-448f-98ee-02171f331efe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66492
4949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.664924949
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.2243002566
Short name T403
Test name
Test status
Simulation time 162141337 ps
CPU time 0.83 seconds
Started Jun 25 05:01:31 PM PDT 24
Finished Jun 25 05:01:34 PM PDT 24
Peak memory 206492 kb
Host smart-7a9cd36b-9c4d-45fb-880a-dfd82fef62b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22430
02566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.2243002566
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.1298257951
Short name T1111
Test name
Test status
Simulation time 213094236 ps
CPU time 0.89 seconds
Started Jun 25 05:01:39 PM PDT 24
Finished Jun 25 05:01:42 PM PDT 24
Peak memory 206600 kb
Host smart-71edd1ef-297c-444f-8bbd-1794671e1d81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12982
57951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.1298257951
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.15811981
Short name T1036
Test name
Test status
Simulation time 210948034 ps
CPU time 0.9 seconds
Started Jun 25 05:01:44 PM PDT 24
Finished Jun 25 05:01:46 PM PDT 24
Peak memory 206592 kb
Host smart-982e0150-19a9-4723-8c27-8b1eb882eee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15811
981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.15811981
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.3714744100
Short name T1966
Test name
Test status
Simulation time 229766252 ps
CPU time 0.87 seconds
Started Jun 25 05:01:37 PM PDT 24
Finished Jun 25 05:01:40 PM PDT 24
Peak memory 206588 kb
Host smart-00823b1f-d1de-484d-9770-5b6640f24742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37147
44100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.3714744100
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.973001857
Short name T1856
Test name
Test status
Simulation time 146534114 ps
CPU time 0.74 seconds
Started Jun 25 05:01:44 PM PDT 24
Finished Jun 25 05:01:46 PM PDT 24
Peak memory 206520 kb
Host smart-289d1308-2075-400d-9419-83217819b780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97300
1857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.973001857
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.315412238
Short name T1067
Test name
Test status
Simulation time 150529287 ps
CPU time 0.83 seconds
Started Jun 25 05:01:39 PM PDT 24
Finished Jun 25 05:01:42 PM PDT 24
Peak memory 206596 kb
Host smart-381bd2f1-7133-4a85-85b7-1e1e1610ae7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31541
2238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.315412238
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.1829481452
Short name T1864
Test name
Test status
Simulation time 149119097 ps
CPU time 0.84 seconds
Started Jun 25 05:01:38 PM PDT 24
Finished Jun 25 05:01:41 PM PDT 24
Peak memory 206508 kb
Host smart-dd36d7dd-c1a9-4ee8-a72e-131f5bbc35e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18294
81452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.1829481452
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.1843024094
Short name T549
Test name
Test status
Simulation time 257151948 ps
CPU time 1.04 seconds
Started Jun 25 05:01:38 PM PDT 24
Finished Jun 25 05:01:41 PM PDT 24
Peak memory 206584 kb
Host smart-9026f5ac-6c03-4cd1-aadd-587d549c7572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18430
24094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.1843024094
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.1338662086
Short name T831
Test name
Test status
Simulation time 12119481714 ps
CPU time 87.42 seconds
Started Jun 25 05:01:38 PM PDT 24
Finished Jun 25 05:03:07 PM PDT 24
Peak memory 206868 kb
Host smart-8e4f1362-e1eb-403d-8ef7-7bb22bafdc33
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1338662086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.1338662086
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.1467243706
Short name T482
Test name
Test status
Simulation time 198804334 ps
CPU time 0.82 seconds
Started Jun 25 05:01:38 PM PDT 24
Finished Jun 25 05:01:40 PM PDT 24
Peak memory 206584 kb
Host smart-b0cf6dc3-b096-43c4-979a-80fa651b9d73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14672
43706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.1467243706
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.706650479
Short name T347
Test name
Test status
Simulation time 175001615 ps
CPU time 0.85 seconds
Started Jun 25 05:01:40 PM PDT 24
Finished Jun 25 05:01:43 PM PDT 24
Peak memory 206508 kb
Host smart-cbd6957f-7e11-49d3-9940-1d3205033149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70665
0479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.706650479
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.4155809817
Short name T877
Test name
Test status
Simulation time 4592830555 ps
CPU time 131.02 seconds
Started Jun 25 05:01:38 PM PDT 24
Finished Jun 25 05:03:51 PM PDT 24
Peak memory 206944 kb
Host smart-1933c39c-5a44-4ecd-827f-a910a11d00a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41558
09817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.4155809817
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.846801895
Short name T2262
Test name
Test status
Simulation time 3946625885 ps
CPU time 4.97 seconds
Started Jun 25 05:01:39 PM PDT 24
Finished Jun 25 05:01:47 PM PDT 24
Peak memory 206628 kb
Host smart-082ec2a3-9b72-46f8-935f-1e1d58721001
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=846801895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.846801895
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.2591397021
Short name T536
Test name
Test status
Simulation time 13379600234 ps
CPU time 12.52 seconds
Started Jun 25 05:01:38 PM PDT 24
Finished Jun 25 05:01:53 PM PDT 24
Peak memory 206716 kb
Host smart-fffe5876-e2c5-4de1-9e99-75376068793a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2591397021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.2591397021
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.440143254
Short name T1740
Test name
Test status
Simulation time 23417375991 ps
CPU time 26.75 seconds
Started Jun 25 05:01:37 PM PDT 24
Finished Jun 25 05:02:06 PM PDT 24
Peak memory 206716 kb
Host smart-4e5ab357-d250-4f05-9431-7da986ed4c62
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=440143254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.440143254
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.3166223834
Short name T811
Test name
Test status
Simulation time 153067869 ps
CPU time 0.79 seconds
Started Jun 25 05:01:39 PM PDT 24
Finished Jun 25 05:01:42 PM PDT 24
Peak memory 206508 kb
Host smart-5a1c6cc8-8ed3-48f9-b8a1-c5fd7b061796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31662
23834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.3166223834
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.3437371539
Short name T1372
Test name
Test status
Simulation time 162746924 ps
CPU time 0.83 seconds
Started Jun 25 05:01:38 PM PDT 24
Finished Jun 25 05:01:41 PM PDT 24
Peak memory 206568 kb
Host smart-39e7d2e9-413a-4690-b83e-11c115fd89d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34373
71539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.3437371539
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.2761123976
Short name T1347
Test name
Test status
Simulation time 155731416 ps
CPU time 0.78 seconds
Started Jun 25 05:01:36 PM PDT 24
Finished Jun 25 05:01:38 PM PDT 24
Peak memory 206596 kb
Host smart-fc97c41c-4af7-4705-bd15-a55ecc458484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27611
23976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.2761123976
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.3426482499
Short name T1554
Test name
Test status
Simulation time 1091462193 ps
CPU time 2.3 seconds
Started Jun 25 05:01:37 PM PDT 24
Finished Jun 25 05:01:41 PM PDT 24
Peak memory 206712 kb
Host smart-4ce8fdd0-3210-44d6-acf2-a6fa2c42731a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34264
82499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.3426482499
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.1465593657
Short name T1148
Test name
Test status
Simulation time 15056151551 ps
CPU time 29.37 seconds
Started Jun 25 05:01:41 PM PDT 24
Finished Jun 25 05:02:13 PM PDT 24
Peak memory 206864 kb
Host smart-b751fa01-83a5-4cd7-b0b3-5caa12a7c265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14655
93657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.1465593657
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.2398133845
Short name T2395
Test name
Test status
Simulation time 329199472 ps
CPU time 1.18 seconds
Started Jun 25 05:01:38 PM PDT 24
Finished Jun 25 05:01:42 PM PDT 24
Peak memory 206572 kb
Host smart-08094673-06b3-4dd6-8634-2c0940636d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23981
33845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.2398133845
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.1267477276
Short name T1765
Test name
Test status
Simulation time 144696265 ps
CPU time 0.78 seconds
Started Jun 25 05:01:48 PM PDT 24
Finished Jun 25 05:01:50 PM PDT 24
Peak memory 206592 kb
Host smart-5aafca64-9616-49cb-b9cb-36b2a7e8573a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12674
77276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.1267477276
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.2303289608
Short name T1181
Test name
Test status
Simulation time 38487927 ps
CPU time 0.72 seconds
Started Jun 25 05:01:39 PM PDT 24
Finished Jun 25 05:01:42 PM PDT 24
Peak memory 206396 kb
Host smart-07824d2e-6f0a-46f3-bdce-24685c9adcf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23032
89608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.2303289608
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.3865853311
Short name T405
Test name
Test status
Simulation time 803182312 ps
CPU time 2.07 seconds
Started Jun 25 05:01:38 PM PDT 24
Finished Jun 25 05:01:42 PM PDT 24
Peak memory 206712 kb
Host smart-913aba6e-2bcb-4cb4-9ef9-7a3fe552e4f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38658
53311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.3865853311
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.1490452148
Short name T966
Test name
Test status
Simulation time 328164792 ps
CPU time 2.07 seconds
Started Jun 25 05:01:39 PM PDT 24
Finished Jun 25 05:01:44 PM PDT 24
Peak memory 206580 kb
Host smart-c12c6ded-c1b4-4f29-9b55-52d0c5b928b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14904
52148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.1490452148
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.2442341094
Short name T1751
Test name
Test status
Simulation time 224430741 ps
CPU time 0.92 seconds
Started Jun 25 05:01:49 PM PDT 24
Finished Jun 25 05:01:52 PM PDT 24
Peak memory 206564 kb
Host smart-96308d33-4c2c-4cfd-be52-f39f7169cf11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24423
41094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.2442341094
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.4053697042
Short name T407
Test name
Test status
Simulation time 171555739 ps
CPU time 0.77 seconds
Started Jun 25 05:01:50 PM PDT 24
Finished Jun 25 05:01:52 PM PDT 24
Peak memory 206576 kb
Host smart-e3a6089d-75bb-4a7b-ad6d-336a759d751a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40536
97042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.4053697042
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.302318822
Short name T1817
Test name
Test status
Simulation time 185346052 ps
CPU time 0.85 seconds
Started Jun 25 05:01:44 PM PDT 24
Finished Jun 25 05:01:46 PM PDT 24
Peak memory 206564 kb
Host smart-4ebc72b6-ca18-4496-a4ba-75f3d72f3e59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30231
8822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.302318822
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_invalid_sync.2677758725
Short name T798
Test name
Test status
Simulation time 13397570911 ps
CPU time 97.15 seconds
Started Jun 25 05:01:38 PM PDT 24
Finished Jun 25 05:03:16 PM PDT 24
Peak memory 206948 kb
Host smart-02e8bb6d-8c3b-4af3-a355-818b35a0794f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2677758725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.2677758725
Directory /workspace/35.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.4134647376
Short name T539
Test name
Test status
Simulation time 205950962 ps
CPU time 0.87 seconds
Started Jun 25 05:01:41 PM PDT 24
Finished Jun 25 05:01:44 PM PDT 24
Peak memory 206504 kb
Host smart-da621e1b-5837-4a96-9f26-1a87df456660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41346
47376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.4134647376
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.4231963931
Short name T843
Test name
Test status
Simulation time 23380639419 ps
CPU time 24.75 seconds
Started Jun 25 05:01:42 PM PDT 24
Finished Jun 25 05:02:08 PM PDT 24
Peak memory 206712 kb
Host smart-fb12559b-66db-4b36-bfe3-6a3a35ca111a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42319
63931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.4231963931
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.1956254424
Short name T1766
Test name
Test status
Simulation time 3337243231 ps
CPU time 3.76 seconds
Started Jun 25 05:01:41 PM PDT 24
Finished Jun 25 05:01:47 PM PDT 24
Peak memory 206624 kb
Host smart-1b740555-54c7-4713-ab24-77676f856a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19562
54424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.1956254424
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.504807417
Short name T813
Test name
Test status
Simulation time 4482885156 ps
CPU time 128.2 seconds
Started Jun 25 05:01:38 PM PDT 24
Finished Jun 25 05:03:49 PM PDT 24
Peak memory 206944 kb
Host smart-8631c00e-e555-41ac-856d-e5a6dae8cda5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=504807417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.504807417
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.3873983865
Short name T1894
Test name
Test status
Simulation time 286815817 ps
CPU time 0.96 seconds
Started Jun 25 05:01:47 PM PDT 24
Finished Jun 25 05:01:49 PM PDT 24
Peak memory 206584 kb
Host smart-ae2a9ee7-faba-4f8f-a378-ec8247c613de
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3873983865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.3873983865
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.3908164540
Short name T2196
Test name
Test status
Simulation time 193604646 ps
CPU time 0.9 seconds
Started Jun 25 05:01:38 PM PDT 24
Finished Jun 25 05:01:41 PM PDT 24
Peak memory 206576 kb
Host smart-f7d74bec-c803-4af1-8934-85531557189e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39081
64540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.3908164540
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.2605828119
Short name T1332
Test name
Test status
Simulation time 10505330381 ps
CPU time 78.69 seconds
Started Jun 25 05:01:38 PM PDT 24
Finished Jun 25 05:02:59 PM PDT 24
Peak memory 207112 kb
Host smart-05dcb0b1-4feb-4e51-9514-e759e2fb104f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26058
28119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.2605828119
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.458209197
Short name T1584
Test name
Test status
Simulation time 5453491528 ps
CPU time 36.38 seconds
Started Jun 25 05:01:43 PM PDT 24
Finished Jun 25 05:02:21 PM PDT 24
Peak memory 206956 kb
Host smart-a8887e49-0799-4eba-970a-566de5158fc9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=458209197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.458209197
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.3700335802
Short name T921
Test name
Test status
Simulation time 156526876 ps
CPU time 0.8 seconds
Started Jun 25 05:01:49 PM PDT 24
Finished Jun 25 05:01:51 PM PDT 24
Peak memory 206572 kb
Host smart-77afc04c-1b5d-4642-8e30-ca762e998696
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3700335802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.3700335802
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.3415285082
Short name T614
Test name
Test status
Simulation time 154241518 ps
CPU time 0.79 seconds
Started Jun 25 05:01:37 PM PDT 24
Finished Jun 25 05:01:40 PM PDT 24
Peak memory 206568 kb
Host smart-ce6a4f55-904e-4bf0-a401-32aa624b5815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34152
85082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.3415285082
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.634428480
Short name T130
Test name
Test status
Simulation time 176665001 ps
CPU time 0.83 seconds
Started Jun 25 05:01:39 PM PDT 24
Finished Jun 25 05:01:42 PM PDT 24
Peak memory 206508 kb
Host smart-dde84ea3-5247-407c-91ff-ca5edd183c79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63442
8480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.634428480
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.575408214
Short name T2130
Test name
Test status
Simulation time 160171514 ps
CPU time 0.82 seconds
Started Jun 25 05:01:42 PM PDT 24
Finished Jun 25 05:01:44 PM PDT 24
Peak memory 206584 kb
Host smart-e044501c-57ca-4726-8d00-961e9e23f06d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57540
8214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.575408214
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.2143844178
Short name T2164
Test name
Test status
Simulation time 166649092 ps
CPU time 0.88 seconds
Started Jun 25 05:01:40 PM PDT 24
Finished Jun 25 05:01:44 PM PDT 24
Peak memory 206504 kb
Host smart-0b82e8f9-049a-49bf-9f97-1bab4ac954b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21438
44178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.2143844178
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.3498582861
Short name T722
Test name
Test status
Simulation time 167176273 ps
CPU time 0.81 seconds
Started Jun 25 05:01:39 PM PDT 24
Finished Jun 25 05:01:42 PM PDT 24
Peak memory 206756 kb
Host smart-3c012db3-f897-45be-8725-93ab82fb0a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34985
82861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.3498582861
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.1836268432
Short name T1507
Test name
Test status
Simulation time 151288463 ps
CPU time 0.82 seconds
Started Jun 25 05:01:48 PM PDT 24
Finished Jun 25 05:01:50 PM PDT 24
Peak memory 206496 kb
Host smart-1266a232-e79d-419c-a9db-7e58428f20a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18362
68432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.1836268432
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.1857916680
Short name T1143
Test name
Test status
Simulation time 193623941 ps
CPU time 0.83 seconds
Started Jun 25 05:01:44 PM PDT 24
Finished Jun 25 05:01:46 PM PDT 24
Peak memory 206492 kb
Host smart-66c8e1c7-bb7e-42da-b7d0-ad0df88ca89b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1857916680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.1857916680
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.3074337969
Short name T1223
Test name
Test status
Simulation time 155605138 ps
CPU time 0.74 seconds
Started Jun 25 05:01:39 PM PDT 24
Finished Jun 25 05:01:42 PM PDT 24
Peak memory 206496 kb
Host smart-92843c94-92be-4fd8-89f6-52dd3c5ead37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30743
37969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.3074337969
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.4116648694
Short name T410
Test name
Test status
Simulation time 42952016 ps
CPU time 0.67 seconds
Started Jun 25 05:01:53 PM PDT 24
Finished Jun 25 05:01:54 PM PDT 24
Peak memory 206596 kb
Host smart-ab631122-e6d6-4530-9dc9-9b53cccd7d07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41166
48694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.4116648694
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.3298233978
Short name T237
Test name
Test status
Simulation time 10564957299 ps
CPU time 23.51 seconds
Started Jun 25 05:01:36 PM PDT 24
Finished Jun 25 05:02:01 PM PDT 24
Peak memory 206884 kb
Host smart-a7f7c7f8-df3c-4d1a-92c6-07b69078278a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32982
33978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.3298233978
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.2775312559
Short name T1957
Test name
Test status
Simulation time 157631393 ps
CPU time 0.84 seconds
Started Jun 25 05:01:43 PM PDT 24
Finished Jun 25 05:01:45 PM PDT 24
Peak memory 206576 kb
Host smart-396dcb5a-6e47-48d4-a051-0678a75f2dca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27753
12559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.2775312559
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.2509114410
Short name T2457
Test name
Test status
Simulation time 209604783 ps
CPU time 0.87 seconds
Started Jun 25 05:01:38 PM PDT 24
Finished Jun 25 05:01:41 PM PDT 24
Peak memory 206572 kb
Host smart-47f4e2df-a537-4ddf-9753-ade962c03980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25091
14410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.2509114410
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.2611427954
Short name T1049
Test name
Test status
Simulation time 228711132 ps
CPU time 0.89 seconds
Started Jun 25 05:01:47 PM PDT 24
Finished Jun 25 05:01:49 PM PDT 24
Peak memory 206528 kb
Host smart-8c082ee8-b8c4-4c64-9b2e-95761a63fac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26114
27954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.2611427954
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.4185952120
Short name T527
Test name
Test status
Simulation time 158228995 ps
CPU time 0.81 seconds
Started Jun 25 05:01:42 PM PDT 24
Finished Jun 25 05:01:44 PM PDT 24
Peak memory 206580 kb
Host smart-14941c83-b7ab-4d09-a8f9-7d5797c06069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41859
52120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.4185952120
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.3916115868
Short name T1608
Test name
Test status
Simulation time 141941378 ps
CPU time 0.78 seconds
Started Jun 25 05:01:39 PM PDT 24
Finished Jun 25 05:01:42 PM PDT 24
Peak memory 206496 kb
Host smart-859e6128-d3d7-49eb-97d5-082bc2ab0cac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39161
15868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.3916115868
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.1021491364
Short name T2293
Test name
Test status
Simulation time 149660514 ps
CPU time 0.78 seconds
Started Jun 25 05:01:50 PM PDT 24
Finished Jun 25 05:01:52 PM PDT 24
Peak memory 206456 kb
Host smart-670d1b5f-8831-4ad1-8121-d2ae8e395a90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10214
91364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.1021491364
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.2529821098
Short name T1867
Test name
Test status
Simulation time 146464791 ps
CPU time 0.83 seconds
Started Jun 25 05:01:51 PM PDT 24
Finished Jun 25 05:01:53 PM PDT 24
Peak memory 206572 kb
Host smart-604cc417-7053-42d6-b38c-0df480dbef10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25298
21098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.2529821098
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.3148688308
Short name T1160
Test name
Test status
Simulation time 200044551 ps
CPU time 0.88 seconds
Started Jun 25 05:01:39 PM PDT 24
Finished Jun 25 05:01:42 PM PDT 24
Peak memory 206512 kb
Host smart-773a1a6b-1c46-4d53-b8ac-5b2ef5039912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31486
88308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.3148688308
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.853989059
Short name T2182
Test name
Test status
Simulation time 5663256846 ps
CPU time 41.64 seconds
Started Jun 25 05:01:48 PM PDT 24
Finished Jun 25 05:02:31 PM PDT 24
Peak memory 206872 kb
Host smart-87e8bca6-fcb2-49b2-919c-c6c76584e46f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=853989059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.853989059
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.1504681045
Short name T2169
Test name
Test status
Simulation time 143167979 ps
CPU time 0.78 seconds
Started Jun 25 05:01:45 PM PDT 24
Finished Jun 25 05:01:47 PM PDT 24
Peak memory 206604 kb
Host smart-f7edc07b-6c4c-4322-b8eb-ccdcc25b98b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15046
81045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.1504681045
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.508688340
Short name T2429
Test name
Test status
Simulation time 164881746 ps
CPU time 0.81 seconds
Started Jun 25 05:01:50 PM PDT 24
Finished Jun 25 05:01:53 PM PDT 24
Peak memory 206580 kb
Host smart-46e43f3f-f29d-4c20-a3d1-51088dbdc3e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50868
8340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.508688340
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.1009989707
Short name T1969
Test name
Test status
Simulation time 14511800891 ps
CPU time 100.55 seconds
Started Jun 25 05:01:52 PM PDT 24
Finished Jun 25 05:03:33 PM PDT 24
Peak memory 206840 kb
Host smart-83bb7d88-113c-4c5b-b367-b4a846d7b360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10099
89707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.1009989707
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.663294087
Short name T11
Test name
Test status
Simulation time 13329912276 ps
CPU time 14.08 seconds
Started Jun 25 05:01:51 PM PDT 24
Finished Jun 25 05:02:06 PM PDT 24
Peak memory 206916 kb
Host smart-73343681-737d-496f-adab-bbb0efd5fae5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=663294087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.663294087
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.1473462182
Short name T1318
Test name
Test status
Simulation time 23314414405 ps
CPU time 25.51 seconds
Started Jun 25 05:01:48 PM PDT 24
Finished Jun 25 05:02:15 PM PDT 24
Peak memory 206716 kb
Host smart-02718ca1-0de0-4fa2-893c-f9316835356f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1473462182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.1473462182
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.508470877
Short name T738
Test name
Test status
Simulation time 157920926 ps
CPU time 0.82 seconds
Started Jun 25 05:01:47 PM PDT 24
Finished Jun 25 05:01:49 PM PDT 24
Peak memory 206600 kb
Host smart-3ac345f0-e924-4c4e-806c-d99a3f0d8ead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50847
0877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.508470877
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.2744259330
Short name T1776
Test name
Test status
Simulation time 202061402 ps
CPU time 0.85 seconds
Started Jun 25 05:01:51 PM PDT 24
Finished Jun 25 05:01:53 PM PDT 24
Peak memory 206600 kb
Host smart-519b18cc-e2b1-4af8-87a8-86955a91bc87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27442
59330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.2744259330
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.3236839805
Short name T1782
Test name
Test status
Simulation time 457531988 ps
CPU time 1.32 seconds
Started Jun 25 05:01:53 PM PDT 24
Finished Jun 25 05:01:55 PM PDT 24
Peak memory 206508 kb
Host smart-ae79416b-1518-4636-977e-caadf4f1264c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32368
39805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.3236839805
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.855630306
Short name T2117
Test name
Test status
Simulation time 331105491 ps
CPU time 0.95 seconds
Started Jun 25 05:01:54 PM PDT 24
Finished Jun 25 05:01:56 PM PDT 24
Peak memory 206436 kb
Host smart-88d466e4-d344-4883-9a32-95e8f8221466
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85563
0306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.855630306
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.3717774106
Short name T561
Test name
Test status
Simulation time 5978121143 ps
CPU time 11.41 seconds
Started Jun 25 05:01:48 PM PDT 24
Finished Jun 25 05:02:01 PM PDT 24
Peak memory 206764 kb
Host smart-ab25e79f-dd7f-495a-83a4-430921d6e1a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37177
74106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.3717774106
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.2583771495
Short name T1256
Test name
Test status
Simulation time 439687130 ps
CPU time 1.44 seconds
Started Jun 25 05:01:48 PM PDT 24
Finished Jun 25 05:01:51 PM PDT 24
Peak memory 206572 kb
Host smart-e166976a-5622-460f-b47d-024430310fe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25837
71495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.2583771495
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.2111912725
Short name T860
Test name
Test status
Simulation time 132204044 ps
CPU time 0.76 seconds
Started Jun 25 05:01:47 PM PDT 24
Finished Jun 25 05:01:49 PM PDT 24
Peak memory 206576 kb
Host smart-be79a62b-ecc4-47dd-832e-c782b917d3da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21119
12725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.2111912725
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.1265367921
Short name T530
Test name
Test status
Simulation time 33562173 ps
CPU time 0.7 seconds
Started Jun 25 05:01:50 PM PDT 24
Finished Jun 25 05:01:51 PM PDT 24
Peak memory 206444 kb
Host smart-7547e521-2672-4ffd-98f7-76d64b7daa5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12653
67921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.1265367921
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.2859356584
Short name T2205
Test name
Test status
Simulation time 812867152 ps
CPU time 2.19 seconds
Started Jun 25 05:01:47 PM PDT 24
Finished Jun 25 05:01:50 PM PDT 24
Peak memory 206812 kb
Host smart-9b41dde7-5db1-4f96-97df-090c80791fef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28593
56584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.2859356584
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.1099899460
Short name T666
Test name
Test status
Simulation time 292173406 ps
CPU time 1.73 seconds
Started Jun 25 05:01:49 PM PDT 24
Finished Jun 25 05:01:52 PM PDT 24
Peak memory 206756 kb
Host smart-629ff558-9608-4f82-98e0-770445c9e1dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10998
99460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.1099899460
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.3657947686
Short name T644
Test name
Test status
Simulation time 206353527 ps
CPU time 0.81 seconds
Started Jun 25 05:01:56 PM PDT 24
Finished Jun 25 05:01:59 PM PDT 24
Peak memory 206588 kb
Host smart-71011466-bd96-4109-a287-ca8eb7aa6f08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36579
47686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.3657947686
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.1629231266
Short name T1839
Test name
Test status
Simulation time 167565237 ps
CPU time 0.81 seconds
Started Jun 25 05:01:57 PM PDT 24
Finished Jun 25 05:02:01 PM PDT 24
Peak memory 206576 kb
Host smart-c7763cd3-4728-4629-b990-533902eb5e91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16292
31266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.1629231266
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.1048600017
Short name T1528
Test name
Test status
Simulation time 232549092 ps
CPU time 0.9 seconds
Started Jun 25 05:01:46 PM PDT 24
Finished Jun 25 05:01:48 PM PDT 24
Peak memory 206496 kb
Host smart-aa3cfdc8-155a-4b16-a9ea-3ea6813e3d8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10486
00017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.1048600017
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.2383975656
Short name T1201
Test name
Test status
Simulation time 242322186 ps
CPU time 1.01 seconds
Started Jun 25 05:01:48 PM PDT 24
Finished Jun 25 05:01:50 PM PDT 24
Peak memory 206572 kb
Host smart-ab188c67-a8ba-406f-bc36-37dc2d215396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23839
75656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.2383975656
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.1771831031
Short name T1292
Test name
Test status
Simulation time 23356097301 ps
CPU time 23.95 seconds
Started Jun 25 05:01:52 PM PDT 24
Finished Jun 25 05:02:17 PM PDT 24
Peak memory 206620 kb
Host smart-3e80b5c1-f052-4ef4-8570-bf0068d50710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17718
31031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.1771831031
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.2982667647
Short name T380
Test name
Test status
Simulation time 3316387689 ps
CPU time 4.32 seconds
Started Jun 25 05:01:48 PM PDT 24
Finished Jun 25 05:01:53 PM PDT 24
Peak memory 206712 kb
Host smart-7b4e945f-74bb-417c-8492-df645cfe4420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29826
67647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.2982667647
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.1232656250
Short name T855
Test name
Test status
Simulation time 13313959712 ps
CPU time 127.8 seconds
Started Jun 25 05:01:46 PM PDT 24
Finished Jun 25 05:03:55 PM PDT 24
Peak memory 206816 kb
Host smart-b914f6cc-acaa-40e7-a7d9-3c2c09109daf
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1232656250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.1232656250
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.2270963054
Short name T1191
Test name
Test status
Simulation time 267993508 ps
CPU time 1.01 seconds
Started Jun 25 05:01:59 PM PDT 24
Finished Jun 25 05:02:02 PM PDT 24
Peak memory 206348 kb
Host smart-eddc37e4-e573-4097-b63e-7f20926f37ec
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2270963054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.2270963054
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.1153714272
Short name T2316
Test name
Test status
Simulation time 204655850 ps
CPU time 0.86 seconds
Started Jun 25 05:01:50 PM PDT 24
Finished Jun 25 05:01:52 PM PDT 24
Peak memory 206464 kb
Host smart-baca6558-17a8-41ff-b570-a68f71075d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11537
14272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.1153714272
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.2376221219
Short name T438
Test name
Test status
Simulation time 12289583874 ps
CPU time 119.75 seconds
Started Jun 25 05:01:46 PM PDT 24
Finished Jun 25 05:03:47 PM PDT 24
Peak memory 206864 kb
Host smart-9bcc218a-8496-4837-a1cb-1405a42fc797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23762
21219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.2376221219
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.3280226514
Short name T1830
Test name
Test status
Simulation time 6369546741 ps
CPU time 182.26 seconds
Started Jun 25 05:01:50 PM PDT 24
Finished Jun 25 05:04:54 PM PDT 24
Peak memory 206836 kb
Host smart-f3b75447-9632-4780-8807-cc2dfe99db49
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3280226514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.3280226514
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.512586659
Short name T2028
Test name
Test status
Simulation time 172504204 ps
CPU time 0.82 seconds
Started Jun 25 05:01:55 PM PDT 24
Finished Jun 25 05:01:59 PM PDT 24
Peak memory 206756 kb
Host smart-0b1b6ce7-5121-43ab-848a-99b50923a590
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=512586659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.512586659
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.1640967594
Short name T1655
Test name
Test status
Simulation time 151609814 ps
CPU time 0.77 seconds
Started Jun 25 05:01:47 PM PDT 24
Finished Jun 25 05:01:49 PM PDT 24
Peak memory 206500 kb
Host smart-cf6f94b8-c62b-4a33-9173-fdb1112e714f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16409
67594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.1640967594
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.1188929240
Short name T120
Test name
Test status
Simulation time 208901723 ps
CPU time 0.85 seconds
Started Jun 25 05:01:48 PM PDT 24
Finished Jun 25 05:01:50 PM PDT 24
Peak memory 206592 kb
Host smart-fdf495e2-ec4f-4e73-8845-baf7cccf2398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11889
29240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.1188929240
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.1841830410
Short name T555
Test name
Test status
Simulation time 195975017 ps
CPU time 0.88 seconds
Started Jun 25 05:01:48 PM PDT 24
Finished Jun 25 05:01:50 PM PDT 24
Peak memory 206568 kb
Host smart-963084d1-cb76-480e-bd7e-c635b4146da6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18418
30410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.1841830410
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.403394773
Short name T369
Test name
Test status
Simulation time 190897977 ps
CPU time 0.81 seconds
Started Jun 25 05:01:46 PM PDT 24
Finished Jun 25 05:01:48 PM PDT 24
Peak memory 206500 kb
Host smart-bbd6d38a-d5c5-40cf-a052-639f246d2703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40339
4773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.403394773
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.2757612049
Short name T1701
Test name
Test status
Simulation time 202318338 ps
CPU time 0.86 seconds
Started Jun 25 05:01:55 PM PDT 24
Finished Jun 25 05:01:58 PM PDT 24
Peak memory 206592 kb
Host smart-22844e7d-3111-4f03-b8b8-ca9bf7692aaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27576
12049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.2757612049
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.2434206124
Short name T1748
Test name
Test status
Simulation time 147995216 ps
CPU time 0.88 seconds
Started Jun 25 05:01:56 PM PDT 24
Finished Jun 25 05:02:00 PM PDT 24
Peak memory 206508 kb
Host smart-36944416-05b9-4917-bd40-b7faed512b3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24342
06124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.2434206124
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.3054410241
Short name T1525
Test name
Test status
Simulation time 275035495 ps
CPU time 0.91 seconds
Started Jun 25 05:01:57 PM PDT 24
Finished Jun 25 05:02:01 PM PDT 24
Peak memory 206436 kb
Host smart-85423567-5b52-4c46-9033-ca243a4e9304
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3054410241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.3054410241
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.802371748
Short name T781
Test name
Test status
Simulation time 141509600 ps
CPU time 0.78 seconds
Started Jun 25 05:01:57 PM PDT 24
Finished Jun 25 05:02:00 PM PDT 24
Peak memory 206592 kb
Host smart-3956e3ce-ca38-4cc2-a2b4-1ea8ff1fc32d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80237
1748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.802371748
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.958414287
Short name T1457
Test name
Test status
Simulation time 34945224 ps
CPU time 0.68 seconds
Started Jun 25 05:01:59 PM PDT 24
Finished Jun 25 05:02:02 PM PDT 24
Peak memory 206260 kb
Host smart-272cc299-740e-40e3-91f3-8331c50ae420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95841
4287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.958414287
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.1757970881
Short name T86
Test name
Test status
Simulation time 21166502970 ps
CPU time 45.22 seconds
Started Jun 25 05:01:54 PM PDT 24
Finished Jun 25 05:02:42 PM PDT 24
Peak memory 206972 kb
Host smart-79f0b9c3-b877-4d25-b977-62f6c17c8f7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17579
70881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.1757970881
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.2836653294
Short name T799
Test name
Test status
Simulation time 191415257 ps
CPU time 0.92 seconds
Started Jun 25 05:01:56 PM PDT 24
Finished Jun 25 05:02:00 PM PDT 24
Peak memory 206500 kb
Host smart-3a5adc1c-740f-4c80-b257-cbd8647ee65a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28366
53294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.2836653294
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.1109458088
Short name T345
Test name
Test status
Simulation time 177393324 ps
CPU time 0.86 seconds
Started Jun 25 05:02:00 PM PDT 24
Finished Jun 25 05:02:03 PM PDT 24
Peak memory 206428 kb
Host smart-7242cd11-4c40-422b-87ab-d92b0bf712b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11094
58088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.1109458088
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.2448165548
Short name T459
Test name
Test status
Simulation time 215440933 ps
CPU time 0.92 seconds
Started Jun 25 05:01:56 PM PDT 24
Finished Jun 25 05:01:59 PM PDT 24
Peak memory 206520 kb
Host smart-64d54e32-37be-4b43-a1f5-538b2cf86e10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24481
65548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.2448165548
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.1827474557
Short name T1778
Test name
Test status
Simulation time 162272438 ps
CPU time 0.83 seconds
Started Jun 25 05:01:59 PM PDT 24
Finished Jun 25 05:02:02 PM PDT 24
Peak memory 206540 kb
Host smart-89358c92-0ac7-48cb-8b90-ce650a5ae870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18274
74557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.1827474557
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.2484359824
Short name T697
Test name
Test status
Simulation time 148153604 ps
CPU time 0.77 seconds
Started Jun 25 05:01:56 PM PDT 24
Finished Jun 25 05:01:59 PM PDT 24
Peak memory 206568 kb
Host smart-75f33c58-d04a-4c4c-a615-675598c0cbc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24843
59824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.2484359824
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.1703716747
Short name T1296
Test name
Test status
Simulation time 150524609 ps
CPU time 0.75 seconds
Started Jun 25 05:01:56 PM PDT 24
Finished Jun 25 05:01:59 PM PDT 24
Peak memory 206512 kb
Host smart-df0d7240-ebbb-4322-ad00-c71f1a45cf98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17037
16747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.1703716747
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.932828787
Short name T2161
Test name
Test status
Simulation time 150096387 ps
CPU time 0.85 seconds
Started Jun 25 05:01:58 PM PDT 24
Finished Jun 25 05:02:02 PM PDT 24
Peak memory 206520 kb
Host smart-815a2ff1-78ac-4b25-90f8-4dbbc52d4a01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93282
8787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.932828787
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.2174347833
Short name T2305
Test name
Test status
Simulation time 182178258 ps
CPU time 1.03 seconds
Started Jun 25 05:01:56 PM PDT 24
Finished Jun 25 05:01:59 PM PDT 24
Peak memory 206604 kb
Host smart-fcdddce4-39c5-4e66-ae61-0ecd2a5a4af4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21743
47833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.2174347833
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.2428398053
Short name T767
Test name
Test status
Simulation time 3468601339 ps
CPU time 33.15 seconds
Started Jun 25 05:01:56 PM PDT 24
Finished Jun 25 05:02:32 PM PDT 24
Peak memory 206860 kb
Host smart-b667e6f9-5930-4394-bd2a-b0ed1ebd683d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2428398053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.2428398053
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.1118047400
Short name T895
Test name
Test status
Simulation time 202768765 ps
CPU time 0.79 seconds
Started Jun 25 05:01:58 PM PDT 24
Finished Jun 25 05:02:01 PM PDT 24
Peak memory 206440 kb
Host smart-b538452f-e0b2-4636-ac77-2bfd5196f17c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11180
47400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.1118047400
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.765969484
Short name T1854
Test name
Test status
Simulation time 146842440 ps
CPU time 0.8 seconds
Started Jun 25 05:01:58 PM PDT 24
Finished Jun 25 05:02:01 PM PDT 24
Peak memory 206600 kb
Host smart-a63db30b-0a45-474b-b714-6a1beda900cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76596
9484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.765969484
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.2500369703
Short name T2137
Test name
Test status
Simulation time 13297177297 ps
CPU time 129.72 seconds
Started Jun 25 05:01:56 PM PDT 24
Finished Jun 25 05:04:08 PM PDT 24
Peak memory 206780 kb
Host smart-6bf6c6d0-741b-4b2f-94c4-bfd3403244ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25003
69703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.2500369703
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.2663540090
Short name T16
Test name
Test status
Simulation time 3831187186 ps
CPU time 4.56 seconds
Started Jun 25 05:01:58 PM PDT 24
Finished Jun 25 05:02:05 PM PDT 24
Peak memory 206776 kb
Host smart-328d2e45-4fb1-4c65-bd94-34a7bf62a5b1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2663540090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.2663540090
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.3781435552
Short name T612
Test name
Test status
Simulation time 13356214859 ps
CPU time 12.68 seconds
Started Jun 25 05:01:55 PM PDT 24
Finished Jun 25 05:02:10 PM PDT 24
Peak memory 206744 kb
Host smart-c2e15fa6-f988-44b0-a214-4638716b631a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3781435552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.3781435552
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.480322975
Short name T1580
Test name
Test status
Simulation time 23328897595 ps
CPU time 28.89 seconds
Started Jun 25 05:01:55 PM PDT 24
Finished Jun 25 05:02:27 PM PDT 24
Peak memory 206972 kb
Host smart-14f14ea4-4f08-4a7e-a5a2-490d62430cea
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=480322975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.480322975
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.768791320
Short name T1821
Test name
Test status
Simulation time 160012890 ps
CPU time 0.75 seconds
Started Jun 25 05:01:55 PM PDT 24
Finished Jun 25 05:01:58 PM PDT 24
Peak memory 206572 kb
Host smart-f5b2e251-e4e5-410a-9341-386b9f8073ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76879
1320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.768791320
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.1131486619
Short name T1159
Test name
Test status
Simulation time 146832083 ps
CPU time 0.77 seconds
Started Jun 25 05:01:55 PM PDT 24
Finished Jun 25 05:01:59 PM PDT 24
Peak memory 206580 kb
Host smart-6f5f42c9-d21b-4471-80d2-80fe48e68ff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11314
86619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.1131486619
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.2436643301
Short name T971
Test name
Test status
Simulation time 418165166 ps
CPU time 1.29 seconds
Started Jun 25 05:02:00 PM PDT 24
Finished Jun 25 05:02:03 PM PDT 24
Peak memory 206572 kb
Host smart-7b4d731e-ac34-4302-9000-a02a5a46491b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24366
43301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.2436643301
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.1157010734
Short name T1169
Test name
Test status
Simulation time 501456429 ps
CPU time 1.44 seconds
Started Jun 25 05:01:55 PM PDT 24
Finished Jun 25 05:01:59 PM PDT 24
Peak memory 206496 kb
Host smart-19140f54-26a6-45c2-b019-fd2f758d73fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11570
10734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.1157010734
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.3456986213
Short name T1090
Test name
Test status
Simulation time 11950621524 ps
CPU time 21.86 seconds
Started Jun 25 05:01:57 PM PDT 24
Finished Jun 25 05:02:22 PM PDT 24
Peak memory 206868 kb
Host smart-79f6c91a-1cfc-4f2e-9748-506a886ee796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34569
86213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.3456986213
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.275992889
Short name T695
Test name
Test status
Simulation time 325627180 ps
CPU time 1.13 seconds
Started Jun 25 05:01:57 PM PDT 24
Finished Jun 25 05:02:02 PM PDT 24
Peak memory 206500 kb
Host smart-39f2f233-5e86-4ac7-8103-061b361a6017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27599
2889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.275992889
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.1073314017
Short name T44
Test name
Test status
Simulation time 143886282 ps
CPU time 0.76 seconds
Started Jun 25 05:01:54 PM PDT 24
Finished Jun 25 05:01:57 PM PDT 24
Peak memory 206568 kb
Host smart-08e604a4-e758-4a05-bd43-740e7168d1f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10733
14017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.1073314017
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.1489274725
Short name T2216
Test name
Test status
Simulation time 80927623 ps
CPU time 0.73 seconds
Started Jun 25 05:01:57 PM PDT 24
Finished Jun 25 05:02:01 PM PDT 24
Peak memory 206556 kb
Host smart-eab1c522-e41b-4c42-bc3e-34d8a08ce544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14892
74725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.1489274725
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.2830267693
Short name T2367
Test name
Test status
Simulation time 936273492 ps
CPU time 2.22 seconds
Started Jun 25 05:02:00 PM PDT 24
Finished Jun 25 05:02:04 PM PDT 24
Peak memory 206724 kb
Host smart-c542adc5-a920-4699-af12-6052fee23564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28302
67693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.2830267693
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.1193415462
Short name T615
Test name
Test status
Simulation time 288156957 ps
CPU time 1.83 seconds
Started Jun 25 05:01:56 PM PDT 24
Finished Jun 25 05:02:00 PM PDT 24
Peak memory 206676 kb
Host smart-3c2a4abe-d132-479d-80be-9ebcc2ec652d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11934
15462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.1193415462
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.1048817871
Short name T593
Test name
Test status
Simulation time 260939149 ps
CPU time 0.86 seconds
Started Jun 25 05:02:06 PM PDT 24
Finished Jun 25 05:02:08 PM PDT 24
Peak memory 206484 kb
Host smart-26a792a7-2287-455e-bfbd-75ea96de8786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10488
17871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.1048817871
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.4166164717
Short name T2277
Test name
Test status
Simulation time 148016225 ps
CPU time 0.8 seconds
Started Jun 25 05:02:04 PM PDT 24
Finished Jun 25 05:02:06 PM PDT 24
Peak memory 206596 kb
Host smart-4f1d1dab-2f22-460d-9114-7f4a59f83090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41661
64717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.4166164717
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.2178049526
Short name T881
Test name
Test status
Simulation time 208639291 ps
CPU time 0.84 seconds
Started Jun 25 05:01:55 PM PDT 24
Finished Jun 25 05:01:59 PM PDT 24
Peak memory 206568 kb
Host smart-410d7f4f-eae9-4d59-b1df-4867e0d53f0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21780
49526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.2178049526
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.1935034363
Short name T1273
Test name
Test status
Simulation time 15461676737 ps
CPU time 144.11 seconds
Started Jun 25 05:01:58 PM PDT 24
Finished Jun 25 05:04:25 PM PDT 24
Peak memory 206852 kb
Host smart-e9b66ba5-7d71-4093-917a-f57dcacf4943
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1935034363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.1935034363
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.3114412290
Short name T1395
Test name
Test status
Simulation time 199735125 ps
CPU time 0.86 seconds
Started Jun 25 05:01:54 PM PDT 24
Finished Jun 25 05:01:58 PM PDT 24
Peak memory 206580 kb
Host smart-5f09bc5c-b42b-4bb6-8d13-072aacf0ba5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31144
12290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.3114412290
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.3064841182
Short name T2326
Test name
Test status
Simulation time 23294925752 ps
CPU time 26.82 seconds
Started Jun 25 05:01:57 PM PDT 24
Finished Jun 25 05:02:26 PM PDT 24
Peak memory 206720 kb
Host smart-d51acaf4-2745-4b13-b9e0-e26ac7625f6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30648
41182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.3064841182
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.524748963
Short name T18
Test name
Test status
Simulation time 3311659843 ps
CPU time 3.8 seconds
Started Jun 25 05:01:55 PM PDT 24
Finished Jun 25 05:02:02 PM PDT 24
Peak memory 206604 kb
Host smart-aaf4bfa3-2357-49ac-8152-e53210df79f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52474
8963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.524748963
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.970286710
Short name T2513
Test name
Test status
Simulation time 6679073328 ps
CPU time 61.47 seconds
Started Jun 25 05:02:07 PM PDT 24
Finished Jun 25 05:03:10 PM PDT 24
Peak memory 207068 kb
Host smart-41e6ccad-c2c7-4dd6-874a-4f6b74100296
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=970286710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.970286710
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.599533019
Short name T1204
Test name
Test status
Simulation time 240364055 ps
CPU time 0.94 seconds
Started Jun 25 05:02:07 PM PDT 24
Finished Jun 25 05:02:11 PM PDT 24
Peak memory 206576 kb
Host smart-08687e12-aca3-4e66-9a7f-3d8129414bc2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=599533019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.599533019
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.2886443697
Short name T1077
Test name
Test status
Simulation time 184653638 ps
CPU time 0.91 seconds
Started Jun 25 05:01:58 PM PDT 24
Finished Jun 25 05:02:02 PM PDT 24
Peak memory 206576 kb
Host smart-4a7a5a52-ef34-4f07-8838-55dc375d2657
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28864
43697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.2886443697
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.2634144852
Short name T619
Test name
Test status
Simulation time 11635349559 ps
CPU time 341.21 seconds
Started Jun 25 05:01:56 PM PDT 24
Finished Jun 25 05:07:39 PM PDT 24
Peak memory 206924 kb
Host smart-ab8d0126-e584-4853-b382-c2a75924d338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26341
44852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.2634144852
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.4248218523
Short name T1730
Test name
Test status
Simulation time 6167884830 ps
CPU time 44.42 seconds
Started Jun 25 05:01:58 PM PDT 24
Finished Jun 25 05:02:45 PM PDT 24
Peak memory 206884 kb
Host smart-ddb59013-29e2-4210-b575-72d039d82e56
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4248218523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.4248218523
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.3753429111
Short name T956
Test name
Test status
Simulation time 163177535 ps
CPU time 0.77 seconds
Started Jun 25 05:02:05 PM PDT 24
Finished Jun 25 05:02:07 PM PDT 24
Peak memory 206576 kb
Host smart-366c7811-d557-47d2-aaa4-092486794767
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3753429111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.3753429111
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.4203847754
Short name T2401
Test name
Test status
Simulation time 146782611 ps
CPU time 0.78 seconds
Started Jun 25 05:01:58 PM PDT 24
Finished Jun 25 05:02:02 PM PDT 24
Peak memory 206508 kb
Host smart-b3ec7658-599e-4c0e-b4f3-d426efd96f2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42038
47754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.4203847754
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.1752094105
Short name T115
Test name
Test status
Simulation time 193283082 ps
CPU time 0.81 seconds
Started Jun 25 05:02:09 PM PDT 24
Finished Jun 25 05:02:12 PM PDT 24
Peak memory 206572 kb
Host smart-49aa4d85-bfb2-418f-bc9e-0b0e465c4d0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17520
94105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.1752094105
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.538473213
Short name T1449
Test name
Test status
Simulation time 149526600 ps
CPU time 0.8 seconds
Started Jun 25 05:02:05 PM PDT 24
Finished Jun 25 05:02:06 PM PDT 24
Peak memory 206872 kb
Host smart-12648d53-d053-4234-9643-35e903e167ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53847
3213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.538473213
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.4289970220
Short name T1818
Test name
Test status
Simulation time 181492267 ps
CPU time 0.84 seconds
Started Jun 25 05:02:05 PM PDT 24
Finished Jun 25 05:02:07 PM PDT 24
Peak memory 206600 kb
Host smart-6c01b929-a3aa-4fa0-8c02-4bff43d6d302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42899
70220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.4289970220
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.1398623873
Short name T2512
Test name
Test status
Simulation time 152571879 ps
CPU time 0.78 seconds
Started Jun 25 05:02:05 PM PDT 24
Finished Jun 25 05:02:08 PM PDT 24
Peak memory 206472 kb
Host smart-d36fd5a3-b6d7-430d-ad0d-e7784e5de47a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13986
23873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.1398623873
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.546491373
Short name T2264
Test name
Test status
Simulation time 159605498 ps
CPU time 0.85 seconds
Started Jun 25 05:02:05 PM PDT 24
Finished Jun 25 05:02:07 PM PDT 24
Peak memory 206492 kb
Host smart-eebff31b-d27b-44c7-a704-2b9b2d879921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54649
1373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.546491373
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.729465640
Short name T2188
Test name
Test status
Simulation time 213729220 ps
CPU time 0.97 seconds
Started Jun 25 05:02:07 PM PDT 24
Finished Jun 25 05:02:10 PM PDT 24
Peak memory 206508 kb
Host smart-eb8c75f3-8c4a-4acf-9d22-637c2983a3ca
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=729465640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.729465640
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.3445432048
Short name T607
Test name
Test status
Simulation time 188308003 ps
CPU time 0.9 seconds
Started Jun 25 05:02:08 PM PDT 24
Finished Jun 25 05:02:11 PM PDT 24
Peak memory 206604 kb
Host smart-e28e23b4-dbc4-419c-b0e7-77ec768f06fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34454
32048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.3445432048
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.38767464
Short name T2159
Test name
Test status
Simulation time 86604875 ps
CPU time 0.73 seconds
Started Jun 25 05:02:07 PM PDT 24
Finished Jun 25 05:02:09 PM PDT 24
Peak memory 206564 kb
Host smart-8b8c5ebd-067a-49c2-b19c-a6aac8dfa840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38767
464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.38767464
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.1840399017
Short name T2108
Test name
Test status
Simulation time 22432867075 ps
CPU time 45.36 seconds
Started Jun 25 05:02:08 PM PDT 24
Finished Jun 25 05:02:56 PM PDT 24
Peak memory 206920 kb
Host smart-f277f307-4c2a-47a3-8154-c3d1298f8f7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18403
99017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.1840399017
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.3292417351
Short name T571
Test name
Test status
Simulation time 178141723 ps
CPU time 0.88 seconds
Started Jun 25 05:02:03 PM PDT 24
Finished Jun 25 05:02:05 PM PDT 24
Peak memory 206508 kb
Host smart-ffc3ef97-e962-43d9-a7a6-e1a3db4f0a92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32924
17351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.3292417351
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.1677646951
Short name T2405
Test name
Test status
Simulation time 222470295 ps
CPU time 1.04 seconds
Started Jun 25 05:02:06 PM PDT 24
Finished Jun 25 05:02:09 PM PDT 24
Peak memory 206508 kb
Host smart-45b52000-27a3-4fd9-9a09-51d960aa6bc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16776
46951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.1677646951
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.2983248935
Short name T1600
Test name
Test status
Simulation time 209412283 ps
CPU time 0.92 seconds
Started Jun 25 05:02:06 PM PDT 24
Finished Jun 25 05:02:09 PM PDT 24
Peak memory 206524 kb
Host smart-5714d33c-dec0-4362-bf89-29c47a04b338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29832
48935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.2983248935
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.2153927721
Short name T2069
Test name
Test status
Simulation time 194223727 ps
CPU time 0.89 seconds
Started Jun 25 05:02:11 PM PDT 24
Finished Jun 25 05:02:14 PM PDT 24
Peak memory 206520 kb
Host smart-b3132d45-397a-42d9-b8b6-801804d15324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21539
27721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.2153927721
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.1716105547
Short name T75
Test name
Test status
Simulation time 145711194 ps
CPU time 0.77 seconds
Started Jun 25 05:02:10 PM PDT 24
Finished Jun 25 05:02:12 PM PDT 24
Peak memory 206448 kb
Host smart-5583459b-f302-43bd-a594-c1ddb675d412
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17161
05547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.1716105547
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.980846720
Short name T90
Test name
Test status
Simulation time 157146278 ps
CPU time 0.85 seconds
Started Jun 25 05:02:08 PM PDT 24
Finished Jun 25 05:02:11 PM PDT 24
Peak memory 206600 kb
Host smart-ed449d1a-4c80-42cb-a910-25608a59fc80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98084
6720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.980846720
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.1871580111
Short name T1538
Test name
Test status
Simulation time 143608657 ps
CPU time 0.76 seconds
Started Jun 25 05:02:04 PM PDT 24
Finished Jun 25 05:02:05 PM PDT 24
Peak memory 206592 kb
Host smart-a9dd4ee6-5d98-49f7-b09f-05d3d650868a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18715
80111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.1871580111
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.3683858426
Short name T1250
Test name
Test status
Simulation time 229621720 ps
CPU time 1 seconds
Started Jun 25 05:02:07 PM PDT 24
Finished Jun 25 05:02:09 PM PDT 24
Peak memory 206580 kb
Host smart-10ae1925-5628-4382-9973-ca6e5d32a218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36838
58426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.3683858426
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.242278653
Short name T33
Test name
Test status
Simulation time 8821686584 ps
CPU time 84.75 seconds
Started Jun 25 05:02:09 PM PDT 24
Finished Jun 25 05:03:35 PM PDT 24
Peak memory 206904 kb
Host smart-3495668f-b19a-4964-b9ff-8ff217904f24
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=242278653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.242278653
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.1554187479
Short name T686
Test name
Test status
Simulation time 167056213 ps
CPU time 0.81 seconds
Started Jun 25 05:02:06 PM PDT 24
Finished Jun 25 05:02:08 PM PDT 24
Peak memory 206584 kb
Host smart-f8b9dbb7-a51a-4a03-8f98-ee8ca9c2a84c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15541
87479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.1554187479
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.3599501171
Short name T384
Test name
Test status
Simulation time 149329259 ps
CPU time 0.83 seconds
Started Jun 25 05:02:07 PM PDT 24
Finished Jun 25 05:02:10 PM PDT 24
Peak memory 206516 kb
Host smart-9e3cbf6e-b137-4a8d-8250-6345ee8207a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35995
01171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.3599501171
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.22929625
Short name T391
Test name
Test status
Simulation time 7255338855 ps
CPU time 52.56 seconds
Started Jun 25 05:02:08 PM PDT 24
Finished Jun 25 05:03:03 PM PDT 24
Peak memory 206940 kb
Host smart-4a88cd20-7a26-4de7-b6d9-a6f49543e9cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22929
625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.22929625
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.1133401421
Short name T8
Test name
Test status
Simulation time 3693599189 ps
CPU time 4.4 seconds
Started Jun 25 05:02:07 PM PDT 24
Finished Jun 25 05:02:14 PM PDT 24
Peak memory 206692 kb
Host smart-bbcd42b2-8833-469b-8f8b-ce5cbe893e0d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1133401421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.1133401421
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.1246810879
Short name T2034
Test name
Test status
Simulation time 13370071725 ps
CPU time 13.22 seconds
Started Jun 25 05:02:07 PM PDT 24
Finished Jun 25 05:02:23 PM PDT 24
Peak memory 206812 kb
Host smart-b0e6103d-1efb-4917-a500-68dea6deb483
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1246810879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.1246810879
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.732103400
Short name T2436
Test name
Test status
Simulation time 23355820284 ps
CPU time 21.28 seconds
Started Jun 25 05:02:12 PM PDT 24
Finished Jun 25 05:02:35 PM PDT 24
Peak memory 206928 kb
Host smart-db9b4610-44d6-40c1-a0cf-56991e4944ad
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=732103400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.732103400
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.2678505723
Short name T1667
Test name
Test status
Simulation time 167602125 ps
CPU time 0.82 seconds
Started Jun 25 05:02:05 PM PDT 24
Finished Jun 25 05:02:07 PM PDT 24
Peak memory 206568 kb
Host smart-62baefc1-0cea-49b7-b62a-9b29b599a67e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26785
05723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.2678505723
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.3316493477
Short name T2228
Test name
Test status
Simulation time 152712997 ps
CPU time 0.81 seconds
Started Jun 25 05:02:06 PM PDT 24
Finished Jun 25 05:02:09 PM PDT 24
Peak memory 206580 kb
Host smart-a84449ce-f73d-4bfb-8083-876815218cb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33164
93477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.3316493477
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.4163301824
Short name T2042
Test name
Test status
Simulation time 146735375 ps
CPU time 0.8 seconds
Started Jun 25 05:02:11 PM PDT 24
Finished Jun 25 05:02:14 PM PDT 24
Peak memory 206516 kb
Host smart-d14fd49e-039a-4879-9783-a2c4fb5237dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41633
01824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.4163301824
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.2842356357
Short name T1787
Test name
Test status
Simulation time 1160205563 ps
CPU time 2.78 seconds
Started Jun 25 05:02:06 PM PDT 24
Finished Jun 25 05:02:10 PM PDT 24
Peak memory 206792 kb
Host smart-0449f362-c18a-487f-a628-2b435eda9c56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28423
56357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.2842356357
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.3357044422
Short name T166
Test name
Test status
Simulation time 13238196677 ps
CPU time 25.04 seconds
Started Jun 25 05:02:08 PM PDT 24
Finished Jun 25 05:02:35 PM PDT 24
Peak memory 206900 kb
Host smart-c1086c5f-7124-42ad-bb94-878da2609ff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33570
44422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.3357044422
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.1500958495
Short name T2310
Test name
Test status
Simulation time 431814236 ps
CPU time 1.43 seconds
Started Jun 25 05:02:10 PM PDT 24
Finished Jun 25 05:02:13 PM PDT 24
Peak memory 206456 kb
Host smart-df5f5b3d-57e6-49dc-8818-f766dd6723fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15009
58495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.1500958495
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.1602138403
Short name T1707
Test name
Test status
Simulation time 151885648 ps
CPU time 0.78 seconds
Started Jun 25 05:02:04 PM PDT 24
Finished Jun 25 05:02:05 PM PDT 24
Peak memory 206576 kb
Host smart-3b170dc0-2f91-48e8-a00b-7339bc551732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16021
38403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.1602138403
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.3308010434
Short name T1883
Test name
Test status
Simulation time 32848144 ps
CPU time 0.66 seconds
Started Jun 25 05:02:12 PM PDT 24
Finished Jun 25 05:02:16 PM PDT 24
Peak memory 206496 kb
Host smart-b3d5bc16-b590-4938-b848-afddd445e7b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33080
10434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.3308010434
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.307675874
Short name T1040
Test name
Test status
Simulation time 924274179 ps
CPU time 2.25 seconds
Started Jun 25 05:02:13 PM PDT 24
Finished Jun 25 05:02:18 PM PDT 24
Peak memory 206736 kb
Host smart-e21123bc-73d0-4a57-8c83-be2f1bcda4a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30767
5874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.307675874
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.2072006309
Short name T183
Test name
Test status
Simulation time 167939259 ps
CPU time 1.47 seconds
Started Jun 25 05:02:11 PM PDT 24
Finished Jun 25 05:02:15 PM PDT 24
Peak memory 206688 kb
Host smart-5898cdce-f894-431c-8aca-59abe7162d34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20720
06309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.2072006309
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.175876123
Short name T602
Test name
Test status
Simulation time 178368534 ps
CPU time 0.78 seconds
Started Jun 25 05:02:23 PM PDT 24
Finished Jun 25 05:02:27 PM PDT 24
Peak memory 206492 kb
Host smart-a795ed83-79d2-4203-aa00-6bcac268af50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17587
6123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.175876123
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.722353548
Short name T1992
Test name
Test status
Simulation time 149988383 ps
CPU time 0.73 seconds
Started Jun 25 05:02:13 PM PDT 24
Finished Jun 25 05:02:16 PM PDT 24
Peak memory 206872 kb
Host smart-53d86fdf-6806-4d23-b83b-df7deaa89509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72235
3548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.722353548
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.734809896
Short name T1482
Test name
Test status
Simulation time 194428278 ps
CPU time 0.88 seconds
Started Jun 25 05:02:09 PM PDT 24
Finished Jun 25 05:02:12 PM PDT 24
Peak memory 206500 kb
Host smart-4d468df0-8096-4c60-b242-f52dde9da31e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73480
9896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.734809896
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.3946008510
Short name T1058
Test name
Test status
Simulation time 13256210467 ps
CPU time 114.95 seconds
Started Jun 25 05:02:13 PM PDT 24
Finished Jun 25 05:04:11 PM PDT 24
Peak memory 206892 kb
Host smart-7825e14c-e16f-49dc-8d66-b2c2ce2d0036
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3946008510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.3946008510
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.820704825
Short name T1853
Test name
Test status
Simulation time 212796773 ps
CPU time 0.92 seconds
Started Jun 25 05:02:06 PM PDT 24
Finished Jun 25 05:02:09 PM PDT 24
Peak memory 206500 kb
Host smart-7236795f-6b9d-45a9-8aa2-dd437084ac10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82070
4825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.820704825
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.1848794838
Short name T667
Test name
Test status
Simulation time 23280357603 ps
CPU time 23.78 seconds
Started Jun 25 05:02:08 PM PDT 24
Finished Jun 25 05:02:34 PM PDT 24
Peak memory 206684 kb
Host smart-fed80581-3217-4c2c-b58a-ca8fc340f175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18487
94838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.1848794838
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.643891758
Short name T1417
Test name
Test status
Simulation time 3421594635 ps
CPU time 4.08 seconds
Started Jun 25 05:02:07 PM PDT 24
Finished Jun 25 05:02:13 PM PDT 24
Peak memory 206632 kb
Host smart-9c58cc96-6f44-484c-9b9a-099af2feb6d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64389
1758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.643891758
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.1570157051
Short name T1675
Test name
Test status
Simulation time 5928053840 ps
CPU time 42.13 seconds
Started Jun 25 05:02:03 PM PDT 24
Finished Jun 25 05:02:46 PM PDT 24
Peak memory 206884 kb
Host smart-cfb451b9-57ef-4e42-a0c8-53b9c6f3725a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1570157051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.1570157051
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.3334341974
Short name T803
Test name
Test status
Simulation time 277855354 ps
CPU time 0.92 seconds
Started Jun 25 05:02:12 PM PDT 24
Finished Jun 25 05:02:15 PM PDT 24
Peak memory 206512 kb
Host smart-96bf0b93-cd70-4a77-b68c-d09cbb37ab99
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3334341974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.3334341974
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.2018015579
Short name T1905
Test name
Test status
Simulation time 211671686 ps
CPU time 0.84 seconds
Started Jun 25 05:02:06 PM PDT 24
Finished Jun 25 05:02:08 PM PDT 24
Peak memory 206496 kb
Host smart-bca9b3e6-cdd7-4b1c-8adc-1fdff70749dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20180
15579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.2018015579
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.1501669472
Short name T2174
Test name
Test status
Simulation time 6044323903 ps
CPU time 167.94 seconds
Started Jun 25 05:02:07 PM PDT 24
Finished Jun 25 05:04:56 PM PDT 24
Peak memory 206920 kb
Host smart-7148eaf7-de4f-4e79-ba30-5267df67f707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15016
69472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.1501669472
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.2079643584
Short name T2313
Test name
Test status
Simulation time 5061426676 ps
CPU time 40.01 seconds
Started Jun 25 05:02:09 PM PDT 24
Finished Jun 25 05:02:51 PM PDT 24
Peak memory 206848 kb
Host smart-c60704db-953b-41eb-a1a7-04232c34926d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2079643584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.2079643584
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.3493596054
Short name T1225
Test name
Test status
Simulation time 149129810 ps
CPU time 0.78 seconds
Started Jun 25 05:02:15 PM PDT 24
Finished Jun 25 05:02:17 PM PDT 24
Peak memory 206496 kb
Host smart-ab29a167-eb9d-4ee4-9d68-dd00269b7005
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3493596054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.3493596054
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.1291358877
Short name T973
Test name
Test status
Simulation time 149235443 ps
CPU time 0.78 seconds
Started Jun 25 05:02:04 PM PDT 24
Finished Jun 25 05:02:06 PM PDT 24
Peak memory 206508 kb
Host smart-18c4add3-60b4-489a-8b1e-98429fe6402d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12913
58877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.1291358877
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.3822148543
Short name T70
Test name
Test status
Simulation time 185354254 ps
CPU time 0.87 seconds
Started Jun 25 05:02:12 PM PDT 24
Finished Jun 25 05:02:15 PM PDT 24
Peak memory 206520 kb
Host smart-cf6177e1-f6eb-4b71-9bcb-4747b79f71a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38221
48543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.3822148543
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.571551243
Short name T458
Test name
Test status
Simulation time 198575979 ps
CPU time 0.85 seconds
Started Jun 25 05:02:07 PM PDT 24
Finished Jun 25 05:02:10 PM PDT 24
Peak memory 206588 kb
Host smart-aba3ed27-4b3e-49c0-a893-9e67c8a1cb51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57155
1243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.571551243
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.2519020070
Short name T357
Test name
Test status
Simulation time 184237363 ps
CPU time 0.8 seconds
Started Jun 25 05:02:09 PM PDT 24
Finished Jun 25 05:02:12 PM PDT 24
Peak memory 206572 kb
Host smart-50b97be1-cebc-4ae6-8866-8c9f336aaa2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25190
20070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.2519020070
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.544176906
Short name T761
Test name
Test status
Simulation time 149181497 ps
CPU time 0.78 seconds
Started Jun 25 05:02:12 PM PDT 24
Finished Jun 25 05:02:15 PM PDT 24
Peak memory 206516 kb
Host smart-4e98f8df-5ab3-46c8-987e-ac3c038f9a7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54417
6906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.544176906
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.1842671219
Short name T2449
Test name
Test status
Simulation time 185271052 ps
CPU time 0.8 seconds
Started Jun 25 05:02:13 PM PDT 24
Finished Jun 25 05:02:16 PM PDT 24
Peak memory 206580 kb
Host smart-72488a57-8016-41ea-91f2-ece1ff2e1fa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18426
71219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.1842671219
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.3313143983
Short name T2090
Test name
Test status
Simulation time 210174405 ps
CPU time 0.89 seconds
Started Jun 25 05:02:07 PM PDT 24
Finished Jun 25 05:02:10 PM PDT 24
Peak memory 206596 kb
Host smart-2fc4ff6b-b533-4c8e-8074-9f19dd11d10e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3313143983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.3313143983
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.2750979682
Short name T2173
Test name
Test status
Simulation time 154386440 ps
CPU time 0.81 seconds
Started Jun 25 05:02:07 PM PDT 24
Finished Jun 25 05:02:09 PM PDT 24
Peak memory 206496 kb
Host smart-5eff03a0-ec1a-4d03-b89d-30be7f9b53db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27509
79682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.2750979682
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.1683577618
Short name T699
Test name
Test status
Simulation time 111125756 ps
CPU time 0.71 seconds
Started Jun 25 05:02:17 PM PDT 24
Finished Jun 25 05:02:19 PM PDT 24
Peak memory 206424 kb
Host smart-ef840193-ba11-41a5-8a41-3ac1adb3ccd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16835
77618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.1683577618
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.115450062
Short name T1265
Test name
Test status
Simulation time 13880537004 ps
CPU time 32.51 seconds
Started Jun 25 05:02:04 PM PDT 24
Finished Jun 25 05:02:38 PM PDT 24
Peak memory 206964 kb
Host smart-4a81e42a-d807-42ff-8e25-d9ea8937a083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11545
0062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.115450062
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.794047520
Short name T2087
Test name
Test status
Simulation time 213610695 ps
CPU time 0.88 seconds
Started Jun 25 05:02:13 PM PDT 24
Finished Jun 25 05:02:16 PM PDT 24
Peak memory 206604 kb
Host smart-d7faf24b-19c1-4857-8c12-1b9150967766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79404
7520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.794047520
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.885852474
Short name T329
Test name
Test status
Simulation time 168620063 ps
CPU time 0.82 seconds
Started Jun 25 05:02:09 PM PDT 24
Finished Jun 25 05:02:12 PM PDT 24
Peak memory 206560 kb
Host smart-bf5b74a0-8ea0-4a8f-b825-431d46f119d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88585
2474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.885852474
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.2255353956
Short name T1166
Test name
Test status
Simulation time 208589172 ps
CPU time 0.82 seconds
Started Jun 25 05:02:23 PM PDT 24
Finished Jun 25 05:02:27 PM PDT 24
Peak memory 206504 kb
Host smart-03e65b32-05d2-4cf9-922f-963a74e72ec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22553
53956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.2255353956
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.337599216
Short name T1527
Test name
Test status
Simulation time 159880642 ps
CPU time 0.83 seconds
Started Jun 25 05:02:13 PM PDT 24
Finished Jun 25 05:02:16 PM PDT 24
Peak memory 206600 kb
Host smart-e0c24fde-7238-4253-9a62-7904ef214dc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33759
9216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.337599216
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.1131855932
Short name T1011
Test name
Test status
Simulation time 150331673 ps
CPU time 0.77 seconds
Started Jun 25 05:02:06 PM PDT 24
Finished Jun 25 05:02:08 PM PDT 24
Peak memory 206504 kb
Host smart-c3219590-c094-4ec5-a107-06a17044db82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11318
55932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.1131855932
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.23433116
Short name T2217
Test name
Test status
Simulation time 148966894 ps
CPU time 0.79 seconds
Started Jun 25 05:02:16 PM PDT 24
Finished Jun 25 05:02:18 PM PDT 24
Peak memory 206592 kb
Host smart-c68a889b-e296-412f-9c78-0f24259c8c96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23433
116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.23433116
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.1162060088
Short name T1444
Test name
Test status
Simulation time 158455825 ps
CPU time 0.79 seconds
Started Jun 25 05:02:24 PM PDT 24
Finished Jun 25 05:02:28 PM PDT 24
Peak memory 206572 kb
Host smart-0c8a56b3-5907-4f3d-b867-1da39794545e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11620
60088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.1162060088
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.527671807
Short name T1649
Test name
Test status
Simulation time 259811151 ps
CPU time 0.94 seconds
Started Jun 25 05:02:12 PM PDT 24
Finished Jun 25 05:02:15 PM PDT 24
Peak memory 206528 kb
Host smart-20079154-2abd-4100-9e05-2a19bb173497
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52767
1807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.527671807
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.1568447024
Short name T1253
Test name
Test status
Simulation time 7603278938 ps
CPU time 56.58 seconds
Started Jun 25 05:02:13 PM PDT 24
Finished Jun 25 05:03:12 PM PDT 24
Peak memory 206944 kb
Host smart-122cd283-fbe5-450e-be22-b083012b7b19
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1568447024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.1568447024
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.109631414
Short name T1190
Test name
Test status
Simulation time 168772886 ps
CPU time 0.83 seconds
Started Jun 25 05:02:14 PM PDT 24
Finished Jun 25 05:02:17 PM PDT 24
Peak memory 206516 kb
Host smart-429fad17-af61-4260-b907-baca595f76eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10963
1414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.109631414
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.291653162
Short name T1257
Test name
Test status
Simulation time 214749800 ps
CPU time 0.83 seconds
Started Jun 25 05:02:13 PM PDT 24
Finished Jun 25 05:02:16 PM PDT 24
Peak memory 206580 kb
Host smart-7ee3071b-1f1c-49e0-9fe1-b8b1e1b00d26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29165
3162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.291653162
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.3511318166
Short name T440
Test name
Test status
Simulation time 10579065113 ps
CPU time 96.72 seconds
Started Jun 25 05:02:24 PM PDT 24
Finished Jun 25 05:04:03 PM PDT 24
Peak memory 206832 kb
Host smart-2b8cde21-bf7e-4950-89a8-921bfd556269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35113
18166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.3511318166
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.4097961649
Short name T2043
Test name
Test status
Simulation time 3596700523 ps
CPU time 5.16 seconds
Started Jun 25 05:02:17 PM PDT 24
Finished Jun 25 05:02:24 PM PDT 24
Peak memory 206640 kb
Host smart-404d7a05-66c8-49f3-8705-6cd87d7d02c2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4097961649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.4097961649
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.3788946810
Short name T643
Test name
Test status
Simulation time 13389448633 ps
CPU time 13.27 seconds
Started Jun 25 05:02:22 PM PDT 24
Finished Jun 25 05:02:37 PM PDT 24
Peak memory 206968 kb
Host smart-5c723cd6-6abc-431a-81fd-4a353547a8cc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3788946810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.3788946810
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.27122062
Short name T2325
Test name
Test status
Simulation time 23363056699 ps
CPU time 25.21 seconds
Started Jun 25 05:02:14 PM PDT 24
Finished Jun 25 05:02:41 PM PDT 24
Peak memory 206712 kb
Host smart-f0283022-5252-4d06-9149-d936a58c21a4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=27122062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.27122062
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.1315945975
Short name T1470
Test name
Test status
Simulation time 184156088 ps
CPU time 0.82 seconds
Started Jun 25 05:02:11 PM PDT 24
Finished Jun 25 05:02:14 PM PDT 24
Peak memory 206580 kb
Host smart-1564a2ca-5c00-46ea-9eea-39e1fff116ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13159
45975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.1315945975
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.4237223597
Short name T1714
Test name
Test status
Simulation time 202414087 ps
CPU time 0.81 seconds
Started Jun 25 05:02:14 PM PDT 24
Finished Jun 25 05:02:17 PM PDT 24
Peak memory 206516 kb
Host smart-a6769263-5f67-49f6-a4ab-9064743b6879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42372
23597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.4237223597
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.700586766
Short name T154
Test name
Test status
Simulation time 532500449 ps
CPU time 1.59 seconds
Started Jun 25 05:02:12 PM PDT 24
Finished Jun 25 05:02:16 PM PDT 24
Peak memory 206764 kb
Host smart-61508cba-9a26-4fcf-97a7-41e91043f174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70058
6766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.700586766
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.2279283748
Short name T107
Test name
Test status
Simulation time 448918305 ps
CPU time 1.33 seconds
Started Jun 25 05:02:25 PM PDT 24
Finished Jun 25 05:02:30 PM PDT 24
Peak memory 206756 kb
Host smart-932c8c3c-b07e-4ee5-9d83-a6c298f15b70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22792
83748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.2279283748
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.184123571
Short name T2204
Test name
Test status
Simulation time 14896183259 ps
CPU time 31.88 seconds
Started Jun 25 05:02:25 PM PDT 24
Finished Jun 25 05:03:00 PM PDT 24
Peak memory 207032 kb
Host smart-f6558db3-1fde-42df-94e1-f71849972afd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18412
3571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.184123571
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.2094546716
Short name T2155
Test name
Test status
Simulation time 466352166 ps
CPU time 1.29 seconds
Started Jun 25 05:02:23 PM PDT 24
Finished Jun 25 05:02:27 PM PDT 24
Peak memory 206480 kb
Host smart-44153c81-e4e4-48ed-a5dc-14a62d248ea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20945
46716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.2094546716
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.2523855051
Short name T362
Test name
Test status
Simulation time 137952502 ps
CPU time 0.77 seconds
Started Jun 25 05:02:24 PM PDT 24
Finished Jun 25 05:02:27 PM PDT 24
Peak memory 206476 kb
Host smart-8efb149f-71f9-4435-8a88-789bb51c3a63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25238
55051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.2523855051
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.3947880133
Short name T1164
Test name
Test status
Simulation time 137034074 ps
CPU time 0.75 seconds
Started Jun 25 05:02:17 PM PDT 24
Finished Jun 25 05:02:19 PM PDT 24
Peak memory 206560 kb
Host smart-4f4692f0-1394-4156-bcbe-9c557c94aeb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39478
80133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.3947880133
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.142451028
Short name T903
Test name
Test status
Simulation time 766507234 ps
CPU time 2.08 seconds
Started Jun 25 05:02:10 PM PDT 24
Finished Jun 25 05:02:14 PM PDT 24
Peak memory 206748 kb
Host smart-7c6f41e3-89de-4792-abb8-7067d1025419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14245
1028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.142451028
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.3487190311
Short name T1983
Test name
Test status
Simulation time 244693153 ps
CPU time 1.51 seconds
Started Jun 25 05:02:24 PM PDT 24
Finished Jun 25 05:02:28 PM PDT 24
Peak memory 206696 kb
Host smart-43a6167f-668b-4f93-a0bd-8def20593063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34871
90311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.3487190311
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.1755142151
Short name T1523
Test name
Test status
Simulation time 229075634 ps
CPU time 0.9 seconds
Started Jun 25 05:02:22 PM PDT 24
Finished Jun 25 05:02:25 PM PDT 24
Peak memory 206572 kb
Host smart-9a8a18eb-79ed-4e83-a7ba-75ac5f2617da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17551
42151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.1755142151
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.1431537610
Short name T2505
Test name
Test status
Simulation time 191385203 ps
CPU time 0.8 seconds
Started Jun 25 05:02:28 PM PDT 24
Finished Jun 25 05:02:31 PM PDT 24
Peak memory 206556 kb
Host smart-de3e142b-bdcc-4ec0-ac17-ebd2740f6e3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14315
37610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.1431537610
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.915878729
Short name T1952
Test name
Test status
Simulation time 201021572 ps
CPU time 0.95 seconds
Started Jun 25 05:02:15 PM PDT 24
Finished Jun 25 05:02:18 PM PDT 24
Peak memory 206572 kb
Host smart-82b019af-c4eb-4098-870b-9086f46b9b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91587
8729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.915878729
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.4012327632
Short name T1366
Test name
Test status
Simulation time 256443088 ps
CPU time 0.96 seconds
Started Jun 25 05:02:22 PM PDT 24
Finished Jun 25 05:02:25 PM PDT 24
Peak memory 206572 kb
Host smart-ff97f89c-fb64-4689-bcda-db5c81c9c932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40123
27632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.4012327632
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.315369223
Short name T882
Test name
Test status
Simulation time 23327486641 ps
CPU time 21.63 seconds
Started Jun 25 05:02:10 PM PDT 24
Finished Jun 25 05:02:34 PM PDT 24
Peak memory 206660 kb
Host smart-e98e5e79-c60f-492b-98c6-0e888a5ab998
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31536
9223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.315369223
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.3947121025
Short name T1742
Test name
Test status
Simulation time 3329390648 ps
CPU time 3.78 seconds
Started Jun 25 05:02:13 PM PDT 24
Finished Jun 25 05:02:19 PM PDT 24
Peak memory 206624 kb
Host smart-a1dc94d9-60d8-4794-afd8-1388252ecf78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39471
21025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.3947121025
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.2636724814
Short name T2088
Test name
Test status
Simulation time 14464322114 ps
CPU time 141.57 seconds
Started Jun 25 05:02:24 PM PDT 24
Finished Jun 25 05:04:49 PM PDT 24
Peak memory 206956 kb
Host smart-18491267-a56d-441f-aa08-f3fb2438cc11
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2636724814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.2636724814
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.1382408233
Short name T1773
Test name
Test status
Simulation time 240363393 ps
CPU time 0.93 seconds
Started Jun 25 05:02:23 PM PDT 24
Finished Jun 25 05:02:25 PM PDT 24
Peak memory 206584 kb
Host smart-c1fe7797-24a2-42f7-9c5d-1bb64ae67513
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1382408233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.1382408233
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.951442721
Short name T2296
Test name
Test status
Simulation time 188901213 ps
CPU time 0.84 seconds
Started Jun 25 05:02:21 PM PDT 24
Finished Jun 25 05:02:22 PM PDT 24
Peak memory 206576 kb
Host smart-49772dad-cede-4bbd-9be9-3f71d456a376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95144
2721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.951442721
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.2074037162
Short name T499
Test name
Test status
Simulation time 10601627204 ps
CPU time 74.3 seconds
Started Jun 25 05:02:14 PM PDT 24
Finished Jun 25 05:03:30 PM PDT 24
Peak memory 206872 kb
Host smart-a18cd6a0-27c9-4855-b328-8844d05b4023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20740
37162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.2074037162
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.1242653436
Short name T842
Test name
Test status
Simulation time 3218871665 ps
CPU time 28.18 seconds
Started Jun 25 05:02:25 PM PDT 24
Finished Jun 25 05:02:56 PM PDT 24
Peak memory 206796 kb
Host smart-a7996ca6-6041-4a4e-ac55-70f79c38a79a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1242653436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.1242653436
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.1778242243
Short name T1855
Test name
Test status
Simulation time 147498471 ps
CPU time 0.79 seconds
Started Jun 25 05:02:21 PM PDT 24
Finished Jun 25 05:02:23 PM PDT 24
Peak memory 206576 kb
Host smart-2acc3825-9886-4ee1-be66-beff6888cb06
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1778242243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.1778242243
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.280943613
Short name T924
Test name
Test status
Simulation time 149444980 ps
CPU time 0.82 seconds
Started Jun 25 05:02:26 PM PDT 24
Finished Jun 25 05:02:30 PM PDT 24
Peak memory 206508 kb
Host smart-3683b839-2291-46e0-8457-f7cf14296df7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28094
3613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.280943613
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.2693908820
Short name T116
Test name
Test status
Simulation time 233223019 ps
CPU time 0.91 seconds
Started Jun 25 05:02:12 PM PDT 24
Finished Jun 25 05:02:15 PM PDT 24
Peak memory 206508 kb
Host smart-224ee794-9610-4e83-997e-41c81502f35f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26939
08820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.2693908820
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.3532852756
Short name T871
Test name
Test status
Simulation time 185648096 ps
CPU time 0.88 seconds
Started Jun 25 05:02:21 PM PDT 24
Finished Jun 25 05:02:24 PM PDT 24
Peak memory 206576 kb
Host smart-bbaa55a8-60a1-44d7-b7a6-84c53b991505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35328
52756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.3532852756
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.2899941670
Short name T388
Test name
Test status
Simulation time 161689805 ps
CPU time 0.75 seconds
Started Jun 25 05:02:11 PM PDT 24
Finished Jun 25 05:02:14 PM PDT 24
Peak memory 206376 kb
Host smart-7cf397cd-32bc-4f7a-acb8-5247202c31ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28999
41670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.2899941670
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.3139024137
Short name T996
Test name
Test status
Simulation time 185382544 ps
CPU time 0.87 seconds
Started Jun 25 05:02:23 PM PDT 24
Finished Jun 25 05:02:25 PM PDT 24
Peak memory 206496 kb
Host smart-34172bf7-5089-453c-b51c-4f7b989e6866
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31390
24137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.3139024137
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.116092413
Short name T2194
Test name
Test status
Simulation time 149733184 ps
CPU time 0.78 seconds
Started Jun 25 05:02:23 PM PDT 24
Finished Jun 25 05:02:25 PM PDT 24
Peak memory 206460 kb
Host smart-88ab18f7-f4f5-4006-b0a5-9dd2c78bc564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11609
2413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.116092413
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.3297218396
Short name T517
Test name
Test status
Simulation time 194364385 ps
CPU time 0.87 seconds
Started Jun 25 05:02:15 PM PDT 24
Finished Jun 25 05:02:17 PM PDT 24
Peak memory 206572 kb
Host smart-e7ca4b96-8d9c-4a7c-a062-ad6b4e9c9c96
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3297218396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.3297218396
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.3260629547
Short name T1735
Test name
Test status
Simulation time 147770135 ps
CPU time 0.75 seconds
Started Jun 25 05:02:24 PM PDT 24
Finished Jun 25 05:02:28 PM PDT 24
Peak memory 206480 kb
Host smart-c96409bd-ac76-4a15-a163-97ae648c54b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32606
29547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.3260629547
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.42215071
Short name T1561
Test name
Test status
Simulation time 35976292 ps
CPU time 0.65 seconds
Started Jun 25 05:02:22 PM PDT 24
Finished Jun 25 05:02:24 PM PDT 24
Peak memory 206572 kb
Host smart-03479afc-745e-4478-b3ea-fccd749f316a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42215
071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.42215071
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.2835051379
Short name T1705
Test name
Test status
Simulation time 20273895334 ps
CPU time 40.46 seconds
Started Jun 25 05:02:17 PM PDT 24
Finished Jun 25 05:02:58 PM PDT 24
Peak memory 206800 kb
Host smart-01fa7890-6f2f-4183-8b41-ecc4550a21c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28350
51379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.2835051379
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.4230634933
Short name T2141
Test name
Test status
Simulation time 224440759 ps
CPU time 0.86 seconds
Started Jun 25 05:02:15 PM PDT 24
Finished Jun 25 05:02:17 PM PDT 24
Peak memory 206516 kb
Host smart-2b996e99-0059-4c41-90eb-1f63d1574146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42306
34933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.4230634933
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.3686637558
Short name T878
Test name
Test status
Simulation time 241145093 ps
CPU time 0.91 seconds
Started Jun 25 05:02:24 PM PDT 24
Finished Jun 25 05:02:27 PM PDT 24
Peak memory 206496 kb
Host smart-94951b2d-3a7f-4407-81ec-43f80e52df73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36866
37558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.3686637558
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.817411773
Short name T637
Test name
Test status
Simulation time 197763237 ps
CPU time 0.83 seconds
Started Jun 25 05:02:25 PM PDT 24
Finished Jun 25 05:02:30 PM PDT 24
Peak memory 206592 kb
Host smart-2bbe2cfd-3fed-4bad-9fda-dd8115d3a0b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81741
1773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.817411773
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.2087499677
Short name T726
Test name
Test status
Simulation time 151762725 ps
CPU time 0.8 seconds
Started Jun 25 05:02:11 PM PDT 24
Finished Jun 25 05:02:14 PM PDT 24
Peak memory 206496 kb
Host smart-e59605fa-5645-4f89-9c04-42bb7cb64499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20874
99677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.2087499677
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.2281219175
Short name T641
Test name
Test status
Simulation time 197287674 ps
CPU time 0.8 seconds
Started Jun 25 05:02:14 PM PDT 24
Finished Jun 25 05:02:16 PM PDT 24
Peak memory 206568 kb
Host smart-e31b65c3-51b2-4cbb-8450-9f5217d70b40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22812
19175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.2281219175
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.3223330813
Short name T439
Test name
Test status
Simulation time 205540093 ps
CPU time 0.81 seconds
Started Jun 25 05:02:23 PM PDT 24
Finished Jun 25 05:02:26 PM PDT 24
Peak memory 206560 kb
Host smart-66d0e589-24cf-4c1c-aa42-30b248c9d9df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32233
30813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.3223330813
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.2713142746
Short name T2072
Test name
Test status
Simulation time 151772672 ps
CPU time 0.84 seconds
Started Jun 25 05:02:29 PM PDT 24
Finished Jun 25 05:02:32 PM PDT 24
Peak memory 206572 kb
Host smart-c733fe17-7c46-4a2e-a86f-1e21557635e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27131
42746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.2713142746
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.3305290598
Short name T1562
Test name
Test status
Simulation time 277695704 ps
CPU time 1.11 seconds
Started Jun 25 05:02:24 PM PDT 24
Finished Jun 25 05:02:28 PM PDT 24
Peak memory 206516 kb
Host smart-ff733008-fa94-4fa3-96fb-45601e0f772f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33052
90598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.3305290598
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.4084345312
Short name T88
Test name
Test status
Simulation time 4801655992 ps
CPU time 35.2 seconds
Started Jun 25 05:02:23 PM PDT 24
Finished Jun 25 05:03:01 PM PDT 24
Peak memory 206972 kb
Host smart-55614cbb-1538-449d-8772-a2dcc1ae45fd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4084345312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.4084345312
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.2343896900
Short name T2124
Test name
Test status
Simulation time 179602597 ps
CPU time 0.86 seconds
Started Jun 25 05:02:24 PM PDT 24
Finished Jun 25 05:02:27 PM PDT 24
Peak memory 206600 kb
Host smart-1609e6d7-3366-46b4-8023-8c29f4ef0542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23438
96900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.2343896900
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.155539765
Short name T1147
Test name
Test status
Simulation time 187718522 ps
CPU time 0.87 seconds
Started Jun 25 05:02:26 PM PDT 24
Finished Jun 25 05:02:30 PM PDT 24
Peak memory 206496 kb
Host smart-dc6a0b5e-67e5-425c-b0fc-124dca9b6274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15553
9765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.155539765
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.2136058384
Short name T1289
Test name
Test status
Simulation time 7291142397 ps
CPU time 65.97 seconds
Started Jun 25 05:02:26 PM PDT 24
Finished Jun 25 05:03:35 PM PDT 24
Peak memory 206892 kb
Host smart-5fb7688a-c308-48bf-aaec-3c23f389dcf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21360
58384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.2136058384
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.935096236
Short name T1468
Test name
Test status
Simulation time 4042386227 ps
CPU time 4.76 seconds
Started Jun 25 04:56:46 PM PDT 24
Finished Jun 25 04:56:52 PM PDT 24
Peak memory 206916 kb
Host smart-2996bbed-211c-4de1-96cc-c86ed4e47f24
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=935096236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.935096236
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.1337434186
Short name T1150
Test name
Test status
Simulation time 13405530243 ps
CPU time 12.55 seconds
Started Jun 25 04:56:46 PM PDT 24
Finished Jun 25 04:57:00 PM PDT 24
Peak memory 206736 kb
Host smart-bb5babea-7e07-4043-bd63-1b2c37d5a123
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1337434186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.1337434186
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.1233138147
Short name T2092
Test name
Test status
Simulation time 23369267254 ps
CPU time 24.56 seconds
Started Jun 25 04:56:46 PM PDT 24
Finished Jun 25 04:57:13 PM PDT 24
Peak memory 206724 kb
Host smart-306bcbe1-f366-4878-84e4-8e246d5c8eb0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1233138147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.1233138147
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.2570223708
Short name T2284
Test name
Test status
Simulation time 193510191 ps
CPU time 0.83 seconds
Started Jun 25 04:56:44 PM PDT 24
Finished Jun 25 04:56:46 PM PDT 24
Peak memory 206584 kb
Host smart-f7def9ce-4fa3-4f71-9674-2c53db0df62c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25702
23708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.2570223708
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.1640496913
Short name T52
Test name
Test status
Simulation time 227011659 ps
CPU time 0.89 seconds
Started Jun 25 04:56:44 PM PDT 24
Finished Jun 25 04:56:46 PM PDT 24
Peak memory 206512 kb
Host smart-b7f980e0-006c-4646-b89c-5c03dd0ad081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16404
96913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.1640496913
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.424292972
Short name T91
Test name
Test status
Simulation time 188890549 ps
CPU time 0.83 seconds
Started Jun 25 04:56:48 PM PDT 24
Finished Jun 25 04:56:50 PM PDT 24
Peak memory 206568 kb
Host smart-3ede75bf-7849-4fa0-9c0c-56f68f9d54a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42429
2972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.424292972
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.4183426299
Short name T1791
Test name
Test status
Simulation time 159826093 ps
CPU time 0.76 seconds
Started Jun 25 04:56:45 PM PDT 24
Finished Jun 25 04:56:48 PM PDT 24
Peak memory 206572 kb
Host smart-5cc76fdb-65ae-473d-88f5-18303c6d9a8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41834
26299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.4183426299
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.4120037430
Short name T1476
Test name
Test status
Simulation time 322706821 ps
CPU time 1.17 seconds
Started Jun 25 04:56:45 PM PDT 24
Finished Jun 25 04:56:47 PM PDT 24
Peak memory 206468 kb
Host smart-0eb38d29-181b-43b3-ae0d-e7cc93c87d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41200
37430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.4120037430
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.748209643
Short name T1772
Test name
Test status
Simulation time 1447668463 ps
CPU time 3.38 seconds
Started Jun 25 04:56:46 PM PDT 24
Finished Jun 25 04:56:51 PM PDT 24
Peak memory 206788 kb
Host smart-9c86abd5-0710-4616-839f-d77561116642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74820
9643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.748209643
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.631219235
Short name T181
Test name
Test status
Simulation time 17850938975 ps
CPU time 39.73 seconds
Started Jun 25 04:56:46 PM PDT 24
Finished Jun 25 04:57:27 PM PDT 24
Peak memory 206856 kb
Host smart-5c701e86-5939-4c90-b238-66ca29508f3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63121
9235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.631219235
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.1338000601
Short name T2192
Test name
Test status
Simulation time 467589720 ps
CPU time 1.31 seconds
Started Jun 25 04:56:45 PM PDT 24
Finished Jun 25 04:56:48 PM PDT 24
Peak memory 206516 kb
Host smart-68c0eaff-d63c-4c5f-bac1-fcf6df5351b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13380
00601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.1338000601
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.3669833001
Short name T969
Test name
Test status
Simulation time 144724385 ps
CPU time 0.78 seconds
Started Jun 25 04:56:47 PM PDT 24
Finished Jun 25 04:56:50 PM PDT 24
Peak memory 206500 kb
Host smart-f56fa078-bb7f-44a1-aa87-fed76f30bbdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36698
33001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.3669833001
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.3372526633
Short name T944
Test name
Test status
Simulation time 54038295 ps
CPU time 0.67 seconds
Started Jun 25 04:56:45 PM PDT 24
Finished Jun 25 04:56:47 PM PDT 24
Peak memory 206596 kb
Host smart-f26bc5b4-6327-4ed0-b9ea-8e9d03b9f57e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33725
26633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.3372526633
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.2353697334
Short name T540
Test name
Test status
Simulation time 866518210 ps
CPU time 2.13 seconds
Started Jun 25 04:56:46 PM PDT 24
Finished Jun 25 04:56:49 PM PDT 24
Peak memory 206696 kb
Host smart-e1257006-52a8-43bc-8bf7-b80f663bbd7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23536
97334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.2353697334
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.1542150543
Short name T382
Test name
Test status
Simulation time 287324390 ps
CPU time 2.29 seconds
Started Jun 25 04:56:48 PM PDT 24
Finished Jun 25 04:56:52 PM PDT 24
Peak memory 206820 kb
Host smart-57483ca0-0c27-4954-b0a0-a9bd95df24ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15421
50543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.1542150543
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.1541890272
Short name T1334
Test name
Test status
Simulation time 160773548 ps
CPU time 0.82 seconds
Started Jun 25 04:57:00 PM PDT 24
Finished Jun 25 04:57:02 PM PDT 24
Peak memory 206604 kb
Host smart-d76b0fcc-e4ab-4b57-a0fc-288ae9387f21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15418
90272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.1541890272
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.2771967572
Short name T2280
Test name
Test status
Simulation time 166259062 ps
CPU time 0.78 seconds
Started Jun 25 04:56:53 PM PDT 24
Finished Jun 25 04:56:55 PM PDT 24
Peak memory 206496 kb
Host smart-1ccd4b89-f1cd-497c-a7e2-dbedf40d806b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27719
67572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.2771967572
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.1476998682
Short name T323
Test name
Test status
Simulation time 154084394 ps
CPU time 0.81 seconds
Started Jun 25 04:56:44 PM PDT 24
Finished Jun 25 04:56:46 PM PDT 24
Peak memory 206568 kb
Host smart-6ca1541e-41e6-48fd-afff-86f653e76ad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14769
98682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.1476998682
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.2015621975
Short name T1747
Test name
Test status
Simulation time 157409054 ps
CPU time 0.83 seconds
Started Jun 25 04:56:48 PM PDT 24
Finished Jun 25 04:56:50 PM PDT 24
Peak memory 206576 kb
Host smart-780a4ace-705d-424f-806f-32fe4118b59f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20156
21975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.2015621975
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.2863253526
Short name T854
Test name
Test status
Simulation time 23366632089 ps
CPU time 29.52 seconds
Started Jun 25 04:56:44 PM PDT 24
Finished Jun 25 04:57:14 PM PDT 24
Peak memory 206680 kb
Host smart-b6197e1b-c3fe-486a-8dd3-a90d809a3cb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28632
53526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.2863253526
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.4138281236
Short name T1987
Test name
Test status
Simulation time 3332209071 ps
CPU time 3.88 seconds
Started Jun 25 04:56:45 PM PDT 24
Finished Jun 25 04:56:51 PM PDT 24
Peak memory 206716 kb
Host smart-f90dfb58-806a-4756-8210-157a259fcae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41382
81236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.4138281236
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.3122332049
Short name T618
Test name
Test status
Simulation time 10403362200 ps
CPU time 299.09 seconds
Started Jun 25 04:56:50 PM PDT 24
Finished Jun 25 05:01:51 PM PDT 24
Peak memory 206872 kb
Host smart-2cd73bda-01cb-437b-8a07-20648e813d0d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3122332049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.3122332049
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.955168385
Short name T523
Test name
Test status
Simulation time 284989198 ps
CPU time 0.96 seconds
Started Jun 25 04:57:01 PM PDT 24
Finished Jun 25 04:57:02 PM PDT 24
Peak memory 206516 kb
Host smart-235ce8f2-1a80-4a77-928b-27337f101328
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=955168385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.955168385
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.725398282
Short name T2027
Test name
Test status
Simulation time 186512644 ps
CPU time 0.82 seconds
Started Jun 25 04:56:44 PM PDT 24
Finished Jun 25 04:56:46 PM PDT 24
Peak memory 206520 kb
Host smart-bf20300e-e26d-47d7-865e-1ea41ae3fa8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72539
8282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.725398282
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.2722443633
Short name T710
Test name
Test status
Simulation time 3353836096 ps
CPU time 98.41 seconds
Started Jun 25 04:56:50 PM PDT 24
Finished Jun 25 04:58:31 PM PDT 24
Peak memory 206852 kb
Host smart-922bbdda-aa13-4df7-b18d-ade0e99b6a31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27224
43633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.2722443633
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.2329414935
Short name T1380
Test name
Test status
Simulation time 5611632471 ps
CPU time 156.93 seconds
Started Jun 25 04:56:46 PM PDT 24
Finished Jun 25 04:59:25 PM PDT 24
Peak memory 206948 kb
Host smart-0fe3ab04-75b9-41fb-be29-f2efe5f035ae
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2329414935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.2329414935
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.289730119
Short name T1414
Test name
Test status
Simulation time 166121609 ps
CPU time 0.8 seconds
Started Jun 25 04:57:04 PM PDT 24
Finished Jun 25 04:57:06 PM PDT 24
Peak memory 206076 kb
Host smart-25552a4e-78f0-4d21-9e6d-e08218c1dfbf
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=289730119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.289730119
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.2788119038
Short name T2348
Test name
Test status
Simulation time 139931334 ps
CPU time 0.79 seconds
Started Jun 25 04:56:46 PM PDT 24
Finished Jun 25 04:56:48 PM PDT 24
Peak memory 206576 kb
Host smart-003ac866-534a-41ea-8019-c2ab4cb7ed78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27881
19038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.2788119038
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.1728265642
Short name T122
Test name
Test status
Simulation time 211239447 ps
CPU time 0.85 seconds
Started Jun 25 04:56:48 PM PDT 24
Finished Jun 25 04:56:51 PM PDT 24
Peak memory 206560 kb
Host smart-699f7748-5c02-408b-91f8-04553c693080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17282
65642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.1728265642
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.3701803298
Short name T2256
Test name
Test status
Simulation time 193527587 ps
CPU time 0.85 seconds
Started Jun 25 04:56:47 PM PDT 24
Finished Jun 25 04:56:50 PM PDT 24
Peak memory 206512 kb
Host smart-e9da384c-d878-49a6-a68e-94ddea759ca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37018
03298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.3701803298
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.2556412862
Short name T1094
Test name
Test status
Simulation time 166758894 ps
CPU time 0.84 seconds
Started Jun 25 04:56:47 PM PDT 24
Finished Jun 25 04:56:50 PM PDT 24
Peak memory 206516 kb
Host smart-932523f7-13ea-4a92-bc4b-90c8b945adbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25564
12862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.2556412862
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.778064569
Short name T2358
Test name
Test status
Simulation time 189064456 ps
CPU time 0.87 seconds
Started Jun 25 04:56:46 PM PDT 24
Finished Jun 25 04:56:48 PM PDT 24
Peak memory 206476 kb
Host smart-15e10b26-e6ce-4432-8447-fd9b6ce8f435
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77806
4569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.778064569
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.3478958451
Short name T1360
Test name
Test status
Simulation time 171935526 ps
CPU time 0.79 seconds
Started Jun 25 04:57:04 PM PDT 24
Finished Jun 25 04:57:06 PM PDT 24
Peak memory 206372 kb
Host smart-af11fef5-9912-4f0e-82a5-fd357bf0bbd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34789
58451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.3478958451
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.2645231276
Short name T29
Test name
Test status
Simulation time 231001804 ps
CPU time 0.96 seconds
Started Jun 25 04:56:51 PM PDT 24
Finished Jun 25 04:56:54 PM PDT 24
Peak memory 206500 kb
Host smart-55a303d7-6ec1-4488-af0a-91cdf0f6c03a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2645231276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.2645231276
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.2028525163
Short name T199
Test name
Test status
Simulation time 219165220 ps
CPU time 0.98 seconds
Started Jun 25 04:56:49 PM PDT 24
Finished Jun 25 04:56:52 PM PDT 24
Peak memory 206508 kb
Host smart-261a0be1-343e-433e-920f-d9279978af3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20285
25163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.2028525163
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.3144876349
Short name T911
Test name
Test status
Simulation time 141611223 ps
CPU time 0.74 seconds
Started Jun 25 04:56:50 PM PDT 24
Finished Jun 25 04:56:53 PM PDT 24
Peak memory 206584 kb
Host smart-fca7813c-7074-4583-8f20-7fe977939eb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31448
76349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.3144876349
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.1297003768
Short name T402
Test name
Test status
Simulation time 35076842 ps
CPU time 0.67 seconds
Started Jun 25 04:56:52 PM PDT 24
Finished Jun 25 04:56:54 PM PDT 24
Peak memory 206564 kb
Host smart-033d5f84-9723-4893-b67f-15108ff4bee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12970
03768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.1297003768
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.2627157539
Short name T2478
Test name
Test status
Simulation time 20811405132 ps
CPU time 44.88 seconds
Started Jun 25 04:56:45 PM PDT 24
Finished Jun 25 04:57:32 PM PDT 24
Peak memory 206860 kb
Host smart-128f9415-ccd3-48b9-b2e7-9b43fe028246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26271
57539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.2627157539
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.1041172905
Short name T1692
Test name
Test status
Simulation time 150703302 ps
CPU time 0.77 seconds
Started Jun 25 04:56:50 PM PDT 24
Finished Jun 25 04:56:53 PM PDT 24
Peak memory 206500 kb
Host smart-51911bd1-9352-4a42-bcd5-89cd6e7058f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10411
72905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.1041172905
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.70343953
Short name T147
Test name
Test status
Simulation time 195844081 ps
CPU time 0.89 seconds
Started Jun 25 04:56:50 PM PDT 24
Finished Jun 25 04:56:53 PM PDT 24
Peak memory 206576 kb
Host smart-bcfaaa71-95fa-4613-9b16-12fed34b73e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70343
953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.70343953
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.3245331700
Short name T2373
Test name
Test status
Simulation time 14542249363 ps
CPU time 314.08 seconds
Started Jun 25 04:56:50 PM PDT 24
Finished Jun 25 05:02:06 PM PDT 24
Peak memory 206952 kb
Host smart-e8091fb1-716c-4cb0-a87d-b5f3b03ca44c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3245331700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.3245331700
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.2244667769
Short name T165
Test name
Test status
Simulation time 17950519333 ps
CPU time 134.23 seconds
Started Jun 25 04:56:50 PM PDT 24
Finished Jun 25 04:59:06 PM PDT 24
Peak memory 206844 kb
Host smart-52323907-bb81-4030-b1a4-ca43dfde0807
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2244667769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.2244667769
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.3885893836
Short name T2487
Test name
Test status
Simulation time 20092054612 ps
CPU time 113.92 seconds
Started Jun 25 04:56:53 PM PDT 24
Finished Jun 25 04:58:48 PM PDT 24
Peak memory 206892 kb
Host smart-3d0a8efc-d7ac-4b3f-aabe-f62ec14bb341
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3885893836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.3885893836
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.559001489
Short name T658
Test name
Test status
Simulation time 177594196 ps
CPU time 0.82 seconds
Started Jun 25 04:57:06 PM PDT 24
Finished Jun 25 04:57:08 PM PDT 24
Peak memory 206620 kb
Host smart-6ee5ff13-eaf4-4161-ad11-b8f9037af3f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55900
1489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.559001489
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.2445517429
Short name T1483
Test name
Test status
Simulation time 184074836 ps
CPU time 0.95 seconds
Started Jun 25 04:56:50 PM PDT 24
Finished Jun 25 04:56:53 PM PDT 24
Peak memory 206572 kb
Host smart-1f3be0ab-78a2-475e-8e88-73bf79105913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24455
17429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.2445517429
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.2943291705
Short name T2011
Test name
Test status
Simulation time 182318031 ps
CPU time 0.83 seconds
Started Jun 25 04:56:50 PM PDT 24
Finished Jun 25 04:56:53 PM PDT 24
Peak memory 206580 kb
Host smart-5d567ea1-50da-4207-aa60-c5321eb519fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29432
91705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.2943291705
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.3163966431
Short name T81
Test name
Test status
Simulation time 161024221 ps
CPU time 0.78 seconds
Started Jun 25 04:56:53 PM PDT 24
Finished Jun 25 04:56:54 PM PDT 24
Peak memory 206504 kb
Host smart-06db989c-fac9-4e7f-a8af-1219fe5f7793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31639
66431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.3163966431
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.2249912851
Short name T206
Test name
Test status
Simulation time 561921956 ps
CPU time 1.59 seconds
Started Jun 25 04:56:54 PM PDT 24
Finished Jun 25 04:56:57 PM PDT 24
Peak memory 225436 kb
Host smart-82d43493-6df4-412c-b95d-460c56b968fb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2249912851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.2249912851
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.3773661591
Short name T54
Test name
Test status
Simulation time 358071910 ps
CPU time 1.25 seconds
Started Jun 25 04:56:54 PM PDT 24
Finished Jun 25 04:56:57 PM PDT 24
Peak memory 206500 kb
Host smart-a69ded63-3531-498b-9e3f-c61331fe3239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37736
61591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.3773661591
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.675387559
Short name T1249
Test name
Test status
Simulation time 155591181 ps
CPU time 0.77 seconds
Started Jun 25 04:56:50 PM PDT 24
Finished Jun 25 04:56:53 PM PDT 24
Peak memory 206516 kb
Host smart-980f2599-ce37-4d62-aaf1-23554f92051b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67538
7559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.675387559
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.2550739532
Short name T2207
Test name
Test status
Simulation time 189231611 ps
CPU time 0.81 seconds
Started Jun 25 04:56:53 PM PDT 24
Finished Jun 25 04:56:56 PM PDT 24
Peak memory 206496 kb
Host smart-e8659c2c-6892-4e01-a3f5-ed003107d4df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25507
39532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.2550739532
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.2374506471
Short name T2279
Test name
Test status
Simulation time 214569238 ps
CPU time 0.87 seconds
Started Jun 25 04:56:53 PM PDT 24
Finished Jun 25 04:56:56 PM PDT 24
Peak memory 206588 kb
Host smart-c418df28-c2ca-4417-9e82-de9f0e12395f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23745
06471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.2374506471
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.2138649079
Short name T1544
Test name
Test status
Simulation time 12096253504 ps
CPU time 334.64 seconds
Started Jun 25 04:56:53 PM PDT 24
Finished Jun 25 05:02:30 PM PDT 24
Peak memory 206872 kb
Host smart-5f693734-fd02-47e1-94ee-b48ddbc5dcf3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2138649079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.2138649079
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.1455831037
Short name T1620
Test name
Test status
Simulation time 178064417 ps
CPU time 0.82 seconds
Started Jun 25 04:56:48 PM PDT 24
Finished Jun 25 04:56:50 PM PDT 24
Peak memory 206576 kb
Host smart-4149cfbe-be4e-4915-88fb-572597e10626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14558
31037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.1455831037
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.1475068602
Short name T1305
Test name
Test status
Simulation time 239184543 ps
CPU time 0.88 seconds
Started Jun 25 04:56:47 PM PDT 24
Finished Jun 25 04:56:50 PM PDT 24
Peak memory 206572 kb
Host smart-a58f2bd7-d3df-4b80-a1b2-e7837a48c703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14750
68602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.1475068602
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.1161694412
Short name T566
Test name
Test status
Simulation time 8070991745 ps
CPU time 59.54 seconds
Started Jun 25 04:56:48 PM PDT 24
Finished Jun 25 04:57:49 PM PDT 24
Peak memory 206936 kb
Host smart-44cc6b01-6f7a-4eb4-9f30-eded407aab8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11616
94412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.1161694412
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.3312497224
Short name T1913
Test name
Test status
Simulation time 14810894149 ps
CPU time 104.24 seconds
Started Jun 25 04:56:53 PM PDT 24
Finished Jun 25 04:58:38 PM PDT 24
Peak memory 206928 kb
Host smart-70dd0b73-26ca-4294-8a5e-925c6c605df9
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3312497224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.3312497224
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.2312890642
Short name T1500
Test name
Test status
Simulation time 3727543413 ps
CPU time 4.3 seconds
Started Jun 25 05:02:22 PM PDT 24
Finished Jun 25 05:02:28 PM PDT 24
Peak memory 206720 kb
Host smart-457e751c-2655-4df9-abcf-b8a1f9df90e0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2312890642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.2312890642
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.2735379335
Short name T1087
Test name
Test status
Simulation time 13316297147 ps
CPU time 12.6 seconds
Started Jun 25 05:02:26 PM PDT 24
Finished Jun 25 05:02:42 PM PDT 24
Peak memory 206736 kb
Host smart-4b7c8ea5-29d6-4707-bb6b-211e2591f572
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2735379335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.2735379335
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.2326358852
Short name T691
Test name
Test status
Simulation time 23415424992 ps
CPU time 21.69 seconds
Started Jun 25 05:02:24 PM PDT 24
Finished Jun 25 05:02:48 PM PDT 24
Peak memory 206828 kb
Host smart-8a036762-8fbd-4de3-b527-10563d79dc2c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2326358852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.2326358852
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.2344845191
Short name T2400
Test name
Test status
Simulation time 156489032 ps
CPU time 0.81 seconds
Started Jun 25 05:02:22 PM PDT 24
Finished Jun 25 05:02:24 PM PDT 24
Peak memory 206500 kb
Host smart-4bcfca55-bea3-4860-b003-f17707518387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23448
45191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.2344845191
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.4199912630
Short name T1634
Test name
Test status
Simulation time 170515374 ps
CPU time 0.83 seconds
Started Jun 25 05:02:23 PM PDT 24
Finished Jun 25 05:02:26 PM PDT 24
Peak memory 206572 kb
Host smart-c44ef971-3a52-48af-8ef7-092ecfaf02f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41999
12630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.4199912630
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.2462898979
Short name T2246
Test name
Test status
Simulation time 409527194 ps
CPU time 1.35 seconds
Started Jun 25 05:02:23 PM PDT 24
Finished Jun 25 05:02:27 PM PDT 24
Peak memory 206448 kb
Host smart-41fbb1b9-ee15-4eb4-bf76-344f5da3e796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24628
98979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.2462898979
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.524198680
Short name T1652
Test name
Test status
Simulation time 619684894 ps
CPU time 1.69 seconds
Started Jun 25 05:02:25 PM PDT 24
Finished Jun 25 05:02:30 PM PDT 24
Peak memory 206508 kb
Host smart-9fd8299e-b89b-4d7f-96f3-5c29f6122bc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52419
8680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.524198680
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.3380690798
Short name T97
Test name
Test status
Simulation time 8746880457 ps
CPU time 15.91 seconds
Started Jun 25 05:02:24 PM PDT 24
Finished Jun 25 05:02:43 PM PDT 24
Peak memory 206840 kb
Host smart-32d5e1df-ba4c-425a-b9bf-10c633ec1ad3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33806
90798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.3380690798
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.518732574
Short name T1221
Test name
Test status
Simulation time 484109332 ps
CPU time 1.59 seconds
Started Jun 25 05:02:25 PM PDT 24
Finished Jun 25 05:02:30 PM PDT 24
Peak memory 206568 kb
Host smart-b2b82b6e-1d5e-4313-93d5-754727e6faea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51873
2574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.518732574
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.3857132035
Short name T1316
Test name
Test status
Simulation time 138929444 ps
CPU time 0.78 seconds
Started Jun 25 05:02:24 PM PDT 24
Finished Jun 25 05:02:28 PM PDT 24
Peak memory 206568 kb
Host smart-23f853b5-675f-4956-a926-26e70e3d8d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38571
32035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.3857132035
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.2933305607
Short name T1238
Test name
Test status
Simulation time 94491383 ps
CPU time 0.73 seconds
Started Jun 25 05:02:28 PM PDT 24
Finished Jun 25 05:02:31 PM PDT 24
Peak memory 206576 kb
Host smart-1f4de7bd-5f90-4e01-9e51-022bf858610a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29333
05607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.2933305607
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.3656253053
Short name T2386
Test name
Test status
Simulation time 840905941 ps
CPU time 2.04 seconds
Started Jun 25 05:02:23 PM PDT 24
Finished Jun 25 05:02:28 PM PDT 24
Peak memory 206732 kb
Host smart-49b433ea-5e06-4f0f-8d1d-37bbe004358f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36562
53053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.3656253053
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.3220181191
Short name T817
Test name
Test status
Simulation time 190687030 ps
CPU time 2.11 seconds
Started Jun 25 05:02:28 PM PDT 24
Finished Jun 25 05:02:33 PM PDT 24
Peak memory 206708 kb
Host smart-d7e59b71-9e04-4aac-b087-2248cf781344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32201
81191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.3220181191
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.270394834
Short name T1051
Test name
Test status
Simulation time 152706314 ps
CPU time 0.76 seconds
Started Jun 25 05:02:21 PM PDT 24
Finished Jun 25 05:02:23 PM PDT 24
Peak memory 206596 kb
Host smart-8cbcff16-fb3b-41c1-a382-4d0ba2c218ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27039
4834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.270394834
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.357422815
Short name T1109
Test name
Test status
Simulation time 218916132 ps
CPU time 0.9 seconds
Started Jun 25 05:02:25 PM PDT 24
Finished Jun 25 05:02:30 PM PDT 24
Peak memory 206568 kb
Host smart-ea4c99db-14d5-4f5e-89ac-32a7f568e241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35742
2815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.357422815
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.1165278963
Short name T1788
Test name
Test status
Simulation time 231703329 ps
CPU time 0.89 seconds
Started Jun 25 05:02:25 PM PDT 24
Finished Jun 25 05:02:29 PM PDT 24
Peak memory 206496 kb
Host smart-ffea4b4b-f1dc-45ef-83d5-66b77789d29a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11652
78963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.1165278963
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.3825267993
Short name T2343
Test name
Test status
Simulation time 23297304141 ps
CPU time 22.5 seconds
Started Jun 25 05:02:25 PM PDT 24
Finished Jun 25 05:02:51 PM PDT 24
Peak memory 206628 kb
Host smart-8ac10649-1caf-433b-a1f6-08aea5789d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38252
67993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.3825267993
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.3265221597
Short name T2215
Test name
Test status
Simulation time 3265376858 ps
CPU time 3.57 seconds
Started Jun 25 05:02:26 PM PDT 24
Finished Jun 25 05:02:33 PM PDT 24
Peak memory 206600 kb
Host smart-5b0a6ea2-eaa0-40da-873f-fc1456e09fb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32652
21597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.3265221597
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.2454528596
Short name T475
Test name
Test status
Simulation time 14146531722 ps
CPU time 136.08 seconds
Started Jun 25 05:02:19 PM PDT 24
Finished Jun 25 05:04:36 PM PDT 24
Peak memory 206932 kb
Host smart-d9b1e6f3-c1c4-4b9e-87ef-124c6b6e6769
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2454528596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.2454528596
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.4251746575
Short name T1207
Test name
Test status
Simulation time 251209061 ps
CPU time 0.93 seconds
Started Jun 25 05:02:25 PM PDT 24
Finished Jun 25 05:02:30 PM PDT 24
Peak memory 206532 kb
Host smart-834d463e-b97d-4518-9947-cf3adbe7b9a4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4251746575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.4251746575
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.1358765046
Short name T2482
Test name
Test status
Simulation time 241027534 ps
CPU time 0.95 seconds
Started Jun 25 05:02:26 PM PDT 24
Finished Jun 25 05:02:31 PM PDT 24
Peak memory 206344 kb
Host smart-53033b9b-3f9c-4ba3-9d18-c73adf69b35c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13587
65046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.1358765046
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.113230890
Short name T1989
Test name
Test status
Simulation time 10944129779 ps
CPU time 304.68 seconds
Started Jun 25 05:02:21 PM PDT 24
Finished Jun 25 05:07:27 PM PDT 24
Peak memory 206952 kb
Host smart-46f119f3-68b3-475d-8e93-37a0e5b34141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11323
0890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.113230890
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.266063590
Short name T212
Test name
Test status
Simulation time 10825796637 ps
CPU time 288.67 seconds
Started Jun 25 05:02:26 PM PDT 24
Finished Jun 25 05:07:18 PM PDT 24
Peak memory 206728 kb
Host smart-e5d8e23a-4939-4d59-89d9-d3c8093a83fb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=266063590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.266063590
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.3036652519
Short name T1494
Test name
Test status
Simulation time 174604523 ps
CPU time 0.82 seconds
Started Jun 25 05:02:26 PM PDT 24
Finished Jun 25 05:02:30 PM PDT 24
Peak memory 206524 kb
Host smart-6fd85ab8-b8ea-45ff-9358-711d11dcd2fb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3036652519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.3036652519
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.1331184096
Short name T2193
Test name
Test status
Simulation time 152878298 ps
CPU time 0.81 seconds
Started Jun 25 05:02:27 PM PDT 24
Finished Jun 25 05:02:31 PM PDT 24
Peak memory 206596 kb
Host smart-fe2e788c-1b37-465a-9d00-d27679d3d2ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13311
84096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.1331184096
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.2861142080
Short name T1493
Test name
Test status
Simulation time 189158094 ps
CPU time 0.91 seconds
Started Jun 25 05:02:22 PM PDT 24
Finished Jun 25 05:02:24 PM PDT 24
Peak memory 206544 kb
Host smart-bc246a3d-0f74-4fad-83d2-8cf53e23fff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28611
42080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.2861142080
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.4263123345
Short name T785
Test name
Test status
Simulation time 165352146 ps
CPU time 0.8 seconds
Started Jun 25 05:02:21 PM PDT 24
Finished Jun 25 05:02:22 PM PDT 24
Peak memory 206564 kb
Host smart-5fad8229-93ad-401b-982e-b21631bef4b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42631
23345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.4263123345
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.961015458
Short name T1480
Test name
Test status
Simulation time 198282749 ps
CPU time 0.84 seconds
Started Jun 25 05:02:23 PM PDT 24
Finished Jun 25 05:02:26 PM PDT 24
Peak memory 206580 kb
Host smart-3eb3a938-920f-43c0-a5ad-68dd400bb5c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96101
5458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.961015458
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.2259921769
Short name T1733
Test name
Test status
Simulation time 195299111 ps
CPU time 0.95 seconds
Started Jun 25 05:02:24 PM PDT 24
Finished Jun 25 05:02:28 PM PDT 24
Peak memory 206572 kb
Host smart-79b8218d-892e-49b2-8b05-6b358c9170ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22599
21769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.2259921769
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.3605883084
Short name T413
Test name
Test status
Simulation time 158319277 ps
CPU time 0.78 seconds
Started Jun 25 05:02:28 PM PDT 24
Finished Jun 25 05:02:31 PM PDT 24
Peak memory 206568 kb
Host smart-7630fd5a-193e-45c3-ad18-aa1189e71a40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36058
83084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.3605883084
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.1018106073
Short name T477
Test name
Test status
Simulation time 221527015 ps
CPU time 0.94 seconds
Started Jun 25 05:02:27 PM PDT 24
Finished Jun 25 05:02:31 PM PDT 24
Peak memory 206588 kb
Host smart-c06b3f89-3d47-4750-99ae-014264129cd9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1018106073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.1018106073
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.3724643098
Short name T627
Test name
Test status
Simulation time 152400357 ps
CPU time 0.74 seconds
Started Jun 25 05:02:24 PM PDT 24
Finished Jun 25 05:02:28 PM PDT 24
Peak memory 206512 kb
Host smart-1a4c4001-c1e9-4aa2-bb0d-8db756e0eb06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37246
43098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.3724643098
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.3058316251
Short name T792
Test name
Test status
Simulation time 31500362 ps
CPU time 0.68 seconds
Started Jun 25 05:02:23 PM PDT 24
Finished Jun 25 05:02:26 PM PDT 24
Peak memory 206456 kb
Host smart-1859eb50-673f-4c33-aaca-cbbec9b4149a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30583
16251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.3058316251
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.1686589562
Short name T2046
Test name
Test status
Simulation time 20886051352 ps
CPU time 46.86 seconds
Started Jun 25 05:02:24 PM PDT 24
Finished Jun 25 05:03:14 PM PDT 24
Peak memory 206820 kb
Host smart-14a3db21-7b34-4113-80ed-28927751e18d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16865
89562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.1686589562
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.988554854
Short name T1453
Test name
Test status
Simulation time 185193151 ps
CPU time 0.86 seconds
Started Jun 25 05:02:24 PM PDT 24
Finished Jun 25 05:02:28 PM PDT 24
Peak memory 206572 kb
Host smart-797ff353-0c83-4b6e-bc3a-3955534196cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98855
4854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.988554854
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.2288761672
Short name T1010
Test name
Test status
Simulation time 183900908 ps
CPU time 0.87 seconds
Started Jun 25 05:02:24 PM PDT 24
Finished Jun 25 05:02:28 PM PDT 24
Peak memory 206496 kb
Host smart-a5b66650-51e8-40f7-81c5-5a5ebcff62e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22887
61672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.2288761672
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.525919639
Short name T763
Test name
Test status
Simulation time 203980616 ps
CPU time 0.81 seconds
Started Jun 25 05:02:23 PM PDT 24
Finished Jun 25 05:02:26 PM PDT 24
Peak memory 206580 kb
Host smart-0f943bf1-04ed-40d1-85d0-3ba77f9d3bcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52591
9639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.525919639
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.2906220512
Short name T1546
Test name
Test status
Simulation time 193352441 ps
CPU time 0.89 seconds
Started Jun 25 05:02:23 PM PDT 24
Finished Jun 25 05:02:27 PM PDT 24
Peak memory 206500 kb
Host smart-18b95dcc-215d-419a-9443-a835be041121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29062
20512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.2906220512
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.2003842574
Short name T2074
Test name
Test status
Simulation time 203869028 ps
CPU time 0.84 seconds
Started Jun 25 05:02:29 PM PDT 24
Finished Jun 25 05:02:32 PM PDT 24
Peak memory 206572 kb
Host smart-7bfe20f0-4d6e-4ca3-a361-c0294070779d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20038
42574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.2003842574
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.1638389888
Short name T149
Test name
Test status
Simulation time 153733061 ps
CPU time 0.8 seconds
Started Jun 25 05:02:27 PM PDT 24
Finished Jun 25 05:02:31 PM PDT 24
Peak memory 206492 kb
Host smart-d2aad137-1865-44c2-833f-01c729009185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16383
89888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.1638389888
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.2359078122
Short name T1029
Test name
Test status
Simulation time 165697344 ps
CPU time 0.83 seconds
Started Jun 25 05:02:27 PM PDT 24
Finished Jun 25 05:02:31 PM PDT 24
Peak memory 206544 kb
Host smart-9b12d7e6-26f6-482f-aa08-e73cd5f46c49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23590
78122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.2359078122
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.2278348959
Short name T1799
Test name
Test status
Simulation time 300585273 ps
CPU time 1 seconds
Started Jun 25 05:02:24 PM PDT 24
Finished Jun 25 05:02:27 PM PDT 24
Peak memory 206584 kb
Host smart-fed04ec0-92da-4c0c-9578-756bd5d2108f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22783
48959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.2278348959
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.2941485076
Short name T453
Test name
Test status
Simulation time 7364820341 ps
CPU time 198.39 seconds
Started Jun 25 05:02:25 PM PDT 24
Finished Jun 25 05:05:46 PM PDT 24
Peak memory 206980 kb
Host smart-9fcac961-29b1-47d2-94b8-3bb580ccd284
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2941485076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.2941485076
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.43933400
Short name T1247
Test name
Test status
Simulation time 168412458 ps
CPU time 0.8 seconds
Started Jun 25 05:02:26 PM PDT 24
Finished Jun 25 05:02:30 PM PDT 24
Peak memory 206608 kb
Host smart-10270d5c-0049-4a5c-9473-5179d68c1159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43933
400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.43933400
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.1016786517
Short name T1161
Test name
Test status
Simulation time 198418866 ps
CPU time 0.86 seconds
Started Jun 25 05:02:23 PM PDT 24
Finished Jun 25 05:02:25 PM PDT 24
Peak memory 206572 kb
Host smart-b52cd322-515d-4a93-aad1-0e8ae8803b3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10167
86517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.1016786517
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.4255011270
Short name T1542
Test name
Test status
Simulation time 10029189751 ps
CPU time 91.81 seconds
Started Jun 25 05:02:27 PM PDT 24
Finished Jun 25 05:04:02 PM PDT 24
Peak memory 206812 kb
Host smart-4b285075-0239-47f1-8f61-d2161694a667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42550
11270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.4255011270
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.3029529055
Short name T952
Test name
Test status
Simulation time 4108434500 ps
CPU time 5.46 seconds
Started Jun 25 05:02:24 PM PDT 24
Finished Jun 25 05:02:32 PM PDT 24
Peak memory 206792 kb
Host smart-b322da2c-6eac-42c8-b7e5-71faf1d675df
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3029529055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.3029529055
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.3300505623
Short name T2084
Test name
Test status
Simulation time 13456931239 ps
CPU time 14.3 seconds
Started Jun 25 05:02:25 PM PDT 24
Finished Jun 25 05:02:43 PM PDT 24
Peak memory 206896 kb
Host smart-d73aae34-d837-4ac3-a61b-a38c1afe9f8e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3300505623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.3300505623
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.3253922666
Short name T2307
Test name
Test status
Simulation time 23484118741 ps
CPU time 28.03 seconds
Started Jun 25 05:02:24 PM PDT 24
Finished Jun 25 05:02:56 PM PDT 24
Peak memory 206948 kb
Host smart-4a95e154-cfb1-4eff-a6d3-b443d1f0df89
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3253922666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.3253922666
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.3880021736
Short name T2502
Test name
Test status
Simulation time 172216362 ps
CPU time 0.78 seconds
Started Jun 25 05:02:23 PM PDT 24
Finished Jun 25 05:02:26 PM PDT 24
Peak memory 206560 kb
Host smart-a1237f50-f3e8-43b0-b77e-b6c35d78fdea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38800
21736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.3880021736
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.3032490603
Short name T514
Test name
Test status
Simulation time 156934644 ps
CPU time 0.81 seconds
Started Jun 25 05:02:27 PM PDT 24
Finished Jun 25 05:02:31 PM PDT 24
Peak memory 206520 kb
Host smart-cf2c3df5-e7c7-4132-bf22-c872451a4797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30324
90603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.3032490603
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.3978297062
Short name T1076
Test name
Test status
Simulation time 571979761 ps
CPU time 1.8 seconds
Started Jun 25 05:02:26 PM PDT 24
Finished Jun 25 05:02:31 PM PDT 24
Peak memory 206768 kb
Host smart-d0816be5-e8d5-4d31-be1f-6b14e7ab99a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39782
97062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.3978297062
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.2781650675
Short name T161
Test name
Test status
Simulation time 1115426497 ps
CPU time 2.62 seconds
Started Jun 25 05:02:36 PM PDT 24
Finished Jun 25 05:02:40 PM PDT 24
Peak memory 206716 kb
Host smart-fab2f3b0-584d-4f2c-8f70-6d45356eeaa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27816
50675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.2781650675
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.472103859
Short name T1232
Test name
Test status
Simulation time 21377390992 ps
CPU time 38.26 seconds
Started Jun 25 05:02:32 PM PDT 24
Finished Jun 25 05:03:12 PM PDT 24
Peak memory 206972 kb
Host smart-f65e07b4-89d1-46a2-a7a4-daa834ab2d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47210
3859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.472103859
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.3573112483
Short name T1363
Test name
Test status
Simulation time 349843982 ps
CPU time 1.08 seconds
Started Jun 25 05:02:31 PM PDT 24
Finished Jun 25 05:02:34 PM PDT 24
Peak memory 206508 kb
Host smart-ba142e63-902f-48c7-8096-1cecbf8a588a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35731
12483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.3573112483
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.469778693
Short name T312
Test name
Test status
Simulation time 146166909 ps
CPU time 0.74 seconds
Started Jun 25 05:02:32 PM PDT 24
Finished Jun 25 05:02:35 PM PDT 24
Peak memory 206588 kb
Host smart-cfffe805-648b-4d10-9321-de34bab0e9f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46977
8693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.469778693
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.266588327
Short name T320
Test name
Test status
Simulation time 42371256 ps
CPU time 0.66 seconds
Started Jun 25 05:02:34 PM PDT 24
Finished Jun 25 05:02:36 PM PDT 24
Peak memory 206596 kb
Host smart-58d79751-7c4a-44f5-b0da-d34fd8dc9560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26658
8327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.266588327
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.3001693542
Short name T687
Test name
Test status
Simulation time 960919453 ps
CPU time 2.19 seconds
Started Jun 25 05:02:32 PM PDT 24
Finished Jun 25 05:02:36 PM PDT 24
Peak memory 206732 kb
Host smart-7950cba2-e039-4e2f-b261-07ba18ba3c81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30016
93542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.3001693542
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.3637526571
Short name T711
Test name
Test status
Simulation time 343891798 ps
CPU time 2.12 seconds
Started Jun 25 05:02:33 PM PDT 24
Finished Jun 25 05:02:37 PM PDT 24
Peak memory 206816 kb
Host smart-6442fdd4-9c8a-487c-9934-7749a1b4e742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36375
26571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.3637526571
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.452179713
Short name T2281
Test name
Test status
Simulation time 235049022 ps
CPU time 0.94 seconds
Started Jun 25 05:02:34 PM PDT 24
Finished Jun 25 05:02:37 PM PDT 24
Peak memory 206504 kb
Host smart-d7937ca7-e892-43b7-89d8-c8f97c04cab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45217
9713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.452179713
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.1315559985
Short name T1280
Test name
Test status
Simulation time 186232032 ps
CPU time 0.79 seconds
Started Jun 25 05:02:34 PM PDT 24
Finished Jun 25 05:02:36 PM PDT 24
Peak memory 206484 kb
Host smart-301651cf-8aa6-4b93-9f03-119c2c2dfef5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13155
59985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.1315559985
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.370364752
Short name T344
Test name
Test status
Simulation time 204661204 ps
CPU time 0.82 seconds
Started Jun 25 05:02:35 PM PDT 24
Finished Jun 25 05:02:37 PM PDT 24
Peak memory 206452 kb
Host smart-c1d8fdf7-2727-4f9e-8622-8109b6c8069f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37036
4752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.370364752
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.2304161926
Short name T1503
Test name
Test status
Simulation time 166689756 ps
CPU time 0.84 seconds
Started Jun 25 05:02:36 PM PDT 24
Finished Jun 25 05:02:38 PM PDT 24
Peak memory 206508 kb
Host smart-8ae2dae0-18db-4366-9994-4b4f4e2cd7ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23041
61926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.2304161926
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.1628189339
Short name T365
Test name
Test status
Simulation time 23329317502 ps
CPU time 21.37 seconds
Started Jun 25 05:02:38 PM PDT 24
Finished Jun 25 05:03:00 PM PDT 24
Peak memory 206700 kb
Host smart-10b256aa-c4be-4c0f-8765-970853f786b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16281
89339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.1628189339
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.3762400484
Short name T1075
Test name
Test status
Simulation time 3272155563 ps
CPU time 4.55 seconds
Started Jun 25 05:02:32 PM PDT 24
Finished Jun 25 05:02:38 PM PDT 24
Peak memory 206700 kb
Host smart-ca321804-d9a5-4bd6-bf07-887f37048fed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37624
00484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.3762400484
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.3771364310
Short name T2202
Test name
Test status
Simulation time 15439942956 ps
CPU time 115.39 seconds
Started Jun 25 05:02:34 PM PDT 24
Finished Jun 25 05:04:31 PM PDT 24
Peak memory 206900 kb
Host smart-542b8767-428c-4e19-8e61-7938444d0ece
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3771364310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.3771364310
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.4248518908
Short name T1973
Test name
Test status
Simulation time 322504742 ps
CPU time 0.99 seconds
Started Jun 25 05:02:32 PM PDT 24
Finished Jun 25 05:02:35 PM PDT 24
Peak memory 206572 kb
Host smart-abf9dcad-a488-4e20-a62a-71ab37e59c56
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4248518908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.4248518908
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.553860783
Short name T648
Test name
Test status
Simulation time 191292438 ps
CPU time 0.85 seconds
Started Jun 25 05:02:33 PM PDT 24
Finished Jun 25 05:02:35 PM PDT 24
Peak memory 206576 kb
Host smart-73dce32b-6283-4c68-b939-811d8d89720e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55386
0783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.553860783
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.873952092
Short name T1624
Test name
Test status
Simulation time 5255087678 ps
CPU time 49.95 seconds
Started Jun 25 05:02:39 PM PDT 24
Finished Jun 25 05:03:30 PM PDT 24
Peak memory 206840 kb
Host smart-f05ad11c-599d-4c0c-b8ad-8ccf9e749b2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87395
2092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.873952092
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.4156968328
Short name T1254
Test name
Test status
Simulation time 14263497823 ps
CPU time 139.02 seconds
Started Jun 25 05:02:31 PM PDT 24
Finished Jun 25 05:04:51 PM PDT 24
Peak memory 206916 kb
Host smart-e149e400-2873-4db9-8e0c-ba845493a393
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4156968328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.4156968328
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.2438053864
Short name T441
Test name
Test status
Simulation time 175312963 ps
CPU time 0.87 seconds
Started Jun 25 05:02:34 PM PDT 24
Finished Jun 25 05:02:37 PM PDT 24
Peak memory 206500 kb
Host smart-484732a0-6b7f-48d0-bf46-d30d2cf440d3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2438053864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.2438053864
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.3205457379
Short name T2270
Test name
Test status
Simulation time 146675528 ps
CPU time 0.74 seconds
Started Jun 25 05:02:33 PM PDT 24
Finished Jun 25 05:02:35 PM PDT 24
Peak memory 206564 kb
Host smart-e28d1af4-87bd-41dd-af47-6087464721d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32054
57379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.3205457379
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.3755524317
Short name T1074
Test name
Test status
Simulation time 230556226 ps
CPU time 0.93 seconds
Started Jun 25 05:02:36 PM PDT 24
Finished Jun 25 05:02:38 PM PDT 24
Peak memory 206576 kb
Host smart-1717476c-8597-43be-a07b-8a8fe1c44cff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37555
24317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.3755524317
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.2020115277
Short name T2158
Test name
Test status
Simulation time 168375966 ps
CPU time 0.84 seconds
Started Jun 25 05:02:35 PM PDT 24
Finished Jun 25 05:02:37 PM PDT 24
Peak memory 206496 kb
Host smart-ec00bc02-28b9-4f36-9eb4-bec4413a6020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20201
15277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.2020115277
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.897263091
Short name T2239
Test name
Test status
Simulation time 164318977 ps
CPU time 0.75 seconds
Started Jun 25 05:02:34 PM PDT 24
Finished Jun 25 05:02:37 PM PDT 24
Peak memory 206480 kb
Host smart-01515974-0676-42cc-980f-075801c3381b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89726
3091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.897263091
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.261146544
Short name T2134
Test name
Test status
Simulation time 167393999 ps
CPU time 0.85 seconds
Started Jun 25 05:02:36 PM PDT 24
Finished Jun 25 05:02:38 PM PDT 24
Peak memory 206572 kb
Host smart-4c5191d3-d93b-46d6-aa1b-b66ee9d50690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26114
6544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.261146544
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.2378003470
Short name T1423
Test name
Test status
Simulation time 152538847 ps
CPU time 0.77 seconds
Started Jun 25 05:02:35 PM PDT 24
Finished Jun 25 05:02:38 PM PDT 24
Peak memory 206456 kb
Host smart-91f90695-33c9-4b18-bd19-fdc95040d0d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23780
03470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.2378003470
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.175682785
Short name T645
Test name
Test status
Simulation time 274047573 ps
CPU time 0.99 seconds
Started Jun 25 05:02:36 PM PDT 24
Finished Jun 25 05:02:38 PM PDT 24
Peak memory 206576 kb
Host smart-8cdd2d78-c234-4430-83be-7f7287f3539c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=175682785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.175682785
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.2137185208
Short name T1131
Test name
Test status
Simulation time 140141258 ps
CPU time 0.77 seconds
Started Jun 25 05:02:34 PM PDT 24
Finished Jun 25 05:02:37 PM PDT 24
Peak memory 206580 kb
Host smart-46a67009-05b1-43ab-8df0-f015d0e09a2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21371
85208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.2137185208
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.2462959403
Short name T983
Test name
Test status
Simulation time 33606589 ps
CPU time 0.67 seconds
Started Jun 25 05:02:34 PM PDT 24
Finished Jun 25 05:02:36 PM PDT 24
Peak memory 206512 kb
Host smart-f41aaeed-4ec7-4c73-aa96-8095112cc84d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24629
59403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.2462959403
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.1915954144
Short name T988
Test name
Test status
Simulation time 161713638 ps
CPU time 0.85 seconds
Started Jun 25 05:02:38 PM PDT 24
Finished Jun 25 05:02:39 PM PDT 24
Peak memory 206580 kb
Host smart-1ee759c9-5e9e-4dfc-bdf3-a293805e9722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19159
54144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.1915954144
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.2393637380
Short name T1771
Test name
Test status
Simulation time 250037177 ps
CPU time 0.9 seconds
Started Jun 25 05:02:33 PM PDT 24
Finished Jun 25 05:02:36 PM PDT 24
Peak memory 206492 kb
Host smart-56c10146-0eb7-4e94-8ff8-067dc2d24166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23936
37380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.2393637380
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.2329298401
Short name T2356
Test name
Test status
Simulation time 216867091 ps
CPU time 0.91 seconds
Started Jun 25 05:02:35 PM PDT 24
Finished Jun 25 05:02:38 PM PDT 24
Peak memory 206480 kb
Host smart-15d9c41a-6c77-4234-895e-d6183527d267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23292
98401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.2329298401
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.2675428934
Short name T573
Test name
Test status
Simulation time 166361179 ps
CPU time 0.79 seconds
Started Jun 25 05:02:32 PM PDT 24
Finished Jun 25 05:02:34 PM PDT 24
Peak memory 206600 kb
Host smart-6e615827-27e7-4d88-b2b4-7ef216e6a12f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26754
28934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.2675428934
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.4070531946
Short name T467
Test name
Test status
Simulation time 162269968 ps
CPU time 0.79 seconds
Started Jun 25 05:02:38 PM PDT 24
Finished Jun 25 05:02:39 PM PDT 24
Peak memory 206576 kb
Host smart-657eb8ab-800a-4252-826c-650daa5f02c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40705
31946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.4070531946
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.3119961392
Short name T1068
Test name
Test status
Simulation time 143435318 ps
CPU time 0.8 seconds
Started Jun 25 05:02:33 PM PDT 24
Finished Jun 25 05:02:36 PM PDT 24
Peak memory 206496 kb
Host smart-b377d7f5-521e-4de2-9026-4fd7f7ee8b25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31199
61392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.3119961392
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.2320864394
Short name T883
Test name
Test status
Simulation time 153438028 ps
CPU time 0.78 seconds
Started Jun 25 05:02:34 PM PDT 24
Finished Jun 25 05:02:37 PM PDT 24
Peak memory 206500 kb
Host smart-2fcf89df-0b03-4d61-b7ce-f4d08e2b0c5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23208
64394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.2320864394
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.1301118673
Short name T1211
Test name
Test status
Simulation time 250136062 ps
CPU time 0.94 seconds
Started Jun 25 05:02:32 PM PDT 24
Finished Jun 25 05:02:35 PM PDT 24
Peak memory 206512 kb
Host smart-5eba96d3-2f1d-4a72-aba5-a98f45c29d9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13011
18673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.1301118673
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.2683949240
Short name T559
Test name
Test status
Simulation time 13197384782 ps
CPU time 126.46 seconds
Started Jun 25 05:02:31 PM PDT 24
Finished Jun 25 05:04:39 PM PDT 24
Peak memory 206840 kb
Host smart-fc082bda-5d29-445e-b2ba-d5a219c7d863
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2683949240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.2683949240
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.2576863314
Short name T1300
Test name
Test status
Simulation time 188831093 ps
CPU time 0.84 seconds
Started Jun 25 05:02:31 PM PDT 24
Finished Jun 25 05:02:34 PM PDT 24
Peak memory 206500 kb
Host smart-e6dcbe5c-e9c9-4430-bb83-ae14d8abece2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25768
63314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.2576863314
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.4230248524
Short name T513
Test name
Test status
Simulation time 186543305 ps
CPU time 0.89 seconds
Started Jun 25 05:02:34 PM PDT 24
Finished Jun 25 05:02:37 PM PDT 24
Peak memory 206572 kb
Host smart-80f7a3da-3498-47d3-b593-9833ddc938bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42302
48524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.4230248524
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.265917706
Short name T342
Test name
Test status
Simulation time 4192582678 ps
CPU time 39.14 seconds
Started Jun 25 05:02:33 PM PDT 24
Finished Jun 25 05:03:13 PM PDT 24
Peak memory 206844 kb
Host smart-aa34687c-41aa-4e49-966e-6eff5531b7a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26591
7706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.265917706
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.2601055481
Short name T1193
Test name
Test status
Simulation time 4347905893 ps
CPU time 5.42 seconds
Started Jun 25 05:02:32 PM PDT 24
Finished Jun 25 05:02:39 PM PDT 24
Peak memory 206792 kb
Host smart-50234a88-d1d8-4fba-8ae5-112b46936350
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2601055481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.2601055481
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.3322650354
Short name T869
Test name
Test status
Simulation time 13417263332 ps
CPU time 13.08 seconds
Started Jun 25 05:02:38 PM PDT 24
Finished Jun 25 05:02:53 PM PDT 24
Peak memory 206864 kb
Host smart-19093005-2391-47c8-b907-c410d4aee8ff
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3322650354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.3322650354
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.3730016898
Short name T1934
Test name
Test status
Simulation time 23372017394 ps
CPU time 22.58 seconds
Started Jun 25 05:02:33 PM PDT 24
Finished Jun 25 05:02:57 PM PDT 24
Peak memory 206736 kb
Host smart-f487a48c-2933-40d0-b42d-106b979aea61
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3730016898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.3730016898
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.1467587387
Short name T1660
Test name
Test status
Simulation time 164660389 ps
CPU time 0.8 seconds
Started Jun 25 05:02:32 PM PDT 24
Finished Jun 25 05:02:35 PM PDT 24
Peak memory 206592 kb
Host smart-623da16c-65d5-433c-ba88-d97873120754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14675
87387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.1467587387
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.3614120467
Short name T939
Test name
Test status
Simulation time 176760800 ps
CPU time 0.84 seconds
Started Jun 25 05:02:39 PM PDT 24
Finished Jun 25 05:02:41 PM PDT 24
Peak memory 206504 kb
Host smart-139230a4-cbb9-40a7-b990-b330500f828e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36141
20467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.3614120467
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.3089355965
Short name T111
Test name
Test status
Simulation time 393875986 ps
CPU time 1.37 seconds
Started Jun 25 05:02:33 PM PDT 24
Finished Jun 25 05:02:36 PM PDT 24
Peak memory 206588 kb
Host smart-65263e85-6887-4f7b-aeca-8e5e3d36e32e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30893
55965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.3089355965
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.411710164
Short name T1219
Test name
Test status
Simulation time 1252953027 ps
CPU time 2.71 seconds
Started Jun 25 05:02:35 PM PDT 24
Finished Jun 25 05:02:39 PM PDT 24
Peak memory 206800 kb
Host smart-ae4c324a-c41d-41ac-8c8d-28b2e7a8149f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41171
0164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.411710164
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.4208267573
Short name T706
Test name
Test status
Simulation time 7122711255 ps
CPU time 14.86 seconds
Started Jun 25 05:02:31 PM PDT 24
Finished Jun 25 05:02:48 PM PDT 24
Peak memory 206868 kb
Host smart-fd0f984e-8da7-4523-86ac-f9f4f40b4790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42082
67573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.4208267573
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.3564988512
Short name T1950
Test name
Test status
Simulation time 457850271 ps
CPU time 1.52 seconds
Started Jun 25 05:02:33 PM PDT 24
Finished Jun 25 05:02:36 PM PDT 24
Peak memory 206484 kb
Host smart-569a6fd6-7108-4abb-a596-ebda4d0c4b2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35649
88512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.3564988512
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.1190484618
Short name T1421
Test name
Test status
Simulation time 159585545 ps
CPU time 0.76 seconds
Started Jun 25 05:02:35 PM PDT 24
Finished Jun 25 05:02:37 PM PDT 24
Peak memory 206568 kb
Host smart-c867e0ff-7e82-4281-9151-974d07356e03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11904
84618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.1190484618
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.965912081
Short name T436
Test name
Test status
Simulation time 40619853 ps
CPU time 0.65 seconds
Started Jun 25 05:02:33 PM PDT 24
Finished Jun 25 05:02:35 PM PDT 24
Peak memory 206572 kb
Host smart-500d5536-5c36-46ce-9f8a-c81e5e5eb50c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96591
2081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.965912081
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.2257048379
Short name T2118
Test name
Test status
Simulation time 979823262 ps
CPU time 2.31 seconds
Started Jun 25 05:02:34 PM PDT 24
Finished Jun 25 05:02:38 PM PDT 24
Peak memory 206708 kb
Host smart-034c84c8-ee00-4b3f-a2cd-7609d4b5862b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22570
48379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.2257048379
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.1575771497
Short name T582
Test name
Test status
Simulation time 190653940 ps
CPU time 1.59 seconds
Started Jun 25 05:02:41 PM PDT 24
Finished Jun 25 05:02:44 PM PDT 24
Peak memory 206740 kb
Host smart-100ab54b-fa4e-4513-9075-a155248558d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15757
71497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.1575771497
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.3528279090
Short name T1694
Test name
Test status
Simulation time 188128802 ps
CPU time 0.79 seconds
Started Jun 25 05:02:43 PM PDT 24
Finished Jun 25 05:02:46 PM PDT 24
Peak memory 206376 kb
Host smart-d4ab8c5c-a3c1-4412-894c-00bfc80bedb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35282
79090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.3528279090
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.1778365753
Short name T1712
Test name
Test status
Simulation time 144579584 ps
CPU time 0.81 seconds
Started Jun 25 05:02:43 PM PDT 24
Finished Jun 25 05:02:45 PM PDT 24
Peak memory 206588 kb
Host smart-7827a231-3a2c-4d5f-a979-951509be5d6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17783
65753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.1778365753
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.996853478
Short name T578
Test name
Test status
Simulation time 235046679 ps
CPU time 0.89 seconds
Started Jun 25 05:02:44 PM PDT 24
Finished Jun 25 05:02:46 PM PDT 24
Peak memory 206500 kb
Host smart-4f57ed7c-5bfa-47ac-917e-1e681128c53d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99685
3478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.996853478
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_invalid_sync.2478827956
Short name T929
Test name
Test status
Simulation time 14013189639 ps
CPU time 102.17 seconds
Started Jun 25 05:02:40 PM PDT 24
Finished Jun 25 05:04:23 PM PDT 24
Peak memory 206980 kb
Host smart-aa0c8a3f-1e07-465b-a8ba-419a1e90890e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2478827956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.2478827956
Directory /workspace/42.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.742792493
Short name T2223
Test name
Test status
Simulation time 243290976 ps
CPU time 0.89 seconds
Started Jun 25 05:02:42 PM PDT 24
Finished Jun 25 05:02:44 PM PDT 24
Peak memory 206580 kb
Host smart-17489a66-70d7-4a6e-8d16-3b5d6140d759
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74279
2493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.742792493
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.3364282503
Short name T704
Test name
Test status
Simulation time 23312442917 ps
CPU time 21.6 seconds
Started Jun 25 05:02:54 PM PDT 24
Finished Jun 25 05:03:20 PM PDT 24
Peak memory 206532 kb
Host smart-4b89c356-1d98-4aaf-b6dd-72ab40a5956f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33642
82503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.3364282503
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.1271231713
Short name T427
Test name
Test status
Simulation time 3298399374 ps
CPU time 3.97 seconds
Started Jun 25 05:02:53 PM PDT 24
Finished Jun 25 05:02:59 PM PDT 24
Peak memory 206556 kb
Host smart-c147dbe8-147a-4529-b08d-a1da78d0ee18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12712
31713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.1271231713
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.3706344532
Short name T2442
Test name
Test status
Simulation time 9183723900 ps
CPU time 84.63 seconds
Started Jun 25 05:02:43 PM PDT 24
Finished Jun 25 05:04:10 PM PDT 24
Peak memory 206868 kb
Host smart-a6ec2722-e5da-428c-ad30-34e83b69bb07
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3706344532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.3706344532
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.2336777637
Short name T1698
Test name
Test status
Simulation time 246257252 ps
CPU time 0.91 seconds
Started Jun 25 05:02:40 PM PDT 24
Finished Jun 25 05:02:42 PM PDT 24
Peak memory 206540 kb
Host smart-a09d930a-3678-445a-82fd-d44e22760538
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2336777637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.2336777637
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.1540143103
Short name T1403
Test name
Test status
Simulation time 230244964 ps
CPU time 0.9 seconds
Started Jun 25 05:02:42 PM PDT 24
Finished Jun 25 05:02:44 PM PDT 24
Peak memory 206584 kb
Host smart-c6bdd879-1d66-4eee-bed6-993678f87930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15401
43103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.1540143103
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.3003349812
Short name T406
Test name
Test status
Simulation time 9146706820 ps
CPU time 63.7 seconds
Started Jun 25 05:02:42 PM PDT 24
Finished Jun 25 05:03:48 PM PDT 24
Peak memory 207124 kb
Host smart-7bd813a7-5c96-4fd2-b2bd-49047415969c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30033
49812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.3003349812
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.1517087234
Short name T1165
Test name
Test status
Simulation time 11837729251 ps
CPU time 81.79 seconds
Started Jun 25 05:02:50 PM PDT 24
Finished Jun 25 05:04:13 PM PDT 24
Peak memory 206868 kb
Host smart-8af9a817-00be-45ae-b65c-0674930160cd
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1517087234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.1517087234
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.1863994423
Short name T2466
Test name
Test status
Simulation time 158849472 ps
CPU time 0.74 seconds
Started Jun 25 05:02:44 PM PDT 24
Finished Jun 25 05:02:46 PM PDT 24
Peak memory 206384 kb
Host smart-6ce0b9a5-bc1b-45d3-9731-dfdbe563e8bf
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1863994423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.1863994423
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.3247645353
Short name T1112
Test name
Test status
Simulation time 144701120 ps
CPU time 0.77 seconds
Started Jun 25 05:02:50 PM PDT 24
Finished Jun 25 05:02:52 PM PDT 24
Peak memory 206516 kb
Host smart-e948915a-2e4d-4c3a-bd80-ee6d4e648e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32476
45353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.3247645353
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.3645953502
Short name T2511
Test name
Test status
Simulation time 189582012 ps
CPU time 0.85 seconds
Started Jun 25 05:02:41 PM PDT 24
Finished Jun 25 05:02:44 PM PDT 24
Peak memory 206600 kb
Host smart-12c61002-6b6f-4607-baff-44e12ffce579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36459
53502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.3645953502
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.1231225721
Short name T2295
Test name
Test status
Simulation time 217491218 ps
CPU time 0.91 seconds
Started Jun 25 05:02:41 PM PDT 24
Finished Jun 25 05:02:43 PM PDT 24
Peak memory 206468 kb
Host smart-32bab4cc-d4fb-40c3-980f-9e677fa31960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12312
25721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.1231225721
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.471455392
Short name T400
Test name
Test status
Simulation time 194229852 ps
CPU time 0.83 seconds
Started Jun 25 05:02:41 PM PDT 24
Finished Jun 25 05:02:44 PM PDT 24
Peak memory 206600 kb
Host smart-3c7fc30e-1a5d-43d5-ab31-4cc56987cb22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47145
5392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.471455392
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.3976330637
Short name T2501
Test name
Test status
Simulation time 162715222 ps
CPU time 0.86 seconds
Started Jun 25 05:02:41 PM PDT 24
Finished Jun 25 05:02:44 PM PDT 24
Peak memory 206580 kb
Host smart-2af602d7-8876-4d3d-b741-157146fdef26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39763
30637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.3976330637
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.2711382254
Short name T756
Test name
Test status
Simulation time 153266911 ps
CPU time 0.85 seconds
Started Jun 25 05:02:41 PM PDT 24
Finished Jun 25 05:02:44 PM PDT 24
Peak memory 206572 kb
Host smart-cec93f71-ce13-4244-9512-81a9c2215506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27113
82254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.2711382254
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.1607702464
Short name T2282
Test name
Test status
Simulation time 229718413 ps
CPU time 0.93 seconds
Started Jun 25 05:02:50 PM PDT 24
Finished Jun 25 05:02:52 PM PDT 24
Peak memory 206584 kb
Host smart-3932a143-ea4a-4c02-9e19-30d5ef9e3917
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1607702464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.1607702464
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.3042496977
Short name T2498
Test name
Test status
Simulation time 144228984 ps
CPU time 0.78 seconds
Started Jun 25 05:02:40 PM PDT 24
Finished Jun 25 05:02:43 PM PDT 24
Peak memory 206504 kb
Host smart-e2514cff-926b-4484-90a1-5d3a67dbd56a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30424
96977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.3042496977
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.4079817006
Short name T2440
Test name
Test status
Simulation time 8139686672 ps
CPU time 20.81 seconds
Started Jun 25 05:02:40 PM PDT 24
Finished Jun 25 05:03:01 PM PDT 24
Peak memory 206928 kb
Host smart-23cc2f0b-3649-4e01-82a5-cf53710e9c95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40798
17006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.4079817006
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.3299710644
Short name T274
Test name
Test status
Simulation time 217027362 ps
CPU time 0.79 seconds
Started Jun 25 05:02:53 PM PDT 24
Finished Jun 25 05:02:57 PM PDT 24
Peak memory 206432 kb
Host smart-9412ff16-170c-44f0-b682-e197cc51e5ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32997
10644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.3299710644
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.2210724574
Short name T1321
Test name
Test status
Simulation time 173449209 ps
CPU time 0.81 seconds
Started Jun 25 05:02:50 PM PDT 24
Finished Jun 25 05:02:52 PM PDT 24
Peak memory 206580 kb
Host smart-9df23f7e-a2f6-4612-8670-54a63a303b48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22107
24574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.2210724574
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.588520538
Short name T333
Test name
Test status
Simulation time 243283409 ps
CPU time 0.87 seconds
Started Jun 25 05:02:53 PM PDT 24
Finished Jun 25 05:02:57 PM PDT 24
Peak memory 206448 kb
Host smart-aebd364d-3323-49f1-b6b2-a7a4d12aef3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58852
0538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.588520538
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.352987024
Short name T336
Test name
Test status
Simulation time 186071681 ps
CPU time 0.81 seconds
Started Jun 25 05:02:43 PM PDT 24
Finished Jun 25 05:02:46 PM PDT 24
Peak memory 206484 kb
Host smart-4138f272-d0cb-4b61-919b-3b6fccf6e315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35298
7024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.352987024
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.2334465453
Short name T904
Test name
Test status
Simulation time 164884526 ps
CPU time 0.79 seconds
Started Jun 25 05:02:43 PM PDT 24
Finished Jun 25 05:02:45 PM PDT 24
Peak memory 206592 kb
Host smart-a8812be6-6fc0-46e6-a43c-3550da084af5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23344
65453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.2334465453
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.510295720
Short name T836
Test name
Test status
Simulation time 219432776 ps
CPU time 0.82 seconds
Started Jun 25 05:02:40 PM PDT 24
Finished Jun 25 05:02:42 PM PDT 24
Peak memory 206516 kb
Host smart-a2fa88b5-cf50-4fe1-b1c9-f6d51224fe7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51029
5720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.510295720
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.1211563725
Short name T478
Test name
Test status
Simulation time 196526085 ps
CPU time 0.81 seconds
Started Jun 25 05:02:42 PM PDT 24
Finished Jun 25 05:02:44 PM PDT 24
Peak memory 206496 kb
Host smart-f9fe4fe1-7f08-412c-8534-647bf31642c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12115
63725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.1211563725
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.1029605950
Short name T755
Test name
Test status
Simulation time 236304169 ps
CPU time 0.93 seconds
Started Jun 25 05:02:53 PM PDT 24
Finished Jun 25 05:02:58 PM PDT 24
Peak memory 206444 kb
Host smart-205289ec-3dc8-4496-afb7-6e88f74b7e44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10296
05950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.1029605950
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.780966510
Short name T2452
Test name
Test status
Simulation time 4886810864 ps
CPU time 46.01 seconds
Started Jun 25 05:02:41 PM PDT 24
Finished Jun 25 05:03:29 PM PDT 24
Peak memory 206776 kb
Host smart-0314771e-c31c-4b26-b331-d5c9c657f860
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=780966510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.780966510
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.2520131797
Short name T1555
Test name
Test status
Simulation time 163917001 ps
CPU time 0.83 seconds
Started Jun 25 05:02:44 PM PDT 24
Finished Jun 25 05:02:46 PM PDT 24
Peak memory 206520 kb
Host smart-7d767b3e-17ea-44b5-a087-da19cf950ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25201
31797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.2520131797
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.3123218529
Short name T2327
Test name
Test status
Simulation time 211455344 ps
CPU time 0.88 seconds
Started Jun 25 05:02:41 PM PDT 24
Finished Jun 25 05:02:44 PM PDT 24
Peak memory 206504 kb
Host smart-a3ed263c-ac3c-4088-b7e9-2c4edb5063c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31232
18529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.3123218529
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.4126427215
Short name T1876
Test name
Test status
Simulation time 13155209086 ps
CPU time 108.63 seconds
Started Jun 25 05:02:55 PM PDT 24
Finished Jun 25 05:04:47 PM PDT 24
Peak memory 206792 kb
Host smart-52bc0f9e-a38a-4657-bd9e-feaa5773a536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41264
27215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.4126427215
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.675970478
Short name T2168
Test name
Test status
Simulation time 3630581341 ps
CPU time 4.39 seconds
Started Jun 25 05:02:43 PM PDT 24
Finished Jun 25 05:02:49 PM PDT 24
Peak memory 206908 kb
Host smart-a0e5eff7-1889-4c99-8437-3754c500018f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=675970478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.675970478
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.3519416848
Short name T1708
Test name
Test status
Simulation time 13365015299 ps
CPU time 12.42 seconds
Started Jun 25 05:02:40 PM PDT 24
Finished Jun 25 05:02:54 PM PDT 24
Peak memory 206652 kb
Host smart-5f9b1079-8776-48f1-b059-51c56b4aca11
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3519416848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.3519416848
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.1861060133
Short name T10
Test name
Test status
Simulation time 23374581283 ps
CPU time 24.9 seconds
Started Jun 25 05:02:54 PM PDT 24
Finished Jun 25 05:03:22 PM PDT 24
Peak memory 206580 kb
Host smart-58121780-b79c-42fa-8a04-3e62c8eb10bd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1861060133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.1861060133
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.1816938161
Short name T1838
Test name
Test status
Simulation time 206851979 ps
CPU time 0.85 seconds
Started Jun 25 05:02:43 PM PDT 24
Finished Jun 25 05:02:46 PM PDT 24
Peak memory 206572 kb
Host smart-10f4792a-9d68-4a05-ae71-bbbf77e0317a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18169
38161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.1816938161
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.221304405
Short name T703
Test name
Test status
Simulation time 160110659 ps
CPU time 0.76 seconds
Started Jun 25 05:02:54 PM PDT 24
Finished Jun 25 05:02:59 PM PDT 24
Peak memory 206416 kb
Host smart-bb920b7c-a31a-4df3-a449-4499abb60306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22130
4405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.221304405
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.951209801
Short name T1361
Test name
Test status
Simulation time 188839624 ps
CPU time 0.89 seconds
Started Jun 25 05:02:44 PM PDT 24
Finished Jun 25 05:02:46 PM PDT 24
Peak memory 206512 kb
Host smart-b96edd65-1e1c-4d62-b15c-fc2f1bf2ecd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95120
9801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.951209801
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.3635637230
Short name T473
Test name
Test status
Simulation time 422223353 ps
CPU time 1.18 seconds
Started Jun 25 05:02:50 PM PDT 24
Finished Jun 25 05:02:52 PM PDT 24
Peak memory 206580 kb
Host smart-f831bf2a-c465-4f99-a3ef-d8ccb431a941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36356
37230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.3635637230
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.509788892
Short name T1437
Test name
Test status
Simulation time 10942682135 ps
CPU time 24.5 seconds
Started Jun 25 05:02:42 PM PDT 24
Finished Jun 25 05:03:08 PM PDT 24
Peak memory 206932 kb
Host smart-2fd63f43-d5cf-4b0d-b9ce-a1a6eceae991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50978
8892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.509788892
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.3967377435
Short name T1041
Test name
Test status
Simulation time 378827884 ps
CPU time 1.16 seconds
Started Jun 25 05:02:42 PM PDT 24
Finished Jun 25 05:02:45 PM PDT 24
Peak memory 206532 kb
Host smart-9f1bb414-3656-4b0c-8ffc-5c48bec36ec2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39673
77435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.3967377435
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.2146076526
Short name T689
Test name
Test status
Simulation time 151341196 ps
CPU time 0.81 seconds
Started Jun 25 05:02:41 PM PDT 24
Finished Jun 25 05:02:44 PM PDT 24
Peak memory 206556 kb
Host smart-f95783b8-3f72-4892-bb84-dc3f099da9d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21460
76526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.2146076526
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.570455657
Short name T2152
Test name
Test status
Simulation time 41482418 ps
CPU time 0.64 seconds
Started Jun 25 05:02:54 PM PDT 24
Finished Jun 25 05:02:58 PM PDT 24
Peak memory 206436 kb
Host smart-7eceeac9-dcc0-4172-86f5-5ad2105397c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57045
5657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.570455657
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.1802489523
Short name T2508
Test name
Test status
Simulation time 865490158 ps
CPU time 1.98 seconds
Started Jun 25 05:02:41 PM PDT 24
Finished Jun 25 05:02:45 PM PDT 24
Peak memory 206744 kb
Host smart-ad4f36b4-9768-4671-b091-52e1bed7a12d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18024
89523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.1802489523
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.3116990389
Short name T2148
Test name
Test status
Simulation time 180526889 ps
CPU time 1.73 seconds
Started Jun 25 05:02:44 PM PDT 24
Finished Jun 25 05:02:47 PM PDT 24
Peak memory 206544 kb
Host smart-2dd7bd80-1b43-4c51-afa5-532fbe0a8193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31169
90389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.3116990389
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.2930135060
Short name T639
Test name
Test status
Simulation time 178045589 ps
CPU time 0.91 seconds
Started Jun 25 05:02:54 PM PDT 24
Finished Jun 25 05:02:58 PM PDT 24
Peak memory 206496 kb
Host smart-13b5b04f-a15f-480b-ab48-b62be9c1c538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29301
35060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.2930135060
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.3499008200
Short name T579
Test name
Test status
Simulation time 159163529 ps
CPU time 0.82 seconds
Started Jun 25 05:02:52 PM PDT 24
Finished Jun 25 05:02:55 PM PDT 24
Peak memory 206504 kb
Host smart-d1194d7c-ff05-4f6e-8f91-a71949c7dfe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34990
08200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.3499008200
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.3155402257
Short name T2306
Test name
Test status
Simulation time 183668802 ps
CPU time 0.87 seconds
Started Jun 25 05:02:52 PM PDT 24
Finished Jun 25 05:02:54 PM PDT 24
Peak memory 206580 kb
Host smart-9508e98f-0d3c-45ad-98ef-23cea98f2c34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31554
02257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.3155402257
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.3200127635
Short name T892
Test name
Test status
Simulation time 213787003 ps
CPU time 0.91 seconds
Started Jun 25 05:02:55 PM PDT 24
Finished Jun 25 05:03:00 PM PDT 24
Peak memory 206572 kb
Host smart-d8ea7864-f0e1-4b5c-89c9-0b982cea8c64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32001
27635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.3200127635
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.3948949391
Short name T1951
Test name
Test status
Simulation time 23276552076 ps
CPU time 20.74 seconds
Started Jun 25 05:02:51 PM PDT 24
Finished Jun 25 05:03:13 PM PDT 24
Peak memory 206720 kb
Host smart-ae17cd10-88a6-4bef-b5ac-ebc8b75c3110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39489
49391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.3948949391
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.1398590458
Short name T2488
Test name
Test status
Simulation time 3286897473 ps
CPU time 4.4 seconds
Started Jun 25 05:02:54 PM PDT 24
Finished Jun 25 05:03:02 PM PDT 24
Peak memory 206624 kb
Host smart-2d61dc46-670a-4a98-9686-160586d86fbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13985
90458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.1398590458
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.738135901
Short name T1545
Test name
Test status
Simulation time 7174715197 ps
CPU time 192.9 seconds
Started Jun 25 05:02:53 PM PDT 24
Finished Jun 25 05:06:08 PM PDT 24
Peak memory 206956 kb
Host smart-a25e0b71-159c-4c01-9ebf-bedfea589b39
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=738135901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.738135901
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.2639164100
Short name T1018
Test name
Test status
Simulation time 241060924 ps
CPU time 0.95 seconds
Started Jun 25 05:02:55 PM PDT 24
Finished Jun 25 05:03:00 PM PDT 24
Peak memory 206524 kb
Host smart-be38e9c5-2bd8-424c-888f-be713fab6e57
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2639164100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.2639164100
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.2262660483
Short name T1884
Test name
Test status
Simulation time 194834724 ps
CPU time 0.9 seconds
Started Jun 25 05:02:54 PM PDT 24
Finished Jun 25 05:02:59 PM PDT 24
Peak memory 206512 kb
Host smart-0531545a-0209-47f9-8fee-29572815c9a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22626
60483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.2262660483
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.152156514
Short name T6
Test name
Test status
Simulation time 3741126223 ps
CPU time 101.12 seconds
Started Jun 25 05:02:53 PM PDT 24
Finished Jun 25 05:04:37 PM PDT 24
Peak memory 206848 kb
Host smart-d7696b21-05e0-4ca2-85bc-4308cb7d7c52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15215
6514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.152156514
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.744229347
Short name T1918
Test name
Test status
Simulation time 8665531309 ps
CPU time 80.73 seconds
Started Jun 25 05:02:54 PM PDT 24
Finished Jun 25 05:04:18 PM PDT 24
Peak memory 206896 kb
Host smart-45466b8c-e2fb-4f2e-8698-9ebb0442247d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=744229347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.744229347
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.2176828494
Short name T1054
Test name
Test status
Simulation time 162767378 ps
CPU time 0.83 seconds
Started Jun 25 05:02:55 PM PDT 24
Finished Jun 25 05:03:00 PM PDT 24
Peak memory 206520 kb
Host smart-9f1d8ebc-bee3-478a-b900-d11a26183d44
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2176828494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.2176828494
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.1045783142
Short name T678
Test name
Test status
Simulation time 163551452 ps
CPU time 0.8 seconds
Started Jun 25 05:02:55 PM PDT 24
Finished Jun 25 05:03:00 PM PDT 24
Peak memory 206440 kb
Host smart-3414905e-c4d8-4672-861c-205ca20d9962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10457
83142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.1045783142
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.2698020509
Short name T1484
Test name
Test status
Simulation time 190280299 ps
CPU time 0.8 seconds
Started Jun 25 05:02:50 PM PDT 24
Finished Jun 25 05:02:52 PM PDT 24
Peak memory 206568 kb
Host smart-3514a7c0-ef21-4c91-ae63-e8de7f035257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26980
20509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.2698020509
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.1531441721
Short name T2274
Test name
Test status
Simulation time 208186549 ps
CPU time 0.81 seconds
Started Jun 25 05:02:53 PM PDT 24
Finished Jun 25 05:02:56 PM PDT 24
Peak memory 206576 kb
Host smart-c4e5ac59-04a3-4656-b7d9-fb57360a3b92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15314
41721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.1531441721
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.2029070269
Short name T1535
Test name
Test status
Simulation time 171531334 ps
CPU time 0.79 seconds
Started Jun 25 05:02:55 PM PDT 24
Finished Jun 25 05:02:59 PM PDT 24
Peak memory 206572 kb
Host smart-4af43423-4efa-4849-8b3f-c5a8340ca33d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20290
70269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.2029070269
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.1212192144
Short name T1653
Test name
Test status
Simulation time 154558041 ps
CPU time 0.8 seconds
Started Jun 25 05:02:52 PM PDT 24
Finished Jun 25 05:02:54 PM PDT 24
Peak memory 206500 kb
Host smart-bc0532c4-ed31-40a4-ace5-b0b31038df21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12121
92144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.1212192144
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.1161208398
Short name T1277
Test name
Test status
Simulation time 147303010 ps
CPU time 0.78 seconds
Started Jun 25 05:02:53 PM PDT 24
Finished Jun 25 05:02:55 PM PDT 24
Peak memory 206580 kb
Host smart-f8c0c63a-61f9-44eb-b8d0-12028e183a23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11612
08398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.1161208398
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.2220469265
Short name T642
Test name
Test status
Simulation time 252025200 ps
CPU time 1.03 seconds
Started Jun 25 05:02:55 PM PDT 24
Finished Jun 25 05:02:59 PM PDT 24
Peak memory 206544 kb
Host smart-ab38aa73-ef75-4de4-9f19-040999955fc9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2220469265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.2220469265
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.2059850898
Short name T622
Test name
Test status
Simulation time 142835351 ps
CPU time 0.78 seconds
Started Jun 25 05:02:51 PM PDT 24
Finished Jun 25 05:02:53 PM PDT 24
Peak memory 206500 kb
Host smart-ce0ec11b-5d9a-4fcc-ae0c-5dee8f3691cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20598
50898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.2059850898
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.474519056
Short name T25
Test name
Test status
Simulation time 36414318 ps
CPU time 0.67 seconds
Started Jun 25 05:02:54 PM PDT 24
Finished Jun 25 05:02:58 PM PDT 24
Peak memory 206588 kb
Host smart-519031c0-db06-4a7e-b3b7-f8c90523a645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47451
9056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.474519056
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.2372549677
Short name T1173
Test name
Test status
Simulation time 7979610608 ps
CPU time 18.43 seconds
Started Jun 25 05:02:55 PM PDT 24
Finished Jun 25 05:03:17 PM PDT 24
Peak memory 206892 kb
Host smart-56b4c755-9321-40dc-8bf5-a5125098e76e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23725
49677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.2372549677
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.2190735918
Short name T733
Test name
Test status
Simulation time 201333553 ps
CPU time 0.83 seconds
Started Jun 25 05:02:55 PM PDT 24
Finished Jun 25 05:03:00 PM PDT 24
Peak memory 206572 kb
Host smart-e688300b-2774-4d72-ba95-c9bcb3d90002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21907
35918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.2190735918
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.338355358
Short name T1237
Test name
Test status
Simulation time 240149415 ps
CPU time 0.92 seconds
Started Jun 25 05:02:51 PM PDT 24
Finished Jun 25 05:02:53 PM PDT 24
Peak memory 206564 kb
Host smart-150c7d01-4939-49f4-8cd4-581e8b009dd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33835
5358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.338355358
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.3384657679
Short name T651
Test name
Test status
Simulation time 212335073 ps
CPU time 0.86 seconds
Started Jun 25 05:02:50 PM PDT 24
Finished Jun 25 05:02:53 PM PDT 24
Peak memory 206520 kb
Host smart-54ba69bc-95fa-4970-bb23-1d4a75ff5fd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33846
57679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.3384657679
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.2160969835
Short name T19
Test name
Test status
Simulation time 174384034 ps
CPU time 0.83 seconds
Started Jun 25 05:02:53 PM PDT 24
Finished Jun 25 05:02:56 PM PDT 24
Peak memory 206492 kb
Host smart-84fe5364-f050-4ba5-b2ea-0154ea1e8a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21609
69835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.2160969835
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.1517559380
Short name T866
Test name
Test status
Simulation time 186673802 ps
CPU time 0.82 seconds
Started Jun 25 05:02:51 PM PDT 24
Finished Jun 25 05:02:53 PM PDT 24
Peak memory 206572 kb
Host smart-997cd5ac-716d-4df6-85c1-8a8f0d49e9ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15175
59380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.1517559380
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.3446886549
Short name T1793
Test name
Test status
Simulation time 158862669 ps
CPU time 0.82 seconds
Started Jun 25 05:02:53 PM PDT 24
Finished Jun 25 05:02:57 PM PDT 24
Peak memory 206568 kb
Host smart-b46ce2e8-7313-4ef0-b3c7-1681d5a14d20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34468
86549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.3446886549
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.3440856395
Short name T1926
Test name
Test status
Simulation time 151335266 ps
CPU time 0.77 seconds
Started Jun 25 05:02:54 PM PDT 24
Finished Jun 25 05:02:58 PM PDT 24
Peak memory 206600 kb
Host smart-e742922a-8c00-424a-8e23-0a63d8948d0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34408
56395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.3440856395
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.2761745851
Short name T1344
Test name
Test status
Simulation time 254698963 ps
CPU time 1.11 seconds
Started Jun 25 05:02:55 PM PDT 24
Finished Jun 25 05:03:00 PM PDT 24
Peak memory 206612 kb
Host smart-670f8851-a916-40bc-8b5b-391fec20a860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27617
45851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.2761745851
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.434301002
Short name T1506
Test name
Test status
Simulation time 7357375595 ps
CPU time 53.2 seconds
Started Jun 25 05:02:55 PM PDT 24
Finished Jun 25 05:03:52 PM PDT 24
Peak memory 206864 kb
Host smart-c853fb97-08b9-4605-b7d8-25840c039a29
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=434301002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.434301002
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.2252350301
Short name T480
Test name
Test status
Simulation time 178258537 ps
CPU time 0.85 seconds
Started Jun 25 05:02:54 PM PDT 24
Finished Jun 25 05:02:58 PM PDT 24
Peak memory 206520 kb
Host smart-a5a73ddc-5f4b-48d3-9371-5371253f39a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22523
50301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.2252350301
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.1316042821
Short name T2231
Test name
Test status
Simulation time 158219414 ps
CPU time 0.8 seconds
Started Jun 25 05:02:51 PM PDT 24
Finished Jun 25 05:02:53 PM PDT 24
Peak memory 206512 kb
Host smart-34a83549-fdf5-4fde-acee-5a4783eff13a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13160
42821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.1316042821
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.3220344955
Short name T532
Test name
Test status
Simulation time 5277712715 ps
CPU time 47.83 seconds
Started Jun 25 05:02:54 PM PDT 24
Finished Jun 25 05:03:46 PM PDT 24
Peak memory 206776 kb
Host smart-b530d443-80b9-4404-9431-aa1eed320665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32203
44955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.3220344955
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.2432402139
Short name T635
Test name
Test status
Simulation time 4288774355 ps
CPU time 4.86 seconds
Started Jun 25 05:02:54 PM PDT 24
Finished Jun 25 05:03:03 PM PDT 24
Peak memory 206796 kb
Host smart-574755a9-60cd-4f1b-8ba7-d81a943e3d8a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2432402139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.2432402139
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.387769807
Short name T784
Test name
Test status
Simulation time 13454943426 ps
CPU time 13.84 seconds
Started Jun 25 05:02:53 PM PDT 24
Finished Jun 25 05:03:09 PM PDT 24
Peak memory 206924 kb
Host smart-a0fd8abb-3b78-49a1-b2cb-ff7af1555b6f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=387769807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.387769807
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.3974439716
Short name T1374
Test name
Test status
Simulation time 23414270900 ps
CPU time 20.86 seconds
Started Jun 25 05:02:51 PM PDT 24
Finished Jun 25 05:03:14 PM PDT 24
Peak memory 207144 kb
Host smart-bdc1b2e8-d38e-40b7-ba23-f28fecc87d0a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3974439716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.3974439716
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.2458298736
Short name T1357
Test name
Test status
Simulation time 169841799 ps
CPU time 0.8 seconds
Started Jun 25 05:02:55 PM PDT 24
Finished Jun 25 05:03:00 PM PDT 24
Peak memory 206484 kb
Host smart-fdb702c8-b08b-48f4-ae7a-4058b7c740ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24582
98736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.2458298736
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.1284473885
Short name T948
Test name
Test status
Simulation time 210978385 ps
CPU time 0.85 seconds
Started Jun 25 05:02:56 PM PDT 24
Finished Jun 25 05:03:01 PM PDT 24
Peak memory 206504 kb
Host smart-363c6ff6-08dc-48fe-a3bc-6e8dbe4274ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12844
73885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.1284473885
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.1181698506
Short name T1220
Test name
Test status
Simulation time 323325011 ps
CPU time 1.13 seconds
Started Jun 25 05:02:52 PM PDT 24
Finished Jun 25 05:02:54 PM PDT 24
Peak memory 206512 kb
Host smart-751183cc-c0cc-44d3-a2c2-f9030539f407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11816
98506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.1181698506
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.231477437
Short name T1327
Test name
Test status
Simulation time 1208386096 ps
CPU time 2.91 seconds
Started Jun 25 05:02:53 PM PDT 24
Finished Jun 25 05:02:58 PM PDT 24
Peak memory 206724 kb
Host smart-54a914a6-dfcf-4b5f-a419-278281c96c96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23147
7437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.231477437
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.2524474125
Short name T2319
Test name
Test status
Simulation time 12155589708 ps
CPU time 25.35 seconds
Started Jun 25 05:02:56 PM PDT 24
Finished Jun 25 05:03:25 PM PDT 24
Peak memory 206844 kb
Host smart-2771201a-e7cf-4db1-96cf-21d73d0bbed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25244
74125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.2524474125
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.68671784
Short name T1284
Test name
Test status
Simulation time 337949879 ps
CPU time 1.16 seconds
Started Jun 25 05:02:54 PM PDT 24
Finished Jun 25 05:02:59 PM PDT 24
Peak memory 206560 kb
Host smart-8f3bdf6d-ea99-4a74-9455-0ebc554655d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68671
784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.68671784
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.39241936
Short name T2050
Test name
Test status
Simulation time 148464962 ps
CPU time 0.75 seconds
Started Jun 25 05:02:55 PM PDT 24
Finished Jun 25 05:02:59 PM PDT 24
Peak memory 206572 kb
Host smart-d1cf5d54-668f-475f-84b2-c3d1263241b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39241
936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.39241936
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.185081565
Short name T2506
Test name
Test status
Simulation time 55637599 ps
CPU time 0.7 seconds
Started Jun 25 05:02:55 PM PDT 24
Finished Jun 25 05:03:00 PM PDT 24
Peak memory 206468 kb
Host smart-4f43a101-a0a1-44d0-96b5-c8401dd310e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18508
1565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.185081565
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.1105810886
Short name T2021
Test name
Test status
Simulation time 809254871 ps
CPU time 1.98 seconds
Started Jun 25 05:02:54 PM PDT 24
Finished Jun 25 05:02:59 PM PDT 24
Peak memory 206744 kb
Host smart-d315c1b9-1741-4beb-9b53-815ac521a494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11058
10886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.1105810886
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.3441148949
Short name T2328
Test name
Test status
Simulation time 166193889 ps
CPU time 1.46 seconds
Started Jun 25 05:02:55 PM PDT 24
Finished Jun 25 05:03:00 PM PDT 24
Peak memory 206752 kb
Host smart-ae922640-26ae-4690-a57f-3953cee040f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34411
48949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.3441148949
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.3748407150
Short name T1796
Test name
Test status
Simulation time 176388936 ps
CPU time 0.83 seconds
Started Jun 25 05:03:06 PM PDT 24
Finished Jun 25 05:03:08 PM PDT 24
Peak memory 206576 kb
Host smart-517d0d0b-3459-4bf9-8b8c-f044cae968bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37484
07150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.3748407150
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.3429083864
Short name T2368
Test name
Test status
Simulation time 172979020 ps
CPU time 0.83 seconds
Started Jun 25 05:03:03 PM PDT 24
Finished Jun 25 05:03:07 PM PDT 24
Peak memory 206588 kb
Host smart-a686e1a2-5184-454c-a2f7-63fa1b052004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34290
83864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.3429083864
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.85280016
Short name T2037
Test name
Test status
Simulation time 253402201 ps
CPU time 0.97 seconds
Started Jun 25 05:02:54 PM PDT 24
Finished Jun 25 05:02:58 PM PDT 24
Peak memory 206576 kb
Host smart-28fac936-b6a2-4a54-b282-9bc3bfbb5494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85280
016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.85280016
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_invalid_sync.1652276022
Short name T216
Test name
Test status
Simulation time 18588657472 ps
CPU time 543.04 seconds
Started Jun 25 05:02:54 PM PDT 24
Finished Jun 25 05:12:01 PM PDT 24
Peak memory 206956 kb
Host smart-caa19e26-d3b4-4814-b471-7375e393a2ed
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1652276022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.1652276022
Directory /workspace/44.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.1253454713
Short name T2248
Test name
Test status
Simulation time 217556989 ps
CPU time 0.86 seconds
Started Jun 25 05:02:54 PM PDT 24
Finished Jun 25 05:02:58 PM PDT 24
Peak memory 206516 kb
Host smart-2b4540ae-cda2-4757-8f94-5e0ed51651f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12534
54713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.1253454713
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.3779500772
Short name T1024
Test name
Test status
Simulation time 23276003109 ps
CPU time 22.34 seconds
Started Jun 25 05:03:06 PM PDT 24
Finished Jun 25 05:03:30 PM PDT 24
Peak memory 206692 kb
Host smart-bfa94326-547f-40dc-9b04-4c452eb87719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37795
00772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.3779500772
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.3954650012
Short name T337
Test name
Test status
Simulation time 3293952960 ps
CPU time 4.12 seconds
Started Jun 25 05:03:03 PM PDT 24
Finished Jun 25 05:03:10 PM PDT 24
Peak memory 206568 kb
Host smart-34923b03-5697-4e58-9df1-e3090519beed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39546
50012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.3954650012
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.1017900514
Short name T2245
Test name
Test status
Simulation time 10321634612 ps
CPU time 102.1 seconds
Started Jun 25 05:03:04 PM PDT 24
Finished Jun 25 05:04:48 PM PDT 24
Peak memory 206908 kb
Host smart-bbb2617c-2ebc-4f3c-89af-7d4bfd915f57
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1017900514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.1017900514
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.2188338724
Short name T1841
Test name
Test status
Simulation time 308076109 ps
CPU time 1.03 seconds
Started Jun 25 05:03:05 PM PDT 24
Finished Jun 25 05:03:08 PM PDT 24
Peak memory 206576 kb
Host smart-3d6b1e48-6d32-4dc4-9493-17260d0c8469
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2188338724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.2188338724
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.2655529898
Short name T868
Test name
Test status
Simulation time 192915141 ps
CPU time 0.9 seconds
Started Jun 25 05:03:04 PM PDT 24
Finished Jun 25 05:03:07 PM PDT 24
Peak memory 206604 kb
Host smart-82ebf821-dd0f-4dd2-bf76-879d02be0361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26555
29898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.2655529898
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.3547310100
Short name T2015
Test name
Test status
Simulation time 4473437266 ps
CPU time 33.54 seconds
Started Jun 25 05:03:03 PM PDT 24
Finished Jun 25 05:03:39 PM PDT 24
Peak memory 206860 kb
Host smart-62a7b712-0271-41eb-9746-12b1d9417122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35473
10100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.3547310100
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.4038002073
Short name T2041
Test name
Test status
Simulation time 10195063325 ps
CPU time 74.25 seconds
Started Jun 25 05:03:03 PM PDT 24
Finished Jun 25 05:04:19 PM PDT 24
Peak memory 206916 kb
Host smart-edacdf4b-94d9-4808-885d-4bff76004c77
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4038002073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.4038002073
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.1729233233
Short name T1139
Test name
Test status
Simulation time 212252901 ps
CPU time 0.88 seconds
Started Jun 25 05:03:03 PM PDT 24
Finished Jun 25 05:03:06 PM PDT 24
Peak memory 206560 kb
Host smart-89c42bc9-5c7a-493b-8000-843a4391d802
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1729233233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.1729233233
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.635037982
Short name T570
Test name
Test status
Simulation time 150041844 ps
CPU time 0.86 seconds
Started Jun 25 05:03:03 PM PDT 24
Finished Jun 25 05:03:06 PM PDT 24
Peak memory 206508 kb
Host smart-82c3caaa-911f-43c8-a7c9-b6f5c7f47b67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63503
7982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.635037982
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.1633661051
Short name T126
Test name
Test status
Simulation time 204104207 ps
CPU time 0.88 seconds
Started Jun 25 05:03:02 PM PDT 24
Finished Jun 25 05:03:05 PM PDT 24
Peak memory 206500 kb
Host smart-470b6cb4-b9ff-4ed5-ba50-a1e8bb51ab77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16336
61051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.1633661051
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.1806814134
Short name T1607
Test name
Test status
Simulation time 171227531 ps
CPU time 0.87 seconds
Started Jun 25 05:03:05 PM PDT 24
Finished Jun 25 05:03:08 PM PDT 24
Peak memory 206576 kb
Host smart-13c11206-13ac-46fd-86e1-37697d1f96c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18068
14134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.1806814134
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.187216970
Short name T1646
Test name
Test status
Simulation time 180550586 ps
CPU time 0.83 seconds
Started Jun 25 05:03:04 PM PDT 24
Finished Jun 25 05:03:07 PM PDT 24
Peak memory 206600 kb
Host smart-86d13270-26fe-4750-a6ae-164c719abe22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18721
6970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.187216970
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.158849616
Short name T2318
Test name
Test status
Simulation time 206324430 ps
CPU time 0.92 seconds
Started Jun 25 05:03:03 PM PDT 24
Finished Jun 25 05:03:06 PM PDT 24
Peak memory 206472 kb
Host smart-967febf7-8a87-47d6-be66-904de9213f93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15884
9616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.158849616
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.3552875088
Short name T879
Test name
Test status
Simulation time 159099818 ps
CPU time 0.82 seconds
Started Jun 25 05:03:03 PM PDT 24
Finished Jun 25 05:03:06 PM PDT 24
Peak memory 206580 kb
Host smart-706ba2ff-4b23-4c40-8fc3-c026c96303c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35528
75088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.3552875088
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.3630043952
Short name T1962
Test name
Test status
Simulation time 266456737 ps
CPU time 0.97 seconds
Started Jun 25 05:03:03 PM PDT 24
Finished Jun 25 05:03:06 PM PDT 24
Peak memory 206580 kb
Host smart-9c371613-c9c6-4207-9772-38d73e9e25cb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3630043952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.3630043952
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.1348415046
Short name T437
Test name
Test status
Simulation time 147183619 ps
CPU time 0.83 seconds
Started Jun 25 05:03:02 PM PDT 24
Finished Jun 25 05:03:05 PM PDT 24
Peak memory 206496 kb
Host smart-a2fde4fc-8990-437d-934b-f319fe5aa3b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13484
15046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.1348415046
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.3647082156
Short name T2263
Test name
Test status
Simulation time 37510915 ps
CPU time 0.66 seconds
Started Jun 25 05:03:07 PM PDT 24
Finished Jun 25 05:03:09 PM PDT 24
Peak memory 206568 kb
Host smart-6251a52f-edb3-454c-adfb-525a8e3318e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36470
82156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.3647082156
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.365913668
Short name T1046
Test name
Test status
Simulation time 16938404741 ps
CPU time 34.15 seconds
Started Jun 25 05:03:05 PM PDT 24
Finished Jun 25 05:03:41 PM PDT 24
Peak memory 206900 kb
Host smart-3b30e0b5-a6ad-4bf5-aacd-dfd9c968b7bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36591
3668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.365913668
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.2181276805
Short name T1162
Test name
Test status
Simulation time 218789186 ps
CPU time 0.86 seconds
Started Jun 25 05:03:05 PM PDT 24
Finished Jun 25 05:03:08 PM PDT 24
Peak memory 206596 kb
Host smart-359a5fea-0288-4a96-9050-d8fcb9336f15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21812
76805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.2181276805
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.573244229
Short name T481
Test name
Test status
Simulation time 196138415 ps
CPU time 0.83 seconds
Started Jun 25 05:03:01 PM PDT 24
Finished Jun 25 05:03:03 PM PDT 24
Peak memory 206564 kb
Host smart-c0778fba-9912-411d-bdff-55789757c74d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57324
4229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.573244229
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.81712012
Short name T588
Test name
Test status
Simulation time 214064950 ps
CPU time 0.99 seconds
Started Jun 25 05:03:02 PM PDT 24
Finished Jun 25 05:03:04 PM PDT 24
Peak memory 206528 kb
Host smart-e4c116a4-d23e-4178-ba57-a7cdc8129a3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81712
012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.81712012
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.4108910924
Short name T2419
Test name
Test status
Simulation time 184860044 ps
CPU time 0.85 seconds
Started Jun 25 05:03:05 PM PDT 24
Finished Jun 25 05:03:08 PM PDT 24
Peak memory 206496 kb
Host smart-9e635f2d-4e18-4e71-81ea-f9d835ba76d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41089
10924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.4108910924
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.1999885118
Short name T2107
Test name
Test status
Simulation time 171094242 ps
CPU time 0.79 seconds
Started Jun 25 05:03:06 PM PDT 24
Finished Jun 25 05:03:09 PM PDT 24
Peak memory 206572 kb
Host smart-186c6ad2-9bbe-4d6e-b9db-b8e33352ebb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19998
85118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.1999885118
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.3554767744
Short name T2371
Test name
Test status
Simulation time 167875605 ps
CPU time 0.8 seconds
Started Jun 25 05:03:06 PM PDT 24
Finished Jun 25 05:03:09 PM PDT 24
Peak memory 206568 kb
Host smart-2d715b09-4a4e-4161-933c-63b139653193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35547
67744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.3554767744
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.3333364897
Short name T2425
Test name
Test status
Simulation time 166921808 ps
CPU time 0.84 seconds
Started Jun 25 05:03:02 PM PDT 24
Finished Jun 25 05:03:05 PM PDT 24
Peak memory 206572 kb
Host smart-04fdcc6d-bcc7-4641-b164-926d1f4e680d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33333
64897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.3333364897
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.2586806714
Short name T1825
Test name
Test status
Simulation time 236335437 ps
CPU time 0.94 seconds
Started Jun 25 05:03:05 PM PDT 24
Finished Jun 25 05:03:08 PM PDT 24
Peak memory 206588 kb
Host smart-9ef83aab-07c8-4932-99fe-c547127fb7ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25868
06714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.2586806714
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.2685151626
Short name T2339
Test name
Test status
Simulation time 9832509144 ps
CPU time 279.99 seconds
Started Jun 25 05:03:06 PM PDT 24
Finished Jun 25 05:07:48 PM PDT 24
Peak memory 206964 kb
Host smart-2308c94b-ad1b-4f8b-96d4-669f9f16767c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2685151626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.2685151626
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.339146384
Short name T1810
Test name
Test status
Simulation time 162559666 ps
CPU time 0.77 seconds
Started Jun 25 05:03:06 PM PDT 24
Finished Jun 25 05:03:09 PM PDT 24
Peak memory 206592 kb
Host smart-8b5ef908-5e35-4f0d-b225-d7462bae488e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33914
6384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.339146384
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.678509576
Short name T301
Test name
Test status
Simulation time 191717721 ps
CPU time 0.88 seconds
Started Jun 25 05:03:03 PM PDT 24
Finished Jun 25 05:03:06 PM PDT 24
Peak memory 206500 kb
Host smart-ea875864-8e26-4cde-876f-de4f90a4214c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67850
9576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.678509576
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.3388842076
Short name T308
Test name
Test status
Simulation time 4735313363 ps
CPU time 127.19 seconds
Started Jun 25 05:03:02 PM PDT 24
Finished Jun 25 05:05:10 PM PDT 24
Peak memory 206920 kb
Host smart-2672663b-7d9c-49ae-bb1c-4c50b238bb6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33888
42076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.3388842076
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.1284878614
Short name T214
Test name
Test status
Simulation time 3648161556 ps
CPU time 4.86 seconds
Started Jun 25 05:03:05 PM PDT 24
Finished Jun 25 05:03:12 PM PDT 24
Peak memory 206912 kb
Host smart-6451485d-6daa-4893-92b2-f1293874a3c8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1284878614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.1284878614
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.3013206359
Short name T1216
Test name
Test status
Simulation time 13472423903 ps
CPU time 13.06 seconds
Started Jun 25 05:03:06 PM PDT 24
Finished Jun 25 05:03:21 PM PDT 24
Peak memory 206880 kb
Host smart-e2a51ca7-5da6-4fc5-8cde-3677a5c626dd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3013206359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.3013206359
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.3508619055
Short name T942
Test name
Test status
Simulation time 23455884499 ps
CPU time 24.31 seconds
Started Jun 25 05:03:07 PM PDT 24
Finished Jun 25 05:03:33 PM PDT 24
Peak memory 206888 kb
Host smart-c77b416c-6a94-4e04-b5c3-72ab69ad3ec1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3508619055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.3508619055
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.871483899
Short name T1353
Test name
Test status
Simulation time 218050447 ps
CPU time 0.92 seconds
Started Jun 25 05:03:03 PM PDT 24
Finished Jun 25 05:03:06 PM PDT 24
Peak memory 206572 kb
Host smart-f2e991d1-b683-494e-875c-f1f95242119b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87148
3899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.871483899
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.3856078370
Short name T1774
Test name
Test status
Simulation time 143483638 ps
CPU time 0.78 seconds
Started Jun 25 05:03:01 PM PDT 24
Finished Jun 25 05:03:03 PM PDT 24
Peak memory 206500 kb
Host smart-77ec560c-f17c-4fec-a5d9-e54fd243619d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38560
78370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.3856078370
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.2920959237
Short name T479
Test name
Test status
Simulation time 563256628 ps
CPU time 1.79 seconds
Started Jun 25 05:03:03 PM PDT 24
Finished Jun 25 05:03:07 PM PDT 24
Peak memory 206796 kb
Host smart-15960a2c-8612-4b87-8903-70d90767005b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29209
59237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.2920959237
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.406636908
Short name T1850
Test name
Test status
Simulation time 608967342 ps
CPU time 1.48 seconds
Started Jun 25 05:03:02 PM PDT 24
Finished Jun 25 05:03:05 PM PDT 24
Peak memory 206580 kb
Host smart-286b0b8d-4fc7-413e-93bc-3875bd1202b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40663
6908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.406636908
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.4009918925
Short name T1744
Test name
Test status
Simulation time 20989273217 ps
CPU time 41.49 seconds
Started Jun 25 05:03:03 PM PDT 24
Finished Jun 25 05:03:47 PM PDT 24
Peak memory 206852 kb
Host smart-fe638dfd-6679-4b05-99c7-3a94a18df722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40099
18925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.4009918925
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.178576405
Short name T85
Test name
Test status
Simulation time 421401362 ps
CPU time 1.15 seconds
Started Jun 25 05:03:03 PM PDT 24
Finished Jun 25 05:03:07 PM PDT 24
Peak memory 206568 kb
Host smart-24324188-99fc-4ac7-8f6e-5313a4b46977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17857
6405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.178576405
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.2426069029
Short name T340
Test name
Test status
Simulation time 136813559 ps
CPU time 0.75 seconds
Started Jun 25 05:03:03 PM PDT 24
Finished Jun 25 05:03:07 PM PDT 24
Peak memory 206516 kb
Host smart-4628e2e8-dd35-4ba7-ada1-d26fa2363db4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24260
69029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.2426069029
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.2379066986
Short name T537
Test name
Test status
Simulation time 74641290 ps
CPU time 0.72 seconds
Started Jun 25 05:03:03 PM PDT 24
Finished Jun 25 05:03:06 PM PDT 24
Peak memory 206460 kb
Host smart-93f0279d-8133-4fce-baa7-e782bb670a64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23790
66986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.2379066986
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.2825720038
Short name T425
Test name
Test status
Simulation time 724018441 ps
CPU time 2.01 seconds
Started Jun 25 05:03:04 PM PDT 24
Finished Jun 25 05:03:09 PM PDT 24
Peak memory 206760 kb
Host smart-101d75b3-3fd0-42ef-aa0e-9408e7aa9eb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28257
20038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.2825720038
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.528720537
Short name T1508
Test name
Test status
Simulation time 302690389 ps
CPU time 1.86 seconds
Started Jun 25 05:03:06 PM PDT 24
Finished Jun 25 05:03:10 PM PDT 24
Peak memory 206824 kb
Host smart-e34c739d-de81-46a8-9487-e43eeae3dd9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52872
0537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.528720537
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.3654210849
Short name T620
Test name
Test status
Simulation time 200100098 ps
CPU time 0.9 seconds
Started Jun 25 05:03:17 PM PDT 24
Finished Jun 25 05:03:20 PM PDT 24
Peak memory 206568 kb
Host smart-0f521396-50e1-4074-b3a2-c047c7b501bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36542
10849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.3654210849
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.3600316243
Short name T624
Test name
Test status
Simulation time 167528308 ps
CPU time 0.79 seconds
Started Jun 25 05:03:13 PM PDT 24
Finished Jun 25 05:03:15 PM PDT 24
Peak memory 206492 kb
Host smart-6ff08f94-96e8-4989-a003-d90bfd7c65d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36003
16243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.3600316243
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.3656295452
Short name T2378
Test name
Test status
Simulation time 161210431 ps
CPU time 0.86 seconds
Started Jun 25 05:03:05 PM PDT 24
Finished Jun 25 05:03:08 PM PDT 24
Peak memory 206580 kb
Host smart-56180ee0-e652-4348-afbc-ea4d4eb3e302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36562
95452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.3656295452
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.2251929220
Short name T764
Test name
Test status
Simulation time 178305095 ps
CPU time 0.86 seconds
Started Jun 25 05:03:04 PM PDT 24
Finished Jun 25 05:03:08 PM PDT 24
Peak memory 206600 kb
Host smart-c7454108-d074-43b7-b495-84c02109af22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22519
29220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.2251929220
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.2347715482
Short name T1329
Test name
Test status
Simulation time 23326549700 ps
CPU time 22.46 seconds
Started Jun 25 05:03:14 PM PDT 24
Finished Jun 25 05:03:37 PM PDT 24
Peak memory 206576 kb
Host smart-af0c3e65-fe57-4853-9444-e106b6fb68e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23477
15482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.2347715482
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.4238388112
Short name T294
Test name
Test status
Simulation time 3359643236 ps
CPU time 3.82 seconds
Started Jun 25 05:03:14 PM PDT 24
Finished Jun 25 05:03:19 PM PDT 24
Peak memory 206616 kb
Host smart-3ec063b2-b258-4b2e-b698-71d8e376fc2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42383
88112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.4238388112
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.647561338
Short name T1158
Test name
Test status
Simulation time 10918892486 ps
CPU time 313 seconds
Started Jun 25 05:03:16 PM PDT 24
Finished Jun 25 05:08:31 PM PDT 24
Peak memory 206884 kb
Host smart-f7e78215-140a-4f33-a909-77dd1f4148ee
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=647561338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.647561338
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.3736153619
Short name T1101
Test name
Test status
Simulation time 238126139 ps
CPU time 0.91 seconds
Started Jun 25 05:03:17 PM PDT 24
Finished Jun 25 05:03:20 PM PDT 24
Peak memory 206572 kb
Host smart-7531352d-4396-4d72-8ea4-1c1842481572
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3736153619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.3736153619
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.216461971
Short name T1859
Test name
Test status
Simulation time 190489494 ps
CPU time 0.96 seconds
Started Jun 25 05:03:17 PM PDT 24
Finished Jun 25 05:03:20 PM PDT 24
Peak memory 206596 kb
Host smart-49295e02-f283-4447-a867-307e38042685
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21646
1971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.216461971
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.652156335
Short name T2431
Test name
Test status
Simulation time 3944727312 ps
CPU time 26.66 seconds
Started Jun 25 05:03:19 PM PDT 24
Finished Jun 25 05:03:49 PM PDT 24
Peak memory 206944 kb
Host smart-417bc024-db84-4fdc-b439-48660a446737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65215
6335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.652156335
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.3469579801
Short name T613
Test name
Test status
Simulation time 10110038526 ps
CPU time 96.56 seconds
Started Jun 25 05:03:18 PM PDT 24
Finished Jun 25 05:04:58 PM PDT 24
Peak memory 206812 kb
Host smart-8b151e3c-4906-45e0-9bac-755b5672b35a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3469579801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.3469579801
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.4290428081
Short name T1448
Test name
Test status
Simulation time 149889627 ps
CPU time 0.83 seconds
Started Jun 25 05:03:16 PM PDT 24
Finished Jun 25 05:03:19 PM PDT 24
Peak memory 206580 kb
Host smart-0b445b44-390f-4ef9-ba46-efa64307ed46
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4290428081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.4290428081
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.3264487931
Short name T1673
Test name
Test status
Simulation time 152002657 ps
CPU time 0.8 seconds
Started Jun 25 05:03:13 PM PDT 24
Finished Jun 25 05:03:14 PM PDT 24
Peak memory 206580 kb
Host smart-fd9d5278-c1a9-414b-bf64-e45f0f7d7cdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32644
87931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.3264487931
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.872919668
Short name T2485
Test name
Test status
Simulation time 167423760 ps
CPU time 0.82 seconds
Started Jun 25 05:03:16 PM PDT 24
Finished Jun 25 05:03:19 PM PDT 24
Peak memory 206504 kb
Host smart-aad93b8f-e999-45c6-9e50-1f239c64ebf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87291
9668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.872919668
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.3520075721
Short name T1568
Test name
Test status
Simulation time 173725553 ps
CPU time 0.85 seconds
Started Jun 25 05:03:14 PM PDT 24
Finished Jun 25 05:03:16 PM PDT 24
Peak memory 206588 kb
Host smart-ae790713-8686-4d0a-a842-152091f6ff18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35200
75721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.3520075721
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.241291839
Short name T367
Test name
Test status
Simulation time 188958926 ps
CPU time 0.83 seconds
Started Jun 25 05:03:16 PM PDT 24
Finished Jun 25 05:03:19 PM PDT 24
Peak memory 206504 kb
Host smart-38f31019-7c8a-4fbe-8d08-0d99c1c0a125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24129
1839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.241291839
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.486141961
Short name T1767
Test name
Test status
Simulation time 200293276 ps
CPU time 0.86 seconds
Started Jun 25 05:03:13 PM PDT 24
Finished Jun 25 05:03:14 PM PDT 24
Peak memory 206748 kb
Host smart-f144e143-8bca-4ce3-bc2d-ca4f008b2ae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48614
1961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.486141961
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.443182615
Short name T1505
Test name
Test status
Simulation time 153462907 ps
CPU time 0.82 seconds
Started Jun 25 05:03:15 PM PDT 24
Finished Jun 25 05:03:17 PM PDT 24
Peak memory 206508 kb
Host smart-b6990806-cb7d-444d-8b01-d84b6eacd3fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44318
2615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.443182615
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.35732299
Short name T865
Test name
Test status
Simulation time 248322348 ps
CPU time 0.97 seconds
Started Jun 25 05:03:14 PM PDT 24
Finished Jun 25 05:03:16 PM PDT 24
Peak memory 206600 kb
Host smart-ff3fb21b-2c22-4563-9501-cfbfe8875b78
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=35732299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.35732299
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.989333168
Short name T2177
Test name
Test status
Simulation time 161253391 ps
CPU time 0.81 seconds
Started Jun 25 05:03:15 PM PDT 24
Finished Jun 25 05:03:18 PM PDT 24
Peak memory 206584 kb
Host smart-1c8f0b7a-f30a-41df-b35e-37ea87161251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98933
3168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.989333168
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.2555904444
Short name T774
Test name
Test status
Simulation time 29769264 ps
CPU time 0.71 seconds
Started Jun 25 05:03:15 PM PDT 24
Finished Jun 25 05:03:17 PM PDT 24
Peak memory 206568 kb
Host smart-9aa283c9-1962-4691-b925-3e15e86d34b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25559
04444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.2555904444
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.35399520
Short name T801
Test name
Test status
Simulation time 17499074835 ps
CPU time 38.26 seconds
Started Jun 25 05:03:17 PM PDT 24
Finished Jun 25 05:03:57 PM PDT 24
Peak memory 206936 kb
Host smart-fef3c52b-66f0-457f-9c93-93cecb7ff0a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35399
520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.35399520
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.3592384507
Short name T1080
Test name
Test status
Simulation time 176083289 ps
CPU time 0.86 seconds
Started Jun 25 05:03:14 PM PDT 24
Finished Jun 25 05:03:16 PM PDT 24
Peak memory 206500 kb
Host smart-14112762-2e55-40f2-a3e4-334b4fee22e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35923
84507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.3592384507
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.169741136
Short name T1865
Test name
Test status
Simulation time 223637114 ps
CPU time 0.91 seconds
Started Jun 25 05:03:14 PM PDT 24
Finished Jun 25 05:03:16 PM PDT 24
Peak memory 206564 kb
Host smart-6a14bfdd-a066-4655-82eb-ea99aed8a7d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16974
1136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.169741136
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.4194193532
Short name T737
Test name
Test status
Simulation time 157724423 ps
CPU time 0.81 seconds
Started Jun 25 05:03:13 PM PDT 24
Finished Jun 25 05:03:16 PM PDT 24
Peak memory 206604 kb
Host smart-81959eeb-2511-4dd0-bd87-dbe31069a65e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41941
93532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.4194193532
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.3026580290
Short name T989
Test name
Test status
Simulation time 140124545 ps
CPU time 0.83 seconds
Started Jun 25 05:03:20 PM PDT 24
Finished Jun 25 05:03:23 PM PDT 24
Peak memory 206552 kb
Host smart-0dfe16bb-4717-4ae3-b954-9488b99462ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30265
80290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.3026580290
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.593593241
Short name T1377
Test name
Test status
Simulation time 143611683 ps
CPU time 0.76 seconds
Started Jun 25 05:03:14 PM PDT 24
Finished Jun 25 05:03:16 PM PDT 24
Peak memory 206548 kb
Host smart-2b3d6420-cf8d-402d-80d3-c20fdfa3f0b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59359
3241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.593593241
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.2773638404
Short name T1840
Test name
Test status
Simulation time 185212423 ps
CPU time 0.79 seconds
Started Jun 25 05:03:13 PM PDT 24
Finished Jun 25 05:03:15 PM PDT 24
Peak memory 206596 kb
Host smart-0ecd8e40-40e7-449e-9189-b4f8ec5639bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27736
38404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.2773638404
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.1265251058
Short name T1447
Test name
Test status
Simulation time 154642584 ps
CPU time 0.85 seconds
Started Jun 25 05:03:19 PM PDT 24
Finished Jun 25 05:03:22 PM PDT 24
Peak memory 206532 kb
Host smart-ea660116-426b-453f-b09a-09a4817ff1b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12652
51058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.1265251058
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.1021408590
Short name T1723
Test name
Test status
Simulation time 205782563 ps
CPU time 0.94 seconds
Started Jun 25 05:03:16 PM PDT 24
Finished Jun 25 05:03:18 PM PDT 24
Peak memory 206512 kb
Host smart-52a9b4e2-2195-452f-9d8d-a895d00b09a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10214
08590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.1021408590
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.2802602824
Short name T485
Test name
Test status
Simulation time 10314271674 ps
CPU time 95.29 seconds
Started Jun 25 05:03:14 PM PDT 24
Finished Jun 25 05:04:51 PM PDT 24
Peak memory 206808 kb
Host smart-64b50bc8-26db-4262-a0d3-d9e2dca97e42
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2802602824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.2802602824
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.3161867278
Short name T1451
Test name
Test status
Simulation time 173674239 ps
CPU time 0.86 seconds
Started Jun 25 05:03:17 PM PDT 24
Finished Jun 25 05:03:20 PM PDT 24
Peak memory 206596 kb
Host smart-8f523293-6917-4e46-844d-7c74dea1d3ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31618
67278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.3161867278
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.4089334217
Short name T1832
Test name
Test status
Simulation time 177057602 ps
CPU time 0.77 seconds
Started Jun 25 05:03:17 PM PDT 24
Finished Jun 25 05:03:20 PM PDT 24
Peak memory 206592 kb
Host smart-679b38b5-44d1-4e26-a6b3-ce1dd4333677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40893
34217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.4089334217
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.195676790
Short name T1540
Test name
Test status
Simulation time 10832127363 ps
CPU time 110.48 seconds
Started Jun 25 05:03:14 PM PDT 24
Finished Jun 25 05:05:06 PM PDT 24
Peak memory 206832 kb
Host smart-d6319a16-1adb-4cc4-bfc9-61461eef11d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19567
6790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.195676790
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.2277223450
Short name T351
Test name
Test status
Simulation time 4146081825 ps
CPU time 4.5 seconds
Started Jun 25 05:03:18 PM PDT 24
Finished Jun 25 05:03:25 PM PDT 24
Peak memory 206904 kb
Host smart-ba89e0b3-449e-4659-9100-80ad29396901
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2277223450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.2277223450
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.984938419
Short name T1176
Test name
Test status
Simulation time 13293746975 ps
CPU time 12.49 seconds
Started Jun 25 05:03:13 PM PDT 24
Finished Jun 25 05:03:27 PM PDT 24
Peak memory 206644 kb
Host smart-3e2f7f38-94e0-462a-b1f5-b30417772428
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=984938419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.984938419
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.738539451
Short name T734
Test name
Test status
Simulation time 23402555567 ps
CPU time 25.44 seconds
Started Jun 25 05:03:18 PM PDT 24
Finished Jun 25 05:03:46 PM PDT 24
Peak memory 206928 kb
Host smart-ff1ca80e-955e-4d37-a0d9-e6beb6c066d9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=738539451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.738539451
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.2339352874
Short name T623
Test name
Test status
Simulation time 205502061 ps
CPU time 0.89 seconds
Started Jun 25 05:03:20 PM PDT 24
Finished Jun 25 05:03:24 PM PDT 24
Peak memory 206564 kb
Host smart-6ae29d3b-53be-464f-b4b3-ab0140a9cbdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23393
52874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.2339352874
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.1061052926
Short name T1924
Test name
Test status
Simulation time 172180437 ps
CPU time 0.84 seconds
Started Jun 25 05:03:19 PM PDT 24
Finished Jun 25 05:03:23 PM PDT 24
Peak memory 206500 kb
Host smart-40569688-eedf-42fe-a0f8-638efbdf9ea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10610
52926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.1061052926
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.695848534
Short name T2172
Test name
Test status
Simulation time 391902256 ps
CPU time 1.26 seconds
Started Jun 25 05:03:17 PM PDT 24
Finished Jun 25 05:03:20 PM PDT 24
Peak memory 206492 kb
Host smart-27cda2a3-6627-48a9-b79a-dcc9f9f664d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69584
8534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.695848534
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.752916536
Short name T748
Test name
Test status
Simulation time 925780064 ps
CPU time 1.93 seconds
Started Jun 25 05:03:13 PM PDT 24
Finished Jun 25 05:03:16 PM PDT 24
Peak memory 206720 kb
Host smart-752f9666-081f-4f9f-8fbc-1639e48e0ade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75291
6536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.752916536
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.2121376332
Short name T1547
Test name
Test status
Simulation time 15118995870 ps
CPU time 32.32 seconds
Started Jun 25 05:03:14 PM PDT 24
Finished Jun 25 05:03:47 PM PDT 24
Peak memory 206852 kb
Host smart-e9165bd5-9462-45dd-ab55-f3b510f0c47b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21213
76332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.2121376332
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.3322865913
Short name T2113
Test name
Test status
Simulation time 279849367 ps
CPU time 1.07 seconds
Started Jun 25 05:03:14 PM PDT 24
Finished Jun 25 05:03:16 PM PDT 24
Peak memory 206600 kb
Host smart-fa35513f-8e0a-4b1b-b302-20f949f9f45d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33228
65913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.3322865913
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.251787668
Short name T1981
Test name
Test status
Simulation time 141707912 ps
CPU time 0.81 seconds
Started Jun 25 05:03:16 PM PDT 24
Finished Jun 25 05:03:19 PM PDT 24
Peak memory 206868 kb
Host smart-61daa488-31aa-401d-9ace-86a8793efbce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25178
7668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.251787668
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.3453871173
Short name T1446
Test name
Test status
Simulation time 36244344 ps
CPU time 0.67 seconds
Started Jun 25 05:03:16 PM PDT 24
Finished Jun 25 05:03:19 PM PDT 24
Peak memory 206480 kb
Host smart-68bb8cd2-38f5-4b27-89fe-67c951f76b67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34538
71173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.3453871173
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.1072210446
Short name T1997
Test name
Test status
Simulation time 850235754 ps
CPU time 2.25 seconds
Started Jun 25 05:03:14 PM PDT 24
Finished Jun 25 05:03:18 PM PDT 24
Peak memory 206820 kb
Host smart-f563028d-064b-43d1-bdb9-310f049ce150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10722
10446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.1072210446
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.1022515479
Short name T2114
Test name
Test status
Simulation time 459399430 ps
CPU time 2.58 seconds
Started Jun 25 05:03:20 PM PDT 24
Finished Jun 25 05:03:25 PM PDT 24
Peak memory 206736 kb
Host smart-b92359cc-0c0f-45ce-9c9e-04d2b0532c11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10225
15479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.1022515479
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.1846504453
Short name T1764
Test name
Test status
Simulation time 188282085 ps
CPU time 0.89 seconds
Started Jun 25 05:03:17 PM PDT 24
Finished Jun 25 05:03:20 PM PDT 24
Peak memory 206576 kb
Host smart-1d8362c9-f7f8-4638-b495-2d897b5b9d2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18465
04453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.1846504453
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.525501814
Short name T510
Test name
Test status
Simulation time 143068896 ps
CPU time 0.77 seconds
Started Jun 25 05:03:15 PM PDT 24
Finished Jun 25 05:03:17 PM PDT 24
Peak memory 206564 kb
Host smart-7c4de6e1-1d69-40dc-87e0-a9f409580956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52550
1814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.525501814
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.1102993605
Short name T2229
Test name
Test status
Simulation time 218701518 ps
CPU time 0.91 seconds
Started Jun 25 05:03:16 PM PDT 24
Finished Jun 25 05:03:19 PM PDT 24
Peak memory 206856 kb
Host smart-f0f552b4-e0f8-41c9-86b3-346ad335ea9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11029
93605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.1102993605
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.2411455895
Short name T447
Test name
Test status
Simulation time 239710067 ps
CPU time 0.94 seconds
Started Jun 25 05:03:13 PM PDT 24
Finished Jun 25 05:03:15 PM PDT 24
Peak memory 206516 kb
Host smart-1df695b3-4a23-401e-b37d-35a288a5bf5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24114
55895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.2411455895
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.1161152183
Short name T1912
Test name
Test status
Simulation time 23294489175 ps
CPU time 23.14 seconds
Started Jun 25 05:03:20 PM PDT 24
Finished Jun 25 05:03:46 PM PDT 24
Peak memory 206712 kb
Host smart-aba5d54c-7f72-42de-ad52-e9b08b75ef74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11611
52183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.1161152183
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.2691092894
Short name T354
Test name
Test status
Simulation time 3311017876 ps
CPU time 3.82 seconds
Started Jun 25 05:03:17 PM PDT 24
Finished Jun 25 05:03:23 PM PDT 24
Peak memory 206612 kb
Host smart-64b6bbb6-fa88-4f25-bcfe-ba7843aba586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26910
92894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.2691092894
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.1026812454
Short name T1126
Test name
Test status
Simulation time 6550459245 ps
CPU time 48.64 seconds
Started Jun 25 05:03:20 PM PDT 24
Finished Jun 25 05:04:11 PM PDT 24
Peak memory 206988 kb
Host smart-ddcfc540-b710-4efe-861a-4c4d12630665
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1026812454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.1026812454
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.3441350185
Short name T1615
Test name
Test status
Simulation time 244533903 ps
CPU time 0.92 seconds
Started Jun 25 05:03:22 PM PDT 24
Finished Jun 25 05:03:25 PM PDT 24
Peak memory 206572 kb
Host smart-94c5c5bc-d32c-4c9c-bb27-ddca443cc6ea
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3441350185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.3441350185
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.1136503038
Short name T1509
Test name
Test status
Simulation time 188971848 ps
CPU time 0.89 seconds
Started Jun 25 05:03:16 PM PDT 24
Finished Jun 25 05:03:19 PM PDT 24
Peak memory 206880 kb
Host smart-722890a2-8d16-4f36-adc5-5acf1d25e951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11365
03038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.1136503038
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.1744732630
Short name T758
Test name
Test status
Simulation time 3687768803 ps
CPU time 35.47 seconds
Started Jun 25 05:03:19 PM PDT 24
Finished Jun 25 05:03:57 PM PDT 24
Peak memory 206780 kb
Host smart-f81de03c-f9e9-4c7c-8318-e837f2bf1d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17447
32630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.1744732630
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.1692128734
Short name T352
Test name
Test status
Simulation time 6127895373 ps
CPU time 173.86 seconds
Started Jun 25 05:03:19 PM PDT 24
Finished Jun 25 05:06:16 PM PDT 24
Peak memory 206896 kb
Host smart-48b41686-34a3-4758-93a4-94ebf5559b7f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1692128734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.1692128734
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.3232422817
Short name T1866
Test name
Test status
Simulation time 161448937 ps
CPU time 0.81 seconds
Started Jun 25 05:03:16 PM PDT 24
Finished Jun 25 05:03:19 PM PDT 24
Peak memory 206584 kb
Host smart-4acd6140-5fd2-4916-bd52-d33ee9adb4aa
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3232422817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.3232422817
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.4213328448
Short name T2000
Test name
Test status
Simulation time 153850765 ps
CPU time 0.77 seconds
Started Jun 25 05:03:17 PM PDT 24
Finished Jun 25 05:03:20 PM PDT 24
Peak memory 206496 kb
Host smart-5f4be7dd-632a-42b1-bf58-5bd453bcbd1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42133
28448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.4213328448
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.3102629690
Short name T140
Test name
Test status
Simulation time 210383635 ps
CPU time 0.87 seconds
Started Jun 25 05:03:20 PM PDT 24
Finished Jun 25 05:03:23 PM PDT 24
Peak memory 206520 kb
Host smart-1f7948fc-98f8-41e2-aba1-559adffbc91a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31026
29690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.3102629690
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.3812086721
Short name T1307
Test name
Test status
Simulation time 173585954 ps
CPU time 0.87 seconds
Started Jun 25 05:03:17 PM PDT 24
Finished Jun 25 05:03:20 PM PDT 24
Peak memory 206496 kb
Host smart-9a34aa28-5d55-4bd0-8247-982fd47e5ebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38120
86721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.3812086721
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.2154005056
Short name T2221
Test name
Test status
Simulation time 175244428 ps
CPU time 0.8 seconds
Started Jun 25 05:03:19 PM PDT 24
Finished Jun 25 05:03:22 PM PDT 24
Peak memory 206500 kb
Host smart-74c046ee-8b52-4a0a-bd40-a9b31f4737b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21540
05056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.2154005056
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.983264731
Short name T1269
Test name
Test status
Simulation time 154801756 ps
CPU time 0.84 seconds
Started Jun 25 05:03:19 PM PDT 24
Finished Jun 25 05:03:22 PM PDT 24
Peak memory 206592 kb
Host smart-1f365a1e-7111-4dfd-87d6-bbdcc11de490
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98326
4731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.983264731
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.109409784
Short name T2430
Test name
Test status
Simulation time 156415957 ps
CPU time 0.82 seconds
Started Jun 25 05:03:22 PM PDT 24
Finished Jun 25 05:03:24 PM PDT 24
Peak memory 206572 kb
Host smart-8553213b-dcf4-4f61-9640-79b72a494730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10940
9784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.109409784
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.3216578703
Short name T1870
Test name
Test status
Simulation time 208129253 ps
CPU time 0.88 seconds
Started Jun 25 05:03:18 PM PDT 24
Finished Jun 25 05:03:21 PM PDT 24
Peak memory 206456 kb
Host smart-ffbc1710-a151-4ae3-9a6d-4e4feac71fb5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3216578703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.3216578703
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.2545603654
Short name T376
Test name
Test status
Simulation time 151215132 ps
CPU time 0.78 seconds
Started Jun 25 05:03:19 PM PDT 24
Finished Jun 25 05:03:23 PM PDT 24
Peak memory 206572 kb
Host smart-e3b3daa6-0cf1-47ce-b916-b2606701e53f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25456
03654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.2545603654
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.3198049000
Short name T848
Test name
Test status
Simulation time 35447801 ps
CPU time 0.67 seconds
Started Jun 25 05:03:19 PM PDT 24
Finished Jun 25 05:03:23 PM PDT 24
Peak memory 206488 kb
Host smart-28beaf52-b604-4c46-a6e5-8dc7e9942c48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31980
49000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.3198049000
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.4186303268
Short name T1504
Test name
Test status
Simulation time 6008159168 ps
CPU time 13.89 seconds
Started Jun 25 05:03:20 PM PDT 24
Finished Jun 25 05:03:36 PM PDT 24
Peak memory 206900 kb
Host smart-0775d832-c0c9-4a7b-9324-748cc45e0ff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41863
03268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.4186303268
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.124057971
Short name T1393
Test name
Test status
Simulation time 190101544 ps
CPU time 0.88 seconds
Started Jun 25 05:03:20 PM PDT 24
Finished Jun 25 05:03:23 PM PDT 24
Peak memory 206520 kb
Host smart-a324c358-1cdc-43ff-81ae-df9c87e1b4e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12405
7971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.124057971
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.2927604217
Short name T470
Test name
Test status
Simulation time 203420867 ps
CPU time 0.85 seconds
Started Jun 25 05:03:18 PM PDT 24
Finished Jun 25 05:03:22 PM PDT 24
Peak memory 206484 kb
Host smart-f3cd0c41-1bf2-45be-85e1-371d2e0d667f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29276
04217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.2927604217
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.1852959615
Short name T2040
Test name
Test status
Simulation time 197176076 ps
CPU time 0.86 seconds
Started Jun 25 05:03:18 PM PDT 24
Finished Jun 25 05:03:21 PM PDT 24
Peak memory 206600 kb
Host smart-077bc903-65bf-494a-99bc-9f27571230f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18529
59615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.1852959615
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.2038530193
Short name T2437
Test name
Test status
Simulation time 197517063 ps
CPU time 0.8 seconds
Started Jun 25 05:03:19 PM PDT 24
Finished Jun 25 05:03:22 PM PDT 24
Peak memory 206516 kb
Host smart-f4c747df-b196-4fc6-aa6f-9825d0271b87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20385
30193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.2038530193
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.3439374613
Short name T1666
Test name
Test status
Simulation time 183323380 ps
CPU time 0.78 seconds
Started Jun 25 05:03:16 PM PDT 24
Finished Jun 25 05:03:18 PM PDT 24
Peak memory 206576 kb
Host smart-d3d8f0d3-5037-45a5-ac0d-0fe38277097e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34393
74613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.3439374613
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.2946920717
Short name T1891
Test name
Test status
Simulation time 161686058 ps
CPU time 0.81 seconds
Started Jun 25 05:03:22 PM PDT 24
Finished Jun 25 05:03:25 PM PDT 24
Peak memory 206568 kb
Host smart-913c4fca-2dfd-4070-b60f-911073274477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29469
20717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.2946920717
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.1608209538
Short name T1670
Test name
Test status
Simulation time 143287502 ps
CPU time 0.75 seconds
Started Jun 25 05:03:21 PM PDT 24
Finished Jun 25 05:03:24 PM PDT 24
Peak memory 206572 kb
Host smart-102c6ce1-0cc8-439c-b34b-ca3ad7c65ed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16082
09538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.1608209538
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.3412531066
Short name T563
Test name
Test status
Simulation time 200340763 ps
CPU time 0.85 seconds
Started Jun 25 05:03:12 PM PDT 24
Finished Jun 25 05:03:13 PM PDT 24
Peak memory 206612 kb
Host smart-9ff838c8-7c6d-48b2-a72b-18a611f0fc3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34125
31066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.3412531066
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.842152388
Short name T1440
Test name
Test status
Simulation time 10392961558 ps
CPU time 73.38 seconds
Started Jun 25 05:03:18 PM PDT 24
Finished Jun 25 05:04:34 PM PDT 24
Peak memory 206824 kb
Host smart-4136b59b-fd53-4dc8-9995-c60bf1a48117
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=842152388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.842152388
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.3133771969
Short name T1526
Test name
Test status
Simulation time 182792350 ps
CPU time 0.82 seconds
Started Jun 25 05:03:21 PM PDT 24
Finished Jun 25 05:03:24 PM PDT 24
Peak memory 206576 kb
Host smart-3b2591f2-655c-4b63-95ac-b83c6cb4f437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31337
71969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.3133771969
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.2810761025
Short name T987
Test name
Test status
Simulation time 170781799 ps
CPU time 0.81 seconds
Started Jun 25 05:03:16 PM PDT 24
Finished Jun 25 05:03:19 PM PDT 24
Peak memory 206580 kb
Host smart-803fd885-cb08-43e6-bce3-8a7f5d0bb02c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28107
61025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.2810761025
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.153270900
Short name T753
Test name
Test status
Simulation time 9295686432 ps
CPU time 87.72 seconds
Started Jun 25 05:03:18 PM PDT 24
Finished Jun 25 05:04:48 PM PDT 24
Peak memory 206952 kb
Host smart-b56bd68e-c3e8-460b-8242-8bdc490fa79f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15327
0900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.153270900
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.1192028445
Short name T1312
Test name
Test status
Simulation time 3937159031 ps
CPU time 4.83 seconds
Started Jun 25 05:03:16 PM PDT 24
Finished Jun 25 05:03:22 PM PDT 24
Peak memory 206820 kb
Host smart-dd59ae02-9c81-489b-b06a-971dba4ee1eb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1192028445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.1192028445
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.521612858
Short name T1492
Test name
Test status
Simulation time 13357118667 ps
CPU time 12.66 seconds
Started Jun 25 05:03:16 PM PDT 24
Finished Jun 25 05:03:30 PM PDT 24
Peak memory 206964 kb
Host smart-c8825549-51db-4c8c-80a1-c23a3397170b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=521612858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.521612858
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.1439212943
Short name T1974
Test name
Test status
Simulation time 23403423804 ps
CPU time 22.84 seconds
Started Jun 25 05:03:18 PM PDT 24
Finished Jun 25 05:03:43 PM PDT 24
Peak memory 206888 kb
Host smart-a42aa526-51f1-4c34-b37c-f57891b48369
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1439212943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.1439212943
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.3010055938
Short name T2
Test name
Test status
Simulation time 159197351 ps
CPU time 0.81 seconds
Started Jun 25 05:03:22 PM PDT 24
Finished Jun 25 05:03:24 PM PDT 24
Peak memory 206496 kb
Host smart-ab7269ea-db76-49d3-ace9-d147518f43e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30100
55938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.3010055938
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.2370869957
Short name T1697
Test name
Test status
Simulation time 167703208 ps
CPU time 0.8 seconds
Started Jun 25 05:03:20 PM PDT 24
Finished Jun 25 05:03:23 PM PDT 24
Peak memory 206592 kb
Host smart-dfb01e0e-42bd-4689-adf0-3587e32772b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23708
69957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.2370869957
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.913768131
Short name T87
Test name
Test status
Simulation time 470214632 ps
CPU time 1.46 seconds
Started Jun 25 05:03:18 PM PDT 24
Finished Jun 25 05:03:23 PM PDT 24
Peak memory 206736 kb
Host smart-d7269306-0128-434a-abe7-ec9eb854a4db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91376
8131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.913768131
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.533789817
Short name T108
Test name
Test status
Simulation time 1373498784 ps
CPU time 3.07 seconds
Started Jun 25 05:03:19 PM PDT 24
Finished Jun 25 05:03:25 PM PDT 24
Peak memory 206728 kb
Host smart-ff2cd7ec-e0a4-46eb-be59-c7f3363a3663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53378
9817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.533789817
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.649631572
Short name T96
Test name
Test status
Simulation time 9660993110 ps
CPU time 17.32 seconds
Started Jun 25 05:03:17 PM PDT 24
Finished Jun 25 05:03:37 PM PDT 24
Peak memory 206800 kb
Host smart-5f20f808-2fc6-4faf-9745-8a16151fc8d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64963
1572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.649631572
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.4176448382
Short name T2005
Test name
Test status
Simulation time 394006171 ps
CPU time 1.31 seconds
Started Jun 25 05:03:18 PM PDT 24
Finished Jun 25 05:03:22 PM PDT 24
Peak memory 206592 kb
Host smart-22857558-6cd6-454a-8d48-d9900ca309b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41764
48382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.4176448382
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.2754801414
Short name T1613
Test name
Test status
Simulation time 144135200 ps
CPU time 0.8 seconds
Started Jun 25 05:03:32 PM PDT 24
Finished Jun 25 05:03:35 PM PDT 24
Peak memory 206560 kb
Host smart-09649109-77c7-436d-900d-621fc3b570d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27548
01414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.2754801414
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.2459621060
Short name T1591
Test name
Test status
Simulation time 60412766 ps
CPU time 0.73 seconds
Started Jun 25 05:03:32 PM PDT 24
Finished Jun 25 05:03:35 PM PDT 24
Peak memory 206568 kb
Host smart-1754383a-0bce-404d-8647-0d0241726163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24596
21060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.2459621060
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.1713465317
Short name T1079
Test name
Test status
Simulation time 1018356850 ps
CPU time 2.46 seconds
Started Jun 25 05:03:34 PM PDT 24
Finished Jun 25 05:03:39 PM PDT 24
Peak memory 206788 kb
Host smart-d701f7e1-a745-4889-b148-13c5d29cfd19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17134
65317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.1713465317
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.901183387
Short name T2366
Test name
Test status
Simulation time 240301452 ps
CPU time 1.51 seconds
Started Jun 25 05:03:33 PM PDT 24
Finished Jun 25 05:03:38 PM PDT 24
Peak memory 206800 kb
Host smart-ed690166-62e1-4d5d-99af-ac6be131f941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90118
3387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.901183387
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.1892231009
Short name T725
Test name
Test status
Simulation time 238435406 ps
CPU time 0.87 seconds
Started Jun 25 05:03:33 PM PDT 24
Finished Jun 25 05:03:37 PM PDT 24
Peak memory 206504 kb
Host smart-4e1e8900-906d-48ba-bb2b-56d02f044736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18922
31009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.1892231009
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.1833698213
Short name T1846
Test name
Test status
Simulation time 135546836 ps
CPU time 0.85 seconds
Started Jun 25 05:03:31 PM PDT 24
Finished Jun 25 05:03:33 PM PDT 24
Peak memory 206540 kb
Host smart-15e3d859-9df6-4660-9304-19efd103f374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18336
98213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.1833698213
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.2024096815
Short name T655
Test name
Test status
Simulation time 206347886 ps
CPU time 0.96 seconds
Started Jun 25 05:03:31 PM PDT 24
Finished Jun 25 05:03:33 PM PDT 24
Peak memory 206508 kb
Host smart-11780efa-7bed-405f-b8ad-b3562dd91c9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20240
96815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.2024096815
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.2938980018
Short name T663
Test name
Test status
Simulation time 182587325 ps
CPU time 0.82 seconds
Started Jun 25 05:03:34 PM PDT 24
Finished Jun 25 05:03:37 PM PDT 24
Peak memory 206496 kb
Host smart-8208b2d0-ced5-4e04-82c6-46968feb643d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29389
80018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.2938980018
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.2639246061
Short name T1369
Test name
Test status
Simulation time 23381888226 ps
CPU time 23.43 seconds
Started Jun 25 05:03:31 PM PDT 24
Finished Jun 25 05:03:57 PM PDT 24
Peak memory 206700 kb
Host smart-ff09210d-36c9-4205-93cf-7f7ab77e80eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26392
46061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.2639246061
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.1986650286
Short name T1567
Test name
Test status
Simulation time 3330234510 ps
CPU time 4.06 seconds
Started Jun 25 05:03:37 PM PDT 24
Finished Jun 25 05:03:44 PM PDT 24
Peak memory 206688 kb
Host smart-2471e746-6949-412c-98b5-7882ba341f62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19866
50286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.1986650286
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.3939322134
Short name T2208
Test name
Test status
Simulation time 3771224438 ps
CPU time 106.32 seconds
Started Jun 25 05:03:30 PM PDT 24
Finished Jun 25 05:05:17 PM PDT 24
Peak memory 206892 kb
Host smart-e60a4b43-65d2-422c-b49a-6e6919fb67c1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3939322134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.3939322134
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.395030669
Short name T1299
Test name
Test status
Simulation time 242016730 ps
CPU time 0.91 seconds
Started Jun 25 05:03:35 PM PDT 24
Finished Jun 25 05:03:39 PM PDT 24
Peak memory 206592 kb
Host smart-8bdca4b2-e6fd-46a7-9090-91a91fa9b25d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=395030669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.395030669
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.2479919399
Short name T1479
Test name
Test status
Simulation time 194708773 ps
CPU time 0.87 seconds
Started Jun 25 05:03:38 PM PDT 24
Finished Jun 25 05:03:42 PM PDT 24
Peak memory 206576 kb
Host smart-92a73559-ae55-47a0-8290-6f89a815416f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24799
19399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.2479919399
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.3901798271
Short name T211
Test name
Test status
Simulation time 12942690779 ps
CPU time 89.7 seconds
Started Jun 25 05:03:33 PM PDT 24
Finished Jun 25 05:05:06 PM PDT 24
Peak memory 206808 kb
Host smart-71c77504-733b-494b-a5eb-b823d30b1e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39017
98271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.3901798271
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.3651221394
Short name T1598
Test name
Test status
Simulation time 4049189089 ps
CPU time 112.89 seconds
Started Jun 25 05:03:32 PM PDT 24
Finished Jun 25 05:05:27 PM PDT 24
Peak memory 206912 kb
Host smart-34c281b1-c0f4-40e9-987c-5927c085b7c8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3651221394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.3651221394
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.2843148939
Short name T305
Test name
Test status
Simulation time 169233616 ps
CPU time 0.84 seconds
Started Jun 25 05:03:31 PM PDT 24
Finished Jun 25 05:03:33 PM PDT 24
Peak memory 206488 kb
Host smart-1d647042-d32f-4477-b53b-b6f9b9acd89f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2843148939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.2843148939
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.3957052591
Short name T2365
Test name
Test status
Simulation time 164735687 ps
CPU time 0.78 seconds
Started Jun 25 05:03:31 PM PDT 24
Finished Jun 25 05:03:33 PM PDT 24
Peak memory 206576 kb
Host smart-643e4565-c021-4365-a2be-7d6c84db37c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39570
52591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.3957052591
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.4085497474
Short name T2342
Test name
Test status
Simulation time 253841378 ps
CPU time 0.9 seconds
Started Jun 25 05:03:29 PM PDT 24
Finished Jun 25 05:03:31 PM PDT 24
Peak memory 206568 kb
Host smart-f11807da-f3e9-4b0c-8c51-9b846746fc10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40854
97474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.4085497474
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.2262858987
Short name T632
Test name
Test status
Simulation time 255146953 ps
CPU time 0.91 seconds
Started Jun 25 05:03:33 PM PDT 24
Finished Jun 25 05:03:37 PM PDT 24
Peak memory 206524 kb
Host smart-32bd1116-765e-4e0a-aa0d-53dbb9d6fbe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22628
58987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.2262858987
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.3524393506
Short name T1119
Test name
Test status
Simulation time 198830560 ps
CPU time 0.8 seconds
Started Jun 25 05:03:38 PM PDT 24
Finished Jun 25 05:03:42 PM PDT 24
Peak memory 206572 kb
Host smart-17f28bfc-58dd-4961-9554-4c803560a5a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35243
93506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.3524393506
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.533267304
Short name T1978
Test name
Test status
Simulation time 185742963 ps
CPU time 0.87 seconds
Started Jun 25 05:03:39 PM PDT 24
Finished Jun 25 05:03:42 PM PDT 24
Peak memory 206572 kb
Host smart-1d430758-6028-414a-8fb3-360b3d96a204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53326
7304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.533267304
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.3912070596
Short name T910
Test name
Test status
Simulation time 182954927 ps
CPU time 0.79 seconds
Started Jun 25 05:03:34 PM PDT 24
Finished Jun 25 05:03:38 PM PDT 24
Peak memory 206576 kb
Host smart-1969ebee-14e7-4d13-bc26-d1a469864f49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39120
70596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.3912070596
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.640061196
Short name T2160
Test name
Test status
Simulation time 226963991 ps
CPU time 0.88 seconds
Started Jun 25 05:03:33 PM PDT 24
Finished Jun 25 05:03:37 PM PDT 24
Peak memory 206508 kb
Host smart-50b55630-2bd1-4292-9dbe-2355277a9e46
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=640061196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.640061196
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.207573610
Short name T190
Test name
Test status
Simulation time 155947544 ps
CPU time 0.75 seconds
Started Jun 25 05:03:32 PM PDT 24
Finished Jun 25 05:03:35 PM PDT 24
Peak memory 206500 kb
Host smart-53ec36fe-b4bd-4e93-9e36-ece121367bcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20757
3610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.207573610
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.2703708899
Short name T1436
Test name
Test status
Simulation time 49823284 ps
CPU time 0.68 seconds
Started Jun 25 05:03:32 PM PDT 24
Finished Jun 25 05:03:35 PM PDT 24
Peak memory 206496 kb
Host smart-b185f839-0545-4785-ba76-ed0519f3b64f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27037
08899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.2703708899
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.1910542552
Short name T178
Test name
Test status
Simulation time 13813467277 ps
CPU time 30.72 seconds
Started Jun 25 05:03:31 PM PDT 24
Finished Jun 25 05:04:04 PM PDT 24
Peak memory 206796 kb
Host smart-dde80619-aa1c-4552-88b1-5e849baff4a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19105
42552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.1910542552
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.2576929734
Short name T1252
Test name
Test status
Simulation time 193782446 ps
CPU time 0.84 seconds
Started Jun 25 05:03:32 PM PDT 24
Finished Jun 25 05:03:36 PM PDT 24
Peak memory 206504 kb
Host smart-d27e0008-791a-402a-98d3-7abbeba5e36d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25769
29734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.2576929734
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.1846057895
Short name T812
Test name
Test status
Simulation time 187393393 ps
CPU time 0.86 seconds
Started Jun 25 05:03:31 PM PDT 24
Finished Jun 25 05:03:33 PM PDT 24
Peak memory 206512 kb
Host smart-947e0ad2-d760-44bf-9b0b-12b34c82dabd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18460
57895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.1846057895
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.271006572
Short name T1438
Test name
Test status
Simulation time 204365911 ps
CPU time 0.9 seconds
Started Jun 25 05:03:31 PM PDT 24
Finished Jun 25 05:03:33 PM PDT 24
Peak memory 206592 kb
Host smart-0a4e9222-27cf-4ab5-b13e-e1e4ae9e99ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27100
6572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.271006572
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.3606834992
Short name T1597
Test name
Test status
Simulation time 213128030 ps
CPU time 0.83 seconds
Started Jun 25 05:03:38 PM PDT 24
Finished Jun 25 05:03:42 PM PDT 24
Peak memory 206576 kb
Host smart-4e82a18a-88cf-4658-8832-55e01d5312af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36068
34992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.3606834992
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.2762974559
Short name T2190
Test name
Test status
Simulation time 179070561 ps
CPU time 0.81 seconds
Started Jun 25 05:03:31 PM PDT 24
Finished Jun 25 05:03:34 PM PDT 24
Peak memory 206504 kb
Host smart-3ba2afe0-8d9b-4142-96f1-5687331e2ae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27629
74559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.2762974559
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.3350554797
Short name T1998
Test name
Test status
Simulation time 171619765 ps
CPU time 0.75 seconds
Started Jun 25 05:03:34 PM PDT 24
Finished Jun 25 05:03:37 PM PDT 24
Peak memory 206588 kb
Host smart-375bd90d-93be-4fe3-93e4-1786cdc6ea6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33505
54797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.3350554797
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.3235901006
Short name T1443
Test name
Test status
Simulation time 153093907 ps
CPU time 0.8 seconds
Started Jun 25 05:03:35 PM PDT 24
Finished Jun 25 05:03:39 PM PDT 24
Peak memory 206332 kb
Host smart-709ae6a5-a66d-4101-95b2-a84a50d18422
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32359
01006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.3235901006
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.729833346
Short name T2315
Test name
Test status
Simulation time 250482374 ps
CPU time 1 seconds
Started Jun 25 05:03:32 PM PDT 24
Finished Jun 25 05:03:36 PM PDT 24
Peak memory 206584 kb
Host smart-26b82006-4774-4099-8145-d909e1bbd673
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72983
3346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.729833346
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.2098064697
Short name T786
Test name
Test status
Simulation time 5892982329 ps
CPU time 156.39 seconds
Started Jun 25 05:03:32 PM PDT 24
Finished Jun 25 05:06:11 PM PDT 24
Peak memory 206872 kb
Host smart-72364108-74b7-497b-b1f1-b55c88b43803
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2098064697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.2098064697
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.1569381168
Short name T2272
Test name
Test status
Simulation time 164996732 ps
CPU time 0.91 seconds
Started Jun 25 05:03:31 PM PDT 24
Finished Jun 25 05:03:34 PM PDT 24
Peak memory 206604 kb
Host smart-7a2e4df1-280c-4b36-91f0-5ac55c1d9195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15693
81168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.1569381168
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.2746028584
Short name T509
Test name
Test status
Simulation time 152639653 ps
CPU time 0.76 seconds
Started Jun 25 05:03:32 PM PDT 24
Finished Jun 25 05:03:36 PM PDT 24
Peak memory 206520 kb
Host smart-08252aea-1a76-4600-a74c-0fca8596c0d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27460
28584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.2746028584
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.2443994132
Short name T1246
Test name
Test status
Simulation time 7488654286 ps
CPU time 222.31 seconds
Started Jun 25 05:03:32 PM PDT 24
Finished Jun 25 05:07:17 PM PDT 24
Peak memory 206920 kb
Host smart-abeeff3d-3641-449a-8cc2-ec653d2877d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24439
94132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.2443994132
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.3766506792
Short name T1743
Test name
Test status
Simulation time 3889933260 ps
CPU time 4.33 seconds
Started Jun 25 05:03:31 PM PDT 24
Finished Jun 25 05:03:37 PM PDT 24
Peak memory 206696 kb
Host smart-f7ca0ccf-f85e-4f65-acd6-8ddf1613bb48
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3766506792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.3766506792
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.409165610
Short name T1358
Test name
Test status
Simulation time 13409028679 ps
CPU time 13.63 seconds
Started Jun 25 05:03:34 PM PDT 24
Finished Jun 25 05:03:50 PM PDT 24
Peak memory 206900 kb
Host smart-04bb3a26-d8ff-4237-9515-1f6275d99a6d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=409165610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.409165610
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.3669035777
Short name T2357
Test name
Test status
Simulation time 23399787283 ps
CPU time 30.44 seconds
Started Jun 25 05:03:32 PM PDT 24
Finished Jun 25 05:04:05 PM PDT 24
Peak memory 206716 kb
Host smart-f3f6e911-939a-4b81-8394-1b8633ecfed3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3669035777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.3669035777
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.441114543
Short name T1233
Test name
Test status
Simulation time 188692481 ps
CPU time 0.86 seconds
Started Jun 25 05:03:32 PM PDT 24
Finished Jun 25 05:03:36 PM PDT 24
Peak memory 206556 kb
Host smart-d2cd5714-d512-4250-b5a7-25c5b3eb44dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44111
4543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.441114543
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.3472034043
Short name T1618
Test name
Test status
Simulation time 141225269 ps
CPU time 0.74 seconds
Started Jun 25 05:03:30 PM PDT 24
Finished Jun 25 05:03:32 PM PDT 24
Peak memory 206500 kb
Host smart-88cd2be2-079f-40a0-aa1d-98383c66573e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34720
34043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.3472034043
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.1837810019
Short name T2414
Test name
Test status
Simulation time 579285548 ps
CPU time 1.76 seconds
Started Jun 25 05:03:31 PM PDT 24
Finished Jun 25 05:03:35 PM PDT 24
Peak memory 206708 kb
Host smart-a176e031-415b-4199-905a-5ea8157331db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18378
10019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.1837810019
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.2934446155
Short name T1089
Test name
Test status
Simulation time 1372733584 ps
CPU time 3.04 seconds
Started Jun 25 05:03:38 PM PDT 24
Finished Jun 25 05:03:44 PM PDT 24
Peak memory 206812 kb
Host smart-7a4077d2-cd50-4e32-b2c0-b5a25c5ed282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29344
46155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.2934446155
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.815310150
Short name T654
Test name
Test status
Simulation time 11877595688 ps
CPU time 22.23 seconds
Started Jun 25 05:03:34 PM PDT 24
Finished Jun 25 05:03:59 PM PDT 24
Peak memory 206932 kb
Host smart-d7757a57-4c48-4ecc-b243-62826f6f4b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81531
0150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.815310150
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.748383281
Short name T1961
Test name
Test status
Simulation time 348679716 ps
CPU time 1.17 seconds
Started Jun 25 05:03:29 PM PDT 24
Finished Jun 25 05:03:31 PM PDT 24
Peak memory 206576 kb
Host smart-1f92078c-04d9-4984-8fc6-b16df3b605e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74838
3281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.748383281
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.2922442354
Short name T630
Test name
Test status
Simulation time 137281209 ps
CPU time 0.77 seconds
Started Jun 25 05:03:31 PM PDT 24
Finished Jun 25 05:03:34 PM PDT 24
Peak memory 206588 kb
Host smart-ce39044d-6aa3-4e26-a292-f4da52cd6dbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29224
42354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.2922442354
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.2903209315
Short name T1157
Test name
Test status
Simulation time 39745622 ps
CPU time 0.65 seconds
Started Jun 25 05:03:38 PM PDT 24
Finished Jun 25 05:03:42 PM PDT 24
Peak memory 206552 kb
Host smart-b287d66b-a30c-4a75-b5b7-bac16981f1e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29032
09315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.2903209315
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.1668875943
Short name T553
Test name
Test status
Simulation time 993326615 ps
CPU time 2.31 seconds
Started Jun 25 05:03:32 PM PDT 24
Finished Jun 25 05:03:37 PM PDT 24
Peak memory 206820 kb
Host smart-23c70107-a211-4558-837d-48b4112999df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16688
75943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.1668875943
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.3920401614
Short name T182
Test name
Test status
Simulation time 222493358 ps
CPU time 1.43 seconds
Started Jun 25 05:03:32 PM PDT 24
Finished Jun 25 05:03:36 PM PDT 24
Peak memory 206728 kb
Host smart-60a6b51f-ac6c-4882-a53d-e0ce2a1a4522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39204
01614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.3920401614
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.3324832920
Short name T496
Test name
Test status
Simulation time 210831734 ps
CPU time 0.83 seconds
Started Jun 25 05:03:38 PM PDT 24
Finished Jun 25 05:03:42 PM PDT 24
Peak memory 206568 kb
Host smart-ac62d58c-b933-4848-a6c3-70e4ee105f84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33248
32920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.3324832920
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.3637587425
Short name T535
Test name
Test status
Simulation time 148901508 ps
CPU time 0.78 seconds
Started Jun 25 05:03:34 PM PDT 24
Finished Jun 25 05:03:38 PM PDT 24
Peak memory 206580 kb
Host smart-9353b6e4-25d1-41b7-b28c-b8c3ea861873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36375
87425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.3637587425
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.1103358134
Short name T776
Test name
Test status
Simulation time 216399855 ps
CPU time 0.86 seconds
Started Jun 25 05:03:35 PM PDT 24
Finished Jun 25 05:03:39 PM PDT 24
Peak memory 206340 kb
Host smart-4823a9d6-a3ff-4a14-b2c5-4063862e1eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11033
58134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.1103358134
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_invalid_sync.4130723401
Short name T1365
Test name
Test status
Simulation time 18301510825 ps
CPU time 137.5 seconds
Started Jun 25 05:03:38 PM PDT 24
Finished Jun 25 05:05:58 PM PDT 24
Peak memory 206968 kb
Host smart-30dbde31-5e00-481c-a11c-fbda09b8cae1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4130723401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.4130723401
Directory /workspace/48.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.3920272742
Short name T295
Test name
Test status
Simulation time 177131880 ps
CPU time 0.8 seconds
Started Jun 25 05:03:37 PM PDT 24
Finished Jun 25 05:03:41 PM PDT 24
Peak memory 206572 kb
Host smart-f719481e-7986-4c6e-8151-a3922dcaa4c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39202
72742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.3920272742
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.3856588564
Short name T2377
Test name
Test status
Simulation time 23262554630 ps
CPU time 27.61 seconds
Started Jun 25 05:03:34 PM PDT 24
Finished Jun 25 05:04:04 PM PDT 24
Peak memory 206628 kb
Host smart-7b37796d-bc2d-4fb6-94f4-293420fed8d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38565
88564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.3856588564
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.3241160381
Short name T2183
Test name
Test status
Simulation time 3331720087 ps
CPU time 3.65 seconds
Started Jun 25 05:03:33 PM PDT 24
Finished Jun 25 05:03:39 PM PDT 24
Peak memory 206696 kb
Host smart-640fe94d-7f93-4794-b653-0db589ab1fc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32411
60381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.3241160381
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.2496653729
Short name T1055
Test name
Test status
Simulation time 7778897172 ps
CPU time 76.82 seconds
Started Jun 25 05:03:33 PM PDT 24
Finished Jun 25 05:04:52 PM PDT 24
Peak memory 206964 kb
Host smart-d0de039b-1da4-492e-8092-6c233180f544
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2496653729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.2496653729
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.1025794824
Short name T718
Test name
Test status
Simulation time 264229548 ps
CPU time 0.92 seconds
Started Jun 25 05:03:34 PM PDT 24
Finished Jun 25 05:03:38 PM PDT 24
Peak memory 206464 kb
Host smart-8f75da90-f7f4-432f-bf73-6230aa757e0f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1025794824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.1025794824
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.562574594
Short name T586
Test name
Test status
Simulation time 215796399 ps
CPU time 0.86 seconds
Started Jun 25 05:03:38 PM PDT 24
Finished Jun 25 05:03:42 PM PDT 24
Peak memory 206576 kb
Host smart-a02fb283-074b-4506-be00-ff1689b12e8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56257
4594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.562574594
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.3160640626
Short name T870
Test name
Test status
Simulation time 7830920611 ps
CPU time 222.74 seconds
Started Jun 25 05:03:34 PM PDT 24
Finished Jun 25 05:07:20 PM PDT 24
Peak memory 206808 kb
Host smart-adea5fc4-9b69-4adc-bfe7-3fdfe3f69bd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31606
40626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.3160640626
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.373083289
Short name T920
Test name
Test status
Simulation time 3018663395 ps
CPU time 21.83 seconds
Started Jun 25 05:03:33 PM PDT 24
Finished Jun 25 05:03:57 PM PDT 24
Peak memory 206896 kb
Host smart-7c49ff31-94ad-4a38-970a-a97fd0294f21
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=373083289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.373083289
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.2731850223
Short name T2186
Test name
Test status
Simulation time 157919238 ps
CPU time 0.79 seconds
Started Jun 25 05:03:45 PM PDT 24
Finished Jun 25 05:03:48 PM PDT 24
Peak memory 206576 kb
Host smart-d815513a-15c3-468a-9d93-64bf1c269452
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2731850223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.2731850223
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.4053314776
Short name T1746
Test name
Test status
Simulation time 156190915 ps
CPU time 0.77 seconds
Started Jun 25 05:03:32 PM PDT 24
Finished Jun 25 05:03:35 PM PDT 24
Peak memory 206572 kb
Host smart-b3396f54-8c6c-49ca-af1a-30e34de043bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40533
14776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.4053314776
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.4000246281
Short name T117
Test name
Test status
Simulation time 156520714 ps
CPU time 0.75 seconds
Started Jun 25 05:03:33 PM PDT 24
Finished Jun 25 05:03:36 PM PDT 24
Peak memory 206500 kb
Host smart-768ca4ab-7a68-47f0-b7ef-a73316e0c720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40002
46281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.4000246281
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.3705699938
Short name T2030
Test name
Test status
Simulation time 184542621 ps
CPU time 0.87 seconds
Started Jun 25 05:03:33 PM PDT 24
Finished Jun 25 05:03:37 PM PDT 24
Peak memory 206576 kb
Host smart-13cd2a5c-7d92-4d29-8037-627cb4737088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37056
99938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.3705699938
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.3515923275
Short name T208
Test name
Test status
Simulation time 174425009 ps
CPU time 0.82 seconds
Started Jun 25 05:03:34 PM PDT 24
Finished Jun 25 05:03:37 PM PDT 24
Peak memory 206592 kb
Host smart-ad15c54e-194d-43f2-bce5-045d2abf3e5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35159
23275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.3515923275
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.2386845267
Short name T397
Test name
Test status
Simulation time 177843709 ps
CPU time 0.86 seconds
Started Jun 25 05:03:33 PM PDT 24
Finished Jun 25 05:03:36 PM PDT 24
Peak memory 206500 kb
Host smart-fd24d099-56a3-494b-8681-7c19e7f5ac95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23868
45267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.2386845267
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.773221339
Short name T594
Test name
Test status
Simulation time 151726800 ps
CPU time 0.8 seconds
Started Jun 25 05:03:34 PM PDT 24
Finished Jun 25 05:03:38 PM PDT 24
Peak memory 206460 kb
Host smart-83d30e1f-2375-49ac-9e77-56036e49d16b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77322
1339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.773221339
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.4244944613
Short name T1137
Test name
Test status
Simulation time 203753799 ps
CPU time 0.91 seconds
Started Jun 25 05:03:35 PM PDT 24
Finished Jun 25 05:03:39 PM PDT 24
Peak memory 206508 kb
Host smart-84063b65-ebaf-4f03-b680-1c2ec0d7c0c5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4244944613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.4244944613
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.1754303302
Short name T374
Test name
Test status
Simulation time 182180875 ps
CPU time 0.8 seconds
Started Jun 25 05:03:35 PM PDT 24
Finished Jun 25 05:03:39 PM PDT 24
Peak memory 206532 kb
Host smart-17d9dc1b-c628-46fe-8374-7a5099dd5843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17543
03302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.1754303302
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.1955578200
Short name T531
Test name
Test status
Simulation time 74567735 ps
CPU time 0.74 seconds
Started Jun 25 05:03:38 PM PDT 24
Finished Jun 25 05:03:42 PM PDT 24
Peak memory 206492 kb
Host smart-9d378f9b-4714-45bb-b567-a097749cb1c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19555
78200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.1955578200
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.3896483279
Short name T794
Test name
Test status
Simulation time 12133706775 ps
CPU time 26.44 seconds
Started Jun 25 05:03:37 PM PDT 24
Finished Jun 25 05:04:07 PM PDT 24
Peak memory 206856 kb
Host smart-fb7e308c-180c-477c-9603-b5aaf6bef00c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38964
83279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.3896483279
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.2501824500
Short name T518
Test name
Test status
Simulation time 166684482 ps
CPU time 0.82 seconds
Started Jun 25 05:03:35 PM PDT 24
Finished Jun 25 05:03:39 PM PDT 24
Peak memory 206528 kb
Host smart-ca20e64b-446d-4eba-94b7-e04e82c5c34e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25018
24500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.2501824500
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.933764907
Short name T2102
Test name
Test status
Simulation time 199311156 ps
CPU time 0.82 seconds
Started Jun 25 05:03:38 PM PDT 24
Finished Jun 25 05:03:42 PM PDT 24
Peak memory 206568 kb
Host smart-512a88af-2378-4c86-a215-ec1a4aacae1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93376
4907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.933764907
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.1113122510
Short name T1328
Test name
Test status
Simulation time 246064858 ps
CPU time 0.97 seconds
Started Jun 25 05:03:35 PM PDT 24
Finished Jun 25 05:03:40 PM PDT 24
Peak memory 206484 kb
Host smart-b559f735-4f9a-43ae-9eed-51a8a181c550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11131
22510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.1113122510
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.2874774299
Short name T1376
Test name
Test status
Simulation time 186486092 ps
CPU time 0.88 seconds
Started Jun 25 05:03:37 PM PDT 24
Finished Jun 25 05:03:41 PM PDT 24
Peak memory 206500 kb
Host smart-396f53ab-d088-454b-b1ab-2f465780fec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28747
74299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.2874774299
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.1524939482
Short name T1122
Test name
Test status
Simulation time 165263936 ps
CPU time 0.79 seconds
Started Jun 25 05:03:33 PM PDT 24
Finished Jun 25 05:03:36 PM PDT 24
Peak memory 206512 kb
Host smart-fb1f6bcd-b98c-41ec-a1bc-555f4aa4b05e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15249
39482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.1524939482
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.1768170863
Short name T1637
Test name
Test status
Simulation time 170593430 ps
CPU time 0.82 seconds
Started Jun 25 05:03:38 PM PDT 24
Finished Jun 25 05:03:41 PM PDT 24
Peak memory 206500 kb
Host smart-dc8fd6d4-1fcb-40ae-992e-c7f9de3243b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17681
70863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.1768170863
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.2765370047
Short name T677
Test name
Test status
Simulation time 160190809 ps
CPU time 0.79 seconds
Started Jun 25 05:03:35 PM PDT 24
Finished Jun 25 05:03:39 PM PDT 24
Peak memory 206592 kb
Host smart-21d10d6f-b16d-4b5a-ad78-ffb25d22327d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27653
70047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.2765370047
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.1935850148
Short name T572
Test name
Test status
Simulation time 228603257 ps
CPU time 0.97 seconds
Started Jun 25 05:03:35 PM PDT 24
Finished Jun 25 05:03:39 PM PDT 24
Peak memory 206536 kb
Host smart-774bc575-7bcf-47e7-845e-3094e9285998
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19358
50148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.1935850148
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.2157139204
Short name T1947
Test name
Test status
Simulation time 172036029 ps
CPU time 0.9 seconds
Started Jun 25 05:03:39 PM PDT 24
Finished Jun 25 05:03:42 PM PDT 24
Peak memory 206504 kb
Host smart-f40bcefd-b0ef-4af8-8ae5-5bc05e4496fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21571
39204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.2157139204
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.2996687226
Short name T961
Test name
Test status
Simulation time 221307044 ps
CPU time 0.87 seconds
Started Jun 25 05:03:37 PM PDT 24
Finished Jun 25 05:03:41 PM PDT 24
Peak memory 206496 kb
Host smart-df2f6560-0874-4b8a-8e6b-38ae1a4d0e9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29966
87226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.2996687226
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.1053967735
Short name T1402
Test name
Test status
Simulation time 4710566039 ps
CPU time 136.87 seconds
Started Jun 25 05:03:36 PM PDT 24
Finished Jun 25 05:05:56 PM PDT 24
Peak memory 206924 kb
Host smart-3354cf29-5543-4d9a-86fa-47454c11b762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10539
67735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.1053967735
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.1775342521
Short name T2494
Test name
Test status
Simulation time 4243124962 ps
CPU time 4.71 seconds
Started Jun 25 05:03:36 PM PDT 24
Finished Jun 25 05:03:44 PM PDT 24
Peak memory 206948 kb
Host smart-4b55209d-9b1b-43b5-a64c-3a8e37ee1fa8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1775342521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.1775342521
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.788757085
Short name T14
Test name
Test status
Simulation time 13315469531 ps
CPU time 12.22 seconds
Started Jun 25 05:03:45 PM PDT 24
Finished Jun 25 05:03:59 PM PDT 24
Peak memory 206888 kb
Host smart-6ade0356-cb7c-4764-9ae2-5531cef4e3db
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=788757085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.788757085
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.3547717324
Short name T2461
Test name
Test status
Simulation time 23405069951 ps
CPU time 28.51 seconds
Started Jun 25 05:03:44 PM PDT 24
Finished Jun 25 05:04:13 PM PDT 24
Peak memory 206968 kb
Host smart-f73a58e9-64a0-4407-bd97-91163be549bd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3547717324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.3547717324
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.875046380
Short name T1732
Test name
Test status
Simulation time 167480691 ps
CPU time 0.87 seconds
Started Jun 25 05:03:36 PM PDT 24
Finished Jun 25 05:03:40 PM PDT 24
Peak memory 206572 kb
Host smart-330cd350-96be-467f-beb9-14a89ebb41cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87504
6380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.875046380
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.4043859167
Short name T1425
Test name
Test status
Simulation time 159235874 ps
CPU time 0.78 seconds
Started Jun 25 05:03:37 PM PDT 24
Finished Jun 25 05:03:41 PM PDT 24
Peak memory 206572 kb
Host smart-3a1b7f0b-3e11-4706-8318-872f93f8e259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40438
59167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.4043859167
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.3284555281
Short name T176
Test name
Test status
Simulation time 412737962 ps
CPU time 1.34 seconds
Started Jun 25 05:03:36 PM PDT 24
Finished Jun 25 05:03:41 PM PDT 24
Peak memory 206568 kb
Host smart-5b05cd7e-f4af-46c9-a857-e76c618b6e65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32845
55281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.3284555281
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.283384169
Short name T179
Test name
Test status
Simulation time 1356849194 ps
CPU time 3 seconds
Started Jun 25 05:03:35 PM PDT 24
Finished Jun 25 05:03:41 PM PDT 24
Peak memory 206740 kb
Host smart-4f7bd6db-76ab-462f-b9d3-fefab6e711f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28338
4169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.283384169
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.670397191
Short name T2422
Test name
Test status
Simulation time 7404508774 ps
CPU time 15.79 seconds
Started Jun 25 05:03:39 PM PDT 24
Finished Jun 25 05:03:57 PM PDT 24
Peak memory 205800 kb
Host smart-50cbceb9-87a7-4ce9-9e7e-08a4245c538a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67039
7191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.670397191
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.3052279749
Short name T1594
Test name
Test status
Simulation time 517546717 ps
CPU time 1.43 seconds
Started Jun 25 05:03:34 PM PDT 24
Finished Jun 25 05:03:38 PM PDT 24
Peak memory 206472 kb
Host smart-d0a386c0-d8e2-4091-93d2-382ab0a9945c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30522
79749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.3052279749
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.520621837
Short name T2070
Test name
Test status
Simulation time 182321603 ps
CPU time 0.82 seconds
Started Jun 25 05:03:45 PM PDT 24
Finished Jun 25 05:03:48 PM PDT 24
Peak memory 206572 kb
Host smart-b3eb43f3-6fcf-4c69-93a8-f93360eaa2fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52062
1837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.520621837
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.2822689670
Short name T316
Test name
Test status
Simulation time 43091810 ps
CPU time 0.64 seconds
Started Jun 25 05:03:44 PM PDT 24
Finished Jun 25 05:03:45 PM PDT 24
Peak memory 206552 kb
Host smart-2d7b09d4-43d3-4a8b-a49d-f82ed5633032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28226
89670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.2822689670
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.2014429006
Short name T1734
Test name
Test status
Simulation time 1008949970 ps
CPU time 2.18 seconds
Started Jun 25 05:03:45 PM PDT 24
Finished Jun 25 05:03:49 PM PDT 24
Peak memory 206804 kb
Host smart-19070bc9-bd51-47bc-a75b-5cd99e05b3db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20144
29006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.2014429006
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.2126826788
Short name T577
Test name
Test status
Simulation time 367832950 ps
CPU time 1.92 seconds
Started Jun 25 05:03:41 PM PDT 24
Finished Jun 25 05:03:44 PM PDT 24
Peak memory 206748 kb
Host smart-4d5ea024-e143-4ba2-847c-6af3a2b0bc99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21268
26788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.2126826788
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.1932961537
Short name T1970
Test name
Test status
Simulation time 222929544 ps
CPU time 0.9 seconds
Started Jun 25 05:03:46 PM PDT 24
Finished Jun 25 05:03:50 PM PDT 24
Peak memory 206576 kb
Host smart-6f388df6-6f7c-46c8-8bab-77b851841170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19329
61537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.1932961537
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.3921538090
Short name T2035
Test name
Test status
Simulation time 170115222 ps
CPU time 0.78 seconds
Started Jun 25 05:03:55 PM PDT 24
Finished Jun 25 05:03:57 PM PDT 24
Peak memory 206400 kb
Host smart-57f470a4-cac9-40cb-b105-13d911c91847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39215
38090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.3921538090
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.2024714133
Short name T1928
Test name
Test status
Simulation time 224991705 ps
CPU time 0.93 seconds
Started Jun 25 05:03:40 PM PDT 24
Finished Jun 25 05:03:43 PM PDT 24
Peak memory 206580 kb
Host smart-bfe10707-3890-4a55-a305-351c6e20d937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20247
14133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.2024714133
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.3242359844
Short name T2299
Test name
Test status
Simulation time 230188386 ps
CPU time 0.92 seconds
Started Jun 25 05:03:39 PM PDT 24
Finished Jun 25 05:03:43 PM PDT 24
Peak memory 205660 kb
Host smart-d59052d7-9657-412d-beb4-31ebb5249734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32423
59844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.3242359844
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.3534238773
Short name T1515
Test name
Test status
Simulation time 23338655074 ps
CPU time 23.93 seconds
Started Jun 25 05:03:38 PM PDT 24
Finished Jun 25 05:04:05 PM PDT 24
Peak memory 206556 kb
Host smart-fb2bedc3-3d56-4213-8490-6d98c920ab41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35342
38773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.3534238773
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.1883102952
Short name T2109
Test name
Test status
Simulation time 3298278966 ps
CPU time 3.57 seconds
Started Jun 25 05:03:36 PM PDT 24
Finished Jun 25 05:03:43 PM PDT 24
Peak memory 206636 kb
Host smart-cbbbbc79-d38d-4091-a28f-d1c720d64b2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18831
02952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.1883102952
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.155380057
Short name T1599
Test name
Test status
Simulation time 3862444264 ps
CPU time 27.18 seconds
Started Jun 25 05:03:42 PM PDT 24
Finished Jun 25 05:04:10 PM PDT 24
Peak memory 206932 kb
Host smart-d57dffb3-ed72-4906-bb22-908d25aa6173
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=155380057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.155380057
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.2731434189
Short name T1401
Test name
Test status
Simulation time 308398751 ps
CPU time 0.96 seconds
Started Jun 25 05:03:55 PM PDT 24
Finished Jun 25 05:03:58 PM PDT 24
Peak memory 206420 kb
Host smart-9e4d5e7e-637e-4c83-992f-4e440a0df20b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2731434189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.2731434189
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.891980592
Short name T1717
Test name
Test status
Simulation time 192834523 ps
CPU time 0.85 seconds
Started Jun 25 05:03:35 PM PDT 24
Finished Jun 25 05:03:38 PM PDT 24
Peak memory 206576 kb
Host smart-5e3f5cf3-d314-4f9d-95ff-5c6c9febc6f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89198
0592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.891980592
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.3046937131
Short name T2103
Test name
Test status
Simulation time 3350245091 ps
CPU time 23.32 seconds
Started Jun 25 05:03:37 PM PDT 24
Finished Jun 25 05:04:03 PM PDT 24
Peak memory 206964 kb
Host smart-b8f56213-7c4b-419b-b72a-c0d1e1e435f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30469
37131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.3046937131
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.4226571066
Short name T2252
Test name
Test status
Simulation time 13359219554 ps
CPU time 98.19 seconds
Started Jun 25 05:03:37 PM PDT 24
Finished Jun 25 05:05:19 PM PDT 24
Peak memory 206908 kb
Host smart-6e65902d-e2bd-44b2-8321-e803d50a60b2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4226571066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.4226571066
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.3777629021
Short name T777
Test name
Test status
Simulation time 149924248 ps
CPU time 0.8 seconds
Started Jun 25 05:03:47 PM PDT 24
Finished Jun 25 05:03:51 PM PDT 24
Peak memory 206508 kb
Host smart-27bf14ed-f99e-4d67-8648-1c10cd65a146
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3777629021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.3777629021
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.2298363489
Short name T923
Test name
Test status
Simulation time 146588917 ps
CPU time 0.8 seconds
Started Jun 25 05:03:35 PM PDT 24
Finished Jun 25 05:03:40 PM PDT 24
Peak memory 206520 kb
Host smart-94f94b64-403a-4813-a19e-7ca1b0289f1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22983
63489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.2298363489
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.3903039905
Short name T132
Test name
Test status
Simulation time 156842541 ps
CPU time 0.84 seconds
Started Jun 25 05:03:38 PM PDT 24
Finished Jun 25 05:03:42 PM PDT 24
Peak memory 206556 kb
Host smart-b3d646fc-0c20-4302-8b68-130055d134b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39030
39905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.3903039905
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.4141926036
Short name T1858
Test name
Test status
Simulation time 182049265 ps
CPU time 0.82 seconds
Started Jun 25 05:03:44 PM PDT 24
Finished Jun 25 05:03:47 PM PDT 24
Peak memory 206496 kb
Host smart-a974dc4c-9e6d-4988-9cc2-3c6c8cf26487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41419
26036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.4141926036
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.3437336259
Short name T1497
Test name
Test status
Simulation time 162313508 ps
CPU time 0.78 seconds
Started Jun 25 05:03:46 PM PDT 24
Finished Jun 25 05:03:49 PM PDT 24
Peak memory 206576 kb
Host smart-21704301-1ded-43a8-a89b-4ee22e9d941a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34373
36259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.3437336259
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.2375113098
Short name T760
Test name
Test status
Simulation time 175597925 ps
CPU time 0.83 seconds
Started Jun 25 05:03:44 PM PDT 24
Finished Jun 25 05:03:45 PM PDT 24
Peak memory 206500 kb
Host smart-b1c7befe-003d-462b-bff4-717717acdffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23751
13098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.2375113098
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.2118393588
Short name T2093
Test name
Test status
Simulation time 150479227 ps
CPU time 0.81 seconds
Started Jun 25 05:03:45 PM PDT 24
Finished Jun 25 05:03:47 PM PDT 24
Peak memory 206504 kb
Host smart-97b7c603-6bb3-474d-9a2d-21dca4d62665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21183
93588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.2118393588
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.4193424568
Short name T1293
Test name
Test status
Simulation time 215383232 ps
CPU time 0.94 seconds
Started Jun 25 05:03:46 PM PDT 24
Finished Jun 25 05:03:50 PM PDT 24
Peak memory 206508 kb
Host smart-913b5346-777e-4b7c-92d1-41fff5dda846
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4193424568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.4193424568
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.1856919295
Short name T1381
Test name
Test status
Simulation time 190805129 ps
CPU time 0.8 seconds
Started Jun 25 05:03:53 PM PDT 24
Finished Jun 25 05:03:55 PM PDT 24
Peak memory 206572 kb
Host smart-b96f0dad-84bf-474c-9dec-c6614705d786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18569
19295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.1856919295
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.1202559922
Short name T927
Test name
Test status
Simulation time 41652319 ps
CPU time 0.72 seconds
Started Jun 25 05:03:46 PM PDT 24
Finished Jun 25 05:03:50 PM PDT 24
Peak memory 206596 kb
Host smart-95876384-de28-4533-bb74-20deef0c4cca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12025
59922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.1202559922
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.1351079286
Short name T1210
Test name
Test status
Simulation time 23059933664 ps
CPU time 58.18 seconds
Started Jun 25 05:03:46 PM PDT 24
Finished Jun 25 05:04:47 PM PDT 24
Peak memory 206888 kb
Host smart-5d2ad40c-1616-4f61-af80-513e1b2c66ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13510
79286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.1351079286
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.3006689431
Short name T1971
Test name
Test status
Simulation time 199258759 ps
CPU time 0.94 seconds
Started Jun 25 05:03:49 PM PDT 24
Finished Jun 25 05:03:52 PM PDT 24
Peak memory 206520 kb
Host smart-b8fae521-466c-4bd8-95c6-73408c9f73f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30066
89431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.3006689431
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.2246566662
Short name T694
Test name
Test status
Simulation time 170743042 ps
CPU time 0.82 seconds
Started Jun 25 05:03:45 PM PDT 24
Finished Jun 25 05:03:48 PM PDT 24
Peak memory 206592 kb
Host smart-4062bfb3-3bd3-4f61-ad77-15e53d3372b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22465
66662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.2246566662
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.2703929825
Short name T2236
Test name
Test status
Simulation time 239221336 ps
CPU time 0.9 seconds
Started Jun 25 05:03:44 PM PDT 24
Finished Jun 25 05:03:47 PM PDT 24
Peak memory 206604 kb
Host smart-58ce2d59-1a87-440a-a9d2-a72a6adf4592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27039
29825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.2703929825
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.129398177
Short name T714
Test name
Test status
Simulation time 187546198 ps
CPU time 0.88 seconds
Started Jun 25 05:03:46 PM PDT 24
Finished Jun 25 05:03:49 PM PDT 24
Peak memory 206576 kb
Host smart-54d90abd-bfac-434b-b23c-1fdbec2f815b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12939
8177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.129398177
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.311525428
Short name T528
Test name
Test status
Simulation time 220134186 ps
CPU time 0.84 seconds
Started Jun 25 05:03:46 PM PDT 24
Finished Jun 25 05:03:49 PM PDT 24
Peak memory 206584 kb
Host smart-61e66df7-424d-42d1-9260-695f32740c8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31152
5428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.311525428
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.2607175165
Short name T1729
Test name
Test status
Simulation time 155727329 ps
CPU time 0.87 seconds
Started Jun 25 05:03:45 PM PDT 24
Finished Jun 25 05:03:48 PM PDT 24
Peak memory 206544 kb
Host smart-54a3ace2-4c81-4717-920c-c738d6f33141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26071
75165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.2607175165
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.1916606791
Short name T328
Test name
Test status
Simulation time 159787494 ps
CPU time 0.86 seconds
Started Jun 25 05:03:44 PM PDT 24
Finished Jun 25 05:03:46 PM PDT 24
Peak memory 206572 kb
Host smart-69a33df2-8550-4f1d-a8c9-701486dcb1a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19166
06791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.1916606791
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.4143660041
Short name T525
Test name
Test status
Simulation time 243535064 ps
CPU time 0.98 seconds
Started Jun 25 05:03:49 PM PDT 24
Finished Jun 25 05:03:53 PM PDT 24
Peak memory 206568 kb
Host smart-6dc369ff-8ff5-4d4d-b041-7993e138a8f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41436
60041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.4143660041
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.3903432470
Short name T2481
Test name
Test status
Simulation time 4494288245 ps
CPU time 31.64 seconds
Started Jun 25 05:03:45 PM PDT 24
Finished Jun 25 05:04:19 PM PDT 24
Peak memory 206796 kb
Host smart-7aaff4a7-83ab-4996-b3b0-2970ef131c3e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3903432470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.3903432470
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.1057333471
Short name T1356
Test name
Test status
Simulation time 170628487 ps
CPU time 0.81 seconds
Started Jun 25 05:03:49 PM PDT 24
Finished Jun 25 05:03:52 PM PDT 24
Peak memory 206500 kb
Host smart-81f4af93-5852-4ca9-9e87-d176668b5e44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10573
33471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.1057333471
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.72790097
Short name T2483
Test name
Test status
Simulation time 211605403 ps
CPU time 0.88 seconds
Started Jun 25 05:03:47 PM PDT 24
Finished Jun 25 05:03:50 PM PDT 24
Peak memory 206536 kb
Host smart-8a2b693d-eb45-412a-bebc-bf5f5db4c5aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72790
097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.72790097
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.1388390872
Short name T1286
Test name
Test status
Simulation time 4291805674 ps
CPU time 32.54 seconds
Started Jun 25 05:03:48 PM PDT 24
Finished Jun 25 05:04:23 PM PDT 24
Peak memory 206864 kb
Host smart-b18dcbc3-d3f1-439a-a855-0648c7532d33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13883
90872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.1388390872
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.3478696755
Short name T15
Test name
Test status
Simulation time 3559402609 ps
CPU time 4.61 seconds
Started Jun 25 04:56:53 PM PDT 24
Finished Jun 25 04:56:59 PM PDT 24
Peak memory 206976 kb
Host smart-5a718392-97e2-4dd4-8d3b-60e2696fdd17
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3478696755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.3478696755
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.2701362512
Short name T1990
Test name
Test status
Simulation time 13326651134 ps
CPU time 12.28 seconds
Started Jun 25 04:56:55 PM PDT 24
Finished Jun 25 04:57:09 PM PDT 24
Peak memory 206892 kb
Host smart-f779ada1-f3bc-4271-a7f7-7b5c33d768c0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2701362512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.2701362512
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.2577123384
Short name T1845
Test name
Test status
Simulation time 23376720985 ps
CPU time 24.37 seconds
Started Jun 25 04:56:53 PM PDT 24
Finished Jun 25 04:57:19 PM PDT 24
Peak memory 206948 kb
Host smart-93b5b7fd-e1fe-4feb-b081-9abd2e966bfe
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2577123384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.2577123384
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.2427995485
Short name T1322
Test name
Test status
Simulation time 177037310 ps
CPU time 0.87 seconds
Started Jun 25 04:56:55 PM PDT 24
Finished Jun 25 04:56:57 PM PDT 24
Peak memory 206476 kb
Host smart-0ccc95c4-53a2-4a0f-90b5-f3e7b51fe24a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24279
95485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.2427995485
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.1578072196
Short name T64
Test name
Test status
Simulation time 164492593 ps
CPU time 0.8 seconds
Started Jun 25 04:56:53 PM PDT 24
Finished Jun 25 04:56:56 PM PDT 24
Peak memory 206576 kb
Host smart-e0fc99a3-1493-4846-9c1b-d5f3f6e59c89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15780
72196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.1578072196
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.566732592
Short name T646
Test name
Test status
Simulation time 524544735 ps
CPU time 1.53 seconds
Started Jun 25 04:56:53 PM PDT 24
Finished Jun 25 04:56:56 PM PDT 24
Peak memory 206568 kb
Host smart-c7140f3f-ad0c-4395-8c8b-f50fd8dd954c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56673
2592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.566732592
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.2561602371
Short name T688
Test name
Test status
Simulation time 860769162 ps
CPU time 1.95 seconds
Started Jun 25 04:57:07 PM PDT 24
Finished Jun 25 04:57:10 PM PDT 24
Peak memory 206788 kb
Host smart-08290806-a376-497b-8538-2b40c2be40c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25616
02371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.2561602371
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.1369672218
Short name T2491
Test name
Test status
Simulation time 20929636841 ps
CPU time 42.64 seconds
Started Jun 25 04:56:55 PM PDT 24
Finished Jun 25 04:57:39 PM PDT 24
Peak memory 206804 kb
Host smart-35f166a0-4f73-4045-92ae-6ba0e2b3168c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13696
72218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.1369672218
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.1022141507
Short name T1582
Test name
Test status
Simulation time 333024170 ps
CPU time 1.21 seconds
Started Jun 25 04:56:54 PM PDT 24
Finished Jun 25 04:56:56 PM PDT 24
Peak memory 206492 kb
Host smart-67350792-b854-4a5b-9662-1be517c11527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10221
41507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.1022141507
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.1413578030
Short name T765
Test name
Test status
Simulation time 156926543 ps
CPU time 0.79 seconds
Started Jun 25 04:57:07 PM PDT 24
Finished Jun 25 04:57:09 PM PDT 24
Peak memory 206600 kb
Host smart-f92d3f9a-ccab-4940-a138-2bc5b2deb78f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14135
78030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.1413578030
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.3807249541
Short name T919
Test name
Test status
Simulation time 42245885 ps
CPU time 0.68 seconds
Started Jun 25 04:57:02 PM PDT 24
Finished Jun 25 04:57:03 PM PDT 24
Peak memory 206516 kb
Host smart-549d1b5d-e413-4b3a-bf55-f5856897483e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38072
49541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.3807249541
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.1934370321
Short name T1593
Test name
Test status
Simulation time 951888236 ps
CPU time 2.32 seconds
Started Jun 25 04:56:54 PM PDT 24
Finished Jun 25 04:56:58 PM PDT 24
Peak memory 206784 kb
Host smart-78811fd8-77b0-4fab-9926-793d3a3eac75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19343
70321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.1934370321
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.2693145194
Short name T1030
Test name
Test status
Simulation time 227893975 ps
CPU time 1.46 seconds
Started Jun 25 04:57:04 PM PDT 24
Finished Jun 25 04:57:07 PM PDT 24
Peak memory 206468 kb
Host smart-167fbe43-ed68-447c-bed0-6ded7919392b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26931
45194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.2693145194
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.717954171
Short name T393
Test name
Test status
Simulation time 176377043 ps
CPU time 0.84 seconds
Started Jun 25 04:57:03 PM PDT 24
Finished Jun 25 04:57:05 PM PDT 24
Peak memory 206592 kb
Host smart-16aebefe-6cd2-4aeb-8132-7b3882454431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71795
4171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.717954171
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.1689396688
Short name T782
Test name
Test status
Simulation time 155752271 ps
CPU time 0.77 seconds
Started Jun 25 04:57:03 PM PDT 24
Finished Jun 25 04:57:06 PM PDT 24
Peak memory 206596 kb
Host smart-c1d471d9-db0d-4ed7-ae9d-ac49592ab7de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16893
96688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.1689396688
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.913886361
Short name T1378
Test name
Test status
Simulation time 175323701 ps
CPU time 0.83 seconds
Started Jun 25 04:56:55 PM PDT 24
Finished Jun 25 04:56:57 PM PDT 24
Peak memory 206560 kb
Host smart-ef5d6ca6-cf0b-4a87-8bd8-79a645e3f030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91388
6361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.913886361
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.965019401
Short name T846
Test name
Test status
Simulation time 208487237 ps
CPU time 0.87 seconds
Started Jun 25 04:56:54 PM PDT 24
Finished Jun 25 04:56:57 PM PDT 24
Peak memory 206564 kb
Host smart-0e1ccf2b-3e18-4020-889a-d1be2613218d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96501
9401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.965019401
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.4033184458
Short name T828
Test name
Test status
Simulation time 23274464248 ps
CPU time 30.29 seconds
Started Jun 25 04:57:05 PM PDT 24
Finished Jun 25 04:57:36 PM PDT 24
Peak memory 206720 kb
Host smart-b1b6fa11-700c-46e3-b591-6fbac18bc403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40331
84458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.4033184458
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.1597637957
Short name T863
Test name
Test status
Simulation time 3363534642 ps
CPU time 3.8 seconds
Started Jun 25 04:56:55 PM PDT 24
Finished Jun 25 04:57:00 PM PDT 24
Peak memory 206676 kb
Host smart-f8d6b578-e8e5-4375-80de-3fc29efbfb73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15976
37957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.1597637957
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.132980207
Short name T2380
Test name
Test status
Simulation time 5953846117 ps
CPU time 173.26 seconds
Started Jun 25 04:56:53 PM PDT 24
Finished Jun 25 04:59:47 PM PDT 24
Peak memory 206892 kb
Host smart-912b2a0e-e53a-443d-be68-b1c9691030d7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=132980207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.132980207
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.2590857429
Short name T744
Test name
Test status
Simulation time 307425375 ps
CPU time 0.95 seconds
Started Jun 25 04:57:04 PM PDT 24
Finished Jun 25 04:57:06 PM PDT 24
Peak memory 206576 kb
Host smart-85896ac7-6b08-493a-8d1a-5df945f124e2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2590857429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.2590857429
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.3333562688
Short name T2324
Test name
Test status
Simulation time 197560578 ps
CPU time 0.88 seconds
Started Jun 25 04:56:55 PM PDT 24
Finished Jun 25 04:56:57 PM PDT 24
Peak memory 206576 kb
Host smart-db81f616-36f3-4787-b63e-53232e82d01e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33335
62688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.3333562688
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.1274436982
Short name T1595
Test name
Test status
Simulation time 3649502705 ps
CPU time 26.03 seconds
Started Jun 25 04:56:55 PM PDT 24
Finished Jun 25 04:57:23 PM PDT 24
Peak memory 206924 kb
Host smart-1ec4fd58-bdf6-47dc-99bd-8a75d28be2ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12744
36982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.1274436982
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.1914610080
Short name T1023
Test name
Test status
Simulation time 4913413884 ps
CPU time 33.55 seconds
Started Jun 25 04:57:05 PM PDT 24
Finished Jun 25 04:57:40 PM PDT 24
Peak memory 206916 kb
Host smart-a717bcc3-8121-4cd0-93c8-a67b16155b3c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1914610080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.1914610080
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.622089697
Short name T862
Test name
Test status
Simulation time 148406301 ps
CPU time 0.81 seconds
Started Jun 25 04:57:03 PM PDT 24
Finished Jun 25 04:57:05 PM PDT 24
Peak memory 206524 kb
Host smart-7e37f55f-b0c0-4f22-ad9c-f29f780154a7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=622089697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.622089697
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.4271500809
Short name T2039
Test name
Test status
Simulation time 175770424 ps
CPU time 0.88 seconds
Started Jun 25 04:56:56 PM PDT 24
Finished Jun 25 04:56:58 PM PDT 24
Peak memory 206500 kb
Host smart-961b9e7f-1123-45df-8377-1a85792c73c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42715
00809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.4271500809
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.1006694973
Short name T139
Test name
Test status
Simulation time 239047677 ps
CPU time 0.95 seconds
Started Jun 25 04:56:56 PM PDT 24
Finished Jun 25 04:56:58 PM PDT 24
Peak memory 206460 kb
Host smart-9e93fbaa-c3db-4dcd-80a3-3718eaa48212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10066
94973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.1006694973
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.2601151511
Short name T976
Test name
Test status
Simulation time 172709802 ps
CPU time 0.87 seconds
Started Jun 25 04:56:56 PM PDT 24
Finished Jun 25 04:56:58 PM PDT 24
Peak memory 206456 kb
Host smart-ecc5f4b1-f58f-4a67-97c1-d317faadd02a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26011
51511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.2601151511
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.3525868300
Short name T1317
Test name
Test status
Simulation time 171641007 ps
CPU time 0.81 seconds
Started Jun 25 04:56:55 PM PDT 24
Finished Jun 25 04:56:58 PM PDT 24
Peak memory 206512 kb
Host smart-24260d9a-b9a9-4b9c-934e-8a63e316db8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35258
68300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.3525868300
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.4199390633
Short name T1564
Test name
Test status
Simulation time 171705786 ps
CPU time 0.87 seconds
Started Jun 25 04:56:56 PM PDT 24
Finished Jun 25 04:56:58 PM PDT 24
Peak memory 206480 kb
Host smart-d2c40d86-fc37-4361-b37c-c76928b2bb0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41993
90633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.4199390633
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.2152813293
Short name T159
Test name
Test status
Simulation time 155222130 ps
CPU time 0.8 seconds
Started Jun 25 04:57:11 PM PDT 24
Finished Jun 25 04:57:13 PM PDT 24
Peak memory 206476 kb
Host smart-ec2de274-1a3e-424f-8adc-797e4a7b222d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21528
13293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.2152813293
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.2176649480
Short name T554
Test name
Test status
Simulation time 229005964 ps
CPU time 0.97 seconds
Started Jun 25 04:56:53 PM PDT 24
Finished Jun 25 04:56:56 PM PDT 24
Peak memory 206584 kb
Host smart-94392664-317d-44ce-9556-a231e126dd3d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2176649480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.2176649480
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.454009156
Short name T692
Test name
Test status
Simulation time 148587995 ps
CPU time 0.78 seconds
Started Jun 25 04:56:56 PM PDT 24
Finished Jun 25 04:56:58 PM PDT 24
Peak memory 206516 kb
Host smart-e9b3321c-ddcf-4ff0-83a6-07eb54e674fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45400
9156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.454009156
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.2239116111
Short name T1556
Test name
Test status
Simulation time 56105193 ps
CPU time 0.69 seconds
Started Jun 25 04:57:03 PM PDT 24
Finished Jun 25 04:57:05 PM PDT 24
Peak memory 206592 kb
Host smart-459e17f1-8742-498a-9c71-bebb7bd77eeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22391
16111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.2239116111
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.310059633
Short name T1777
Test name
Test status
Simulation time 17275575675 ps
CPU time 38.1 seconds
Started Jun 25 04:57:04 PM PDT 24
Finished Jun 25 04:57:43 PM PDT 24
Peak memory 206888 kb
Host smart-b60a862e-8691-44cf-86fd-ac2201ae76e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31005
9633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.310059633
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.1834942496
Short name T742
Test name
Test status
Simulation time 198841382 ps
CPU time 0.9 seconds
Started Jun 25 04:57:03 PM PDT 24
Finished Jun 25 04:57:05 PM PDT 24
Peak memory 206576 kb
Host smart-7e14aafd-6afe-4ff6-8b9a-f58f4067fec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18349
42496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.1834942496
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.3983627835
Short name T1028
Test name
Test status
Simulation time 235076141 ps
CPU time 0.89 seconds
Started Jun 25 04:57:04 PM PDT 24
Finished Jun 25 04:57:06 PM PDT 24
Peak memory 206448 kb
Host smart-cdce1acc-94f3-4a82-96f3-b98e1d82c4f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39836
27835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.3983627835
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.1691362646
Short name T1775
Test name
Test status
Simulation time 15700344823 ps
CPU time 101.77 seconds
Started Jun 25 04:57:03 PM PDT 24
Finished Jun 25 04:58:46 PM PDT 24
Peak memory 206852 kb
Host smart-898c9797-6c93-488d-acac-26a0934883f2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1691362646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.1691362646
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.2631391725
Short name T169
Test name
Test status
Simulation time 12557212969 ps
CPU time 121.63 seconds
Started Jun 25 04:57:03 PM PDT 24
Finished Jun 25 04:59:06 PM PDT 24
Peak memory 206828 kb
Host smart-d9221161-cecb-4da7-ab41-6745c31b4bcc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2631391725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.2631391725
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.3395639757
Short name T2338
Test name
Test status
Simulation time 7516157261 ps
CPU time 30.56 seconds
Started Jun 25 04:57:03 PM PDT 24
Finished Jun 25 04:57:35 PM PDT 24
Peak memory 206844 kb
Host smart-22ce259d-aa39-4d44-b794-417ca446c930
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3395639757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.3395639757
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.3185110493
Short name T1954
Test name
Test status
Simulation time 256725785 ps
CPU time 0.96 seconds
Started Jun 25 04:57:04 PM PDT 24
Finished Jun 25 04:57:06 PM PDT 24
Peak memory 206596 kb
Host smart-7ae56518-6c3a-4b93-b2a5-345d49495cce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31851
10493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.3185110493
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.1879337862
Short name T1882
Test name
Test status
Simulation time 227405240 ps
CPU time 0.87 seconds
Started Jun 25 04:56:55 PM PDT 24
Finished Jun 25 04:56:58 PM PDT 24
Peak memory 206468 kb
Host smart-b750fa00-07c8-4753-b0f6-552529902230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18793
37862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.1879337862
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.1879265731
Short name T1008
Test name
Test status
Simulation time 150615156 ps
CPU time 0.73 seconds
Started Jun 25 04:56:55 PM PDT 24
Finished Jun 25 04:56:57 PM PDT 24
Peak memory 206500 kb
Host smart-9323a4dd-c555-406d-b34c-87a0972e84c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18792
65731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.1879265731
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.2460130318
Short name T538
Test name
Test status
Simulation time 164057192 ps
CPU time 0.86 seconds
Started Jun 25 04:57:11 PM PDT 24
Finished Jun 25 04:57:14 PM PDT 24
Peak memory 206476 kb
Host smart-d6b40d53-0c23-410b-b72f-5ae97296f24d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24601
30318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.2460130318
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.284846630
Short name T1558
Test name
Test status
Simulation time 205339390 ps
CPU time 0.85 seconds
Started Jun 25 04:56:54 PM PDT 24
Finished Jun 25 04:56:56 PM PDT 24
Peak memory 206496 kb
Host smart-e67bc4e1-1d29-45b6-a350-ce905ba80c98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28484
6630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.284846630
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.3526847724
Short name T1939
Test name
Test status
Simulation time 239339911 ps
CPU time 0.98 seconds
Started Jun 25 04:56:59 PM PDT 24
Finished Jun 25 04:57:01 PM PDT 24
Peak memory 206512 kb
Host smart-f8bbbfb0-0cdf-457e-8abd-51b9df0940ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35268
47724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.3526847724
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.496681463
Short name T596
Test name
Test status
Simulation time 5440818652 ps
CPU time 54.51 seconds
Started Jun 25 04:56:56 PM PDT 24
Finished Jun 25 04:57:52 PM PDT 24
Peak memory 206840 kb
Host smart-12ce95bf-6bba-47fc-a5f0-89806149ce09
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=496681463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.496681463
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.2408142013
Short name T2443
Test name
Test status
Simulation time 232597602 ps
CPU time 0.93 seconds
Started Jun 25 04:57:07 PM PDT 24
Finished Jun 25 04:57:08 PM PDT 24
Peak memory 206604 kb
Host smart-e1bfa002-2766-4c7b-be93-7a0eab748cdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24081
42013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.2408142013
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.1562990144
Short name T1680
Test name
Test status
Simulation time 162907548 ps
CPU time 0.79 seconds
Started Jun 25 04:56:54 PM PDT 24
Finished Jun 25 04:56:56 PM PDT 24
Peak memory 206568 kb
Host smart-c0ec70b8-6d1b-4c52-809b-d20656e19590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15629
90144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.1562990144
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.3838837964
Short name T936
Test name
Test status
Simulation time 7361926942 ps
CPU time 54.35 seconds
Started Jun 25 04:56:54 PM PDT 24
Finished Jun 25 04:57:50 PM PDT 24
Peak memory 206932 kb
Host smart-5436f293-bb33-461d-942d-dce38c16bb6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38388
37964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.3838837964
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.848260757
Short name T1428
Test name
Test status
Simulation time 4250495223 ps
CPU time 5.25 seconds
Started Jun 25 04:57:04 PM PDT 24
Finished Jun 25 04:57:10 PM PDT 24
Peak memory 206944 kb
Host smart-a58baa12-8319-42d0-b5ee-febb6d392a5f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=848260757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.848260757
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.2376000024
Short name T796
Test name
Test status
Simulation time 13336376849 ps
CPU time 12.84 seconds
Started Jun 25 04:57:01 PM PDT 24
Finished Jun 25 04:57:14 PM PDT 24
Peak memory 206648 kb
Host smart-e90db7ee-ccae-4a49-bf42-ca89ac1b50ab
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2376000024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.2376000024
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.3219641013
Short name T2150
Test name
Test status
Simulation time 23387186523 ps
CPU time 24.76 seconds
Started Jun 25 04:57:11 PM PDT 24
Finished Jun 25 04:57:38 PM PDT 24
Peak memory 206624 kb
Host smart-c73b6c66-2150-4e47-b7e7-a91b1ac51eba
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3219641013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.3219641013
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.4006511284
Short name T1797
Test name
Test status
Simulation time 149480012 ps
CPU time 0.81 seconds
Started Jun 25 04:57:04 PM PDT 24
Finished Jun 25 04:57:07 PM PDT 24
Peak memory 206576 kb
Host smart-473b25fb-0fcd-4a18-b48c-c49a81c0d59e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40065
11284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.4006511284
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.2528197546
Short name T1611
Test name
Test status
Simulation time 157612845 ps
CPU time 0.82 seconds
Started Jun 25 04:57:03 PM PDT 24
Finished Jun 25 04:57:05 PM PDT 24
Peak memory 206504 kb
Host smart-17f6e228-3c9c-4c3d-a3ae-fb83c95a0728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25281
97546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.2528197546
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.3892535682
Short name T412
Test name
Test status
Simulation time 375905917 ps
CPU time 1.28 seconds
Started Jun 25 04:57:01 PM PDT 24
Finished Jun 25 04:57:03 PM PDT 24
Peak memory 206516 kb
Host smart-39dac828-4baf-46ed-a686-2f0baa99aa95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38925
35682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.3892535682
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.1450615374
Short name T1019
Test name
Test status
Simulation time 535454821 ps
CPU time 1.57 seconds
Started Jun 25 04:57:03 PM PDT 24
Finished Jun 25 04:57:05 PM PDT 24
Peak memory 206520 kb
Host smart-38e4b7d5-c356-415a-b1ce-f86d4981f686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14506
15374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.1450615374
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.2192733282
Short name T173
Test name
Test status
Simulation time 6137864160 ps
CPU time 11.19 seconds
Started Jun 25 04:57:11 PM PDT 24
Finished Jun 25 04:57:24 PM PDT 24
Peak memory 205700 kb
Host smart-7df186e2-7b0f-4a58-8f08-45cb04b1e4e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21927
33282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.2192733282
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.3214220234
Short name T2409
Test name
Test status
Simulation time 483447061 ps
CPU time 1.39 seconds
Started Jun 25 04:57:10 PM PDT 24
Finished Jun 25 04:57:12 PM PDT 24
Peak memory 206496 kb
Host smart-a758e70d-a545-4f46-99ae-5aec5af286d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32142
20234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.3214220234
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.850443022
Short name T394
Test name
Test status
Simulation time 192527187 ps
CPU time 0.77 seconds
Started Jun 25 04:57:10 PM PDT 24
Finished Jun 25 04:57:12 PM PDT 24
Peak memory 206576 kb
Host smart-659a89cd-61f0-4588-8d39-c6f83c7961a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85044
3022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.850443022
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.103787033
Short name T1808
Test name
Test status
Simulation time 40594386 ps
CPU time 0.63 seconds
Started Jun 25 04:57:11 PM PDT 24
Finished Jun 25 04:57:13 PM PDT 24
Peak memory 206600 kb
Host smart-5555a517-ea92-4e0f-958e-b477014fabb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10378
7033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.103787033
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.4266594970
Short name T335
Test name
Test status
Simulation time 949185581 ps
CPU time 2.42 seconds
Started Jun 25 04:57:12 PM PDT 24
Finished Jun 25 04:57:17 PM PDT 24
Peak memory 206760 kb
Host smart-6c920d13-faf0-46c3-9bfa-17dafd2bf91b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42665
94970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.4266594970
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.498909978
Short name T1085
Test name
Test status
Simulation time 171458006 ps
CPU time 1.65 seconds
Started Jun 25 04:57:11 PM PDT 24
Finished Jun 25 04:57:15 PM PDT 24
Peak memory 206832 kb
Host smart-394a5d05-de4e-426e-8003-9b2ec6360ac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49890
9978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.498909978
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.1754467335
Short name T343
Test name
Test status
Simulation time 186465331 ps
CPU time 0.82 seconds
Started Jun 25 04:57:20 PM PDT 24
Finished Jun 25 04:57:23 PM PDT 24
Peak memory 206580 kb
Host smart-b465fde9-0c48-487c-8c28-6785e4af40e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17544
67335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.1754467335
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.3369143874
Short name T751
Test name
Test status
Simulation time 206389650 ps
CPU time 0.79 seconds
Started Jun 25 04:57:22 PM PDT 24
Finished Jun 25 04:57:25 PM PDT 24
Peak memory 206568 kb
Host smart-d78fe0e8-b1db-44ce-b832-26498a9f29b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33691
43874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.3369143874
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.1910602945
Short name T1202
Test name
Test status
Simulation time 216347005 ps
CPU time 0.91 seconds
Started Jun 25 04:57:14 PM PDT 24
Finished Jun 25 04:57:16 PM PDT 24
Peak memory 206572 kb
Host smart-d4716a12-6cc1-486f-b997-86439d8452e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19106
02945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.1910602945
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_invalid_sync.3023862107
Short name T76
Test name
Test status
Simulation time 10432205690 ps
CPU time 72.08 seconds
Started Jun 25 04:57:12 PM PDT 24
Finished Jun 25 04:58:26 PM PDT 24
Peak memory 206956 kb
Host smart-bccfbcc6-c52b-4578-b297-b07b999b5d6e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3023862107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.3023862107
Directory /workspace/6.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.2699489396
Short name T1259
Test name
Test status
Simulation time 202280415 ps
CPU time 0.92 seconds
Started Jun 25 04:57:09 PM PDT 24
Finished Jun 25 04:57:11 PM PDT 24
Peak memory 206576 kb
Host smart-894b7b5e-cac4-4557-b3a4-82b1c422aa53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26994
89396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.2699489396
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.2614425224
Short name T373
Test name
Test status
Simulation time 23307892008 ps
CPU time 23.57 seconds
Started Jun 25 04:57:11 PM PDT 24
Finished Jun 25 04:57:36 PM PDT 24
Peak memory 205276 kb
Host smart-5766fad1-5749-4d9c-9520-c64c96120f42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26144
25224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.2614425224
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.627412420
Short name T1940
Test name
Test status
Simulation time 3323066801 ps
CPU time 4.25 seconds
Started Jun 25 04:57:12 PM PDT 24
Finished Jun 25 04:57:19 PM PDT 24
Peak memory 206692 kb
Host smart-a0da50b4-c36f-4c87-81ff-c7ef38ae3a37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62741
2420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.627412420
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.3734364451
Short name T2138
Test name
Test status
Simulation time 10526873223 ps
CPU time 78.31 seconds
Started Jun 25 04:57:13 PM PDT 24
Finished Jun 25 04:58:33 PM PDT 24
Peak memory 206892 kb
Host smart-e86045aa-a9db-4a8e-acf6-eab2bb4a36a9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3734364451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.3734364451
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.4051490383
Short name T1811
Test name
Test status
Simulation time 236255567 ps
CPU time 0.88 seconds
Started Jun 25 04:57:20 PM PDT 24
Finished Jun 25 04:57:23 PM PDT 24
Peak memory 206604 kb
Host smart-c1e49011-a89e-4909-932d-2ab14d1c9173
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4051490383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.4051490383
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.3776128365
Short name T1407
Test name
Test status
Simulation time 205078164 ps
CPU time 0.9 seconds
Started Jun 25 04:57:11 PM PDT 24
Finished Jun 25 04:57:14 PM PDT 24
Peak memory 206508 kb
Host smart-7e0f752c-e904-4fde-bf3e-65656d1a6570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37761
28365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.3776128365
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.4223831082
Short name T2257
Test name
Test status
Simulation time 10215350667 ps
CPU time 284.27 seconds
Started Jun 25 04:57:12 PM PDT 24
Finished Jun 25 05:01:58 PM PDT 24
Peak memory 206852 kb
Host smart-5724a08e-ce0c-45e8-b2f2-d9dceb8b9e91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42238
31082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.4223831082
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.57737840
Short name T1412
Test name
Test status
Simulation time 14944333658 ps
CPU time 423.18 seconds
Started Jun 25 04:57:11 PM PDT 24
Finished Jun 25 05:04:16 PM PDT 24
Peak memory 206888 kb
Host smart-d7ace2c3-9f81-4aae-9b38-5d18a11caaff
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=57737840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.57737840
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.1617731272
Short name T1168
Test name
Test status
Simulation time 159812632 ps
CPU time 0.81 seconds
Started Jun 25 04:57:20 PM PDT 24
Finished Jun 25 04:57:22 PM PDT 24
Peak memory 206588 kb
Host smart-74df9c53-a9c2-44a9-81b7-a80dfb75c45b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1617731272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.1617731272
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.3070834444
Short name T1491
Test name
Test status
Simulation time 151387397 ps
CPU time 0.78 seconds
Started Jun 25 04:57:11 PM PDT 24
Finished Jun 25 04:57:14 PM PDT 24
Peak memory 206580 kb
Host smart-9a15fa2c-3ee3-4115-967a-4964295bcf79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30708
34444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.3070834444
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.966554115
Short name T145
Test name
Test status
Simulation time 201570003 ps
CPU time 0.9 seconds
Started Jun 25 04:57:11 PM PDT 24
Finished Jun 25 04:57:14 PM PDT 24
Peak memory 206600 kb
Host smart-6ccf12ce-c8a7-4ef3-aa4e-5ff866739cd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96655
4115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.966554115
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.1055888472
Short name T1781
Test name
Test status
Simulation time 214013284 ps
CPU time 0.85 seconds
Started Jun 25 04:57:09 PM PDT 24
Finished Jun 25 04:57:11 PM PDT 24
Peak memory 206580 kb
Host smart-80b40bd4-83de-4a9a-94a2-793cd59fcb95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10558
88472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.1055888472
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.3655428978
Short name T2345
Test name
Test status
Simulation time 166155891 ps
CPU time 0.77 seconds
Started Jun 25 04:57:09 PM PDT 24
Finished Jun 25 04:57:11 PM PDT 24
Peak memory 206564 kb
Host smart-57ab0bf0-88b9-43a3-824e-3de54ad18f2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36554
28978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.3655428978
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.2913297719
Short name T2120
Test name
Test status
Simulation time 213499947 ps
CPU time 0.99 seconds
Started Jun 25 04:57:13 PM PDT 24
Finished Jun 25 04:57:16 PM PDT 24
Peak memory 206576 kb
Host smart-54d3dcad-9435-4dff-a8f0-84bc5c7d0409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29132
97719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.2913297719
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.2203553337
Short name T492
Test name
Test status
Simulation time 161314756 ps
CPU time 0.83 seconds
Started Jun 25 04:57:20 PM PDT 24
Finished Jun 25 04:57:23 PM PDT 24
Peak memory 206472 kb
Host smart-9724da59-78e6-4b77-9ca8-fdb0094b7258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22035
53337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.2203553337
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.2242533738
Short name T2128
Test name
Test status
Simulation time 250052053 ps
CPU time 0.94 seconds
Started Jun 25 04:57:11 PM PDT 24
Finished Jun 25 04:57:14 PM PDT 24
Peak memory 206532 kb
Host smart-f3c3e871-b297-476e-8f88-981af3bd7d5a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2242533738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.2242533738
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.1514122130
Short name T2333
Test name
Test status
Simulation time 149528223 ps
CPU time 0.77 seconds
Started Jun 25 04:57:10 PM PDT 24
Finished Jun 25 04:57:12 PM PDT 24
Peak memory 206544 kb
Host smart-b127a0d3-2d52-4d7a-92bf-bd1f271dbcf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15141
22130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.1514122130
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.1657850964
Short name T2201
Test name
Test status
Simulation time 30873501 ps
CPU time 0.65 seconds
Started Jun 25 04:57:23 PM PDT 24
Finished Jun 25 04:57:25 PM PDT 24
Peak memory 206568 kb
Host smart-11929a83-0cc8-4670-95e5-c86185b70273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16578
50964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.1657850964
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.1651436020
Short name T1475
Test name
Test status
Simulation time 12239981960 ps
CPU time 26.68 seconds
Started Jun 25 04:57:11 PM PDT 24
Finished Jun 25 04:57:40 PM PDT 24
Peak memory 206848 kb
Host smart-bef51a25-f096-4ddf-bb31-958561b7cc9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16514
36020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.1651436020
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.3906303394
Short name T2388
Test name
Test status
Simulation time 157381063 ps
CPU time 0.8 seconds
Started Jun 25 04:57:11 PM PDT 24
Finished Jun 25 04:57:14 PM PDT 24
Peak memory 206752 kb
Host smart-4e929e1c-c548-425a-8de6-d029747ba11a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39063
03394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.3906303394
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.3196373016
Short name T1044
Test name
Test status
Simulation time 188907535 ps
CPU time 0.88 seconds
Started Jun 25 04:57:12 PM PDT 24
Finished Jun 25 04:57:15 PM PDT 24
Peak memory 206472 kb
Host smart-491b03e6-3ae6-4c15-90c4-8980fab49542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31963
73016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.3196373016
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.4936531
Short name T2493
Test name
Test status
Simulation time 10494936983 ps
CPU time 287.72 seconds
Started Jun 25 04:57:11 PM PDT 24
Finished Jun 25 05:02:02 PM PDT 24
Peak memory 206960 kb
Host smart-a9033155-bd0a-47fe-98f2-23b15925094b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4936531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.4936531
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.3789812043
Short name T681
Test name
Test status
Simulation time 25300160237 ps
CPU time 164.36 seconds
Started Jun 25 04:57:12 PM PDT 24
Finished Jun 25 04:59:59 PM PDT 24
Peak memory 206808 kb
Host smart-61a332ad-beb7-4aec-96ff-fb7c04462a25
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3789812043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.3789812043
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.465128659
Short name T2237
Test name
Test status
Simulation time 176897747 ps
CPU time 0.85 seconds
Started Jun 25 04:57:22 PM PDT 24
Finished Jun 25 04:57:25 PM PDT 24
Peak memory 206512 kb
Host smart-6cc13e86-673f-4ca6-81ee-7c2d0a9a7be8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46512
8659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.465128659
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.4269438750
Short name T544
Test name
Test status
Simulation time 157277113 ps
CPU time 0.86 seconds
Started Jun 25 04:57:12 PM PDT 24
Finished Jun 25 04:57:15 PM PDT 24
Peak memory 206572 kb
Host smart-f5d10f7a-4ac8-45fc-bf64-b2de0bc6da42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42694
38750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.4269438750
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.595527559
Short name T1903
Test name
Test status
Simulation time 139409175 ps
CPU time 0.79 seconds
Started Jun 25 04:57:10 PM PDT 24
Finished Jun 25 04:57:12 PM PDT 24
Peak memory 206512 kb
Host smart-60c82aa3-49bf-4732-bd61-7f60125da0ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59552
7559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.595527559
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.4171659084
Short name T2185
Test name
Test status
Simulation time 167278415 ps
CPU time 0.83 seconds
Started Jun 25 04:57:18 PM PDT 24
Finished Jun 25 04:57:20 PM PDT 24
Peak memory 206496 kb
Host smart-a973b04f-ed2f-4c9f-b78a-570e8602ae4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41716
59084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.4171659084
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.2597523596
Short name T1671
Test name
Test status
Simulation time 158798506 ps
CPU time 0.83 seconds
Started Jun 25 04:57:27 PM PDT 24
Finished Jun 25 04:57:28 PM PDT 24
Peak memory 206556 kb
Host smart-3026c8e7-7129-4830-a573-39cbe5bc1f21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25975
23596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.2597523596
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.3829243850
Short name T600
Test name
Test status
Simulation time 241443363 ps
CPU time 0.9 seconds
Started Jun 25 04:57:12 PM PDT 24
Finished Jun 25 04:57:15 PM PDT 24
Peak memory 206604 kb
Host smart-dbe0689d-70d5-4625-8a8c-d340c846dbeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38292
43850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.3829243850
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.1546994314
Short name T974
Test name
Test status
Simulation time 5510404586 ps
CPU time 41.3 seconds
Started Jun 25 04:57:12 PM PDT 24
Finished Jun 25 04:57:55 PM PDT 24
Peak memory 206896 kb
Host smart-8316cb6f-9cbd-4412-ba5e-a58556ad7d55
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1546994314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.1546994314
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.765639751
Short name T1152
Test name
Test status
Simulation time 198514599 ps
CPU time 0.83 seconds
Started Jun 25 04:57:19 PM PDT 24
Finished Jun 25 04:57:21 PM PDT 24
Peak memory 206516 kb
Host smart-50ade4a5-21d9-4412-be3c-758abe5185b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76563
9751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.765639751
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.3786077514
Short name T716
Test name
Test status
Simulation time 210860541 ps
CPU time 0.83 seconds
Started Jun 25 04:57:11 PM PDT 24
Finished Jun 25 04:57:14 PM PDT 24
Peak memory 206572 kb
Host smart-c592ca7b-bdb3-40d5-b6f9-ab2f31beb34d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37860
77514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.3786077514
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.1164739235
Short name T2075
Test name
Test status
Simulation time 14503161829 ps
CPU time 105.14 seconds
Started Jun 25 04:57:11 PM PDT 24
Finished Jun 25 04:58:57 PM PDT 24
Peak memory 206932 kb
Host smart-b3d0ff39-4689-4fc7-994a-85df798589f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11647
39235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.1164739235
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.983259412
Short name T2112
Test name
Test status
Simulation time 3522482809 ps
CPU time 4.42 seconds
Started Jun 25 04:57:21 PM PDT 24
Finished Jun 25 04:57:28 PM PDT 24
Peak memory 206848 kb
Host smart-c4626940-07a7-445a-8bcd-8d2aebafab16
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=983259412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.983259412
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.101806482
Short name T2016
Test name
Test status
Simulation time 13371085662 ps
CPU time 12.48 seconds
Started Jun 25 04:57:21 PM PDT 24
Finished Jun 25 04:57:36 PM PDT 24
Peak memory 206628 kb
Host smart-f047e038-6afc-4fdf-9ea8-f9ced875c7b6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=101806482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.101806482
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.2326577695
Short name T2290
Test name
Test status
Simulation time 23376225977 ps
CPU time 24.57 seconds
Started Jun 25 04:57:21 PM PDT 24
Finished Jun 25 04:57:48 PM PDT 24
Peak memory 206736 kb
Host smart-f8dbd16f-29ec-4587-a6b3-aacac3e1f5e9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2326577695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.2326577695
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.1934515217
Short name T1537
Test name
Test status
Simulation time 147299567 ps
CPU time 0.85 seconds
Started Jun 25 04:57:20 PM PDT 24
Finished Jun 25 04:57:22 PM PDT 24
Peak memory 206596 kb
Host smart-174235b1-4aaa-4d4a-bc7d-2c662814157e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19345
15217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.1934515217
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.763883647
Short name T2416
Test name
Test status
Simulation time 146027914 ps
CPU time 0.73 seconds
Started Jun 25 04:57:20 PM PDT 24
Finished Jun 25 04:57:22 PM PDT 24
Peak memory 206592 kb
Host smart-2c8b928b-49ee-47e7-ba04-85831537b605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76388
3647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.763883647
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.3650202909
Short name T1886
Test name
Test status
Simulation time 996625206 ps
CPU time 2.22 seconds
Started Jun 25 04:57:21 PM PDT 24
Finished Jun 25 04:57:26 PM PDT 24
Peak memory 206920 kb
Host smart-81c8cb19-77a6-4715-8232-75c3a8db9e08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36502
02909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.3650202909
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.2827153659
Short name T98
Test name
Test status
Simulation time 12381973237 ps
CPU time 26.8 seconds
Started Jun 25 04:57:20 PM PDT 24
Finished Jun 25 04:57:49 PM PDT 24
Peak memory 206848 kb
Host smart-f0cbb61f-b780-4e93-bc0f-36db5a8a96bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28271
53659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.2827153659
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.298772946
Short name T787
Test name
Test status
Simulation time 497305645 ps
CPU time 1.47 seconds
Started Jun 25 04:57:23 PM PDT 24
Finished Jun 25 04:57:26 PM PDT 24
Peak memory 206508 kb
Host smart-457a4f7e-803a-4518-924b-e92b5553a4bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29877
2946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.298772946
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.3563871948
Short name T503
Test name
Test status
Simulation time 133250806 ps
CPU time 0.8 seconds
Started Jun 25 04:57:20 PM PDT 24
Finished Jun 25 04:57:23 PM PDT 24
Peak memory 206580 kb
Host smart-7e90a14b-6f98-442e-960a-ff194bb3022c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35638
71948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.3563871948
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.3219725038
Short name T233
Test name
Test status
Simulation time 33014415 ps
CPU time 0.68 seconds
Started Jun 25 04:57:21 PM PDT 24
Finished Jun 25 04:57:23 PM PDT 24
Peak memory 206552 kb
Host smart-947efe2a-af54-4da8-ae4c-5dc47f32c2ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32197
25038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.3219725038
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.2385151631
Short name T1146
Test name
Test status
Simulation time 892535152 ps
CPU time 1.99 seconds
Started Jun 25 04:57:20 PM PDT 24
Finished Jun 25 04:57:24 PM PDT 24
Peak memory 206744 kb
Host smart-fd0f1ecc-c94c-4ec5-94e6-49b54ba5449a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23851
51631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.2385151631
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.2156236328
Short name T2227
Test name
Test status
Simulation time 179488681 ps
CPU time 1.34 seconds
Started Jun 25 04:57:20 PM PDT 24
Finished Jun 25 04:57:24 PM PDT 24
Peak memory 206828 kb
Host smart-4408e988-7e7b-4199-9a4b-25728a2ebeaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21562
36328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.2156236328
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.2295481088
Short name T2455
Test name
Test status
Simulation time 224590590 ps
CPU time 0.9 seconds
Started Jun 25 04:57:29 PM PDT 24
Finished Jun 25 04:57:32 PM PDT 24
Peak memory 206604 kb
Host smart-66b5b167-8e7d-4b30-a19c-5363619d0f10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22954
81088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.2295481088
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.829997269
Short name T1753
Test name
Test status
Simulation time 148403261 ps
CPU time 0.77 seconds
Started Jun 25 04:57:32 PM PDT 24
Finished Jun 25 04:57:35 PM PDT 24
Peak memory 206500 kb
Host smart-492f0df9-9166-475c-b909-8aa513cc222a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82999
7269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.829997269
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.820265209
Short name T617
Test name
Test status
Simulation time 295122520 ps
CPU time 0.99 seconds
Started Jun 25 04:57:23 PM PDT 24
Finished Jun 25 04:57:26 PM PDT 24
Peak memory 206596 kb
Host smart-3f216309-fd35-4f94-ac1e-61344a0aceb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82026
5209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.820265209
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.3242914475
Short name T1170
Test name
Test status
Simulation time 231301783 ps
CPU time 0.86 seconds
Started Jun 25 04:57:22 PM PDT 24
Finished Jun 25 04:57:25 PM PDT 24
Peak memory 206572 kb
Host smart-1fb6f944-bcd8-4caa-8a54-43f1de42a29c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32429
14475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.3242914475
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.1484557063
Short name T1433
Test name
Test status
Simulation time 23317983785 ps
CPU time 21.96 seconds
Started Jun 25 04:57:24 PM PDT 24
Finished Jun 25 04:57:47 PM PDT 24
Peak memory 206716 kb
Host smart-e73de9ae-0cb8-4bff-85e8-2a8cb38d492e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14845
57063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.1484557063
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.759710044
Short name T1513
Test name
Test status
Simulation time 3310742652 ps
CPU time 3.68 seconds
Started Jun 25 04:57:27 PM PDT 24
Finished Jun 25 04:57:31 PM PDT 24
Peak memory 206692 kb
Host smart-061af167-dd02-4d23-be72-bf87e4100a0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75971
0044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.759710044
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.4166946641
Short name T2151
Test name
Test status
Simulation time 10300800567 ps
CPU time 292.47 seconds
Started Jun 25 04:57:22 PM PDT 24
Finished Jun 25 05:02:17 PM PDT 24
Peak memory 206948 kb
Host smart-e0a24c9e-883a-4c16-a8b1-997e03a6a8e2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4166946641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.4166946641
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.2714481486
Short name T1984
Test name
Test status
Simulation time 265332246 ps
CPU time 0.89 seconds
Started Jun 25 04:57:30 PM PDT 24
Finished Jun 25 04:57:33 PM PDT 24
Peak memory 206512 kb
Host smart-c76fffcf-4dee-480c-9ba7-2d38a22c2c33
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2714481486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.2714481486
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.2996618921
Short name T2441
Test name
Test status
Simulation time 193290298 ps
CPU time 0.83 seconds
Started Jun 25 04:57:21 PM PDT 24
Finished Jun 25 04:57:24 PM PDT 24
Peak memory 206476 kb
Host smart-79f1d985-247d-4df6-afc7-e91fba3de8a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29966
18921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.2996618921
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.1527893335
Short name T476
Test name
Test status
Simulation time 7148043190 ps
CPU time 66.95 seconds
Started Jun 25 04:57:19 PM PDT 24
Finished Jun 25 04:58:27 PM PDT 24
Peak memory 206864 kb
Host smart-0c3d9489-e4cc-4dd7-bc15-8daad73b134e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15278
93335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.1527893335
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.2524048519
Short name T858
Test name
Test status
Simulation time 6362671035 ps
CPU time 59.84 seconds
Started Jun 25 04:57:21 PM PDT 24
Finished Jun 25 04:58:23 PM PDT 24
Peak memory 206964 kb
Host smart-9489a890-d916-4681-a739-88039d1e99fd
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2524048519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.2524048519
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.1440162793
Short name T210
Test name
Test status
Simulation time 154476073 ps
CPU time 0.81 seconds
Started Jun 25 04:57:31 PM PDT 24
Finished Jun 25 04:57:33 PM PDT 24
Peak memory 206604 kb
Host smart-92383a18-be0f-45cc-ae97-3fb9ce03ec32
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1440162793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.1440162793
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.2351262247
Short name T997
Test name
Test status
Simulation time 140051255 ps
CPU time 0.81 seconds
Started Jun 25 04:57:27 PM PDT 24
Finished Jun 25 04:57:28 PM PDT 24
Peak memory 206188 kb
Host smart-fce42a2c-1903-4c8e-94bf-adc51c89fdb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23512
62247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.2351262247
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.1703898388
Short name T142
Test name
Test status
Simulation time 190602983 ps
CPU time 0.86 seconds
Started Jun 25 04:57:21 PM PDT 24
Finished Jun 25 04:57:24 PM PDT 24
Peak memory 206596 kb
Host smart-b6c23873-4d07-496a-9203-adfc1f3ac059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17038
98388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.1703898388
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.3012651912
Short name T1835
Test name
Test status
Simulation time 164889168 ps
CPU time 0.8 seconds
Started Jun 25 04:57:21 PM PDT 24
Finished Jun 25 04:57:24 PM PDT 24
Peak memory 206508 kb
Host smart-9dfde3a6-32a0-410e-bd0d-a2f58ad4ca0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30126
51912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.3012651912
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.1922483524
Short name T683
Test name
Test status
Simulation time 159181428 ps
CPU time 0.81 seconds
Started Jun 25 04:57:21 PM PDT 24
Finished Jun 25 04:57:24 PM PDT 24
Peak memory 206512 kb
Host smart-efdfd88f-32a0-4549-90e6-1c19d1e1614c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19224
83524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.1922483524
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.1699870638
Short name T674
Test name
Test status
Simulation time 181697955 ps
CPU time 0.8 seconds
Started Jun 25 04:57:25 PM PDT 24
Finished Jun 25 04:57:27 PM PDT 24
Peak memory 206480 kb
Host smart-e6020a15-df4b-40f8-a1fa-f90bdda07abc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16998
70638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.1699870638
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.1531728259
Short name T826
Test name
Test status
Simulation time 174766402 ps
CPU time 0.82 seconds
Started Jun 25 04:57:31 PM PDT 24
Finished Jun 25 04:57:33 PM PDT 24
Peak memory 206596 kb
Host smart-a8721f1e-de08-4d5f-bf52-abf7a6ffae08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15317
28259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.1531728259
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.1400160536
Short name T747
Test name
Test status
Simulation time 230170745 ps
CPU time 0.89 seconds
Started Jun 25 04:57:20 PM PDT 24
Finished Jun 25 04:57:22 PM PDT 24
Peak memory 206580 kb
Host smart-1263709b-3054-4477-b12b-ada245eaa3f2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1400160536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.1400160536
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.1991601879
Short name T1953
Test name
Test status
Simulation time 178578391 ps
CPU time 0.84 seconds
Started Jun 25 04:57:21 PM PDT 24
Finished Jun 25 04:57:25 PM PDT 24
Peak memory 206468 kb
Host smart-faa88ee8-442d-4973-80d7-da48e5d13c0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19916
01879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.1991601879
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.1057030255
Short name T1560
Test name
Test status
Simulation time 55477581 ps
CPU time 0.67 seconds
Started Jun 25 04:57:31 PM PDT 24
Finished Jun 25 04:57:33 PM PDT 24
Peak memory 206568 kb
Host smart-81fb34bc-66b9-4c1c-98e7-1fa2a06b1f15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10570
30255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.1057030255
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.2875167242
Short name T2056
Test name
Test status
Simulation time 6843916702 ps
CPU time 15.58 seconds
Started Jun 25 04:57:20 PM PDT 24
Finished Jun 25 04:57:36 PM PDT 24
Peak memory 206824 kb
Host smart-2d49f250-66e6-4172-8a10-fd6b5b882c1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28751
67242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.2875167242
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.2530265329
Short name T949
Test name
Test status
Simulation time 233167466 ps
CPU time 0.91 seconds
Started Jun 25 04:57:21 PM PDT 24
Finished Jun 25 04:57:24 PM PDT 24
Peak memory 206576 kb
Host smart-7a583260-ed07-4c71-93f4-7bfa73db57da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25302
65329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.2530265329
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.1537044211
Short name T1035
Test name
Test status
Simulation time 203305904 ps
CPU time 0.87 seconds
Started Jun 25 04:57:21 PM PDT 24
Finished Jun 25 04:57:24 PM PDT 24
Peak memory 206500 kb
Host smart-a3a1f4bb-d759-43f5-adbc-bb750cf6555d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15370
44211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.1537044211
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.2893565944
Short name T156
Test name
Test status
Simulation time 11674629803 ps
CPU time 55.07 seconds
Started Jun 25 04:57:21 PM PDT 24
Finished Jun 25 04:58:18 PM PDT 24
Peak memory 206976 kb
Host smart-4cb409ce-e59d-448d-8057-418dbe683679
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2893565944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.2893565944
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.4008813553
Short name T1683
Test name
Test status
Simulation time 24200393327 ps
CPU time 191.87 seconds
Started Jun 25 04:57:22 PM PDT 24
Finished Jun 25 05:00:36 PM PDT 24
Peak memory 206888 kb
Host smart-a3c72ad2-4079-4787-8515-7adb2ba228ce
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4008813553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.4008813553
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.2039804549
Short name T757
Test name
Test status
Simulation time 216626382 ps
CPU time 0.93 seconds
Started Jun 25 04:57:29 PM PDT 24
Finished Jun 25 04:57:31 PM PDT 24
Peak memory 206544 kb
Host smart-d78ba0a6-8290-4cbc-888a-a8ad0ae76883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20398
04549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.2039804549
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.1290558476
Short name T471
Test name
Test status
Simulation time 139292171 ps
CPU time 0.85 seconds
Started Jun 25 04:57:22 PM PDT 24
Finished Jun 25 04:57:25 PM PDT 24
Peak memory 206568 kb
Host smart-38ef8cf2-80ed-45b4-b8b9-135d50b7aabf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12905
58476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.1290558476
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.1389961564
Short name T1171
Test name
Test status
Simulation time 186496850 ps
CPU time 0.84 seconds
Started Jun 25 04:57:27 PM PDT 24
Finished Jun 25 04:57:28 PM PDT 24
Peak memory 206276 kb
Host smart-bd7c7689-5691-436f-84ae-8aea80e926b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13899
61564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.1389961564
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.823979959
Short name T32
Test name
Test status
Simulation time 193828032 ps
CPU time 0.82 seconds
Started Jun 25 04:57:32 PM PDT 24
Finished Jun 25 04:57:34 PM PDT 24
Peak memory 206572 kb
Host smart-0496b2ac-2f80-4eb7-aa34-e69bc0385952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82397
9959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.823979959
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.3403615693
Short name T2446
Test name
Test status
Simulation time 157189720 ps
CPU time 0.85 seconds
Started Jun 25 04:57:21 PM PDT 24
Finished Jun 25 04:57:24 PM PDT 24
Peak memory 206512 kb
Host smart-35542bee-ceaf-4f3d-9d1a-ea59c0e12361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34036
15693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.3403615693
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.2396539853
Short name T1579
Test name
Test status
Simulation time 238558770 ps
CPU time 0.94 seconds
Started Jun 25 04:57:22 PM PDT 24
Finished Jun 25 04:57:25 PM PDT 24
Peak memory 206584 kb
Host smart-d86043db-a5cd-499f-ad24-ff6b99f26cb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23965
39853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.2396539853
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.2476503787
Short name T2153
Test name
Test status
Simulation time 4707936808 ps
CPU time 44.37 seconds
Started Jun 25 04:57:25 PM PDT 24
Finished Jun 25 04:58:10 PM PDT 24
Peak memory 206756 kb
Host smart-3b91326f-e25d-46c6-bcd7-0a394d1ec80b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2476503787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.2476503787
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.1330201383
Short name T773
Test name
Test status
Simulation time 174478670 ps
CPU time 0.84 seconds
Started Jun 25 04:57:30 PM PDT 24
Finished Jun 25 04:57:32 PM PDT 24
Peak memory 206500 kb
Host smart-086daa17-5c69-4846-954c-11eb4957aa16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13302
01383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.1330201383
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.3975372144
Short name T2411
Test name
Test status
Simulation time 192554339 ps
CPU time 0.82 seconds
Started Jun 25 04:57:23 PM PDT 24
Finished Jun 25 04:57:25 PM PDT 24
Peak memory 206572 kb
Host smart-66a733b3-5c11-42f0-af18-2abdef32fbfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39753
72144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.3975372144
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.1189307610
Short name T2178
Test name
Test status
Simulation time 2856006524 ps
CPU time 74.84 seconds
Started Jun 25 04:57:21 PM PDT 24
Finished Jun 25 04:58:39 PM PDT 24
Peak memory 206836 kb
Host smart-2bd43ad1-7f55-4eb9-90e7-9ce07a43f3cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11893
07610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.1189307610
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.1079385519
Short name T661
Test name
Test status
Simulation time 3899342033 ps
CPU time 4.7 seconds
Started Jun 25 04:57:30 PM PDT 24
Finished Jun 25 04:57:37 PM PDT 24
Peak memory 206968 kb
Host smart-7eec8a1e-0d49-45b5-a6bb-8a9e6f77dc9a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1079385519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.1079385519
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.763029752
Short name T819
Test name
Test status
Simulation time 13372936604 ps
CPU time 14.55 seconds
Started Jun 25 04:57:29 PM PDT 24
Finished Jun 25 04:57:45 PM PDT 24
Peak memory 206656 kb
Host smart-b6596c22-213d-4f27-92a1-a9567a6dd4af
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=763029752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.763029752
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.3983081619
Short name T521
Test name
Test status
Simulation time 23394669586 ps
CPU time 22.94 seconds
Started Jun 25 04:57:32 PM PDT 24
Finished Jun 25 04:57:57 PM PDT 24
Peak memory 206848 kb
Host smart-3eec1cab-5d80-4ea7-a3a1-6f2789c55105
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3983081619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.3983081619
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.2193650131
Short name T1009
Test name
Test status
Simulation time 178562590 ps
CPU time 0.84 seconds
Started Jun 25 04:57:32 PM PDT 24
Finished Jun 25 04:57:34 PM PDT 24
Peak memory 206596 kb
Host smart-902f8cfb-467d-44f3-b58d-3165a5fb7890
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21936
50131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.2193650131
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.1723002131
Short name T575
Test name
Test status
Simulation time 146404743 ps
CPU time 0.8 seconds
Started Jun 25 04:57:32 PM PDT 24
Finished Jun 25 04:57:34 PM PDT 24
Peak memory 206580 kb
Host smart-d6151eac-e5c4-45c1-a6e2-623b0b88a25d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17230
02131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.1723002131
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.3301611229
Short name T1197
Test name
Test status
Simulation time 511981536 ps
CPU time 1.55 seconds
Started Jun 25 04:57:32 PM PDT 24
Finished Jun 25 04:57:36 PM PDT 24
Peak memory 206808 kb
Host smart-5f123f49-b27e-4f01-8ca7-8f992fa285b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33016
11229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.3301611229
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.678234334
Short name T1499
Test name
Test status
Simulation time 368917555 ps
CPU time 1.12 seconds
Started Jun 25 04:57:33 PM PDT 24
Finished Jun 25 04:57:35 PM PDT 24
Peak memory 206532 kb
Host smart-37431fc5-780f-4507-92b2-d1f2ae60e625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67823
4334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.678234334
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.1870427269
Short name T1533
Test name
Test status
Simulation time 12125051748 ps
CPU time 23.91 seconds
Started Jun 25 04:57:30 PM PDT 24
Finished Jun 25 04:57:55 PM PDT 24
Peak memory 206892 kb
Host smart-89c1564a-6670-402a-8a7d-f420ba77603f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18704
27269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.1870427269
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.1088600559
Short name T2008
Test name
Test status
Simulation time 457544863 ps
CPU time 1.3 seconds
Started Jun 25 04:57:32 PM PDT 24
Finished Jun 25 04:57:35 PM PDT 24
Peak memory 206268 kb
Host smart-81c96ace-9b13-4e66-a80e-2c04b88312d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10886
00559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.1088600559
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.2454119624
Short name T1208
Test name
Test status
Simulation time 141680859 ps
CPU time 0.75 seconds
Started Jun 25 04:57:28 PM PDT 24
Finished Jun 25 04:57:30 PM PDT 24
Peak memory 206572 kb
Host smart-b78a2dd8-c854-4f65-b4cf-f40301edc918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24541
19624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.2454119624
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.613535857
Short name T1602
Test name
Test status
Simulation time 57083852 ps
CPU time 0.71 seconds
Started Jun 25 04:57:31 PM PDT 24
Finished Jun 25 04:57:34 PM PDT 24
Peak memory 206596 kb
Host smart-058c2582-76a6-43db-8f55-3a4f25bd134c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61353
5857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.613535857
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.2798723472
Short name T1125
Test name
Test status
Simulation time 791853483 ps
CPU time 1.99 seconds
Started Jun 25 04:57:32 PM PDT 24
Finished Jun 25 04:57:36 PM PDT 24
Peak memory 206812 kb
Host smart-ed1d028d-2125-4514-880c-73e3093b573d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27987
23472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.2798723472
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.998169758
Short name T449
Test name
Test status
Simulation time 185207759 ps
CPU time 2.33 seconds
Started Jun 25 04:57:29 PM PDT 24
Finished Jun 25 04:57:33 PM PDT 24
Peak memory 206784 kb
Host smart-055f6aa3-7e03-4bee-a28a-6a9519473f63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99816
9758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.998169758
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.3849617267
Short name T2139
Test name
Test status
Simulation time 197026087 ps
CPU time 0.96 seconds
Started Jun 25 04:57:42 PM PDT 24
Finished Jun 25 04:57:45 PM PDT 24
Peak memory 206492 kb
Host smart-6b50791e-1621-4ca4-9a21-86f6a3b6bcb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38496
17267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.3849617267
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.3751006367
Short name T522
Test name
Test status
Simulation time 142140138 ps
CPU time 0.78 seconds
Started Jun 25 04:57:38 PM PDT 24
Finished Jun 25 04:57:40 PM PDT 24
Peak memory 206568 kb
Host smart-d23a89dc-79cf-4447-b23d-c8c82a84c7dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37510
06367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.3751006367
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.2639721818
Short name T51
Test name
Test status
Simulation time 189687204 ps
CPU time 0.88 seconds
Started Jun 25 04:57:29 PM PDT 24
Finished Jun 25 04:57:31 PM PDT 24
Peak memory 206504 kb
Host smart-7b9f5c2c-2085-4d8a-b4bb-5dede011c8a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26397
21818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.2639721818
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_invalid_sync.3283920919
Short name T1843
Test name
Test status
Simulation time 17554233467 ps
CPU time 502.17 seconds
Started Jun 25 04:57:29 PM PDT 24
Finished Jun 25 05:05:53 PM PDT 24
Peak memory 206976 kb
Host smart-8d20e74e-ef7e-41c2-a74a-95c9916aea81
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3283920919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.3283920919
Directory /workspace/8.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.1990806835
Short name T693
Test name
Test status
Simulation time 167905064 ps
CPU time 0.84 seconds
Started Jun 25 04:57:31 PM PDT 24
Finished Jun 25 04:57:33 PM PDT 24
Peak memory 206472 kb
Host smart-dfef7e13-5035-4ca8-9d0a-0bd2d73f2f48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19908
06835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.1990806835
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.2526874911
Short name T2157
Test name
Test status
Simulation time 23374739605 ps
CPU time 22.66 seconds
Started Jun 25 04:57:30 PM PDT 24
Finished Jun 25 04:57:54 PM PDT 24
Peak memory 206664 kb
Host smart-884dc2a9-a9c5-47a7-9698-bf8f4b94d53c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25268
74911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.2526874911
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.1627447999
Short name T17
Test name
Test status
Simulation time 3312831739 ps
CPU time 4.75 seconds
Started Jun 25 04:57:28 PM PDT 24
Finished Jun 25 04:57:34 PM PDT 24
Peak memory 206700 kb
Host smart-5b239dc1-08e7-4467-b713-f5e7dfa376be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16274
47999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.1627447999
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.360176849
Short name T396
Test name
Test status
Simulation time 12600710276 ps
CPU time 126.23 seconds
Started Jun 25 04:57:32 PM PDT 24
Finished Jun 25 04:59:40 PM PDT 24
Peak memory 206976 kb
Host smart-a5838aea-cfb3-41cb-bbbf-883396c67ed8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=360176849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.360176849
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.3795877189
Short name T1343
Test name
Test status
Simulation time 232706046 ps
CPU time 0.94 seconds
Started Jun 25 04:57:40 PM PDT 24
Finished Jun 25 04:57:42 PM PDT 24
Peak memory 206496 kb
Host smart-6d39cd21-b65d-4ba8-9b7a-a001b55a5284
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3795877189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.3795877189
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.457714128
Short name T2243
Test name
Test status
Simulation time 207631409 ps
CPU time 0.88 seconds
Started Jun 25 04:57:32 PM PDT 24
Finished Jun 25 04:57:35 PM PDT 24
Peak memory 206596 kb
Host smart-8752ee51-918d-42dc-b319-c0fd2f279836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45771
4128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.457714128
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.1189862968
Short name T1603
Test name
Test status
Simulation time 14530535823 ps
CPU time 101.89 seconds
Started Jun 25 04:57:32 PM PDT 24
Finished Jun 25 04:59:16 PM PDT 24
Peak memory 206596 kb
Host smart-c49ceb94-f5be-4bdf-9c84-1490f56a6fa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11898
62968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.1189862968
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.3113059100
Short name T1178
Test name
Test status
Simulation time 9252087021 ps
CPU time 87.09 seconds
Started Jun 25 04:57:30 PM PDT 24
Finished Jun 25 04:58:59 PM PDT 24
Peak memory 206944 kb
Host smart-8387cae1-f9d6-4e8a-8ce0-4a69cd844b8a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3113059100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.3113059100
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.1569131081
Short name T968
Test name
Test status
Simulation time 153726831 ps
CPU time 0.84 seconds
Started Jun 25 04:57:41 PM PDT 24
Finished Jun 25 04:57:44 PM PDT 24
Peak memory 206572 kb
Host smart-2d89c4c3-b48f-40bb-9379-e7447a6a2774
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1569131081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.1569131081
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.1997031220
Short name T2198
Test name
Test status
Simulation time 238705236 ps
CPU time 0.89 seconds
Started Jun 25 04:57:30 PM PDT 24
Finished Jun 25 04:57:32 PM PDT 24
Peak memory 206496 kb
Host smart-198923a9-a2a0-4296-a44b-b5103cbe4b14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19970
31220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.1997031220
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.3453658771
Short name T146
Test name
Test status
Simulation time 240347084 ps
CPU time 0.89 seconds
Started Jun 25 04:57:30 PM PDT 24
Finished Jun 25 04:57:32 PM PDT 24
Peak memory 206584 kb
Host smart-3e579d9b-8da6-48ff-b6bd-7198b32d4001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34536
58771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.3453658771
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.3263136343
Short name T1149
Test name
Test status
Simulation time 205741987 ps
CPU time 0.83 seconds
Started Jun 25 04:57:30 PM PDT 24
Finished Jun 25 04:57:32 PM PDT 24
Peak memory 206552 kb
Host smart-dc19793a-9448-4f8d-9980-30e0d083c7d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32631
36343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.3263136343
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.207820006
Short name T1385
Test name
Test status
Simulation time 145294537 ps
CPU time 0.8 seconds
Started Jun 25 04:57:32 PM PDT 24
Finished Jun 25 04:57:35 PM PDT 24
Peak memory 206568 kb
Host smart-a2bfb389-c44d-400b-a4fe-61512f7e106e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20782
0006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.207820006
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.1582890387
Short name T1783
Test name
Test status
Simulation time 165990784 ps
CPU time 0.81 seconds
Started Jun 25 04:57:33 PM PDT 24
Finished Jun 25 04:57:35 PM PDT 24
Peak memory 206520 kb
Host smart-c6d0929b-841a-4e38-82e6-548d630f0c22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15828
90387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.1582890387
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.2259333361
Short name T1434
Test name
Test status
Simulation time 161155449 ps
CPU time 0.8 seconds
Started Jun 25 04:57:39 PM PDT 24
Finished Jun 25 04:57:41 PM PDT 24
Peak memory 206544 kb
Host smart-3995497a-b8a3-46c1-942d-3015493cf1c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22593
33361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.2259333361
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.3504057392
Short name T1310
Test name
Test status
Simulation time 212888104 ps
CPU time 0.97 seconds
Started Jun 25 04:57:28 PM PDT 24
Finished Jun 25 04:57:30 PM PDT 24
Peak memory 206568 kb
Host smart-b1916316-32ca-4844-bebe-407ac405f854
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3504057392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.3504057392
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.1227439337
Short name T2012
Test name
Test status
Simulation time 144881071 ps
CPU time 0.8 seconds
Started Jun 25 04:57:31 PM PDT 24
Finished Jun 25 04:57:34 PM PDT 24
Peak memory 206568 kb
Host smart-8026edc7-fe04-4ed8-93ff-b4b8264cca60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12274
39337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.1227439337
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.506666209
Short name T1362
Test name
Test status
Simulation time 33725668 ps
CPU time 0.65 seconds
Started Jun 25 04:57:40 PM PDT 24
Finished Jun 25 04:57:42 PM PDT 24
Peak memory 206568 kb
Host smart-0a0127f2-8324-4cac-8c77-f1ad61590739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50666
6209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.506666209
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.4117766581
Short name T1405
Test name
Test status
Simulation time 17963159435 ps
CPU time 39.11 seconds
Started Jun 25 04:57:30 PM PDT 24
Finished Jun 25 04:58:10 PM PDT 24
Peak memory 206860 kb
Host smart-dd2de230-c2ed-4a83-aa66-20e03ea510d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41177
66581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.4117766581
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.2293181316
Short name T2444
Test name
Test status
Simulation time 174360346 ps
CPU time 0.88 seconds
Started Jun 25 04:57:32 PM PDT 24
Finished Jun 25 04:57:35 PM PDT 24
Peak memory 206508 kb
Host smart-5758100d-a8ce-4d9a-8637-fffa245409a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22931
81316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.2293181316
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.2544528185
Short name T825
Test name
Test status
Simulation time 170266315 ps
CPU time 0.82 seconds
Started Jun 25 04:57:28 PM PDT 24
Finished Jun 25 04:57:30 PM PDT 24
Peak memory 206580 kb
Host smart-e37890a3-eb81-49a7-ae2b-5301be4e1690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25445
28185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.2544528185
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.3943038322
Short name T172
Test name
Test status
Simulation time 5393572760 ps
CPU time 134.75 seconds
Started Jun 25 04:57:28 PM PDT 24
Finished Jun 25 04:59:44 PM PDT 24
Peak memory 206880 kb
Host smart-17eecbaf-74df-44d0-9fee-50dbfd3b726f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3943038322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.3943038322
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.2567035136
Short name T157
Test name
Test status
Simulation time 16767169796 ps
CPU time 132 seconds
Started Jun 25 04:57:30 PM PDT 24
Finished Jun 25 04:59:44 PM PDT 24
Peak memory 206900 kb
Host smart-b5d90359-2fca-459f-968e-ab7a13a81dbd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2567035136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.2567035136
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.2131253803
Short name T1801
Test name
Test status
Simulation time 13059165766 ps
CPU time 92.22 seconds
Started Jun 25 04:57:30 PM PDT 24
Finished Jun 25 04:59:04 PM PDT 24
Peak memory 206924 kb
Host smart-f6c97a74-3b71-43b1-9b60-4dc081ef05d2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2131253803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.2131253803
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.3093561149
Short name T543
Test name
Test status
Simulation time 238502692 ps
CPU time 0.9 seconds
Started Jun 25 04:57:42 PM PDT 24
Finished Jun 25 04:57:45 PM PDT 24
Peak memory 206880 kb
Host smart-a19727f5-3a69-412a-9552-b5dd48213956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30935
61149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.3093561149
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.949339811
Short name T489
Test name
Test status
Simulation time 205117562 ps
CPU time 0.87 seconds
Started Jun 25 04:57:30 PM PDT 24
Finished Jun 25 04:57:33 PM PDT 24
Peak memory 206488 kb
Host smart-0149d473-841f-4cc7-a998-92db2fabfb54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94933
9811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.949339811
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.3683331656
Short name T1958
Test name
Test status
Simulation time 168519836 ps
CPU time 0.86 seconds
Started Jun 25 04:57:31 PM PDT 24
Finished Jun 25 04:57:34 PM PDT 24
Peak memory 206512 kb
Host smart-28423f8d-9d46-4c44-9138-204124f58e72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36833
31656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.3683331656
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.2051899840
Short name T361
Test name
Test status
Simulation time 159512375 ps
CPU time 0.76 seconds
Started Jun 25 04:57:42 PM PDT 24
Finished Jun 25 04:57:45 PM PDT 24
Peak memory 206868 kb
Host smart-ba29dfbe-1355-42d7-910e-ced2dac4df1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20518
99840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.2051899840
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.1191848552
Short name T628
Test name
Test status
Simulation time 158871089 ps
CPU time 0.81 seconds
Started Jun 25 04:57:28 PM PDT 24
Finished Jun 25 04:57:30 PM PDT 24
Peak memory 206512 kb
Host smart-689a1817-03a2-4b8e-afc6-df0c9ecdc9a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11918
48552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.1191848552
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.322182615
Short name T809
Test name
Test status
Simulation time 250772380 ps
CPU time 0.98 seconds
Started Jun 25 04:57:31 PM PDT 24
Finished Jun 25 04:57:34 PM PDT 24
Peak memory 206584 kb
Host smart-c073f90a-6ab7-4035-8c65-6178b94670d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32218
2615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.322182615
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.1428286747
Short name T902
Test name
Test status
Simulation time 3016496417 ps
CPU time 82.48 seconds
Started Jun 25 04:57:31 PM PDT 24
Finished Jun 25 04:58:55 PM PDT 24
Peak memory 206876 kb
Host smart-e3c97f1b-1217-4872-9900-87fe2a49e86d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1428286747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.1428286747
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.513801390
Short name T2089
Test name
Test status
Simulation time 182035491 ps
CPU time 0.86 seconds
Started Jun 25 04:57:39 PM PDT 24
Finished Jun 25 04:57:41 PM PDT 24
Peak memory 206596 kb
Host smart-5536f528-da91-49dd-912f-b7fe65897364
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51380
1390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.513801390
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.3166217266
Short name T330
Test name
Test status
Simulation time 194085738 ps
CPU time 0.83 seconds
Started Jun 25 04:57:32 PM PDT 24
Finished Jun 25 04:57:35 PM PDT 24
Peak memory 206548 kb
Host smart-d2b31065-d6fd-4337-9d05-b052cf382c3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31662
17266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.3166217266
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.3140092799
Short name T1516
Test name
Test status
Simulation time 9275262724 ps
CPU time 89.23 seconds
Started Jun 25 04:57:32 PM PDT 24
Finished Jun 25 04:59:03 PM PDT 24
Peak memory 206788 kb
Host smart-9f944f72-81e3-4ae5-8ce1-f8d0c207921e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31400
92799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.3140092799
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.2928643530
Short name T2133
Test name
Test status
Simulation time 4145301770 ps
CPU time 4.89 seconds
Started Jun 25 04:57:40 PM PDT 24
Finished Jun 25 04:57:46 PM PDT 24
Peak memory 206896 kb
Host smart-aac4f98a-328f-4855-a233-94bb6f4280a2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2928643530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.2928643530
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.3046851964
Short name T2364
Test name
Test status
Simulation time 13350766288 ps
CPU time 14.95 seconds
Started Jun 25 04:57:39 PM PDT 24
Finished Jun 25 04:57:55 PM PDT 24
Peak memory 206640 kb
Host smart-4107a113-c1e8-4cf8-aed5-5b68f5b6d426
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3046851964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.3046851964
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.3505949994
Short name T222
Test name
Test status
Simulation time 23312856048 ps
CPU time 21.74 seconds
Started Jun 25 04:57:38 PM PDT 24
Finished Jun 25 04:58:00 PM PDT 24
Peak memory 206884 kb
Host smart-9d5bd627-7f21-4bc1-ae46-62b59ecefb7c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3505949994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.3505949994
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.163713055
Short name T793
Test name
Test status
Simulation time 153874316 ps
CPU time 0.76 seconds
Started Jun 25 04:57:41 PM PDT 24
Finished Jun 25 04:57:43 PM PDT 24
Peak memory 206508 kb
Host smart-98a8a6b5-b704-4d71-86ad-71ceae2b495a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16371
3055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.163713055
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.2178687889
Short name T1239
Test name
Test status
Simulation time 157240076 ps
CPU time 0.83 seconds
Started Jun 25 04:57:42 PM PDT 24
Finished Jun 25 04:57:45 PM PDT 24
Peak memory 206576 kb
Host smart-30933a38-3f92-4bb0-a5c2-d3fbc0bd8425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21786
87889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.2178687889
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.3141385176
Short name T1551
Test name
Test status
Simulation time 436552940 ps
CPU time 1.42 seconds
Started Jun 25 04:57:41 PM PDT 24
Finished Jun 25 04:57:44 PM PDT 24
Peak memory 206528 kb
Host smart-65546406-db6a-45f2-bd19-91338fd835a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31413
85176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.3141385176
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.3631048928
Short name T2242
Test name
Test status
Simulation time 957587678 ps
CPU time 1.97 seconds
Started Jun 25 04:57:42 PM PDT 24
Finished Jun 25 04:57:47 PM PDT 24
Peak memory 206740 kb
Host smart-7deeb715-e31d-423b-b4a3-e6ac50e0ccbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36310
48928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.3631048928
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.1036456223
Short name T1100
Test name
Test status
Simulation time 21116918848 ps
CPU time 39.37 seconds
Started Jun 25 04:57:42 PM PDT 24
Finished Jun 25 04:58:24 PM PDT 24
Peak memory 206852 kb
Host smart-e5d3a118-02da-4a7c-8d3b-a49be7c75ac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10364
56223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.1036456223
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.1107607224
Short name T978
Test name
Test status
Simulation time 406220443 ps
CPU time 1.25 seconds
Started Jun 25 04:57:39 PM PDT 24
Finished Jun 25 04:57:41 PM PDT 24
Peak memory 206500 kb
Host smart-2f5da25e-7702-44f0-828b-a8d8455fff8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11076
07224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.1107607224
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.871645811
Short name T45
Test name
Test status
Simulation time 146950200 ps
CPU time 0.78 seconds
Started Jun 25 04:57:38 PM PDT 24
Finished Jun 25 04:57:39 PM PDT 24
Peak memory 206496 kb
Host smart-8d838c4c-9ea2-4699-9e20-579ce9038649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87164
5811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.871645811
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.2928623095
Short name T2297
Test name
Test status
Simulation time 44122512 ps
CPU time 0.68 seconds
Started Jun 25 04:57:39 PM PDT 24
Finished Jun 25 04:57:41 PM PDT 24
Peak memory 206500 kb
Host smart-693815e4-26f5-4540-8217-8fd229462fed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29286
23095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.2928623095
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.3027948360
Short name T1187
Test name
Test status
Simulation time 838731181 ps
CPU time 2.28 seconds
Started Jun 25 04:57:39 PM PDT 24
Finished Jun 25 04:57:43 PM PDT 24
Peak memory 206812 kb
Host smart-2e2a73f6-8072-4eca-b679-008c66aa483d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30279
48360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.3027948360
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.169187113
Short name T2331
Test name
Test status
Simulation time 369998586 ps
CPU time 2.11 seconds
Started Jun 25 04:57:40 PM PDT 24
Finished Jun 25 04:57:44 PM PDT 24
Peak memory 206696 kb
Host smart-acf46b5e-adf9-4cbe-b8ff-42a4e013a719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16918
7113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.169187113
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.2503225981
Short name T1878
Test name
Test status
Simulation time 195035986 ps
CPU time 0.87 seconds
Started Jun 25 04:57:48 PM PDT 24
Finished Jun 25 04:57:51 PM PDT 24
Peak memory 206576 kb
Host smart-9a3c6b3a-8ab0-4bd3-9ca3-24d29f198b6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25032
25981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.2503225981
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.2785460637
Short name T1994
Test name
Test status
Simulation time 149828626 ps
CPU time 0.76 seconds
Started Jun 25 04:57:54 PM PDT 24
Finished Jun 25 04:57:57 PM PDT 24
Peak memory 206492 kb
Host smart-707f9494-1537-407d-9ae5-f9b4cdee77f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27854
60637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.2785460637
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.4010748716
Short name T2462
Test name
Test status
Simulation time 145677200 ps
CPU time 0.77 seconds
Started Jun 25 04:57:41 PM PDT 24
Finished Jun 25 04:57:43 PM PDT 24
Peak memory 206572 kb
Host smart-9237d0fd-ec5d-456b-8378-739928a66ecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40107
48716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.4010748716
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_invalid_sync.3753306020
Short name T2451
Test name
Test status
Simulation time 10995114291 ps
CPU time 80.64 seconds
Started Jun 25 04:57:41 PM PDT 24
Finished Jun 25 04:59:04 PM PDT 24
Peak memory 207224 kb
Host smart-c6c0c6ba-e61d-4ff6-b6cf-fed48d57fcc4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3753306020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.3753306020
Directory /workspace/9.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.3459495642
Short name T2085
Test name
Test status
Simulation time 157543422 ps
CPU time 0.8 seconds
Started Jun 25 04:57:41 PM PDT 24
Finished Jun 25 04:57:43 PM PDT 24
Peak memory 206508 kb
Host smart-5849195a-e709-4dde-94a2-0cac62c99fe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34594
95642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.3459495642
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.2147559517
Short name T1038
Test name
Test status
Simulation time 23298440024 ps
CPU time 29.18 seconds
Started Jun 25 04:57:40 PM PDT 24
Finished Jun 25 04:58:10 PM PDT 24
Peak memory 206708 kb
Host smart-7170b5ed-f8b9-4f3d-bbfa-9febbcf520d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21475
59517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.2147559517
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.492503825
Short name T1869
Test name
Test status
Simulation time 3270922681 ps
CPU time 3.9 seconds
Started Jun 25 04:57:41 PM PDT 24
Finished Jun 25 04:57:46 PM PDT 24
Peak memory 206692 kb
Host smart-2d85481c-cc7c-4a9a-94c1-023ec4d31825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49250
3825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.492503825
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.236468682
Short name T353
Test name
Test status
Simulation time 10086887584 ps
CPU time 287.78 seconds
Started Jun 25 04:57:44 PM PDT 24
Finished Jun 25 05:02:34 PM PDT 24
Peak memory 206948 kb
Host smart-05cf5922-df97-41ad-94f5-330f82acaf43
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=236468682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.236468682
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.3388331347
Short name T897
Test name
Test status
Simulation time 253563984 ps
CPU time 0.96 seconds
Started Jun 25 04:57:51 PM PDT 24
Finished Jun 25 04:57:54 PM PDT 24
Peak memory 206508 kb
Host smart-bebe19a3-5efe-404a-8806-d989c80dfa8d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3388331347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.3388331347
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.3993287849
Short name T1388
Test name
Test status
Simulation time 197072615 ps
CPU time 0.88 seconds
Started Jun 25 04:57:41 PM PDT 24
Finished Jun 25 04:57:43 PM PDT 24
Peak memory 206596 kb
Host smart-78cd9d8a-3da7-4c0f-8eeb-d9c78f1ab13b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39932
87849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.3993287849
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.4262093822
Short name T676
Test name
Test status
Simulation time 12254525717 ps
CPU time 339.07 seconds
Started Jun 25 04:57:41 PM PDT 24
Finished Jun 25 05:03:21 PM PDT 24
Peak memory 206868 kb
Host smart-24d2f990-8440-4387-b05f-d0fd2034060f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42620
93822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.4262093822
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.1483793353
Short name T1574
Test name
Test status
Simulation time 8461921647 ps
CPU time 236.19 seconds
Started Jun 25 04:57:41 PM PDT 24
Finished Jun 25 05:01:39 PM PDT 24
Peak memory 206972 kb
Host smart-a367497c-0b78-4ccf-847a-90213d5ac207
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1483793353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.1483793353
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.1100897243
Short name T933
Test name
Test status
Simulation time 206275990 ps
CPU time 0.88 seconds
Started Jun 25 04:57:49 PM PDT 24
Finished Jun 25 04:57:51 PM PDT 24
Peak memory 206524 kb
Host smart-89a7ab1e-81d0-4b1c-9de4-5117636d1074
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1100897243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.1100897243
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.4044104219
Short name T1872
Test name
Test status
Simulation time 204392991 ps
CPU time 0.85 seconds
Started Jun 25 04:57:41 PM PDT 24
Finished Jun 25 04:57:44 PM PDT 24
Peak memory 206536 kb
Host smart-7ed5e8ae-9af3-4acd-ba4b-89a3d1fe2ba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40441
04219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.4044104219
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.160100750
Short name T2250
Test name
Test status
Simulation time 228490192 ps
CPU time 0.92 seconds
Started Jun 25 04:57:42 PM PDT 24
Finished Jun 25 04:57:45 PM PDT 24
Peak memory 206596 kb
Host smart-1ae63bed-11b5-49c1-8d4d-cee95e9b5bfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16010
0750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.160100750
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.3808787159
Short name T729
Test name
Test status
Simulation time 157539550 ps
CPU time 0.79 seconds
Started Jun 25 04:57:40 PM PDT 24
Finished Jun 25 04:57:42 PM PDT 24
Peak memory 206508 kb
Host smart-f5d2c40d-8c77-4b2d-9ae9-e7af134f6e9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38087
87159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.3808787159
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.37631623
Short name T806
Test name
Test status
Simulation time 233857650 ps
CPU time 0.87 seconds
Started Jun 25 04:57:41 PM PDT 24
Finished Jun 25 04:57:43 PM PDT 24
Peak memory 206588 kb
Host smart-578d243a-af5c-429b-a468-0c331e92abc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37631
623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.37631623
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.636401341
Short name T421
Test name
Test status
Simulation time 190814600 ps
CPU time 0.84 seconds
Started Jun 25 04:57:44 PM PDT 24
Finished Jun 25 04:57:47 PM PDT 24
Peak memory 206576 kb
Host smart-c6b39521-54f6-4e49-b709-a29fe3736908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63640
1341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.636401341
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.2288127621
Short name T1306
Test name
Test status
Simulation time 181972861 ps
CPU time 0.83 seconds
Started Jun 25 04:57:50 PM PDT 24
Finished Jun 25 04:57:52 PM PDT 24
Peak memory 206496 kb
Host smart-294491e6-0ea9-4c6d-b893-658562a601f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22881
27621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.2288127621
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.4088857997
Short name T398
Test name
Test status
Simulation time 222505082 ps
CPU time 0.92 seconds
Started Jun 25 04:57:41 PM PDT 24
Finished Jun 25 04:57:43 PM PDT 24
Peak memory 206592 kb
Host smart-e89c9132-5e14-4cb0-aa64-0b641e23dae0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4088857997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.4088857997
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.4271355284
Short name T1032
Test name
Test status
Simulation time 155882312 ps
CPU time 0.78 seconds
Started Jun 25 04:57:44 PM PDT 24
Finished Jun 25 04:57:47 PM PDT 24
Peak memory 206576 kb
Host smart-2b6e62b9-f2c3-42f9-b733-936db68b702d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42713
55284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.4271355284
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.3210005372
Short name T1548
Test name
Test status
Simulation time 98914805 ps
CPU time 0.76 seconds
Started Jun 25 04:57:48 PM PDT 24
Finished Jun 25 04:57:50 PM PDT 24
Peak memory 206568 kb
Host smart-15bd03c2-c4d9-43d2-a09c-69a159ab6dfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32100
05372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.3210005372
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.3745708239
Short name T1592
Test name
Test status
Simulation time 22745732141 ps
CPU time 57.63 seconds
Started Jun 25 04:57:43 PM PDT 24
Finished Jun 25 04:58:43 PM PDT 24
Peak memory 206912 kb
Host smart-1de019b1-62af-4f5f-9f67-1f6a148c4fdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37457
08239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.3745708239
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.3018936018
Short name T2447
Test name
Test status
Simulation time 156068607 ps
CPU time 0.83 seconds
Started Jun 25 04:57:43 PM PDT 24
Finished Jun 25 04:57:46 PM PDT 24
Peak memory 206512 kb
Host smart-19227501-5f6f-4ad6-923d-d1f287683020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30189
36018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.3018936018
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.3270453251
Short name T947
Test name
Test status
Simulation time 243600986 ps
CPU time 0.96 seconds
Started Jun 25 04:57:44 PM PDT 24
Finished Jun 25 04:57:46 PM PDT 24
Peak memory 206496 kb
Host smart-a5eb267a-bbc5-4d7a-84e4-df04cf513af9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32704
53251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.3270453251
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.649050528
Short name T735
Test name
Test status
Simulation time 12967673887 ps
CPU time 86.99 seconds
Started Jun 25 04:57:42 PM PDT 24
Finished Jun 25 04:59:11 PM PDT 24
Peak memory 207004 kb
Host smart-d60cbd0d-f365-4b11-b187-7f631ac4a118
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=649050528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.649050528
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.3502482901
Short name T1725
Test name
Test status
Simulation time 28539319699 ps
CPU time 708.24 seconds
Started Jun 25 04:57:43 PM PDT 24
Finished Jun 25 05:09:34 PM PDT 24
Peak memory 206928 kb
Host smart-5f2d3c5e-e053-4e05-8b04-bd72781eb2ca
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3502482901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.3502482901
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.4157365759
Short name T1174
Test name
Test status
Simulation time 16148829041 ps
CPU time 87.23 seconds
Started Jun 25 04:57:44 PM PDT 24
Finished Jun 25 04:59:13 PM PDT 24
Peak memory 206848 kb
Host smart-e588c88c-4845-44c6-8e9b-7dd152fdbd62
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4157365759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.4157365759
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.2767502912
Short name T2469
Test name
Test status
Simulation time 182076965 ps
CPU time 0.84 seconds
Started Jun 25 04:57:49 PM PDT 24
Finished Jun 25 04:57:51 PM PDT 24
Peak memory 206616 kb
Host smart-d29cde90-0a21-4e28-9598-212b674bc76b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27675
02912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.2767502912
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.10617912
Short name T2387
Test name
Test status
Simulation time 221031928 ps
CPU time 0.91 seconds
Started Jun 25 04:57:42 PM PDT 24
Finished Jun 25 04:57:45 PM PDT 24
Peak memory 206584 kb
Host smart-c8799d70-84b4-4b11-8d86-c6865108663b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10617
912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.10617912
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.693046637
Short name T1116
Test name
Test status
Simulation time 163931193 ps
CPU time 0.83 seconds
Started Jun 25 04:57:43 PM PDT 24
Finished Jun 25 04:57:46 PM PDT 24
Peak memory 206500 kb
Host smart-59261ab1-8b03-484f-b6a6-aa291d8e2523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69304
6637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.693046637
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.2434204300
Short name T964
Test name
Test status
Simulation time 242106593 ps
CPU time 0.83 seconds
Started Jun 25 04:57:51 PM PDT 24
Finished Jun 25 04:57:54 PM PDT 24
Peak memory 206496 kb
Host smart-21595dc2-09d3-4602-b160-03d0bd0a9b3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24342
04300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.2434204300
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.93231489
Short name T100
Test name
Test status
Simulation time 174298224 ps
CPU time 0.8 seconds
Started Jun 25 04:57:54 PM PDT 24
Finished Jun 25 04:57:57 PM PDT 24
Peak memory 206540 kb
Host smart-ca549cdd-813a-46f2-b549-6fd818d40156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93231
489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.93231489
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.458466260
Short name T1805
Test name
Test status
Simulation time 211710182 ps
CPU time 0.94 seconds
Started Jun 25 04:57:41 PM PDT 24
Finished Jun 25 04:57:43 PM PDT 24
Peak memory 206492 kb
Host smart-646a82d6-d403-4a2b-b5ff-f211822b1836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45846
6260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.458466260
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.1921816557
Short name T2111
Test name
Test status
Simulation time 5229473446 ps
CPU time 147.4 seconds
Started Jun 25 04:57:42 PM PDT 24
Finished Jun 25 05:00:11 PM PDT 24
Peak memory 206880 kb
Host smart-64745ca8-e805-423b-8b8d-1b5e4efb5082
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1921816557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.1921816557
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.1476854721
Short name T2003
Test name
Test status
Simulation time 182668727 ps
CPU time 0.85 seconds
Started Jun 25 04:57:52 PM PDT 24
Finished Jun 25 04:57:56 PM PDT 24
Peak memory 206576 kb
Host smart-eb348a5d-6bb3-42fd-b0d8-b0ef0c2a89e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14768
54721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.1476854721
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.2770921682
Short name T823
Test name
Test status
Simulation time 178686291 ps
CPU time 0.81 seconds
Started Jun 25 04:57:47 PM PDT 24
Finished Jun 25 04:57:49 PM PDT 24
Peak memory 206576 kb
Host smart-17fc7161-44c9-4d65-ad87-88deed49bdec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27709
21682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.2770921682
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.2891435356
Short name T387
Test name
Test status
Simulation time 3919535378 ps
CPU time 36.39 seconds
Started Jun 25 04:57:51 PM PDT 24
Finished Jun 25 04:58:30 PM PDT 24
Peak memory 206864 kb
Host smart-c23817ed-db04-446e-a716-13eacbacafcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28914
35356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.2891435356
Directory /workspace/9.usbdev_streaming_out/latest
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