Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	120548	1		T1	2		T2	3		T3	4
all_values[1]	120548	1		T1	2		T2	3		T3	4
all_values[2]	120548	1		T1	2		T2	3		T3	4
all_values[3]	120548	1		T1	2		T2	3		T3	4
all_values[4]	120548	1		T1	2		T2	3		T3	4
all_values[5]	120548	1		T1	2		T2	3		T3	4
all_values[6]	120548	1		T1	2		T2	3		T3	4
all_values[7]	120548	1		T1	2		T2	3		T3	4
all_values[8]	120548	1		T1	2		T2	3		T3	4
all_values[9]	120548	1		T1	2		T2	3		T3	4
all_values[10]	120548	1		T1	2		T2	3		T3	4
all_values[11]	120548	1		T1	2		T2	3		T3	4
all_values[12]	120548	1		T1	2		T2	3		T3	4
all_values[13]	120548	1		T1	2		T2	3		T3	4
all_values[14]	120548	1		T1	2		T2	3		T3	4
all_values[15]	120548	1		T1	2		T2	3		T3	4
all_values[16]	120548	1		T1	2		T2	3		T3	4
all_values[17]	120548	1		T1	2		T2	3		T3	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2162863	1		T1	36		T2	51		T3	70
auto[1]	7001	1		T2	3		T3	2		T17	14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2164936	1		T1	36		T2	54		T3	72
auto[1]	4928	1		T210	126		T211	123		T213	54

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	119575	1		T1	2		T2	3		T3	4
all_values[0]	auto[0]	auto[1]	118	1		T213	4		T212	4		T304	4
all_values[0]	auto[1]	auto[0]	707	1		T27	3		T41	3		T42	3
all_values[0]	auto[1]	auto[1]	148	1		T210	5		T211	8		T213	1
all_values[1]	auto[0]	auto[0]	118751	1		T1	2		T3	2		T16	4
all_values[1]	auto[0]	auto[1]	146	1		T210	2		T211	1		T213	3
all_values[1]	auto[1]	auto[0]	1543	1		T2	3		T3	2		T17	14
all_values[1]	auto[1]	auto[1]	108	1		T210	6		T211	5		T212	3
all_values[2]	auto[0]	auto[0]	120134	1		T1	2		T2	3		T3	4
all_values[2]	auto[0]	auto[1]	137	1		T210	4		T211	3		T213	3
all_values[2]	auto[1]	auto[0]	126	1		T35	2		T36	2		T37	2
all_values[2]	auto[1]	auto[1]	151	1		T210	4		T211	3		T213	1
all_values[3]	auto[0]	auto[0]	118760	1		T1	2		T2	3		T3	4
all_values[3]	auto[0]	auto[1]	119	1		T210	1		T211	4		T213	1
all_values[3]	auto[1]	auto[0]	1507	1		T60	1485		T210	2		T211	1
all_values[3]	auto[1]	auto[1]	162	1		T210	3		T211	2		T213	4
all_values[4]	auto[0]	auto[0]	120256	1		T1	2		T2	3		T3	4
all_values[4]	auto[0]	auto[1]	119	1		T210	6		T213	3		T212	4
all_values[4]	auto[1]	auto[0]	39	1		T61	2		T211	1		T305	1
all_values[4]	auto[1]	auto[1]	134	1		T210	1		T211	4		T213	1
all_values[5]	auto[0]	auto[0]	120247	1		T1	2		T2	3		T3	4
all_values[5]	auto[0]	auto[1]	149	1		T210	2		T211	3		T212	1
all_values[5]	auto[1]	auto[0]	21	1		T213	2		T304	3		T305	1
all_values[5]	auto[1]	auto[1]	131	1		T210	5		T211	4		T212	6
all_values[6]	auto[0]	auto[0]	120251	1		T1	2		T2	3		T3	4
all_values[6]	auto[0]	auto[1]	109	1		T210	6		T211	3		T212	1
all_values[6]	auto[1]	auto[0]	31	1		T210	1		T211	1		T213	1
all_values[6]	auto[1]	auto[1]	157	1		T210	1		T211	4		T212	6
all_values[7]	auto[0]	auto[0]	120226	1		T1	2		T2	3		T3	4
all_values[7]	auto[0]	auto[1]	164	1		T210	4		T211	4		T213	1
all_values[7]	auto[1]	auto[0]	31	1		T25	2		T44	2		T45	2
all_values[7]	auto[1]	auto[1]	127	1		T210	2		T211	3		T213	4
all_values[8]	auto[0]	auto[0]	120226	1		T1	2		T2	3		T3	4
all_values[8]	auto[0]	auto[1]	137	1		T210	1		T211	2		T213	1
all_values[8]	auto[1]	auto[0]	38	1		T49	11		T211	1		T306	1
all_values[8]	auto[1]	auto[1]	147	1		T210	6		T211	5		T213	4
all_values[9]	auto[0]	auto[0]	120224	1		T1	2		T2	3		T3	4
all_values[9]	auto[0]	auto[1]	131	1		T210	3		T211	5		T213	2
all_values[9]	auto[1]	auto[0]	55	1		T40	5		T58	5		T59	5
all_values[9]	auto[1]	auto[1]	138	1		T210	5		T211	2		T213	3
all_values[10]	auto[0]	auto[0]	120245	1		T1	2		T2	3		T3	4
all_values[10]	auto[0]	auto[1]	140	1		T210	5		T211	1		T212	5
all_values[10]	auto[1]	auto[0]	35	1		T210	1		T213	1		T212	1
all_values[10]	auto[1]	auto[1]	128	1		T210	2		T211	5		T212	2
all_values[11]	auto[0]	auto[0]	120146	1		T1	2		T2	3		T3	4
all_values[11]	auto[0]	auto[1]	138	1		T210	5		T211	6		T213	1
all_values[11]	auto[1]	auto[0]	130	1		T39	2		T66	2		T67	2
all_values[11]	auto[1]	auto[1]	134	1		T210	2		T211	2		T213	3
all_values[12]	auto[0]	auto[0]	120222	1		T1	2		T2	3		T3	4
all_values[12]	auto[0]	auto[1]	160	1		T210	4		T211	5		T212	4
all_values[12]	auto[1]	auto[0]	47	1		T68	3		T70	3		T71	3
all_values[12]	auto[1]	auto[1]	119	1		T210	2		T211	3		T212	4
all_values[13]	auto[0]	auto[0]	120246	1		T1	2		T2	3		T3	4
all_values[13]	auto[0]	auto[1]	142	1		T210	3		T211	7		T213	3
all_values[13]	auto[1]	auto[0]	36	1		T211	1		T213	1		T212	1
all_values[13]	auto[1]	auto[1]	124	1		T210	5		T213	1		T212	3
all_values[14]	auto[0]	auto[0]	120238	1		T1	2		T2	3		T3	4
all_values[14]	auto[0]	auto[1]	120	1		T210	5		T211	2		T213	1
all_values[14]	auto[1]	auto[0]	23	1		T212	1		T304	1		T303	2
all_values[14]	auto[1]	auto[1]	167	1		T210	3		T211	6		T213	4
all_values[15]	auto[0]	auto[0]	120248	1		T1	2		T2	3		T3	4
all_values[15]	auto[0]	auto[1]	123	1		T210	5		T211	2		T212	5
all_values[15]	auto[1]	auto[0]	35	1		T211	1		T213	2		T304	1
all_values[15]	auto[1]	auto[1]	142	1		T210	3		T211	5		T212	2
all_values[16]	auto[0]	auto[0]	120218	1		T1	2		T2	3		T3	4
all_values[16]	auto[0]	auto[1]	122	1		T210	7		T211	1		T212	5
all_values[16]	auto[1]	auto[0]	59	1		T63	8		T64	8		T65	8
all_values[16]	auto[1]	auto[1]	149	1		T210	1		T211	7		T212	3
all_values[17]	auto[0]	auto[0]	120235	1		T1	2		T2	3		T3	4
all_values[17]	auto[0]	auto[1]	141	1		T210	3		T211	2		T213	3
all_values[17]	auto[1]	auto[0]	25	1		T50	2		T51	2		T210	1
all_values[17]	auto[1]	auto[1]	147	1		T210	4		T211	4		T213	2