Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	120548	1		T1	2		T2	3		T3	4
all_pins[1]	120548	1		T1	2		T2	3		T3	4
all_pins[2]	120548	1		T1	2		T2	3		T3	4
all_pins[3]	120548	1		T1	2		T2	3		T3	4
all_pins[4]	120548	1		T1	2		T2	3		T3	4
all_pins[5]	120548	1		T1	2		T2	3		T3	4
all_pins[6]	120548	1		T1	2		T2	3		T3	4
all_pins[7]	120548	1		T1	2		T2	3		T3	4
all_pins[8]	120548	1		T1	2		T2	3		T3	4
all_pins[9]	120548	1		T1	2		T2	3		T3	4
all_pins[10]	120548	1		T1	2		T2	3		T3	4
all_pins[11]	120548	1		T1	2		T2	3		T3	4
all_pins[12]	120548	1		T1	2		T2	3		T3	4
all_pins[13]	120548	1		T1	2		T2	3		T3	4
all_pins[14]	120548	1		T1	2		T2	3		T3	4
all_pins[15]	120548	1		T1	2		T2	3		T3	4
all_pins[16]	120548	1		T1	2		T2	3		T3	4
all_pins[17]	120548	1		T1	2		T2	3		T3	4

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2167530	1		T1	36		T2	53		T3	71
values[0x1]	2334	1		T2	1		T3	1		T17	12
transitions[0x0=>0x1]	2003	1		T2	1		T3	1		T17	12
transitions[0x1=>0x0]	2021	1		T2	1		T3	1		T17	12

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	120439	1		T1	2		T2	3		T3	4
all_pins[0]	values[0x1]	109	1		T43	1		T292	1		T307	1
all_pins[0]	transitions[0x0=>0x1]	95	1		T43	1		T292	1		T307	1
all_pins[0]	transitions[0x1=>0x0]	979	1		T2	1		T3	1		T17	12
all_pins[1]	values[0x0]	119555	1		T1	2		T2	2		T3	3
all_pins[1]	values[0x1]	993	1		T2	1		T3	1		T17	12
all_pins[1]	transitions[0x0=>0x1]	979	1		T2	1		T3	1		T17	12
all_pins[1]	transitions[0x1=>0x0]	117	1		T35	1		T36	1		T37	1
all_pins[2]	values[0x0]	120417	1		T1	2		T2	3		T3	4
all_pins[2]	values[0x1]	131	1		T35	1		T36	1		T37	1
all_pins[2]	transitions[0x0=>0x1]	108	1		T35	1		T36	1		T37	1
all_pins[2]	transitions[0x1=>0x0]	57	1		T60	1		T211	1		T213	1
all_pins[3]	values[0x0]	120468	1		T1	2		T2	3		T3	4
all_pins[3]	values[0x1]	80	1		T60	1		T210	2		T211	1
all_pins[3]	transitions[0x0=>0x1]	64	1		T60	1		T210	2		T211	1
all_pins[3]	transitions[0x1=>0x0]	44	1		T61	1		T211	3		T213	1
all_pins[4]	values[0x0]	120488	1		T1	2		T2	3		T3	4
all_pins[4]	values[0x1]	60	1		T61	1		T211	3		T213	1
all_pins[4]	transitions[0x0=>0x1]	38	1		T61	1		T211	2		T213	1
all_pins[4]	transitions[0x1=>0x0]	42	1		T210	3		T211	1		T303	2
all_pins[5]	values[0x0]	120484	1		T1	2		T2	3		T3	4
all_pins[5]	values[0x1]	64	1		T210	3		T211	2		T212	2
all_pins[5]	transitions[0x0=>0x1]	47	1		T210	3		T211	2		T212	2
all_pins[5]	transitions[0x1=>0x0]	62	1		T211	3		T212	1		T306	1
all_pins[6]	values[0x0]	120469	1		T1	2		T2	3		T3	4
all_pins[6]	values[0x1]	79	1		T211	3		T212	1		T306	1
all_pins[6]	transitions[0x0=>0x1]	63	1		T211	2		T212	1		T306	1
all_pins[6]	transitions[0x1=>0x0]	44	1		T25	1		T44	1		T45	1
all_pins[7]	values[0x0]	120488	1		T1	2		T2	3		T3	4
all_pins[7]	values[0x1]	60	1		T25	1		T44	1		T45	1
all_pins[7]	transitions[0x0=>0x1]	45	1		T25	1		T44	1		T45	1
all_pins[7]	transitions[0x1=>0x0]	48	1		T49	1		T210	1		T213	1
all_pins[8]	values[0x0]	120485	1		T1	2		T2	3		T3	4
all_pins[8]	values[0x1]	63	1		T49	1		T210	3		T213	1
all_pins[8]	transitions[0x0=>0x1]	46	1		T49	1		T210	3		T213	1
all_pins[8]	transitions[0x1=>0x0]	55	1		T40	2		T58	2		T59	2
all_pins[9]	values[0x0]	120476	1		T1	2		T2	3		T3	4
all_pins[9]	values[0x1]	72	1		T40	2		T58	2		T59	2
all_pins[9]	transitions[0x0=>0x1]	57	1		T40	2		T58	2		T59	2
all_pins[9]	transitions[0x1=>0x0]	66	1		T210	2		T211	3		T212	1
all_pins[10]	values[0x0]	120467	1		T1	2		T2	3		T3	4
all_pins[10]	values[0x1]	81	1		T210	2		T211	4		T212	2
all_pins[10]	transitions[0x0=>0x1]	54	1		T210	1		T211	3		T212	1
all_pins[10]	transitions[0x1=>0x0]	94	1		T39	1		T66	1		T67	1
all_pins[11]	values[0x0]	120427	1		T1	2		T2	3		T3	4
all_pins[11]	values[0x1]	121	1		T39	1		T66	1		T67	1
all_pins[11]	transitions[0x0=>0x1]	112	1		T39	1		T66	1		T67	1
all_pins[11]	transitions[0x1=>0x0]	58	1		T68	1		T70	1		T71	1
all_pins[12]	values[0x0]	120481	1		T1	2		T2	3		T3	4
all_pins[12]	values[0x1]	67	1		T68	1		T70	1		T71	1
all_pins[12]	transitions[0x0=>0x1]	51	1		T68	1		T70	1		T71	1
all_pins[12]	transitions[0x1=>0x0]	44	1		T210	2		T213	1		T304	2
all_pins[13]	values[0x0]	120488	1		T1	2		T2	3		T3	4
all_pins[13]	values[0x1]	60	1		T210	2		T213	1		T304	3
all_pins[13]	transitions[0x0=>0x1]	39	1		T210	2		T213	1		T304	3
all_pins[13]	transitions[0x1=>0x0]	60	1		T210	2		T211	2		T213	1
all_pins[14]	values[0x0]	120467	1		T1	2		T2	3		T3	4
all_pins[14]	values[0x1]	81	1		T210	2		T211	2		T213	1
all_pins[14]	transitions[0x0=>0x1]	58	1		T210	1		T211	2		T213	1
all_pins[14]	transitions[0x1=>0x0]	35	1		T210	1		T211	2		T304	1
all_pins[15]	values[0x0]	120490	1		T1	2		T2	3		T3	4
all_pins[15]	values[0x1]	58	1		T210	2		T211	2		T304	1
all_pins[15]	transitions[0x0=>0x1]	42	1		T210	2		T308	1		T309	2
all_pins[15]	transitions[0x1=>0x0]	73	1		T63	4		T64	4		T65	4
all_pins[16]	values[0x0]	120459	1		T1	2		T2	3		T3	4
all_pins[16]	values[0x1]	89	1		T63	4		T64	4		T65	4
all_pins[16]	transitions[0x0=>0x1]	70	1		T63	4		T64	4		T65	4
all_pins[16]	transitions[0x1=>0x0]	47	1		T50	1		T51	1		T210	1
all_pins[17]	values[0x0]	120482	1		T1	2		T2	3		T3	4
all_pins[17]	values[0x1]	66	1		T50	1		T51	1		T210	1
all_pins[17]	transitions[0x0=>0x1]	35	1		T50	1		T51	1		T210	1
all_pins[17]	transitions[0x1=>0x0]	96	1		T43	1		T292	1		T307	1