Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	278	1		T210	7		T211	7		T213	4
all_values[1]	278	1		T210	7		T211	7		T213	4
all_values[2]	278	1		T210	7		T211	7		T213	4
all_values[3]	278	1		T210	7		T211	7		T213	4
all_values[4]	278	1		T210	7		T211	7		T213	4
all_values[5]	278	1		T210	7		T211	7		T213	4
all_values[6]	278	1		T210	7		T211	7		T213	4
all_values[7]	278	1		T210	7		T211	7		T213	4
all_values[8]	278	1		T210	7		T211	7		T213	4
all_values[9]	278	1		T210	7		T211	7		T213	4
all_values[10]	278	1		T210	7		T211	7		T213	4
all_values[11]	278	1		T210	7		T211	7		T213	4
all_values[12]	278	1		T210	7		T211	7		T213	4
all_values[13]	278	1		T210	7		T211	7		T213	4
all_values[14]	278	1		T210	7		T211	7		T213	4
all_values[15]	278	1		T210	7		T211	7		T213	4
all_values[16]	278	1		T210	7		T211	7		T213	4
all_values[17]	278	1		T210	7		T211	7		T213	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2637	1		T210	73		T211	51		T213	41
auto[1]	2367	1		T210	53		T211	75		T213	31

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	914	1		T210	18		T211	21		T213	30
auto[1]	4090	1		T210	108		T211	105		T213	42

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2937	1		T210	72		T211	74		T213	51
auto[1]	2067	1		T210	54		T211	52		T213	21

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	31	1		T210	2		T302	1		T303	1
all_values[0]	auto[0]	auto[0]	auto[1]	42	1		T213	2		T212	3		T304	2
all_values[0]	auto[0]	auto[1]	auto[0]	28	1		T210	1		T308	1		T309	5
all_values[0]	auto[0]	auto[1]	auto[1]	61	1		T210	2		T211	2		T212	2
all_values[0]	auto[1]	auto[0]	auto[1]	56	1		T210	1		T213	1		T212	2
all_values[0]	auto[1]	auto[1]	auto[1]	60	1		T210	1		T211	5		T213	1
all_values[1]	auto[0]	auto[0]	auto[0]	39	1		T211	2		T213	1		T305	1
all_values[1]	auto[0]	auto[0]	auto[1]	61	1		T210	2		T213	1		T212	3
all_values[1]	auto[0]	auto[1]	auto[0]	30	1		T213	1		T303	1		T310	1
all_values[1]	auto[0]	auto[1]	auto[1]	43	1		T210	2		T211	3		T212	1
all_values[1]	auto[1]	auto[0]	auto[1]	53	1		T210	1		T212	1		T304	2
all_values[1]	auto[1]	auto[1]	auto[1]	52	1		T210	2		T211	2		T213	1
all_values[2]	auto[0]	auto[0]	auto[0]	17	1		T211	2		T213	1		T311	1
all_values[2]	auto[0]	auto[0]	auto[1]	46	1		T210	2		T211	2		T213	1
all_values[2]	auto[0]	auto[1]	auto[0]	23	1		T304	1		T302	2		T305	1
all_values[2]	auto[0]	auto[1]	auto[1]	58	1		T210	1		T211	1		T212	1
all_values[2]	auto[1]	auto[0]	auto[1]	70	1		T210	3		T211	1		T212	4
all_values[2]	auto[1]	auto[1]	auto[1]	64	1		T210	1		T211	1		T213	2
all_values[3]	auto[0]	auto[0]	auto[0]	29	1		T210	3		T212	1		T308	3
all_values[3]	auto[0]	auto[0]	auto[1]	49	1		T211	1		T212	3		T304	1
all_values[3]	auto[0]	auto[1]	auto[0]	16	1		T210	1		T211	2		T308	1
all_values[3]	auto[0]	auto[1]	auto[1]	59	1		T210	1		T211	2		T213	1
all_values[3]	auto[1]	auto[0]	auto[1]	64	1		T210	1		T211	1		T213	2
all_values[3]	auto[1]	auto[1]	auto[1]	61	1		T210	1		T211	1		T213	1
all_values[4]	auto[0]	auto[0]	auto[0]	46	1		T210	1		T211	4		T213	1
all_values[4]	auto[0]	auto[0]	auto[1]	55	1		T210	4		T213	1		T212	1
all_values[4]	auto[0]	auto[1]	auto[0]	23	1		T305	1		T312	1		T313	1
all_values[4]	auto[0]	auto[1]	auto[1]	59	1		T211	2		T213	1		T212	1
all_values[4]	auto[1]	auto[0]	auto[1]	60	1		T210	2		T213	1		T212	2
all_values[4]	auto[1]	auto[1]	auto[1]	35	1		T211	1		T212	2		T308	1
all_values[5]	auto[0]	auto[0]	auto[0]	27	1		T210	1		T211	1		T213	2
all_values[5]	auto[0]	auto[0]	auto[1]	71	1		T211	2		T304	2		T306	3
all_values[5]	auto[0]	auto[1]	auto[0]	17	1		T213	2		T304	3		T305	1
all_values[5]	auto[0]	auto[1]	auto[1]	55	1		T210	1		T211	2		T212	3
all_values[5]	auto[1]	auto[0]	auto[1]	57	1		T210	1		T211	1		T212	1
all_values[5]	auto[1]	auto[1]	auto[1]	51	1		T210	4		T211	1		T212	2
all_values[6]	auto[0]	auto[0]	auto[0]	33	1		T213	3		T212	1		T304	2
all_values[6]	auto[0]	auto[0]	auto[1]	44	1		T210	2		T212	1		T304	1
all_values[6]	auto[0]	auto[1]	auto[0]	26	1		T210	1		T211	1		T213	1
all_values[6]	auto[0]	auto[1]	auto[1]	67	1		T211	2		T212	3		T306	1
all_values[6]	auto[1]	auto[0]	auto[1]	52	1		T210	3		T211	1		T304	1
all_values[6]	auto[1]	auto[1]	auto[1]	56	1		T210	1		T211	3		T212	2
all_values[7]	auto[0]	auto[0]	auto[0]	19	1		T210	2		T211	1		T302	1
all_values[7]	auto[0]	auto[0]	auto[1]	65	1		T210	3		T213	1		T212	1
all_values[7]	auto[0]	auto[1]	auto[0]	15	1		T308	1		T303	2		T311	1
all_values[7]	auto[0]	auto[1]	auto[1]	53	1		T211	1		T213	2		T212	2
all_values[7]	auto[1]	auto[0]	auto[1]	76	1		T210	1		T211	4		T213	1
all_values[7]	auto[1]	auto[1]	auto[1]	50	1		T210	1		T211	1		T212	2
all_values[8]	auto[0]	auto[0]	auto[0]	22	1		T210	1		T306	1		T302	2
all_values[8]	auto[0]	auto[0]	auto[1]	66	1		T211	1		T213	1		T212	3
all_values[8]	auto[0]	auto[1]	auto[0]	21	1		T211	1		T305	2		T309	2
all_values[8]	auto[0]	auto[1]	auto[1]	57	1		T210	2		T211	3		T213	1
all_values[8]	auto[1]	auto[0]	auto[1]	60	1		T210	1		T213	1		T212	3
all_values[8]	auto[1]	auto[1]	auto[1]	52	1		T210	3		T211	2		T213	1
all_values[9]	auto[0]	auto[0]	auto[0]	35	1		T212	1		T306	1		T302	4
all_values[9]	auto[0]	auto[0]	auto[1]	54	1		T210	1		T211	2		T213	1
all_values[9]	auto[0]	auto[1]	auto[0]	22	1		T211	1		T212	1		T309	1
all_values[9]	auto[0]	auto[1]	auto[1]	56	1		T210	5		T211	3		T213	1
all_values[9]	auto[1]	auto[0]	auto[1]	60	1		T210	1		T213	2		T212	2
all_values[9]	auto[1]	auto[1]	auto[1]	51	1		T211	1		T212	1		T304	2
all_values[10]	auto[0]	auto[0]	auto[0]	33	1		T211	2		T213	3		T212	1
all_values[10]	auto[0]	auto[0]	auto[1]	67	1		T210	2		T211	1		T212	3
all_values[10]	auto[0]	auto[1]	auto[0]	22	1		T210	1		T213	1		T308	3
all_values[10]	auto[0]	auto[1]	auto[1]	54	1		T210	1		T211	3		T212	2
all_values[10]	auto[1]	auto[0]	auto[1]	48	1		T210	3		T306	2		T302	1
all_values[10]	auto[1]	auto[1]	auto[1]	54	1		T211	1		T212	1		T304	2
all_values[11]	auto[0]	auto[0]	auto[0]	36	1		T210	1		T213	1		T212	1
all_values[11]	auto[0]	auto[0]	auto[1]	57	1		T210	3		T211	2		T213	1
all_values[11]	auto[0]	auto[1]	auto[0]	17	1		T306	1		T314	1		T315	1
all_values[11]	auto[0]	auto[1]	auto[1]	45	1		T211	1		T213	1		T304	2
all_values[11]	auto[1]	auto[0]	auto[1]	67	1		T210	2		T211	3		T213	1
all_values[11]	auto[1]	auto[1]	auto[1]	56	1		T210	1		T211	1		T212	2
all_values[12]	auto[0]	auto[0]	auto[0]	23	1		T210	2		T213	2		T306	1
all_values[12]	auto[0]	auto[0]	auto[1]	58	1		T210	2		T211	1		T212	2
all_values[12]	auto[0]	auto[1]	auto[0]	22	1		T213	2		T311	2		T310	3
all_values[12]	auto[0]	auto[1]	auto[1]	55	1		T210	1		T211	2		T212	1
all_values[12]	auto[1]	auto[0]	auto[1]	81	1		T210	2		T211	4		T212	3
all_values[12]	auto[1]	auto[1]	auto[1]	39	1		T212	1		T302	1		T305	2
all_values[13]	auto[0]	auto[0]	auto[0]	30	1		T213	1		T212	3		T306	3
all_values[13]	auto[0]	auto[0]	auto[1]	57	1		T210	2		T211	2		T213	1
all_values[13]	auto[0]	auto[1]	auto[0]	27	1		T211	1		T304	3		T309	1
all_values[13]	auto[0]	auto[1]	auto[1]	58	1		T210	2		T213	1		T212	1
all_values[13]	auto[1]	auto[0]	auto[1]	63	1		T210	1		T211	3		T212	3
all_values[13]	auto[1]	auto[1]	auto[1]	43	1		T210	2		T211	1		T213	1
all_values[14]	auto[0]	auto[0]	auto[0]	24	1		T212	5		T304	2		T303	3
all_values[14]	auto[0]	auto[0]	auto[1]	45	1		T210	1		T211	2		T212	1
all_values[14]	auto[0]	auto[1]	auto[0]	15	1		T303	1		T315	1		T316	2
all_values[14]	auto[0]	auto[1]	auto[1]	74	1		T210	1		T211	3		T213	2
all_values[14]	auto[1]	auto[0]	auto[1]	59	1		T210	2		T211	2		T213	2
all_values[14]	auto[1]	auto[1]	auto[1]	61	1		T210	3		T212	1		T304	2
all_values[15]	auto[0]	auto[0]	auto[0]	34	1		T213	2		T212	1		T304	2
all_values[15]	auto[0]	auto[0]	auto[1]	52	1		T210	2		T212	2		T304	1
all_values[15]	auto[0]	auto[1]	auto[0]	23	1		T211	1		T213	2		T308	1
all_values[15]	auto[0]	auto[1]	auto[1]	61	1		T210	2		T211	3		T212	1
all_values[15]	auto[1]	auto[0]	auto[1]	59	1		T210	1		T212	2		T304	3
all_values[15]	auto[1]	auto[1]	auto[1]	49	1		T210	2		T211	3		T212	1
all_values[16]	auto[0]	auto[0]	auto[0]	24	1		T213	1		T302	2		T308	4
all_values[16]	auto[0]	auto[0]	auto[1]	52	1		T210	3		T211	1		T212	1
all_values[16]	auto[0]	auto[1]	auto[0]	27	1		T213	3		T304	3		T302	2
all_values[16]	auto[0]	auto[1]	auto[1]	57	1		T210	1		T211	1		T212	3
all_values[16]	auto[1]	auto[0]	auto[1]	62	1		T210	3		T211	1		T212	2
all_values[16]	auto[1]	auto[1]	auto[1]	56	1		T211	4		T212	1		T306	2
all_values[17]	auto[0]	auto[0]	auto[0]	22	1		T212	3		T306	1		T305	1
all_values[17]	auto[0]	auto[0]	auto[1]	56	1		T213	1		T212	2		T304	1
all_values[17]	auto[0]	auto[1]	auto[0]	16	1		T210	1		T211	2		T306	1
all_values[17]	auto[0]	auto[1]	auto[1]	54	1		T210	3		T211	2		T212	1
all_values[17]	auto[1]	auto[0]	auto[1]	69	1		T210	2		T211	1		T213	1
all_values[17]	auto[1]	auto[1]	auto[1]	61	1		T210	1		T211	2		T213	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal