Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.35 97.82 93.76 97.44 73.44 96.21 98.17 96.58


Total test records in report: 2686
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T2573 /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.4161090125 Jun 26 05:15:39 PM PDT 24 Jun 26 05:16:49 PM PDT 24 7057251523 ps
T2574 /workspace/coverage/default/0.usbdev_max_length_in_transaction.1580988329 Jun 26 05:10:15 PM PDT 24 Jun 26 05:10:17 PM PDT 24 291719392 ps
T2575 /workspace/coverage/default/9.usbdev_setup_trans_ignored.3871918635 Jun 26 05:14:04 PM PDT 24 Jun 26 05:14:06 PM PDT 24 146943061 ps
T2576 /workspace/coverage/default/6.usbdev_random_length_in_transaction.3810857019 Jun 26 05:13:02 PM PDT 24 Jun 26 05:13:04 PM PDT 24 200947355 ps
T2577 /workspace/coverage/default/24.usbdev_phy_pins_sense.51888422 Jun 26 05:17:37 PM PDT 24 Jun 26 05:17:43 PM PDT 24 65001567 ps
T2578 /workspace/coverage/default/38.usbdev_pkt_sent.2520432592 Jun 26 05:20:16 PM PDT 24 Jun 26 05:20:18 PM PDT 24 219318485 ps
T2579 /workspace/coverage/default/13.usbdev_min_length_in_transaction.195969796 Jun 26 05:15:13 PM PDT 24 Jun 26 05:15:15 PM PDT 24 156536662 ps
T2580 /workspace/coverage/default/32.usbdev_aon_wake_resume.3043546108 Jun 26 05:19:00 PM PDT 24 Jun 26 05:19:24 PM PDT 24 23394680275 ps
T2581 /workspace/coverage/default/16.usbdev_min_length_in_transaction.4020839346 Jun 26 05:15:53 PM PDT 24 Jun 26 05:15:55 PM PDT 24 146073953 ps
T2582 /workspace/coverage/default/4.usbdev_streaming_out.1660919911 Jun 26 05:12:16 PM PDT 24 Jun 26 05:14:34 PM PDT 24 5073905296 ps
T2583 /workspace/coverage/default/17.usbdev_setup_trans_ignored.580593065 Jun 26 05:16:10 PM PDT 24 Jun 26 05:16:12 PM PDT 24 180198195 ps
T268 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3256584084 Jun 26 04:43:20 PM PDT 24 Jun 26 04:43:25 PM PDT 24 188962726 ps
T202 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.402040127 Jun 26 04:43:16 PM PDT 24 Jun 26 04:43:21 PM PDT 24 111436125 ps
T228 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3685158445 Jun 26 04:43:23 PM PDT 24 Jun 26 04:43:30 PM PDT 24 83005253 ps
T203 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2094881187 Jun 26 04:43:21 PM PDT 24 Jun 26 04:43:27 PM PDT 24 118238961 ps
T210 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.2415784950 Jun 26 04:43:23 PM PDT 24 Jun 26 04:43:29 PM PDT 24 62232425 ps
T211 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.4071645281 Jun 26 04:43:43 PM PDT 24 Jun 26 04:43:51 PM PDT 24 86738824 ps
T213 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.1368076727 Jun 26 04:43:55 PM PDT 24 Jun 26 04:44:07 PM PDT 24 34060875 ps
T212 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2987568426 Jun 26 04:43:23 PM PDT 24 Jun 26 04:43:28 PM PDT 24 54172713 ps
T304 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1338171162 Jun 26 04:43:34 PM PDT 24 Jun 26 04:43:43 PM PDT 24 42956835 ps
T204 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1920092155 Jun 26 04:43:37 PM PDT 24 Jun 26 04:43:47 PM PDT 24 474431605 ps
T206 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3905922912 Jun 26 04:43:28 PM PDT 24 Jun 26 04:43:36 PM PDT 24 110460790 ps
T207 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.504291556 Jun 26 04:43:21 PM PDT 24 Jun 26 04:43:26 PM PDT 24 182608541 ps
T306 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.4069559209 Jun 26 04:43:43 PM PDT 24 Jun 26 04:43:50 PM PDT 24 56376929 ps
T2584 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2511784756 Jun 26 04:43:16 PM PDT 24 Jun 26 04:43:22 PM PDT 24 116877659 ps
T269 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.916611433 Jun 26 04:43:15 PM PDT 24 Jun 26 04:43:20 PM PDT 24 66861158 ps
T270 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3765002547 Jun 26 04:43:16 PM PDT 24 Jun 26 04:43:24 PM PDT 24 407594229 ps
T283 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3668192708 Jun 26 04:43:33 PM PDT 24 Jun 26 04:43:42 PM PDT 24 286111812 ps
T234 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3030694696 Jun 26 04:43:29 PM PDT 24 Jun 26 04:43:41 PM PDT 24 642480105 ps
T302 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3618188245 Jun 26 04:43:21 PM PDT 24 Jun 26 04:43:26 PM PDT 24 36822737 ps
T308 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.4292812736 Jun 26 04:43:37 PM PDT 24 Jun 26 04:43:45 PM PDT 24 41756685 ps
T305 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1812792343 Jun 26 04:43:30 PM PDT 24 Jun 26 04:43:38 PM PDT 24 68854470 ps
T227 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1864621062 Jun 26 04:43:22 PM PDT 24 Jun 26 04:43:28 PM PDT 24 181399015 ps
T235 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.4204225278 Jun 26 04:43:15 PM PDT 24 Jun 26 04:43:20 PM PDT 24 276771243 ps
T236 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3789564760 Jun 26 04:43:21 PM PDT 24 Jun 26 04:43:28 PM PDT 24 300090004 ps
T248 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2162322194 Jun 26 04:43:28 PM PDT 24 Jun 26 04:43:40 PM PDT 24 823288811 ps
T303 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2985559410 Jun 26 04:43:24 PM PDT 24 Jun 26 04:43:30 PM PDT 24 52983341 ps
T237 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.162333411 Jun 26 04:43:17 PM PDT 24 Jun 26 04:43:22 PM PDT 24 114661058 ps
T309 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.1028097206 Jun 26 04:43:48 PM PDT 24 Jun 26 04:43:56 PM PDT 24 41201079 ps
T311 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.1863041532 Jun 26 04:43:44 PM PDT 24 Jun 26 04:43:52 PM PDT 24 29246613 ps
T2585 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.814314775 Jun 26 04:43:14 PM PDT 24 Jun 26 04:43:22 PM PDT 24 719053641 ps
T2586 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1273608549 Jun 26 04:43:43 PM PDT 24 Jun 26 04:43:51 PM PDT 24 48467468 ps
T249 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.521963785 Jun 26 04:43:24 PM PDT 24 Jun 26 04:43:32 PM PDT 24 114663094 ps
T251 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2041995028 Jun 26 04:43:37 PM PDT 24 Jun 26 04:43:47 PM PDT 24 798823252 ps
T250 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1015599390 Jun 26 04:43:30 PM PDT 24 Jun 26 04:43:42 PM PDT 24 643601752 ps
T271 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2492078293 Jun 26 04:43:17 PM PDT 24 Jun 26 04:43:21 PM PDT 24 48116070 ps
T314 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.676256458 Jun 26 04:43:37 PM PDT 24 Jun 26 04:43:45 PM PDT 24 50013872 ps
T310 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1745472939 Jun 26 04:43:43 PM PDT 24 Jun 26 04:43:51 PM PDT 24 49154743 ps
T253 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1016449528 Jun 26 04:43:21 PM PDT 24 Jun 26 04:43:28 PM PDT 24 875640727 ps
T284 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.251169219 Jun 26 04:43:30 PM PDT 24 Jun 26 04:43:38 PM PDT 24 75366513 ps
T272 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3189425529 Jun 26 04:43:41 PM PDT 24 Jun 26 04:43:49 PM PDT 24 38634797 ps
T273 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.3218963272 Jun 26 04:43:22 PM PDT 24 Jun 26 04:43:27 PM PDT 24 47502664 ps
T241 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2884613472 Jun 26 04:43:29 PM PDT 24 Jun 26 04:43:38 PM PDT 24 230927921 ps
T285 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1583067075 Jun 26 04:43:39 PM PDT 24 Jun 26 04:43:48 PM PDT 24 50767474 ps
T315 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.134473268 Jun 26 04:43:33 PM PDT 24 Jun 26 04:43:41 PM PDT 24 64670679 ps
T2587 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1102075636 Jun 26 04:43:16 PM PDT 24 Jun 26 04:43:24 PM PDT 24 297820601 ps
T252 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3739735888 Jun 26 04:43:17 PM PDT 24 Jun 26 04:43:22 PM PDT 24 130698184 ps
T286 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1503516371 Jun 26 04:43:24 PM PDT 24 Jun 26 04:43:31 PM PDT 24 68604203 ps
T300 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3501684956 Jun 26 04:43:28 PM PDT 24 Jun 26 04:43:37 PM PDT 24 159687655 ps
T274 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3943647218 Jun 26 04:43:38 PM PDT 24 Jun 26 04:43:46 PM PDT 24 67301063 ps
T238 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1713446731 Jun 26 04:43:30 PM PDT 24 Jun 26 04:43:41 PM PDT 24 299161070 ps
T2588 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2790831624 Jun 26 04:43:39 PM PDT 24 Jun 26 04:43:47 PM PDT 24 66648077 ps
T301 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.252138641 Jun 26 04:43:41 PM PDT 24 Jun 26 04:43:49 PM PDT 24 144663454 ps
T275 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3211448875 Jun 26 04:43:16 PM PDT 24 Jun 26 04:43:22 PM PDT 24 168596713 ps
T325 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.2418742074 Jun 26 04:43:22 PM PDT 24 Jun 26 04:43:29 PM PDT 24 301341687 ps
T239 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1242522904 Jun 26 04:43:18 PM PDT 24 Jun 26 04:43:25 PM PDT 24 253742386 ps
T242 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1115820380 Jun 26 04:43:17 PM PDT 24 Jun 26 04:43:23 PM PDT 24 76689464 ps
T276 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1846311990 Jun 26 04:43:16 PM PDT 24 Jun 26 04:43:21 PM PDT 24 56108871 ps
T2589 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.359254761 Jun 26 04:43:15 PM PDT 24 Jun 26 04:43:21 PM PDT 24 164569675 ps
T2590 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3168494223 Jun 26 04:43:30 PM PDT 24 Jun 26 04:43:39 PM PDT 24 98293957 ps
T2591 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1884603790 Jun 26 04:43:36 PM PDT 24 Jun 26 04:43:45 PM PDT 24 174073209 ps
T2592 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3259078504 Jun 26 04:43:23 PM PDT 24 Jun 26 04:43:30 PM PDT 24 210915309 ps
T2593 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2216473856 Jun 26 04:43:28 PM PDT 24 Jun 26 04:43:38 PM PDT 24 301574004 ps
T2594 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2951029639 Jun 26 04:43:23 PM PDT 24 Jun 26 04:43:30 PM PDT 24 79222855 ps
T312 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3857436194 Jun 26 04:43:41 PM PDT 24 Jun 26 04:43:48 PM PDT 24 31622830 ps
T2595 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2351361380 Jun 26 04:43:17 PM PDT 24 Jun 26 04:43:25 PM PDT 24 479656651 ps
T277 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3034006047 Jun 26 04:43:16 PM PDT 24 Jun 26 04:43:21 PM PDT 24 121951570 ps
T2596 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2288917150 Jun 26 04:43:21 PM PDT 24 Jun 26 04:43:26 PM PDT 24 125677287 ps
T2597 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1774833343 Jun 26 04:43:43 PM PDT 24 Jun 26 04:43:51 PM PDT 24 41043847 ps
T321 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.453233720 Jun 26 04:43:24 PM PDT 24 Jun 26 04:43:32 PM PDT 24 519769041 ps
T316 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1006779690 Jun 26 04:43:42 PM PDT 24 Jun 26 04:43:49 PM PDT 24 39515518 ps
T278 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.96495945 Jun 26 04:43:15 PM PDT 24 Jun 26 04:43:20 PM PDT 24 200472106 ps
T2598 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1526308541 Jun 26 04:43:15 PM PDT 24 Jun 26 04:43:20 PM PDT 24 175095977 ps
T2599 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1587896610 Jun 26 04:43:39 PM PDT 24 Jun 26 04:43:48 PM PDT 24 172773915 ps
T319 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1507514013 Jun 26 04:43:17 PM PDT 24 Jun 26 04:43:25 PM PDT 24 856807817 ps
T313 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.4212001251 Jun 26 04:43:43 PM PDT 24 Jun 26 04:43:51 PM PDT 24 48948159 ps
T2600 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2804387920 Jun 26 04:43:42 PM PDT 24 Jun 26 04:43:50 PM PDT 24 48951235 ps
T2601 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3346801392 Jun 26 04:43:36 PM PDT 24 Jun 26 04:43:45 PM PDT 24 163094165 ps
T2602 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.618346432 Jun 26 04:43:15 PM PDT 24 Jun 26 04:43:26 PM PDT 24 1254598240 ps
T2603 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2109215731 Jun 26 04:43:37 PM PDT 24 Jun 26 04:43:45 PM PDT 24 90233860 ps
T2604 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1657647847 Jun 26 04:43:15 PM PDT 24 Jun 26 04:43:20 PM PDT 24 208187813 ps
T240 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1410918850 Jun 26 04:43:22 PM PDT 24 Jun 26 04:43:29 PM PDT 24 59177225 ps
T279 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.325313803 Jun 26 04:43:37 PM PDT 24 Jun 26 04:43:45 PM PDT 24 55776506 ps
T322 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2098760487 Jun 26 04:43:41 PM PDT 24 Jun 26 04:43:53 PM PDT 24 744933888 ps
T2605 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.1624116663 Jun 26 04:43:29 PM PDT 24 Jun 26 04:43:37 PM PDT 24 36955201 ps
T2606 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.759982617 Jun 26 04:43:17 PM PDT 24 Jun 26 04:43:22 PM PDT 24 86216048 ps
T280 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.305227180 Jun 26 04:43:14 PM PDT 24 Jun 26 04:43:20 PM PDT 24 119101456 ps
T281 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.587741059 Jun 26 04:43:21 PM PDT 24 Jun 26 04:43:25 PM PDT 24 99888729 ps
T2607 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3449434740 Jun 26 04:43:33 PM PDT 24 Jun 26 04:43:42 PM PDT 24 260010004 ps
T2608 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.4121918777 Jun 26 04:43:16 PM PDT 24 Jun 26 04:43:22 PM PDT 24 121827831 ps
T2609 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3308517060 Jun 26 04:43:28 PM PDT 24 Jun 26 04:43:36 PM PDT 24 89081852 ps
T2610 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.239602236 Jun 26 04:43:41 PM PDT 24 Jun 26 04:43:49 PM PDT 24 41634765 ps
T2611 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.845957612 Jun 26 04:43:40 PM PDT 24 Jun 26 04:43:48 PM PDT 24 35268303 ps
T243 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1549350528 Jun 26 04:43:23 PM PDT 24 Jun 26 04:43:30 PM PDT 24 255344005 ps
T2612 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3655731736 Jun 26 04:43:16 PM PDT 24 Jun 26 04:43:21 PM PDT 24 76177519 ps
T282 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1144143788 Jun 26 04:43:22 PM PDT 24 Jun 26 04:43:29 PM PDT 24 135091089 ps
T2613 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1460184736 Jun 26 04:43:21 PM PDT 24 Jun 26 04:43:32 PM PDT 24 730268119 ps
T2614 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.180025056 Jun 26 04:43:22 PM PDT 24 Jun 26 04:43:27 PM PDT 24 161429016 ps
T2615 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.1780761681 Jun 26 04:43:49 PM PDT 24 Jun 26 04:43:57 PM PDT 24 38489330 ps
T2616 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3807739714 Jun 26 04:43:16 PM PDT 24 Jun 26 04:43:21 PM PDT 24 66736175 ps
T2617 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2438400574 Jun 26 04:43:24 PM PDT 24 Jun 26 04:43:31 PM PDT 24 55733482 ps
T2618 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.843960356 Jun 26 04:43:42 PM PDT 24 Jun 26 04:43:50 PM PDT 24 83706996 ps
T2619 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1621317486 Jun 26 04:43:37 PM PDT 24 Jun 26 04:43:46 PM PDT 24 175094956 ps
T317 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1948492215 Jun 26 04:43:22 PM PDT 24 Jun 26 04:43:31 PM PDT 24 908680622 ps
T2620 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2383406692 Jun 26 04:43:17 PM PDT 24 Jun 26 04:43:24 PM PDT 24 113628467 ps
T2621 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1160540984 Jun 26 04:43:23 PM PDT 24 Jun 26 04:43:28 PM PDT 24 70024428 ps
T2622 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3473724766 Jun 26 04:43:44 PM PDT 24 Jun 26 04:43:52 PM PDT 24 59518297 ps
T2623 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3676358737 Jun 26 04:43:15 PM PDT 24 Jun 26 04:43:18 PM PDT 24 48133883 ps
T2624 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.447316589 Jun 26 04:43:22 PM PDT 24 Jun 26 04:43:27 PM PDT 24 73246931 ps
T2625 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3025012665 Jun 26 04:43:44 PM PDT 24 Jun 26 04:43:52 PM PDT 24 47749410 ps
T318 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2147394164 Jun 26 04:43:16 PM PDT 24 Jun 26 04:43:24 PM PDT 24 1037188189 ps
T2626 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3016851144 Jun 26 04:43:23 PM PDT 24 Jun 26 04:43:30 PM PDT 24 163005342 ps
T2627 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3354569811 Jun 26 04:43:14 PM PDT 24 Jun 26 04:43:18 PM PDT 24 57834955 ps
T2628 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.901200842 Jun 26 04:43:13 PM PDT 24 Jun 26 04:43:16 PM PDT 24 199299482 ps
T2629 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2161345126 Jun 26 04:43:40 PM PDT 24 Jun 26 04:43:48 PM PDT 24 76222039 ps
T2630 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2262758525 Jun 26 04:43:34 PM PDT 24 Jun 26 04:43:43 PM PDT 24 71989200 ps
T2631 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.4143863394 Jun 26 04:43:55 PM PDT 24 Jun 26 04:44:07 PM PDT 24 52017955 ps
T2632 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1559208739 Jun 26 04:43:36 PM PDT 24 Jun 26 04:43:46 PM PDT 24 111248168 ps
T2633 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2182436390 Jun 26 04:43:29 PM PDT 24 Jun 26 04:43:36 PM PDT 24 37771349 ps
T2634 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2747340995 Jun 26 04:43:15 PM PDT 24 Jun 26 04:43:23 PM PDT 24 527092371 ps
T2635 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2220835806 Jun 26 04:43:23 PM PDT 24 Jun 26 04:43:28 PM PDT 24 44922636 ps
T2636 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1409664082 Jun 26 04:43:17 PM PDT 24 Jun 26 04:43:22 PM PDT 24 70571508 ps
T2637 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3340609476 Jun 26 04:43:23 PM PDT 24 Jun 26 04:43:31 PM PDT 24 151219216 ps
T2638 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1895521120 Jun 26 04:43:22 PM PDT 24 Jun 26 04:43:28 PM PDT 24 134640669 ps
T2639 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.595414251 Jun 26 04:43:42 PM PDT 24 Jun 26 04:43:49 PM PDT 24 66613138 ps
T2640 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1003202054 Jun 26 04:43:39 PM PDT 24 Jun 26 04:43:48 PM PDT 24 98125189 ps
T2641 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2082344878 Jun 26 04:43:43 PM PDT 24 Jun 26 04:43:51 PM PDT 24 49778185 ps
T2642 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2802054381 Jun 26 04:43:16 PM PDT 24 Jun 26 04:43:20 PM PDT 24 48191858 ps
T2643 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3489402519 Jun 26 04:43:37 PM PDT 24 Jun 26 04:43:45 PM PDT 24 32892995 ps
T2644 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3000786563 Jun 26 04:43:23 PM PDT 24 Jun 26 04:43:31 PM PDT 24 252941912 ps
T244 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1401262769 Jun 26 04:43:33 PM PDT 24 Jun 26 04:43:46 PM PDT 24 1431684097 ps
T2645 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.441718393 Jun 26 04:43:43 PM PDT 24 Jun 26 04:43:50 PM PDT 24 38233697 ps
T2646 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1732688690 Jun 26 04:43:16 PM PDT 24 Jun 26 04:43:21 PM PDT 24 150842862 ps
T2647 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1747620386 Jun 26 04:43:39 PM PDT 24 Jun 26 04:43:48 PM PDT 24 65095607 ps
T2648 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1964565841 Jun 26 04:43:38 PM PDT 24 Jun 26 04:43:47 PM PDT 24 216025156 ps
T2649 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2713407566 Jun 26 04:43:30 PM PDT 24 Jun 26 04:43:38 PM PDT 24 37545131 ps
T2650 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.86033224 Jun 26 04:43:43 PM PDT 24 Jun 26 04:43:50 PM PDT 24 63637785 ps
T320 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.368441170 Jun 26 04:43:15 PM PDT 24 Jun 26 04:43:22 PM PDT 24 539999549 ps
T2651 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3361844756 Jun 26 04:43:17 PM PDT 24 Jun 26 04:43:21 PM PDT 24 77981448 ps
T2652 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.4250247209 Jun 26 04:43:35 PM PDT 24 Jun 26 04:43:44 PM PDT 24 57251480 ps
T324 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2994864424 Jun 26 04:43:37 PM PDT 24 Jun 26 04:43:49 PM PDT 24 516009684 ps
T323 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3103941917 Jun 26 04:43:36 PM PDT 24 Jun 26 04:43:48 PM PDT 24 1002355242 ps
T2653 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.640178480 Jun 26 04:43:37 PM PDT 24 Jun 26 04:43:47 PM PDT 24 144103794 ps
T2654 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3763758594 Jun 26 04:43:36 PM PDT 24 Jun 26 04:43:44 PM PDT 24 35923680 ps
T2655 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1377554262 Jun 26 04:43:55 PM PDT 24 Jun 26 04:44:07 PM PDT 24 37180571 ps
T2656 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3807597419 Jun 26 04:43:35 PM PDT 24 Jun 26 04:43:44 PM PDT 24 117410985 ps
T2657 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1326418103 Jun 26 04:43:23 PM PDT 24 Jun 26 04:43:30 PM PDT 24 265614940 ps
T2658 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.85990711 Jun 26 04:43:26 PM PDT 24 Jun 26 04:43:34 PM PDT 24 140329239 ps
T2659 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2545418989 Jun 26 04:43:43 PM PDT 24 Jun 26 04:43:51 PM PDT 24 39555416 ps
T2660 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1337136006 Jun 26 04:43:21 PM PDT 24 Jun 26 04:43:28 PM PDT 24 555554230 ps
T2661 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1683879504 Jun 26 04:43:30 PM PDT 24 Jun 26 04:43:38 PM PDT 24 73192664 ps
T2662 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3999010138 Jun 26 04:43:29 PM PDT 24 Jun 26 04:43:36 PM PDT 24 62679449 ps
T2663 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1192338681 Jun 26 04:43:25 PM PDT 24 Jun 26 04:43:34 PM PDT 24 174412780 ps
T2664 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2312660817 Jun 26 04:43:15 PM PDT 24 Jun 26 04:43:19 PM PDT 24 155526089 ps
T2665 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2663186677 Jun 26 04:43:44 PM PDT 24 Jun 26 04:43:51 PM PDT 24 84174953 ps
T2666 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2819135685 Jun 26 04:43:23 PM PDT 24 Jun 26 04:43:30 PM PDT 24 175708444 ps
T2667 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1299637968 Jun 26 04:43:24 PM PDT 24 Jun 26 04:43:31 PM PDT 24 136822342 ps
T2668 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2442621922 Jun 26 04:43:42 PM PDT 24 Jun 26 04:43:49 PM PDT 24 95284054 ps
T2669 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3357525475 Jun 26 04:43:29 PM PDT 24 Jun 26 04:43:38 PM PDT 24 171620162 ps
T2670 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1476951750 Jun 26 04:43:17 PM PDT 24 Jun 26 04:43:23 PM PDT 24 462909467 ps
T2671 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2018085425 Jun 26 04:43:23 PM PDT 24 Jun 26 04:43:34 PM PDT 24 797817213 ps
T2672 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1873363088 Jun 26 04:43:39 PM PDT 24 Jun 26 04:43:48 PM PDT 24 132044324 ps
T2673 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3747029805 Jun 26 04:43:37 PM PDT 24 Jun 26 04:43:46 PM PDT 24 105199310 ps
T2674 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1077379830 Jun 26 04:43:28 PM PDT 24 Jun 26 04:43:37 PM PDT 24 234103984 ps
T2675 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.4059461706 Jun 26 04:43:34 PM PDT 24 Jun 26 04:43:43 PM PDT 24 187906308 ps
T2676 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1224658490 Jun 26 04:43:29 PM PDT 24 Jun 26 04:43:37 PM PDT 24 117656809 ps
T2677 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2258652298 Jun 26 04:43:14 PM PDT 24 Jun 26 04:43:18 PM PDT 24 140383333 ps
T2678 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.4242855453 Jun 26 04:43:24 PM PDT 24 Jun 26 04:43:30 PM PDT 24 34437498 ps
T2679 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3762997664 Jun 26 04:43:43 PM PDT 24 Jun 26 04:43:51 PM PDT 24 123323594 ps
T2680 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1912959962 Jun 26 04:43:22 PM PDT 24 Jun 26 04:43:27 PM PDT 24 71166031 ps
T2681 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.45146576 Jun 26 04:43:36 PM PDT 24 Jun 26 04:43:45 PM PDT 24 114536156 ps
T2682 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1629962841 Jun 26 04:43:13 PM PDT 24 Jun 26 04:43:16 PM PDT 24 104283490 ps
T2683 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3713203846 Jun 26 04:43:37 PM PDT 24 Jun 26 04:43:46 PM PDT 24 66988676 ps
T2684 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.707697039 Jun 26 04:43:31 PM PDT 24 Jun 26 04:43:39 PM PDT 24 247312341 ps
T2685 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2861676505 Jun 26 04:43:18 PM PDT 24 Jun 26 04:43:24 PM PDT 24 155774989 ps
T2686 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3348776516 Jun 26 04:43:27 PM PDT 24 Jun 26 04:43:36 PM PDT 24 281792454 ps

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.2313726629
Short name T5
Test name
Test status
Simulation time 9553227625 ps
CPU time 73.25 seconds
Started Jun 26 05:16:14 PM PDT 24
Finished Jun 26 05:17:29 PM PDT 24
Peak memory 206564 kb
Host smart-6758b149-3f5d-431c-8e7c-a27b1793b4a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23137
26629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.2313726629
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.653824320
Short name T3
Test name
Test status
Simulation time 23330779553 ps
CPU time 22.96 seconds
Started Jun 26 05:17:00 PM PDT 24
Finished Jun 26 05:17:27 PM PDT 24
Peak memory 206488 kb
Host smart-18921a01-d464-42e1-b555-86249df474a6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=653824320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.653824320
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.4071645281
Short name T211
Test name
Test status
Simulation time 86738824 ps
CPU time 0.75 seconds
Started Jun 26 04:43:43 PM PDT 24
Finished Jun 26 04:43:51 PM PDT 24
Peak memory 205816 kb
Host smart-2f958e11-fe73-4f36-943d-d692e7967565
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4071645281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.4071645281
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.2221214168
Short name T19
Test name
Test status
Simulation time 190615509 ps
CPU time 0.86 seconds
Started Jun 26 05:21:10 PM PDT 24
Finished Jun 26 05:21:15 PM PDT 24
Peak memory 206140 kb
Host smart-8465ce74-bd05-45e1-936d-0e6a6f9aded4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22212
14168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.2221214168
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1920092155
Short name T204
Test name
Test status
Simulation time 474431605 ps
CPU time 2.8 seconds
Started Jun 26 04:43:37 PM PDT 24
Finished Jun 26 04:43:47 PM PDT 24
Peak memory 206160 kb
Host smart-0207e985-ccb9-410d-9487-54faf8b54765
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1920092155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.1920092155
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.2405684239
Short name T6
Test name
Test status
Simulation time 5058016873 ps
CPU time 143.36 seconds
Started Jun 26 05:20:21 PM PDT 24
Finished Jun 26 05:22:49 PM PDT 24
Peak memory 206548 kb
Host smart-a18d1c74-823d-4d2a-adda-b8e082c3dd5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24056
84239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.2405684239
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2985559410
Short name T303
Test name
Test status
Simulation time 52983341 ps
CPU time 0.74 seconds
Started Jun 26 04:43:24 PM PDT 24
Finished Jun 26 04:43:30 PM PDT 24
Peak memory 205792 kb
Host smart-28b567d1-faaf-431d-addc-d16db88e6d6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2985559410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.2985559410
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.2735844432
Short name T150
Test name
Test status
Simulation time 221020418 ps
CPU time 0.84 seconds
Started Jun 26 05:21:01 PM PDT 24
Finished Jun 26 05:21:08 PM PDT 24
Peak memory 206180 kb
Host smart-eda09887-420b-47ca-9935-7140fca6e7a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27358
44432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.2735844432
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3789564760
Short name T236
Test name
Test status
Simulation time 300090004 ps
CPU time 3.02 seconds
Started Jun 26 04:43:21 PM PDT 24
Finished Jun 26 04:43:28 PM PDT 24
Peak memory 214444 kb
Host smart-ae066131-9395-49d3-8e8a-d8371a669fdb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3789564760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.3789564760
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/default/6.usbdev_device_address.165468742
Short name T90
Test name
Test status
Simulation time 16161768680 ps
CPU time 30.12 seconds
Started Jun 26 05:12:47 PM PDT 24
Finished Jun 26 05:13:19 PM PDT 24
Peak memory 206596 kb
Host smart-40cd6a95-dbaf-47af-92f7-749b0b0b624e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16546
8742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.165468742
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.2343407098
Short name T399
Test name
Test status
Simulation time 203587957 ps
CPU time 0.92 seconds
Started Jun 26 05:10:40 PM PDT 24
Finished Jun 26 05:10:42 PM PDT 24
Peak memory 206224 kb
Host smart-7ffc045d-715f-42cc-98cf-1d01a6a7baab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23434
07098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.2343407098
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.3553672975
Short name T36
Test name
Test status
Simulation time 149050901 ps
CPU time 0.79 seconds
Started Jun 26 05:16:40 PM PDT 24
Finished Jun 26 05:16:42 PM PDT 24
Peak memory 206112 kb
Host smart-08607597-fb8c-44e3-84e3-c225ce2f1b28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35536
72975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.3553672975
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.4247011999
Short name T111
Test name
Test status
Simulation time 409504181 ps
CPU time 1.21 seconds
Started Jun 26 05:15:43 PM PDT 24
Finished Jun 26 05:15:46 PM PDT 24
Peak memory 206096 kb
Host smart-f576d8a9-8a5b-4124-810a-6081b1372da2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42470
11999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.4247011999
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.941403821
Short name T11
Test name
Test status
Simulation time 3805823267 ps
CPU time 4.41 seconds
Started Jun 26 05:14:09 PM PDT 24
Finished Jun 26 05:14:16 PM PDT 24
Peak memory 206244 kb
Host smart-4643cd5f-fe05-44ae-bf31-72c3710c221e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=941403821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.941403821
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.1892102238
Short name T28
Test name
Test status
Simulation time 42348138 ps
CPU time 0.65 seconds
Started Jun 26 05:14:22 PM PDT 24
Finished Jun 26 05:14:25 PM PDT 24
Peak memory 206132 kb
Host smart-45994583-3465-4eec-bb9e-cc01e0d63283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18921
02238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.1892102238
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.2146743521
Short name T66
Test name
Test status
Simulation time 184759822 ps
CPU time 0.82 seconds
Started Jun 26 05:14:21 PM PDT 24
Finished Jun 26 05:14:24 PM PDT 24
Peak memory 206208 kb
Host smart-1313b85e-faeb-48df-9704-72e805a30093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21467
43521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.2146743521
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1812792343
Short name T305
Test name
Test status
Simulation time 68854470 ps
CPU time 0.72 seconds
Started Jun 26 04:43:30 PM PDT 24
Finished Jun 26 04:43:38 PM PDT 24
Peak memory 205820 kb
Host smart-a9948dcc-1a15-4697-b783-ae6f48117273
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1812792343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.1812792343
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.2677445994
Short name T201
Test name
Test status
Simulation time 444684291 ps
CPU time 1.34 seconds
Started Jun 26 05:10:12 PM PDT 24
Finished Jun 26 05:10:14 PM PDT 24
Peak memory 225012 kb
Host smart-7d6da14a-821f-4623-8b86-bcdc2e433d94
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2677445994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.2677445994
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.2673095760
Short name T73
Test name
Test status
Simulation time 303830973 ps
CPU time 1.06 seconds
Started Jun 26 05:09:41 PM PDT 24
Finished Jun 26 05:09:43 PM PDT 24
Peak memory 206436 kb
Host smart-32053582-3bdc-465d-95f7-d0e1b3e897e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26730
95760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.2673095760
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.827542248
Short name T38
Test name
Test status
Simulation time 20166242412 ps
CPU time 21.05 seconds
Started Jun 26 05:09:55 PM PDT 24
Finished Jun 26 05:10:17 PM PDT 24
Peak memory 206312 kb
Host smart-faf2ce54-41c4-4299-a156-0c8aeaf43e97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82754
2248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.827542248
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.2929796293
Short name T98
Test name
Test status
Simulation time 12060015453 ps
CPU time 209.95 seconds
Started Jun 26 05:10:37 PM PDT 24
Finished Jun 26 05:14:08 PM PDT 24
Peak memory 206432 kb
Host smart-38988bc5-9d4e-477b-9b0e-aa0602d046a3
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2929796293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.2929796293
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3943647218
Short name T274
Test name
Test status
Simulation time 67301063 ps
CPU time 1.01 seconds
Started Jun 26 04:43:38 PM PDT 24
Finished Jun 26 04:43:46 PM PDT 24
Peak memory 205996 kb
Host smart-95d90148-3489-4082-aadb-cc94f82a89a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3943647218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.3943647218
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.4179969350
Short name T104
Test name
Test status
Simulation time 758438603 ps
CPU time 2.07 seconds
Started Jun 26 05:11:54 PM PDT 24
Finished Jun 26 05:11:58 PM PDT 24
Peak memory 206428 kb
Host smart-61624574-51c8-4b3f-bb1e-393dd4d34606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41799
69350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.4179969350
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.672056014
Short name T43
Test name
Test status
Simulation time 187253572 ps
CPU time 0.81 seconds
Started Jun 26 05:14:42 PM PDT 24
Finished Jun 26 05:14:44 PM PDT 24
Peak memory 206212 kb
Host smart-00a15437-a33a-46fa-b19e-4f1bbc0eff4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67205
6014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.672056014
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2804387920
Short name T2600
Test name
Test status
Simulation time 48951235 ps
CPU time 0.7 seconds
Started Jun 26 04:43:42 PM PDT 24
Finished Jun 26 04:43:50 PM PDT 24
Peak memory 205788 kb
Host smart-4b869fa5-c0c7-40a1-9397-be284ff9abab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2804387920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.2804387920
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1948492215
Short name T317
Test name
Test status
Simulation time 908680622 ps
CPU time 5.38 seconds
Started Jun 26 04:43:22 PM PDT 24
Finished Jun 26 04:43:31 PM PDT 24
Peak memory 206224 kb
Host smart-c3fc4045-6690-4fba-a9ff-f8bab4565d49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1948492215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.1948492215
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3676358737
Short name T2623
Test name
Test status
Simulation time 48133883 ps
CPU time 0.65 seconds
Started Jun 26 04:43:15 PM PDT 24
Finished Jun 26 04:43:18 PM PDT 24
Peak memory 205792 kb
Host smart-f5f85846-dfb4-4935-87a4-74f78ce67dc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3676358737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.3676358737
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.4220697991
Short name T63
Test name
Test status
Simulation time 473875534 ps
CPU time 1.29 seconds
Started Jun 26 05:09:33 PM PDT 24
Finished Jun 26 05:09:35 PM PDT 24
Peak memory 206228 kb
Host smart-85d98571-ae0d-4c0e-8c81-71be5ffa7329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42206
97991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.4220697991
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.3460855118
Short name T196
Test name
Test status
Simulation time 13448074210 ps
CPU time 15.78 seconds
Started Jun 26 05:15:18 PM PDT 24
Finished Jun 26 05:15:34 PM PDT 24
Peak memory 206700 kb
Host smart-df705038-d311-43f9-a599-50e5ef312d14
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3460855118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.3460855118
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3103941917
Short name T323
Test name
Test status
Simulation time 1002355242 ps
CPU time 5.1 seconds
Started Jun 26 04:43:36 PM PDT 24
Finished Jun 26 04:43:48 PM PDT 24
Peak memory 206132 kb
Host smart-6c324973-f52c-42fa-9a5d-b209ba0d11da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3103941917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.3103941917
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.3666062441
Short name T186
Test name
Test status
Simulation time 14092361174 ps
CPU time 107.62 seconds
Started Jun 26 05:11:03 PM PDT 24
Finished Jun 26 05:12:52 PM PDT 24
Peak memory 206436 kb
Host smart-88a02954-f9fb-4413-9f5c-ac3a688250b3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3666062441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.3666062441
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1713446731
Short name T238
Test name
Test status
Simulation time 299161070 ps
CPU time 3.17 seconds
Started Jun 26 04:43:30 PM PDT 24
Finished Jun 26 04:43:41 PM PDT 24
Peak memory 222260 kb
Host smart-3b51507e-939e-453c-b5de-a34fddfa7905
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1713446731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.1713446731
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.743652980
Short name T46
Test name
Test status
Simulation time 396397089 ps
CPU time 1.27 seconds
Started Jun 26 05:10:33 PM PDT 24
Finished Jun 26 05:10:35 PM PDT 24
Peak memory 206204 kb
Host smart-7bdc5e76-323d-4cde-9631-992c06d7a217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74365
2980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.743652980
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.3377366457
Short name T58
Test name
Test status
Simulation time 135988259 ps
CPU time 0.76 seconds
Started Jun 26 05:09:17 PM PDT 24
Finished Jun 26 05:09:19 PM PDT 24
Peak memory 206204 kb
Host smart-db8dedb0-2d7d-4a44-8e50-9df1d0d81949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33773
66457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.3377366457
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2802054381
Short name T2642
Test name
Test status
Simulation time 48191858 ps
CPU time 0.69 seconds
Started Jun 26 04:43:16 PM PDT 24
Finished Jun 26 04:43:20 PM PDT 24
Peak memory 205816 kb
Host smart-4de1c984-33de-45ae-abd6-5981945dea45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2802054381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.2802054381
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3030694696
Short name T234
Test name
Test status
Simulation time 642480105 ps
CPU time 4.54 seconds
Started Jun 26 04:43:29 PM PDT 24
Finished Jun 26 04:43:41 PM PDT 24
Peak memory 206164 kb
Host smart-7689f09f-9f0e-42f6-9cd0-9a9520725b68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3030694696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.3030694696
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.1228796179
Short name T844
Test name
Test status
Simulation time 1393344859 ps
CPU time 2.98 seconds
Started Jun 26 05:20:40 PM PDT 24
Finished Jun 26 05:20:44 PM PDT 24
Peak memory 206452 kb
Host smart-e9f74026-e525-41fb-af9d-8beb2d30fdd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12287
96179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.1228796179
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_invalid_sync.411808903
Short name T92
Test name
Test status
Simulation time 9045097648 ps
CPU time 246.48 seconds
Started Jun 26 05:19:33 PM PDT 24
Finished Jun 26 05:23:42 PM PDT 24
Peak memory 206404 kb
Host smart-4659ecac-0fde-4a50-9bce-8701b72b83ad
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=411808903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.411808903
Directory /workspace/34.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.4136808944
Short name T152
Test name
Test status
Simulation time 877659178 ps
CPU time 2.04 seconds
Started Jun 26 05:10:17 PM PDT 24
Finished Jun 26 05:10:20 PM PDT 24
Peak memory 206436 kb
Host smart-56fe9e2a-4c08-49c9-971a-de15d067f5a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41368
08944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.4136808944
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.3964215425
Short name T818
Test name
Test status
Simulation time 39056213 ps
CPU time 0.66 seconds
Started Jun 26 05:15:27 PM PDT 24
Finished Jun 26 05:15:28 PM PDT 24
Peak memory 206096 kb
Host smart-ac22e379-9795-403c-b9dc-02d4a7a4cf10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39642
15425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.3964215425
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.3018217593
Short name T528
Test name
Test status
Simulation time 178643240 ps
CPU time 0.83 seconds
Started Jun 26 05:09:49 PM PDT 24
Finished Jun 26 05:09:50 PM PDT 24
Peak memory 206228 kb
Host smart-2f7897c7-fcff-4d18-b5fe-0112280550fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30182
17593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.3018217593
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.3356513001
Short name T126
Test name
Test status
Simulation time 235223627 ps
CPU time 0.91 seconds
Started Jun 26 05:14:52 PM PDT 24
Finished Jun 26 05:14:53 PM PDT 24
Peak memory 206124 kb
Host smart-764a82fc-0c9e-4062-9c54-f9206cc94fe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33565
13001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.3356513001
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.4092494559
Short name T84
Test name
Test status
Simulation time 139039477 ps
CPU time 0.78 seconds
Started Jun 26 05:10:11 PM PDT 24
Finished Jun 26 05:10:13 PM PDT 24
Peak memory 206204 kb
Host smart-0e411371-7780-40d3-842e-e3769378d086
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40924
94559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.4092494559
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.23368055
Short name T195
Test name
Test status
Simulation time 345249364 ps
CPU time 1.97 seconds
Started Jun 26 05:14:31 PM PDT 24
Finished Jun 26 05:14:34 PM PDT 24
Peak memory 206392 kb
Host smart-f12f2fec-226e-4fc2-864e-78e8884b2061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23368
055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.23368055
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_device_address.1828840737
Short name T94
Test name
Test status
Simulation time 18267035422 ps
CPU time 34.54 seconds
Started Jun 26 05:17:01 PM PDT 24
Finished Jun 26 05:17:39 PM PDT 24
Peak memory 206484 kb
Host smart-dc5282e4-7979-4ada-a3d9-2fc8ad883264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18288
40737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.1828840737
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.249456200
Short name T44
Test name
Test status
Simulation time 169700029 ps
CPU time 0.82 seconds
Started Jun 26 05:09:17 PM PDT 24
Finished Jun 26 05:09:19 PM PDT 24
Peak memory 206400 kb
Host smart-17a6c266-1c41-49e7-8020-fbb63d429504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24945
6200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.249456200
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.3898141901
Short name T60
Test name
Test status
Simulation time 4246681841 ps
CPU time 10.22 seconds
Started Jun 26 05:09:34 PM PDT 24
Finished Jun 26 05:09:45 PM PDT 24
Peak memory 206416 kb
Host smart-673bc8e2-19d0-43ee-aaf9-8d8a0144cde4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38981
41901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.3898141901
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.2190207178
Short name T61
Test name
Test status
Simulation time 209025107 ps
CPU time 0.82 seconds
Started Jun 26 05:09:33 PM PDT 24
Finished Jun 26 05:09:35 PM PDT 24
Peak memory 206172 kb
Host smart-910ac58b-e635-448c-8f85-3cba563fedbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21902
07178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.2190207178
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.4255867274
Short name T49
Test name
Test status
Simulation time 253126231 ps
CPU time 0.98 seconds
Started Jun 26 05:09:56 PM PDT 24
Finished Jun 26 05:09:58 PM PDT 24
Peak memory 206188 kb
Host smart-4c8dce77-b662-469c-b54d-b1c54cdce696
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42558
67274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.4255867274
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.1133408283
Short name T70
Test name
Test status
Simulation time 224936380 ps
CPU time 0.88 seconds
Started Jun 26 05:09:58 PM PDT 24
Finished Jun 26 05:09:59 PM PDT 24
Peak memory 206100 kb
Host smart-359315e4-8c48-4a11-8513-55068bdf979d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11334
08283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.1133408283
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.4140227883
Short name T50
Test name
Test status
Simulation time 180395767 ps
CPU time 0.84 seconds
Started Jun 26 05:10:12 PM PDT 24
Finished Jun 26 05:10:14 PM PDT 24
Peak memory 206112 kb
Host smart-d75be436-006d-4acb-9b67-1e5c685b321e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41402
27883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.4140227883
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.2940062001
Short name T170
Test name
Test status
Simulation time 1403900739 ps
CPU time 3.16 seconds
Started Jun 26 05:14:27 PM PDT 24
Finished Jun 26 05:14:31 PM PDT 24
Peak memory 206380 kb
Host smart-9c624b1f-30ee-46f2-871b-7a373e22aefc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29400
62001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.2940062001
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1242522904
Short name T239
Test name
Test status
Simulation time 253742386 ps
CPU time 3.32 seconds
Started Jun 26 04:43:18 PM PDT 24
Finished Jun 26 04:43:25 PM PDT 24
Peak memory 214324 kb
Host smart-e5014429-d887-47b9-9850-e8f3308d991f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1242522904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.1242522904
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1401262769
Short name T244
Test name
Test status
Simulation time 1431684097 ps
CPU time 5.68 seconds
Started Jun 26 04:43:33 PM PDT 24
Finished Jun 26 04:43:46 PM PDT 24
Peak memory 206088 kb
Host smart-ae9004b7-01b4-43dc-91bb-6dc0f95939b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1401262769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.1401262769
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.1826288343
Short name T131
Test name
Test status
Simulation time 273751428 ps
CPU time 0.91 seconds
Started Jun 26 05:09:40 PM PDT 24
Finished Jun 26 05:09:42 PM PDT 24
Peak memory 206176 kb
Host smart-115851c4-0f72-4488-a9dc-b27765e8654a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18262
88343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.1826288343
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.3469799494
Short name T231
Test name
Test status
Simulation time 263484856 ps
CPU time 1.03 seconds
Started Jun 26 05:09:48 PM PDT 24
Finished Jun 26 05:09:49 PM PDT 24
Peak memory 206208 kb
Host smart-64022041-7849-4e85-8b3c-2651345b1fcc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3469799494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.3469799494
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.4209267474
Short name T1831
Test name
Test status
Simulation time 10343272419 ps
CPU time 49.02 seconds
Started Jun 26 05:10:04 PM PDT 24
Finished Jun 26 05:10:54 PM PDT 24
Peak memory 206532 kb
Host smart-d2768e9c-36ee-4b3b-a421-4d1e2d3f36fb
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4209267474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.4209267474
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.2498019019
Short name T87
Test name
Test status
Simulation time 17039425899 ps
CPU time 44.2 seconds
Started Jun 26 05:14:21 PM PDT 24
Finished Jun 26 05:15:07 PM PDT 24
Peak memory 206568 kb
Host smart-886a22d0-66bd-46b6-902f-2c5106c28053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24980
19019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.2498019019
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_invalid_sync.3014016952
Short name T226
Test name
Test status
Simulation time 5403336118 ps
CPU time 38.3 seconds
Started Jun 26 05:14:46 PM PDT 24
Finished Jun 26 05:15:25 PM PDT 24
Peak memory 206572 kb
Host smart-d9c48c4a-1b8f-4741-9f13-f290987cf652
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3014016952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.3014016952
Directory /workspace/12.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.1598180230
Short name T2058
Test name
Test status
Simulation time 218149774 ps
CPU time 0.87 seconds
Started Jun 26 05:15:06 PM PDT 24
Finished Jun 26 05:15:08 PM PDT 24
Peak memory 206132 kb
Host smart-bcc94c47-c2e2-4232-8a4a-f962d7417c56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15981
80230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.1598180230
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.910404841
Short name T143
Test name
Test status
Simulation time 241584825 ps
CPU time 0.89 seconds
Started Jun 26 05:15:20 PM PDT 24
Finished Jun 26 05:15:22 PM PDT 24
Peak memory 206140 kb
Host smart-317f00e4-88f9-4643-8b6a-b4054511cfae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91040
4841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.910404841
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.1303273485
Short name T148
Test name
Test status
Simulation time 223093375 ps
CPU time 0.92 seconds
Started Jun 26 05:16:05 PM PDT 24
Finished Jun 26 05:16:08 PM PDT 24
Peak memory 206112 kb
Host smart-498a29e4-1f9a-45bf-8697-0536a7d001b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13032
73485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.1303273485
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.3007966861
Short name T2478
Test name
Test status
Simulation time 258320329 ps
CPU time 0.87 seconds
Started Jun 26 05:11:01 PM PDT 24
Finished Jun 26 05:11:03 PM PDT 24
Peak memory 206200 kb
Host smart-d12db202-4254-4490-bfc4-cf05a139d165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30079
66861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.3007966861
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.2849168792
Short name T138
Test name
Test status
Simulation time 184104866 ps
CPU time 0.83 seconds
Started Jun 26 05:16:47 PM PDT 24
Finished Jun 26 05:16:51 PM PDT 24
Peak memory 206208 kb
Host smart-8ed37925-548f-4db7-bd83-4440d2878d7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28491
68792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.2849168792
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.2058766603
Short name T128
Test name
Test status
Simulation time 195649486 ps
CPU time 0.81 seconds
Started Jun 26 05:16:56 PM PDT 24
Finished Jun 26 05:17:00 PM PDT 24
Peak memory 206116 kb
Host smart-89e0b34b-8caf-4878-a83a-5a52f44f447b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20587
66603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.2058766603
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.2699621246
Short name T142
Test name
Test status
Simulation time 198468377 ps
CPU time 0.93 seconds
Started Jun 26 05:17:51 PM PDT 24
Finished Jun 26 05:17:56 PM PDT 24
Peak memory 206012 kb
Host smart-49cb0a12-0dcc-43f1-ac9d-a00b7d2c8bae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26996
21246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.2699621246
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.3652663554
Short name T122
Test name
Test status
Simulation time 228803078 ps
CPU time 0.9 seconds
Started Jun 26 05:18:46 PM PDT 24
Finished Jun 26 05:18:49 PM PDT 24
Peak memory 206208 kb
Host smart-dbbc9ae3-9c51-446f-b399-c65e21c972da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36526
63554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.3652663554
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.1328715231
Short name T146
Test name
Test status
Simulation time 201401723 ps
CPU time 0.87 seconds
Started Jun 26 05:18:53 PM PDT 24
Finished Jun 26 05:18:55 PM PDT 24
Peak memory 206124 kb
Host smart-e0a2d717-ad7b-496e-bf6d-c57e5200ca83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13287
15231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.1328715231
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.2380001417
Short name T1302
Test name
Test status
Simulation time 235076985 ps
CPU time 0.92 seconds
Started Jun 26 05:19:08 PM PDT 24
Finished Jun 26 05:19:11 PM PDT 24
Peak memory 206392 kb
Host smart-a9eb67e0-1dd5-4cd3-bcdd-aadfa421dbc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23800
01417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.2380001417
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1102075636
Short name T2587
Test name
Test status
Simulation time 297820601 ps
CPU time 3.66 seconds
Started Jun 26 04:43:16 PM PDT 24
Finished Jun 26 04:43:24 PM PDT 24
Peak memory 205944 kb
Host smart-768cfa27-750b-4980-8b06-b676e118629d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1102075636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.1102075636
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.618346432
Short name T2602
Test name
Test status
Simulation time 1254598240 ps
CPU time 7.98 seconds
Started Jun 26 04:43:15 PM PDT 24
Finished Jun 26 04:43:26 PM PDT 24
Peak memory 206056 kb
Host smart-cc681445-c6e1-4567-b84b-6b7490631ea2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=618346432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.618346432
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1629962841
Short name T2682
Test name
Test status
Simulation time 104283490 ps
CPU time 0.86 seconds
Started Jun 26 04:43:13 PM PDT 24
Finished Jun 26 04:43:16 PM PDT 24
Peak memory 205832 kb
Host smart-8d0946fa-ee01-4295-9553-c31747cc18c5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1629962841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1629962841
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1526308541
Short name T2598
Test name
Test status
Simulation time 175095977 ps
CPU time 1.81 seconds
Started Jun 26 04:43:15 PM PDT 24
Finished Jun 26 04:43:20 PM PDT 24
Peak memory 214372 kb
Host smart-148c399c-7e92-4028-8284-2e38356540be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526308541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.1526308541
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.2312660817
Short name T2664
Test name
Test status
Simulation time 155526089 ps
CPU time 1.05 seconds
Started Jun 26 04:43:15 PM PDT 24
Finished Jun 26 04:43:19 PM PDT 24
Peak memory 206140 kb
Host smart-3cd6d467-e8ad-469b-96fb-0f2dc4c0a673
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2312660817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.2312660817
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3361844756
Short name T2651
Test name
Test status
Simulation time 77981448 ps
CPU time 0.73 seconds
Started Jun 26 04:43:17 PM PDT 24
Finished Jun 26 04:43:21 PM PDT 24
Peak memory 205800 kb
Host smart-78b05832-5ff8-4c09-a4fb-bd0cd3e9fb39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3361844756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.3361844756
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1846311990
Short name T276
Test name
Test status
Simulation time 56108871 ps
CPU time 1.41 seconds
Started Jun 26 04:43:16 PM PDT 24
Finished Jun 26 04:43:21 PM PDT 24
Peak memory 214392 kb
Host smart-b573ecde-a491-4655-b5f9-a29ba627a018
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1846311990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.1846311990
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2383406692
Short name T2620
Test name
Test status
Simulation time 113628467 ps
CPU time 2.49 seconds
Started Jun 26 04:43:17 PM PDT 24
Finished Jun 26 04:43:24 PM PDT 24
Peak memory 205984 kb
Host smart-cb5b8a47-7ec4-41b8-aae2-6ea66c2e8613
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2383406692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.2383406692
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.359254761
Short name T2589
Test name
Test status
Simulation time 164569675 ps
CPU time 1.62 seconds
Started Jun 26 04:43:15 PM PDT 24
Finished Jun 26 04:43:21 PM PDT 24
Peak memory 206200 kb
Host smart-1c2f4aa7-49ac-4c2a-988f-01294e8d2cfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=359254761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.359254761
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2147394164
Short name T318
Test name
Test status
Simulation time 1037188189 ps
CPU time 4.35 seconds
Started Jun 26 04:43:16 PM PDT 24
Finished Jun 26 04:43:24 PM PDT 24
Peak memory 206180 kb
Host smart-230e0ee4-8110-4ec8-9a7f-4bc6a196ea12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2147394164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.2147394164
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1144143788
Short name T282
Test name
Test status
Simulation time 135091089 ps
CPU time 3.19 seconds
Started Jun 26 04:43:22 PM PDT 24
Finished Jun 26 04:43:29 PM PDT 24
Peak memory 205996 kb
Host smart-aeaf84d1-8978-4f9c-8b31-784e2fc03285
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1144143788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.1144143788
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1460184736
Short name T2613
Test name
Test status
Simulation time 730268119 ps
CPU time 7.02 seconds
Started Jun 26 04:43:21 PM PDT 24
Finished Jun 26 04:43:32 PM PDT 24
Peak memory 206028 kb
Host smart-3cfce835-14cb-4b70-87c3-9fc535c58da0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1460184736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.1460184736
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.916611433
Short name T269
Test name
Test status
Simulation time 66861158 ps
CPU time 0.86 seconds
Started Jun 26 04:43:15 PM PDT 24
Finished Jun 26 04:43:20 PM PDT 24
Peak memory 205832 kb
Host smart-9c6e9514-6788-441a-b70c-0e52929fe8b7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=916611433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.916611433
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2861676505
Short name T2685
Test name
Test status
Simulation time 155774989 ps
CPU time 2.14 seconds
Started Jun 26 04:43:18 PM PDT 24
Finished Jun 26 04:43:24 PM PDT 24
Peak memory 214336 kb
Host smart-12b221c9-4da0-40d2-8680-259c77897d6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861676505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.2861676505
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3034006047
Short name T277
Test name
Test status
Simulation time 121951570 ps
CPU time 1.06 seconds
Started Jun 26 04:43:16 PM PDT 24
Finished Jun 26 04:43:21 PM PDT 24
Peak memory 206100 kb
Host smart-7b238a57-b8f3-44eb-89f3-07b133771395
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3034006047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.3034006047
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3211448875
Short name T275
Test name
Test status
Simulation time 168596713 ps
CPU time 2.4 seconds
Started Jun 26 04:43:16 PM PDT 24
Finished Jun 26 04:43:22 PM PDT 24
Peak memory 214404 kb
Host smart-9ddc91ac-5293-4c6f-bba1-db0e8b7212d0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3211448875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.3211448875
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2351361380
Short name T2595
Test name
Test status
Simulation time 479656651 ps
CPU time 4.37 seconds
Started Jun 26 04:43:17 PM PDT 24
Finished Jun 26 04:43:25 PM PDT 24
Peak memory 206020 kb
Host smart-8b211df5-e0ff-4dd6-9dc9-7cc986fce478
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2351361380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.2351361380
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.759982617
Short name T2606
Test name
Test status
Simulation time 86216048 ps
CPU time 1.06 seconds
Started Jun 26 04:43:17 PM PDT 24
Finished Jun 26 04:43:22 PM PDT 24
Peak memory 206192 kb
Host smart-b7c3f5eb-c634-42fe-abdc-3afd7cf4bcd5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=759982617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.759982617
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1115820380
Short name T242
Test name
Test status
Simulation time 76689464 ps
CPU time 2.15 seconds
Started Jun 26 04:43:17 PM PDT 24
Finished Jun 26 04:43:23 PM PDT 24
Peak memory 214392 kb
Host smart-cc25d2cf-9685-4aa0-a8b5-6a11e77d74d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1115820380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.1115820380
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1476951750
Short name T2670
Test name
Test status
Simulation time 462909467 ps
CPU time 2.8 seconds
Started Jun 26 04:43:17 PM PDT 24
Finished Jun 26 04:43:23 PM PDT 24
Peak memory 206252 kb
Host smart-be1462b1-f4ff-4723-be43-51d8f275ddb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1476951750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.1476951750
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3168494223
Short name T2590
Test name
Test status
Simulation time 98293957 ps
CPU time 2.26 seconds
Started Jun 26 04:43:30 PM PDT 24
Finished Jun 26 04:43:39 PM PDT 24
Peak memory 214424 kb
Host smart-c4690a54-7dc0-4f3d-9074-ed95010b53e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168494223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.3168494223
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3999010138
Short name T2662
Test name
Test status
Simulation time 62679449 ps
CPU time 0.92 seconds
Started Jun 26 04:43:29 PM PDT 24
Finished Jun 26 04:43:36 PM PDT 24
Peak memory 205832 kb
Host smart-409a0390-54d2-48ba-93aa-c7af5eee410f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3999010138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.3999010138
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.1624116663
Short name T2605
Test name
Test status
Simulation time 36955201 ps
CPU time 0.66 seconds
Started Jun 26 04:43:29 PM PDT 24
Finished Jun 26 04:43:37 PM PDT 24
Peak memory 205804 kb
Host smart-855b0101-d5d4-4ca1-99da-a1a6220a8b8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1624116663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.1624116663
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3905922912
Short name T206
Test name
Test status
Simulation time 110460790 ps
CPU time 1.7 seconds
Started Jun 26 04:43:28 PM PDT 24
Finished Jun 26 04:43:36 PM PDT 24
Peak memory 206192 kb
Host smart-0f000e2f-ad2c-4439-af55-df5dd044829d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3905922912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.3905922912
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3501684956
Short name T300
Test name
Test status
Simulation time 159687655 ps
CPU time 1.87 seconds
Started Jun 26 04:43:28 PM PDT 24
Finished Jun 26 04:43:37 PM PDT 24
Peak memory 219136 kb
Host smart-e4a14b0f-d01d-4ba0-8603-9768dd1ca375
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501684956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.3501684956
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1224658490
Short name T2676
Test name
Test status
Simulation time 117656809 ps
CPU time 1.01 seconds
Started Jun 26 04:43:29 PM PDT 24
Finished Jun 26 04:43:37 PM PDT 24
Peak memory 206072 kb
Host smart-9c448f1c-2a24-42c3-b2f1-1082a571237b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1224658490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.1224658490
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3449434740
Short name T2607
Test name
Test status
Simulation time 260010004 ps
CPU time 1.79 seconds
Started Jun 26 04:43:33 PM PDT 24
Finished Jun 26 04:43:42 PM PDT 24
Peak memory 206080 kb
Host smart-32fc81d8-8ec8-415a-ad1e-3400043a1ab2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3449434740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.3449434740
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2884613472
Short name T241
Test name
Test status
Simulation time 230927921 ps
CPU time 2.21 seconds
Started Jun 26 04:43:29 PM PDT 24
Finished Jun 26 04:43:38 PM PDT 24
Peak memory 221772 kb
Host smart-10ffbee7-002b-4549-b196-815b6ba4bd71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2884613472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.2884613472
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2216473856
Short name T2593
Test name
Test status
Simulation time 301574004 ps
CPU time 2.45 seconds
Started Jun 26 04:43:28 PM PDT 24
Finished Jun 26 04:43:38 PM PDT 24
Peak memory 206192 kb
Host smart-fbb79f8f-a788-4f7e-87a0-20d9b1182a9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2216473856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.2216473856
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1683879504
Short name T2661
Test name
Test status
Simulation time 73192664 ps
CPU time 1.49 seconds
Started Jun 26 04:43:30 PM PDT 24
Finished Jun 26 04:43:38 PM PDT 24
Peak memory 214476 kb
Host smart-42bef513-cfe6-4672-9b52-4694c44dbe9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683879504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.1683879504
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.251169219
Short name T284
Test name
Test status
Simulation time 75366513 ps
CPU time 0.96 seconds
Started Jun 26 04:43:30 PM PDT 24
Finished Jun 26 04:43:38 PM PDT 24
Peak memory 206072 kb
Host smart-04bdaeb0-105a-43bb-9fc3-c8be9001820d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=251169219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.251169219
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2182436390
Short name T2633
Test name
Test status
Simulation time 37771349 ps
CPU time 0.67 seconds
Started Jun 26 04:43:29 PM PDT 24
Finished Jun 26 04:43:36 PM PDT 24
Peak memory 205820 kb
Host smart-97fe9144-5059-4aa5-ab80-a058b3c698ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2182436390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.2182436390
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3348776516
Short name T2686
Test name
Test status
Simulation time 281792454 ps
CPU time 1.82 seconds
Started Jun 26 04:43:27 PM PDT 24
Finished Jun 26 04:43:36 PM PDT 24
Peak memory 206180 kb
Host smart-a3d9c2a3-df74-4123-a21b-553c152524aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3348776516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3348776516
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1077379830
Short name T2674
Test name
Test status
Simulation time 234103984 ps
CPU time 2.09 seconds
Started Jun 26 04:43:28 PM PDT 24
Finished Jun 26 04:43:37 PM PDT 24
Peak memory 221712 kb
Host smart-f1d285b1-8a4a-4169-88a8-f7c40a38d608
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1077379830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.1077379830
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.707697039
Short name T2684
Test name
Test status
Simulation time 247312341 ps
CPU time 1.88 seconds
Started Jun 26 04:43:31 PM PDT 24
Finished Jun 26 04:43:39 PM PDT 24
Peak memory 214452 kb
Host smart-2c68ce74-99cd-422d-9179-5d5bfa33c8e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707697039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbde
v_csr_mem_rw_with_rand_reset.707697039
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3308517060
Short name T2609
Test name
Test status
Simulation time 89081852 ps
CPU time 1.11 seconds
Started Jun 26 04:43:28 PM PDT 24
Finished Jun 26 04:43:36 PM PDT 24
Peak memory 206136 kb
Host smart-4c13c627-f102-4591-926a-fee6ff5308e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3308517060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.3308517060
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2713407566
Short name T2649
Test name
Test status
Simulation time 37545131 ps
CPU time 0.75 seconds
Started Jun 26 04:43:30 PM PDT 24
Finished Jun 26 04:43:38 PM PDT 24
Peak memory 205812 kb
Host smart-4c0506a5-bb91-4640-8aa4-be3d8cb9d1ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2713407566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.2713407566
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3668192708
Short name T283
Test name
Test status
Simulation time 286111812 ps
CPU time 1.87 seconds
Started Jun 26 04:43:33 PM PDT 24
Finished Jun 26 04:43:42 PM PDT 24
Peak memory 206104 kb
Host smart-461e4fd4-b4be-4014-8ba2-22040c30c9e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3668192708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.3668192708
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3357525475
Short name T2669
Test name
Test status
Simulation time 171620162 ps
CPU time 2.18 seconds
Started Jun 26 04:43:29 PM PDT 24
Finished Jun 26 04:43:38 PM PDT 24
Peak memory 222100 kb
Host smart-6db4db5f-ae84-4ccf-aa8a-2857420ace73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3357525475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3357525475
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2162322194
Short name T248
Test name
Test status
Simulation time 823288811 ps
CPU time 4.66 seconds
Started Jun 26 04:43:28 PM PDT 24
Finished Jun 26 04:43:40 PM PDT 24
Peak memory 206168 kb
Host smart-b5a9cef7-8c0c-4c98-bcd1-4afd5600b024
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2162322194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.2162322194
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1587896610
Short name T2599
Test name
Test status
Simulation time 172773915 ps
CPU time 1.8 seconds
Started Jun 26 04:43:39 PM PDT 24
Finished Jun 26 04:43:48 PM PDT 24
Peak memory 214260 kb
Host smart-67a9af5f-704a-4aeb-be32-c9a8273cc289
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587896610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.1587896610
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3489402519
Short name T2643
Test name
Test status
Simulation time 32892995 ps
CPU time 0.7 seconds
Started Jun 26 04:43:37 PM PDT 24
Finished Jun 26 04:43:45 PM PDT 24
Peak memory 205820 kb
Host smart-c4b64256-320c-4dcc-a20c-ede86fba2993
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3489402519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.3489402519
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.4059461706
Short name T2675
Test name
Test status
Simulation time 187906308 ps
CPU time 1.17 seconds
Started Jun 26 04:43:34 PM PDT 24
Finished Jun 26 04:43:43 PM PDT 24
Peak memory 206180 kb
Host smart-64016f68-cadb-4e9c-8efb-cba0c2be5481
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4059461706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.4059461706
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1015599390
Short name T250
Test name
Test status
Simulation time 643601752 ps
CPU time 4.4 seconds
Started Jun 26 04:43:30 PM PDT 24
Finished Jun 26 04:43:42 PM PDT 24
Peak memory 206152 kb
Host smart-8af6e9d4-d21e-42a1-8e4f-0fade74daf10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1015599390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.1015599390
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.4250247209
Short name T2652
Test name
Test status
Simulation time 57251480 ps
CPU time 1.26 seconds
Started Jun 26 04:43:35 PM PDT 24
Finished Jun 26 04:43:44 PM PDT 24
Peak memory 214376 kb
Host smart-732943f1-444f-4faf-a6b7-bc38fe7fce6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250247209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.4250247209
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2109215731
Short name T2603
Test name
Test status
Simulation time 90233860 ps
CPU time 1.11 seconds
Started Jun 26 04:43:37 PM PDT 24
Finished Jun 26 04:43:45 PM PDT 24
Peak memory 206136 kb
Host smart-6f027b09-9409-410a-97d4-598a3c620ced
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2109215731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.2109215731
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1338171162
Short name T304
Test name
Test status
Simulation time 42956835 ps
CPU time 0.72 seconds
Started Jun 26 04:43:34 PM PDT 24
Finished Jun 26 04:43:43 PM PDT 24
Peak memory 205836 kb
Host smart-87041558-e94b-4a75-98da-272986ee2590
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1338171162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.1338171162
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3346801392
Short name T2601
Test name
Test status
Simulation time 163094165 ps
CPU time 1.63 seconds
Started Jun 26 04:43:36 PM PDT 24
Finished Jun 26 04:43:45 PM PDT 24
Peak memory 206112 kb
Host smart-04cfdc21-2132-49e2-b787-991d80d6e5cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3346801392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.3346801392
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3747029805
Short name T2673
Test name
Test status
Simulation time 105199310 ps
CPU time 1.44 seconds
Started Jun 26 04:43:37 PM PDT 24
Finished Jun 26 04:43:46 PM PDT 24
Peak memory 221680 kb
Host smart-81a0400f-8c8c-4cb3-b0d8-566f1dab06ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3747029805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.3747029805
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2041995028
Short name T251
Test name
Test status
Simulation time 798823252 ps
CPU time 2.94 seconds
Started Jun 26 04:43:37 PM PDT 24
Finished Jun 26 04:43:47 PM PDT 24
Peak memory 205972 kb
Host smart-f638563c-ac06-491c-8eed-3a5697e64be0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2041995028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.2041995028
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1621317486
Short name T2619
Test name
Test status
Simulation time 175094956 ps
CPU time 1.45 seconds
Started Jun 26 04:43:37 PM PDT 24
Finished Jun 26 04:43:46 PM PDT 24
Peak memory 214364 kb
Host smart-930a124f-f64c-4883-97db-20a58e4c3266
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621317486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.1621317486
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1583067075
Short name T285
Test name
Test status
Simulation time 50767474 ps
CPU time 1 seconds
Started Jun 26 04:43:39 PM PDT 24
Finished Jun 26 04:43:48 PM PDT 24
Peak memory 205880 kb
Host smart-5d208e74-e55c-4595-928a-136a9725d4a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1583067075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.1583067075
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.676256458
Short name T314
Test name
Test status
Simulation time 50013872 ps
CPU time 0.67 seconds
Started Jun 26 04:43:37 PM PDT 24
Finished Jun 26 04:43:45 PM PDT 24
Peak memory 205600 kb
Host smart-2aa0b953-1929-4249-974d-f85d750a8d8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=676256458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.676256458
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2262758525
Short name T2630
Test name
Test status
Simulation time 71989200 ps
CPU time 1.06 seconds
Started Jun 26 04:43:34 PM PDT 24
Finished Jun 26 04:43:43 PM PDT 24
Peak memory 206180 kb
Host smart-1bd78af6-92a5-4973-9038-605966e8e5ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2262758525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.2262758525
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3807597419
Short name T2656
Test name
Test status
Simulation time 117410985 ps
CPU time 1.65 seconds
Started Jun 26 04:43:35 PM PDT 24
Finished Jun 26 04:43:44 PM PDT 24
Peak memory 222008 kb
Host smart-075ed854-c6b4-4ea6-b0a8-8dd15d0d3368
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3807597419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.3807597419
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1747620386
Short name T2647
Test name
Test status
Simulation time 65095607 ps
CPU time 1.22 seconds
Started Jun 26 04:43:39 PM PDT 24
Finished Jun 26 04:43:48 PM PDT 24
Peak memory 216080 kb
Host smart-c87c6715-6d5c-4c4a-8b80-0bf5ddba1dfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747620386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.1747620386
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.325313803
Short name T279
Test name
Test status
Simulation time 55776506 ps
CPU time 0.86 seconds
Started Jun 26 04:43:37 PM PDT 24
Finished Jun 26 04:43:45 PM PDT 24
Peak memory 205832 kb
Host smart-6799f976-31f8-47b3-8222-681583f7800d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=325313803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.325313803
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.134473268
Short name T315
Test name
Test status
Simulation time 64670679 ps
CPU time 0.65 seconds
Started Jun 26 04:43:33 PM PDT 24
Finished Jun 26 04:43:41 PM PDT 24
Peak memory 205820 kb
Host smart-9b3459c8-9296-4c6a-b6d5-93159f423097
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=134473268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.134473268
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1884603790
Short name T2591
Test name
Test status
Simulation time 174073209 ps
CPU time 1.17 seconds
Started Jun 26 04:43:36 PM PDT 24
Finished Jun 26 04:43:45 PM PDT 24
Peak memory 206128 kb
Host smart-c2d8a831-e6ad-4f6c-8463-c06c3cbf415b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1884603790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.1884603790
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1559208739
Short name T2632
Test name
Test status
Simulation time 111248168 ps
CPU time 2.53 seconds
Started Jun 26 04:43:36 PM PDT 24
Finished Jun 26 04:43:46 PM PDT 24
Peak memory 214376 kb
Host smart-459dcf81-288e-4d85-8935-5f404e5e69e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1559208739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.1559208739
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1003202054
Short name T2640
Test name
Test status
Simulation time 98125189 ps
CPU time 1.67 seconds
Started Jun 26 04:43:39 PM PDT 24
Finished Jun 26 04:43:48 PM PDT 24
Peak memory 214376 kb
Host smart-4b09a45f-4b40-412b-800c-780f8c2d42fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003202054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.1003202054
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3713203846
Short name T2683
Test name
Test status
Simulation time 66988676 ps
CPU time 0.98 seconds
Started Jun 26 04:43:37 PM PDT 24
Finished Jun 26 04:43:46 PM PDT 24
Peak memory 205976 kb
Host smart-266d4843-3d51-4a32-b625-6ac22715c43e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3713203846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.3713203846
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.4292812736
Short name T308
Test name
Test status
Simulation time 41756685 ps
CPU time 0.66 seconds
Started Jun 26 04:43:37 PM PDT 24
Finished Jun 26 04:43:45 PM PDT 24
Peak memory 205804 kb
Host smart-6992c9d4-ddbf-4d95-985d-5b3fbd0dcab0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4292812736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.4292812736
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1964565841
Short name T2648
Test name
Test status
Simulation time 216025156 ps
CPU time 1.75 seconds
Started Jun 26 04:43:38 PM PDT 24
Finished Jun 26 04:43:47 PM PDT 24
Peak memory 206192 kb
Host smart-b0acf961-c8c4-45fe-b362-75f82b04668f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1964565841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.1964565841
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.640178480
Short name T2653
Test name
Test status
Simulation time 144103794 ps
CPU time 1.89 seconds
Started Jun 26 04:43:37 PM PDT 24
Finished Jun 26 04:43:47 PM PDT 24
Peak memory 214288 kb
Host smart-1c09717d-f211-4a2a-9415-2c1135bd9a42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=640178480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.640178480
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2994864424
Short name T324
Test name
Test status
Simulation time 516009684 ps
CPU time 4.3 seconds
Started Jun 26 04:43:37 PM PDT 24
Finished Jun 26 04:43:49 PM PDT 24
Peak memory 206212 kb
Host smart-ac2343ca-b11b-4e8c-8a9c-9267421b8d5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2994864424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.2994864424
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1873363088
Short name T2672
Test name
Test status
Simulation time 132044324 ps
CPU time 1.28 seconds
Started Jun 26 04:43:39 PM PDT 24
Finished Jun 26 04:43:48 PM PDT 24
Peak memory 222628 kb
Host smart-971ce9c2-22dc-414e-8544-34a98f556d61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873363088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.1873363088
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3189425529
Short name T272
Test name
Test status
Simulation time 38634797 ps
CPU time 0.83 seconds
Started Jun 26 04:43:41 PM PDT 24
Finished Jun 26 04:43:49 PM PDT 24
Peak memory 205964 kb
Host smart-9772ccb3-3295-4dd9-8290-d22e34d167bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3189425529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.3189425529
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2545418989
Short name T2659
Test name
Test status
Simulation time 39555416 ps
CPU time 0.67 seconds
Started Jun 26 04:43:43 PM PDT 24
Finished Jun 26 04:43:51 PM PDT 24
Peak memory 205920 kb
Host smart-76e54107-4a52-47b8-98bf-f9149b44f007
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2545418989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.2545418989
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.252138641
Short name T301
Test name
Test status
Simulation time 144663454 ps
CPU time 1.16 seconds
Started Jun 26 04:43:41 PM PDT 24
Finished Jun 26 04:43:49 PM PDT 24
Peak memory 206228 kb
Host smart-6a2514a4-9b4e-483b-afd9-cfbe88c5eed7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=252138641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.252138641
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.45146576
Short name T2681
Test name
Test status
Simulation time 114536156 ps
CPU time 1.51 seconds
Started Jun 26 04:43:36 PM PDT 24
Finished Jun 26 04:43:45 PM PDT 24
Peak memory 206476 kb
Host smart-d15a6f68-d233-414e-856a-64f584c939be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=45146576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.45146576
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2098760487
Short name T322
Test name
Test status
Simulation time 744933888 ps
CPU time 4.37 seconds
Started Jun 26 04:43:41 PM PDT 24
Finished Jun 26 04:43:53 PM PDT 24
Peak memory 206200 kb
Host smart-dde8a1cf-dbad-401a-8b24-adc7a741dac4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2098760487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.2098760487
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.305227180
Short name T280
Test name
Test status
Simulation time 119101456 ps
CPU time 3.2 seconds
Started Jun 26 04:43:14 PM PDT 24
Finished Jun 26 04:43:20 PM PDT 24
Peak memory 206024 kb
Host smart-11707d60-e7cf-410d-bf78-552eab4e089d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=305227180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.305227180
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.814314775
Short name T2585
Test name
Test status
Simulation time 719053641 ps
CPU time 4.68 seconds
Started Jun 26 04:43:14 PM PDT 24
Finished Jun 26 04:43:22 PM PDT 24
Peak memory 206068 kb
Host smart-3d650ec7-5d60-45d8-97b3-13fcc4bb6a7c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=814314775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.814314775
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.901200842
Short name T2628
Test name
Test status
Simulation time 199299482 ps
CPU time 0.94 seconds
Started Jun 26 04:43:13 PM PDT 24
Finished Jun 26 04:43:16 PM PDT 24
Peak memory 205856 kb
Host smart-f7bd26b5-ccb0-4174-aee1-560ab4e1b6af
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=901200842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.901200842
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3807739714
Short name T2616
Test name
Test status
Simulation time 66736175 ps
CPU time 1.24 seconds
Started Jun 26 04:43:16 PM PDT 24
Finished Jun 26 04:43:21 PM PDT 24
Peak memory 214444 kb
Host smart-20d65ffa-e8f2-437a-8a70-4e19d1206128
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807739714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.3807739714
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1409664082
Short name T2636
Test name
Test status
Simulation time 70571508 ps
CPU time 0.98 seconds
Started Jun 26 04:43:17 PM PDT 24
Finished Jun 26 04:43:22 PM PDT 24
Peak memory 206056 kb
Host smart-cb4ec639-039a-4640-85a9-051fc94f4f16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1409664082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.1409664082
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.96495945
Short name T278
Test name
Test status
Simulation time 200472106 ps
CPU time 2.41 seconds
Started Jun 26 04:43:15 PM PDT 24
Finished Jun 26 04:43:20 PM PDT 24
Peak memory 214340 kb
Host smart-1a72da84-dc3b-4e9f-91b6-2700d0e3b15e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=96495945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.96495945
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2511784756
Short name T2584
Test name
Test status
Simulation time 116877659 ps
CPU time 2.38 seconds
Started Jun 26 04:43:16 PM PDT 24
Finished Jun 26 04:43:22 PM PDT 24
Peak memory 206300 kb
Host smart-4b0bd58d-6bf1-444e-a190-04a4ca97108d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2511784756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.2511784756
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1657647847
Short name T2604
Test name
Test status
Simulation time 208187813 ps
CPU time 1.68 seconds
Started Jun 26 04:43:15 PM PDT 24
Finished Jun 26 04:43:20 PM PDT 24
Peak memory 206108 kb
Host smart-180e7795-b780-4d43-8945-9844aa22008d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1657647847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.1657647847
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.162333411
Short name T237
Test name
Test status
Simulation time 114661058 ps
CPU time 1.65 seconds
Started Jun 26 04:43:17 PM PDT 24
Finished Jun 26 04:43:22 PM PDT 24
Peak memory 206220 kb
Host smart-6c6e9064-7fb8-477a-a257-9e912f51c946
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=162333411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.162333411
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.4204225278
Short name T235
Test name
Test status
Simulation time 276771243 ps
CPU time 2.44 seconds
Started Jun 26 04:43:15 PM PDT 24
Finished Jun 26 04:43:20 PM PDT 24
Peak memory 206088 kb
Host smart-506ad6f1-5ef3-46a5-b5c6-d57e802a728f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4204225278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.4204225278
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.2790831624
Short name T2588
Test name
Test status
Simulation time 66648077 ps
CPU time 0.73 seconds
Started Jun 26 04:43:39 PM PDT 24
Finished Jun 26 04:43:47 PM PDT 24
Peak memory 205820 kb
Host smart-27481969-c9e9-43d5-9245-b7ca2c464114
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2790831624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.2790831624
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3763758594
Short name T2654
Test name
Test status
Simulation time 35923680 ps
CPU time 0.7 seconds
Started Jun 26 04:43:36 PM PDT 24
Finished Jun 26 04:43:44 PM PDT 24
Peak memory 205816 kb
Host smart-a8aaaa5f-bd8a-4442-ae94-74ee40614c41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3763758594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.3763758594
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2161345126
Short name T2629
Test name
Test status
Simulation time 76222039 ps
CPU time 0.68 seconds
Started Jun 26 04:43:40 PM PDT 24
Finished Jun 26 04:43:48 PM PDT 24
Peak memory 205812 kb
Host smart-aac60b35-aa52-4390-be6f-85ffd860973d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2161345126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.2161345126
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1745472939
Short name T310
Test name
Test status
Simulation time 49154743 ps
CPU time 0.77 seconds
Started Jun 26 04:43:43 PM PDT 24
Finished Jun 26 04:43:51 PM PDT 24
Peak memory 205820 kb
Host smart-edd400af-2122-4b31-96a6-2944a2006f00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1745472939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.1745472939
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.4069559209
Short name T306
Test name
Test status
Simulation time 56376929 ps
CPU time 0.71 seconds
Started Jun 26 04:43:43 PM PDT 24
Finished Jun 26 04:43:50 PM PDT 24
Peak memory 205816 kb
Host smart-048de209-1399-44a7-be24-83cfc162e199
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4069559209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.4069559209
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.441718393
Short name T2645
Test name
Test status
Simulation time 38233697 ps
CPU time 0.73 seconds
Started Jun 26 04:43:43 PM PDT 24
Finished Jun 26 04:43:50 PM PDT 24
Peak memory 205820 kb
Host smart-d4514b1c-dbb1-4155-a9de-d64b038902c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=441718393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.441718393
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2442621922
Short name T2668
Test name
Test status
Simulation time 95284054 ps
CPU time 0.78 seconds
Started Jun 26 04:43:42 PM PDT 24
Finished Jun 26 04:43:49 PM PDT 24
Peak memory 205816 kb
Host smart-99543a5b-d022-4f19-8069-7bff2278804e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2442621922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.2442621922
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.845957612
Short name T2611
Test name
Test status
Simulation time 35268303 ps
CPU time 0.68 seconds
Started Jun 26 04:43:40 PM PDT 24
Finished Jun 26 04:43:48 PM PDT 24
Peak memory 206104 kb
Host smart-dc30da5f-b1e2-463e-9238-59d76616e381
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=845957612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.845957612
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3025012665
Short name T2625
Test name
Test status
Simulation time 47749410 ps
CPU time 0.7 seconds
Started Jun 26 04:43:44 PM PDT 24
Finished Jun 26 04:43:52 PM PDT 24
Peak memory 205820 kb
Host smart-65ce76f5-c7c5-45ad-ac41-3847c2cfefa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3025012665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.3025012665
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3765002547
Short name T270
Test name
Test status
Simulation time 407594229 ps
CPU time 3.61 seconds
Started Jun 26 04:43:16 PM PDT 24
Finished Jun 26 04:43:24 PM PDT 24
Peak memory 206012 kb
Host smart-81e2d779-e816-4261-bbf9-b8fe76c2e1f1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3765002547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.3765002547
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2747340995
Short name T2634
Test name
Test status
Simulation time 527092371 ps
CPU time 4.2 seconds
Started Jun 26 04:43:15 PM PDT 24
Finished Jun 26 04:43:23 PM PDT 24
Peak memory 206388 kb
Host smart-b715b961-fab8-45c7-8f52-a0e7a81be744
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2747340995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.2747340995
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1732688690
Short name T2646
Test name
Test status
Simulation time 150842862 ps
CPU time 0.97 seconds
Started Jun 26 04:43:16 PM PDT 24
Finished Jun 26 04:43:21 PM PDT 24
Peak memory 205864 kb
Host smart-13d57778-cbd4-42f7-8278-bd0208b7ccb6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1732688690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.1732688690
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3739735888
Short name T252
Test name
Test status
Simulation time 130698184 ps
CPU time 1.46 seconds
Started Jun 26 04:43:17 PM PDT 24
Finished Jun 26 04:43:22 PM PDT 24
Peak memory 214472 kb
Host smart-d43ea14c-54d8-4ac9-ae76-deaa0ce84651
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739735888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.3739735888
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2492078293
Short name T271
Test name
Test status
Simulation time 48116070 ps
CPU time 0.97 seconds
Started Jun 26 04:43:17 PM PDT 24
Finished Jun 26 04:43:21 PM PDT 24
Peak memory 206096 kb
Host smart-19c24e60-81d2-414d-925d-3379bf1f082b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2492078293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2492078293
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3618188245
Short name T302
Test name
Test status
Simulation time 36822737 ps
CPU time 0.64 seconds
Started Jun 26 04:43:21 PM PDT 24
Finished Jun 26 04:43:26 PM PDT 24
Peak memory 205820 kb
Host smart-b1fec2b1-f064-4956-bfd4-fe54f0aabca9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3618188245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.3618188245
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3354569811
Short name T2627
Test name
Test status
Simulation time 57834955 ps
CPU time 1.39 seconds
Started Jun 26 04:43:14 PM PDT 24
Finished Jun 26 04:43:18 PM PDT 24
Peak memory 214328 kb
Host smart-a1995b1d-0cdf-449f-b178-334f7b32c517
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3354569811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.3354569811
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.4121918777
Short name T2608
Test name
Test status
Simulation time 121827831 ps
CPU time 2.36 seconds
Started Jun 26 04:43:16 PM PDT 24
Finished Jun 26 04:43:22 PM PDT 24
Peak memory 205880 kb
Host smart-18304ce6-9dd0-4c97-95ee-a04aa99e0d15
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4121918777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.4121918777
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2258652298
Short name T2677
Test name
Test status
Simulation time 140383333 ps
CPU time 1.21 seconds
Started Jun 26 04:43:14 PM PDT 24
Finished Jun 26 04:43:18 PM PDT 24
Peak memory 206192 kb
Host smart-d4c988b8-0ff3-4448-94b7-4c62f9173dd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2258652298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.2258652298
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.402040127
Short name T202
Test name
Test status
Simulation time 111436125 ps
CPU time 1.41 seconds
Started Jun 26 04:43:16 PM PDT 24
Finished Jun 26 04:43:21 PM PDT 24
Peak memory 206140 kb
Host smart-c7583843-71ba-4717-b687-5e21e20f3040
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=402040127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.402040127
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.368441170
Short name T320
Test name
Test status
Simulation time 539999549 ps
CPU time 2.85 seconds
Started Jun 26 04:43:15 PM PDT 24
Finished Jun 26 04:43:22 PM PDT 24
Peak memory 206132 kb
Host smart-e9ade17c-9635-4991-83b2-e637f105f83c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=368441170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.368441170
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.86033224
Short name T2650
Test name
Test status
Simulation time 63637785 ps
CPU time 0.68 seconds
Started Jun 26 04:43:43 PM PDT 24
Finished Jun 26 04:43:50 PM PDT 24
Peak memory 205836 kb
Host smart-8e7da664-2a12-4b80-9529-daca6d7afb9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=86033224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.86033224
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.595414251
Short name T2639
Test name
Test status
Simulation time 66613138 ps
CPU time 0.71 seconds
Started Jun 26 04:43:42 PM PDT 24
Finished Jun 26 04:43:49 PM PDT 24
Peak memory 205812 kb
Host smart-dd97e5cf-a3f1-4f0c-bb83-56ddb64c9033
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=595414251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.595414251
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.843960356
Short name T2618
Test name
Test status
Simulation time 83706996 ps
CPU time 0.72 seconds
Started Jun 26 04:43:42 PM PDT 24
Finished Jun 26 04:43:50 PM PDT 24
Peak memory 205812 kb
Host smart-f1910fa8-de7d-4583-aae0-488a36197f66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=843960356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.843960356
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1273608549
Short name T2586
Test name
Test status
Simulation time 48467468 ps
CPU time 0.7 seconds
Started Jun 26 04:43:43 PM PDT 24
Finished Jun 26 04:43:51 PM PDT 24
Peak memory 205816 kb
Host smart-2f4865df-3dc7-40d9-9f5c-94cece3ee585
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1273608549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.1273608549
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1774833343
Short name T2597
Test name
Test status
Simulation time 41043847 ps
CPU time 0.74 seconds
Started Jun 26 04:43:43 PM PDT 24
Finished Jun 26 04:43:51 PM PDT 24
Peak memory 205800 kb
Host smart-be63bdac-9a6f-4ac2-9fce-b80b25b63f0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1774833343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.1774833343
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2082344878
Short name T2641
Test name
Test status
Simulation time 49778185 ps
CPU time 0.68 seconds
Started Jun 26 04:43:43 PM PDT 24
Finished Jun 26 04:43:51 PM PDT 24
Peak memory 205820 kb
Host smart-5ad01915-3d60-41e0-bca9-aedc4f9eb532
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2082344878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.2082344878
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3762997664
Short name T2679
Test name
Test status
Simulation time 123323594 ps
CPU time 0.83 seconds
Started Jun 26 04:43:43 PM PDT 24
Finished Jun 26 04:43:51 PM PDT 24
Peak memory 205820 kb
Host smart-e0cb812c-a9cc-4d42-9fb2-c1a24f9b536b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3762997664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.3762997664
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.4212001251
Short name T313
Test name
Test status
Simulation time 48948159 ps
CPU time 0.69 seconds
Started Jun 26 04:43:43 PM PDT 24
Finished Jun 26 04:43:51 PM PDT 24
Peak memory 205820 kb
Host smart-a316dfe5-bcce-4767-b94f-610b423d9755
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4212001251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.4212001251
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3857436194
Short name T312
Test name
Test status
Simulation time 31622830 ps
CPU time 0.7 seconds
Started Jun 26 04:43:41 PM PDT 24
Finished Jun 26 04:43:48 PM PDT 24
Peak memory 205820 kb
Host smart-bd1f1837-a252-402c-96bf-b9b23540a9fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3857436194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.3857436194
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3685158445
Short name T228
Test name
Test status
Simulation time 83005253 ps
CPU time 2.03 seconds
Started Jun 26 04:43:23 PM PDT 24
Finished Jun 26 04:43:30 PM PDT 24
Peak memory 206056 kb
Host smart-6e00897b-2e37-4a6d-aab9-c44d754e4bce
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3685158445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.3685158445
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2018085425
Short name T2671
Test name
Test status
Simulation time 797817213 ps
CPU time 5.04 seconds
Started Jun 26 04:43:23 PM PDT 24
Finished Jun 26 04:43:34 PM PDT 24
Peak memory 206032 kb
Host smart-26903281-1022-4246-8056-ccee5ae8f280
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2018085425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.2018085425
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2951029639
Short name T2594
Test name
Test status
Simulation time 79222855 ps
CPU time 0.79 seconds
Started Jun 26 04:43:23 PM PDT 24
Finished Jun 26 04:43:30 PM PDT 24
Peak memory 205840 kb
Host smart-bb812128-b46a-47ca-928f-de2fd069d230
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2951029639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.2951029639
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1864621062
Short name T227
Test name
Test status
Simulation time 181399015 ps
CPU time 1.82 seconds
Started Jun 26 04:43:22 PM PDT 24
Finished Jun 26 04:43:28 PM PDT 24
Peak memory 214368 kb
Host smart-b986cb78-fc40-4b9a-8764-5676df01fb92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864621062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.1864621062
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1895521120
Short name T2638
Test name
Test status
Simulation time 134640669 ps
CPU time 0.98 seconds
Started Jun 26 04:43:22 PM PDT 24
Finished Jun 26 04:43:28 PM PDT 24
Peak memory 206072 kb
Host smart-05003052-3434-429b-8341-328b81763ad1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1895521120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.1895521120
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1160540984
Short name T2621
Test name
Test status
Simulation time 70024428 ps
CPU time 0.7 seconds
Started Jun 26 04:43:23 PM PDT 24
Finished Jun 26 04:43:28 PM PDT 24
Peak memory 205832 kb
Host smart-ba5a654b-894e-422c-93ab-b40a39369bb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1160540984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.1160540984
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3256584084
Short name T268
Test name
Test status
Simulation time 188962726 ps
CPU time 1.51 seconds
Started Jun 26 04:43:20 PM PDT 24
Finished Jun 26 04:43:25 PM PDT 24
Peak memory 214392 kb
Host smart-32ff0e77-1ae8-4cae-8094-8ebd13b5f836
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3256584084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.3256584084
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2819135685
Short name T2666
Test name
Test status
Simulation time 175708444 ps
CPU time 2.5 seconds
Started Jun 26 04:43:23 PM PDT 24
Finished Jun 26 04:43:30 PM PDT 24
Peak memory 206020 kb
Host smart-05736f03-d66e-489f-a319-45b6792001b8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2819135685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.2819135685
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.85990711
Short name T2658
Test name
Test status
Simulation time 140329239 ps
CPU time 1.24 seconds
Started Jun 26 04:43:26 PM PDT 24
Finished Jun 26 04:43:34 PM PDT 24
Peak memory 206096 kb
Host smart-97f7a328-0e48-447e-932f-675b660bfe75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=85990711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.85990711
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3655731736
Short name T2612
Test name
Test status
Simulation time 76177519 ps
CPU time 1.92 seconds
Started Jun 26 04:43:16 PM PDT 24
Finished Jun 26 04:43:21 PM PDT 24
Peak memory 206192 kb
Host smart-4424a6a9-3004-4f38-a5a4-dc8a86757ed9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3655731736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.3655731736
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1507514013
Short name T319
Test name
Test status
Simulation time 856807817 ps
CPU time 4.61 seconds
Started Jun 26 04:43:17 PM PDT 24
Finished Jun 26 04:43:25 PM PDT 24
Peak memory 206148 kb
Host smart-fa1cd303-25de-4aa0-8602-f5f2886a5990
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1507514013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.1507514013
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2663186677
Short name T2665
Test name
Test status
Simulation time 84174953 ps
CPU time 0.72 seconds
Started Jun 26 04:43:44 PM PDT 24
Finished Jun 26 04:43:51 PM PDT 24
Peak memory 205740 kb
Host smart-d8d4401c-155b-4aa6-b330-a08f6baba950
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2663186677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.2663186677
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.4143863394
Short name T2631
Test name
Test status
Simulation time 52017955 ps
CPU time 0.69 seconds
Started Jun 26 04:43:55 PM PDT 24
Finished Jun 26 04:44:07 PM PDT 24
Peak memory 205796 kb
Host smart-d5dd67e3-3524-4d5e-9df2-7b30fa09bf98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4143863394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.4143863394
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1377554262
Short name T2655
Test name
Test status
Simulation time 37180571 ps
CPU time 0.67 seconds
Started Jun 26 04:43:55 PM PDT 24
Finished Jun 26 04:44:07 PM PDT 24
Peak memory 205792 kb
Host smart-d6e43b1f-498d-4133-8228-23d86af041f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1377554262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.1377554262
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.1780761681
Short name T2615
Test name
Test status
Simulation time 38489330 ps
CPU time 0.69 seconds
Started Jun 26 04:43:49 PM PDT 24
Finished Jun 26 04:43:57 PM PDT 24
Peak memory 205812 kb
Host smart-da26387e-94e3-4945-869f-d2737b1ed5be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1780761681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.1780761681
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.239602236
Short name T2610
Test name
Test status
Simulation time 41634765 ps
CPU time 0.67 seconds
Started Jun 26 04:43:41 PM PDT 24
Finished Jun 26 04:43:49 PM PDT 24
Peak memory 205900 kb
Host smart-5180fba9-8767-4804-aea2-a3877b069a4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=239602236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.239602236
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.1863041532
Short name T311
Test name
Test status
Simulation time 29246613 ps
CPU time 0.67 seconds
Started Jun 26 04:43:44 PM PDT 24
Finished Jun 26 04:43:52 PM PDT 24
Peak memory 205736 kb
Host smart-525f5c9b-a352-4894-be21-50af7ae3a54d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1863041532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.1863041532
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.1028097206
Short name T309
Test name
Test status
Simulation time 41201079 ps
CPU time 0.68 seconds
Started Jun 26 04:43:48 PM PDT 24
Finished Jun 26 04:43:56 PM PDT 24
Peak memory 205812 kb
Host smart-625aae44-f364-4fc2-a92f-8c0e39ef7ed5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1028097206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.1028097206
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1006779690
Short name T316
Test name
Test status
Simulation time 39515518 ps
CPU time 0.67 seconds
Started Jun 26 04:43:42 PM PDT 24
Finished Jun 26 04:43:49 PM PDT 24
Peak memory 205816 kb
Host smart-26dea147-059e-4d55-ad14-c7afdfc9db03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1006779690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.1006779690
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.1368076727
Short name T213
Test name
Test status
Simulation time 34060875 ps
CPU time 0.64 seconds
Started Jun 26 04:43:55 PM PDT 24
Finished Jun 26 04:44:07 PM PDT 24
Peak memory 205792 kb
Host smart-74f99f82-fe1e-4f60-92fe-2fce50d8acf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1368076727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.1368076727
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.3473724766
Short name T2622
Test name
Test status
Simulation time 59518297 ps
CPU time 0.7 seconds
Started Jun 26 04:43:44 PM PDT 24
Finished Jun 26 04:43:52 PM PDT 24
Peak memory 205724 kb
Host smart-beba1082-63d3-47e5-abe9-607df8bc11a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3473724766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.3473724766
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.521963785
Short name T249
Test name
Test status
Simulation time 114663094 ps
CPU time 1.33 seconds
Started Jun 26 04:43:24 PM PDT 24
Finished Jun 26 04:43:32 PM PDT 24
Peak memory 214368 kb
Host smart-8af696c7-1543-499a-ae7f-01f5b2112510
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521963785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev
_csr_mem_rw_with_rand_reset.521963785
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1912959962
Short name T2680
Test name
Test status
Simulation time 71166031 ps
CPU time 1 seconds
Started Jun 26 04:43:22 PM PDT 24
Finished Jun 26 04:43:27 PM PDT 24
Peak memory 206360 kb
Host smart-4fa3eb11-ae41-4a8f-aa6d-5e701bdf840a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1912959962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.1912959962
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2288917150
Short name T2596
Test name
Test status
Simulation time 125677287 ps
CPU time 1.14 seconds
Started Jun 26 04:43:21 PM PDT 24
Finished Jun 26 04:43:26 PM PDT 24
Peak memory 206116 kb
Host smart-a4d39b35-27e0-41ac-bb82-224c7c3affe1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2288917150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.2288917150
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2094881187
Short name T203
Test name
Test status
Simulation time 118238961 ps
CPU time 1.88 seconds
Started Jun 26 04:43:21 PM PDT 24
Finished Jun 26 04:43:27 PM PDT 24
Peak memory 222368 kb
Host smart-6a66ba89-b854-4653-9d67-086b76d37324
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2094881187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.2094881187
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.180025056
Short name T2614
Test name
Test status
Simulation time 161429016 ps
CPU time 1.35 seconds
Started Jun 26 04:43:22 PM PDT 24
Finished Jun 26 04:43:27 PM PDT 24
Peak memory 217100 kb
Host smart-9fe44f9d-bc6f-46e7-a8af-b3c034d12c7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180025056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev
_csr_mem_rw_with_rand_reset.180025056
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1503516371
Short name T286
Test name
Test status
Simulation time 68604203 ps
CPU time 0.91 seconds
Started Jun 26 04:43:24 PM PDT 24
Finished Jun 26 04:43:31 PM PDT 24
Peak memory 206100 kb
Host smart-bdd63578-9986-4522-b2cc-b437e5a34372
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1503516371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.1503516371
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.2987568426
Short name T212
Test name
Test status
Simulation time 54172713 ps
CPU time 0.74 seconds
Started Jun 26 04:43:23 PM PDT 24
Finished Jun 26 04:43:28 PM PDT 24
Peak memory 205928 kb
Host smart-aad55bde-1ab1-47b7-bcc7-c4082b73f136
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2987568426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.2987568426
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3259078504
Short name T2592
Test name
Test status
Simulation time 210915309 ps
CPU time 1.89 seconds
Started Jun 26 04:43:23 PM PDT 24
Finished Jun 26 04:43:30 PM PDT 24
Peak memory 206096 kb
Host smart-a6490be1-0a79-4370-ad25-360899ce228c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3259078504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.3259078504
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1549350528
Short name T243
Test name
Test status
Simulation time 255344005 ps
CPU time 2.95 seconds
Started Jun 26 04:43:23 PM PDT 24
Finished Jun 26 04:43:30 PM PDT 24
Peak memory 221908 kb
Host smart-0037f1cd-9ff1-487f-89fc-4d4a02e02db0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1549350528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1549350528
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1016449528
Short name T253
Test name
Test status
Simulation time 875640727 ps
CPU time 3.47 seconds
Started Jun 26 04:43:21 PM PDT 24
Finished Jun 26 04:43:28 PM PDT 24
Peak memory 206216 kb
Host smart-1dd836fc-4203-453a-91d9-bd6c28388676
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1016449528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.1016449528
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1299637968
Short name T2667
Test name
Test status
Simulation time 136822342 ps
CPU time 1.63 seconds
Started Jun 26 04:43:24 PM PDT 24
Finished Jun 26 04:43:31 PM PDT 24
Peak memory 214372 kb
Host smart-572203b5-94e2-48c4-b41b-83824d945b0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299637968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.1299637968
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.587741059
Short name T281
Test name
Test status
Simulation time 99888729 ps
CPU time 0.86 seconds
Started Jun 26 04:43:21 PM PDT 24
Finished Jun 26 04:43:25 PM PDT 24
Peak memory 205820 kb
Host smart-a6503dcb-1272-4a4d-bd8f-da6c1b1f8ad7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=587741059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.587741059
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.4242855453
Short name T2678
Test name
Test status
Simulation time 34437498 ps
CPU time 0.67 seconds
Started Jun 26 04:43:24 PM PDT 24
Finished Jun 26 04:43:30 PM PDT 24
Peak memory 205828 kb
Host smart-f4823a0b-61d2-4aa2-bec5-25c972d7612c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4242855453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.4242855453
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1326418103
Short name T2657
Test name
Test status
Simulation time 265614940 ps
CPU time 1.79 seconds
Started Jun 26 04:43:23 PM PDT 24
Finished Jun 26 04:43:30 PM PDT 24
Peak memory 206200 kb
Host smart-b142079c-5a95-4362-ad02-7bbc6c15ca15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1326418103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.1326418103
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1410918850
Short name T240
Test name
Test status
Simulation time 59177225 ps
CPU time 1.74 seconds
Started Jun 26 04:43:22 PM PDT 24
Finished Jun 26 04:43:29 PM PDT 24
Peak memory 221804 kb
Host smart-3aa90c83-7344-4569-9507-42c98882ba99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1410918850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.1410918850
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1337136006
Short name T2660
Test name
Test status
Simulation time 555554230 ps
CPU time 3 seconds
Started Jun 26 04:43:21 PM PDT 24
Finished Jun 26 04:43:28 PM PDT 24
Peak memory 206196 kb
Host smart-221ea63e-b565-4410-976a-81007f01b32a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1337136006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.1337136006
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3016851144
Short name T2626
Test name
Test status
Simulation time 163005342 ps
CPU time 2.03 seconds
Started Jun 26 04:43:23 PM PDT 24
Finished Jun 26 04:43:30 PM PDT 24
Peak memory 213696 kb
Host smart-8f15a48a-143f-4380-985f-1b6ff2551358
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016851144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.3016851144
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.3218963272
Short name T273
Test name
Test status
Simulation time 47502664 ps
CPU time 0.75 seconds
Started Jun 26 04:43:22 PM PDT 24
Finished Jun 26 04:43:27 PM PDT 24
Peak memory 205832 kb
Host smart-2709361f-43ca-486a-9ac3-c60f977764f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3218963272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.3218963272
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2220835806
Short name T2635
Test name
Test status
Simulation time 44922636 ps
CPU time 0.67 seconds
Started Jun 26 04:43:23 PM PDT 24
Finished Jun 26 04:43:28 PM PDT 24
Peak memory 204812 kb
Host smart-0d22bedd-a25c-4e48-be1f-cba90ad8d6a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2220835806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.2220835806
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1192338681
Short name T2663
Test name
Test status
Simulation time 174412780 ps
CPU time 1.69 seconds
Started Jun 26 04:43:25 PM PDT 24
Finished Jun 26 04:43:34 PM PDT 24
Peak memory 206076 kb
Host smart-717d34e7-1e6b-4f1f-bd87-35467868bd17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1192338681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.1192338681
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2438400574
Short name T2617
Test name
Test status
Simulation time 55733482 ps
CPU time 1.33 seconds
Started Jun 26 04:43:24 PM PDT 24
Finished Jun 26 04:43:31 PM PDT 24
Peak memory 206252 kb
Host smart-3479f5ed-f1a9-4f51-8a8c-1100c7d821c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2438400574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.2438400574
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.2418742074
Short name T325
Test name
Test status
Simulation time 301341687 ps
CPU time 2.51 seconds
Started Jun 26 04:43:22 PM PDT 24
Finished Jun 26 04:43:29 PM PDT 24
Peak memory 206172 kb
Host smart-90aa8d20-df12-4f2b-9203-9b74208bb62d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2418742074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.2418742074
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3000786563
Short name T2644
Test name
Test status
Simulation time 252941912 ps
CPU time 2 seconds
Started Jun 26 04:43:23 PM PDT 24
Finished Jun 26 04:43:31 PM PDT 24
Peak memory 214360 kb
Host smart-f56e7fb0-eb92-40e8-a0b3-ef162aaa96f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000786563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.3000786563
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.447316589
Short name T2624
Test name
Test status
Simulation time 73246931 ps
CPU time 0.88 seconds
Started Jun 26 04:43:22 PM PDT 24
Finished Jun 26 04:43:27 PM PDT 24
Peak memory 205832 kb
Host smart-33623b92-a75a-4f96-b7f8-e26db04c1003
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=447316589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.447316589
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.2415784950
Short name T210
Test name
Test status
Simulation time 62232425 ps
CPU time 0.72 seconds
Started Jun 26 04:43:23 PM PDT 24
Finished Jun 26 04:43:29 PM PDT 24
Peak memory 205828 kb
Host smart-100a1328-165d-400e-b3af-c8189d5a23ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2415784950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.2415784950
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.504291556
Short name T207
Test name
Test status
Simulation time 182608541 ps
CPU time 1.78 seconds
Started Jun 26 04:43:21 PM PDT 24
Finished Jun 26 04:43:26 PM PDT 24
Peak memory 206152 kb
Host smart-940ce39c-5a28-47f9-9f9f-dbe85117c9ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=504291556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.504291556
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3340609476
Short name T2637
Test name
Test status
Simulation time 151219216 ps
CPU time 2.94 seconds
Started Jun 26 04:43:23 PM PDT 24
Finished Jun 26 04:43:31 PM PDT 24
Peak memory 222044 kb
Host smart-316b7916-f6ad-47cb-9ead-28e76981ddd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3340609476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.3340609476
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.453233720
Short name T321
Test name
Test status
Simulation time 519769041 ps
CPU time 2.86 seconds
Started Jun 26 04:43:24 PM PDT 24
Finished Jun 26 04:43:32 PM PDT 24
Peak memory 206136 kb
Host smart-92979d76-ac3f-443f-a39e-67cb65b720a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=453233720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.453233720
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.1435163010
Short name T745
Test name
Test status
Simulation time 4247898724 ps
CPU time 4.92 seconds
Started Jun 26 05:09:11 PM PDT 24
Finished Jun 26 05:09:16 PM PDT 24
Peak memory 206432 kb
Host smart-b4b0377d-1beb-4e3d-b251-2e21b0a61919
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1435163010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.1435163010
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.863771112
Short name T1954
Test name
Test status
Simulation time 13335053590 ps
CPU time 14.18 seconds
Started Jun 26 05:09:16 PM PDT 24
Finished Jun 26 05:09:31 PM PDT 24
Peak memory 206348 kb
Host smart-bf70d6e9-73be-4249-8180-4cdaad2677a9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=863771112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.863771112
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.3050606408
Short name T1771
Test name
Test status
Simulation time 23341928287 ps
CPU time 25.7 seconds
Started Jun 26 05:09:18 PM PDT 24
Finished Jun 26 05:09:44 PM PDT 24
Peak memory 206496 kb
Host smart-46a303bf-de95-4f7f-b48b-d6a38c626106
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3050606408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.3050606408
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.3226422078
Short name T396
Test name
Test status
Simulation time 162130788 ps
CPU time 0.76 seconds
Started Jun 26 05:09:17 PM PDT 24
Finished Jun 26 05:09:19 PM PDT 24
Peak memory 206116 kb
Host smart-faf0b4fe-0e8e-4bfb-b32f-20445477d721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32264
22078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.3226422078
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.583454565
Short name T2082
Test name
Test status
Simulation time 178564588 ps
CPU time 0.81 seconds
Started Jun 26 05:09:17 PM PDT 24
Finished Jun 26 05:09:18 PM PDT 24
Peak memory 206176 kb
Host smart-a3f0d37c-8ff0-4761-b6cc-c906acade590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58345
4565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.583454565
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.4233708382
Short name T190
Test name
Test status
Simulation time 351705829 ps
CPU time 1.25 seconds
Started Jun 26 05:09:17 PM PDT 24
Finished Jun 26 05:09:20 PM PDT 24
Peak memory 206116 kb
Host smart-485d5e7e-d72d-4d75-ad90-9f413b6c596f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42337
08382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.4233708382
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.1351538661
Short name T1666
Test name
Test status
Simulation time 360674443 ps
CPU time 0.99 seconds
Started Jun 26 05:09:25 PM PDT 24
Finished Jun 26 05:09:26 PM PDT 24
Peak memory 206140 kb
Host smart-b5d5a240-5cd3-4f38-a135-0161176d410f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13515
38661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.1351538661
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.1402475726
Short name T1733
Test name
Test status
Simulation time 6530882870 ps
CPU time 14.94 seconds
Started Jun 26 05:09:26 PM PDT 24
Finished Jun 26 05:09:42 PM PDT 24
Peak memory 206496 kb
Host smart-1b8bada8-6dd3-47f4-afc8-fb8281552e10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14024
75726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.1402475726
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.813678021
Short name T2000
Test name
Test status
Simulation time 513593040 ps
CPU time 1.45 seconds
Started Jun 26 05:09:26 PM PDT 24
Finished Jun 26 05:09:29 PM PDT 24
Peak memory 206120 kb
Host smart-f52f8bcc-75ab-4b33-86a6-639a46f97d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81367
8021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.813678021
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.4205591792
Short name T2314
Test name
Test status
Simulation time 143858001 ps
CPU time 0.77 seconds
Started Jun 26 05:09:27 PM PDT 24
Finished Jun 26 05:09:28 PM PDT 24
Peak memory 206132 kb
Host smart-3e239dce-39d7-46af-a473-0d61fe5d859e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42055
91792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.4205591792
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.874122716
Short name T2515
Test name
Test status
Simulation time 5107758128 ps
CPU time 127.04 seconds
Started Jun 26 05:09:17 PM PDT 24
Finished Jun 26 05:11:25 PM PDT 24
Peak memory 206528 kb
Host smart-42b6f5ff-c6b4-486a-ac83-d2465061efbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87412
2716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.874122716
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_enable.3430024429
Short name T1127
Test name
Test status
Simulation time 43297033 ps
CPU time 0.65 seconds
Started Jun 26 05:09:33 PM PDT 24
Finished Jun 26 05:09:34 PM PDT 24
Peak memory 206200 kb
Host smart-6c517e88-7cb4-48b7-b5b0-7679c5f5317d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34300
24429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.3430024429
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.3203725637
Short name T620
Test name
Test status
Simulation time 915973973 ps
CPU time 2.19 seconds
Started Jun 26 05:09:26 PM PDT 24
Finished Jun 26 05:09:29 PM PDT 24
Peak memory 206452 kb
Host smart-ddf7b823-4ced-4712-b807-f5fa129cf425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32037
25637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.3203725637
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.2343656248
Short name T2196
Test name
Test status
Simulation time 327720656 ps
CPU time 2.3 seconds
Started Jun 26 05:09:33 PM PDT 24
Finished Jun 26 05:09:37 PM PDT 24
Peak memory 206404 kb
Host smart-f26ecf4a-64a9-4c23-8a3f-ac18f321a2b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23436
56248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.2343656248
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.1868379262
Short name T469
Test name
Test status
Simulation time 246222380 ps
CPU time 0.94 seconds
Started Jun 26 05:10:12 PM PDT 24
Finished Jun 26 05:10:14 PM PDT 24
Peak memory 206128 kb
Host smart-ff40bb90-5c16-4cf0-9602-d056b0d4a816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18683
79262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.1868379262
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.2750704057
Short name T810
Test name
Test status
Simulation time 157766348 ps
CPU time 0.81 seconds
Started Jun 26 05:10:05 PM PDT 24
Finished Jun 26 05:10:07 PM PDT 24
Peak memory 206392 kb
Host smart-0b08e12a-791b-4132-8162-d0aa2eec1199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27507
04057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.2750704057
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.1771369891
Short name T1236
Test name
Test status
Simulation time 235294789 ps
CPU time 0.89 seconds
Started Jun 26 05:09:32 PM PDT 24
Finished Jun 26 05:09:33 PM PDT 24
Peak memory 206192 kb
Host smart-a97fcba2-e861-4ea1-b025-e068c9eba6cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17713
69891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.1771369891
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_invalid_sync.3513589235
Short name T2048
Test name
Test status
Simulation time 8837864736 ps
CPU time 70.46 seconds
Started Jun 26 05:09:33 PM PDT 24
Finished Jun 26 05:10:44 PM PDT 24
Peak memory 206524 kb
Host smart-454b05f0-cd63-4302-a1d0-f7f5b03e3059
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3513589235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.3513589235
Directory /workspace/0.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.2179414335
Short name T2347
Test name
Test status
Simulation time 177999170 ps
CPU time 0.85 seconds
Started Jun 26 05:09:33 PM PDT 24
Finished Jun 26 05:09:35 PM PDT 24
Peak memory 206188 kb
Host smart-893e6b60-1307-4f6e-8912-03509e524938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21794
14335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.2179414335
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.587284454
Short name T64
Test name
Test status
Simulation time 454207326 ps
CPU time 1.2 seconds
Started Jun 26 05:09:33 PM PDT 24
Finished Jun 26 05:09:34 PM PDT 24
Peak memory 206116 kb
Host smart-f71d0e82-4a69-408a-a96a-ca97b3945a4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58728
4454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.587284454
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.1236489788
Short name T1770
Test name
Test status
Simulation time 23384099262 ps
CPU time 22.03 seconds
Started Jun 26 05:09:31 PM PDT 24
Finished Jun 26 05:09:53 PM PDT 24
Peak memory 206236 kb
Host smart-5aabc7ad-94b3-4bca-a7ac-f39ece183f11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12364
89788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.1236489788
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.4071808843
Short name T1981
Test name
Test status
Simulation time 3342596698 ps
CPU time 4.03 seconds
Started Jun 26 05:09:33 PM PDT 24
Finished Jun 26 05:09:38 PM PDT 24
Peak memory 206268 kb
Host smart-cead2142-b417-4d34-8304-02e1c3558c49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40718
08843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.4071808843
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.3220248163
Short name T2466
Test name
Test status
Simulation time 10261167022 ps
CPU time 276.65 seconds
Started Jun 26 05:09:33 PM PDT 24
Finished Jun 26 05:14:10 PM PDT 24
Peak memory 206572 kb
Host smart-7ac770ca-a296-43f7-a2c9-04310f3747da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32202
48163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.3220248163
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.2475663098
Short name T897
Test name
Test status
Simulation time 3920242820 ps
CPU time 36.27 seconds
Started Jun 26 05:09:39 PM PDT 24
Finished Jun 26 05:10:16 PM PDT 24
Peak memory 206436 kb
Host smart-dbc384b6-b2fa-48d8-b254-c1ac7d057845
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2475663098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.2475663098
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.1580988329
Short name T2574
Test name
Test status
Simulation time 291719392 ps
CPU time 0.94 seconds
Started Jun 26 05:10:15 PM PDT 24
Finished Jun 26 05:10:17 PM PDT 24
Peak memory 206116 kb
Host smart-eb3837bd-b16d-4da7-a2ca-b6bda5edbe5b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1580988329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.1580988329
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.942519944
Short name T1132
Test name
Test status
Simulation time 187150795 ps
CPU time 0.85 seconds
Started Jun 26 05:09:33 PM PDT 24
Finished Jun 26 05:09:35 PM PDT 24
Peak memory 206180 kb
Host smart-7918d116-62f4-4f0f-bf84-0e1ffc63564d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94251
9944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.942519944
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.3436879088
Short name T805
Test name
Test status
Simulation time 3706846592 ps
CPU time 97.15 seconds
Started Jun 26 05:09:39 PM PDT 24
Finished Jun 26 05:11:17 PM PDT 24
Peak memory 206388 kb
Host smart-7f333720-bec3-46fb-90ea-ed5fb3d356bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34368
79088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.3436879088
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.1308921938
Short name T1327
Test name
Test status
Simulation time 5574982906 ps
CPU time 156.95 seconds
Started Jun 26 05:09:44 PM PDT 24
Finished Jun 26 05:12:21 PM PDT 24
Peak memory 206460 kb
Host smart-93938d20-96c0-4744-b419-724a6662d6bf
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1308921938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.1308921938
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.3482371206
Short name T898
Test name
Test status
Simulation time 158161139 ps
CPU time 0.79 seconds
Started Jun 26 05:10:12 PM PDT 24
Finished Jun 26 05:10:14 PM PDT 24
Peak memory 206188 kb
Host smart-9621956f-ceb3-4196-a1b5-2ef36df8a2b2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3482371206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.3482371206
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.1720338142
Short name T1396
Test name
Test status
Simulation time 206191741 ps
CPU time 0.84 seconds
Started Jun 26 05:09:41 PM PDT 24
Finished Jun 26 05:09:42 PM PDT 24
Peak memory 206212 kb
Host smart-385bc603-04ae-4a47-8851-2792d34c33fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17203
38142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.1720338142
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.3156321425
Short name T65
Test name
Test status
Simulation time 447420267 ps
CPU time 1.34 seconds
Started Jun 26 05:09:40 PM PDT 24
Finished Jun 26 05:09:43 PM PDT 24
Peak memory 206144 kb
Host smart-be3aca46-4cfb-4386-985f-6ff9cd50beb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31563
21425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.3156321425
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.4013478096
Short name T588
Test name
Test status
Simulation time 227126562 ps
CPU time 0.9 seconds
Started Jun 26 05:09:40 PM PDT 24
Finished Jun 26 05:09:42 PM PDT 24
Peak memory 206224 kb
Host smart-aec3b49d-ce45-4eb9-8423-26311aa4f945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40134
78096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.4013478096
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.3201770046
Short name T1744
Test name
Test status
Simulation time 228962489 ps
CPU time 0.86 seconds
Started Jun 26 05:09:40 PM PDT 24
Finished Jun 26 05:09:42 PM PDT 24
Peak memory 206400 kb
Host smart-1a9f4df4-be35-4685-9838-858972bdc7e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32017
70046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.3201770046
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.1630374528
Short name T370
Test name
Test status
Simulation time 232363544 ps
CPU time 0.83 seconds
Started Jun 26 05:09:44 PM PDT 24
Finished Jun 26 05:09:46 PM PDT 24
Peak memory 206132 kb
Host smart-34047df1-2197-477a-90ce-fbc546d5fe1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16303
74528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.1630374528
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.2964425435
Short name T1005
Test name
Test status
Simulation time 191457203 ps
CPU time 0.8 seconds
Started Jun 26 05:10:03 PM PDT 24
Finished Jun 26 05:10:05 PM PDT 24
Peak memory 206224 kb
Host smart-0922fd1d-80c0-431f-b35e-712d0d0d03c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29644
25435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.2964425435
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.1172805188
Short name T938
Test name
Test status
Simulation time 163721752 ps
CPU time 0.79 seconds
Started Jun 26 05:09:40 PM PDT 24
Finished Jun 26 05:09:41 PM PDT 24
Peak memory 206212 kb
Host smart-d4b87843-b57c-43c4-8ebe-12e28125cb87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11728
05188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.1172805188
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.2792259249
Short name T2387
Test name
Test status
Simulation time 236282795 ps
CPU time 0.95 seconds
Started Jun 26 05:09:39 PM PDT 24
Finished Jun 26 05:09:41 PM PDT 24
Peak memory 206136 kb
Host smart-e57496f7-119c-4770-a252-ea8e922387bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27922
59249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.2792259249
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.1263450703
Short name T2447
Test name
Test status
Simulation time 276824312 ps
CPU time 0.93 seconds
Started Jun 26 05:09:45 PM PDT 24
Finished Jun 26 05:09:47 PM PDT 24
Peak memory 206136 kb
Host smart-dfb66fa2-5953-4340-abfa-555341ca68d0
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1263450703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.1263450703
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.4065762658
Short name T209
Test name
Test status
Simulation time 223818822 ps
CPU time 0.92 seconds
Started Jun 26 05:09:40 PM PDT 24
Finished Jun 26 05:09:42 PM PDT 24
Peak memory 206212 kb
Host smart-3c24ebc1-4dda-4403-a85d-d59337a5a19e
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4065762658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.4065762658
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.853711290
Short name T24
Test name
Test status
Simulation time 48307841 ps
CPU time 0.64 seconds
Started Jun 26 05:10:05 PM PDT 24
Finished Jun 26 05:10:06 PM PDT 24
Peak memory 206204 kb
Host smart-7e48081b-d914-42f8-83ec-423ac1eec324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85371
1290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.853711290
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.2514593902
Short name T2457
Test name
Test status
Simulation time 15336247778 ps
CPU time 34.28 seconds
Started Jun 26 05:09:47 PM PDT 24
Finished Jun 26 05:10:22 PM PDT 24
Peak memory 206480 kb
Host smart-a9bce119-91aa-4fbb-8ac3-d09797069bdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25145
93902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.2514593902
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.348243517
Short name T2243
Test name
Test status
Simulation time 201361298 ps
CPU time 0.84 seconds
Started Jun 26 05:09:47 PM PDT 24
Finished Jun 26 05:09:49 PM PDT 24
Peak memory 206208 kb
Host smart-52687e2e-9e2b-49f5-8dad-e64a51d83b3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34824
3517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.348243517
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.3786364916
Short name T220
Test name
Test status
Simulation time 254795483 ps
CPU time 0.96 seconds
Started Jun 26 05:09:48 PM PDT 24
Finished Jun 26 05:09:50 PM PDT 24
Peak memory 206216 kb
Host smart-3b5e36eb-126d-4084-9833-7e4c9ad24116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37863
64916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.3786364916
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.827993553
Short name T179
Test name
Test status
Simulation time 9670280856 ps
CPU time 83.9 seconds
Started Jun 26 05:09:58 PM PDT 24
Finished Jun 26 05:11:22 PM PDT 24
Peak memory 206548 kb
Host smart-a47105ac-af4d-42de-afc1-28c1476cce87
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=827993553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.827993553
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.571778648
Short name T2421
Test name
Test status
Simulation time 7087356733 ps
CPU time 177.93 seconds
Started Jun 26 05:09:55 PM PDT 24
Finished Jun 26 05:12:53 PM PDT 24
Peak memory 206496 kb
Host smart-6a3ac932-306b-4df8-a2c1-37acdab9c76c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=571778648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.571778648
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.4251118633
Short name T505
Test name
Test status
Simulation time 12584420573 ps
CPU time 258.3 seconds
Started Jun 26 05:09:55 PM PDT 24
Finished Jun 26 05:14:14 PM PDT 24
Peak memory 206464 kb
Host smart-98b9b5fd-55c2-4380-800b-dded429f4126
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4251118633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.4251118633
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.154689260
Short name T2317
Test name
Test status
Simulation time 177423897 ps
CPU time 0.84 seconds
Started Jun 26 05:10:11 PM PDT 24
Finished Jun 26 05:10:12 PM PDT 24
Peak memory 206136 kb
Host smart-8da0fe2c-6b27-46ba-be60-77bdf6c21c2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15468
9260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.154689260
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.95558490
Short name T1342
Test name
Test status
Simulation time 151735651 ps
CPU time 0.77 seconds
Started Jun 26 05:09:56 PM PDT 24
Finished Jun 26 05:09:57 PM PDT 24
Peak memory 206212 kb
Host smart-027fba98-5918-4cc6-9880-b0d476b2daeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95558
490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.95558490
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.3493234139
Short name T1107
Test name
Test status
Simulation time 171038467 ps
CPU time 0.83 seconds
Started Jun 26 05:09:55 PM PDT 24
Finished Jun 26 05:09:57 PM PDT 24
Peak memory 206232 kb
Host smart-1ff97c14-e4f2-4fbb-a6cc-fd3032564222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34932
34139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.3493234139
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.3310571380
Short name T2366
Test name
Test status
Simulation time 411243619 ps
CPU time 1.48 seconds
Started Jun 26 05:09:55 PM PDT 24
Finished Jun 26 05:09:57 PM PDT 24
Peak memory 206176 kb
Host smart-48d5974f-2423-45ea-affb-fd6cd82fe581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33105
71380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.3310571380
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.3557640288
Short name T1560
Test name
Test status
Simulation time 155154724 ps
CPU time 0.77 seconds
Started Jun 26 05:10:05 PM PDT 24
Finished Jun 26 05:10:07 PM PDT 24
Peak memory 206124 kb
Host smart-b272d6d7-38d8-4454-81e0-1b9b2b0dc3ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35576
40288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.3557640288
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.3120924071
Short name T1922
Test name
Test status
Simulation time 224336534 ps
CPU time 0.85 seconds
Started Jun 26 05:10:06 PM PDT 24
Finished Jun 26 05:10:07 PM PDT 24
Peak memory 206192 kb
Host smart-14b50af9-1172-4be7-8963-54fac430a622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31209
24071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.3120924071
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.635423336
Short name T1619
Test name
Test status
Simulation time 216626350 ps
CPU time 0.93 seconds
Started Jun 26 05:09:54 PM PDT 24
Finished Jun 26 05:09:56 PM PDT 24
Peak memory 206108 kb
Host smart-fa5582b8-0cb0-4ebe-a01b-3a9e7995d0c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63542
3336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.635423336
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.246482601
Short name T1286
Test name
Test status
Simulation time 6300474999 ps
CPU time 42.9 seconds
Started Jun 26 05:12:08 PM PDT 24
Finished Jun 26 05:12:52 PM PDT 24
Peak memory 206440 kb
Host smart-6e5326f0-112d-4a3d-9c30-802bf8adb5ef
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=246482601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.246482601
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.57181448
Short name T1218
Test name
Test status
Simulation time 195638549 ps
CPU time 0.81 seconds
Started Jun 26 05:10:03 PM PDT 24
Finished Jun 26 05:10:05 PM PDT 24
Peak memory 206148 kb
Host smart-40264979-76cb-4732-a7a9-8f986f16c982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57181
448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.57181448
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.3643257281
Short name T939
Test name
Test status
Simulation time 172403597 ps
CPU time 0.79 seconds
Started Jun 26 05:09:57 PM PDT 24
Finished Jun 26 05:09:58 PM PDT 24
Peak memory 206124 kb
Host smart-80934ada-7708-4711-83bc-c498fff7eb28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36432
57281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.3643257281
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.2178976320
Short name T157
Test name
Test status
Simulation time 5429817689 ps
CPU time 53.21 seconds
Started Jun 26 05:10:05 PM PDT 24
Finished Jun 26 05:10:59 PM PDT 24
Peak memory 206528 kb
Host smart-93a28f4b-e631-4f3d-9698-7979c2c33b83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21789
76320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.2178976320
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.51886863
Short name T883
Test name
Test status
Simulation time 4031260538 ps
CPU time 4.79 seconds
Started Jun 26 05:10:12 PM PDT 24
Finished Jun 26 05:10:18 PM PDT 24
Peak memory 206248 kb
Host smart-83dcbad7-7f18-48fa-820b-b90300e23995
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=51886863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.51886863
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.2068858993
Short name T1042
Test name
Test status
Simulation time 13400125815 ps
CPU time 11.44 seconds
Started Jun 26 05:10:12 PM PDT 24
Finished Jun 26 05:10:24 PM PDT 24
Peak memory 206484 kb
Host smart-5dad68cc-0b66-44f3-83fb-7c1deb52e00a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2068858993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.2068858993
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.2446101060
Short name T1070
Test name
Test status
Simulation time 23374738323 ps
CPU time 24.53 seconds
Started Jun 26 05:10:12 PM PDT 24
Finished Jun 26 05:10:37 PM PDT 24
Peak memory 206296 kb
Host smart-19662530-eab5-4b63-97e4-74539c8295df
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2446101060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.2446101060
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.2803711639
Short name T783
Test name
Test status
Simulation time 155806203 ps
CPU time 0.78 seconds
Started Jun 26 05:10:13 PM PDT 24
Finished Jun 26 05:10:14 PM PDT 24
Peak memory 206140 kb
Host smart-1caa91db-dafb-414b-b28b-55e11f80bbe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28037
11639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.2803711639
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.966179652
Short name T794
Test name
Test status
Simulation time 138093964 ps
CPU time 0.73 seconds
Started Jun 26 05:10:11 PM PDT 24
Finished Jun 26 05:10:12 PM PDT 24
Peak memory 206228 kb
Host smart-6b510fa2-d0ff-4172-b6ac-186c42b50c3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96617
9652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.966179652
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.3036616955
Short name T1993
Test name
Test status
Simulation time 514661546 ps
CPU time 1.49 seconds
Started Jun 26 05:10:10 PM PDT 24
Finished Jun 26 05:10:12 PM PDT 24
Peak memory 206188 kb
Host smart-dc0ed2a2-6148-43b3-abba-540fdc4b297d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30366
16955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.3036616955
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.2870025649
Short name T1782
Test name
Test status
Simulation time 637437755 ps
CPU time 1.6 seconds
Started Jun 26 05:10:18 PM PDT 24
Finished Jun 26 05:10:20 PM PDT 24
Peak memory 206144 kb
Host smart-e2b66f60-0852-4afe-b334-e1409635d1d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28700
25649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.2870025649
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.2101192574
Short name T2433
Test name
Test status
Simulation time 15836936026 ps
CPU time 28.84 seconds
Started Jun 26 05:10:22 PM PDT 24
Finished Jun 26 05:10:51 PM PDT 24
Peak memory 206720 kb
Host smart-8de6ef0f-2020-47f9-b47e-fbd7e0bbdded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21011
92574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.2101192574
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.4149489032
Short name T1416
Test name
Test status
Simulation time 497713645 ps
CPU time 1.4 seconds
Started Jun 26 05:10:21 PM PDT 24
Finished Jun 26 05:10:24 PM PDT 24
Peak memory 206240 kb
Host smart-164d138d-4d53-4987-aa3f-0f80eae87789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41494
89032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.4149489032
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.496216677
Short name T1689
Test name
Test status
Simulation time 136982006 ps
CPU time 0.79 seconds
Started Jun 26 05:10:20 PM PDT 24
Finished Jun 26 05:10:22 PM PDT 24
Peak memory 206396 kb
Host smart-54e5c629-409a-458c-9751-8e997251a68a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49621
6677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.496216677
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.3277476364
Short name T2303
Test name
Test status
Simulation time 41940064 ps
CPU time 0.64 seconds
Started Jun 26 05:10:18 PM PDT 24
Finished Jun 26 05:10:19 PM PDT 24
Peak memory 206188 kb
Host smart-88c8bb3d-60bd-4fb8-8402-9ff736b973b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32774
76364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.3277476364
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.138885418
Short name T1313
Test name
Test status
Simulation time 321789933 ps
CPU time 1.87 seconds
Started Jun 26 05:10:20 PM PDT 24
Finished Jun 26 05:10:23 PM PDT 24
Peak memory 206468 kb
Host smart-c34b55b7-d688-416b-956f-4c7892f45ebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13888
5418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.138885418
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.2306463301
Short name T379
Test name
Test status
Simulation time 152961427 ps
CPU time 0.77 seconds
Started Jun 26 05:10:40 PM PDT 24
Finished Jun 26 05:10:42 PM PDT 24
Peak memory 206124 kb
Host smart-635ab159-ef95-4977-8c88-f8c01ff14cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23064
63301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.2306463301
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.3935908813
Short name T2558
Test name
Test status
Simulation time 218844353 ps
CPU time 0.89 seconds
Started Jun 26 05:10:18 PM PDT 24
Finished Jun 26 05:10:20 PM PDT 24
Peak memory 206192 kb
Host smart-fe51b232-5a94-47d6-bfce-f26d6961058f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39359
08813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.3935908813
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.4185367757
Short name T2523
Test name
Test status
Simulation time 10101623420 ps
CPU time 264.3 seconds
Started Jun 26 05:10:21 PM PDT 24
Finished Jun 26 05:14:46 PM PDT 24
Peak memory 206524 kb
Host smart-c24cc394-e121-483d-821c-02ddd8ddb57a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4185367757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.4185367757
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.1858480408
Short name T1618
Test name
Test status
Simulation time 208890820 ps
CPU time 0.88 seconds
Started Jun 26 05:10:18 PM PDT 24
Finished Jun 26 05:10:20 PM PDT 24
Peak memory 206172 kb
Host smart-d23356cf-5cef-4925-b231-84d0827c4769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18584
80408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.1858480408
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.1535148363
Short name T748
Test name
Test status
Simulation time 23317470717 ps
CPU time 27.45 seconds
Started Jun 26 05:10:20 PM PDT 24
Finished Jun 26 05:10:48 PM PDT 24
Peak memory 206312 kb
Host smart-294cc122-9170-41af-bcea-4db834e1fc50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15351
48363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.1535148363
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.807796986
Short name T814
Test name
Test status
Simulation time 3271912713 ps
CPU time 3.54 seconds
Started Jun 26 05:10:19 PM PDT 24
Finished Jun 26 05:10:24 PM PDT 24
Peak memory 206236 kb
Host smart-1cbb11d0-1a9c-464f-9968-27d539f0aa71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80779
6986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.807796986
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.3557695339
Short name T1900
Test name
Test status
Simulation time 11272004425 ps
CPU time 76.89 seconds
Started Jun 26 05:10:21 PM PDT 24
Finished Jun 26 05:11:38 PM PDT 24
Peak memory 206416 kb
Host smart-224c4494-2a2d-4157-9d95-d0d1dee02f1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35576
95339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.3557695339
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.841787290
Short name T2105
Test name
Test status
Simulation time 4066500013 ps
CPU time 35.85 seconds
Started Jun 26 05:10:26 PM PDT 24
Finished Jun 26 05:11:03 PM PDT 24
Peak memory 206460 kb
Host smart-4fed4f00-bb20-43d5-9226-5db2d3b01995
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=841787290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.841787290
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.1013426723
Short name T110
Test name
Test status
Simulation time 289845742 ps
CPU time 0.94 seconds
Started Jun 26 05:10:48 PM PDT 24
Finished Jun 26 05:10:50 PM PDT 24
Peak memory 206048 kb
Host smart-dd166220-3127-48fe-988f-d358ec93ebcc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1013426723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.1013426723
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.1757683905
Short name T599
Test name
Test status
Simulation time 203318070 ps
CPU time 0.84 seconds
Started Jun 26 05:10:19 PM PDT 24
Finished Jun 26 05:10:21 PM PDT 24
Peak memory 206212 kb
Host smart-30e1cdba-e531-4fbb-84c9-8f965e3a089f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17576
83905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.1757683905
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.1133539195
Short name T1742
Test name
Test status
Simulation time 4922608918 ps
CPU time 47.79 seconds
Started Jun 26 05:10:18 PM PDT 24
Finished Jun 26 05:11:06 PM PDT 24
Peak memory 206596 kb
Host smart-70fe68b9-59eb-4e07-b550-358715cf7a26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11335
39195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.1133539195
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.1462394264
Short name T1970
Test name
Test status
Simulation time 4092149839 ps
CPU time 111.11 seconds
Started Jun 26 05:10:19 PM PDT 24
Finished Jun 26 05:12:12 PM PDT 24
Peak memory 206448 kb
Host smart-06c338ac-7ee2-4c14-9ec5-b028be536049
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1462394264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.1462394264
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.2858531044
Short name T1426
Test name
Test status
Simulation time 214661787 ps
CPU time 0.83 seconds
Started Jun 26 05:10:50 PM PDT 24
Finished Jun 26 05:10:52 PM PDT 24
Peak memory 206248 kb
Host smart-205da393-e113-405f-9bb2-69a5f6d7a9e9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2858531044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.2858531044
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.3906008320
Short name T1911
Test name
Test status
Simulation time 155740112 ps
CPU time 0.78 seconds
Started Jun 26 05:10:20 PM PDT 24
Finished Jun 26 05:10:22 PM PDT 24
Peak memory 206232 kb
Host smart-79e16cc7-2868-43c8-abb8-7db06fc3f084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39060
08320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.3906008320
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.3865987485
Short name T130
Test name
Test status
Simulation time 213831110 ps
CPU time 0.88 seconds
Started Jun 26 05:10:25 PM PDT 24
Finished Jun 26 05:10:27 PM PDT 24
Peak memory 206152 kb
Host smart-b4af773d-9a15-4c32-9a21-a73e26f4795b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38659
87485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.3865987485
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.3234861307
Short name T387
Test name
Test status
Simulation time 228585509 ps
CPU time 0.89 seconds
Started Jun 26 05:10:24 PM PDT 24
Finished Jun 26 05:10:26 PM PDT 24
Peak memory 206224 kb
Host smart-38b144ac-474b-41a9-bb95-16d370c48331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32348
61307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.3234861307
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.3194180109
Short name T655
Test name
Test status
Simulation time 161224181 ps
CPU time 0.79 seconds
Started Jun 26 05:10:26 PM PDT 24
Finished Jun 26 05:10:28 PM PDT 24
Peak memory 206232 kb
Host smart-9a66b63e-400d-4fd9-a5ad-a0275005d58a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31941
80109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.3194180109
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.1318554729
Short name T1323
Test name
Test status
Simulation time 165850852 ps
CPU time 0.78 seconds
Started Jun 26 05:10:27 PM PDT 24
Finished Jun 26 05:10:28 PM PDT 24
Peak memory 206132 kb
Host smart-cb3dc70b-d51b-4969-9969-8840c2a7f734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13185
54729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.1318554729
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.1720758770
Short name T1712
Test name
Test status
Simulation time 186586333 ps
CPU time 0.78 seconds
Started Jun 26 05:10:40 PM PDT 24
Finished Jun 26 05:10:42 PM PDT 24
Peak memory 206116 kb
Host smart-2e1467d2-b4be-418d-99a2-80411bd90307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17207
58770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.1720758770
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.2767304330
Short name T1501
Test name
Test status
Simulation time 188592724 ps
CPU time 0.88 seconds
Started Jun 26 05:10:26 PM PDT 24
Finished Jun 26 05:10:28 PM PDT 24
Peak memory 206160 kb
Host smart-f0fe038b-5776-4a2a-8ae4-4e296a554ea7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2767304330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.2767304330
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.996925763
Short name T521
Test name
Test status
Simulation time 190517652 ps
CPU time 0.87 seconds
Started Jun 26 05:10:26 PM PDT 24
Finished Jun 26 05:10:28 PM PDT 24
Peak memory 206232 kb
Host smart-16fd37d3-3a4e-4876-9edf-bf34a960f78a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99692
5763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.996925763
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.3556405384
Short name T1699
Test name
Test status
Simulation time 187983419 ps
CPU time 0.81 seconds
Started Jun 26 05:10:26 PM PDT 24
Finished Jun 26 05:10:28 PM PDT 24
Peak memory 206136 kb
Host smart-96a16feb-c7c5-477a-9853-3f1f0c91b49d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35564
05384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.3556405384
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.3739711596
Short name T1829
Test name
Test status
Simulation time 49757908 ps
CPU time 0.66 seconds
Started Jun 26 05:10:46 PM PDT 24
Finished Jun 26 05:10:48 PM PDT 24
Peak memory 206024 kb
Host smart-40ca823e-6413-495e-9fff-f7fe7413b734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37397
11596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.3739711596
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.4238820181
Short name T1554
Test name
Test status
Simulation time 14335897275 ps
CPU time 34.18 seconds
Started Jun 26 05:10:26 PM PDT 24
Finished Jun 26 05:11:00 PM PDT 24
Peak memory 206484 kb
Host smart-343b76fa-4b2d-48be-ab06-2c5ad3ff7d6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42388
20181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.4238820181
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.311278374
Short name T1152
Test name
Test status
Simulation time 172035490 ps
CPU time 0.84 seconds
Started Jun 26 05:10:23 PM PDT 24
Finished Jun 26 05:10:25 PM PDT 24
Peak memory 206208 kb
Host smart-2ab8d191-5529-48fe-9faf-a9f706129738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31127
8374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.311278374
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.2004463537
Short name T398
Test name
Test status
Simulation time 249050133 ps
CPU time 0.91 seconds
Started Jun 26 05:10:26 PM PDT 24
Finished Jun 26 05:10:28 PM PDT 24
Peak memory 206136 kb
Host smart-9cf6352b-f6b4-480a-96bf-005282d2e5e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20044
63537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.2004463537
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.742686520
Short name T967
Test name
Test status
Simulation time 12173201119 ps
CPU time 80.74 seconds
Started Jun 26 05:10:27 PM PDT 24
Finished Jun 26 05:11:49 PM PDT 24
Peak memory 206572 kb
Host smart-73117a21-ba13-4439-b831-4bfadcc2e6ef
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=742686520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.742686520
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.2360110763
Short name T165
Test name
Test status
Simulation time 11950072487 ps
CPU time 214.53 seconds
Started Jun 26 05:10:26 PM PDT 24
Finished Jun 26 05:14:01 PM PDT 24
Peak memory 206468 kb
Host smart-ddbfaf07-fdec-4b20-a2a6-ee0c50fe828f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2360110763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.2360110763
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.161990427
Short name T197
Test name
Test status
Simulation time 16077906614 ps
CPU time 376.03 seconds
Started Jun 26 05:10:26 PM PDT 24
Finished Jun 26 05:16:44 PM PDT 24
Peak memory 206460 kb
Host smart-ae239868-9373-4f82-b5fd-b46783394468
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=161990427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.161990427
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.3731286052
Short name T1339
Test name
Test status
Simulation time 194774231 ps
CPU time 0.83 seconds
Started Jun 26 05:10:49 PM PDT 24
Finished Jun 26 05:10:50 PM PDT 24
Peak memory 206232 kb
Host smart-5a9b3d5a-9ab3-4721-a414-d59d49c73916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37312
86052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.3731286052
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.23347919
Short name T1767
Test name
Test status
Simulation time 202204731 ps
CPU time 0.85 seconds
Started Jun 26 05:10:37 PM PDT 24
Finished Jun 26 05:10:38 PM PDT 24
Peak memory 206028 kb
Host smart-5e994855-b239-4c59-bcf7-f33beb413fc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23347
919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.23347919
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.3144723320
Short name T1195
Test name
Test status
Simulation time 151493207 ps
CPU time 0.77 seconds
Started Jun 26 05:10:36 PM PDT 24
Finished Jun 26 05:10:38 PM PDT 24
Peak memory 206116 kb
Host smart-0c909d7c-24d1-4d0c-a3f1-5a7fc3da052f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31447
23320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.3144723320
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.1094525857
Short name T2016
Test name
Test status
Simulation time 153024921 ps
CPU time 0.81 seconds
Started Jun 26 05:10:36 PM PDT 24
Finished Jun 26 05:10:37 PM PDT 24
Peak memory 206116 kb
Host smart-e49139a3-9279-431a-9b22-07f4205c5652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10945
25857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.1094525857
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.2834971441
Short name T214
Test name
Test status
Simulation time 1345427512 ps
CPU time 2.13 seconds
Started Jun 26 05:10:49 PM PDT 24
Finished Jun 26 05:10:52 PM PDT 24
Peak memory 225236 kb
Host smart-7393de15-aa07-44ee-91aa-b20269c0b004
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2834971441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.2834971441
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.2420989619
Short name T1309
Test name
Test status
Simulation time 190767984 ps
CPU time 0.8 seconds
Started Jun 26 05:10:47 PM PDT 24
Finished Jun 26 05:10:48 PM PDT 24
Peak memory 206024 kb
Host smart-af090e56-07bd-4610-b280-92abdf41bc56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24209
89619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.2420989619
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.2240872801
Short name T1174
Test name
Test status
Simulation time 189404220 ps
CPU time 0.81 seconds
Started Jun 26 05:10:32 PM PDT 24
Finished Jun 26 05:10:34 PM PDT 24
Peak memory 206112 kb
Host smart-7989a10a-8274-4926-962d-eda0b03de7ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22408
72801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.2240872801
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.3080869053
Short name T1117
Test name
Test status
Simulation time 243111910 ps
CPU time 0.96 seconds
Started Jun 26 05:10:34 PM PDT 24
Finished Jun 26 05:10:35 PM PDT 24
Peak memory 206132 kb
Host smart-ad224f5a-300b-45be-9746-6b6ca1425b38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30808
69053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.3080869053
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.671846957
Short name T668
Test name
Test status
Simulation time 4763032661 ps
CPU time 132.43 seconds
Started Jun 26 05:10:33 PM PDT 24
Finished Jun 26 05:12:46 PM PDT 24
Peak memory 206444 kb
Host smart-9a97f644-5dc6-42c6-b725-dff5cd317213
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=671846957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.671846957
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.2591201543
Short name T2333
Test name
Test status
Simulation time 198473066 ps
CPU time 0.84 seconds
Started Jun 26 05:10:41 PM PDT 24
Finished Jun 26 05:10:43 PM PDT 24
Peak memory 206128 kb
Host smart-6ba9c24c-9f43-4e3a-85f7-6c4dd6b2071f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25912
01543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.2591201543
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.782109102
Short name T2012
Test name
Test status
Simulation time 192234143 ps
CPU time 0.83 seconds
Started Jun 26 05:10:33 PM PDT 24
Finished Jun 26 05:10:34 PM PDT 24
Peak memory 206208 kb
Host smart-b2067493-19b5-40e2-a4b0-d4131bd9f5bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78210
9102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.782109102
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.1568296986
Short name T2211
Test name
Test status
Simulation time 3902455200 ps
CPU time 35.34 seconds
Started Jun 26 05:10:35 PM PDT 24
Finished Jun 26 05:11:11 PM PDT 24
Peak memory 206448 kb
Host smart-751df1cb-1f16-4740-9498-8f026f8933ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15682
96986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.1568296986
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.3829300679
Short name T2311
Test name
Test status
Simulation time 13313134088 ps
CPU time 11.89 seconds
Started Jun 26 05:14:09 PM PDT 24
Finished Jun 26 05:14:22 PM PDT 24
Peak memory 206328 kb
Host smart-389f10b6-b036-4bc6-8b4a-18ae479c0fce
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3829300679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.3829300679
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.685436713
Short name T2174
Test name
Test status
Simulation time 23409482659 ps
CPU time 23.25 seconds
Started Jun 26 05:14:11 PM PDT 24
Finished Jun 26 05:14:37 PM PDT 24
Peak memory 206328 kb
Host smart-33c71d42-677b-40c0-87dc-7b6db517f7f6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=685436713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.685436713
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.3550113302
Short name T1847
Test name
Test status
Simulation time 177935917 ps
CPU time 0.82 seconds
Started Jun 26 05:14:06 PM PDT 24
Finished Jun 26 05:14:08 PM PDT 24
Peak memory 206124 kb
Host smart-63f7accf-a384-4677-9bcf-a71c1b53e43b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35501
13302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.3550113302
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.2295936071
Short name T618
Test name
Test status
Simulation time 145314538 ps
CPU time 0.78 seconds
Started Jun 26 05:14:10 PM PDT 24
Finished Jun 26 05:14:13 PM PDT 24
Peak memory 206164 kb
Host smart-2613930e-f3a9-4093-9190-7d3fd5f7f2b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22959
36071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.2295936071
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.445212559
Short name T2463
Test name
Test status
Simulation time 302850147 ps
CPU time 1.17 seconds
Started Jun 26 05:14:09 PM PDT 24
Finished Jun 26 05:14:13 PM PDT 24
Peak memory 206212 kb
Host smart-db5a4a49-ab09-49e5-a6f4-f38500dc322a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44521
2559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.445212559
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.1855524592
Short name T2502
Test name
Test status
Simulation time 641850185 ps
CPU time 1.59 seconds
Started Jun 26 05:14:09 PM PDT 24
Finished Jun 26 05:14:13 PM PDT 24
Peak memory 206456 kb
Host smart-783d3dba-0d37-4d33-9109-43184cd2a246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18555
24592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.1855524592
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.3665851394
Short name T182
Test name
Test status
Simulation time 6371232554 ps
CPU time 12.05 seconds
Started Jun 26 05:14:11 PM PDT 24
Finished Jun 26 05:14:25 PM PDT 24
Peak memory 206580 kb
Host smart-b5ace906-f31e-4eb4-9685-18ce02e05261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36658
51394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.3665851394
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.3790420537
Short name T1531
Test name
Test status
Simulation time 365226349 ps
CPU time 1.31 seconds
Started Jun 26 05:14:10 PM PDT 24
Finished Jun 26 05:14:13 PM PDT 24
Peak memory 206440 kb
Host smart-fd76156a-2284-4e68-a06c-2250a55ce841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37904
20537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.3790420537
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.3997792234
Short name T660
Test name
Test status
Simulation time 156645068 ps
CPU time 0.78 seconds
Started Jun 26 05:14:15 PM PDT 24
Finished Jun 26 05:14:18 PM PDT 24
Peak memory 206388 kb
Host smart-1926306c-3be4-41d7-b0d0-817a39faf061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39977
92234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.3997792234
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.850405260
Short name T1844
Test name
Test status
Simulation time 113561493 ps
CPU time 0.74 seconds
Started Jun 26 05:14:15 PM PDT 24
Finished Jun 26 05:14:18 PM PDT 24
Peak memory 206212 kb
Host smart-9193c8b6-2c27-44a7-8515-4dfcd0d3b55e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85040
5260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.850405260
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.327044124
Short name T17
Test name
Test status
Simulation time 844466885 ps
CPU time 1.98 seconds
Started Jun 26 05:14:14 PM PDT 24
Finished Jun 26 05:14:17 PM PDT 24
Peak memory 206288 kb
Host smart-bcc52bed-fa08-462d-91ee-b516aa7d42cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32704
4124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.327044124
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.1415868088
Short name T1523
Test name
Test status
Simulation time 194175765 ps
CPU time 1.69 seconds
Started Jun 26 05:14:15 PM PDT 24
Finished Jun 26 05:14:17 PM PDT 24
Peak memory 206444 kb
Host smart-8c5832b9-0922-450e-8137-8d4c84613c7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14158
68088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.1415868088
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.3172023608
Short name T782
Test name
Test status
Simulation time 171739617 ps
CPU time 0.81 seconds
Started Jun 26 05:14:26 PM PDT 24
Finished Jun 26 05:14:28 PM PDT 24
Peak memory 206188 kb
Host smart-6f5ffca4-5b78-43aa-9931-2b71bb71af20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31720
23608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.3172023608
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.1632299764
Short name T1715
Test name
Test status
Simulation time 184302976 ps
CPU time 0.77 seconds
Started Jun 26 05:14:21 PM PDT 24
Finished Jun 26 05:14:23 PM PDT 24
Peak memory 206232 kb
Host smart-49e138a9-3473-438a-a813-a457c29d7440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16322
99764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.1632299764
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.669461663
Short name T2
Test name
Test status
Simulation time 234888427 ps
CPU time 0.86 seconds
Started Jun 26 05:14:15 PM PDT 24
Finished Jun 26 05:14:18 PM PDT 24
Peak memory 206140 kb
Host smart-3d344545-232a-4c8d-8908-3c32288f6686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66946
1663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.669461663
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_invalid_sync.1741130066
Short name T1260
Test name
Test status
Simulation time 7905073505 ps
CPU time 78.1 seconds
Started Jun 26 05:14:15 PM PDT 24
Finished Jun 26 05:15:35 PM PDT 24
Peak memory 206576 kb
Host smart-cad97b5b-35ca-455d-8a76-02da73dbc686
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1741130066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.1741130066
Directory /workspace/10.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.1171942413
Short name T1679
Test name
Test status
Simulation time 181029211 ps
CPU time 0.79 seconds
Started Jun 26 05:14:17 PM PDT 24
Finished Jun 26 05:14:19 PM PDT 24
Peak memory 206204 kb
Host smart-9b3a562a-ff63-4b4e-ae82-ccddec7d07a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11719
42413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.1171942413
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.1541389576
Short name T765
Test name
Test status
Simulation time 23347677473 ps
CPU time 23.56 seconds
Started Jun 26 05:14:17 PM PDT 24
Finished Jun 26 05:14:42 PM PDT 24
Peak memory 206228 kb
Host smart-b745c3cf-fe22-4efc-b794-47e74060e318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15413
89576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.1541389576
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.3597220877
Short name T361
Test name
Test status
Simulation time 3340310922 ps
CPU time 4.03 seconds
Started Jun 26 05:14:14 PM PDT 24
Finished Jun 26 05:14:19 PM PDT 24
Peak memory 206224 kb
Host smart-9e8e5f69-da28-47ce-93c0-c9a537e5ac32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35972
20877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.3597220877
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.3896847672
Short name T1726
Test name
Test status
Simulation time 8060958035 ps
CPU time 79.54 seconds
Started Jun 26 05:14:15 PM PDT 24
Finished Jun 26 05:15:37 PM PDT 24
Peak memory 206516 kb
Host smart-102ad872-f0c3-4cdd-afcf-33d09489f0ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38968
47672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.3896847672
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.521597226
Short name T1614
Test name
Test status
Simulation time 5147522219 ps
CPU time 143.74 seconds
Started Jun 26 05:14:17 PM PDT 24
Finished Jun 26 05:16:43 PM PDT 24
Peak memory 206532 kb
Host smart-71ae27ab-a05d-4489-a8cc-a2ccd5791737
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=521597226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.521597226
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.3302407790
Short name T1824
Test name
Test status
Simulation time 246726490 ps
CPU time 0.93 seconds
Started Jun 26 05:14:28 PM PDT 24
Finished Jun 26 05:14:30 PM PDT 24
Peak memory 206144 kb
Host smart-1709061a-9cef-4334-b6c3-e5b7d1664564
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3302407790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.3302407790
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.2078121289
Short name T557
Test name
Test status
Simulation time 192425625 ps
CPU time 0.95 seconds
Started Jun 26 05:14:14 PM PDT 24
Finished Jun 26 05:14:16 PM PDT 24
Peak memory 206116 kb
Host smart-40b495e4-8b59-4beb-99e4-35b2974672a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20781
21289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.2078121289
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.870742171
Short name T1084
Test name
Test status
Simulation time 3451807489 ps
CPU time 24.14 seconds
Started Jun 26 05:14:15 PM PDT 24
Finished Jun 26 05:14:40 PM PDT 24
Peak memory 206484 kb
Host smart-1ddeaacc-9874-4d8b-b1e1-15dd3b72b3df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87074
2171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.870742171
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.4288332921
Short name T1571
Test name
Test status
Simulation time 5517252370 ps
CPU time 50.16 seconds
Started Jun 26 05:14:15 PM PDT 24
Finished Jun 26 05:15:07 PM PDT 24
Peak memory 206544 kb
Host smart-170a6104-25f3-4418-a6bd-c655be1107c8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4288332921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.4288332921
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.1493938888
Short name T1962
Test name
Test status
Simulation time 150034591 ps
CPU time 0.79 seconds
Started Jun 26 05:14:22 PM PDT 24
Finished Jun 26 05:14:25 PM PDT 24
Peak memory 206144 kb
Host smart-e698e79e-1d1c-4e4e-9f3e-f471cbeee66e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1493938888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.1493938888
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.1398219203
Short name T2068
Test name
Test status
Simulation time 164204398 ps
CPU time 0.81 seconds
Started Jun 26 05:14:16 PM PDT 24
Finished Jun 26 05:14:19 PM PDT 24
Peak memory 206128 kb
Host smart-6ea06d35-6207-4b3d-bf91-e904b46657b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13982
19203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.1398219203
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.1148045391
Short name T127
Test name
Test status
Simulation time 198844682 ps
CPU time 0.85 seconds
Started Jun 26 05:14:26 PM PDT 24
Finished Jun 26 05:14:28 PM PDT 24
Peak memory 206188 kb
Host smart-d70068eb-6d21-41dd-9cad-908196919155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11480
45391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.1148045391
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.432086705
Short name T1505
Test name
Test status
Simulation time 175484692 ps
CPU time 0.85 seconds
Started Jun 26 05:14:21 PM PDT 24
Finished Jun 26 05:14:23 PM PDT 24
Peak memory 206204 kb
Host smart-9e5114ff-81da-492a-bffc-ec1dac56fba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43208
6705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.432086705
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.1998149107
Short name T2097
Test name
Test status
Simulation time 189136767 ps
CPU time 0.81 seconds
Started Jun 26 05:14:22 PM PDT 24
Finished Jun 26 05:14:25 PM PDT 24
Peak memory 206132 kb
Host smart-b0252058-c217-446f-b820-7b91e8f3a446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19981
49107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.1998149107
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.2564190798
Short name T1027
Test name
Test status
Simulation time 155079885 ps
CPU time 0.8 seconds
Started Jun 26 05:14:20 PM PDT 24
Finished Jun 26 05:14:22 PM PDT 24
Peak memory 206116 kb
Host smart-b903870a-a851-4485-845d-feee18f34beb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25641
90798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.2564190798
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.3971442223
Short name T2090
Test name
Test status
Simulation time 159062514 ps
CPU time 0.76 seconds
Started Jun 26 05:14:26 PM PDT 24
Finished Jun 26 05:14:28 PM PDT 24
Peak memory 206128 kb
Host smart-fb7a1045-09f3-41ff-9d47-6c054a19f28f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39714
42223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.3971442223
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.874879439
Short name T780
Test name
Test status
Simulation time 238663267 ps
CPU time 0.94 seconds
Started Jun 26 05:14:21 PM PDT 24
Finished Jun 26 05:14:23 PM PDT 24
Peak memory 206252 kb
Host smart-0a0c302e-6259-4b55-a824-9348c083c230
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=874879439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.874879439
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.3330919923
Short name T586
Test name
Test status
Simulation time 142938924 ps
CPU time 0.73 seconds
Started Jun 26 05:14:21 PM PDT 24
Finished Jun 26 05:14:24 PM PDT 24
Peak memory 206224 kb
Host smart-0c2bf9ea-94b1-4b5c-8db8-786ca4efe7af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33309
19923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.3330919923
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.3907598978
Short name T1399
Test name
Test status
Simulation time 189040687 ps
CPU time 0.85 seconds
Started Jun 26 05:14:20 PM PDT 24
Finished Jun 26 05:14:22 PM PDT 24
Peak memory 206144 kb
Host smart-4451d0ff-d8e7-4ef9-8e60-a4afd4e36d40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39075
98978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.3907598978
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.2395285135
Short name T2386
Test name
Test status
Simulation time 236566813 ps
CPU time 0.9 seconds
Started Jun 26 05:14:21 PM PDT 24
Finished Jun 26 05:14:24 PM PDT 24
Peak memory 206184 kb
Host smart-0abdfd2f-bc87-4915-9c51-4c387ebf73b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23952
85135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.2395285135
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.3903385934
Short name T694
Test name
Test status
Simulation time 201876825 ps
CPU time 0.89 seconds
Started Jun 26 05:14:25 PM PDT 24
Finished Jun 26 05:14:27 PM PDT 24
Peak memory 206192 kb
Host smart-f97e0430-d3a3-42ba-ad9d-bb4ac44c09b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39033
85934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.3903385934
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.2912047491
Short name T2158
Test name
Test status
Simulation time 157063301 ps
CPU time 0.82 seconds
Started Jun 26 05:14:21 PM PDT 24
Finished Jun 26 05:14:23 PM PDT 24
Peak memory 206212 kb
Host smart-3468b1fa-46ba-4050-ab3a-a90b2a298261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29120
47491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.2912047491
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.2930495133
Short name T489
Test name
Test status
Simulation time 167088012 ps
CPU time 0.82 seconds
Started Jun 26 05:14:23 PM PDT 24
Finished Jun 26 05:14:25 PM PDT 24
Peak memory 206396 kb
Host smart-317c0388-3b2b-4ca7-ada9-6ab759d7399b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29304
95133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.2930495133
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.643499580
Short name T2073
Test name
Test status
Simulation time 160856347 ps
CPU time 0.81 seconds
Started Jun 26 05:14:21 PM PDT 24
Finished Jun 26 05:14:23 PM PDT 24
Peak memory 206244 kb
Host smart-a23f0a07-d776-4e6e-9b0c-7e75f5bfea5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64349
9580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.643499580
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.980129799
Short name T1836
Test name
Test status
Simulation time 213591855 ps
CPU time 0.89 seconds
Started Jun 26 05:14:21 PM PDT 24
Finished Jun 26 05:14:23 PM PDT 24
Peak memory 206132 kb
Host smart-57198cb8-5ef4-47a5-bf3c-bf2ac79bf20c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98012
9799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.980129799
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.1523831619
Short name T2298
Test name
Test status
Simulation time 3839780998 ps
CPU time 105.64 seconds
Started Jun 26 05:14:21 PM PDT 24
Finished Jun 26 05:16:08 PM PDT 24
Peak memory 206372 kb
Host smart-ac537bbb-fd2f-474e-aa33-361e2f7a7388
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1523831619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.1523831619
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.2594313269
Short name T1735
Test name
Test status
Simulation time 166444921 ps
CPU time 0.81 seconds
Started Jun 26 05:14:22 PM PDT 24
Finished Jun 26 05:14:25 PM PDT 24
Peak memory 206404 kb
Host smart-5b8ae941-c96d-4801-b88c-8084f70bbf56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25943
13269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.2594313269
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.1140084343
Short name T1438
Test name
Test status
Simulation time 158020935 ps
CPU time 0.77 seconds
Started Jun 26 05:14:28 PM PDT 24
Finished Jun 26 05:14:30 PM PDT 24
Peak memory 206012 kb
Host smart-1c5c3079-09f2-4f5a-83cd-8aac16aa1a8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11400
84343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.1140084343
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.1340116448
Short name T1843
Test name
Test status
Simulation time 6894971918 ps
CPU time 61.58 seconds
Started Jun 26 05:14:21 PM PDT 24
Finished Jun 26 05:15:25 PM PDT 24
Peak memory 206540 kb
Host smart-3644c873-6f18-40e8-b962-8f83ebedb221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13401
16448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.1340116448
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.47433937
Short name T1326
Test name
Test status
Simulation time 3944508433 ps
CPU time 4.73 seconds
Started Jun 26 05:14:22 PM PDT 24
Finished Jun 26 05:14:29 PM PDT 24
Peak memory 206204 kb
Host smart-2d7809f5-78d8-45f1-bb50-040de16d55ad
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=47433937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.47433937
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.110649438
Short name T2453
Test name
Test status
Simulation time 13395928335 ps
CPU time 12.89 seconds
Started Jun 26 05:14:22 PM PDT 24
Finished Jun 26 05:14:36 PM PDT 24
Peak memory 206480 kb
Host smart-6eeab81c-3d9b-461e-a0a5-4acd915a36f1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=110649438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.110649438
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.4081982845
Short name T437
Test name
Test status
Simulation time 23294602231 ps
CPU time 21.22 seconds
Started Jun 26 05:14:28 PM PDT 24
Finished Jun 26 05:14:50 PM PDT 24
Peak memory 206316 kb
Host smart-b689b138-d9fc-4349-8ea7-6eb3be7d5d53
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4081982845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.4081982845
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.1953563901
Short name T2327
Test name
Test status
Simulation time 171844924 ps
CPU time 0.81 seconds
Started Jun 26 05:14:28 PM PDT 24
Finished Jun 26 05:14:30 PM PDT 24
Peak memory 206124 kb
Host smart-b8577455-d5e1-494f-bf24-1adc314cac25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19535
63901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.1953563901
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.2120819949
Short name T2278
Test name
Test status
Simulation time 161203726 ps
CPU time 0.8 seconds
Started Jun 26 05:14:23 PM PDT 24
Finished Jun 26 05:14:26 PM PDT 24
Peak memory 206176 kb
Host smart-ac34ee86-a343-44b2-b922-2de175fec691
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21208
19949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.2120819949
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.494887303
Short name T2004
Test name
Test status
Simulation time 470183237 ps
CPU time 1.31 seconds
Started Jun 26 05:14:27 PM PDT 24
Finished Jun 26 05:14:30 PM PDT 24
Peak memory 206200 kb
Host smart-8e4c192b-a21d-4c30-9a18-6089a42c7a33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49488
7303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.494887303
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_device_address.2630132131
Short name T647
Test name
Test status
Simulation time 15199199798 ps
CPU time 30.85 seconds
Started Jun 26 05:14:27 PM PDT 24
Finished Jun 26 05:14:59 PM PDT 24
Peak memory 206524 kb
Host smart-3d4fe535-dcdb-4062-bf59-229f486474c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26301
32131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.2630132131
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.98933954
Short name T2089
Test name
Test status
Simulation time 467507172 ps
CPU time 1.34 seconds
Started Jun 26 05:14:28 PM PDT 24
Finished Jun 26 05:14:31 PM PDT 24
Peak memory 206244 kb
Host smart-d6640b92-8924-4d5e-9242-637084e4b09e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98933
954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.98933954
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.1964905366
Short name T2378
Test name
Test status
Simulation time 227830613 ps
CPU time 0.83 seconds
Started Jun 26 05:14:33 PM PDT 24
Finished Jun 26 05:14:34 PM PDT 24
Peak memory 206116 kb
Host smart-0b2c54e0-244e-4fe4-8d6d-05499cdfd82d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19649
05366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.1964905366
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.2921945270
Short name T1833
Test name
Test status
Simulation time 28174404 ps
CPU time 0.64 seconds
Started Jun 26 05:14:35 PM PDT 24
Finished Jun 26 05:14:36 PM PDT 24
Peak memory 206240 kb
Host smart-363ebdf0-4336-463d-903b-e43654cd5626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29219
45270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.2921945270
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.2372207376
Short name T2166
Test name
Test status
Simulation time 954216920 ps
CPU time 2.14 seconds
Started Jun 26 05:14:26 PM PDT 24
Finished Jun 26 05:14:29 PM PDT 24
Peak memory 206400 kb
Host smart-2e4b96dd-a13f-4882-8dd1-e121edd3c488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23722
07376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.2372207376
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.3239518480
Short name T2017
Test name
Test status
Simulation time 213354622 ps
CPU time 0.84 seconds
Started Jun 26 05:14:42 PM PDT 24
Finished Jun 26 05:14:44 PM PDT 24
Peak memory 206244 kb
Host smart-9d42875e-772f-4d1e-a195-439082aba6d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32395
18480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.3239518480
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.65955127
Short name T1483
Test name
Test status
Simulation time 143952956 ps
CPU time 0.76 seconds
Started Jun 26 05:14:41 PM PDT 24
Finished Jun 26 05:14:43 PM PDT 24
Peak memory 206140 kb
Host smart-f31825f0-1320-492c-9006-4349eaa7acd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65955
127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.65955127
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.793796878
Short name T1515
Test name
Test status
Simulation time 213732113 ps
CPU time 0.91 seconds
Started Jun 26 05:14:35 PM PDT 24
Finished Jun 26 05:14:36 PM PDT 24
Peak memory 206240 kb
Host smart-1c882099-36f2-4c7b-9c80-da46be0dcb27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79379
6878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.793796878
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_invalid_sync.4117117940
Short name T99
Test name
Test status
Simulation time 6208316734 ps
CPU time 172.12 seconds
Started Jun 26 05:14:33 PM PDT 24
Finished Jun 26 05:17:26 PM PDT 24
Peak memory 206428 kb
Host smart-557ce131-ad81-40ae-b0a6-3ca6dd619ec1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4117117940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_invalid_sync.4117117940
Directory /workspace/11.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.4254313080
Short name T2531
Test name
Test status
Simulation time 214114039 ps
CPU time 0.91 seconds
Started Jun 26 05:14:34 PM PDT 24
Finished Jun 26 05:14:35 PM PDT 24
Peak memory 206096 kb
Host smart-efb4bf36-f1ea-456b-aa62-e64d84dc27ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42543
13080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.4254313080
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.954906523
Short name T1409
Test name
Test status
Simulation time 23307942938 ps
CPU time 22.46 seconds
Started Jun 26 05:14:43 PM PDT 24
Finished Jun 26 05:15:07 PM PDT 24
Peak memory 206336 kb
Host smart-2181f229-8356-46f3-b91a-b7d6e81bd800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95490
6523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.954906523
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.665173166
Short name T2321
Test name
Test status
Simulation time 3363867071 ps
CPU time 4.08 seconds
Started Jun 26 05:14:41 PM PDT 24
Finished Jun 26 05:14:47 PM PDT 24
Peak memory 206160 kb
Host smart-6f469ff7-22b1-4cae-a7bd-828ca75b4651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66517
3166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.665173166
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.2805899651
Short name T2062
Test name
Test status
Simulation time 7972811541 ps
CPU time 54.56 seconds
Started Jun 26 05:14:40 PM PDT 24
Finished Jun 26 05:15:36 PM PDT 24
Peak memory 206472 kb
Host smart-e264b56a-25fd-4dfa-b763-4c32dec497de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28058
99651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.2805899651
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.132283755
Short name T365
Test name
Test status
Simulation time 7290122133 ps
CPU time 50.41 seconds
Started Jun 26 05:14:41 PM PDT 24
Finished Jun 26 05:15:32 PM PDT 24
Peak memory 206612 kb
Host smart-29ee49b5-54af-4813-ba6d-166f408aba33
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=132283755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.132283755
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.2463732626
Short name T1033
Test name
Test status
Simulation time 242758184 ps
CPU time 0.88 seconds
Started Jun 26 05:14:47 PM PDT 24
Finished Jun 26 05:14:49 PM PDT 24
Peak memory 206196 kb
Host smart-329d554a-44b4-47f7-93ea-0506732fc83f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2463732626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.2463732626
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.2785925423
Short name T1916
Test name
Test status
Simulation time 188102703 ps
CPU time 0.85 seconds
Started Jun 26 05:14:41 PM PDT 24
Finished Jun 26 05:14:44 PM PDT 24
Peak memory 206084 kb
Host smart-7fcd2fd9-ba89-49b8-a9ce-f2e2a36efdaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27859
25423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.2785925423
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.2331380103
Short name T2167
Test name
Test status
Simulation time 3878281712 ps
CPU time 35.01 seconds
Started Jun 26 05:14:43 PM PDT 24
Finished Jun 26 05:15:19 PM PDT 24
Peak memory 206544 kb
Host smart-7c560a35-5655-469b-a7cd-3539b838bcca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23313
80103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.2331380103
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.705545935
Short name T1765
Test name
Test status
Simulation time 5205584649 ps
CPU time 146.28 seconds
Started Jun 26 05:14:41 PM PDT 24
Finished Jun 26 05:17:08 PM PDT 24
Peak memory 206532 kb
Host smart-492c79b3-425f-4bdd-b039-9dbaf5a5e905
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=705545935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.705545935
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.2193711596
Short name T1932
Test name
Test status
Simulation time 145141622 ps
CPU time 0.79 seconds
Started Jun 26 05:14:42 PM PDT 24
Finished Jun 26 05:14:45 PM PDT 24
Peak memory 206416 kb
Host smart-74b8aaac-b0b2-4284-a702-98bd34a171dd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2193711596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.2193711596
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.2734782527
Short name T1634
Test name
Test status
Simulation time 142528502 ps
CPU time 0.78 seconds
Started Jun 26 05:14:41 PM PDT 24
Finished Jun 26 05:14:43 PM PDT 24
Peak memory 206128 kb
Host smart-238b8ba0-5fc3-4db6-96f0-6964a6ed3c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27347
82527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.2734782527
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.620841888
Short name T257
Test name
Test status
Simulation time 191678436 ps
CPU time 0.89 seconds
Started Jun 26 05:14:52 PM PDT 24
Finished Jun 26 05:14:55 PM PDT 24
Peak memory 206140 kb
Host smart-29d4f7ca-d0a4-4b1b-8013-2dbb73a3e41b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62084
1888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.620841888
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.2058926231
Short name T1516
Test name
Test status
Simulation time 188574864 ps
CPU time 0.82 seconds
Started Jun 26 05:14:41 PM PDT 24
Finished Jun 26 05:14:43 PM PDT 24
Peak memory 206116 kb
Host smart-f21ac628-675d-421b-ae30-836e10e16dcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20589
26231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.2058926231
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.3931236360
Short name T2047
Test name
Test status
Simulation time 200749666 ps
CPU time 0.87 seconds
Started Jun 26 05:14:41 PM PDT 24
Finished Jun 26 05:14:43 PM PDT 24
Peak memory 206196 kb
Host smart-3decf9a3-b357-4f75-8376-dfbaa1e1a7d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39312
36360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.3931236360
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.214036944
Short name T1135
Test name
Test status
Simulation time 155639672 ps
CPU time 0.75 seconds
Started Jun 26 05:14:40 PM PDT 24
Finished Jun 26 05:14:42 PM PDT 24
Peak memory 206152 kb
Host smart-c57cd103-af00-4a5b-b3cb-65cd230897d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21403
6944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.214036944
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.737186323
Short name T744
Test name
Test status
Simulation time 246381696 ps
CPU time 0.96 seconds
Started Jun 26 05:14:42 PM PDT 24
Finished Jun 26 05:14:44 PM PDT 24
Peak memory 206232 kb
Host smart-0b0f9ea9-5fa0-42ad-8770-8be9ac809540
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=737186323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.737186323
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.3845246876
Short name T2519
Test name
Test status
Simulation time 162945620 ps
CPU time 0.8 seconds
Started Jun 26 05:14:52 PM PDT 24
Finished Jun 26 05:14:55 PM PDT 24
Peak memory 206120 kb
Host smart-b084008d-d83f-4d9a-835a-c33921fe8316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38452
46876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.3845246876
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.696926990
Short name T1992
Test name
Test status
Simulation time 79510619 ps
CPU time 0.68 seconds
Started Jun 26 05:14:42 PM PDT 24
Finished Jun 26 05:14:45 PM PDT 24
Peak memory 206224 kb
Host smart-24dada9f-c378-4320-a91d-dbaf2c70bbe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69692
6990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.696926990
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.2473484286
Short name T1658
Test name
Test status
Simulation time 17406618156 ps
CPU time 35.53 seconds
Started Jun 26 05:14:42 PM PDT 24
Finished Jun 26 05:15:19 PM PDT 24
Peak memory 206536 kb
Host smart-590ceebe-a100-43c7-b08d-1798c2dc3cb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24734
84286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.2473484286
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.1701289393
Short name T1355
Test name
Test status
Simulation time 277938473 ps
CPU time 0.98 seconds
Started Jun 26 05:14:41 PM PDT 24
Finished Jun 26 05:14:43 PM PDT 24
Peak memory 206224 kb
Host smart-997e7660-e80c-40fc-8e49-0e774099ca44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17012
89393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.1701289393
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.261560295
Short name T356
Test name
Test status
Simulation time 178108118 ps
CPU time 0.84 seconds
Started Jun 26 05:14:52 PM PDT 24
Finished Jun 26 05:14:54 PM PDT 24
Peak memory 206140 kb
Host smart-51017816-f742-41f4-be9d-d5598d77c35b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26156
0295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.261560295
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.1851506800
Short name T1154
Test name
Test status
Simulation time 189961254 ps
CPU time 0.89 seconds
Started Jun 26 05:14:43 PM PDT 24
Finished Jun 26 05:14:46 PM PDT 24
Peak memory 206212 kb
Host smart-0902f189-fe05-41bc-93df-c4379d52612a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18515
06800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.1851506800
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.1405256108
Short name T1802
Test name
Test status
Simulation time 153391667 ps
CPU time 0.79 seconds
Started Jun 26 05:14:39 PM PDT 24
Finished Jun 26 05:14:41 PM PDT 24
Peak memory 206208 kb
Host smart-314ac8a1-2d71-464a-9d67-e487756f9824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14052
56108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.1405256108
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.2352812814
Short name T1793
Test name
Test status
Simulation time 154738301 ps
CPU time 0.8 seconds
Started Jun 26 05:14:39 PM PDT 24
Finished Jun 26 05:14:41 PM PDT 24
Peak memory 206196 kb
Host smart-03d959c3-e90a-4ca0-864d-4c416932ed8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23528
12814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.2352812814
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.3605754665
Short name T2026
Test name
Test status
Simulation time 179903774 ps
CPU time 0.8 seconds
Started Jun 26 05:14:52 PM PDT 24
Finished Jun 26 05:14:53 PM PDT 24
Peak memory 206140 kb
Host smart-472e2e61-328c-4c09-a974-e45ed6ffaafa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36057
54665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.3605754665
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.1069077452
Short name T1895
Test name
Test status
Simulation time 209723609 ps
CPU time 0.91 seconds
Started Jun 26 05:14:43 PM PDT 24
Finished Jun 26 05:14:45 PM PDT 24
Peak memory 206192 kb
Host smart-f1b84648-f75d-441f-9ea3-b91699f5a334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10690
77452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.1069077452
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.2805670645
Short name T925
Test name
Test status
Simulation time 4375748834 ps
CPU time 31.83 seconds
Started Jun 26 05:14:40 PM PDT 24
Finished Jun 26 05:15:14 PM PDT 24
Peak memory 206724 kb
Host smart-0326d0c9-0a65-439d-9771-a190e5416086
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2805670645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.2805670645
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.1891195577
Short name T1488
Test name
Test status
Simulation time 177359461 ps
CPU time 0.81 seconds
Started Jun 26 05:14:40 PM PDT 24
Finished Jun 26 05:14:41 PM PDT 24
Peak memory 206120 kb
Host smart-2d7962c7-ba35-40ec-87ef-b1be24a68570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18911
95577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.1891195577
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.3711779154
Short name T1979
Test name
Test status
Simulation time 159079453 ps
CPU time 0.79 seconds
Started Jun 26 05:14:52 PM PDT 24
Finished Jun 26 05:14:53 PM PDT 24
Peak memory 206120 kb
Host smart-23878f6c-46ce-4529-bf69-1a56e27a0afa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37117
79154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.3711779154
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.2056813856
Short name T407
Test name
Test status
Simulation time 6953596353 ps
CPU time 49.49 seconds
Started Jun 26 05:14:40 PM PDT 24
Finished Jun 26 05:15:30 PM PDT 24
Peak memory 206492 kb
Host smart-54773b0c-9ab6-4588-b6eb-a813248b94a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20568
13856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.2056813856
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.556430962
Short name T1866
Test name
Test status
Simulation time 4099260461 ps
CPU time 5 seconds
Started Jun 26 05:14:47 PM PDT 24
Finished Jun 26 05:14:52 PM PDT 24
Peak memory 206468 kb
Host smart-6fb7220b-ba40-45ce-a197-f1036e1f2f92
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=556430962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.556430962
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.4113938808
Short name T965
Test name
Test status
Simulation time 13371431209 ps
CPU time 12.45 seconds
Started Jun 26 05:14:45 PM PDT 24
Finished Jun 26 05:14:58 PM PDT 24
Peak memory 206316 kb
Host smart-32608e92-3086-47c1-b69c-eac3f58581f2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4113938808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.4113938808
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.3487605822
Short name T10
Test name
Test status
Simulation time 23392037863 ps
CPU time 26.56 seconds
Started Jun 26 05:14:49 PM PDT 24
Finished Jun 26 05:15:16 PM PDT 24
Peak memory 206268 kb
Host smart-0258c006-f8a1-4d4c-9d0e-69fd5c090a7a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3487605822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.3487605822
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.2043070130
Short name T1356
Test name
Test status
Simulation time 192051039 ps
CPU time 0.84 seconds
Started Jun 26 05:14:48 PM PDT 24
Finished Jun 26 05:14:50 PM PDT 24
Peak memory 206108 kb
Host smart-a910c7ed-a844-40da-81ad-d520efd37983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20430
70130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.2043070130
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.772617122
Short name T1184
Test name
Test status
Simulation time 160449655 ps
CPU time 0.83 seconds
Started Jun 26 05:14:47 PM PDT 24
Finished Jun 26 05:14:49 PM PDT 24
Peak memory 206216 kb
Host smart-ce320956-b51d-444a-aeeb-112ebf34ce80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77261
7122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.772617122
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.2585760588
Short name T609
Test name
Test status
Simulation time 256402466 ps
CPU time 1.01 seconds
Started Jun 26 05:14:53 PM PDT 24
Finished Jun 26 05:14:55 PM PDT 24
Peak memory 206124 kb
Host smart-e41129be-89ee-4e2f-9a28-dbfae939ce51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25857
60588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.2585760588
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.2128794475
Short name T1345
Test name
Test status
Simulation time 1252597407 ps
CPU time 2.61 seconds
Started Jun 26 05:14:46 PM PDT 24
Finished Jun 26 05:14:49 PM PDT 24
Peak memory 206404 kb
Host smart-587f41bf-070d-43ff-bdfc-e56eb2dedb3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21287
94475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.2128794475
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.18394690
Short name T1877
Test name
Test status
Simulation time 13908833983 ps
CPU time 29.75 seconds
Started Jun 26 05:14:48 PM PDT 24
Finished Jun 26 05:15:19 PM PDT 24
Peak memory 206480 kb
Host smart-38230dfb-477a-4228-acd1-7a2c53ec796b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18394
690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.18394690
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.801601567
Short name T1720
Test name
Test status
Simulation time 523499484 ps
CPU time 1.4 seconds
Started Jun 26 05:14:47 PM PDT 24
Finished Jun 26 05:14:49 PM PDT 24
Peak memory 206148 kb
Host smart-0683e877-8cdf-477d-a81c-24ce3ab98725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80160
1567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.801601567
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.2369535074
Short name T992
Test name
Test status
Simulation time 139732946 ps
CPU time 0.74 seconds
Started Jun 26 05:14:49 PM PDT 24
Finished Jun 26 05:14:51 PM PDT 24
Peak memory 206108 kb
Host smart-0764bf53-f0c6-4651-a777-998963e6b42d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23695
35074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.2369535074
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.374592739
Short name T1045
Test name
Test status
Simulation time 59459659 ps
CPU time 0.66 seconds
Started Jun 26 05:14:48 PM PDT 24
Finished Jun 26 05:14:50 PM PDT 24
Peak memory 206188 kb
Host smart-6a37ab90-76b6-4a30-bee9-b6505368ae08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37459
2739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.374592739
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.1402559149
Short name T1161
Test name
Test status
Simulation time 698596330 ps
CPU time 1.97 seconds
Started Jun 26 05:14:53 PM PDT 24
Finished Jun 26 05:14:56 PM PDT 24
Peak memory 206396 kb
Host smart-39ddf8cb-7827-40e8-b356-b9b62c94c87f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14025
59149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.1402559149
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.2023647556
Short name T1864
Test name
Test status
Simulation time 172814804 ps
CPU time 1.28 seconds
Started Jun 26 05:14:48 PM PDT 24
Finished Jun 26 05:14:50 PM PDT 24
Peak memory 206392 kb
Host smart-d7825718-0749-49df-bbb4-c5072777ed8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20236
47556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.2023647556
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.1036232933
Short name T2258
Test name
Test status
Simulation time 191640443 ps
CPU time 0.82 seconds
Started Jun 26 05:14:53 PM PDT 24
Finished Jun 26 05:14:55 PM PDT 24
Peak memory 206140 kb
Host smart-b200a57c-e08b-424c-87b0-284de1be1151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10362
32933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.1036232933
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.1601992212
Short name T2557
Test name
Test status
Simulation time 143770870 ps
CPU time 0.8 seconds
Started Jun 26 05:14:54 PM PDT 24
Finished Jun 26 05:14:56 PM PDT 24
Peak memory 206180 kb
Host smart-f20acc3c-c923-49b6-9ce1-f3cf595a7bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16019
92212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.1601992212
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.4004488728
Short name T1332
Test name
Test status
Simulation time 200450616 ps
CPU time 0.82 seconds
Started Jun 26 05:14:47 PM PDT 24
Finished Jun 26 05:14:49 PM PDT 24
Peak memory 206244 kb
Host smart-b2509121-a90e-43e6-a8f8-e76e9958bc07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40044
88728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.4004488728
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.236674007
Short name T1590
Test name
Test status
Simulation time 166996052 ps
CPU time 0.8 seconds
Started Jun 26 05:14:48 PM PDT 24
Finished Jun 26 05:14:51 PM PDT 24
Peak memory 206176 kb
Host smart-e89ab346-1365-4ba3-a709-d060f860d024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23667
4007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.236674007
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.1446357160
Short name T452
Test name
Test status
Simulation time 23308566251 ps
CPU time 22.75 seconds
Started Jun 26 05:14:49 PM PDT 24
Finished Jun 26 05:15:13 PM PDT 24
Peak memory 206228 kb
Host smart-39d7d821-6f3d-4363-beca-9763935e4be4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14463
57160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.1446357160
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.2612630043
Short name T1292
Test name
Test status
Simulation time 3354884821 ps
CPU time 4.81 seconds
Started Jun 26 05:14:47 PM PDT 24
Finished Jun 26 05:14:53 PM PDT 24
Peak memory 206252 kb
Host smart-023c6f46-54e1-496d-bd35-c38be34cae94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26126
30043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.2612630043
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.1475869169
Short name T1312
Test name
Test status
Simulation time 7383623949 ps
CPU time 50.96 seconds
Started Jun 26 05:14:47 PM PDT 24
Finished Jun 26 05:15:39 PM PDT 24
Peak memory 206520 kb
Host smart-a2052702-dc3e-475e-a48b-4d7900ca6a14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14758
69169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.1475869169
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.3271955721
Short name T1144
Test name
Test status
Simulation time 5188311314 ps
CPU time 36.72 seconds
Started Jun 26 05:14:54 PM PDT 24
Finished Jun 26 05:15:32 PM PDT 24
Peak memory 206532 kb
Host smart-6fda24b0-e1e4-48ff-9a12-f68dc3f63d7d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3271955721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.3271955721
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.4261877091
Short name T2445
Test name
Test status
Simulation time 243111193 ps
CPU time 0.91 seconds
Started Jun 26 05:15:00 PM PDT 24
Finished Jun 26 05:15:03 PM PDT 24
Peak memory 206144 kb
Host smart-053925d5-d882-4437-a4ee-64d4e917f95b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4261877091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.4261877091
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.4156750204
Short name T1267
Test name
Test status
Simulation time 198429434 ps
CPU time 0.86 seconds
Started Jun 26 05:14:48 PM PDT 24
Finished Jun 26 05:14:49 PM PDT 24
Peak memory 206180 kb
Host smart-2bd0ea11-9094-4787-9518-b3e05e42948d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41567
50204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.4156750204
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.2403757122
Short name T1317
Test name
Test status
Simulation time 3878096649 ps
CPU time 105.83 seconds
Started Jun 26 05:14:53 PM PDT 24
Finished Jun 26 05:16:41 PM PDT 24
Peak memory 206456 kb
Host smart-92418cc2-d12b-470e-ba6b-dc9cfe87cded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24037
57122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.2403757122
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.3699938487
Short name T259
Test name
Test status
Simulation time 6376202964 ps
CPU time 178.14 seconds
Started Jun 26 05:14:55 PM PDT 24
Finished Jun 26 05:17:55 PM PDT 24
Peak memory 206520 kb
Host smart-8f7b9232-a1d0-4646-807c-e4924cc468f5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3699938487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.3699938487
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.133196374
Short name T2276
Test name
Test status
Simulation time 174726176 ps
CPU time 0.86 seconds
Started Jun 26 05:14:59 PM PDT 24
Finished Jun 26 05:15:01 PM PDT 24
Peak memory 206228 kb
Host smart-da1e0f91-db9d-4dd1-861e-75649eaa63e2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=133196374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.133196374
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.1574029175
Short name T1121
Test name
Test status
Simulation time 142588526 ps
CPU time 0.76 seconds
Started Jun 26 05:14:55 PM PDT 24
Finished Jun 26 05:14:58 PM PDT 24
Peak memory 206208 kb
Host smart-eaecfc86-69a6-4a60-aaaf-ff95f548d568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15740
29175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.1574029175
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.675367313
Short name T119
Test name
Test status
Simulation time 185161005 ps
CPU time 0.85 seconds
Started Jun 26 05:14:53 PM PDT 24
Finished Jun 26 05:14:55 PM PDT 24
Peak memory 206144 kb
Host smart-76f2a750-2093-4dfb-b650-f67360636892
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67536
7313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.675367313
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.2376484564
Short name T1188
Test name
Test status
Simulation time 219173115 ps
CPU time 0.85 seconds
Started Jun 26 05:14:53 PM PDT 24
Finished Jun 26 05:14:55 PM PDT 24
Peak memory 206172 kb
Host smart-a2dc45fa-a7a3-4e8d-bc3d-2c2aade26ca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23764
84564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.2376484564
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.2117332190
Short name T872
Test name
Test status
Simulation time 155848131 ps
CPU time 0.78 seconds
Started Jun 26 05:14:55 PM PDT 24
Finished Jun 26 05:14:58 PM PDT 24
Peak memory 206208 kb
Host smart-04b11dd6-2590-41e7-8078-af22fc6b85b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21173
32190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.2117332190
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.2734788850
Short name T101
Test name
Test status
Simulation time 190601642 ps
CPU time 0.83 seconds
Started Jun 26 05:14:56 PM PDT 24
Finished Jun 26 05:14:58 PM PDT 24
Peak memory 206440 kb
Host smart-f09a225c-46f8-4c70-aba7-b2087b31f16e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27347
88850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.2734788850
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.1264454752
Short name T766
Test name
Test status
Simulation time 147750527 ps
CPU time 0.78 seconds
Started Jun 26 05:14:54 PM PDT 24
Finished Jun 26 05:14:56 PM PDT 24
Peak memory 206180 kb
Host smart-ee49bccb-5f0c-4578-ac0b-1ce9c181f696
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12644
54752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.1264454752
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.2967338151
Short name T1874
Test name
Test status
Simulation time 261717872 ps
CPU time 1.07 seconds
Started Jun 26 05:14:54 PM PDT 24
Finished Jun 26 05:14:57 PM PDT 24
Peak memory 206144 kb
Host smart-0cd53091-d712-40f1-98f7-d2c803c38a6a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2967338151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.2967338151
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.1526255759
Short name T1644
Test name
Test status
Simulation time 213103975 ps
CPU time 0.8 seconds
Started Jun 26 05:14:54 PM PDT 24
Finished Jun 26 05:14:57 PM PDT 24
Peak memory 206116 kb
Host smart-46bf1039-c4ef-4cd2-9ec1-362a0f54d71f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15262
55759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.1526255759
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.1188811190
Short name T1333
Test name
Test status
Simulation time 92673903 ps
CPU time 0.72 seconds
Started Jun 26 05:14:56 PM PDT 24
Finished Jun 26 05:14:58 PM PDT 24
Peak memory 206192 kb
Host smart-1d72565d-fd68-4bb9-9321-dd4b27fe4f73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11888
11190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.1188811190
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.3899262311
Short name T2092
Test name
Test status
Simulation time 9923881123 ps
CPU time 23.75 seconds
Started Jun 26 05:14:55 PM PDT 24
Finished Jun 26 05:15:21 PM PDT 24
Peak memory 206496 kb
Host smart-d63a42ed-c767-41d2-8d27-841f20ca6da1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38992
62311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.3899262311
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.570772730
Short name T806
Test name
Test status
Simulation time 205459806 ps
CPU time 0.84 seconds
Started Jun 26 05:14:54 PM PDT 24
Finished Jun 26 05:14:56 PM PDT 24
Peak memory 206180 kb
Host smart-773cd43b-8051-464a-86f4-c0e3705d574a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57077
2730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.570772730
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.1678090757
Short name T1865
Test name
Test status
Simulation time 225272976 ps
CPU time 0.95 seconds
Started Jun 26 05:14:56 PM PDT 24
Finished Jun 26 05:14:59 PM PDT 24
Peak memory 206224 kb
Host smart-58bdbb87-99ba-419c-a408-99813c636ca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16780
90757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.1678090757
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.2992018531
Short name T353
Test name
Test status
Simulation time 227491279 ps
CPU time 0.98 seconds
Started Jun 26 05:15:01 PM PDT 24
Finished Jun 26 05:15:03 PM PDT 24
Peak memory 206200 kb
Host smart-d860ad58-6534-4be4-adf3-5bbe9f551614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29920
18531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.2992018531
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.3347697199
Short name T2244
Test name
Test status
Simulation time 168743388 ps
CPU time 0.83 seconds
Started Jun 26 05:14:52 PM PDT 24
Finished Jun 26 05:14:54 PM PDT 24
Peak memory 206172 kb
Host smart-44059164-c561-41a0-87d3-9bb9a69a341e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33476
97199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.3347697199
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.4042449601
Short name T1290
Test name
Test status
Simulation time 190869107 ps
CPU time 0.84 seconds
Started Jun 26 05:14:56 PM PDT 24
Finished Jun 26 05:14:58 PM PDT 24
Peak memory 206168 kb
Host smart-2349b69e-2280-4265-8846-e58db92966ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40424
49601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.4042449601
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.3057896994
Short name T1230
Test name
Test status
Simulation time 171176528 ps
CPU time 0.76 seconds
Started Jun 26 05:14:53 PM PDT 24
Finished Jun 26 05:14:56 PM PDT 24
Peak memory 206172 kb
Host smart-ecc0a62a-f03f-4d16-89c8-6f3a79524661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30578
96994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.3057896994
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.2529565025
Short name T596
Test name
Test status
Simulation time 174405302 ps
CPU time 0.79 seconds
Started Jun 26 05:14:57 PM PDT 24
Finished Jun 26 05:14:59 PM PDT 24
Peak memory 206224 kb
Host smart-5f2b2a17-f6c2-4464-9282-e4e55b4648f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25295
65025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.2529565025
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.1955659611
Short name T1338
Test name
Test status
Simulation time 240324946 ps
CPU time 0.96 seconds
Started Jun 26 05:14:55 PM PDT 24
Finished Jun 26 05:14:58 PM PDT 24
Peak memory 206176 kb
Host smart-9f53cfc6-16b5-418e-93a2-5cd76110738e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19556
59611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.1955659611
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.3560056967
Short name T1429
Test name
Test status
Simulation time 6302806096 ps
CPU time 58.47 seconds
Started Jun 26 05:14:55 PM PDT 24
Finished Jun 26 05:15:55 PM PDT 24
Peak memory 206512 kb
Host smart-f3bbf2f0-d623-4717-822d-343b505f4acb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3560056967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.3560056967
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.1749132153
Short name T2269
Test name
Test status
Simulation time 182661018 ps
CPU time 0.79 seconds
Started Jun 26 05:14:53 PM PDT 24
Finished Jun 26 05:14:56 PM PDT 24
Peak memory 206084 kb
Host smart-4716ddfa-be3f-4780-b428-2dfaa225f5cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17491
32153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.1749132153
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.1896902910
Short name T464
Test name
Test status
Simulation time 185907629 ps
CPU time 0.79 seconds
Started Jun 26 05:14:52 PM PDT 24
Finished Jun 26 05:14:54 PM PDT 24
Peak memory 206204 kb
Host smart-34c2528b-ad6c-43fa-952e-9a541c0ef33e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18969
02910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.1896902910
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.870770682
Short name T1116
Test name
Test status
Simulation time 7979899310 ps
CPU time 58.63 seconds
Started Jun 26 05:14:55 PM PDT 24
Finished Jun 26 05:15:56 PM PDT 24
Peak memory 206464 kb
Host smart-d9e6e0aa-2c14-4889-acea-ee19d383888c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87077
0682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.870770682
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.2248337367
Short name T12
Test name
Test status
Simulation time 4239692011 ps
CPU time 5.31 seconds
Started Jun 26 05:15:02 PM PDT 24
Finished Jun 26 05:15:09 PM PDT 24
Peak memory 206256 kb
Host smart-76426e23-1a55-4617-b2b4-8ade4fb9d917
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2248337367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.2248337367
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.3274211899
Short name T1677
Test name
Test status
Simulation time 13383484650 ps
CPU time 14.63 seconds
Started Jun 26 05:15:01 PM PDT 24
Finished Jun 26 05:15:18 PM PDT 24
Peak memory 206508 kb
Host smart-bd5426aa-b760-446c-a12d-a46b8b6715ed
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3274211899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.3274211899
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.1969959634
Short name T1904
Test name
Test status
Simulation time 23363107543 ps
CPU time 26.2 seconds
Started Jun 26 05:15:03 PM PDT 24
Finished Jun 26 05:15:31 PM PDT 24
Peak memory 206600 kb
Host smart-d7e4f6eb-24dc-43ec-a41a-1f555c396c47
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1969959634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.1969959634
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.3606304176
Short name T1551
Test name
Test status
Simulation time 149685586 ps
CPU time 0.83 seconds
Started Jun 26 05:15:00 PM PDT 24
Finished Jun 26 05:15:03 PM PDT 24
Peak memory 206396 kb
Host smart-9c35b7d7-aff8-4fd1-97af-12dd7dea494c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36063
04176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.3606304176
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.4001319460
Short name T435
Test name
Test status
Simulation time 180907401 ps
CPU time 0.86 seconds
Started Jun 26 05:15:02 PM PDT 24
Finished Jun 26 05:15:05 PM PDT 24
Peak memory 206168 kb
Host smart-81c3a699-0d82-4bd9-81e3-5e01b24d2d8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40013
19460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.4001319460
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.3304374615
Short name T2331
Test name
Test status
Simulation time 280264255 ps
CPU time 1.04 seconds
Started Jun 26 05:15:00 PM PDT 24
Finished Jun 26 05:15:03 PM PDT 24
Peak memory 206148 kb
Host smart-0bd7db21-42fc-45db-a63e-6ffb3b5a041a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33043
74615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.3304374615
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.2983778065
Short name T178
Test name
Test status
Simulation time 1551079264 ps
CPU time 3.19 seconds
Started Jun 26 05:15:01 PM PDT 24
Finished Jun 26 05:15:07 PM PDT 24
Peak memory 206428 kb
Host smart-973dd565-5f42-4bde-8c08-68b6dd832da9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29837
78065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.2983778065
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.1985166583
Short name T916
Test name
Test status
Simulation time 17492830202 ps
CPU time 36.57 seconds
Started Jun 26 05:14:58 PM PDT 24
Finished Jun 26 05:15:35 PM PDT 24
Peak memory 206480 kb
Host smart-bb00d78b-a2cc-49cb-be6c-b248484920d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19851
66583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.1985166583
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.1274947470
Short name T621
Test name
Test status
Simulation time 427700209 ps
CPU time 1.32 seconds
Started Jun 26 05:15:00 PM PDT 24
Finished Jun 26 05:15:02 PM PDT 24
Peak memory 206232 kb
Host smart-1567770b-f17b-46c2-a1c9-43f5a5af5cb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12749
47470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.1274947470
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.2655171696
Short name T601
Test name
Test status
Simulation time 167002305 ps
CPU time 0.91 seconds
Started Jun 26 05:15:00 PM PDT 24
Finished Jun 26 05:15:03 PM PDT 24
Peak memory 206116 kb
Host smart-fe2dabcd-f753-42be-8e82-1895f9ed7ae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26551
71696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.2655171696
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.4219402866
Short name T2155
Test name
Test status
Simulation time 35898426 ps
CPU time 0.68 seconds
Started Jun 26 05:15:02 PM PDT 24
Finished Jun 26 05:15:05 PM PDT 24
Peak memory 206228 kb
Host smart-70581835-fe3f-40f8-b518-f049587ea12c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42194
02866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.4219402866
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.1665446856
Short name T417
Test name
Test status
Simulation time 903971018 ps
CPU time 1.99 seconds
Started Jun 26 05:14:59 PM PDT 24
Finished Jun 26 05:15:03 PM PDT 24
Peak memory 206416 kb
Host smart-66cb1771-3426-4149-9cf6-535d4ce87845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16654
46856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.1665446856
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.3338748799
Short name T701
Test name
Test status
Simulation time 192769207 ps
CPU time 1.87 seconds
Started Jun 26 05:14:59 PM PDT 24
Finished Jun 26 05:15:02 PM PDT 24
Peak memory 206468 kb
Host smart-78e65953-8c7d-4ac7-8adf-cfd82fd30a8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33387
48799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.3338748799
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.4006987987
Short name T1924
Test name
Test status
Simulation time 227392197 ps
CPU time 0.91 seconds
Started Jun 26 05:15:07 PM PDT 24
Finished Jun 26 05:15:09 PM PDT 24
Peak memory 206148 kb
Host smart-603918e2-d122-41b3-8b99-0db2976be9f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40069
87987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.4006987987
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.3322625111
Short name T2508
Test name
Test status
Simulation time 147972280 ps
CPU time 0.75 seconds
Started Jun 26 05:15:06 PM PDT 24
Finished Jun 26 05:15:08 PM PDT 24
Peak memory 206136 kb
Host smart-174be834-3263-4320-99cd-f781537412ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33226
25111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.3322625111
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.789122693
Short name T504
Test name
Test status
Simulation time 182884418 ps
CPU time 0.94 seconds
Started Jun 26 05:15:02 PM PDT 24
Finished Jun 26 05:15:05 PM PDT 24
Peak memory 206184 kb
Host smart-efea30a0-cef0-40fc-95a2-609c05c07d56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78912
2693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.789122693
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_invalid_sync.3758316761
Short name T1136
Test name
Test status
Simulation time 8031447286 ps
CPU time 60.69 seconds
Started Jun 26 05:15:01 PM PDT 24
Finished Jun 26 05:16:04 PM PDT 24
Peak memory 206532 kb
Host smart-340d5516-ab2a-458d-be4f-4a8fd6211e02
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3758316761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.3758316761
Directory /workspace/13.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.1707187320
Short name T54
Test name
Test status
Simulation time 165346915 ps
CPU time 0.77 seconds
Started Jun 26 05:15:01 PM PDT 24
Finished Jun 26 05:15:04 PM PDT 24
Peak memory 206192 kb
Host smart-e59ef5fe-f211-4b15-ba7f-1120da947861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17071
87320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.1707187320
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.4089633614
Short name T2308
Test name
Test status
Simulation time 23307900661 ps
CPU time 23.69 seconds
Started Jun 26 05:15:02 PM PDT 24
Finished Jun 26 05:15:28 PM PDT 24
Peak memory 206332 kb
Host smart-f550be8a-bca3-4330-b3c1-f3fdc4b17758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40896
33614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.4089633614
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.1929112107
Short name T1271
Test name
Test status
Simulation time 3309593263 ps
CPU time 3.92 seconds
Started Jun 26 05:15:00 PM PDT 24
Finished Jun 26 05:15:05 PM PDT 24
Peak memory 206232 kb
Host smart-2b8c18f5-4e3a-4577-b9c3-304be31ef133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19291
12107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.1929112107
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.3389400548
Short name T1072
Test name
Test status
Simulation time 5777855109 ps
CPU time 155.44 seconds
Started Jun 26 05:15:01 PM PDT 24
Finished Jun 26 05:17:39 PM PDT 24
Peak memory 206548 kb
Host smart-f53e16ad-3c44-4b39-9c8f-f263b63d6dfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33894
00548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.3389400548
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.2985605890
Short name T580
Test name
Test status
Simulation time 3028487692 ps
CPU time 20.89 seconds
Started Jun 26 05:15:07 PM PDT 24
Finished Jun 26 05:15:29 PM PDT 24
Peak memory 206540 kb
Host smart-a1251e9b-3293-483f-89af-39329dfa39e8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2985605890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.2985605890
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.2712328432
Short name T327
Test name
Test status
Simulation time 242504594 ps
CPU time 0.97 seconds
Started Jun 26 05:15:16 PM PDT 24
Finished Jun 26 05:15:17 PM PDT 24
Peak memory 206136 kb
Host smart-fedbf004-f236-430d-8259-cde5464fcccb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2712328432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.2712328432
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.1311251061
Short name T1275
Test name
Test status
Simulation time 236783128 ps
CPU time 0.89 seconds
Started Jun 26 05:15:01 PM PDT 24
Finished Jun 26 05:15:04 PM PDT 24
Peak memory 206212 kb
Host smart-af532059-6e91-4ea5-b031-179833a5defc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13112
51061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.1311251061
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.3356251275
Short name T156
Test name
Test status
Simulation time 6680311502 ps
CPU time 45.82 seconds
Started Jun 26 05:15:01 PM PDT 24
Finished Jun 26 05:15:48 PM PDT 24
Peak memory 206524 kb
Host smart-e958c45c-761f-4106-b302-5125a21e2364
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33562
51275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.3356251275
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.1913813763
Short name T1632
Test name
Test status
Simulation time 7979398973 ps
CPU time 56.03 seconds
Started Jun 26 05:15:02 PM PDT 24
Finished Jun 26 05:16:00 PM PDT 24
Peak memory 206500 kb
Host smart-a8d0c133-7d53-45d8-9399-9a99877f60ee
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1913813763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.1913813763
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.195969796
Short name T2579
Test name
Test status
Simulation time 156536662 ps
CPU time 0.8 seconds
Started Jun 26 05:15:13 PM PDT 24
Finished Jun 26 05:15:15 PM PDT 24
Peak memory 206140 kb
Host smart-e3937885-3acb-4947-b956-3864fc183020
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=195969796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.195969796
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.1059642034
Short name T661
Test name
Test status
Simulation time 150404429 ps
CPU time 0.8 seconds
Started Jun 26 05:15:03 PM PDT 24
Finished Jun 26 05:15:06 PM PDT 24
Peak memory 206176 kb
Host smart-8cae0b3f-600d-4a3a-be2b-6b81efe2d400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10596
42034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.1059642034
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.690748560
Short name T773
Test name
Test status
Simulation time 233138294 ps
CPU time 0.86 seconds
Started Jun 26 05:15:09 PM PDT 24
Finished Jun 26 05:15:11 PM PDT 24
Peak memory 206188 kb
Host smart-cb6b7e5f-8201-4504-a294-3e5bce794777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69074
8560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.690748560
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.1168991190
Short name T1035
Test name
Test status
Simulation time 157929913 ps
CPU time 0.79 seconds
Started Jun 26 05:15:08 PM PDT 24
Finished Jun 26 05:15:10 PM PDT 24
Peak memory 206208 kb
Host smart-00bcfe17-1a29-4173-93f0-09784ed4fed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11689
91190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.1168991190
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.1236245341
Short name T1028
Test name
Test status
Simulation time 151665313 ps
CPU time 0.8 seconds
Started Jun 26 05:15:09 PM PDT 24
Finished Jun 26 05:15:11 PM PDT 24
Peak memory 206180 kb
Host smart-01202ac2-8bc2-43de-b940-ef9ec370e08d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12362
45341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.1236245341
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.812741057
Short name T1385
Test name
Test status
Simulation time 157415964 ps
CPU time 0.76 seconds
Started Jun 26 05:15:10 PM PDT 24
Finished Jun 26 05:15:12 PM PDT 24
Peak memory 206192 kb
Host smart-e565b400-c013-453f-a4a0-c23c73af8af3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81274
1057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.812741057
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.2362334679
Short name T1951
Test name
Test status
Simulation time 228365691 ps
CPU time 0.92 seconds
Started Jun 26 05:15:10 PM PDT 24
Finished Jun 26 05:15:12 PM PDT 24
Peak memory 206240 kb
Host smart-65cf2707-9bf8-451e-991c-4fb20a2291d4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2362334679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.2362334679
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.502790516
Short name T977
Test name
Test status
Simulation time 140215836 ps
CPU time 0.75 seconds
Started Jun 26 05:15:05 PM PDT 24
Finished Jun 26 05:15:07 PM PDT 24
Peak memory 206144 kb
Host smart-fb3fddef-440f-4a29-b009-2e5cde145873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50279
0516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.502790516
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.1698023446
Short name T777
Test name
Test status
Simulation time 72066320 ps
CPU time 0.66 seconds
Started Jun 26 05:15:09 PM PDT 24
Finished Jun 26 05:15:11 PM PDT 24
Peak memory 206120 kb
Host smart-325f117c-a60a-4531-9165-50a9090b1300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16980
23446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.1698023446
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.3971264446
Short name T1722
Test name
Test status
Simulation time 8775953546 ps
CPU time 18.64 seconds
Started Jun 26 05:15:11 PM PDT 24
Finished Jun 26 05:15:30 PM PDT 24
Peak memory 206592 kb
Host smart-674f29cc-d361-4fee-a2ff-f9c649b633c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39712
64446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.3971264446
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.1088357640
Short name T1472
Test name
Test status
Simulation time 250336683 ps
CPU time 0.9 seconds
Started Jun 26 05:15:09 PM PDT 24
Finished Jun 26 05:15:11 PM PDT 24
Peak memory 206180 kb
Host smart-0be6fcc0-4979-41b6-aa7c-147188578a96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10883
57640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.1088357640
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.4107010870
Short name T1089
Test name
Test status
Simulation time 253168416 ps
CPU time 0.92 seconds
Started Jun 26 05:15:09 PM PDT 24
Finished Jun 26 05:15:11 PM PDT 24
Peak memory 206208 kb
Host smart-6f831e01-aa1f-4361-b8cf-089edb1b48eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41070
10870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.4107010870
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.439484497
Short name T1786
Test name
Test status
Simulation time 188375502 ps
CPU time 0.8 seconds
Started Jun 26 05:15:13 PM PDT 24
Finished Jun 26 05:15:15 PM PDT 24
Peak memory 206140 kb
Host smart-2f1303c3-5107-4e1f-860f-58e38ba6bdf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43948
4497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.439484497
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.357945645
Short name T2228
Test name
Test status
Simulation time 201913555 ps
CPU time 0.9 seconds
Started Jun 26 05:15:08 PM PDT 24
Finished Jun 26 05:15:10 PM PDT 24
Peak memory 206124 kb
Host smart-d4771bdf-385a-4eee-9b4f-c52e21b75f42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35794
5645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.357945645
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.223128388
Short name T2085
Test name
Test status
Simulation time 160443315 ps
CPU time 0.76 seconds
Started Jun 26 05:15:07 PM PDT 24
Finished Jun 26 05:15:09 PM PDT 24
Peak memory 206172 kb
Host smart-b545978e-6fd0-44a7-a9f2-5a912c7cbeef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22312
8388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.223128388
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.245330985
Short name T1255
Test name
Test status
Simulation time 227145550 ps
CPU time 0.9 seconds
Started Jun 26 05:15:06 PM PDT 24
Finished Jun 26 05:15:08 PM PDT 24
Peak memory 206172 kb
Host smart-cc4ba511-2b29-41b0-b86f-ac4ea80930fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24533
0985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.245330985
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.572310971
Short name T2383
Test name
Test status
Simulation time 157308385 ps
CPU time 0.76 seconds
Started Jun 26 05:15:10 PM PDT 24
Finished Jun 26 05:15:11 PM PDT 24
Peak memory 206132 kb
Host smart-34b0aa0a-e0fc-4912-bccf-8aa532cc4f36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57231
0971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.572310971
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.3511465801
Short name T2492
Test name
Test status
Simulation time 227026431 ps
CPU time 0.98 seconds
Started Jun 26 05:15:09 PM PDT 24
Finished Jun 26 05:15:11 PM PDT 24
Peak memory 206188 kb
Host smart-a25cdadf-17e0-4c13-96b1-106f40866cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35114
65801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.3511465801
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.3724458566
Short name T760
Test name
Test status
Simulation time 4923047125 ps
CPU time 129.95 seconds
Started Jun 26 05:15:10 PM PDT 24
Finished Jun 26 05:17:21 PM PDT 24
Peak memory 206524 kb
Host smart-bd41949e-94f7-4557-b1c7-f209fe7ae834
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3724458566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.3724458566
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.962226103
Short name T2476
Test name
Test status
Simulation time 154536599 ps
CPU time 0.76 seconds
Started Jun 26 05:15:07 PM PDT 24
Finished Jun 26 05:15:09 PM PDT 24
Peak memory 206188 kb
Host smart-9d896621-de50-435b-8aec-a47f29dd6fb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96222
6103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.962226103
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.2314666299
Short name T1825
Test name
Test status
Simulation time 170950680 ps
CPU time 0.83 seconds
Started Jun 26 05:15:08 PM PDT 24
Finished Jun 26 05:15:09 PM PDT 24
Peak memory 206120 kb
Host smart-95fd3878-d659-4e16-9ed0-185383d021f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23146
66299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.2314666299
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.534827563
Short name T1112
Test name
Test status
Simulation time 4960153234 ps
CPU time 148.36 seconds
Started Jun 26 05:15:09 PM PDT 24
Finished Jun 26 05:17:38 PM PDT 24
Peak memory 206472 kb
Host smart-40152f7b-2f26-4f5e-966c-44a84dd36c7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53482
7563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.534827563
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.1302429893
Short name T2404
Test name
Test status
Simulation time 4047859935 ps
CPU time 4.92 seconds
Started Jun 26 05:15:17 PM PDT 24
Finished Jun 26 05:15:22 PM PDT 24
Peak memory 206308 kb
Host smart-05400b7c-6a26-4b01-ac98-f6c0eaae0cc7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1302429893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.1302429893
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.2585166126
Short name T2216
Test name
Test status
Simulation time 23389513583 ps
CPU time 25.17 seconds
Started Jun 26 05:15:15 PM PDT 24
Finished Jun 26 05:15:41 PM PDT 24
Peak memory 206512 kb
Host smart-a1f35b4b-3181-4d0e-ac17-3bc760185724
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2585166126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.2585166126
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.2794809189
Short name T2168
Test name
Test status
Simulation time 193735456 ps
CPU time 0.8 seconds
Started Jun 26 05:15:14 PM PDT 24
Finished Jun 26 05:15:16 PM PDT 24
Peak memory 206100 kb
Host smart-e9da7e72-2800-4f3c-99f6-72028e6a2e49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27948
09189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.2794809189
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.2794369190
Short name T1593
Test name
Test status
Simulation time 143804660 ps
CPU time 0.8 seconds
Started Jun 26 05:15:19 PM PDT 24
Finished Jun 26 05:15:20 PM PDT 24
Peak memory 206184 kb
Host smart-e2cfb191-15c4-4dd9-9d34-465518735d75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27943
69190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.2794369190
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.667851108
Short name T2038
Test name
Test status
Simulation time 180635045 ps
CPU time 0.85 seconds
Started Jun 26 05:15:17 PM PDT 24
Finished Jun 26 05:15:19 PM PDT 24
Peak memory 206396 kb
Host smart-26f6b09b-bcea-4161-93b0-e370f826492c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66785
1108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.667851108
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.1066034899
Short name T1358
Test name
Test status
Simulation time 598022119 ps
CPU time 1.44 seconds
Started Jun 26 05:15:15 PM PDT 24
Finished Jun 26 05:15:18 PM PDT 24
Peak memory 206128 kb
Host smart-d0af08da-1a23-4d32-993f-0d6a8f1c03dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10660
34899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.1066034899
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.1328789082
Short name T191
Test name
Test status
Simulation time 7973080464 ps
CPU time 14.84 seconds
Started Jun 26 05:15:13 PM PDT 24
Finished Jun 26 05:15:29 PM PDT 24
Peak memory 206512 kb
Host smart-5d7bf98b-cc9e-4264-8d89-fa0e95fdc415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13287
89082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.1328789082
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.3561243545
Short name T436
Test name
Test status
Simulation time 347227268 ps
CPU time 1.11 seconds
Started Jun 26 05:15:17 PM PDT 24
Finished Jun 26 05:15:19 PM PDT 24
Peak memory 206180 kb
Host smart-1175704c-5c48-45db-a2e8-c147f637549a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35612
43545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.3561243545
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.3676303886
Short name T2267
Test name
Test status
Simulation time 162131985 ps
CPU time 0.77 seconds
Started Jun 26 05:15:20 PM PDT 24
Finished Jun 26 05:15:22 PM PDT 24
Peak memory 206116 kb
Host smart-7564448e-9b26-4d1d-970b-cc234e53dd9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36763
03886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.3676303886
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.243159152
Short name T869
Test name
Test status
Simulation time 29402761 ps
CPU time 0.64 seconds
Started Jun 26 05:15:17 PM PDT 24
Finished Jun 26 05:15:19 PM PDT 24
Peak memory 206220 kb
Host smart-b7f16ef4-8b17-4a16-8f12-27c5d2fb6a4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24315
9152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.243159152
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.2497849649
Short name T673
Test name
Test status
Simulation time 700812094 ps
CPU time 1.72 seconds
Started Jun 26 05:15:18 PM PDT 24
Finished Jun 26 05:15:20 PM PDT 24
Peak memory 206336 kb
Host smart-b68cdf56-a432-4916-b3a0-b7de11194bad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24978
49649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.2497849649
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.3622747219
Short name T649
Test name
Test status
Simulation time 241781217 ps
CPU time 2.22 seconds
Started Jun 26 05:15:20 PM PDT 24
Finished Jun 26 05:15:23 PM PDT 24
Peak memory 206340 kb
Host smart-6a9288b6-2dd8-4e47-a78d-310efc533114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36227
47219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.3622747219
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.3802934053
Short name T1329
Test name
Test status
Simulation time 206164753 ps
CPU time 0.92 seconds
Started Jun 26 05:15:26 PM PDT 24
Finished Jun 26 05:15:27 PM PDT 24
Peak memory 206140 kb
Host smart-f50b8205-6816-442a-81c1-4d36f3a5c580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38029
34053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.3802934053
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.1941440895
Short name T879
Test name
Test status
Simulation time 171791940 ps
CPU time 0.8 seconds
Started Jun 26 05:15:30 PM PDT 24
Finished Jun 26 05:15:32 PM PDT 24
Peak memory 206192 kb
Host smart-9bf598d9-f3bb-4296-a7cc-932ee0322153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19414
40895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.1941440895
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.1088762726
Short name T865
Test name
Test status
Simulation time 197723210 ps
CPU time 0.88 seconds
Started Jun 26 05:15:19 PM PDT 24
Finished Jun 26 05:15:21 PM PDT 24
Peak memory 206092 kb
Host smart-4cd1a329-5db5-469b-bc20-2def0667cb90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10887
62726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.1088762726
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.3765378544
Short name T1491
Test name
Test status
Simulation time 191418199 ps
CPU time 0.85 seconds
Started Jun 26 05:15:20 PM PDT 24
Finished Jun 26 05:15:22 PM PDT 24
Peak memory 206224 kb
Host smart-4fbfcdb0-418d-4344-a32c-609fa2c0d158
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37653
78544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.3765378544
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.3501433094
Short name T1528
Test name
Test status
Simulation time 23361441912 ps
CPU time 24.54 seconds
Started Jun 26 05:15:21 PM PDT 24
Finished Jun 26 05:15:46 PM PDT 24
Peak memory 206316 kb
Host smart-b283afda-e0b3-4513-b7cc-f7991b165dab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35014
33094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.3501433094
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.517761390
Short name T882
Test name
Test status
Simulation time 3340579029 ps
CPU time 4.68 seconds
Started Jun 26 05:15:32 PM PDT 24
Finished Jun 26 05:15:37 PM PDT 24
Peak memory 206240 kb
Host smart-0db54868-0c1d-41a4-87d6-c955c1f0b1fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51776
1390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.517761390
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.508989834
Short name T796
Test name
Test status
Simulation time 9590464273 ps
CPU time 64.66 seconds
Started Jun 26 05:15:20 PM PDT 24
Finished Jun 26 05:16:26 PM PDT 24
Peak memory 206540 kb
Host smart-03051a56-ba7b-4ea7-b641-da3a3773c3ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50898
9834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.508989834
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.3479768045
Short name T1002
Test name
Test status
Simulation time 6922447539 ps
CPU time 51.43 seconds
Started Jun 26 05:15:22 PM PDT 24
Finished Jun 26 05:16:14 PM PDT 24
Peak memory 206772 kb
Host smart-3932910e-8343-4a79-aeb9-0c066cf93940
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3479768045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.3479768045
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.2153305620
Short name T1259
Test name
Test status
Simulation time 267309026 ps
CPU time 0.91 seconds
Started Jun 26 05:15:27 PM PDT 24
Finished Jun 26 05:15:29 PM PDT 24
Peak memory 206236 kb
Host smart-612291de-32d8-4566-be95-38a365287134
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2153305620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.2153305620
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.3176419782
Short name T1669
Test name
Test status
Simulation time 216533979 ps
CPU time 0.91 seconds
Started Jun 26 05:15:21 PM PDT 24
Finished Jun 26 05:15:23 PM PDT 24
Peak memory 206120 kb
Host smart-53517a1b-baa7-410b-bb34-5e1ccd6409ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31764
19782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.3176419782
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.4038605522
Short name T2045
Test name
Test status
Simulation time 6252620197 ps
CPU time 53.18 seconds
Started Jun 26 05:15:22 PM PDT 24
Finished Jun 26 05:16:16 PM PDT 24
Peak memory 206444 kb
Host smart-3eba7dc3-26a8-475d-80f3-9abe26253f38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40386
05522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.4038605522
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.3379556001
Short name T2009
Test name
Test status
Simulation time 3958052798 ps
CPU time 34.86 seconds
Started Jun 26 05:15:20 PM PDT 24
Finished Jun 26 05:15:56 PM PDT 24
Peak memory 206496 kb
Host smart-e358b152-c5ad-4bbd-93e7-2b89b2909169
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3379556001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.3379556001
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.2392447693
Short name T973
Test name
Test status
Simulation time 164874451 ps
CPU time 0.79 seconds
Started Jun 26 05:15:29 PM PDT 24
Finished Jun 26 05:15:31 PM PDT 24
Peak memory 206192 kb
Host smart-f21bd80f-5387-4516-80a6-deb6d802715b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2392447693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.2392447693
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.2107455063
Short name T1376
Test name
Test status
Simulation time 149655309 ps
CPU time 0.76 seconds
Started Jun 26 05:15:19 PM PDT 24
Finished Jun 26 05:15:20 PM PDT 24
Peak memory 206128 kb
Host smart-af3a5169-8678-45a0-9aee-e7849c857655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21074
55063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.2107455063
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.2626080939
Short name T2379
Test name
Test status
Simulation time 156269123 ps
CPU time 0.81 seconds
Started Jun 26 05:15:23 PM PDT 24
Finished Jun 26 05:15:25 PM PDT 24
Peak memory 206224 kb
Host smart-c7e3e121-dd86-486e-a425-ed8c6c66292b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26260
80939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.2626080939
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.1227435220
Short name T2544
Test name
Test status
Simulation time 188009308 ps
CPU time 0.8 seconds
Started Jun 26 05:15:21 PM PDT 24
Finished Jun 26 05:15:23 PM PDT 24
Peak memory 206212 kb
Host smart-b0feca0c-b3f9-4b7f-b3b7-c023a94e1fc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12274
35220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.1227435220
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.1807583949
Short name T430
Test name
Test status
Simulation time 152636719 ps
CPU time 0.83 seconds
Started Jun 26 05:15:23 PM PDT 24
Finished Jun 26 05:15:25 PM PDT 24
Peak memory 206120 kb
Host smart-077b4716-d2f2-4fe0-b369-36e74816e83b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18075
83949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.1807583949
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.2692880816
Short name T1649
Test name
Test status
Simulation time 167090872 ps
CPU time 0.8 seconds
Started Jun 26 05:15:27 PM PDT 24
Finished Jun 26 05:15:28 PM PDT 24
Peak memory 206128 kb
Host smart-552ef092-83c3-4fa1-bc1b-18b8705f5c47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26928
80816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.2692880816
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.3470580599
Short name T2481
Test name
Test status
Simulation time 273073506 ps
CPU time 0.96 seconds
Started Jun 26 05:15:29 PM PDT 24
Finished Jun 26 05:15:31 PM PDT 24
Peak memory 206240 kb
Host smart-888f7a8d-73a4-473c-9927-134b8b8e2d89
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3470580599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.3470580599
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.673378476
Short name T1480
Test name
Test status
Simulation time 143217532 ps
CPU time 0.79 seconds
Started Jun 26 05:15:30 PM PDT 24
Finished Jun 26 05:15:32 PM PDT 24
Peak memory 206180 kb
Host smart-714a015f-3d28-47e8-9a0e-1a449b9237d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67337
8476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.673378476
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.2168964517
Short name T263
Test name
Test status
Simulation time 20664536524 ps
CPU time 44.75 seconds
Started Jun 26 05:15:28 PM PDT 24
Finished Jun 26 05:16:15 PM PDT 24
Peak memory 206512 kb
Host smart-06f8704e-367b-48cc-8d00-019a94b7e003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21689
64517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.2168964517
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.4054240928
Short name T1734
Test name
Test status
Simulation time 204360981 ps
CPU time 0.85 seconds
Started Jun 26 05:15:28 PM PDT 24
Finished Jun 26 05:15:30 PM PDT 24
Peak memory 206176 kb
Host smart-d8072688-8627-4053-a1f9-661fe964c335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40542
40928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.4054240928
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.59015231
Short name T1169
Test name
Test status
Simulation time 254180976 ps
CPU time 0.88 seconds
Started Jun 26 05:15:28 PM PDT 24
Finished Jun 26 05:15:30 PM PDT 24
Peak memory 206228 kb
Host smart-ae103b7e-a550-46f1-a7ff-b028d87bd9a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59015
231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.59015231
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.2782077263
Short name T293
Test name
Test status
Simulation time 250874974 ps
CPU time 0.87 seconds
Started Jun 26 05:15:28 PM PDT 24
Finished Jun 26 05:15:30 PM PDT 24
Peak memory 206136 kb
Host smart-a9df6435-666e-46fe-b251-be73efad4e89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27820
77263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.2782077263
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.2024615408
Short name T956
Test name
Test status
Simulation time 178986722 ps
CPU time 0.85 seconds
Started Jun 26 05:15:31 PM PDT 24
Finished Jun 26 05:15:33 PM PDT 24
Peak memory 206228 kb
Host smart-b642b65b-310f-4421-93e1-96acbcac62f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20246
15408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.2024615408
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.2746736033
Short name T868
Test name
Test status
Simulation time 164593527 ps
CPU time 0.82 seconds
Started Jun 26 05:15:29 PM PDT 24
Finished Jun 26 05:15:31 PM PDT 24
Peak memory 206208 kb
Host smart-61071f9e-fed0-45e1-b021-b5a5763ad863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27467
36033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.2746736033
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.211618881
Short name T532
Test name
Test status
Simulation time 163614399 ps
CPU time 0.78 seconds
Started Jun 26 05:15:27 PM PDT 24
Finished Jun 26 05:15:29 PM PDT 24
Peak memory 206208 kb
Host smart-83bacac9-8baa-4a61-a3fd-8597687ee836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21161
8881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.211618881
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.1049603205
Short name T1405
Test name
Test status
Simulation time 148506812 ps
CPU time 0.83 seconds
Started Jun 26 05:15:28 PM PDT 24
Finished Jun 26 05:15:30 PM PDT 24
Peak memory 206132 kb
Host smart-97e0614a-61df-431f-92ed-3d68c8780da4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10496
03205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.1049603205
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.2889341256
Short name T1315
Test name
Test status
Simulation time 231702839 ps
CPU time 0.97 seconds
Started Jun 26 05:15:30 PM PDT 24
Finished Jun 26 05:15:32 PM PDT 24
Peak memory 206188 kb
Host smart-551c85d2-cd71-4334-a379-c51fc41a0ed9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28893
41256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.2889341256
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.4139590992
Short name T1687
Test name
Test status
Simulation time 7135943357 ps
CPU time 66.06 seconds
Started Jun 26 05:15:31 PM PDT 24
Finished Jun 26 05:16:38 PM PDT 24
Peak memory 206512 kb
Host smart-8015bf20-03b3-4a81-957c-2f877a180026
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4139590992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.4139590992
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.2167339130
Short name T1663
Test name
Test status
Simulation time 199258280 ps
CPU time 0.85 seconds
Started Jun 26 05:15:28 PM PDT 24
Finished Jun 26 05:15:30 PM PDT 24
Peak memory 206116 kb
Host smart-124df97f-fd55-44e1-9dbf-7e7d05abd6ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21673
39130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.2167339130
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.739640437
Short name T1752
Test name
Test status
Simulation time 165458879 ps
CPU time 0.79 seconds
Started Jun 26 05:15:29 PM PDT 24
Finished Jun 26 05:15:31 PM PDT 24
Peak memory 206124 kb
Host smart-11019640-01bd-4749-8e31-f9f43b389087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73964
0437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.739640437
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.2804516619
Short name T1519
Test name
Test status
Simulation time 5564380318 ps
CPU time 52.79 seconds
Started Jun 26 05:15:31 PM PDT 24
Finished Jun 26 05:16:25 PM PDT 24
Peak memory 206720 kb
Host smart-12e8c75b-b66c-4d7c-96ce-71ab27879005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28045
16619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.2804516619
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.3475535244
Short name T1321
Test name
Test status
Simulation time 4337654567 ps
CPU time 4.48 seconds
Started Jun 26 05:15:26 PM PDT 24
Finished Jun 26 05:15:32 PM PDT 24
Peak memory 206528 kb
Host smart-bc2ce1b2-8df4-41db-b33a-01f9b2ca4929
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3475535244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.3475535244
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.1175766393
Short name T587
Test name
Test status
Simulation time 13373562747 ps
CPU time 15.95 seconds
Started Jun 26 05:15:28 PM PDT 24
Finished Jun 26 05:15:46 PM PDT 24
Peak memory 206292 kb
Host smart-fcf23792-c230-4432-b081-332c2ec427c2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1175766393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.1175766393
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.4272543116
Short name T2304
Test name
Test status
Simulation time 23340019545 ps
CPU time 24.33 seconds
Started Jun 26 05:15:34 PM PDT 24
Finished Jun 26 05:15:59 PM PDT 24
Peak memory 206236 kb
Host smart-3641c809-9ec4-4fb5-b8d4-286b2800dba7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4272543116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.4272543116
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.3119794752
Short name T497
Test name
Test status
Simulation time 180271656 ps
CPU time 0.89 seconds
Started Jun 26 05:15:42 PM PDT 24
Finished Jun 26 05:15:45 PM PDT 24
Peak memory 206212 kb
Host smart-128a6c29-ce60-461c-b123-b9a3fec83527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31197
94752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.3119794752
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.2720778354
Short name T1511
Test name
Test status
Simulation time 144496680 ps
CPU time 0.77 seconds
Started Jun 26 05:15:34 PM PDT 24
Finished Jun 26 05:15:36 PM PDT 24
Peak memory 206172 kb
Host smart-fbf675aa-483f-4f25-9774-60b82f6147fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27207
78354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.2720778354
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.343183604
Short name T1404
Test name
Test status
Simulation time 285387507 ps
CPU time 1.02 seconds
Started Jun 26 05:15:34 PM PDT 24
Finished Jun 26 05:15:36 PM PDT 24
Peak memory 206140 kb
Host smart-9d9d8be1-1089-45e4-9732-583d5e6667cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34318
3604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.343183604
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.2172501914
Short name T2137
Test name
Test status
Simulation time 18336608221 ps
CPU time 33.67 seconds
Started Jun 26 05:15:34 PM PDT 24
Finished Jun 26 05:16:09 PM PDT 24
Peak memory 206496 kb
Host smart-99737514-17d0-4005-871f-b77d12608994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21725
01914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.2172501914
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.2929556707
Short name T1785
Test name
Test status
Simulation time 485651240 ps
CPU time 1.35 seconds
Started Jun 26 05:15:42 PM PDT 24
Finished Jun 26 05:15:46 PM PDT 24
Peak memory 206100 kb
Host smart-987dbb6c-0242-466d-8beb-0c657d94fbb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29295
56707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.2929556707
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.1854789759
Short name T450
Test name
Test status
Simulation time 191328063 ps
CPU time 0.8 seconds
Started Jun 26 05:15:38 PM PDT 24
Finished Jun 26 05:15:40 PM PDT 24
Peak memory 206196 kb
Host smart-d7002080-6a4a-4cfd-8abb-1c5be970791b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18547
89759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.1854789759
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.71896661
Short name T2361
Test name
Test status
Simulation time 37571443 ps
CPU time 0.65 seconds
Started Jun 26 05:15:39 PM PDT 24
Finished Jun 26 05:15:42 PM PDT 24
Peak memory 206216 kb
Host smart-7880cbda-5c73-40ab-98a4-b455b1c5a528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71896
661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.71896661
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.2547186742
Short name T1277
Test name
Test status
Simulation time 911476745 ps
CPU time 2.29 seconds
Started Jun 26 05:15:34 PM PDT 24
Finished Jun 26 05:15:38 PM PDT 24
Peak memory 206356 kb
Host smart-5e29b04f-c09b-41e5-85a4-1ee78894aab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25471
86742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.2547186742
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.1353563914
Short name T1476
Test name
Test status
Simulation time 202805614 ps
CPU time 1.99 seconds
Started Jun 26 05:15:36 PM PDT 24
Finished Jun 26 05:15:39 PM PDT 24
Peak memory 206404 kb
Host smart-c6c1c0af-4360-4466-bdb7-a61e6ddcdd54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13535
63914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.1353563914
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.1485115920
Short name T416
Test name
Test status
Simulation time 224308648 ps
CPU time 0.96 seconds
Started Jun 26 05:15:39 PM PDT 24
Finished Jun 26 05:15:42 PM PDT 24
Peak memory 206140 kb
Host smart-40b3219d-3a8a-40c8-ac76-189dd76a79f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14851
15920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.1485115920
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.3374472941
Short name T1467
Test name
Test status
Simulation time 143684269 ps
CPU time 0.75 seconds
Started Jun 26 05:15:40 PM PDT 24
Finished Jun 26 05:15:42 PM PDT 24
Peak memory 206140 kb
Host smart-39b57258-cc26-40a1-967d-ab1884602275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33744
72941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.3374472941
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.1482938331
Short name T1840
Test name
Test status
Simulation time 193369362 ps
CPU time 0.87 seconds
Started Jun 26 05:15:42 PM PDT 24
Finished Jun 26 05:15:45 PM PDT 24
Peak memory 206220 kb
Host smart-8ccb7286-270f-4383-aba8-fa742cef442f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14829
38331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.1482938331
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.3635732432
Short name T1463
Test name
Test status
Simulation time 6370968807 ps
CPU time 56.82 seconds
Started Jun 26 05:15:32 PM PDT 24
Finished Jun 26 05:16:30 PM PDT 24
Peak memory 206560 kb
Host smart-d3805b0e-5a5e-4ecf-a0dc-3ea7f4defd35
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3635732432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.3635732432
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.2905383709
Short name T1545
Test name
Test status
Simulation time 173781434 ps
CPU time 0.86 seconds
Started Jun 26 05:15:42 PM PDT 24
Finished Jun 26 05:15:45 PM PDT 24
Peak memory 206200 kb
Host smart-1e906615-d49d-4650-a8de-5586c62afcb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29053
83709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.2905383709
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.1705479341
Short name T575
Test name
Test status
Simulation time 23332317188 ps
CPU time 23.84 seconds
Started Jun 26 05:15:39 PM PDT 24
Finished Jun 26 05:16:04 PM PDT 24
Peak memory 206212 kb
Host smart-ad351318-0c70-480d-9a44-102334e7b97f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17054
79341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.1705479341
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.4114726615
Short name T2113
Test name
Test status
Simulation time 3289438452 ps
CPU time 3.41 seconds
Started Jun 26 05:15:32 PM PDT 24
Finished Jun 26 05:15:36 PM PDT 24
Peak memory 206260 kb
Host smart-c95eabb9-b30f-4b86-bd87-295156c5939c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41147
26615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.4114726615
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.2495157685
Short name T2332
Test name
Test status
Simulation time 5508950905 ps
CPU time 155.63 seconds
Started Jun 26 05:15:40 PM PDT 24
Finished Jun 26 05:18:18 PM PDT 24
Peak memory 206536 kb
Host smart-33fdfb54-4bd3-4aaa-ad50-7e0f9bf685be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24951
57685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.2495157685
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.4161090125
Short name T2573
Test name
Test status
Simulation time 7057251523 ps
CPU time 68.82 seconds
Started Jun 26 05:15:39 PM PDT 24
Finished Jun 26 05:16:49 PM PDT 24
Peak memory 206556 kb
Host smart-adb4b391-2c6b-4e34-a5e1-ecf1f51bbe53
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4161090125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.4161090125
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.1655886586
Short name T289
Test name
Test status
Simulation time 271358340 ps
CPU time 1.02 seconds
Started Jun 26 05:15:39 PM PDT 24
Finished Jun 26 05:15:42 PM PDT 24
Peak memory 206228 kb
Host smart-3088a3e6-0bd6-4fcb-9836-8b6c7a7c7ec2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1655886586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.1655886586
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.2501495331
Short name T79
Test name
Test status
Simulation time 253033763 ps
CPU time 0.91 seconds
Started Jun 26 05:15:39 PM PDT 24
Finished Jun 26 05:15:42 PM PDT 24
Peak memory 206232 kb
Host smart-680b2775-49ae-4c04-b7d5-005b98edf444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25014
95331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.2501495331
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.552917116
Short name T1811
Test name
Test status
Simulation time 5277166566 ps
CPU time 39.7 seconds
Started Jun 26 05:15:32 PM PDT 24
Finished Jun 26 05:16:13 PM PDT 24
Peak memory 206500 kb
Host smart-2fdba2fb-226d-4f5a-b190-82f2d85bdd56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55291
7116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.552917116
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.1376655350
Short name T544
Test name
Test status
Simulation time 5361893854 ps
CPU time 38.3 seconds
Started Jun 26 05:15:39 PM PDT 24
Finished Jun 26 05:16:19 PM PDT 24
Peak memory 206596 kb
Host smart-1acc861c-3496-470c-a863-feed87bbfec6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1376655350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.1376655350
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.1198064723
Short name T944
Test name
Test status
Simulation time 149671545 ps
CPU time 0.77 seconds
Started Jun 26 05:15:39 PM PDT 24
Finished Jun 26 05:15:41 PM PDT 24
Peak memory 206416 kb
Host smart-749f3023-15fb-4e4c-9bc2-0c6a96ab4bac
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1198064723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.1198064723
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.3844806511
Short name T1088
Test name
Test status
Simulation time 153524421 ps
CPU time 0.78 seconds
Started Jun 26 05:15:34 PM PDT 24
Finished Jun 26 05:15:36 PM PDT 24
Peak memory 206128 kb
Host smart-2c91eaf4-a41f-474d-a938-cd81f61bdc5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38448
06511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.3844806511
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.4201089336
Short name T1953
Test name
Test status
Simulation time 200814149 ps
CPU time 0.86 seconds
Started Jun 26 05:15:41 PM PDT 24
Finished Jun 26 05:15:44 PM PDT 24
Peak memory 206232 kb
Host smart-b6e3010f-7183-4609-8ed5-7d3f15637fdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42010
89336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.4201089336
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.1780180004
Short name T1363
Test name
Test status
Simulation time 185181273 ps
CPU time 0.84 seconds
Started Jun 26 05:15:40 PM PDT 24
Finished Jun 26 05:15:42 PM PDT 24
Peak memory 205152 kb
Host smart-7a225c41-f238-4f8b-8959-5b81ab9ad713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17801
80004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.1780180004
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.4223321694
Short name T2355
Test name
Test status
Simulation time 174541586 ps
CPU time 0.78 seconds
Started Jun 26 05:15:40 PM PDT 24
Finished Jun 26 05:15:42 PM PDT 24
Peak memory 205240 kb
Host smart-d1b17470-7d6b-4789-a82a-547a5f954983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42233
21694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.4223321694
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.867058672
Short name T1099
Test name
Test status
Simulation time 161080401 ps
CPU time 0.77 seconds
Started Jun 26 05:15:39 PM PDT 24
Finished Jun 26 05:15:41 PM PDT 24
Peak memory 206204 kb
Host smart-a7b55160-b401-4554-94b5-625491c34a59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86705
8672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.867058672
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.4174321337
Short name T737
Test name
Test status
Simulation time 148364857 ps
CPU time 0.78 seconds
Started Jun 26 05:15:42 PM PDT 24
Finished Jun 26 05:15:45 PM PDT 24
Peak memory 206180 kb
Host smart-88ad72ac-dbea-4a16-9ec3-56707ecd1928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41743
21337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.4174321337
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.758414026
Short name T813
Test name
Test status
Simulation time 223614963 ps
CPU time 0.87 seconds
Started Jun 26 05:15:34 PM PDT 24
Finished Jun 26 05:15:36 PM PDT 24
Peak memory 206224 kb
Host smart-c0b21383-db44-4161-ac99-8893613d668a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=758414026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.758414026
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.1005440189
Short name T1015
Test name
Test status
Simulation time 163445416 ps
CPU time 0.81 seconds
Started Jun 26 05:15:33 PM PDT 24
Finished Jun 26 05:15:35 PM PDT 24
Peak memory 206176 kb
Host smart-0bdaad87-b013-4c82-a7e4-3020bca92c57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10054
40189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.1005440189
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.1757553830
Short name T23
Test name
Test status
Simulation time 90612668 ps
CPU time 0.72 seconds
Started Jun 26 05:15:39 PM PDT 24
Finished Jun 26 05:15:42 PM PDT 24
Peak memory 206108 kb
Host smart-acc20224-4359-4fe6-aa39-3c99ccdd6783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17575
53830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.1757553830
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.2435164171
Short name T2145
Test name
Test status
Simulation time 16459337201 ps
CPU time 37.14 seconds
Started Jun 26 05:15:36 PM PDT 24
Finished Jun 26 05:16:14 PM PDT 24
Peak memory 206580 kb
Host smart-7ed419a8-72e7-4fe4-a016-741f56f05d85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24351
64171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.2435164171
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.3161865221
Short name T638
Test name
Test status
Simulation time 248515107 ps
CPU time 0.91 seconds
Started Jun 26 05:15:41 PM PDT 24
Finished Jun 26 05:15:44 PM PDT 24
Peak memory 206224 kb
Host smart-af94be18-2db0-4773-8794-2ce6ee60c746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31618
65221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.3161865221
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.4180998023
Short name T294
Test name
Test status
Simulation time 183485673 ps
CPU time 0.87 seconds
Started Jun 26 05:15:33 PM PDT 24
Finished Jun 26 05:15:35 PM PDT 24
Peak memory 206236 kb
Host smart-20a3504a-dcdd-46b4-8ee9-a461f5def1f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41809
98023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.4180998023
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.2640552151
Short name T2293
Test name
Test status
Simulation time 162770118 ps
CPU time 0.83 seconds
Started Jun 26 05:15:41 PM PDT 24
Finished Jun 26 05:15:44 PM PDT 24
Peak memory 206232 kb
Host smart-1884215e-d074-4596-8aa3-bd1c558a82fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26405
52151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.2640552151
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.4008970218
Short name T468
Test name
Test status
Simulation time 179195213 ps
CPU time 0.76 seconds
Started Jun 26 05:15:34 PM PDT 24
Finished Jun 26 05:15:36 PM PDT 24
Peak memory 206168 kb
Host smart-8939d10a-0dd4-4ad7-acf1-fe4ce9e0d069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40089
70218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.4008970218
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.722875531
Short name T2054
Test name
Test status
Simulation time 189174052 ps
CPU time 0.92 seconds
Started Jun 26 05:15:34 PM PDT 24
Finished Jun 26 05:15:36 PM PDT 24
Peak memory 206084 kb
Host smart-208c4bba-5ad0-448e-b025-308327615e5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72287
5531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.722875531
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.4277057412
Short name T1444
Test name
Test status
Simulation time 150866966 ps
CPU time 0.77 seconds
Started Jun 26 05:15:40 PM PDT 24
Finished Jun 26 05:15:43 PM PDT 24
Peak memory 206192 kb
Host smart-adeab54b-282b-49ca-9e96-af7f1a484cbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42770
57412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.4277057412
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.2060219956
Short name T2473
Test name
Test status
Simulation time 176058716 ps
CPU time 0.8 seconds
Started Jun 26 05:15:40 PM PDT 24
Finished Jun 26 05:15:43 PM PDT 24
Peak memory 206148 kb
Host smart-78f8d4f1-b9d5-4146-bb1d-3319a6642a1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20602
19956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.2060219956
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.2408772924
Short name T381
Test name
Test status
Simulation time 238518721 ps
CPU time 0.91 seconds
Started Jun 26 05:15:39 PM PDT 24
Finished Jun 26 05:15:42 PM PDT 24
Peak memory 206136 kb
Host smart-1a7d8beb-3457-4269-925a-802e88c48218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24087
72924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.2408772924
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.2617602913
Short name T1816
Test name
Test status
Simulation time 4502486488 ps
CPU time 29.41 seconds
Started Jun 26 05:15:42 PM PDT 24
Finished Jun 26 05:16:13 PM PDT 24
Peak memory 206512 kb
Host smart-b3f95a0c-a5c6-4cb3-ba91-88cc96cbeb8c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2617602913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.2617602913
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.1292522337
Short name T480
Test name
Test status
Simulation time 174527682 ps
CPU time 0.77 seconds
Started Jun 26 05:15:38 PM PDT 24
Finished Jun 26 05:15:40 PM PDT 24
Peak memory 206200 kb
Host smart-c3b09afc-e810-472c-93f1-e303996e80a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12925
22337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.1292522337
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.2308142718
Short name T2432
Test name
Test status
Simulation time 165576594 ps
CPU time 0.77 seconds
Started Jun 26 05:15:42 PM PDT 24
Finished Jun 26 05:15:44 PM PDT 24
Peak memory 206224 kb
Host smart-ec0fc501-ca7d-40c8-b043-74a283567a76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23081
42718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.2308142718
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.1278692922
Short name T2374
Test name
Test status
Simulation time 4213341566 ps
CPU time 38.41 seconds
Started Jun 26 05:15:39 PM PDT 24
Finished Jun 26 05:16:19 PM PDT 24
Peak memory 206528 kb
Host smart-91f6d696-4fba-4bcf-887c-6956c1a2ee5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12786
92922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.1278692922
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.2590689396
Short name T2213
Test name
Test status
Simulation time 3659673351 ps
CPU time 4.34 seconds
Started Jun 26 05:15:38 PM PDT 24
Finished Jun 26 05:15:43 PM PDT 24
Peak memory 206552 kb
Host smart-d4139af9-b85d-408a-ac08-391ec5b3e4b5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2590689396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.2590689396
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.1450534191
Short name T1367
Test name
Test status
Simulation time 13374386694 ps
CPU time 15.67 seconds
Started Jun 26 05:15:40 PM PDT 24
Finished Jun 26 05:15:57 PM PDT 24
Peak memory 206600 kb
Host smart-465564bf-9fa8-4416-aa8f-409596fb7fb8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1450534191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.1450534191
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.1095116802
Short name T1341
Test name
Test status
Simulation time 23338053204 ps
CPU time 23.32 seconds
Started Jun 26 05:15:42 PM PDT 24
Finished Jun 26 05:16:07 PM PDT 24
Peak memory 206328 kb
Host smart-910850b3-3f74-4a82-8775-30e3b7c416b9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1095116802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.1095116802
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.3388905868
Short name T74
Test name
Test status
Simulation time 164998333 ps
CPU time 0.79 seconds
Started Jun 26 05:15:45 PM PDT 24
Finished Jun 26 05:15:48 PM PDT 24
Peak memory 206208 kb
Host smart-060a2641-73e9-425b-9633-6995478ea9a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33889
05868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.3388905868
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.1434984466
Short name T56
Test name
Test status
Simulation time 140466506 ps
CPU time 0.79 seconds
Started Jun 26 05:15:47 PM PDT 24
Finished Jun 26 05:15:50 PM PDT 24
Peak memory 206164 kb
Host smart-8e581844-a571-4702-8661-bb5c3638a672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14349
84466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.1434984466
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.1296424157
Short name T113
Test name
Test status
Simulation time 334485214 ps
CPU time 1.08 seconds
Started Jun 26 05:15:46 PM PDT 24
Finished Jun 26 05:15:49 PM PDT 24
Peak memory 206208 kb
Host smart-296a3cea-fa19-435b-9874-f2928102f8c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12964
24157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.1296424157
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.1017778682
Short name T1814
Test name
Test status
Simulation time 842579438 ps
CPU time 1.89 seconds
Started Jun 26 05:15:46 PM PDT 24
Finished Jun 26 05:15:50 PM PDT 24
Peak memory 206436 kb
Host smart-18e2b3ae-8f2b-430a-a1af-af2e902e0056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10177
78682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.1017778682
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.987429134
Short name T2128
Test name
Test status
Simulation time 7436045609 ps
CPU time 15.85 seconds
Started Jun 26 05:15:45 PM PDT 24
Finished Jun 26 05:16:03 PM PDT 24
Peak memory 206516 kb
Host smart-e71ff2ad-a12c-4ab3-9cf0-c21bd518945b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98742
9134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.987429134
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.3541914785
Short name T1079
Test name
Test status
Simulation time 347213110 ps
CPU time 1.28 seconds
Started Jun 26 05:15:45 PM PDT 24
Finished Jun 26 05:15:48 PM PDT 24
Peak memory 206176 kb
Host smart-be0d1229-f300-45e0-8234-08fd05af24a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35419
14785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.3541914785
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.4207238411
Short name T1253
Test name
Test status
Simulation time 136238768 ps
CPU time 0.73 seconds
Started Jun 26 05:15:45 PM PDT 24
Finished Jun 26 05:15:48 PM PDT 24
Peak memory 206116 kb
Host smart-f14019eb-ed46-40b7-b755-e9a4bf715cf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42072
38411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.4207238411
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.1020567579
Short name T1675
Test name
Test status
Simulation time 42095594 ps
CPU time 0.65 seconds
Started Jun 26 05:15:44 PM PDT 24
Finished Jun 26 05:15:46 PM PDT 24
Peak memory 206184 kb
Host smart-4a119346-af32-4a0e-a773-f6b61331f256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10205
67579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.1020567579
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.2777158765
Short name T1719
Test name
Test status
Simulation time 879265086 ps
CPU time 2 seconds
Started Jun 26 05:15:48 PM PDT 24
Finished Jun 26 05:15:52 PM PDT 24
Peak memory 206444 kb
Host smart-7a566eaf-0d56-4ab1-a78c-51937c27d2c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27771
58765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.2777158765
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.544724361
Short name T1167
Test name
Test status
Simulation time 213790303 ps
CPU time 1.48 seconds
Started Jun 26 05:15:43 PM PDT 24
Finished Jun 26 05:15:47 PM PDT 24
Peak memory 206652 kb
Host smart-a99e802a-ae48-4ee3-ba87-e5a736909047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54472
4361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.544724361
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.1324905297
Short name T770
Test name
Test status
Simulation time 232705025 ps
CPU time 0.94 seconds
Started Jun 26 05:15:59 PM PDT 24
Finished Jun 26 05:16:04 PM PDT 24
Peak memory 206224 kb
Host smart-a991a263-7d7d-4cac-bac2-99c2628f6c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13249
05297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.1324905297
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.4113916349
Short name T2429
Test name
Test status
Simulation time 140963274 ps
CPU time 0.81 seconds
Started Jun 26 05:15:58 PM PDT 24
Finished Jun 26 05:16:03 PM PDT 24
Peak memory 206224 kb
Host smart-2460e682-f7f0-4708-b111-31525a96f2c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41139
16349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.4113916349
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.1626627463
Short name T1639
Test name
Test status
Simulation time 208044594 ps
CPU time 0.88 seconds
Started Jun 26 05:15:45 PM PDT 24
Finished Jun 26 05:15:48 PM PDT 24
Peak memory 206232 kb
Host smart-28bfab19-f317-4ebf-8e39-be0ef6eb68a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16266
27463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.1626627463
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.3192372347
Short name T676
Test name
Test status
Simulation time 207454536 ps
CPU time 0.83 seconds
Started Jun 26 05:15:44 PM PDT 24
Finished Jun 26 05:15:47 PM PDT 24
Peak memory 206184 kb
Host smart-b27ea20c-ab95-4711-ac84-e5ddcf37a633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31923
72347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.3192372347
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.3317459136
Short name T723
Test name
Test status
Simulation time 23295567403 ps
CPU time 22.87 seconds
Started Jun 26 05:15:45 PM PDT 24
Finished Jun 26 05:16:10 PM PDT 24
Peak memory 206240 kb
Host smart-a0325008-c67b-4c10-ab6e-f35895e784b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33174
59136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.3317459136
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.3466489575
Short name T1541
Test name
Test status
Simulation time 3343162025 ps
CPU time 4.6 seconds
Started Jun 26 05:15:45 PM PDT 24
Finished Jun 26 05:15:52 PM PDT 24
Peak memory 206172 kb
Host smart-13b915e8-b866-45eb-8854-622dcd021a3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34664
89575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.3466489575
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.3021108831
Short name T441
Test name
Test status
Simulation time 6058392712 ps
CPU time 41.73 seconds
Started Jun 26 05:15:47 PM PDT 24
Finished Jun 26 05:16:30 PM PDT 24
Peak memory 206516 kb
Host smart-3be28cb1-102d-423e-98c7-d5000824a159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30211
08831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.3021108831
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.995744212
Short name T1060
Test name
Test status
Simulation time 5739210461 ps
CPU time 176.3 seconds
Started Jun 26 05:15:43 PM PDT 24
Finished Jun 26 05:18:41 PM PDT 24
Peak memory 206456 kb
Host smart-a057b93e-32db-40a7-a521-74b8e5af2c85
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=995744212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.995744212
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.1038823987
Short name T937
Test name
Test status
Simulation time 242433202 ps
CPU time 0.89 seconds
Started Jun 26 05:15:59 PM PDT 24
Finished Jun 26 05:16:03 PM PDT 24
Peak memory 206240 kb
Host smart-211f222f-0148-44e9-a134-6e63e03e9139
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1038823987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.1038823987
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.782381818
Short name T483
Test name
Test status
Simulation time 184123378 ps
CPU time 0.81 seconds
Started Jun 26 05:15:48 PM PDT 24
Finished Jun 26 05:15:50 PM PDT 24
Peak memory 206204 kb
Host smart-1a3e505d-9161-4b38-839e-c622afd279dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78238
1818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.782381818
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.2438990122
Short name T1887
Test name
Test status
Simulation time 3912130108 ps
CPU time 27.71 seconds
Started Jun 26 05:15:45 PM PDT 24
Finished Jun 26 05:16:14 PM PDT 24
Peak memory 206464 kb
Host smart-fba05e05-44a7-4ed2-bc1b-d1bb8cc79cfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24389
90122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.2438990122
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.1558405015
Short name T426
Test name
Test status
Simulation time 2778123402 ps
CPU time 76.26 seconds
Started Jun 26 05:15:44 PM PDT 24
Finished Jun 26 05:17:02 PM PDT 24
Peak memory 206404 kb
Host smart-03f67989-6aa8-47b9-8d33-daac58e4dc86
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1558405015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.1558405015
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.4020839346
Short name T2581
Test name
Test status
Simulation time 146073953 ps
CPU time 0.78 seconds
Started Jun 26 05:15:53 PM PDT 24
Finished Jun 26 05:15:55 PM PDT 24
Peak memory 206208 kb
Host smart-e12ef792-cfc6-4cb1-9f14-f0c553767929
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4020839346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.4020839346
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.2989689562
Short name T1464
Test name
Test status
Simulation time 146304392 ps
CPU time 0.76 seconds
Started Jun 26 05:15:45 PM PDT 24
Finished Jun 26 05:15:48 PM PDT 24
Peak memory 206124 kb
Host smart-f9673501-3722-46fa-bca7-ac2e512376f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29896
89562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.2989689562
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.240491989
Short name T118
Test name
Test status
Simulation time 240410163 ps
CPU time 0.93 seconds
Started Jun 26 05:15:46 PM PDT 24
Finished Jun 26 05:15:49 PM PDT 24
Peak memory 206232 kb
Host smart-a099852f-ce71-4f31-8290-8e3714a81280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24049
1989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.240491989
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.2215890209
Short name T397
Test name
Test status
Simulation time 156381874 ps
CPU time 0.76 seconds
Started Jun 26 05:15:47 PM PDT 24
Finished Jun 26 05:15:49 PM PDT 24
Peak memory 206184 kb
Host smart-718ee57a-6ae5-4ad0-bd7c-943bdd1b4cce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22158
90209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.2215890209
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.4159047686
Short name T330
Test name
Test status
Simulation time 171149693 ps
CPU time 0.79 seconds
Started Jun 26 05:15:46 PM PDT 24
Finished Jun 26 05:15:49 PM PDT 24
Peak memory 206228 kb
Host smart-5ae582fb-0c7c-4906-ab92-a328b3a2c6c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41590
47686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.4159047686
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.2827555627
Short name T102
Test name
Test status
Simulation time 174096382 ps
CPU time 0.84 seconds
Started Jun 26 05:15:48 PM PDT 24
Finished Jun 26 05:15:50 PM PDT 24
Peak memory 206176 kb
Host smart-420ec0de-f1c8-420f-a354-4fae7df78985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28275
55627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.2827555627
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.3023980937
Short name T1703
Test name
Test status
Simulation time 148361131 ps
CPU time 0.78 seconds
Started Jun 26 05:15:54 PM PDT 24
Finished Jun 26 05:15:56 PM PDT 24
Peak memory 206144 kb
Host smart-cb4fbb6e-f16a-4bad-a8c2-6745acf60087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30239
80937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.3023980937
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.216560224
Short name T940
Test name
Test status
Simulation time 274336766 ps
CPU time 0.94 seconds
Started Jun 26 05:15:45 PM PDT 24
Finished Jun 26 05:15:48 PM PDT 24
Peak memory 206196 kb
Host smart-41c2258e-be2d-45e8-8229-59ff62ca5a34
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=216560224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.216560224
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.1731122427
Short name T887
Test name
Test status
Simulation time 171868629 ps
CPU time 0.8 seconds
Started Jun 26 05:15:46 PM PDT 24
Finished Jun 26 05:15:49 PM PDT 24
Peak memory 206176 kb
Host smart-fecf6be1-31bd-467a-839d-3402428a2282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17311
22427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.1731122427
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.2945429856
Short name T1204
Test name
Test status
Simulation time 40244739 ps
CPU time 0.65 seconds
Started Jun 26 05:15:50 PM PDT 24
Finished Jun 26 05:15:52 PM PDT 24
Peak memory 206192 kb
Host smart-b61abbaf-ac11-4cef-8c23-e18733807f04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29454
29856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.2945429856
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.40790266
Short name T824
Test name
Test status
Simulation time 21554601039 ps
CPU time 48.49 seconds
Started Jun 26 05:15:52 PM PDT 24
Finished Jun 26 05:16:41 PM PDT 24
Peak memory 206584 kb
Host smart-7985c6a7-e54c-47a0-9172-daa2fa905b73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40790
266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.40790266
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.2840368633
Short name T307
Test name
Test status
Simulation time 187865906 ps
CPU time 0.85 seconds
Started Jun 26 05:15:52 PM PDT 24
Finished Jun 26 05:15:54 PM PDT 24
Peak memory 206440 kb
Host smart-ffb3e890-aadd-48d9-b63a-f606b469fc92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28403
68633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.2840368633
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.722865278
Short name T1527
Test name
Test status
Simulation time 184486259 ps
CPU time 0.85 seconds
Started Jun 26 05:15:55 PM PDT 24
Finished Jun 26 05:15:57 PM PDT 24
Peak memory 206188 kb
Host smart-8e07460e-464b-4d6d-abec-ff1854e6463e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72286
5278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.722865278
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.2660513274
Short name T2402
Test name
Test status
Simulation time 239544557 ps
CPU time 0.9 seconds
Started Jun 26 05:15:51 PM PDT 24
Finished Jun 26 05:15:53 PM PDT 24
Peak memory 206148 kb
Host smart-1ee59688-7bd8-49ef-8262-e76e13e3c19a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26605
13274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.2660513274
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.4141001180
Short name T386
Test name
Test status
Simulation time 157296373 ps
CPU time 0.83 seconds
Started Jun 26 05:15:55 PM PDT 24
Finished Jun 26 05:15:57 PM PDT 24
Peak memory 205948 kb
Host smart-f670c7fc-c5fa-441d-aca1-5f288dac448e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41410
01180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.4141001180
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.1111681415
Short name T2532
Test name
Test status
Simulation time 143075822 ps
CPU time 0.74 seconds
Started Jun 26 05:15:50 PM PDT 24
Finished Jun 26 05:15:51 PM PDT 24
Peak memory 206116 kb
Host smart-96ed54f5-f7cd-4bac-8bdc-deeb99ab4dd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11116
81415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.1111681415
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.3421960278
Short name T1147
Test name
Test status
Simulation time 169314087 ps
CPU time 0.77 seconds
Started Jun 26 05:15:53 PM PDT 24
Finished Jun 26 05:15:55 PM PDT 24
Peak memory 206116 kb
Host smart-c4cb090f-0854-4bd0-b0c6-b063d85a4663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34219
60278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.3421960278
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.775624199
Short name T448
Test name
Test status
Simulation time 156731845 ps
CPU time 0.8 seconds
Started Jun 26 05:15:55 PM PDT 24
Finished Jun 26 05:15:57 PM PDT 24
Peak memory 205960 kb
Host smart-e55a4277-c55a-433b-80d4-ab8885938346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77562
4199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.775624199
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.4265363237
Short name T1880
Test name
Test status
Simulation time 243364294 ps
CPU time 0.95 seconds
Started Jun 26 05:15:53 PM PDT 24
Finished Jun 26 05:15:55 PM PDT 24
Peak memory 206236 kb
Host smart-1f5b98b8-40e1-42b7-9eed-86f3b5eab685
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42653
63237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.4265363237
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.905310445
Short name T1316
Test name
Test status
Simulation time 6759799033 ps
CPU time 193.82 seconds
Started Jun 26 05:15:55 PM PDT 24
Finished Jun 26 05:19:10 PM PDT 24
Peak memory 206508 kb
Host smart-750e8444-b092-450c-8c56-245e616b8d04
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=905310445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.905310445
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.2295755353
Short name T503
Test name
Test status
Simulation time 209362730 ps
CPU time 0.87 seconds
Started Jun 26 05:15:59 PM PDT 24
Finished Jun 26 05:16:03 PM PDT 24
Peak memory 206212 kb
Host smart-34fba66d-9848-4a95-8a81-21a0e1840002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22957
55353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.2295755353
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.1229030486
Short name T1731
Test name
Test status
Simulation time 166574651 ps
CPU time 0.77 seconds
Started Jun 26 05:15:54 PM PDT 24
Finished Jun 26 05:15:56 PM PDT 24
Peak memory 206196 kb
Host smart-8e35595f-1959-4c6e-ab83-3b5340a626f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12290
30486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.1229030486
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.1911130492
Short name T636
Test name
Test status
Simulation time 5681595250 ps
CPU time 155.41 seconds
Started Jun 26 05:15:52 PM PDT 24
Finished Jun 26 05:18:28 PM PDT 24
Peak memory 206488 kb
Host smart-c93ac2a5-9b66-4048-91d8-1b4ab556dd67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19111
30492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.1911130492
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.1861160315
Short name T656
Test name
Test status
Simulation time 4414297309 ps
CPU time 5.12 seconds
Started Jun 26 05:15:58 PM PDT 24
Finished Jun 26 05:16:06 PM PDT 24
Peak memory 206564 kb
Host smart-62e00996-5b05-4f8f-b5d5-49dbfa27a4cc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1861160315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.1861160315
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.1421534408
Short name T1069
Test name
Test status
Simulation time 13390336953 ps
CPU time 13.1 seconds
Started Jun 26 05:15:59 PM PDT 24
Finished Jun 26 05:16:15 PM PDT 24
Peak memory 206244 kb
Host smart-627bf776-3745-48e0-a195-e66b27f4316d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1421534408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.1421534408
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.3728882014
Short name T807
Test name
Test status
Simulation time 23345859590 ps
CPU time 24.4 seconds
Started Jun 26 05:15:59 PM PDT 24
Finished Jun 26 05:16:27 PM PDT 24
Peak memory 206300 kb
Host smart-b19cbe86-8bcb-40d1-abf5-34a5d7eabb0e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3728882014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.3728882014
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.1137510625
Short name T1335
Test name
Test status
Simulation time 159647302 ps
CPU time 0.79 seconds
Started Jun 26 05:15:57 PM PDT 24
Finished Jun 26 05:16:00 PM PDT 24
Peak memory 206208 kb
Host smart-5c9e5113-7c12-4f03-a11b-7042a083d1b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11375
10625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.1137510625
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.682057015
Short name T1445
Test name
Test status
Simulation time 169406073 ps
CPU time 0.8 seconds
Started Jun 26 05:16:00 PM PDT 24
Finished Jun 26 05:16:05 PM PDT 24
Peak memory 206172 kb
Host smart-f63eeb6e-3f94-4f97-876e-168c5cbf1b3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68205
7015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.682057015
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.2324906125
Short name T730
Test name
Test status
Simulation time 306436532 ps
CPU time 1.08 seconds
Started Jun 26 05:16:00 PM PDT 24
Finished Jun 26 05:16:05 PM PDT 24
Peak memory 206176 kb
Host smart-1ad41875-16e1-4aa9-97e0-3e38447cd3c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23249
06125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.2324906125
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.3871754578
Short name T1138
Test name
Test status
Simulation time 1277106937 ps
CPU time 2.87 seconds
Started Jun 26 05:16:03 PM PDT 24
Finished Jun 26 05:16:09 PM PDT 24
Peak memory 206280 kb
Host smart-7eff4a91-1237-48f4-83c3-ac9dbcd27307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38717
54578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.3871754578
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.3374311397
Short name T1575
Test name
Test status
Simulation time 17000571415 ps
CPU time 33.63 seconds
Started Jun 26 05:16:00 PM PDT 24
Finished Jun 26 05:16:37 PM PDT 24
Peak memory 206484 kb
Host smart-cbae5a5a-4a6f-48f7-b3b7-910390f2a509
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33743
11397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.3374311397
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.1908890430
Short name T712
Test name
Test status
Simulation time 443422927 ps
CPU time 1.52 seconds
Started Jun 26 05:15:58 PM PDT 24
Finished Jun 26 05:16:03 PM PDT 24
Peak memory 206200 kb
Host smart-87514ea3-3899-400b-a5d4-ba96602157d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19088
90430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.1908890430
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.2651047654
Short name T1063
Test name
Test status
Simulation time 144444184 ps
CPU time 0.8 seconds
Started Jun 26 05:15:59 PM PDT 24
Finished Jun 26 05:16:03 PM PDT 24
Peak memory 206116 kb
Host smart-af067747-5090-4094-a52c-bd19fb8013f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26510
47654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.2651047654
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.3143255545
Short name T2336
Test name
Test status
Simulation time 83353496 ps
CPU time 0.68 seconds
Started Jun 26 05:15:57 PM PDT 24
Finished Jun 26 05:15:59 PM PDT 24
Peak memory 206088 kb
Host smart-2bbf3eb6-f586-4b9a-a9c8-591b0e1b8dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31432
55545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.3143255545
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.517721239
Short name T1428
Test name
Test status
Simulation time 872565495 ps
CPU time 2.04 seconds
Started Jun 26 05:15:57 PM PDT 24
Finished Jun 26 05:16:01 PM PDT 24
Peak memory 206336 kb
Host smart-9f389a11-9f2e-4962-9cea-d978c589526a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51772
1239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.517721239
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.549537366
Short name T2288
Test name
Test status
Simulation time 175873628 ps
CPU time 1.6 seconds
Started Jun 26 05:16:01 PM PDT 24
Finished Jun 26 05:16:06 PM PDT 24
Peak memory 206384 kb
Host smart-8073f8bd-f29d-4f88-91b7-65b4a49822f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54953
7366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.549537366
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.1016302206
Short name T440
Test name
Test status
Simulation time 250261087 ps
CPU time 0.9 seconds
Started Jun 26 05:16:13 PM PDT 24
Finished Jun 26 05:16:16 PM PDT 24
Peak memory 206128 kb
Host smart-def4d2e0-c2ca-4e36-b0ee-e0fe66285512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10163
02206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.1016302206
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.467660975
Short name T1643
Test name
Test status
Simulation time 161924610 ps
CPU time 0.79 seconds
Started Jun 26 05:16:16 PM PDT 24
Finished Jun 26 05:16:19 PM PDT 24
Peak memory 206024 kb
Host smart-fcedaa51-4037-4a7e-b65a-4760aea89e03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46766
0975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.467660975
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.3414146958
Short name T1683
Test name
Test status
Simulation time 255092139 ps
CPU time 0.88 seconds
Started Jun 26 05:16:03 PM PDT 24
Finished Jun 26 05:16:07 PM PDT 24
Peak memory 206028 kb
Host smart-b494df6d-baf1-44a9-9bcd-6ae0670af011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34141
46958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.3414146958
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.739697570
Short name T1109
Test name
Test status
Simulation time 173404391 ps
CPU time 0.86 seconds
Started Jun 26 05:15:59 PM PDT 24
Finished Jun 26 05:16:03 PM PDT 24
Peak memory 206392 kb
Host smart-06060375-aa2c-4b84-8e65-3bce52cd740a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73969
7570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.739697570
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.3426327892
Short name T2067
Test name
Test status
Simulation time 23277536445 ps
CPU time 29.81 seconds
Started Jun 26 05:15:57 PM PDT 24
Finished Jun 26 05:16:29 PM PDT 24
Peak memory 206232 kb
Host smart-96663dd9-86f7-42cb-aca0-f4621262865d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34263
27892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.3426327892
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.211838295
Short name T831
Test name
Test status
Simulation time 3318655011 ps
CPU time 3.54 seconds
Started Jun 26 05:15:57 PM PDT 24
Finished Jun 26 05:16:03 PM PDT 24
Peak memory 206268 kb
Host smart-766f5e7c-ff56-45f4-a164-e3237c930f79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21183
8295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.211838295
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.1924354215
Short name T941
Test name
Test status
Simulation time 6369246334 ps
CPU time 61.3 seconds
Started Jun 26 05:15:59 PM PDT 24
Finished Jun 26 05:17:04 PM PDT 24
Peak memory 206540 kb
Host smart-3d71fb92-4749-4a96-92b3-183ff637f64a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19243
54215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.1924354215
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.1753858762
Short name T2438
Test name
Test status
Simulation time 4938119750 ps
CPU time 46.67 seconds
Started Jun 26 05:16:13 PM PDT 24
Finished Jun 26 05:17:02 PM PDT 24
Peak memory 206168 kb
Host smart-439c21cf-8c48-4401-a8a5-dae91acb52c8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1753858762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.1753858762
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.649588237
Short name T1595
Test name
Test status
Simulation time 238856055 ps
CPU time 0.85 seconds
Started Jun 26 05:16:11 PM PDT 24
Finished Jun 26 05:16:12 PM PDT 24
Peak memory 206136 kb
Host smart-3b04f92e-c149-45c0-aeae-58c46738142f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=649588237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.649588237
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.3967430530
Short name T564
Test name
Test status
Simulation time 204266753 ps
CPU time 0.86 seconds
Started Jun 26 05:15:59 PM PDT 24
Finished Jun 26 05:16:03 PM PDT 24
Peak memory 206180 kb
Host smart-04c7df85-2c79-4dc8-b80f-6190ebbdbf4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39674
30530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.3967430530
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.2924552309
Short name T163
Test name
Test status
Simulation time 5552550171 ps
CPU time 153.81 seconds
Started Jun 26 05:16:07 PM PDT 24
Finished Jun 26 05:18:43 PM PDT 24
Peak memory 206556 kb
Host smart-6d75b3aa-9104-4e10-95f5-9e3d8b7ec558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29245
52309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.2924552309
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.378394558
Short name T2043
Test name
Test status
Simulation time 5348866446 ps
CPU time 43.29 seconds
Started Jun 26 05:16:02 PM PDT 24
Finished Jun 26 05:16:49 PM PDT 24
Peak memory 206580 kb
Host smart-bfcdaaff-c29a-400b-8bca-5ce2f8fcd653
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=378394558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.378394558
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.2019854792
Short name T154
Test name
Test status
Simulation time 217141796 ps
CPU time 0.84 seconds
Started Jun 26 05:16:15 PM PDT 24
Finished Jun 26 05:16:18 PM PDT 24
Peak memory 206236 kb
Host smart-ae0877b4-63cc-4c11-819f-5e9fda200ec9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2019854792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.2019854792
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.3666562523
Short name T1933
Test name
Test status
Simulation time 151480257 ps
CPU time 0.76 seconds
Started Jun 26 05:16:03 PM PDT 24
Finished Jun 26 05:16:07 PM PDT 24
Peak memory 206028 kb
Host smart-aac5380e-e92c-4ff9-81d3-7eeeee5a8140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36665
62523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.3666562523
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.472643865
Short name T945
Test name
Test status
Simulation time 189308782 ps
CPU time 0.84 seconds
Started Jun 26 05:16:05 PM PDT 24
Finished Jun 26 05:16:08 PM PDT 24
Peak memory 206140 kb
Host smart-0ac28866-7fb5-4517-95ee-f922a72ff9af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47264
3865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.472643865
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.571263646
Short name T2344
Test name
Test status
Simulation time 175962392 ps
CPU time 0.82 seconds
Started Jun 26 05:16:13 PM PDT 24
Finished Jun 26 05:16:16 PM PDT 24
Peak memory 206024 kb
Host smart-749ab708-64e9-4e50-9ba0-9c92ca4f6bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57126
3646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.571263646
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.489728943
Short name T1996
Test name
Test status
Simulation time 210179644 ps
CPU time 0.84 seconds
Started Jun 26 05:16:07 PM PDT 24
Finished Jun 26 05:16:10 PM PDT 24
Peak memory 206224 kb
Host smart-7282e524-1229-4ab9-a9d6-c17ed2ed4e44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48972
8943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.489728943
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.3169260453
Short name T722
Test name
Test status
Simulation time 161215357 ps
CPU time 0.79 seconds
Started Jun 26 05:16:12 PM PDT 24
Finished Jun 26 05:16:14 PM PDT 24
Peak memory 206184 kb
Host smart-5e896a08-ab96-4614-96ab-149a87070aff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31692
60453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.3169260453
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.4163065412
Short name T2455
Test name
Test status
Simulation time 200518288 ps
CPU time 0.85 seconds
Started Jun 26 05:16:04 PM PDT 24
Finished Jun 26 05:16:08 PM PDT 24
Peak memory 206196 kb
Host smart-da7f2062-7407-4255-915d-9d04524d1c56
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4163065412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.4163065412
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.802147019
Short name T21
Test name
Test status
Simulation time 156725407 ps
CPU time 0.74 seconds
Started Jun 26 05:16:05 PM PDT 24
Finished Jun 26 05:16:08 PM PDT 24
Peak memory 206200 kb
Host smart-358d147c-3158-481a-918e-f3a970033098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80214
7019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.802147019
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.3577261008
Short name T1470
Test name
Test status
Simulation time 102065731 ps
CPU time 0.72 seconds
Started Jun 26 05:16:11 PM PDT 24
Finished Jun 26 05:16:12 PM PDT 24
Peak memory 206172 kb
Host smart-4176505b-f9be-4632-b1cf-c57b0bac0a82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35772
61008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.3577261008
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.1341749779
Short name T2284
Test name
Test status
Simulation time 8669031170 ps
CPU time 18.44 seconds
Started Jun 26 05:16:13 PM PDT 24
Finished Jun 26 05:16:34 PM PDT 24
Peak memory 206136 kb
Host smart-f393a0c7-2e0c-4fa6-b8a4-fca2e1bd8df6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13417
49779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.1341749779
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.853328474
Short name T1205
Test name
Test status
Simulation time 150904649 ps
CPU time 0.81 seconds
Started Jun 26 05:16:06 PM PDT 24
Finished Jun 26 05:16:09 PM PDT 24
Peak memory 206200 kb
Host smart-d398d7be-4d34-4299-ad2b-d11d6e8ac0d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85332
8474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.853328474
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.837560537
Short name T1743
Test name
Test status
Simulation time 231301111 ps
CPU time 0.92 seconds
Started Jun 26 05:16:04 PM PDT 24
Finished Jun 26 05:16:08 PM PDT 24
Peak memory 206132 kb
Host smart-6de06081-f428-435d-8b4b-58233408cc56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83756
0537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.837560537
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.674326622
Short name T219
Test name
Test status
Simulation time 235372822 ps
CPU time 0.97 seconds
Started Jun 26 05:16:15 PM PDT 24
Finished Jun 26 05:16:18 PM PDT 24
Peak memory 206232 kb
Host smart-d480646c-16da-4920-98c4-9e7489973e81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67432
6622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.674326622
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.2230524047
Short name T693
Test name
Test status
Simulation time 188526785 ps
CPU time 0.89 seconds
Started Jun 26 05:16:04 PM PDT 24
Finished Jun 26 05:16:07 PM PDT 24
Peak memory 206212 kb
Host smart-3037e235-fad3-45de-b4d1-5e861a196181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22305
24047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.2230524047
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.2013030222
Short name T871
Test name
Test status
Simulation time 146203854 ps
CPU time 0.76 seconds
Started Jun 26 05:16:04 PM PDT 24
Finished Jun 26 05:16:08 PM PDT 24
Peak memory 206100 kb
Host smart-99f34f3c-dd53-4bbe-bdd4-2b895deaca76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20130
30222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.2013030222
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.1654298304
Short name T2497
Test name
Test status
Simulation time 148746669 ps
CPU time 0.75 seconds
Started Jun 26 05:16:15 PM PDT 24
Finished Jun 26 05:16:18 PM PDT 24
Peak memory 206212 kb
Host smart-ece58c55-8223-4ee3-aa47-95286a0fac1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16542
98304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.1654298304
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.580593065
Short name T2583
Test name
Test status
Simulation time 180198195 ps
CPU time 0.85 seconds
Started Jun 26 05:16:10 PM PDT 24
Finished Jun 26 05:16:12 PM PDT 24
Peak memory 206396 kb
Host smart-3be55752-23a4-43f8-93f5-3cfdc7cb8462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58059
3065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.580593065
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.579136191
Short name T256
Test name
Test status
Simulation time 238612856 ps
CPU time 0.96 seconds
Started Jun 26 05:16:06 PM PDT 24
Finished Jun 26 05:16:10 PM PDT 24
Peak memory 206224 kb
Host smart-ec6dc3c2-264d-4d76-8e30-b0cc72a64432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57913
6191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.579136191
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.1860839055
Short name T1407
Test name
Test status
Simulation time 4675547892 ps
CPU time 33.2 seconds
Started Jun 26 05:16:03 PM PDT 24
Finished Jun 26 05:16:39 PM PDT 24
Peak memory 206572 kb
Host smart-bffea554-4c3f-4123-803f-86a8705ced75
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1860839055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.1860839055
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.332316516
Short name T1763
Test name
Test status
Simulation time 180754606 ps
CPU time 0.81 seconds
Started Jun 26 05:16:12 PM PDT 24
Finished Jun 26 05:16:15 PM PDT 24
Peak memory 206208 kb
Host smart-c51d9436-1dd3-416e-b037-b79c3cfcd4b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33231
6516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.332316516
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.2410444800
Short name T337
Test name
Test status
Simulation time 183369336 ps
CPU time 0.79 seconds
Started Jun 26 05:16:05 PM PDT 24
Finished Jun 26 05:16:08 PM PDT 24
Peak memory 206120 kb
Host smart-ee2d037f-03fd-4ec3-98ce-1c8c3e6cfcbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24104
44800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.2410444800
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.803720494
Short name T1347
Test name
Test status
Simulation time 6046184885 ps
CPU time 61.71 seconds
Started Jun 26 05:16:07 PM PDT 24
Finished Jun 26 05:17:11 PM PDT 24
Peak memory 206528 kb
Host smart-db49f6eb-25d2-48dc-9bb4-4adcd52f1bd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80372
0494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.803720494
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.2534243257
Short name T1299
Test name
Test status
Simulation time 4380099108 ps
CPU time 5.28 seconds
Started Jun 26 05:16:11 PM PDT 24
Finished Jun 26 05:16:18 PM PDT 24
Peak memory 206356 kb
Host smart-828a501c-2833-48bd-b174-bb8c823fae64
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2534243257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.2534243257
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.3635850226
Short name T598
Test name
Test status
Simulation time 13402444974 ps
CPU time 16.58 seconds
Started Jun 26 05:16:16 PM PDT 24
Finished Jun 26 05:16:34 PM PDT 24
Peak memory 206168 kb
Host smart-7efaffc6-8b51-44e6-bc38-706501334a55
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3635850226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.3635850226
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.1540496426
Short name T1892
Test name
Test status
Simulation time 23379668901 ps
CPU time 23.08 seconds
Started Jun 26 05:16:12 PM PDT 24
Finished Jun 26 05:16:37 PM PDT 24
Peak memory 206556 kb
Host smart-720894fc-a0ff-4868-b3e3-8a4ea271b8c9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1540496426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.1540496426
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.1924038466
Short name T1944
Test name
Test status
Simulation time 151349674 ps
CPU time 0.8 seconds
Started Jun 26 05:16:13 PM PDT 24
Finished Jun 26 05:16:16 PM PDT 24
Peak memory 206200 kb
Host smart-d2aeda41-628f-4ff0-b1d8-3737900e8d0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19240
38466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.1924038466
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.3319710933
Short name T1540
Test name
Test status
Simulation time 149320020 ps
CPU time 0.72 seconds
Started Jun 26 05:16:12 PM PDT 24
Finished Jun 26 05:16:15 PM PDT 24
Peak memory 206196 kb
Host smart-d66994b7-9983-4f64-aa5c-529a8da118d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33197
10933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.3319710933
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.351805183
Short name T112
Test name
Test status
Simulation time 511608628 ps
CPU time 1.54 seconds
Started Jun 26 05:16:11 PM PDT 24
Finished Jun 26 05:16:14 PM PDT 24
Peak memory 206416 kb
Host smart-5b449f90-c49d-4c1e-a15f-a82ba42e0afa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35180
5183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.351805183
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.1890855781
Short name T1040
Test name
Test status
Simulation time 847043811 ps
CPU time 2.06 seconds
Started Jun 26 05:16:13 PM PDT 24
Finished Jun 26 05:16:17 PM PDT 24
Peak memory 206428 kb
Host smart-692b08bf-366f-4af3-85b7-a89156160880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18908
55781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.1890855781
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.1902084
Short name T2098
Test name
Test status
Simulation time 10361019004 ps
CPU time 19.59 seconds
Started Jun 26 05:16:12 PM PDT 24
Finished Jun 26 05:16:33 PM PDT 24
Peak memory 206496 kb
Host smart-dcc5ab77-e85b-4d50-add9-a32587e1eb86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19020
84 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.1902084
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.1002657261
Short name T1512
Test name
Test status
Simulation time 450625728 ps
CPU time 1.34 seconds
Started Jun 26 05:16:12 PM PDT 24
Finished Jun 26 05:16:14 PM PDT 24
Peak memory 206176 kb
Host smart-af221e19-b093-45a1-a787-67c08efc6321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10026
57261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.1002657261
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.3152906572
Short name T1918
Test name
Test status
Simulation time 136046659 ps
CPU time 0.75 seconds
Started Jun 26 05:16:13 PM PDT 24
Finished Jun 26 05:16:16 PM PDT 24
Peak memory 206192 kb
Host smart-137cbc61-361a-4aa1-97c6-491b4342f679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31529
06572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.3152906572
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.4286499737
Short name T1165
Test name
Test status
Simulation time 45348085 ps
CPU time 0.66 seconds
Started Jun 26 05:16:13 PM PDT 24
Finished Jun 26 05:16:16 PM PDT 24
Peak memory 206128 kb
Host smart-9044d391-79fc-4d24-bed1-0b3def4db0b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42864
99737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.4286499737
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.860916879
Short name T1760
Test name
Test status
Simulation time 879386435 ps
CPU time 1.96 seconds
Started Jun 26 05:16:13 PM PDT 24
Finished Jun 26 05:16:18 PM PDT 24
Peak memory 206432 kb
Host smart-de8e5e09-9256-4327-b1f6-15e71a0ca414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86091
6879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.860916879
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.960783822
Short name T1102
Test name
Test status
Simulation time 290770710 ps
CPU time 2.05 seconds
Started Jun 26 05:16:13 PM PDT 24
Finished Jun 26 05:16:17 PM PDT 24
Peak memory 206396 kb
Host smart-e3c177b3-c91f-4c92-bf68-be5610ef5363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96078
3822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.960783822
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.1062984867
Short name T1696
Test name
Test status
Simulation time 186983938 ps
CPU time 0.84 seconds
Started Jun 26 05:16:18 PM PDT 24
Finished Jun 26 05:16:21 PM PDT 24
Peak memory 206148 kb
Host smart-bb3a3740-4417-481e-986e-b8b23f255e07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10629
84867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.1062984867
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.3754648775
Short name T1532
Test name
Test status
Simulation time 137942617 ps
CPU time 0.84 seconds
Started Jun 26 05:16:19 PM PDT 24
Finished Jun 26 05:16:22 PM PDT 24
Peak memory 206136 kb
Host smart-b13dd68f-adfa-4c48-a85c-75d8580d461f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37546
48775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.3754648775
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.3343103349
Short name T342
Test name
Test status
Simulation time 220203796 ps
CPU time 0.88 seconds
Started Jun 26 05:16:11 PM PDT 24
Finished Jun 26 05:16:13 PM PDT 24
Peak memory 206212 kb
Host smart-ebf8c85d-847e-43d3-8036-483d023edabb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33431
03349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.3343103349
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_invalid_sync.2722742869
Short name T1835
Test name
Test status
Simulation time 5536585141 ps
CPU time 55.8 seconds
Started Jun 26 05:16:12 PM PDT 24
Finished Jun 26 05:17:09 PM PDT 24
Peak memory 206556 kb
Host smart-6e567563-0463-49da-b0ac-543e2493748f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2722742869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.2722742869
Directory /workspace/18.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.3757211106
Short name T2112
Test name
Test status
Simulation time 209915112 ps
CPU time 0.86 seconds
Started Jun 26 05:16:12 PM PDT 24
Finished Jun 26 05:16:15 PM PDT 24
Peak memory 206204 kb
Host smart-2df7c648-c298-4952-ba3c-9831e132681e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37572
11106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.3757211106
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.2488095714
Short name T1837
Test name
Test status
Simulation time 23316989123 ps
CPU time 24.66 seconds
Started Jun 26 05:16:12 PM PDT 24
Finished Jun 26 05:16:39 PM PDT 24
Peak memory 206212 kb
Host smart-86af0e63-63cb-471b-8828-3f67f3f5a4b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24880
95714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.2488095714
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.1651151405
Short name T1029
Test name
Test status
Simulation time 3276515857 ps
CPU time 3.77 seconds
Started Jun 26 05:16:14 PM PDT 24
Finished Jun 26 05:16:20 PM PDT 24
Peak memory 206256 kb
Host smart-b4289e16-809d-470f-a8d3-0cb5d9478a5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16511
51405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.1651151405
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.616132682
Short name T1549
Test name
Test status
Simulation time 6542454061 ps
CPU time 45.81 seconds
Started Jun 26 05:16:17 PM PDT 24
Finished Jun 26 05:17:04 PM PDT 24
Peak memory 206468 kb
Host smart-ca7525de-f5a9-4d4e-9047-bc900f128575
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=616132682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.616132682
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.3170652885
Short name T2431
Test name
Test status
Simulation time 240392618 ps
CPU time 0.9 seconds
Started Jun 26 05:16:19 PM PDT 24
Finished Jun 26 05:16:22 PM PDT 24
Peak memory 206144 kb
Host smart-2e2c4440-6516-404f-8bf3-8e875e376356
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3170652885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.3170652885
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.3492931440
Short name T650
Test name
Test status
Simulation time 224386318 ps
CPU time 0.87 seconds
Started Jun 26 05:16:18 PM PDT 24
Finished Jun 26 05:16:21 PM PDT 24
Peak memory 206224 kb
Host smart-e9e727db-4ba0-4f85-b34a-742c3c5d5e52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34929
31440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.3492931440
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.931546426
Short name T1672
Test name
Test status
Simulation time 3731521223 ps
CPU time 102.71 seconds
Started Jun 26 05:16:17 PM PDT 24
Finished Jun 26 05:18:02 PM PDT 24
Peak memory 206476 kb
Host smart-143e2739-a38e-47bc-aec2-6056af848a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93154
6426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.931546426
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.4249620153
Short name T1757
Test name
Test status
Simulation time 3324927833 ps
CPU time 26 seconds
Started Jun 26 05:16:17 PM PDT 24
Finished Jun 26 05:16:44 PM PDT 24
Peak memory 206444 kb
Host smart-7d03518f-7793-4ec5-8c6b-bece45ef6975
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4249620153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.4249620153
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.34456016
Short name T1762
Test name
Test status
Simulation time 162959323 ps
CPU time 0.79 seconds
Started Jun 26 05:16:20 PM PDT 24
Finished Jun 26 05:16:23 PM PDT 24
Peak memory 206124 kb
Host smart-b0025e3d-cdf7-448d-a459-85e6c9509f35
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=34456016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.34456016
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.2368587242
Short name T1832
Test name
Test status
Simulation time 147650287 ps
CPU time 0.77 seconds
Started Jun 26 05:16:18 PM PDT 24
Finished Jun 26 05:16:21 PM PDT 24
Peak memory 206196 kb
Host smart-c3c792f5-f72a-4285-a521-5eb3aa084d05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23685
87242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.2368587242
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.4090581162
Short name T2277
Test name
Test status
Simulation time 206347337 ps
CPU time 0.88 seconds
Started Jun 26 05:16:19 PM PDT 24
Finished Jun 26 05:16:22 PM PDT 24
Peak memory 206176 kb
Host smart-f5c41b62-cf59-43b0-ab3f-547729bb4b66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40905
81162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.4090581162
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.2003444973
Short name T2362
Test name
Test status
Simulation time 190419298 ps
CPU time 0.82 seconds
Started Jun 26 05:16:18 PM PDT 24
Finished Jun 26 05:16:20 PM PDT 24
Peak memory 206224 kb
Host smart-509e3c90-8bb4-4a5d-87eb-7af968012974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20034
44973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.2003444973
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.3631371163
Short name T413
Test name
Test status
Simulation time 184074024 ps
CPU time 0.9 seconds
Started Jun 26 05:16:18 PM PDT 24
Finished Jun 26 05:16:20 PM PDT 24
Peak memory 206444 kb
Host smart-879809b7-e2cc-47d3-8d4e-63563beed571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36313
71163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.3631371163
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.4204586210
Short name T685
Test name
Test status
Simulation time 181850629 ps
CPU time 0.82 seconds
Started Jun 26 05:16:18 PM PDT 24
Finished Jun 26 05:16:20 PM PDT 24
Peak memory 206124 kb
Host smart-cbd75824-7df4-408d-8d07-db5f8ab78f1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42045
86210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.4204586210
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.738090842
Short name T193
Test name
Test status
Simulation time 198387311 ps
CPU time 0.83 seconds
Started Jun 26 05:16:25 PM PDT 24
Finished Jun 26 05:16:28 PM PDT 24
Peak memory 206252 kb
Host smart-5964a487-a290-46e3-9cef-ecd5bbd37aea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73809
0842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.738090842
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.174282073
Short name T822
Test name
Test status
Simulation time 290619404 ps
CPU time 1.07 seconds
Started Jun 26 05:16:18 PM PDT 24
Finished Jun 26 05:16:21 PM PDT 24
Peak memory 206232 kb
Host smart-9e1b32a4-3f61-4aa2-9d03-3d3bb62f5788
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=174282073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.174282073
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.3248890712
Short name T920
Test name
Test status
Simulation time 216687651 ps
CPU time 0.83 seconds
Started Jun 26 05:16:19 PM PDT 24
Finished Jun 26 05:16:21 PM PDT 24
Peak memory 206180 kb
Host smart-e0260a7f-3936-4a5f-b3af-6e0412516e3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32488
90712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.3248890712
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.339726118
Short name T884
Test name
Test status
Simulation time 33630933 ps
CPU time 0.64 seconds
Started Jun 26 05:16:19 PM PDT 24
Finished Jun 26 05:16:22 PM PDT 24
Peak memory 206160 kb
Host smart-0c85f970-0512-44d2-9f69-b783df553093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33972
6118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.339726118
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.2692552474
Short name T265
Test name
Test status
Simulation time 16441406995 ps
CPU time 33.38 seconds
Started Jun 26 05:16:18 PM PDT 24
Finished Jun 26 05:16:52 PM PDT 24
Peak memory 206512 kb
Host smart-893e81d0-e87d-4df5-86e5-30c1af226c45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26925
52474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.2692552474
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.3801047855
Short name T1708
Test name
Test status
Simulation time 179890897 ps
CPU time 0.82 seconds
Started Jun 26 05:16:19 PM PDT 24
Finished Jun 26 05:16:21 PM PDT 24
Peak memory 206120 kb
Host smart-5ffadd9e-364f-49bb-a972-06c5ce6c5c11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38010
47855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.3801047855
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.4234563361
Short name T2376
Test name
Test status
Simulation time 202784630 ps
CPU time 0.85 seconds
Started Jun 26 05:16:17 PM PDT 24
Finished Jun 26 05:16:19 PM PDT 24
Peak memory 206148 kb
Host smart-59da298a-142c-40f9-bf90-99a6199b05e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42345
63361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.4234563361
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.2284130621
Short name T1241
Test name
Test status
Simulation time 232997116 ps
CPU time 0.89 seconds
Started Jun 26 05:16:25 PM PDT 24
Finished Jun 26 05:16:28 PM PDT 24
Peak memory 206252 kb
Host smart-df5e0238-0e70-4222-9c3c-b09929aae21c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22841
30621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.2284130621
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.3665726867
Short name T2571
Test name
Test status
Simulation time 190200003 ps
CPU time 0.86 seconds
Started Jun 26 05:16:18 PM PDT 24
Finished Jun 26 05:16:21 PM PDT 24
Peak memory 206188 kb
Host smart-065b1309-1d32-4e92-8db4-cfc2d8c8425a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36657
26867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.3665726867
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.2090552384
Short name T1855
Test name
Test status
Simulation time 190364920 ps
CPU time 0.81 seconds
Started Jun 26 05:16:19 PM PDT 24
Finished Jun 26 05:16:21 PM PDT 24
Peak memory 206200 kb
Host smart-3549deb0-d0ed-4ef9-a201-7ef190cdc090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20905
52384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.2090552384
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.1882832311
Short name T1717
Test name
Test status
Simulation time 152052712 ps
CPU time 0.77 seconds
Started Jun 26 05:16:18 PM PDT 24
Finished Jun 26 05:16:20 PM PDT 24
Peak memory 206076 kb
Host smart-b47d61c4-e7f9-4f9e-9066-ada0fb697a38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18828
32311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.1882832311
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.2684135025
Short name T96
Test name
Test status
Simulation time 148307179 ps
CPU time 0.78 seconds
Started Jun 26 05:16:21 PM PDT 24
Finished Jun 26 05:16:24 PM PDT 24
Peak memory 206192 kb
Host smart-8b6f62b4-51fe-47ea-879d-6cd3e17d32f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26841
35025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.2684135025
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.1548759513
Short name T1025
Test name
Test status
Simulation time 221774270 ps
CPU time 0.92 seconds
Started Jun 26 05:16:19 PM PDT 24
Finished Jun 26 05:16:22 PM PDT 24
Peak memory 206212 kb
Host smart-393ae7b9-9cd1-4232-95f9-a032e8360372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15487
59513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.1548759513
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.3143528347
Short name T1854
Test name
Test status
Simulation time 4076315761 ps
CPU time 112.99 seconds
Started Jun 26 05:16:15 PM PDT 24
Finished Jun 26 05:18:10 PM PDT 24
Peak memory 206384 kb
Host smart-d651fa15-7324-46c7-9f68-3fa4ca75b6b4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3143528347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.3143528347
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.1155596275
Short name T1055
Test name
Test status
Simulation time 182449112 ps
CPU time 0.81 seconds
Started Jun 26 05:16:19 PM PDT 24
Finished Jun 26 05:16:21 PM PDT 24
Peak memory 206164 kb
Host smart-fe9da029-9aab-4203-9d5e-acfbbdd1447b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11555
96275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.1155596275
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.2209952641
Short name T1318
Test name
Test status
Simulation time 155526844 ps
CPU time 0.78 seconds
Started Jun 26 05:16:16 PM PDT 24
Finished Jun 26 05:16:18 PM PDT 24
Peak memory 206192 kb
Host smart-991386fc-ad5c-47e8-9e34-50e77f74fd03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22099
52641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.2209952641
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.2919517905
Short name T1083
Test name
Test status
Simulation time 5256845411 ps
CPU time 50.51 seconds
Started Jun 26 05:16:20 PM PDT 24
Finished Jun 26 05:17:13 PM PDT 24
Peak memory 206568 kb
Host smart-2361500d-5e91-4ae3-abc6-7a06025b9332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29195
17905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.2919517905
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.438704305
Short name T629
Test name
Test status
Simulation time 4254358890 ps
CPU time 4.67 seconds
Started Jun 26 05:16:20 PM PDT 24
Finished Jun 26 05:16:27 PM PDT 24
Peak memory 206204 kb
Host smart-36e8d1d7-6bcb-48a6-ace1-4b4873d7b0a6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=438704305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.438704305
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.2528058011
Short name T2051
Test name
Test status
Simulation time 13356907714 ps
CPU time 13.01 seconds
Started Jun 26 05:16:24 PM PDT 24
Finished Jun 26 05:16:39 PM PDT 24
Peak memory 206544 kb
Host smart-036564f7-6a0a-492e-911b-05611b40a582
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2528058011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.2528058011
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.3620328890
Short name T1231
Test name
Test status
Simulation time 23446009753 ps
CPU time 22.41 seconds
Started Jun 26 05:16:22 PM PDT 24
Finished Jun 26 05:16:46 PM PDT 24
Peak memory 206504 kb
Host smart-8e6f6349-40c4-4168-a7d3-4906211384df
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3620328890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.3620328890
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.755204772
Short name T952
Test name
Test status
Simulation time 147730606 ps
CPU time 0.87 seconds
Started Jun 26 05:16:25 PM PDT 24
Finished Jun 26 05:16:28 PM PDT 24
Peak memory 206132 kb
Host smart-3fd0f860-48e1-478f-b991-9d547f3ac00f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75520
4772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.755204772
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.2570948540
Short name T2412
Test name
Test status
Simulation time 165125035 ps
CPU time 0.78 seconds
Started Jun 26 05:16:24 PM PDT 24
Finished Jun 26 05:16:27 PM PDT 24
Peak memory 206196 kb
Host smart-e24b8991-be2b-4e64-b2a4-be17aaa71ae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25709
48540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.2570948540
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.1903374179
Short name T1180
Test name
Test status
Simulation time 337323766 ps
CPU time 1.22 seconds
Started Jun 26 05:16:23 PM PDT 24
Finished Jun 26 05:16:26 PM PDT 24
Peak memory 206204 kb
Host smart-19bc6766-6e34-471c-950b-b3b12d2b8e6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19033
74179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.1903374179
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.2738441527
Short name T843
Test name
Test status
Simulation time 1100350759 ps
CPU time 2.41 seconds
Started Jun 26 05:16:24 PM PDT 24
Finished Jun 26 05:16:28 PM PDT 24
Peak memory 206380 kb
Host smart-90dba704-2b88-4c20-80d1-42cbf214a7c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27384
41527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.2738441527
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.2078742286
Short name T1934
Test name
Test status
Simulation time 19652329021 ps
CPU time 43.59 seconds
Started Jun 26 05:16:26 PM PDT 24
Finished Jun 26 05:17:13 PM PDT 24
Peak memory 206512 kb
Host smart-39017290-b2a5-4666-85bc-d61ca4813138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20787
42286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.2078742286
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.3613124855
Short name T912
Test name
Test status
Simulation time 403300448 ps
CPU time 1.24 seconds
Started Jun 26 05:16:26 PM PDT 24
Finished Jun 26 05:16:30 PM PDT 24
Peak memory 206212 kb
Host smart-985118f5-9f5c-4ed1-ae8e-11e7a7eeea7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36131
24855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.3613124855
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.1397653330
Short name T1548
Test name
Test status
Simulation time 164394895 ps
CPU time 0.9 seconds
Started Jun 26 05:16:23 PM PDT 24
Finished Jun 26 05:16:26 PM PDT 24
Peak memory 206172 kb
Host smart-ea1296a8-8cb5-446b-86df-8621246bd884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13976
53330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.1397653330
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.2328981011
Short name T778
Test name
Test status
Simulation time 78399319 ps
CPU time 0.7 seconds
Started Jun 26 05:16:26 PM PDT 24
Finished Jun 26 05:16:29 PM PDT 24
Peak memory 206220 kb
Host smart-2d900f16-2fb2-45f8-a23e-6a4eef0d7432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23289
81011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.2328981011
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.2742077646
Short name T942
Test name
Test status
Simulation time 973041650 ps
CPU time 2.48 seconds
Started Jun 26 05:16:23 PM PDT 24
Finished Jun 26 05:16:27 PM PDT 24
Peak memory 206332 kb
Host smart-d022e62a-cfa3-4d3b-97e7-f1f76fd198f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27420
77646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.2742077646
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.2455757958
Short name T1668
Test name
Test status
Simulation time 358754591 ps
CPU time 2.42 seconds
Started Jun 26 05:16:26 PM PDT 24
Finished Jun 26 05:16:31 PM PDT 24
Peak memory 206668 kb
Host smart-95029784-d4f7-4dab-b63d-292cb3d0ae5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24557
57958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.2455757958
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.3047603621
Short name T1199
Test name
Test status
Simulation time 234407177 ps
CPU time 0.91 seconds
Started Jun 26 05:16:32 PM PDT 24
Finished Jun 26 05:16:34 PM PDT 24
Peak memory 206224 kb
Host smart-8770f345-216b-40c1-aaf0-17edb1ffbafd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30476
03621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.3047603621
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.2390432876
Short name T2369
Test name
Test status
Simulation time 171801457 ps
CPU time 0.83 seconds
Started Jun 26 05:16:32 PM PDT 24
Finished Jun 26 05:16:34 PM PDT 24
Peak memory 206140 kb
Host smart-853e231a-be7a-41ce-b73c-34bd8670571f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23904
32876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.2390432876
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.2097941930
Short name T1269
Test name
Test status
Simulation time 215926602 ps
CPU time 0.92 seconds
Started Jun 26 05:16:24 PM PDT 24
Finished Jun 26 05:16:26 PM PDT 24
Peak memory 206192 kb
Host smart-bbe8b39f-943a-4a06-8fe7-aa5741183db6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20979
41930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.2097941930
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.3019209903
Short name T2160
Test name
Test status
Simulation time 232722188 ps
CPU time 0.89 seconds
Started Jun 26 05:16:24 PM PDT 24
Finished Jun 26 05:16:26 PM PDT 24
Peak memory 206192 kb
Host smart-49164372-0205-43a3-8f1d-c9b330873a73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30192
09903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.3019209903
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.3272300416
Short name T2462
Test name
Test status
Simulation time 23297782834 ps
CPU time 22.65 seconds
Started Jun 26 05:16:24 PM PDT 24
Finished Jun 26 05:16:49 PM PDT 24
Peak memory 206228 kb
Host smart-83a73c53-7c5a-4c07-af3f-dcdf05a6f7bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32723
00416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.3272300416
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.3524121101
Short name T1688
Test name
Test status
Simulation time 3291531237 ps
CPU time 4.06 seconds
Started Jun 26 05:16:24 PM PDT 24
Finished Jun 26 05:16:31 PM PDT 24
Peak memory 206264 kb
Host smart-04549ddb-d563-4df6-beb3-c73995c369c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35241
21101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.3524121101
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.2385285373
Short name T1988
Test name
Test status
Simulation time 11023274794 ps
CPU time 83.91 seconds
Started Jun 26 05:16:30 PM PDT 24
Finished Jun 26 05:17:55 PM PDT 24
Peak memory 206540 kb
Host smart-e1468947-49d4-43f7-b97d-9480887842af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23852
85373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.2385285373
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.2782675330
Short name T612
Test name
Test status
Simulation time 3770514537 ps
CPU time 25.68 seconds
Started Jun 26 05:16:27 PM PDT 24
Finished Jun 26 05:16:56 PM PDT 24
Peak memory 205720 kb
Host smart-7b6f602e-1e99-43b8-afa1-787d57d59dc5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2782675330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.2782675330
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.3659896931
Short name T2095
Test name
Test status
Simulation time 287972920 ps
CPU time 0.97 seconds
Started Jun 26 05:16:34 PM PDT 24
Finished Jun 26 05:16:36 PM PDT 24
Peak memory 206220 kb
Host smart-4106f339-2736-494e-b511-9804cd8713c3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3659896931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.3659896931
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.823764853
Short name T1610
Test name
Test status
Simulation time 195760087 ps
CPU time 0.86 seconds
Started Jun 26 05:16:26 PM PDT 24
Finished Jun 26 05:16:29 PM PDT 24
Peak memory 206216 kb
Host smart-621e4ef2-b98c-40ff-8ea7-fd75d4df819d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82376
4853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.823764853
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.3144991979
Short name T2292
Test name
Test status
Simulation time 3569022366 ps
CPU time 25.78 seconds
Started Jun 26 05:16:27 PM PDT 24
Finished Jun 26 05:16:55 PM PDT 24
Peak memory 206460 kb
Host smart-313c3bf2-57d2-452b-8881-581a852e9fb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31449
91979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.3144991979
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.2095262610
Short name T873
Test name
Test status
Simulation time 4269152069 ps
CPU time 43.79 seconds
Started Jun 26 05:16:25 PM PDT 24
Finished Jun 26 05:17:11 PM PDT 24
Peak memory 206496 kb
Host smart-758761bb-63e8-4dbf-922a-9265f1d233cf
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2095262610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.2095262610
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.4228788866
Short name T393
Test name
Test status
Simulation time 166098771 ps
CPU time 0.85 seconds
Started Jun 26 05:16:32 PM PDT 24
Finished Jun 26 05:16:34 PM PDT 24
Peak memory 206228 kb
Host smart-43365149-1f4d-4915-8866-f747539af523
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4228788866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.4228788866
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.186871327
Short name T502
Test name
Test status
Simulation time 152701748 ps
CPU time 0.77 seconds
Started Jun 26 05:16:23 PM PDT 24
Finished Jun 26 05:16:26 PM PDT 24
Peak memory 206196 kb
Host smart-7e709a0d-7244-4ebe-a920-ac3b2881042c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18687
1327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.186871327
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.2414810962
Short name T125
Test name
Test status
Simulation time 195400313 ps
CPU time 0.85 seconds
Started Jun 26 05:16:24 PM PDT 24
Finished Jun 26 05:16:26 PM PDT 24
Peak memory 206396 kb
Host smart-cbb9c7ec-f417-49f0-be63-627944e69a77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24148
10962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.2414810962
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.1182838063
Short name T1048
Test name
Test status
Simulation time 175238375 ps
CPU time 0.78 seconds
Started Jun 26 05:16:26 PM PDT 24
Finished Jun 26 05:16:29 PM PDT 24
Peak memory 206224 kb
Host smart-a65aaec5-9c4f-4baf-99b2-e0b9ed891a6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11828
38063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.1182838063
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.935284444
Short name T62
Test name
Test status
Simulation time 151647304 ps
CPU time 0.78 seconds
Started Jun 26 05:16:25 PM PDT 24
Finished Jun 26 05:16:28 PM PDT 24
Peak memory 206232 kb
Host smart-7e4a4d58-80bc-40d1-9f66-02828da96e1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93528
4444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.935284444
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.591092554
Short name T1440
Test name
Test status
Simulation time 173139890 ps
CPU time 0.83 seconds
Started Jun 26 05:16:25 PM PDT 24
Finished Jun 26 05:16:29 PM PDT 24
Peak memory 206112 kb
Host smart-2a6925a1-8dbf-4e7f-9b48-582f9d5e89c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59109
2554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.591092554
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.4246833935
Short name T1456
Test name
Test status
Simulation time 199844053 ps
CPU time 0.82 seconds
Started Jun 26 05:16:32 PM PDT 24
Finished Jun 26 05:16:34 PM PDT 24
Peak memory 206448 kb
Host smart-407b1ad6-10b5-443b-ab0e-c88e485fdc9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42468
33935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.4246833935
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.1192033877
Short name T1265
Test name
Test status
Simulation time 247812081 ps
CPU time 0.93 seconds
Started Jun 26 05:16:29 PM PDT 24
Finished Jun 26 05:16:31 PM PDT 24
Peak memory 206248 kb
Host smart-671a5f2a-1552-416d-bbbd-ce1347a46206
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1192033877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.1192033877
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.3814438681
Short name T2482
Test name
Test status
Simulation time 142633360 ps
CPU time 0.77 seconds
Started Jun 26 05:16:27 PM PDT 24
Finished Jun 26 05:16:30 PM PDT 24
Peak memory 206168 kb
Host smart-894bedf4-39dd-4618-b446-019798f8aded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38144
38681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.3814438681
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.4264475462
Short name T2217
Test name
Test status
Simulation time 64724396 ps
CPU time 0.68 seconds
Started Jun 26 05:16:32 PM PDT 24
Finished Jun 26 05:16:34 PM PDT 24
Peak memory 206120 kb
Host smart-afb4274b-375d-4c7c-abf2-69262a78837c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42644
75462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.4264475462
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.2985366164
Short name T2322
Test name
Test status
Simulation time 6928419569 ps
CPU time 15.54 seconds
Started Jun 26 05:16:27 PM PDT 24
Finished Jun 26 05:16:45 PM PDT 24
Peak memory 206576 kb
Host smart-9a1552de-a7fa-4e04-97e8-e3e49c4cbcec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29853
66164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.2985366164
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.3212461484
Short name T1314
Test name
Test status
Simulation time 169531145 ps
CPU time 0.83 seconds
Started Jun 26 05:16:26 PM PDT 24
Finished Jun 26 05:16:30 PM PDT 24
Peak memory 206172 kb
Host smart-473cfbc7-088b-4246-b2d7-d60e53b0913a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32124
61484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.3212461484
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.2552066339
Short name T1889
Test name
Test status
Simulation time 239011905 ps
CPU time 0.9 seconds
Started Jun 26 05:16:27 PM PDT 24
Finished Jun 26 05:16:31 PM PDT 24
Peak memory 206216 kb
Host smart-3375af13-8169-48eb-a744-2d3bebc3a360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25520
66339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.2552066339
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.917658434
Short name T2306
Test name
Test status
Simulation time 208279895 ps
CPU time 0.84 seconds
Started Jun 26 05:16:33 PM PDT 24
Finished Jun 26 05:16:35 PM PDT 24
Peak memory 206144 kb
Host smart-2efc7180-11a0-45d5-acf6-f9b961a3aaa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91765
8434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.917658434
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.1456106225
Short name T798
Test name
Test status
Simulation time 181787483 ps
CPU time 0.91 seconds
Started Jun 26 05:16:27 PM PDT 24
Finished Jun 26 05:16:31 PM PDT 24
Peak memory 205188 kb
Host smart-f02486be-b3c4-417b-8eec-e1ac7547002a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14561
06225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.1456106225
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.2585339539
Short name T517
Test name
Test status
Simulation time 159167849 ps
CPU time 0.78 seconds
Started Jun 26 05:16:31 PM PDT 24
Finished Jun 26 05:16:33 PM PDT 24
Peak memory 206232 kb
Host smart-7f0ecbb8-e1be-4407-b7d6-56ca2e73d1cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25853
39539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.2585339539
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.2248671035
Short name T1325
Test name
Test status
Simulation time 155645633 ps
CPU time 0.76 seconds
Started Jun 26 05:16:32 PM PDT 24
Finished Jun 26 05:16:34 PM PDT 24
Peak memory 206116 kb
Host smart-c4039cc4-bbf0-4ff3-8793-15cccafb712a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22486
71035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.2248671035
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.4240205265
Short name T465
Test name
Test status
Simulation time 212525932 ps
CPU time 0.86 seconds
Started Jun 26 05:16:32 PM PDT 24
Finished Jun 26 05:16:34 PM PDT 24
Peak memory 206136 kb
Host smart-47ba79dc-9e29-4e58-8d39-4c982a3d5600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42402
05265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.4240205265
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.478003689
Short name T896
Test name
Test status
Simulation time 194349840 ps
CPU time 0.87 seconds
Started Jun 26 05:16:31 PM PDT 24
Finished Jun 26 05:16:33 PM PDT 24
Peak memory 206192 kb
Host smart-9131c5d0-3462-4b6c-8a6a-7af77de62f42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47800
3689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.478003689
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.2858341634
Short name T1423
Test name
Test status
Simulation time 4566632445 ps
CPU time 31.63 seconds
Started Jun 26 05:16:31 PM PDT 24
Finished Jun 26 05:17:04 PM PDT 24
Peak memory 206504 kb
Host smart-0feccdaf-622e-4a41-b08d-98b2a2796bc8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2858341634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.2858341634
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.1191109307
Short name T718
Test name
Test status
Simulation time 165032923 ps
CPU time 0.82 seconds
Started Jun 26 05:16:31 PM PDT 24
Finished Jun 26 05:16:32 PM PDT 24
Peak memory 206128 kb
Host smart-5bfffe02-466f-4cca-b9c2-b57a36e534b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11911
09307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.1191109307
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.1516622735
Short name T1258
Test name
Test status
Simulation time 169007869 ps
CPU time 0.8 seconds
Started Jun 26 05:16:33 PM PDT 24
Finished Jun 26 05:16:35 PM PDT 24
Peak memory 206104 kb
Host smart-02b75142-f396-4ffc-8e75-92b612cf4c00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15166
22735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.1516622735
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.1475007449
Short name T559
Test name
Test status
Simulation time 3980884829 ps
CPU time 36.67 seconds
Started Jun 26 05:16:31 PM PDT 24
Finished Jun 26 05:17:08 PM PDT 24
Peak memory 206488 kb
Host smart-c81f0a16-0015-4f0b-b047-3e5382c4e0f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14750
07449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.1475007449
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.3764797882
Short name T1496
Test name
Test status
Simulation time 3874708538 ps
CPU time 4.69 seconds
Started Jun 26 05:10:50 PM PDT 24
Finished Jun 26 05:10:55 PM PDT 24
Peak memory 206704 kb
Host smart-03d0550f-0823-4a4b-892b-6ca0a512ebb8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3764797882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.3764797882
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.2081911449
Short name T2003
Test name
Test status
Simulation time 13446939366 ps
CPU time 14.75 seconds
Started Jun 26 05:10:47 PM PDT 24
Finished Jun 26 05:11:02 PM PDT 24
Peak memory 206428 kb
Host smart-266f0b87-b762-45e6-8278-da9d771b9b28
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2081911449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.2081911449
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.808830800
Short name T1008
Test name
Test status
Simulation time 23313929881 ps
CPU time 24.24 seconds
Started Jun 26 05:10:48 PM PDT 24
Finished Jun 26 05:11:13 PM PDT 24
Peak memory 206308 kb
Host smart-021f6d56-15d6-4569-9865-d8d40cfacd81
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=808830800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.808830800
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.187363124
Short name T479
Test name
Test status
Simulation time 176931662 ps
CPU time 0.77 seconds
Started Jun 26 05:10:46 PM PDT 24
Finished Jun 26 05:10:47 PM PDT 24
Peak memory 206224 kb
Host smart-f0617716-72f7-4eb3-849f-5b3c4a202e41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18736
3124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.187363124
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.27002436
Short name T25
Test name
Test status
Simulation time 173923282 ps
CPU time 0.82 seconds
Started Jun 26 05:10:48 PM PDT 24
Finished Jun 26 05:10:50 PM PDT 24
Peak memory 206024 kb
Host smart-71aa573e-57b9-4463-8068-cd1168f975c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27002
436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.27002436
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.147381039
Short name T40
Test name
Test status
Simulation time 145291599 ps
CPU time 0.79 seconds
Started Jun 26 05:10:54 PM PDT 24
Finished Jun 26 05:10:56 PM PDT 24
Peak memory 206216 kb
Host smart-d3d3ee38-3216-4234-af27-becb8eded195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14738
1039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.147381039
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.1386990985
Short name T741
Test name
Test status
Simulation time 160130606 ps
CPU time 0.78 seconds
Started Jun 26 05:10:47 PM PDT 24
Finished Jun 26 05:10:49 PM PDT 24
Peak memory 206148 kb
Host smart-ecb44ce6-e2ea-434a-91d7-c735c2ff1e43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13869
90985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.1386990985
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.3783721555
Short name T105
Test name
Test status
Simulation time 460294813 ps
CPU time 1.34 seconds
Started Jun 26 05:10:55 PM PDT 24
Finished Jun 26 05:10:57 PM PDT 24
Peak memory 206196 kb
Host smart-68e49d84-122d-49db-a202-e36cf12af442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37837
21555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.3783721555
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.2650510330
Short name T108
Test name
Test status
Simulation time 1133228006 ps
CPU time 2.51 seconds
Started Jun 26 05:10:54 PM PDT 24
Finished Jun 26 05:10:58 PM PDT 24
Peak memory 206368 kb
Host smart-b4a2d366-baf7-42fb-afc6-9facd75bff8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26505
10330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.2650510330
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.854678814
Short name T1354
Test name
Test status
Simulation time 21732585247 ps
CPU time 42.41 seconds
Started Jun 26 05:10:53 PM PDT 24
Finished Jun 26 05:11:36 PM PDT 24
Peak memory 206488 kb
Host smart-df51990d-a905-4daa-9e70-76ac8d3150ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85467
8814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.854678814
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.991268523
Short name T1194
Test name
Test status
Simulation time 337178042 ps
CPU time 1.05 seconds
Started Jun 26 05:10:55 PM PDT 24
Finished Jun 26 05:10:57 PM PDT 24
Peak memory 206200 kb
Host smart-d20abbd0-2c10-4588-b90c-cb896213271d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99126
8523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.991268523
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.4250405713
Short name T255
Test name
Test status
Simulation time 211129116 ps
CPU time 0.82 seconds
Started Jun 26 05:10:55 PM PDT 24
Finished Jun 26 05:10:57 PM PDT 24
Peak memory 206112 kb
Host smart-037df644-0fea-42e1-9710-6994959f526f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42504
05713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.4250405713
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.454651641
Short name T2143
Test name
Test status
Simulation time 46981127 ps
CPU time 0.65 seconds
Started Jun 26 05:10:55 PM PDT 24
Finished Jun 26 05:10:56 PM PDT 24
Peak memory 206136 kb
Host smart-a3c12493-33e1-4698-8275-98293495f1d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45465
1641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.454651641
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.2168502696
Short name T1631
Test name
Test status
Simulation time 935691357 ps
CPU time 2.11 seconds
Started Jun 26 05:10:55 PM PDT 24
Finished Jun 26 05:10:58 PM PDT 24
Peak memory 206324 kb
Host smart-6bb7f595-03fd-4ff0-b73f-5a4441552688
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21685
02696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.2168502696
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.2793830799
Short name T1977
Test name
Test status
Simulation time 245314411 ps
CPU time 1.59 seconds
Started Jun 26 05:10:54 PM PDT 24
Finished Jun 26 05:10:57 PM PDT 24
Peak memory 206320 kb
Host smart-184002c7-e26e-49d9-ae75-d25e42b11171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27938
30799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.2793830799
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.291643901
Short name T1852
Test name
Test status
Simulation time 260862493 ps
CPU time 0.83 seconds
Started Jun 26 05:11:15 PM PDT 24
Finished Jun 26 05:11:17 PM PDT 24
Peak memory 206216 kb
Host smart-3d59cc63-6a8b-4370-ae7b-64b0aae71b04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29164
3901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.291643901
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.827616554
Short name T1909
Test name
Test status
Simulation time 154630355 ps
CPU time 0.77 seconds
Started Jun 26 05:11:16 PM PDT 24
Finished Jun 26 05:11:17 PM PDT 24
Peak memory 206216 kb
Host smart-a628663d-b710-4a44-9609-9362612a24cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82761
6554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.827616554
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.2072461638
Short name T1963
Test name
Test status
Simulation time 168563717 ps
CPU time 0.82 seconds
Started Jun 26 05:10:55 PM PDT 24
Finished Jun 26 05:10:57 PM PDT 24
Peak memory 206124 kb
Host smart-278c9e92-4dd4-4607-afbd-aa0902074e14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20724
61638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.2072461638
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_invalid_sync.98556210
Short name T1250
Test name
Test status
Simulation time 7560826543 ps
CPU time 208.13 seconds
Started Jun 26 05:10:57 PM PDT 24
Finished Jun 26 05:14:26 PM PDT 24
Peak memory 206532 kb
Host smart-941f5a8b-145b-49d3-81f1-8250ee514ebc
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=98556210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.98556210
Directory /workspace/2.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.1474970720
Short name T1651
Test name
Test status
Simulation time 218722993 ps
CPU time 0.86 seconds
Started Jun 26 05:10:55 PM PDT 24
Finished Jun 26 05:10:57 PM PDT 24
Peak memory 206228 kb
Host smart-f5d73885-6570-4ce6-af3a-77f12013c5c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14749
70720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.1474970720
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.3161424546
Short name T2546
Test name
Test status
Simulation time 23366626675 ps
CPU time 22.65 seconds
Started Jun 26 05:10:55 PM PDT 24
Finished Jun 26 05:11:18 PM PDT 24
Peak memory 206328 kb
Host smart-6134a471-6d4d-489c-a101-cc49827c51ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31614
24546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.3161424546
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.4229381145
Short name T2560
Test name
Test status
Simulation time 3288259849 ps
CPU time 3.93 seconds
Started Jun 26 05:10:54 PM PDT 24
Finished Jun 26 05:10:59 PM PDT 24
Peak memory 206236 kb
Host smart-f1855edf-28e8-4102-8f8a-964b0f765e86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42293
81145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.4229381145
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.3902383307
Short name T2320
Test name
Test status
Simulation time 7984696019 ps
CPU time 211.55 seconds
Started Jun 26 05:10:54 PM PDT 24
Finished Jun 26 05:14:27 PM PDT 24
Peak memory 206548 kb
Host smart-9f41277e-ecf9-4705-8c6e-a5f4124d1a7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39023
83307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.3902383307
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.972010582
Short name T2405
Test name
Test status
Simulation time 7242973534 ps
CPU time 193.29 seconds
Started Jun 26 05:11:01 PM PDT 24
Finished Jun 26 05:14:16 PM PDT 24
Peak memory 206532 kb
Host smart-fd2c946e-1e6c-4b0c-9d2b-f61fae343c95
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=972010582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.972010582
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.3186351071
Short name T1543
Test name
Test status
Simulation time 279656982 ps
CPU time 0.91 seconds
Started Jun 26 05:11:17 PM PDT 24
Finished Jun 26 05:11:19 PM PDT 24
Peak memory 206248 kb
Host smart-2970c98c-48c9-4abd-8b48-2dfea13e3f8c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3186351071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.3186351071
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.3925122730
Short name T2338
Test name
Test status
Simulation time 189084223 ps
CPU time 0.87 seconds
Started Jun 26 05:11:03 PM PDT 24
Finished Jun 26 05:11:05 PM PDT 24
Peak memory 206172 kb
Host smart-2b63995d-fb38-41b9-aec9-ebe52356abc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39251
22730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.3925122730
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.650265106
Short name T2181
Test name
Test status
Simulation time 6111801554 ps
CPU time 162.25 seconds
Started Jun 26 05:11:03 PM PDT 24
Finished Jun 26 05:13:47 PM PDT 24
Peak memory 206528 kb
Host smart-7a275ca4-d783-4d21-a21c-43b92471bd56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65026
5106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.650265106
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.278583539
Short name T2036
Test name
Test status
Simulation time 4459228387 ps
CPU time 125.25 seconds
Started Jun 26 05:11:02 PM PDT 24
Finished Jun 26 05:13:09 PM PDT 24
Peak memory 206564 kb
Host smart-16cdf324-d544-47bc-a0b3-10234e8e6244
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=278583539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.278583539
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.1417514391
Short name T1183
Test name
Test status
Simulation time 156247009 ps
CPU time 0.82 seconds
Started Jun 26 05:11:16 PM PDT 24
Finished Jun 26 05:11:18 PM PDT 24
Peak memory 206228 kb
Host smart-30de3b3b-a4f8-4748-b479-923ce44bfc7f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1417514391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.1417514391
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.788562237
Short name T571
Test name
Test status
Simulation time 143749132 ps
CPU time 0.72 seconds
Started Jun 26 05:11:01 PM PDT 24
Finished Jun 26 05:11:02 PM PDT 24
Peak memory 206220 kb
Host smart-f975560a-3c98-4111-a6e3-e66cfd3f4d46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78856
2237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.788562237
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.2384837984
Short name T2015
Test name
Test status
Simulation time 167741176 ps
CPU time 0.85 seconds
Started Jun 26 05:11:02 PM PDT 24
Finished Jun 26 05:11:04 PM PDT 24
Peak memory 206204 kb
Host smart-e375738f-47f4-4e69-b5a1-2e19e13b07af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23848
37984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.2384837984
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.544515667
Short name T828
Test name
Test status
Simulation time 184519436 ps
CPU time 0.8 seconds
Started Jun 26 05:11:01 PM PDT 24
Finished Jun 26 05:11:03 PM PDT 24
Peak memory 206148 kb
Host smart-86840aea-0bcb-45c9-b51d-e6b77c69558d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54451
5667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.544515667
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.3972463886
Short name T1190
Test name
Test status
Simulation time 177534075 ps
CPU time 0.85 seconds
Started Jun 26 05:11:01 PM PDT 24
Finished Jun 26 05:11:03 PM PDT 24
Peak memory 206172 kb
Host smart-449df27e-2b0d-4bbe-8cbd-e27440e205c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39724
63886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.3972463886
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.3571485872
Short name T838
Test name
Test status
Simulation time 155398984 ps
CPU time 0.73 seconds
Started Jun 26 05:11:17 PM PDT 24
Finished Jun 26 05:11:19 PM PDT 24
Peak memory 206196 kb
Host smart-03853153-3fbe-476d-ab1f-86c844010a4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35714
85872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.3571485872
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.1370910331
Short name T663
Test name
Test status
Simulation time 211926073 ps
CPU time 0.96 seconds
Started Jun 26 05:11:03 PM PDT 24
Finished Jun 26 05:11:05 PM PDT 24
Peak memory 206400 kb
Host smart-0476919f-1d4e-420d-8d53-a8a41d9d7913
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1370910331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.1370910331
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.770937490
Short name T208
Test name
Test status
Simulation time 240960177 ps
CPU time 0.93 seconds
Started Jun 26 05:11:02 PM PDT 24
Finished Jun 26 05:11:04 PM PDT 24
Peak memory 206116 kb
Host smart-86b57969-03f5-4b7c-8016-ec434699eea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77093
7490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.770937490
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.3598362460
Short name T913
Test name
Test status
Simulation time 186457061 ps
CPU time 0.79 seconds
Started Jun 26 05:11:05 PM PDT 24
Finished Jun 26 05:11:07 PM PDT 24
Peak memory 206212 kb
Host smart-a5717be5-8081-4b96-bfc8-27dd96e36ec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35983
62460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.3598362460
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.2006471023
Short name T2520
Test name
Test status
Simulation time 42320387 ps
CPU time 0.67 seconds
Started Jun 26 05:11:17 PM PDT 24
Finished Jun 26 05:11:18 PM PDT 24
Peak memory 206112 kb
Host smart-e56d76e7-210d-4449-9c04-356cf6c41867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20064
71023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.2006471023
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.1517813006
Short name T2209
Test name
Test status
Simulation time 16398820264 ps
CPU time 36.64 seconds
Started Jun 26 05:11:02 PM PDT 24
Finished Jun 26 05:11:40 PM PDT 24
Peak memory 206492 kb
Host smart-971bc42e-818c-4d1c-be79-3cacef691cc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15178
13006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.1517813006
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.702393459
Short name T2427
Test name
Test status
Simulation time 176955712 ps
CPU time 0.79 seconds
Started Jun 26 05:11:06 PM PDT 24
Finished Jun 26 05:11:08 PM PDT 24
Peak memory 206216 kb
Host smart-3d2f18c9-57a9-4e07-b993-b016d0607fd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70239
3459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.702393459
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.1870435898
Short name T679
Test name
Test status
Simulation time 198478862 ps
CPU time 0.85 seconds
Started Jun 26 05:11:03 PM PDT 24
Finished Jun 26 05:11:05 PM PDT 24
Peak memory 206188 kb
Host smart-adca671d-c2ee-4e33-a808-97565e291ee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18704
35898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.1870435898
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.4275184947
Short name T572
Test name
Test status
Simulation time 20852396067 ps
CPU time 556.38 seconds
Started Jun 26 05:11:03 PM PDT 24
Finished Jun 26 05:20:21 PM PDT 24
Peak memory 206516 kb
Host smart-26fffdf7-02a8-4538-9fd9-96fba9458e42
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4275184947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.4275184947
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.2908263355
Short name T933
Test name
Test status
Simulation time 10664763680 ps
CPU time 198.16 seconds
Started Jun 26 05:11:03 PM PDT 24
Finished Jun 26 05:14:23 PM PDT 24
Peak memory 206460 kb
Host smart-d222642e-52a5-4d9b-ae11-bba22ea068e3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2908263355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.2908263355
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.1559853051
Short name T1695
Test name
Test status
Simulation time 166221889 ps
CPU time 0.79 seconds
Started Jun 26 05:11:17 PM PDT 24
Finished Jun 26 05:11:19 PM PDT 24
Peak memory 206192 kb
Host smart-217bf9f2-8003-4f2c-9440-91b807d7747e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15598
53051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.1559853051
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.249087220
Short name T1118
Test name
Test status
Simulation time 171761417 ps
CPU time 0.83 seconds
Started Jun 26 05:11:01 PM PDT 24
Finished Jun 26 05:11:04 PM PDT 24
Peak memory 206112 kb
Host smart-a1b1b490-9c7c-4f6a-a4d7-aef775cb6da3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24908
7220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.249087220
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.3308444834
Short name T454
Test name
Test status
Simulation time 149474631 ps
CPU time 0.76 seconds
Started Jun 26 05:11:09 PM PDT 24
Finished Jun 26 05:11:11 PM PDT 24
Peak memory 206212 kb
Host smart-7e1c2648-46c0-4da1-aab8-5023120346a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33084
44834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.3308444834
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.1313998901
Short name T71
Test name
Test status
Simulation time 167948513 ps
CPU time 0.78 seconds
Started Jun 26 05:11:11 PM PDT 24
Finished Jun 26 05:11:13 PM PDT 24
Peak memory 206100 kb
Host smart-0c6275a2-5a71-40ab-982a-afbdd425b0db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13139
98901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.1313998901
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.597594588
Short name T200
Test name
Test status
Simulation time 1149010701 ps
CPU time 2.03 seconds
Started Jun 26 05:11:15 PM PDT 24
Finished Jun 26 05:11:18 PM PDT 24
Peak memory 224984 kb
Host smart-9eb594ee-aa5a-418b-875f-6ad3945d2c4f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=597594588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.597594588
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.2725867019
Short name T47
Test name
Test status
Simulation time 429683545 ps
CPU time 1.21 seconds
Started Jun 26 05:11:09 PM PDT 24
Finished Jun 26 05:11:12 PM PDT 24
Peak memory 206128 kb
Host smart-2deb63ff-27c0-4238-8af4-9abd88259e4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27258
67019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.2725867019
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.2003614614
Short name T1611
Test name
Test status
Simulation time 153967493 ps
CPU time 0.75 seconds
Started Jun 26 05:11:09 PM PDT 24
Finished Jun 26 05:11:10 PM PDT 24
Peak memory 206132 kb
Host smart-39c31e2c-87dc-4452-862e-d3a75ecaaf47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20036
14614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.2003614614
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.4286260511
Short name T1227
Test name
Test status
Simulation time 157443429 ps
CPU time 0.76 seconds
Started Jun 26 05:11:09 PM PDT 24
Finished Jun 26 05:11:11 PM PDT 24
Peak memory 206224 kb
Host smart-b3343ef2-b462-41e5-983d-c264daf180a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42862
60511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.4286260511
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.2182691769
Short name T734
Test name
Test status
Simulation time 227963499 ps
CPU time 0.92 seconds
Started Jun 26 05:11:10 PM PDT 24
Finished Jun 26 05:11:12 PM PDT 24
Peak memory 206140 kb
Host smart-fc06aa4f-5982-4b53-a73a-3f3f7c3aab9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21826
91769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.2182691769
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.3507733768
Short name T2183
Test name
Test status
Simulation time 6403102520 ps
CPU time 56.66 seconds
Started Jun 26 05:11:10 PM PDT 24
Finished Jun 26 05:12:08 PM PDT 24
Peak memory 206460 kb
Host smart-546b3d62-7387-4a59-986e-3be9c9815eaa
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3507733768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.3507733768
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.4244127454
Short name T1289
Test name
Test status
Simulation time 187051701 ps
CPU time 0.79 seconds
Started Jun 26 05:11:11 PM PDT 24
Finished Jun 26 05:11:13 PM PDT 24
Peak memory 206100 kb
Host smart-9b0ef51f-7ecb-4d2c-9004-911e5a1f776b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42441
27454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.4244127454
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.1449238538
Short name T1741
Test name
Test status
Simulation time 182383194 ps
CPU time 0.84 seconds
Started Jun 26 05:11:09 PM PDT 24
Finished Jun 26 05:11:11 PM PDT 24
Peak memory 206208 kb
Host smart-7335ba16-852a-453b-910b-d1aa6fe34a5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14492
38538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.1449238538
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.473936509
Short name T418
Test name
Test status
Simulation time 3964242891 ps
CPU time 36.49 seconds
Started Jun 26 05:11:10 PM PDT 24
Finished Jun 26 05:11:48 PM PDT 24
Peak memory 206396 kb
Host smart-d63d2bb6-1d49-4b13-a134-7e1ad54aa936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47393
6509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.473936509
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.661237340
Short name T232
Test name
Test status
Simulation time 9959718710 ps
CPU time 170.78 seconds
Started Jun 26 05:11:10 PM PDT 24
Finished Jun 26 05:14:02 PM PDT 24
Peak memory 206516 kb
Host smart-c96aede6-117b-4b3d-ae85-b86a2f1f565d
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=661237340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.661237340
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.2421959906
Short name T1754
Test name
Test status
Simulation time 4297097841 ps
CPU time 4.7 seconds
Started Jun 26 05:16:31 PM PDT 24
Finished Jun 26 05:16:36 PM PDT 24
Peak memory 206584 kb
Host smart-2dd551b0-1d42-49b0-89c1-9690494a48e2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2421959906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.2421959906
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.253568101
Short name T1061
Test name
Test status
Simulation time 13370822220 ps
CPU time 15.54 seconds
Started Jun 26 05:16:31 PM PDT 24
Finished Jun 26 05:16:48 PM PDT 24
Peak memory 206328 kb
Host smart-3331c051-1dff-4d15-bf91-c7f9d280ac7e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=253568101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.253568101
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.1829516232
Short name T2081
Test name
Test status
Simulation time 23411385846 ps
CPU time 23.43 seconds
Started Jun 26 05:16:39 PM PDT 24
Finished Jun 26 05:17:03 PM PDT 24
Peak memory 206300 kb
Host smart-ab17d521-f2e8-49cc-941a-e978e6d704e9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1829516232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.1829516232
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.3549386453
Short name T1921
Test name
Test status
Simulation time 202967188 ps
CPU time 0.86 seconds
Started Jun 26 05:16:40 PM PDT 24
Finished Jun 26 05:16:41 PM PDT 24
Peak memory 206204 kb
Host smart-8ea16ace-936b-4bbb-8a48-bb511711b596
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35493
86453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.3549386453
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.504325725
Short name T2261
Test name
Test status
Simulation time 151597038 ps
CPU time 0.75 seconds
Started Jun 26 05:16:40 PM PDT 24
Finished Jun 26 05:16:42 PM PDT 24
Peak memory 206212 kb
Host smart-6aff6683-2513-4632-8ce3-ee8a7a05b5d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50432
5725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.504325725
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.3380614952
Short name T975
Test name
Test status
Simulation time 160579151 ps
CPU time 0.84 seconds
Started Jun 26 05:16:39 PM PDT 24
Finished Jun 26 05:16:40 PM PDT 24
Peak memory 206192 kb
Host smart-1b64ebb1-9016-4895-b405-ce0f3ab993e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33806
14952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.3380614952
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.2394805695
Short name T1845
Test name
Test status
Simulation time 461372433 ps
CPU time 1.22 seconds
Started Jun 26 05:16:38 PM PDT 24
Finished Jun 26 05:16:40 PM PDT 24
Peak memory 206224 kb
Host smart-55cd8ff0-d9b4-4990-a3e6-e261f04b0415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23948
05695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.2394805695
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.685400574
Short name T1176
Test name
Test status
Simulation time 19821112784 ps
CPU time 34.95 seconds
Started Jun 26 05:16:41 PM PDT 24
Finished Jun 26 05:17:18 PM PDT 24
Peak memory 206552 kb
Host smart-c4ad6625-8d3e-4628-b793-b3c0dd6d19eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68540
0574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.685400574
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.2308285476
Short name T764
Test name
Test status
Simulation time 385929713 ps
CPU time 1.23 seconds
Started Jun 26 05:16:40 PM PDT 24
Finished Jun 26 05:16:42 PM PDT 24
Peak memory 206212 kb
Host smart-2ff0395c-b782-4896-b917-7280ae66eb13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23082
85476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.2308285476
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_enable.373850892
Short name T1294
Test name
Test status
Simulation time 38521249 ps
CPU time 0.66 seconds
Started Jun 26 05:16:39 PM PDT 24
Finished Jun 26 05:16:40 PM PDT 24
Peak memory 206176 kb
Host smart-77b3585c-38b4-4536-b74b-2717e18e7f3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37385
0892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.373850892
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.3620193416
Short name T1667
Test name
Test status
Simulation time 756303588 ps
CPU time 1.86 seconds
Started Jun 26 05:16:39 PM PDT 24
Finished Jun 26 05:16:42 PM PDT 24
Peak memory 206380 kb
Host smart-50f5c5d6-9a15-4a82-9f60-55561a7ac824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36201
93416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.3620193416
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.1789158737
Short name T475
Test name
Test status
Simulation time 147380140 ps
CPU time 1.19 seconds
Started Jun 26 05:16:41 PM PDT 24
Finished Jun 26 05:16:43 PM PDT 24
Peak memory 206328 kb
Host smart-f7d33052-e694-4b1b-8462-ee6d052f3397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17891
58737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.1789158737
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.2510597559
Short name T444
Test name
Test status
Simulation time 209761695 ps
CPU time 0.84 seconds
Started Jun 26 05:16:50 PM PDT 24
Finished Jun 26 05:16:54 PM PDT 24
Peak memory 206024 kb
Host smart-0266a5ef-df0e-454c-b64d-ff242e03c5d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25105
97559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.2510597559
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.4284155045
Short name T1906
Test name
Test status
Simulation time 155959205 ps
CPU time 0.74 seconds
Started Jun 26 05:16:47 PM PDT 24
Finished Jun 26 05:16:50 PM PDT 24
Peak memory 206136 kb
Host smart-6f5dec6b-50e3-4fd9-8aa7-c2e929ff5973
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42841
55045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.4284155045
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.2036126962
Short name T1095
Test name
Test status
Simulation time 223111488 ps
CPU time 0.88 seconds
Started Jun 26 05:16:40 PM PDT 24
Finished Jun 26 05:16:42 PM PDT 24
Peak memory 206232 kb
Host smart-97ee30cb-4f9e-4a7c-a749-b95c75b3e8ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20361
26962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.2036126962
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_invalid_sync.2947756477
Short name T2468
Test name
Test status
Simulation time 5308970312 ps
CPU time 133.92 seconds
Started Jun 26 05:16:39 PM PDT 24
Finished Jun 26 05:18:54 PM PDT 24
Peak memory 206388 kb
Host smart-b14b8e53-82af-46ac-a6f8-518b0331209c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2947756477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_invalid_sync.2947756477
Directory /workspace/20.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.2351534349
Short name T964
Test name
Test status
Simulation time 197606861 ps
CPU time 0.87 seconds
Started Jun 26 05:16:43 PM PDT 24
Finished Jun 26 05:16:45 PM PDT 24
Peak memory 206224 kb
Host smart-e11bfc2c-00d7-4791-a3d2-15063fac6896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23515
34349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.2351534349
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.1818318596
Short name T467
Test name
Test status
Simulation time 23346740666 ps
CPU time 25.89 seconds
Started Jun 26 05:16:39 PM PDT 24
Finished Jun 26 05:17:06 PM PDT 24
Peak memory 206264 kb
Host smart-628b3414-e161-48a8-ba56-566c127eefbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18183
18596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.1818318596
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.2751601461
Short name T2471
Test name
Test status
Simulation time 3312997266 ps
CPU time 3.63 seconds
Started Jun 26 05:16:40 PM PDT 24
Finished Jun 26 05:16:44 PM PDT 24
Peak memory 206276 kb
Host smart-edc90b4f-aab9-46ca-9221-372e4fae2c41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27516
01461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.2751601461
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.2983495050
Short name T2263
Test name
Test status
Simulation time 10277540526 ps
CPU time 303.19 seconds
Started Jun 26 05:16:39 PM PDT 24
Finished Jun 26 05:21:43 PM PDT 24
Peak memory 206484 kb
Host smart-5a9931bd-2fea-4162-99f8-a9c2866769de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29834
95050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.2983495050
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.225159942
Short name T1787
Test name
Test status
Simulation time 4933604797 ps
CPU time 128.77 seconds
Started Jun 26 05:16:46 PM PDT 24
Finished Jun 26 05:18:56 PM PDT 24
Peak memory 206544 kb
Host smart-e85c9d12-1afa-4f0e-9475-44c5715ebfb3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=225159942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.225159942
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.1748647263
Short name T491
Test name
Test status
Simulation time 267069724 ps
CPU time 1 seconds
Started Jun 26 05:16:50 PM PDT 24
Finished Jun 26 05:16:54 PM PDT 24
Peak memory 206216 kb
Host smart-244909cd-c568-4705-b7f9-a81c89defb4e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1748647263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.1748647263
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.525035551
Short name T546
Test name
Test status
Simulation time 235156927 ps
CPU time 0.88 seconds
Started Jun 26 05:16:47 PM PDT 24
Finished Jun 26 05:16:50 PM PDT 24
Peak memory 206204 kb
Host smart-11c5ed09-342d-4024-ab1b-587619aec7ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52503
5551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.525035551
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.511565324
Short name T1606
Test name
Test status
Simulation time 3478589368 ps
CPU time 96.8 seconds
Started Jun 26 05:16:47 PM PDT 24
Finished Jun 26 05:18:27 PM PDT 24
Peak memory 206440 kb
Host smart-d9f413a3-191f-46fc-a559-6d8ae140b095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51156
5324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.511565324
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.4244226857
Short name T2152
Test name
Test status
Simulation time 4336078590 ps
CPU time 31.98 seconds
Started Jun 26 05:16:52 PM PDT 24
Finished Jun 26 05:17:27 PM PDT 24
Peak memory 206452 kb
Host smart-b3e67ea5-d9e2-412d-8b22-e7a9fe15702e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4244226857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.4244226857
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.3719513271
Short name T1273
Test name
Test status
Simulation time 170692258 ps
CPU time 0.82 seconds
Started Jun 26 05:16:47 PM PDT 24
Finished Jun 26 05:16:51 PM PDT 24
Peak memory 206120 kb
Host smart-c6fcc364-11e7-4062-b182-53843c1dfa60
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3719513271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.3719513271
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.1953819316
Short name T2509
Test name
Test status
Simulation time 180320542 ps
CPU time 0.77 seconds
Started Jun 26 05:16:50 PM PDT 24
Finished Jun 26 05:16:54 PM PDT 24
Peak memory 206024 kb
Host smart-8372dc52-4670-43ff-a120-bc4f801483e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19538
19316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.1953819316
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.2062290725
Short name T934
Test name
Test status
Simulation time 200362517 ps
CPU time 0.88 seconds
Started Jun 26 05:16:53 PM PDT 24
Finished Jun 26 05:16:57 PM PDT 24
Peak memory 206184 kb
Host smart-e2eb6cde-e3d3-4c30-8a68-61fedfca1c96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20622
90725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.2062290725
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.4019388789
Short name T1202
Test name
Test status
Simulation time 165498533 ps
CPU time 0.83 seconds
Started Jun 26 05:16:49 PM PDT 24
Finished Jun 26 05:16:53 PM PDT 24
Peak memory 206176 kb
Host smart-828cbe21-1f47-4bbe-bda4-d450679bdec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40193
88789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.4019388789
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.3930523291
Short name T1758
Test name
Test status
Simulation time 151407670 ps
CPU time 0.78 seconds
Started Jun 26 05:16:47 PM PDT 24
Finished Jun 26 05:16:51 PM PDT 24
Peak memory 206204 kb
Host smart-9c6c6ddc-e10e-4a01-a483-89868b26b524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39305
23291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.3930523291
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.4220510344
Short name T175
Test name
Test status
Simulation time 152861125 ps
CPU time 0.76 seconds
Started Jun 26 05:16:49 PM PDT 24
Finished Jun 26 05:16:53 PM PDT 24
Peak memory 206120 kb
Host smart-2fd1261e-079d-4402-9653-c04a676fd505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42205
10344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.4220510344
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.844612719
Short name T1756
Test name
Test status
Simulation time 255213068 ps
CPU time 0.99 seconds
Started Jun 26 05:16:46 PM PDT 24
Finished Jun 26 05:16:49 PM PDT 24
Peak memory 206200 kb
Host smart-c4cdebc2-6be1-437a-b2b4-c831c6efb9a9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=844612719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.844612719
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.3508309470
Short name T1213
Test name
Test status
Simulation time 164614411 ps
CPU time 0.79 seconds
Started Jun 26 05:16:51 PM PDT 24
Finished Jun 26 05:16:55 PM PDT 24
Peak memory 206128 kb
Host smart-544a46ab-bf00-42b5-9872-4fea9589ca6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35083
09470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.3508309470
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.1283838961
Short name T33
Test name
Test status
Simulation time 42209837 ps
CPU time 0.71 seconds
Started Jun 26 05:16:50 PM PDT 24
Finished Jun 26 05:16:54 PM PDT 24
Peak memory 206172 kb
Host smart-a4c5d51a-7e80-41f4-b9e3-274f0e330c22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12838
38961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.1283838961
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.602603451
Short name T247
Test name
Test status
Simulation time 23454021044 ps
CPU time 53.9 seconds
Started Jun 26 05:16:48 PM PDT 24
Finished Jun 26 05:17:46 PM PDT 24
Peak memory 206468 kb
Host smart-ca35ce87-1a28-4950-a912-d532ab715452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60260
3451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.602603451
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.2158072559
Short name T1923
Test name
Test status
Simulation time 201240074 ps
CPU time 0.87 seconds
Started Jun 26 05:16:48 PM PDT 24
Finished Jun 26 05:16:51 PM PDT 24
Peak memory 206184 kb
Host smart-41945b13-99ec-446f-a72f-afe5840b275a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21580
72559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.2158072559
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.1366901817
Short name T2254
Test name
Test status
Simulation time 191763514 ps
CPU time 0.81 seconds
Started Jun 26 05:16:46 PM PDT 24
Finished Jun 26 05:16:48 PM PDT 24
Peak memory 206192 kb
Host smart-e0837ab5-015b-4fb4-ae93-5edaa3c8d8b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13669
01817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.1366901817
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.198916919
Short name T1486
Test name
Test status
Simulation time 160413726 ps
CPU time 0.79 seconds
Started Jun 26 05:16:52 PM PDT 24
Finished Jun 26 05:16:56 PM PDT 24
Peak memory 206144 kb
Host smart-770a6c20-bb3e-414c-9d68-4a85edf91632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19891
6919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.198916919
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.4294608311
Short name T1319
Test name
Test status
Simulation time 254671432 ps
CPU time 0.86 seconds
Started Jun 26 05:16:50 PM PDT 24
Finished Jun 26 05:16:54 PM PDT 24
Peak memory 206028 kb
Host smart-bdb7b1f7-535b-4025-863d-e3abfff11438
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42946
08311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.4294608311
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.3223331518
Short name T2192
Test name
Test status
Simulation time 205835763 ps
CPU time 0.82 seconds
Started Jun 26 05:16:48 PM PDT 24
Finished Jun 26 05:16:52 PM PDT 24
Peak memory 206220 kb
Host smart-86d623d1-2871-43f4-993d-48ba393c4793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32233
31518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.3223331518
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.3319426864
Short name T846
Test name
Test status
Simulation time 191639310 ps
CPU time 0.79 seconds
Started Jun 26 05:16:51 PM PDT 24
Finished Jun 26 05:16:55 PM PDT 24
Peak memory 206112 kb
Host smart-68c93539-7d07-445f-8c95-d1bf118cdc50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33194
26864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.3319426864
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.21124027
Short name T1899
Test name
Test status
Simulation time 169382920 ps
CPU time 0.79 seconds
Started Jun 26 05:16:47 PM PDT 24
Finished Jun 26 05:16:50 PM PDT 24
Peak memory 206148 kb
Host smart-b715edb0-ac42-45d2-a1f3-2435a1601e7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21124
027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.21124027
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.3078929424
Short name T88
Test name
Test status
Simulation time 180645910 ps
CPU time 0.86 seconds
Started Jun 26 05:16:54 PM PDT 24
Finished Jun 26 05:16:58 PM PDT 24
Peak memory 206188 kb
Host smart-81338028-f752-48ae-a6cb-6ec504110164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30789
29424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.3078929424
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.4186707892
Short name T2063
Test name
Test status
Simulation time 5615367145 ps
CPU time 50.85 seconds
Started Jun 26 05:16:48 PM PDT 24
Finished Jun 26 05:17:42 PM PDT 24
Peak memory 206512 kb
Host smart-d831f4bc-4817-4a63-a876-15042b5008f4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4186707892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.4186707892
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.1318961943
Short name T2341
Test name
Test status
Simulation time 225034914 ps
CPU time 0.83 seconds
Started Jun 26 05:16:46 PM PDT 24
Finished Jun 26 05:16:47 PM PDT 24
Peak memory 206212 kb
Host smart-7ec59dc5-b219-41b0-b766-81a812d5dcfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13189
61943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.1318961943
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.3818832596
Short name T2297
Test name
Test status
Simulation time 176714174 ps
CPU time 0.79 seconds
Started Jun 26 05:16:50 PM PDT 24
Finished Jun 26 05:16:54 PM PDT 24
Peak memory 206112 kb
Host smart-0eb11d7b-1b15-42dd-be45-bd444e4dfad3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38188
32596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.3818832596
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.4043572242
Short name T2503
Test name
Test status
Simulation time 5808346225 ps
CPU time 39.04 seconds
Started Jun 26 05:16:47 PM PDT 24
Finished Jun 26 05:17:29 PM PDT 24
Peak memory 206492 kb
Host smart-01ad7b74-847f-4981-9e0a-b1e6fc2d2270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40435
72242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.4043572242
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.18621288
Short name T476
Test name
Test status
Simulation time 4073771966 ps
CPU time 4.72 seconds
Started Jun 26 05:16:53 PM PDT 24
Finished Jun 26 05:17:01 PM PDT 24
Peak memory 206384 kb
Host smart-7179b0ab-f0d8-4d43-8ba6-62b89445cd9f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=18621288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.18621288
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.2730078404
Short name T2300
Test name
Test status
Simulation time 13349443938 ps
CPU time 14.35 seconds
Started Jun 26 05:16:48 PM PDT 24
Finished Jun 26 05:17:05 PM PDT 24
Peak memory 206244 kb
Host smart-638c92a9-cd39-4e12-9444-8face11f2c6c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2730078404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.2730078404
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.2917215065
Short name T1003
Test name
Test status
Simulation time 23390552310 ps
CPU time 22.29 seconds
Started Jun 26 05:16:47 PM PDT 24
Finished Jun 26 05:17:12 PM PDT 24
Peak memory 206516 kb
Host smart-d6666f79-0814-409e-8682-a728e7c67ea1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2917215065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.2917215065
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.4068341569
Short name T1973
Test name
Test status
Simulation time 185397239 ps
CPU time 0.87 seconds
Started Jun 26 05:16:48 PM PDT 24
Finished Jun 26 05:16:52 PM PDT 24
Peak memory 206124 kb
Host smart-bf1459c6-8b76-4425-ab40-bcfeff304876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40683
41569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.4068341569
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.492441393
Short name T611
Test name
Test status
Simulation time 167596316 ps
CPU time 0.82 seconds
Started Jun 26 05:16:51 PM PDT 24
Finished Jun 26 05:16:55 PM PDT 24
Peak memory 206168 kb
Host smart-18b3dd19-3e9b-4dd6-8b64-4383f223ef0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49244
1393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.492441393
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.1408488345
Short name T1175
Test name
Test status
Simulation time 535403690 ps
CPU time 1.5 seconds
Started Jun 26 05:16:48 PM PDT 24
Finished Jun 26 05:16:52 PM PDT 24
Peak memory 206208 kb
Host smart-d0fc6b50-d287-4d7a-8723-b64ad19a61a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14084
88345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.1408488345
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.805814725
Short name T2131
Test name
Test status
Simulation time 942272382 ps
CPU time 2.35 seconds
Started Jun 26 05:16:49 PM PDT 24
Finished Jun 26 05:16:55 PM PDT 24
Peak memory 206428 kb
Host smart-9f3dbf16-b6e2-4d9c-82e7-e7df566d9ce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80581
4725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.805814725
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.3069716661
Short name T837
Test name
Test status
Simulation time 10682496014 ps
CPU time 20.87 seconds
Started Jun 26 05:16:51 PM PDT 24
Finished Jun 26 05:17:15 PM PDT 24
Peak memory 206556 kb
Host smart-b1ad768f-e451-4ef4-af3e-83583dc1e434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30697
16661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.3069716661
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.3871763818
Short name T1155
Test name
Test status
Simulation time 448914102 ps
CPU time 1.38 seconds
Started Jun 26 05:16:57 PM PDT 24
Finished Jun 26 05:17:02 PM PDT 24
Peak memory 206124 kb
Host smart-4bf04e5e-4b13-455b-a653-5d5c1857c088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38717
63818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.3871763818
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.1038167845
Short name T35
Test name
Test status
Simulation time 148519505 ps
CPU time 0.78 seconds
Started Jun 26 05:16:53 PM PDT 24
Finished Jun 26 05:16:56 PM PDT 24
Peak memory 206440 kb
Host smart-dd564524-c40f-4691-ab88-1aa9843bf790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10381
67845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.1038167845
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.2800393499
Short name T2565
Test name
Test status
Simulation time 35091165 ps
CPU time 0.67 seconds
Started Jun 26 05:16:53 PM PDT 24
Finished Jun 26 05:16:57 PM PDT 24
Peak memory 206216 kb
Host smart-d0f1f9b6-4aea-4955-bb96-3da550005cb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28003
93499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.2800393499
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.1692887099
Short name T1908
Test name
Test status
Simulation time 1032100818 ps
CPU time 2.18 seconds
Started Jun 26 05:16:55 PM PDT 24
Finished Jun 26 05:17:01 PM PDT 24
Peak memory 206336 kb
Host smart-d156b477-4ba3-47c5-b619-0e2cbbaae21c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16928
87099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.1692887099
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.4121452356
Short name T513
Test name
Test status
Simulation time 174891325 ps
CPU time 1.79 seconds
Started Jun 26 05:16:52 PM PDT 24
Finished Jun 26 05:16:57 PM PDT 24
Peak memory 206392 kb
Host smart-6972258d-8f5b-4ebc-a1d3-bde6f455e7a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41214
52356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.4121452356
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.401244610
Short name T1858
Test name
Test status
Simulation time 223165752 ps
CPU time 0.88 seconds
Started Jun 26 05:16:58 PM PDT 24
Finished Jun 26 05:17:02 PM PDT 24
Peak memory 206232 kb
Host smart-75fe5100-0c23-4749-ab6d-6b800e27aa9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40124
4610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.401244610
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.1643883118
Short name T825
Test name
Test status
Simulation time 140202414 ps
CPU time 0.77 seconds
Started Jun 26 05:17:00 PM PDT 24
Finished Jun 26 05:17:04 PM PDT 24
Peak memory 206212 kb
Host smart-2c789355-318d-455e-91a2-2de71e257c8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16438
83118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.1643883118
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.2069654597
Short name T1949
Test name
Test status
Simulation time 239069367 ps
CPU time 0.93 seconds
Started Jun 26 05:16:57 PM PDT 24
Finished Jun 26 05:17:01 PM PDT 24
Peak memory 206140 kb
Host smart-43aa8905-b14c-4c52-b996-748995d09d9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20696
54597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.2069654597
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_invalid_sync.1237813002
Short name T1288
Test name
Test status
Simulation time 6653149074 ps
CPU time 48.46 seconds
Started Jun 26 05:16:56 PM PDT 24
Finished Jun 26 05:17:48 PM PDT 24
Peak memory 206432 kb
Host smart-3b369721-a946-44c1-ac8e-82d5c6dce8b3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1237813002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_invalid_sync.1237813002
Directory /workspace/21.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.1087987806
Short name T2094
Test name
Test status
Simulation time 178047312 ps
CPU time 0.85 seconds
Started Jun 26 05:16:54 PM PDT 24
Finished Jun 26 05:16:58 PM PDT 24
Peak memory 206172 kb
Host smart-42082919-d6f2-4e01-bbc3-e8184a0e2f22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10879
87806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.1087987806
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.3015663573
Short name T1740
Test name
Test status
Simulation time 23313270676 ps
CPU time 21.49 seconds
Started Jun 26 05:16:58 PM PDT 24
Finished Jun 26 05:17:23 PM PDT 24
Peak memory 206236 kb
Host smart-f22f2c53-7dbd-497b-8da3-85dbcf2b75ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30156
63573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.3015663573
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.3759039411
Short name T1279
Test name
Test status
Simulation time 3261344428 ps
CPU time 3.93 seconds
Started Jun 26 05:16:52 PM PDT 24
Finished Jun 26 05:16:59 PM PDT 24
Peak memory 206232 kb
Host smart-27a8a283-fb59-44b7-9c06-3d12400ab3d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37590
39411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.3759039411
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.2107369047
Short name T1393
Test name
Test status
Simulation time 7929959169 ps
CPU time 78.65 seconds
Started Jun 26 05:16:53 PM PDT 24
Finished Jun 26 05:18:15 PM PDT 24
Peak memory 206504 kb
Host smart-d727ff5e-c005-47da-abfc-ddcaf4c228d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21073
69047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.2107369047
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.2239106603
Short name T644
Test name
Test status
Simulation time 7104079131 ps
CPU time 195.67 seconds
Started Jun 26 05:16:52 PM PDT 24
Finished Jun 26 05:20:11 PM PDT 24
Peak memory 206536 kb
Host smart-b351f28b-41bc-4e55-b970-90004b41746b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2239106603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.2239106603
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.3365386431
Short name T1497
Test name
Test status
Simulation time 247549314 ps
CPU time 0.96 seconds
Started Jun 26 05:16:58 PM PDT 24
Finished Jun 26 05:17:02 PM PDT 24
Peak memory 206168 kb
Host smart-89ee8820-f245-4817-b07c-e788ac3b07f4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3365386431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.3365386431
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.3890640368
Short name T2493
Test name
Test status
Simulation time 219485597 ps
CPU time 0.88 seconds
Started Jun 26 05:16:56 PM PDT 24
Finished Jun 26 05:17:01 PM PDT 24
Peak memory 206100 kb
Host smart-51b813e9-f45c-4649-b8e9-b0ff61da0437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38906
40368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.3890640368
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.3678350502
Short name T439
Test name
Test status
Simulation time 5487966262 ps
CPU time 40 seconds
Started Jun 26 05:16:53 PM PDT 24
Finished Jun 26 05:17:36 PM PDT 24
Peak memory 206440 kb
Host smart-9bb20396-a997-4508-8140-6f8f02aa4155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36783
50502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.3678350502
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.786106252
Short name T1238
Test name
Test status
Simulation time 3667992479 ps
CPU time 26.97 seconds
Started Jun 26 05:16:57 PM PDT 24
Finished Jun 26 05:17:27 PM PDT 24
Peak memory 206360 kb
Host smart-814faddb-7776-4c04-a9ab-1dc03f26b5d5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=786106252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.786106252
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.902511445
Short name T1447
Test name
Test status
Simulation time 195619097 ps
CPU time 0.8 seconds
Started Jun 26 05:17:00 PM PDT 24
Finished Jun 26 05:17:04 PM PDT 24
Peak memory 206144 kb
Host smart-90b8c4bd-ada2-4afd-bd81-f55ef60bb408
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=902511445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.902511445
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.1091431381
Short name T1162
Test name
Test status
Simulation time 155143835 ps
CPU time 0.79 seconds
Started Jun 26 05:16:53 PM PDT 24
Finished Jun 26 05:16:57 PM PDT 24
Peak memory 206184 kb
Host smart-cc07b11c-ef0d-4aae-9ba0-b34700222ea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10914
31381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.1091431381
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.884833408
Short name T2436
Test name
Test status
Simulation time 228632110 ps
CPU time 0.89 seconds
Started Jun 26 05:16:53 PM PDT 24
Finished Jun 26 05:16:57 PM PDT 24
Peak memory 206208 kb
Host smart-f8f82f1b-4123-49f3-abf7-ee5905a7350b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88483
3408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.884833408
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.232397888
Short name T924
Test name
Test status
Simulation time 199289378 ps
CPU time 0.89 seconds
Started Jun 26 05:16:53 PM PDT 24
Finished Jun 26 05:16:58 PM PDT 24
Peak memory 206224 kb
Host smart-d2cbde66-05db-4b80-a23e-3375b408190e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23239
7888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.232397888
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.3048340693
Short name T2287
Test name
Test status
Simulation time 172168753 ps
CPU time 0.8 seconds
Started Jun 26 05:16:57 PM PDT 24
Finished Jun 26 05:17:01 PM PDT 24
Peak memory 206120 kb
Host smart-09c015ef-09ee-4d17-881b-fcad4150b2c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30483
40693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.3048340693
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.391067945
Short name T1729
Test name
Test status
Simulation time 161143074 ps
CPU time 0.8 seconds
Started Jun 26 05:16:59 PM PDT 24
Finished Jun 26 05:17:02 PM PDT 24
Peak memory 206448 kb
Host smart-88ad812d-ef50-4e4a-9926-64180a0df218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39106
7945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.391067945
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.1074950694
Short name T1780
Test name
Test status
Simulation time 238947161 ps
CPU time 1.04 seconds
Started Jun 26 05:16:54 PM PDT 24
Finished Jun 26 05:16:59 PM PDT 24
Peak memory 206196 kb
Host smart-17a33220-0546-450c-a062-dcd8dd69680b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1074950694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.1074950694
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.2068894441
Short name T1092
Test name
Test status
Simulation time 152178197 ps
CPU time 0.73 seconds
Started Jun 26 05:16:54 PM PDT 24
Finished Jun 26 05:16:58 PM PDT 24
Peak memory 206112 kb
Host smart-2cc90a7b-54ed-4f41-ba78-ad5cd308b05a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20688
94441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.2068894441
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.120315967
Short name T1368
Test name
Test status
Simulation time 34278772 ps
CPU time 0.67 seconds
Started Jun 26 05:17:01 PM PDT 24
Finished Jun 26 05:17:05 PM PDT 24
Peak memory 206196 kb
Host smart-ecb8016c-c90c-4b65-8a6e-8d0969617864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12031
5967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.120315967
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.551158513
Short name T2019
Test name
Test status
Simulation time 7238240371 ps
CPU time 17.9 seconds
Started Jun 26 05:16:54 PM PDT 24
Finished Jun 26 05:17:15 PM PDT 24
Peak memory 206744 kb
Host smart-0a2373dd-9213-4b0c-9354-1666553ec96d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55115
8513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.551158513
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.352152744
Short name T1582
Test name
Test status
Simulation time 178112816 ps
CPU time 0.85 seconds
Started Jun 26 05:16:53 PM PDT 24
Finished Jun 26 05:16:58 PM PDT 24
Peak memory 206192 kb
Host smart-72db07b1-d3a6-47e0-a2bb-9fce47fd8ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35215
2744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.352152744
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.3483649194
Short name T1622
Test name
Test status
Simulation time 198742871 ps
CPU time 0.89 seconds
Started Jun 26 05:16:56 PM PDT 24
Finished Jun 26 05:17:01 PM PDT 24
Peak memory 206188 kb
Host smart-06d92062-2ab5-4d9d-b147-ac78c33d7ef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34836
49194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.3483649194
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.1911429292
Short name T529
Test name
Test status
Simulation time 191820451 ps
CPU time 0.83 seconds
Started Jun 26 05:16:59 PM PDT 24
Finished Jun 26 05:17:03 PM PDT 24
Peak memory 206200 kb
Host smart-3c161106-89b0-4081-b273-5a1de8e2ee4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19114
29292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.1911429292
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.936139939
Short name T674
Test name
Test status
Simulation time 182475245 ps
CPU time 0.83 seconds
Started Jun 26 05:16:55 PM PDT 24
Finished Jun 26 05:16:59 PM PDT 24
Peak memory 206116 kb
Host smart-f87fffa3-6c2b-4256-8b1b-4e5b8bfcc4d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93613
9939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.936139939
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.912517530
Short name T949
Test name
Test status
Simulation time 138604905 ps
CPU time 0.78 seconds
Started Jun 26 05:16:54 PM PDT 24
Finished Jun 26 05:16:58 PM PDT 24
Peak memory 206120 kb
Host smart-48445729-5810-4d98-8fda-fe06179b10c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91251
7530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.912517530
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.105683035
Short name T359
Test name
Test status
Simulation time 149988204 ps
CPU time 0.77 seconds
Started Jun 26 05:17:00 PM PDT 24
Finished Jun 26 05:17:04 PM PDT 24
Peak memory 206080 kb
Host smart-41795c0c-fc16-4148-aaf9-830b23acef9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10568
3035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.105683035
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.3443092124
Short name T462
Test name
Test status
Simulation time 155856396 ps
CPU time 0.76 seconds
Started Jun 26 05:16:59 PM PDT 24
Finished Jun 26 05:17:03 PM PDT 24
Peak memory 206148 kb
Host smart-4d621542-2cc1-42ed-b84a-580da76faf78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34430
92124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.3443092124
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.705479346
Short name T1967
Test name
Test status
Simulation time 234426989 ps
CPU time 0.96 seconds
Started Jun 26 05:16:53 PM PDT 24
Finished Jun 26 05:16:57 PM PDT 24
Peak memory 206188 kb
Host smart-6e5c019b-ae2a-4aaa-8c86-96a7e20eb413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70547
9346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.705479346
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.2998394613
Short name T2274
Test name
Test status
Simulation time 4615384374 ps
CPU time 121.99 seconds
Started Jun 26 05:16:58 PM PDT 24
Finished Jun 26 05:19:03 PM PDT 24
Peak memory 206400 kb
Host smart-a8dc4ebb-7a81-4f68-b9f4-625b00db903c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2998394613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.2998394613
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.226303658
Short name T1000
Test name
Test status
Simulation time 160408169 ps
CPU time 0.8 seconds
Started Jun 26 05:16:59 PM PDT 24
Finished Jun 26 05:17:03 PM PDT 24
Peak memory 206196 kb
Host smart-f78ad4af-94e3-4eb2-8014-196f460ee166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22630
3658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.226303658
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.3036262967
Short name T1365
Test name
Test status
Simulation time 200171043 ps
CPU time 0.91 seconds
Started Jun 26 05:16:53 PM PDT 24
Finished Jun 26 05:16:57 PM PDT 24
Peak memory 206204 kb
Host smart-afa6d629-71c3-43af-9137-0c4ddbff05a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30362
62967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.3036262967
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.2880441676
Short name T2319
Test name
Test status
Simulation time 2999086727 ps
CPU time 78.08 seconds
Started Jun 26 05:16:53 PM PDT 24
Finished Jun 26 05:18:14 PM PDT 24
Peak memory 206436 kb
Host smart-963b8520-b342-47cd-958e-4da543ec06ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28804
41676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.2880441676
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.282127630
Short name T791
Test name
Test status
Simulation time 3850409167 ps
CPU time 4.53 seconds
Started Jun 26 05:17:00 PM PDT 24
Finished Jun 26 05:17:09 PM PDT 24
Peak memory 206464 kb
Host smart-ae6b68ca-37f1-4e2c-b988-cf48a3862605
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=282127630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.282127630
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.296445178
Short name T948
Test name
Test status
Simulation time 13373529883 ps
CPU time 14.52 seconds
Started Jun 26 05:17:00 PM PDT 24
Finished Jun 26 05:17:17 PM PDT 24
Peak memory 206328 kb
Host smart-88d8540a-102f-4110-a190-860a53a6ac4f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=296445178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.296445178
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.3774433413
Short name T2441
Test name
Test status
Simulation time 156089239 ps
CPU time 0.82 seconds
Started Jun 26 05:17:04 PM PDT 24
Finished Jun 26 05:17:08 PM PDT 24
Peak memory 206028 kb
Host smart-bec50041-60b6-4ac3-be5b-31be43ccc9f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37744
33413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.3774433413
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.567886328
Short name T2464
Test name
Test status
Simulation time 193007079 ps
CPU time 0.8 seconds
Started Jun 26 05:16:59 PM PDT 24
Finished Jun 26 05:17:03 PM PDT 24
Peak memory 206188 kb
Host smart-e4a16ba5-caa8-4585-bdff-47e740562449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56788
6328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.567886328
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.2173451038
Short name T855
Test name
Test status
Simulation time 367151775 ps
CPU time 1.19 seconds
Started Jun 26 05:17:04 PM PDT 24
Finished Jun 26 05:17:09 PM PDT 24
Peak memory 206028 kb
Host smart-a0442cb4-f3a2-4169-816b-592a7b1fe167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21734
51038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.2173451038
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.1753587221
Short name T2395
Test name
Test status
Simulation time 1211206556 ps
CPU time 2.67 seconds
Started Jun 26 05:17:02 PM PDT 24
Finished Jun 26 05:17:09 PM PDT 24
Peak memory 206376 kb
Host smart-6ae34a43-2975-449c-950c-14411752ea38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17535
87221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.1753587221
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.1839014603
Short name T1146
Test name
Test status
Simulation time 433554460 ps
CPU time 1.31 seconds
Started Jun 26 05:17:03 PM PDT 24
Finished Jun 26 05:17:08 PM PDT 24
Peak memory 206100 kb
Host smart-7e28cbb3-b892-431e-a46b-2748c90ba26f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18390
14603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.1839014603
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.3346671145
Short name T1974
Test name
Test status
Simulation time 173350818 ps
CPU time 0.77 seconds
Started Jun 26 05:17:00 PM PDT 24
Finished Jun 26 05:17:05 PM PDT 24
Peak memory 206120 kb
Host smart-28e7f11f-41eb-4df6-bce2-9912edf8a3fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33466
71145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.3346671145
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.3270856277
Short name T1819
Test name
Test status
Simulation time 46843307 ps
CPU time 0.67 seconds
Started Jun 26 05:17:02 PM PDT 24
Finished Jun 26 05:17:07 PM PDT 24
Peak memory 206240 kb
Host smart-9ee8aadc-d56e-4d32-8f8b-127c407c24d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32708
56277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.3270856277
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.3223449740
Short name T2442
Test name
Test status
Simulation time 976616172 ps
CPU time 2.3 seconds
Started Jun 26 05:17:04 PM PDT 24
Finished Jun 26 05:17:10 PM PDT 24
Peak memory 206352 kb
Host smart-eb8dbe3d-e557-483e-8b94-e2bbfa6d77af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32234
49740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.3223449740
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.3520077318
Short name T1645
Test name
Test status
Simulation time 339238270 ps
CPU time 2.16 seconds
Started Jun 26 05:17:02 PM PDT 24
Finished Jun 26 05:17:08 PM PDT 24
Peak memory 206476 kb
Host smart-7cbe8521-914a-4d78-bdc8-6affa59b49e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35200
77318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.3520077318
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.3488660465
Short name T2273
Test name
Test status
Simulation time 234888579 ps
CPU time 0.85 seconds
Started Jun 26 05:17:08 PM PDT 24
Finished Jun 26 05:17:12 PM PDT 24
Peak memory 206176 kb
Host smart-684dc8cf-ab0a-48b2-8ef9-3dc35e7c2ab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34886
60465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.3488660465
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.1078748858
Short name T1873
Test name
Test status
Simulation time 153244517 ps
CPU time 0.79 seconds
Started Jun 26 05:17:09 PM PDT 24
Finished Jun 26 05:17:13 PM PDT 24
Peak memory 206400 kb
Host smart-764447f2-8ed9-4051-ab2a-b8579daa78e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10787
48858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.1078748858
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.3063275114
Short name T1489
Test name
Test status
Simulation time 223976044 ps
CPU time 0.92 seconds
Started Jun 26 05:17:03 PM PDT 24
Finished Jun 26 05:17:08 PM PDT 24
Peak memory 205336 kb
Host smart-760001f4-ba95-40c0-9aac-353a5067e64c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30632
75114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.3063275114
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_invalid_sync.1666676624
Short name T69
Test name
Test status
Simulation time 6696761455 ps
CPU time 63.38 seconds
Started Jun 26 05:17:03 PM PDT 24
Finished Jun 26 05:18:10 PM PDT 24
Peak memory 205684 kb
Host smart-a57b829d-89b8-424b-bda7-d72d68f54138
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1666676624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.1666676624
Directory /workspace/22.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.1851573986
Short name T2435
Test name
Test status
Simulation time 235312370 ps
CPU time 0.9 seconds
Started Jun 26 05:17:02 PM PDT 24
Finished Jun 26 05:17:07 PM PDT 24
Peak memory 206172 kb
Host smart-4e153962-26f6-44cf-bb45-e8432ad2c891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18515
73986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.1851573986
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.3091539482
Short name T2370
Test name
Test status
Simulation time 23322614291 ps
CPU time 21.32 seconds
Started Jun 26 05:17:01 PM PDT 24
Finished Jun 26 05:17:27 PM PDT 24
Peak memory 206240 kb
Host smart-79715ed6-fdd9-4791-8ea6-8f9a6ff33bd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30915
39482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.3091539482
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.1000988426
Short name T970
Test name
Test status
Simulation time 3303085969 ps
CPU time 4.29 seconds
Started Jun 26 05:17:04 PM PDT 24
Finished Jun 26 05:17:12 PM PDT 24
Peak memory 206232 kb
Host smart-28b1c6f5-020b-4966-83f9-70d25a54c9e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10009
88426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.1000988426
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.2740844879
Short name T1507
Test name
Test status
Simulation time 8333213986 ps
CPU time 76.55 seconds
Started Jun 26 05:17:09 PM PDT 24
Finished Jun 26 05:18:29 PM PDT 24
Peak memory 206500 kb
Host smart-36886cc6-1ef2-47ff-af91-0e52142a54ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27408
44879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.2740844879
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.3322749089
Short name T456
Test name
Test status
Simulation time 5754804925 ps
CPU time 162.4 seconds
Started Jun 26 05:17:09 PM PDT 24
Finished Jun 26 05:19:55 PM PDT 24
Peak memory 206504 kb
Host smart-e4c47fcc-5629-4d97-a9a9-77fcf51d7dea
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3322749089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.3322749089
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.3782181340
Short name T1640
Test name
Test status
Simulation time 255977622 ps
CPU time 0.94 seconds
Started Jun 26 05:17:11 PM PDT 24
Finished Jun 26 05:17:15 PM PDT 24
Peak memory 206192 kb
Host smart-af38a080-40fe-43a0-8546-82da0ecf4184
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3782181340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.3782181340
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.1653753945
Short name T1130
Test name
Test status
Simulation time 202363141 ps
CPU time 0.93 seconds
Started Jun 26 05:17:10 PM PDT 24
Finished Jun 26 05:17:14 PM PDT 24
Peak memory 206448 kb
Host smart-85cf385c-12e8-4dc4-ad94-e3fcf0aaa074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16537
53945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.1653753945
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.1703423047
Short name T637
Test name
Test status
Simulation time 6810144903 ps
CPU time 187.94 seconds
Started Jun 26 05:17:08 PM PDT 24
Finished Jun 26 05:20:19 PM PDT 24
Peak memory 206532 kb
Host smart-ea789e33-3c75-4eb1-a716-f767fca4ad7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17034
23047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.1703423047
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.2729198147
Short name T726
Test name
Test status
Simulation time 4843386080 ps
CPU time 44.95 seconds
Started Jun 26 05:17:08 PM PDT 24
Finished Jun 26 05:17:55 PM PDT 24
Peak memory 206480 kb
Host smart-6c98d9aa-f701-450b-8e55-acaf4a459556
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2729198147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.2729198147
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.2059594855
Short name T1375
Test name
Test status
Simulation time 180540969 ps
CPU time 0.81 seconds
Started Jun 26 05:17:09 PM PDT 24
Finished Jun 26 05:17:13 PM PDT 24
Peak memory 206200 kb
Host smart-a8f932c4-6817-416a-87a9-beee5562e984
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2059594855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.2059594855
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.1784119481
Short name T1822
Test name
Test status
Simulation time 164573494 ps
CPU time 0.83 seconds
Started Jun 26 05:17:08 PM PDT 24
Finished Jun 26 05:17:12 PM PDT 24
Peak memory 206216 kb
Host smart-b790f39e-0eb7-481c-a991-6b4c2668b9d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17841
19481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.1784119481
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.1610441259
Short name T140
Test name
Test status
Simulation time 214933712 ps
CPU time 0.93 seconds
Started Jun 26 05:17:07 PM PDT 24
Finished Jun 26 05:17:11 PM PDT 24
Peak memory 206176 kb
Host smart-8fdd638b-12d8-4916-b2ca-1b45dba4f4dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16104
41259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.1610441259
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.3916230998
Short name T1242
Test name
Test status
Simulation time 155955083 ps
CPU time 0.82 seconds
Started Jun 26 05:17:08 PM PDT 24
Finished Jun 26 05:17:12 PM PDT 24
Peak memory 206396 kb
Host smart-17a9d20c-b2c3-4fd7-80e2-647caebc6a20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39162
30998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.3916230998
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.3626462100
Short name T700
Test name
Test status
Simulation time 183707947 ps
CPU time 0.83 seconds
Started Jun 26 05:17:08 PM PDT 24
Finished Jun 26 05:17:12 PM PDT 24
Peak memory 206176 kb
Host smart-d04c2cc9-efa2-493c-8e64-bca0e67f85fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36264
62100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.3626462100
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.1419787363
Short name T703
Test name
Test status
Simulation time 151482657 ps
CPU time 0.79 seconds
Started Jun 26 05:17:07 PM PDT 24
Finished Jun 26 05:17:10 PM PDT 24
Peak memory 206168 kb
Host smart-29bde6a9-50d2-49fe-bfe4-4257a244a746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14197
87363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.1419787363
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.754935039
Short name T1432
Test name
Test status
Simulation time 184061003 ps
CPU time 0.89 seconds
Started Jun 26 05:17:09 PM PDT 24
Finished Jun 26 05:17:13 PM PDT 24
Peak memory 206188 kb
Host smart-482ce346-0dc8-48eb-9d05-065cb48a9566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75493
5039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.754935039
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.2760272155
Short name T1533
Test name
Test status
Simulation time 223818839 ps
CPU time 0.93 seconds
Started Jun 26 05:17:11 PM PDT 24
Finished Jun 26 05:17:15 PM PDT 24
Peak memory 206192 kb
Host smart-c9db40f3-8b12-4555-b304-336e368fa050
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2760272155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.2760272155
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.3368085718
Short name T2368
Test name
Test status
Simulation time 144754241 ps
CPU time 0.75 seconds
Started Jun 26 05:17:05 PM PDT 24
Finished Jun 26 05:17:09 PM PDT 24
Peak memory 206208 kb
Host smart-42f9e88f-9617-43bd-a154-66d4c1217c93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33680
85718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.3368085718
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.4076224923
Short name T30
Test name
Test status
Simulation time 34145997 ps
CPU time 0.64 seconds
Started Jun 26 05:17:08 PM PDT 24
Finished Jun 26 05:17:12 PM PDT 24
Peak memory 206196 kb
Host smart-3dda01d4-6ea5-4c58-8b7d-5981301d6a40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40762
24923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.4076224923
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.1555945262
Short name T1796
Test name
Test status
Simulation time 6133063771 ps
CPU time 15.83 seconds
Started Jun 26 05:17:09 PM PDT 24
Finished Jun 26 05:17:28 PM PDT 24
Peak memory 206536 kb
Host smart-42b824cc-eb90-49f8-82b9-52c32bb010fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15559
45262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.1555945262
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.1310097604
Short name T1291
Test name
Test status
Simulation time 192277572 ps
CPU time 0.81 seconds
Started Jun 26 05:17:09 PM PDT 24
Finished Jun 26 05:17:13 PM PDT 24
Peak memory 206116 kb
Host smart-7fac88f2-f0c9-457d-a8a7-33953708b09b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13100
97604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.1310097604
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.3505691317
Short name T565
Test name
Test status
Simulation time 211012456 ps
CPU time 0.84 seconds
Started Jun 26 05:17:07 PM PDT 24
Finished Jun 26 05:17:11 PM PDT 24
Peak memory 206224 kb
Host smart-b4f5ce40-a5df-4556-855d-6fe92b67cd7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35056
91317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.3505691317
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.491687668
Short name T699
Test name
Test status
Simulation time 191943322 ps
CPU time 0.88 seconds
Started Jun 26 05:17:06 PM PDT 24
Finished Jun 26 05:17:10 PM PDT 24
Peak memory 206132 kb
Host smart-286dff6a-d693-445f-a8ac-1a9c856eefa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49168
7668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.491687668
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.3421017564
Short name T1693
Test name
Test status
Simulation time 202790594 ps
CPU time 0.87 seconds
Started Jun 26 05:17:06 PM PDT 24
Finished Jun 26 05:17:09 PM PDT 24
Peak memory 206144 kb
Host smart-3809e438-d595-42fc-b71c-77cd5071ea25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34210
17564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.3421017564
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.557090409
Short name T787
Test name
Test status
Simulation time 139709968 ps
CPU time 0.78 seconds
Started Jun 26 05:17:09 PM PDT 24
Finished Jun 26 05:17:13 PM PDT 24
Peak memory 206164 kb
Host smart-0f410c84-9259-44ca-a38f-95329c82b975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55709
0409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.557090409
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.4042180073
Short name T1282
Test name
Test status
Simulation time 152327774 ps
CPU time 0.8 seconds
Started Jun 26 05:17:05 PM PDT 24
Finished Jun 26 05:17:09 PM PDT 24
Peak memory 206204 kb
Host smart-c3531116-19ec-4442-8504-a7901e9f11a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40421
80073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.4042180073
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.3820633990
Short name T458
Test name
Test status
Simulation time 147658274 ps
CPU time 0.77 seconds
Started Jun 26 05:17:08 PM PDT 24
Finished Jun 26 05:17:12 PM PDT 24
Peak memory 206224 kb
Host smart-e2d6cf58-36da-4e91-b41b-6c7d22d66061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38206
33990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.3820633990
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.3251417647
Short name T894
Test name
Test status
Simulation time 238275659 ps
CPU time 0.94 seconds
Started Jun 26 05:17:06 PM PDT 24
Finished Jun 26 05:17:10 PM PDT 24
Peak memory 206204 kb
Host smart-2eaa1ca1-950e-47fe-87e1-c759eb78fee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32514
17647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.3251417647
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.1858663879
Short name T1377
Test name
Test status
Simulation time 5174108865 ps
CPU time 132.08 seconds
Started Jun 26 05:17:08 PM PDT 24
Finished Jun 26 05:19:22 PM PDT 24
Peak memory 206504 kb
Host smart-1bdd8020-3c4a-4150-9f4d-43a7d32dd648
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1858663879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.1858663879
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.2048745320
Short name T2156
Test name
Test status
Simulation time 183180750 ps
CPU time 0.82 seconds
Started Jun 26 05:17:07 PM PDT 24
Finished Jun 26 05:17:11 PM PDT 24
Peak memory 206200 kb
Host smart-7d0fe8f3-820b-4e8f-b692-53f802712c6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20487
45320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.2048745320
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.872219007
Short name T2359
Test name
Test status
Simulation time 145495555 ps
CPU time 0.77 seconds
Started Jun 26 05:17:08 PM PDT 24
Finished Jun 26 05:17:11 PM PDT 24
Peak memory 206080 kb
Host smart-a309f4d3-957b-409e-8642-8943e254bba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87221
9007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.872219007
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.259241734
Short name T343
Test name
Test status
Simulation time 7501289668 ps
CPU time 71.91 seconds
Started Jun 26 05:17:08 PM PDT 24
Finished Jun 26 05:18:23 PM PDT 24
Peak memory 206500 kb
Host smart-0bcf01eb-6df6-41ba-b0e1-773c26e5a83f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25924
1734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.259241734
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.3475869377
Short name T2490
Test name
Test status
Simulation time 4155499509 ps
CPU time 4.88 seconds
Started Jun 26 05:17:12 PM PDT 24
Finished Jun 26 05:17:20 PM PDT 24
Peak memory 206200 kb
Host smart-572e64a8-a1dd-4741-b0f7-80a1e7c1cc1a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3475869377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.3475869377
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.2611958840
Short name T675
Test name
Test status
Simulation time 13397573940 ps
CPU time 12.5 seconds
Started Jun 26 05:17:17 PM PDT 24
Finished Jun 26 05:17:36 PM PDT 24
Peak memory 206516 kb
Host smart-0a10dd7b-df0b-476d-9255-724fbb909458
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2611958840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.2611958840
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.248926990
Short name T447
Test name
Test status
Simulation time 23369722788 ps
CPU time 23.68 seconds
Started Jun 26 05:17:13 PM PDT 24
Finished Jun 26 05:17:40 PM PDT 24
Peak memory 206244 kb
Host smart-2ab5b300-5b86-4005-af49-87af3b68b6e4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=248926990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.248926990
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.2485199764
Short name T1123
Test name
Test status
Simulation time 212513413 ps
CPU time 0.85 seconds
Started Jun 26 05:17:15 PM PDT 24
Finished Jun 26 05:17:20 PM PDT 24
Peak memory 206208 kb
Host smart-eaa24e47-a02b-4cf6-a3c2-b77656f3e3ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24851
99764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.2485199764
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.2790182069
Short name T494
Test name
Test status
Simulation time 145299907 ps
CPU time 0.81 seconds
Started Jun 26 05:17:12 PM PDT 24
Finished Jun 26 05:17:16 PM PDT 24
Peak memory 206176 kb
Host smart-0cab9043-5ac8-4b9d-bd09-51942b7c5a13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27901
82069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.2790182069
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.915949825
Short name T852
Test name
Test status
Simulation time 399778401 ps
CPU time 1.27 seconds
Started Jun 26 05:17:13 PM PDT 24
Finished Jun 26 05:17:18 PM PDT 24
Peak memory 206212 kb
Host smart-2eab6e85-9fae-404d-bed1-5c3bbf591e10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91594
9825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.915949825
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.4215435919
Short name T2212
Test name
Test status
Simulation time 369860329 ps
CPU time 1.05 seconds
Started Jun 26 05:17:12 PM PDT 24
Finished Jun 26 05:17:16 PM PDT 24
Peak memory 206124 kb
Host smart-c0a16e8d-bbbb-4b78-bb90-93bb8a055292
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42154
35919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.4215435919
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.913794243
Short name T1038
Test name
Test status
Simulation time 19521756830 ps
CPU time 36.72 seconds
Started Jun 26 05:17:12 PM PDT 24
Finished Jun 26 05:17:51 PM PDT 24
Peak memory 206544 kb
Host smart-79c1e98e-4805-48d6-99fe-e23ab26d9869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91379
4243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.913794243
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.88096152
Short name T2538
Test name
Test status
Simulation time 421841503 ps
CPU time 1.47 seconds
Started Jun 26 05:17:13 PM PDT 24
Finished Jun 26 05:17:18 PM PDT 24
Peak memory 206200 kb
Host smart-40f4edd7-8c8b-498c-8f55-109e463ff182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88096
152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.88096152
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.1491019510
Short name T816
Test name
Test status
Simulation time 154662797 ps
CPU time 0.8 seconds
Started Jun 26 05:17:15 PM PDT 24
Finished Jun 26 05:17:22 PM PDT 24
Peak memory 206184 kb
Host smart-458a70b3-a255-4b4d-8fcf-15739cc3097d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14910
19510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.1491019510
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.3417179861
Short name T384
Test name
Test status
Simulation time 53297166 ps
CPU time 0.69 seconds
Started Jun 26 05:17:12 PM PDT 24
Finished Jun 26 05:17:15 PM PDT 24
Peak memory 206188 kb
Host smart-95464f3e-d59f-4b2c-9215-639176719f44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34171
79861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.3417179861
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.3964003754
Short name T1961
Test name
Test status
Simulation time 932564452 ps
CPU time 2.05 seconds
Started Jun 26 05:17:13 PM PDT 24
Finished Jun 26 05:17:18 PM PDT 24
Peak memory 206444 kb
Host smart-244430f1-bee0-4f9d-8e53-373395de401a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39640
03754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.3964003754
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.2604795523
Short name T460
Test name
Test status
Simulation time 194785867 ps
CPU time 1.52 seconds
Started Jun 26 05:17:14 PM PDT 24
Finished Jun 26 05:17:20 PM PDT 24
Peak memory 206472 kb
Host smart-627a83d8-2feb-4b88-84a7-692df1f87237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26047
95523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.2604795523
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.3258577998
Short name T114
Test name
Test status
Simulation time 163603906 ps
CPU time 0.77 seconds
Started Jun 26 05:17:25 PM PDT 24
Finished Jun 26 05:17:31 PM PDT 24
Peak memory 206132 kb
Host smart-dcc2f2dc-1efa-41dc-88d7-403de838d09d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32585
77998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.3258577998
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.4093574287
Short name T2525
Test name
Test status
Simulation time 165796965 ps
CPU time 0.76 seconds
Started Jun 26 05:17:24 PM PDT 24
Finished Jun 26 05:17:31 PM PDT 24
Peak memory 206192 kb
Host smart-ed0a10ae-e634-4bc7-8928-33d583c7e0a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40935
74287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.4093574287
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.2193262336
Short name T345
Test name
Test status
Simulation time 234749428 ps
CPU time 0.93 seconds
Started Jun 26 05:17:12 PM PDT 24
Finished Jun 26 05:17:17 PM PDT 24
Peak memory 206440 kb
Host smart-086f4a72-02d5-40b3-9935-43f937e79cd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21932
62336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.2193262336
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_invalid_sync.182465143
Short name T2022
Test name
Test status
Simulation time 5772237541 ps
CPU time 155.85 seconds
Started Jun 26 05:17:15 PM PDT 24
Finished Jun 26 05:19:55 PM PDT 24
Peak memory 206428 kb
Host smart-8831db5f-1de8-451e-bed0-8f5ac63149a0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=182465143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.182465143
Directory /workspace/23.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.2549647564
Short name T1336
Test name
Test status
Simulation time 172198389 ps
CPU time 0.83 seconds
Started Jun 26 05:17:17 PM PDT 24
Finished Jun 26 05:17:24 PM PDT 24
Peak memory 206120 kb
Host smart-b10adbb9-1192-4a72-a26b-9ef8f5895032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25496
47564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.2549647564
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.4284317338
Short name T2053
Test name
Test status
Simulation time 23354305435 ps
CPU time 23.95 seconds
Started Jun 26 05:17:14 PM PDT 24
Finished Jun 26 05:17:42 PM PDT 24
Peak memory 206236 kb
Host smart-7ee08a24-b051-49fe-b11d-a84073c06076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42843
17338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.4284317338
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.2339663104
Short name T823
Test name
Test status
Simulation time 3275246242 ps
CPU time 3.35 seconds
Started Jun 26 05:17:16 PM PDT 24
Finished Jun 26 05:17:25 PM PDT 24
Peak memory 206224 kb
Host smart-b91c085a-51da-49b8-9626-aba263bfc0ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23396
63104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.2339663104
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.712713641
Short name T1591
Test name
Test status
Simulation time 7594331616 ps
CPU time 52.29 seconds
Started Jun 26 05:17:14 PM PDT 24
Finished Jun 26 05:18:11 PM PDT 24
Peak memory 206512 kb
Host smart-93e769f2-4edd-45fb-9e69-3d105b891605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71271
3641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.712713641
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.3045070202
Short name T338
Test name
Test status
Simulation time 4062848387 ps
CPU time 26.75 seconds
Started Jun 26 05:17:11 PM PDT 24
Finished Jun 26 05:17:41 PM PDT 24
Peak memory 206476 kb
Host smart-a118bcee-4448-4fba-8e21-37ed1d0547f0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3045070202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.3045070202
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.3423724182
Short name T1886
Test name
Test status
Simulation time 247300027 ps
CPU time 0.95 seconds
Started Jun 26 05:17:25 PM PDT 24
Finished Jun 26 05:17:32 PM PDT 24
Peak memory 206144 kb
Host smart-8453dd3e-b519-40c9-8e75-19cd000d6127
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3423724182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.3423724182
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.3521947580
Short name T378
Test name
Test status
Simulation time 210222759 ps
CPU time 0.94 seconds
Started Jun 26 05:17:17 PM PDT 24
Finished Jun 26 05:17:24 PM PDT 24
Peak memory 206128 kb
Host smart-c12331bd-ba38-4e27-8487-078063da7b6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35219
47580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.3521947580
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.2230878344
Short name T1156
Test name
Test status
Simulation time 5554415166 ps
CPU time 50.91 seconds
Started Jun 26 05:17:15 PM PDT 24
Finished Jun 26 05:18:12 PM PDT 24
Peak memory 206584 kb
Host smart-a93427ce-07d7-4728-9029-40f86c4d4583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22308
78344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.2230878344
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.851325750
Short name T411
Test name
Test status
Simulation time 5571895722 ps
CPU time 157.21 seconds
Started Jun 26 05:17:15 PM PDT 24
Finished Jun 26 05:19:58 PM PDT 24
Peak memory 206492 kb
Host smart-31620f8b-b43e-49c3-a467-3bd3f650fb54
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=851325750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.851325750
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.3548650962
Short name T401
Test name
Test status
Simulation time 172490105 ps
CPU time 0.78 seconds
Started Jun 26 05:17:25 PM PDT 24
Finished Jun 26 05:17:31 PM PDT 24
Peak memory 206144 kb
Host smart-39547331-173e-4fa0-99ef-4499c226b7e5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3548650962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.3548650962
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.3510969675
Short name T1625
Test name
Test status
Simulation time 163658276 ps
CPU time 0.76 seconds
Started Jun 26 05:17:15 PM PDT 24
Finished Jun 26 05:17:22 PM PDT 24
Peak memory 206212 kb
Host smart-c8254f95-6731-44df-a853-a839bc4ca805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35109
69675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.3510969675
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.483481652
Short name T123
Test name
Test status
Simulation time 227171923 ps
CPU time 0.86 seconds
Started Jun 26 05:17:16 PM PDT 24
Finished Jun 26 05:17:23 PM PDT 24
Peak memory 206140 kb
Host smart-2e920c27-749a-4c41-a0fa-b8ad620467ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48348
1652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.483481652
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.1386155463
Short name T509
Test name
Test status
Simulation time 162073566 ps
CPU time 0.77 seconds
Started Jun 26 05:17:14 PM PDT 24
Finished Jun 26 05:17:19 PM PDT 24
Peak memory 206216 kb
Host smart-d4666f44-2cd2-4143-bbf5-881a25abe707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13861
55463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.1386155463
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.3559783212
Short name T1759
Test name
Test status
Simulation time 168090172 ps
CPU time 0.79 seconds
Started Jun 26 05:17:17 PM PDT 24
Finished Jun 26 05:17:24 PM PDT 24
Peak memory 206212 kb
Host smart-7f6f6773-716f-4f03-8595-6bee818bdb21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35597
83212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.3559783212
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.1987885361
Short name T626
Test name
Test status
Simulation time 147179534 ps
CPU time 0.77 seconds
Started Jun 26 05:17:19 PM PDT 24
Finished Jun 26 05:17:25 PM PDT 24
Peak memory 206112 kb
Host smart-885e6fdb-4c1f-45d0-9aae-4c5ac335fcdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19878
85361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.1987885361
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.3757966242
Short name T881
Test name
Test status
Simulation time 160989931 ps
CPU time 0.76 seconds
Started Jun 26 05:17:20 PM PDT 24
Finished Jun 26 05:17:26 PM PDT 24
Peak memory 206212 kb
Host smart-1080f821-c6d4-43a3-95e0-487ebdbe4f62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37579
66242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.3757966242
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.552461117
Short name T961
Test name
Test status
Simulation time 254130958 ps
CPU time 0.98 seconds
Started Jun 26 05:17:23 PM PDT 24
Finished Jun 26 05:17:30 PM PDT 24
Peak memory 206208 kb
Host smart-1bd0f09e-d2b6-459d-8054-d58481906713
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=552461117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.552461117
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.1193849491
Short name T2528
Test name
Test status
Simulation time 181138666 ps
CPU time 0.83 seconds
Started Jun 26 05:17:20 PM PDT 24
Finished Jun 26 05:17:26 PM PDT 24
Peak memory 206096 kb
Host smart-4cc764f3-5e44-43d1-a17e-1e4581f57988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11938
49491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.1193849491
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.2571783933
Short name T1745
Test name
Test status
Simulation time 39158029 ps
CPU time 0.66 seconds
Started Jun 26 05:17:23 PM PDT 24
Finished Jun 26 05:17:30 PM PDT 24
Peak memory 206216 kb
Host smart-0cfb1e48-9afb-4e33-8b35-cc153d07a853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25717
83933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.2571783933
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.1965890301
Short name T1849
Test name
Test status
Simulation time 22980749797 ps
CPU time 55.36 seconds
Started Jun 26 05:17:21 PM PDT 24
Finished Jun 26 05:18:22 PM PDT 24
Peak memory 206592 kb
Host smart-40bf5915-222a-4747-abdc-560e42fed94b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19658
90301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.1965890301
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.2216933340
Short name T903
Test name
Test status
Simulation time 142611617 ps
CPU time 0.79 seconds
Started Jun 26 05:17:18 PM PDT 24
Finished Jun 26 05:17:25 PM PDT 24
Peak memory 206204 kb
Host smart-c74a8bda-d151-410c-a213-f0edffd608b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22169
33340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.2216933340
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.324474196
Short name T769
Test name
Test status
Simulation time 217091702 ps
CPU time 0.93 seconds
Started Jun 26 05:17:18 PM PDT 24
Finished Jun 26 05:17:25 PM PDT 24
Peak memory 206200 kb
Host smart-49f96d32-8405-45b6-8aef-87b776fe3e19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32447
4196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.324474196
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.719919398
Short name T1766
Test name
Test status
Simulation time 254270044 ps
CPU time 0.9 seconds
Started Jun 26 05:17:25 PM PDT 24
Finished Jun 26 05:17:31 PM PDT 24
Peak memory 206196 kb
Host smart-a7b047b9-78d1-459d-9fa1-ed5329aec000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71991
9398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.719919398
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.3101874295
Short name T878
Test name
Test status
Simulation time 177120129 ps
CPU time 0.83 seconds
Started Jun 26 05:17:19 PM PDT 24
Finished Jun 26 05:17:26 PM PDT 24
Peak memory 206212 kb
Host smart-697334b8-4f02-4199-93c2-3b3e3c75bb53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31018
74295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.3101874295
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.576286318
Short name T39
Test name
Test status
Simulation time 184588332 ps
CPU time 0.83 seconds
Started Jun 26 05:17:20 PM PDT 24
Finished Jun 26 05:17:26 PM PDT 24
Peak memory 206224 kb
Host smart-8894f4e2-5e90-40e0-93ee-3ca20f22a5ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57628
6318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.576286318
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.1775966248
Short name T1542
Test name
Test status
Simulation time 158319301 ps
CPU time 0.8 seconds
Started Jun 26 05:17:22 PM PDT 24
Finished Jun 26 05:17:29 PM PDT 24
Peak memory 206172 kb
Host smart-4f17fce2-6d3f-43b5-89b8-471cda784c77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17759
66248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.1775966248
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.81092098
Short name T1001
Test name
Test status
Simulation time 156919695 ps
CPU time 0.79 seconds
Started Jun 26 05:17:20 PM PDT 24
Finished Jun 26 05:17:26 PM PDT 24
Peak memory 206224 kb
Host smart-fb7fde00-4f6b-430c-b92b-eeb54c1e4c72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81092
098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.81092098
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.2465516041
Short name T1839
Test name
Test status
Simulation time 209681716 ps
CPU time 0.9 seconds
Started Jun 26 05:17:19 PM PDT 24
Finished Jun 26 05:17:26 PM PDT 24
Peak memory 206232 kb
Host smart-9beffaf1-4948-4b4b-b2c8-bd31ad4183bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24655
16041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.2465516041
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.3728166813
Short name T1058
Test name
Test status
Simulation time 4342821706 ps
CPU time 39.45 seconds
Started Jun 26 05:17:19 PM PDT 24
Finished Jun 26 05:18:04 PM PDT 24
Peak memory 206520 kb
Host smart-e5fe20d9-7fae-4b82-9130-b38d313ddebb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3728166813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.3728166813
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.3710731054
Short name T288
Test name
Test status
Simulation time 181296096 ps
CPU time 0.84 seconds
Started Jun 26 05:17:20 PM PDT 24
Finished Jun 26 05:17:27 PM PDT 24
Peak memory 206180 kb
Host smart-0e8f92d0-17c9-4ff7-8ee6-9dac6d1628dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37107
31054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.3710731054
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.3221893525
Short name T103
Test name
Test status
Simulation time 202390206 ps
CPU time 0.9 seconds
Started Jun 26 05:17:21 PM PDT 24
Finished Jun 26 05:17:28 PM PDT 24
Peak memory 206196 kb
Host smart-0e598e5b-0afb-4272-a1c6-ffc398fb10f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32218
93525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.3221893525
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.927190
Short name T2397
Test name
Test status
Simulation time 6051700944 ps
CPU time 44.72 seconds
Started Jun 26 05:17:20 PM PDT 24
Finished Jun 26 05:18:10 PM PDT 24
Peak memory 206588 kb
Host smart-ba36fede-48a3-44a7-beff-43bb15d0c3da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92719
0 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.927190
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.2423457958
Short name T1192
Test name
Test status
Simulation time 4175347996 ps
CPU time 5.1 seconds
Started Jun 26 05:17:29 PM PDT 24
Finished Jun 26 05:17:38 PM PDT 24
Peak memory 206216 kb
Host smart-24c1ef42-3d9b-4182-9a2d-331e3d7fe4bc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2423457958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.2423457958
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.2146727709
Short name T2530
Test name
Test status
Simulation time 13328141134 ps
CPU time 13.14 seconds
Started Jun 26 05:17:23 PM PDT 24
Finished Jun 26 05:17:43 PM PDT 24
Peak memory 206248 kb
Host smart-dea6be57-7429-4f88-aa91-eed053b783fc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2146727709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.2146727709
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.1657524599
Short name T2488
Test name
Test status
Simulation time 23371830249 ps
CPU time 23.86 seconds
Started Jun 26 05:17:27 PM PDT 24
Finished Jun 26 05:17:56 PM PDT 24
Peak memory 206336 kb
Host smart-bd0a1e21-599b-460c-8b0c-5dc3eca84244
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1657524599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.1657524599
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.1768766319
Short name T2237
Test name
Test status
Simulation time 149349213 ps
CPU time 0.8 seconds
Started Jun 26 05:17:25 PM PDT 24
Finished Jun 26 05:17:31 PM PDT 24
Peak memory 206176 kb
Host smart-1e626307-a61e-4f3d-be5f-406992392a52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17687
66319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.1768766319
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.3774812678
Short name T1701
Test name
Test status
Simulation time 164576839 ps
CPU time 0.79 seconds
Started Jun 26 05:17:27 PM PDT 24
Finished Jun 26 05:17:32 PM PDT 24
Peak memory 206212 kb
Host smart-27742972-a007-4224-896e-35773915839e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37748
12678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.3774812678
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.1866504654
Short name T2484
Test name
Test status
Simulation time 298020033 ps
CPU time 1.01 seconds
Started Jun 26 05:17:29 PM PDT 24
Finished Jun 26 05:17:33 PM PDT 24
Peak memory 206228 kb
Host smart-977e6e9c-1b46-494b-a814-a83bfa058e19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18665
04654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.1866504654
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.402037637
Short name T617
Test name
Test status
Simulation time 453141464 ps
CPU time 1.31 seconds
Started Jun 26 05:17:29 PM PDT 24
Finished Jun 26 05:17:34 PM PDT 24
Peak memory 205944 kb
Host smart-d8f1869d-b583-4367-8d5e-4c9dad6ad552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40203
7637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.402037637
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.399035055
Short name T1612
Test name
Test status
Simulation time 22743050488 ps
CPU time 46.91 seconds
Started Jun 26 05:17:26 PM PDT 24
Finished Jun 26 05:18:18 PM PDT 24
Peak memory 206512 kb
Host smart-39151bed-c8ba-4914-8fea-62fc53ab3069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39903
5055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.399035055
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.3906006440
Short name T2220
Test name
Test status
Simulation time 469760400 ps
CPU time 1.38 seconds
Started Jun 26 05:17:36 PM PDT 24
Finished Jun 26 05:17:43 PM PDT 24
Peak memory 206128 kb
Host smart-2716593a-97ff-4b45-912f-5fb25f80c2b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39060
06440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.3906006440
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.183754947
Short name T630
Test name
Test status
Simulation time 143622381 ps
CPU time 0.76 seconds
Started Jun 26 05:17:32 PM PDT 24
Finished Jun 26 05:17:36 PM PDT 24
Peak memory 206200 kb
Host smart-3bdda35a-940f-4dc4-a95b-269f68ad53a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18375
4947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.183754947
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.11936615
Short name T1049
Test name
Test status
Simulation time 45922621 ps
CPU time 0.67 seconds
Started Jun 26 05:17:31 PM PDT 24
Finished Jun 26 05:17:34 PM PDT 24
Peak memory 206180 kb
Host smart-c8106237-62e0-4dc9-8a64-e272752fe8f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11936
615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.11936615
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.704959792
Short name T1989
Test name
Test status
Simulation time 1011685400 ps
CPU time 2.17 seconds
Started Jun 26 05:17:37 PM PDT 24
Finished Jun 26 05:17:44 PM PDT 24
Peak memory 206332 kb
Host smart-822311a2-872e-4662-a24a-72525b37b210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70495
9792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.704959792
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.2090313753
Short name T889
Test name
Test status
Simulation time 259700447 ps
CPU time 1.49 seconds
Started Jun 26 05:17:36 PM PDT 24
Finished Jun 26 05:17:43 PM PDT 24
Peak memory 206340 kb
Host smart-ac552834-8f96-4df8-9df2-5b6dba168dfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20903
13753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.2090313753
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.1231206765
Short name T953
Test name
Test status
Simulation time 210097414 ps
CPU time 0.93 seconds
Started Jun 26 05:17:39 PM PDT 24
Finished Jun 26 05:17:45 PM PDT 24
Peak memory 206132 kb
Host smart-ff7418a4-9ae8-46a5-bf0a-5e1b074aded8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12312
06765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.1231206765
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.894235501
Short name T804
Test name
Test status
Simulation time 174444343 ps
CPU time 0.8 seconds
Started Jun 26 05:17:39 PM PDT 24
Finished Jun 26 05:17:44 PM PDT 24
Peak memory 206184 kb
Host smart-ba55b4ad-32b2-409d-b920-85d4c4c17fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89423
5501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.894235501
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.1568403060
Short name T1772
Test name
Test status
Simulation time 259246668 ps
CPU time 0.92 seconds
Started Jun 26 05:17:31 PM PDT 24
Finished Jun 26 05:17:35 PM PDT 24
Peak memory 206236 kb
Host smart-02f1d7b3-dea6-4d1c-860b-c60306d3fe97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15684
03060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.1568403060
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_invalid_sync.4196896185
Short name T2109
Test name
Test status
Simulation time 6937315451 ps
CPU time 197.99 seconds
Started Jun 26 05:17:32 PM PDT 24
Finished Jun 26 05:20:52 PM PDT 24
Peak memory 205664 kb
Host smart-95344c6a-d6a0-4276-acc0-ce13c5d1fd33
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4196896185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.4196896185
Directory /workspace/24.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.1393463080
Short name T2133
Test name
Test status
Simulation time 258288408 ps
CPU time 0.93 seconds
Started Jun 26 05:17:31 PM PDT 24
Finished Jun 26 05:17:35 PM PDT 24
Peak memory 206096 kb
Host smart-abe8e467-8998-4ea4-9de0-aab9ff204125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13934
63080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.1393463080
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.1713587064
Short name T429
Test name
Test status
Simulation time 23342186838 ps
CPU time 24.51 seconds
Started Jun 26 05:17:37 PM PDT 24
Finished Jun 26 05:18:06 PM PDT 24
Peak memory 206240 kb
Host smart-91b1d93e-798e-4821-ae88-d01fdefb127d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17135
87064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.1713587064
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.711448874
Short name T2084
Test name
Test status
Simulation time 3347588003 ps
CPU time 4.67 seconds
Started Jun 26 05:17:35 PM PDT 24
Finished Jun 26 05:17:44 PM PDT 24
Peak memory 206232 kb
Host smart-54ee7405-cf69-44df-8985-4274b54fb5d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71144
8874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.711448874
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.594031157
Short name T2234
Test name
Test status
Simulation time 8129143136 ps
CPU time 64.12 seconds
Started Jun 26 05:17:36 PM PDT 24
Finished Jun 26 05:18:45 PM PDT 24
Peak memory 206568 kb
Host smart-f19ef99a-f9b8-4e83-93d5-19e54d1fa433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59403
1157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.594031157
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.280224533
Short name T1129
Test name
Test status
Simulation time 5770828418 ps
CPU time 159.91 seconds
Started Jun 26 05:17:30 PM PDT 24
Finished Jun 26 05:20:13 PM PDT 24
Peak memory 206488 kb
Host smart-adfb952a-f150-4538-a3b4-a20d5c9d3ca0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=280224533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.280224533
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.408751940
Short name T1018
Test name
Test status
Simulation time 238176667 ps
CPU time 0.9 seconds
Started Jun 26 05:17:38 PM PDT 24
Finished Jun 26 05:17:44 PM PDT 24
Peak memory 206136 kb
Host smart-bf50f2a6-5945-4171-9911-562e7201872e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=408751940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.408751940
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.275370005
Short name T1076
Test name
Test status
Simulation time 197776182 ps
CPU time 0.89 seconds
Started Jun 26 05:17:36 PM PDT 24
Finished Jun 26 05:17:42 PM PDT 24
Peak memory 206216 kb
Host smart-c9ed50fc-2c36-41d6-865f-d1f6e71a3faf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27537
0005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.275370005
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.612299962
Short name T2496
Test name
Test status
Simulation time 4621108814 ps
CPU time 44.54 seconds
Started Jun 26 05:17:33 PM PDT 24
Finished Jun 26 05:18:21 PM PDT 24
Peak memory 206512 kb
Host smart-a5d0b106-8081-4449-8e64-097d84e2f49a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61229
9962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.612299962
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.3059846694
Short name T471
Test name
Test status
Simulation time 5789835245 ps
CPU time 45.45 seconds
Started Jun 26 05:17:32 PM PDT 24
Finished Jun 26 05:18:20 PM PDT 24
Peak memory 205848 kb
Host smart-e33b79ae-161f-4d03-8a91-c113a241e313
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3059846694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.3059846694
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.744928775
Short name T1016
Test name
Test status
Simulation time 147511362 ps
CPU time 0.79 seconds
Started Jun 26 05:17:39 PM PDT 24
Finished Jun 26 05:17:44 PM PDT 24
Peak memory 206248 kb
Host smart-a5d3dc20-55ba-4b36-bef8-56b29b2c4055
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=744928775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.744928775
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.1947385447
Short name T2225
Test name
Test status
Simulation time 171226662 ps
CPU time 0.8 seconds
Started Jun 26 05:17:31 PM PDT 24
Finished Jun 26 05:17:34 PM PDT 24
Peak memory 206136 kb
Host smart-aa906629-5b9b-451f-9a87-bb3175309473
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19473
85447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.1947385447
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.1506934099
Short name T2110
Test name
Test status
Simulation time 228981617 ps
CPU time 0.86 seconds
Started Jun 26 05:17:31 PM PDT 24
Finished Jun 26 05:17:35 PM PDT 24
Peak memory 206116 kb
Host smart-612a6905-e6ec-48eb-b46c-0846570bd96f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15069
34099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.1506934099
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.3863097474
Short name T1941
Test name
Test status
Simulation time 154660677 ps
CPU time 0.88 seconds
Started Jun 26 05:17:32 PM PDT 24
Finished Jun 26 05:17:35 PM PDT 24
Peak memory 206192 kb
Host smart-20d47da8-7250-4192-8439-7f8326532813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38630
97474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.3863097474
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.928946487
Short name T1131
Test name
Test status
Simulation time 211407979 ps
CPU time 0.86 seconds
Started Jun 26 05:17:36 PM PDT 24
Finished Jun 26 05:17:42 PM PDT 24
Peak memory 206124 kb
Host smart-6bd8a006-b380-4b37-8872-e2a4f49fa0b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92894
6487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.928946487
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.122968819
Short name T2162
Test name
Test status
Simulation time 145732583 ps
CPU time 0.75 seconds
Started Jun 26 05:17:31 PM PDT 24
Finished Jun 26 05:17:34 PM PDT 24
Peak memory 206120 kb
Host smart-f9acbc03-766d-42a5-8614-08508c1b4eae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12296
8819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.122968819
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.1134284827
Short name T1587
Test name
Test status
Simulation time 152332911 ps
CPU time 0.77 seconds
Started Jun 26 05:17:49 PM PDT 24
Finished Jun 26 05:17:52 PM PDT 24
Peak memory 206028 kb
Host smart-793bda5e-564a-4166-a3cf-fd72d22e7e2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11342
84827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.1134284827
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.544171698
Short name T664
Test name
Test status
Simulation time 215271314 ps
CPU time 0.89 seconds
Started Jun 26 05:17:29 PM PDT 24
Finished Jun 26 05:17:34 PM PDT 24
Peak memory 206232 kb
Host smart-d7e7535d-600a-4b87-ae00-f7f077de9605
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=544171698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.544171698
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.3472443592
Short name T2566
Test name
Test status
Simulation time 213379760 ps
CPU time 0.83 seconds
Started Jun 26 05:17:35 PM PDT 24
Finished Jun 26 05:17:41 PM PDT 24
Peak memory 206116 kb
Host smart-38e2d7a4-848c-406b-ba20-14756fb20c70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34724
43592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.3472443592
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.51888422
Short name T2577
Test name
Test status
Simulation time 65001567 ps
CPU time 0.7 seconds
Started Jun 26 05:17:37 PM PDT 24
Finished Jun 26 05:17:43 PM PDT 24
Peak memory 206208 kb
Host smart-50b2ee79-266c-4a53-84f2-6dd1e025fa26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51888
422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.51888422
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.2156674808
Short name T1624
Test name
Test status
Simulation time 22121395667 ps
CPU time 48.3 seconds
Started Jun 26 05:17:36 PM PDT 24
Finished Jun 26 05:18:30 PM PDT 24
Peak memory 206436 kb
Host smart-ed5b34e9-9a56-441e-b029-743c1f246dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21566
74808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.2156674808
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.1480260963
Short name T820
Test name
Test status
Simulation time 200230118 ps
CPU time 0.89 seconds
Started Jun 26 05:17:33 PM PDT 24
Finished Jun 26 05:17:36 PM PDT 24
Peak memory 206200 kb
Host smart-1cbe6505-9fb3-4371-9e78-a93f767554dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14802
60963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.1480260963
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.751218533
Short name T2495
Test name
Test status
Simulation time 277601524 ps
CPU time 0.97 seconds
Started Jun 26 05:17:35 PM PDT 24
Finished Jun 26 05:17:40 PM PDT 24
Peak memory 206120 kb
Host smart-f7eea777-cf72-487b-bee0-c1424f704b1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75121
8533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.751218533
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.3666173907
Short name T1577
Test name
Test status
Simulation time 255983978 ps
CPU time 0.93 seconds
Started Jun 26 05:17:37 PM PDT 24
Finished Jun 26 05:17:43 PM PDT 24
Peak memory 206224 kb
Host smart-1582f70a-91a8-4eec-ae95-c6691a60638c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36661
73907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.3666173907
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.2786782872
Short name T391
Test name
Test status
Simulation time 164625793 ps
CPU time 0.81 seconds
Started Jun 26 05:17:33 PM PDT 24
Finished Jun 26 05:17:37 PM PDT 24
Peak memory 206200 kb
Host smart-38f3d5d7-55f3-4b24-a749-8839a64dbe7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27867
82872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.2786782872
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.1393676983
Short name T2139
Test name
Test status
Simulation time 146772894 ps
CPU time 0.79 seconds
Started Jun 26 05:17:36 PM PDT 24
Finished Jun 26 05:17:42 PM PDT 24
Peak memory 206044 kb
Host smart-a180885b-24cb-4f97-9f42-f6615441c98d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13936
76983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.1393676983
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.1100612037
Short name T1881
Test name
Test status
Simulation time 143318597 ps
CPU time 0.76 seconds
Started Jun 26 05:17:49 PM PDT 24
Finished Jun 26 05:17:53 PM PDT 24
Peak memory 205948 kb
Host smart-e1f6a690-9374-4ef3-827a-9771bc7d4b4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11006
12037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.1100612037
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.154719258
Short name T1433
Test name
Test status
Simulation time 193789066 ps
CPU time 0.85 seconds
Started Jun 26 05:17:49 PM PDT 24
Finished Jun 26 05:17:53 PM PDT 24
Peak memory 206028 kb
Host smart-7d433ae8-b3c9-4a13-86fc-2826eb3ec7c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15471
9258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.154719258
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.3784100733
Short name T833
Test name
Test status
Simulation time 210619435 ps
CPU time 0.92 seconds
Started Jun 26 05:17:34 PM PDT 24
Finished Jun 26 05:17:39 PM PDT 24
Peak memory 206224 kb
Host smart-759aff76-029b-427c-9c3d-38e1c5e2c74b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37841
00733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.3784100733
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.1197223947
Short name T490
Test name
Test status
Simulation time 4764304932 ps
CPU time 41.32 seconds
Started Jun 26 05:17:32 PM PDT 24
Finished Jun 26 05:18:16 PM PDT 24
Peak memory 206508 kb
Host smart-38744b8f-cf6b-4b90-a45e-af0d039a9344
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1197223947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.1197223947
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.1180508025
Short name T1403
Test name
Test status
Simulation time 157370026 ps
CPU time 0.79 seconds
Started Jun 26 05:17:37 PM PDT 24
Finished Jun 26 05:17:43 PM PDT 24
Peak memory 206212 kb
Host smart-50bfae1e-fb7b-413f-af8b-29286364aed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11805
08025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.1180508025
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.1671931450
Short name T874
Test name
Test status
Simulation time 167008236 ps
CPU time 0.81 seconds
Started Jun 26 05:17:39 PM PDT 24
Finished Jun 26 05:17:45 PM PDT 24
Peak memory 206120 kb
Host smart-2939c5dc-5fdd-4b29-b19c-88ac3ec5943d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16719
31450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.1671931450
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.2988344230
Short name T369
Test name
Test status
Simulation time 5438427266 ps
CPU time 51.81 seconds
Started Jun 26 05:17:38 PM PDT 24
Finished Jun 26 05:18:34 PM PDT 24
Peak memory 206344 kb
Host smart-3100fd3e-1db6-4b64-9b43-b13fe69d476f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29883
44230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.2988344230
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.2991913637
Short name T15
Test name
Test status
Simulation time 3969317282 ps
CPU time 4.59 seconds
Started Jun 26 05:17:39 PM PDT 24
Finished Jun 26 05:17:49 PM PDT 24
Peak memory 206380 kb
Host smart-a6f9a44f-c5be-4772-9678-13d8f1c69557
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2991913637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.2991913637
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.2462460930
Short name T672
Test name
Test status
Simulation time 13497265251 ps
CPU time 12.8 seconds
Started Jun 26 05:17:39 PM PDT 24
Finished Jun 26 05:17:57 PM PDT 24
Peak memory 206460 kb
Host smart-ceb6e4eb-77f9-4ccf-b372-535a22376357
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2462460930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.2462460930
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.1139955987
Short name T432
Test name
Test status
Simulation time 23319839588 ps
CPU time 22.41 seconds
Started Jun 26 05:17:37 PM PDT 24
Finished Jun 26 05:18:04 PM PDT 24
Peak memory 206488 kb
Host smart-26c67345-dee6-4890-a675-10cb014baf17
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1139955987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.1139955987
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.2397365490
Short name T2164
Test name
Test status
Simulation time 242741085 ps
CPU time 0.93 seconds
Started Jun 26 05:17:37 PM PDT 24
Finished Jun 26 05:17:43 PM PDT 24
Peak memory 206176 kb
Host smart-7ddcfaea-fdb4-470e-8a85-4d36a667b3fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23973
65490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.2397365490
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.3996100056
Short name T969
Test name
Test status
Simulation time 177132932 ps
CPU time 0.74 seconds
Started Jun 26 05:17:37 PM PDT 24
Finished Jun 26 05:17:42 PM PDT 24
Peak memory 206172 kb
Host smart-5371ffc9-beeb-4cf2-8dd9-9b26c641a4c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39961
00056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.3996100056
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.1465059783
Short name T192
Test name
Test status
Simulation time 404915358 ps
CPU time 1.3 seconds
Started Jun 26 05:17:38 PM PDT 24
Finished Jun 26 05:17:45 PM PDT 24
Peak memory 206096 kb
Host smart-835f4e84-644c-406e-9acb-53506f6b18d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14650
59783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.1465059783
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.200225048
Short name T2527
Test name
Test status
Simulation time 1088967986 ps
CPU time 2.55 seconds
Started Jun 26 05:17:40 PM PDT 24
Finished Jun 26 05:17:47 PM PDT 24
Peak memory 206324 kb
Host smart-75fb98af-1e9c-4543-935f-51a76c683636
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20022
5048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.200225048
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.3422280677
Short name T2260
Test name
Test status
Simulation time 8927784156 ps
CPU time 18.24 seconds
Started Jun 26 05:17:37 PM PDT 24
Finished Jun 26 05:18:00 PM PDT 24
Peak memory 206592 kb
Host smart-44017a96-093e-456e-a01d-33708679057a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34222
80677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.3422280677
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.346686588
Short name T1455
Test name
Test status
Simulation time 383651588 ps
CPU time 1.23 seconds
Started Jun 26 05:17:49 PM PDT 24
Finished Jun 26 05:17:53 PM PDT 24
Peak memory 205852 kb
Host smart-ffc0f042-69c4-47ee-9a52-05976e882e0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34668
6588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.346686588
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.242434373
Short name T2475
Test name
Test status
Simulation time 183568626 ps
CPU time 0.82 seconds
Started Jun 26 05:17:36 PM PDT 24
Finished Jun 26 05:17:42 PM PDT 24
Peak memory 206160 kb
Host smart-b9a84649-8043-422f-8910-84af103ea255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24243
4373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.242434373
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.2041352194
Short name T1654
Test name
Test status
Simulation time 36275044 ps
CPU time 0.67 seconds
Started Jun 26 05:17:49 PM PDT 24
Finished Jun 26 05:17:53 PM PDT 24
Peak memory 206016 kb
Host smart-63da5f9e-3f0b-4ebd-8a5d-662f4a6602b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20413
52194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.2041352194
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.197357533
Short name T1097
Test name
Test status
Simulation time 703011516 ps
CPU time 1.78 seconds
Started Jun 26 05:17:40 PM PDT 24
Finished Jun 26 05:17:46 PM PDT 24
Peak memory 206348 kb
Host smart-6e62f676-eb6c-44c4-917b-379895ba4816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19735
7533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.197357533
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.823451399
Short name T1298
Test name
Test status
Simulation time 187443888 ps
CPU time 2.18 seconds
Started Jun 26 05:17:39 PM PDT 24
Finished Jun 26 05:17:46 PM PDT 24
Peak memory 206636 kb
Host smart-845d9032-d1ed-4b1f-9356-a12fdaec91e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82345
1399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.823451399
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.2071559981
Short name T2391
Test name
Test status
Simulation time 239177934 ps
CPU time 0.99 seconds
Started Jun 26 05:17:52 PM PDT 24
Finished Jun 26 05:17:57 PM PDT 24
Peak memory 206112 kb
Host smart-641cfd95-f4f6-4090-8a85-22f759f23c25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20715
59981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.2071559981
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.2308777826
Short name T1108
Test name
Test status
Simulation time 147555646 ps
CPU time 0.77 seconds
Started Jun 26 05:17:53 PM PDT 24
Finished Jun 26 05:17:57 PM PDT 24
Peak memory 206184 kb
Host smart-1d734b46-f01f-4464-9734-350c3e6f8eb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23087
77826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.2308777826
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.1482057797
Short name T1272
Test name
Test status
Simulation time 159557465 ps
CPU time 0.79 seconds
Started Jun 26 05:17:39 PM PDT 24
Finished Jun 26 05:17:45 PM PDT 24
Peak memory 206188 kb
Host smart-85760618-6cca-44cc-8074-f9a48a3cc388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14820
57797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.1482057797
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_invalid_sync.3920917753
Short name T1986
Test name
Test status
Simulation time 8012813169 ps
CPU time 59.47 seconds
Started Jun 26 05:17:37 PM PDT 24
Finished Jun 26 05:18:41 PM PDT 24
Peak memory 206500 kb
Host smart-af5dabaa-c337-4623-911b-c09873bc03aa
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3920917753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.3920917753
Directory /workspace/25.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.1161537791
Short name T533
Test name
Test status
Simulation time 228618648 ps
CPU time 0.86 seconds
Started Jun 26 05:17:38 PM PDT 24
Finished Jun 26 05:17:44 PM PDT 24
Peak memory 206112 kb
Host smart-56675cc2-7d16-41fd-b3ed-da666f5ebc54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11615
37791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.1161537791
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.4064256579
Short name T1598
Test name
Test status
Simulation time 23280345521 ps
CPU time 22.01 seconds
Started Jun 26 05:17:39 PM PDT 24
Finished Jun 26 05:18:06 PM PDT 24
Peak memory 206312 kb
Host smart-3605c899-74a2-4638-8ed0-44d3f8a2e789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40642
56579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.4064256579
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.3339726617
Short name T2193
Test name
Test status
Simulation time 3332468717 ps
CPU time 4.25 seconds
Started Jun 26 05:17:40 PM PDT 24
Finished Jun 26 05:17:49 PM PDT 24
Peak memory 206176 kb
Host smart-2f3ab1f8-5317-469f-8938-644e53b408a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33397
26617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.3339726617
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.3391246947
Short name T1815
Test name
Test status
Simulation time 7495971606 ps
CPU time 70.05 seconds
Started Jun 26 05:17:37 PM PDT 24
Finished Jun 26 05:18:52 PM PDT 24
Peak memory 206528 kb
Host smart-150b3635-ea6b-4d51-8036-26b5b8b2f5d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33912
46947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.3391246947
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.3492506976
Short name T662
Test name
Test status
Simulation time 2869963268 ps
CPU time 77.12 seconds
Started Jun 26 05:17:46 PM PDT 24
Finished Jun 26 05:19:07 PM PDT 24
Peak memory 206364 kb
Host smart-164560de-3323-4f47-9f78-098f57384224
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3492506976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.3492506976
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.253857758
Short name T802
Test name
Test status
Simulation time 255020942 ps
CPU time 0.95 seconds
Started Jun 26 05:17:51 PM PDT 24
Finished Jun 26 05:17:56 PM PDT 24
Peak memory 206192 kb
Host smart-f4638174-a52f-47aa-a719-42f44292ad5c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=253857758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.253857758
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.4158598955
Short name T2030
Test name
Test status
Simulation time 188684015 ps
CPU time 0.83 seconds
Started Jun 26 05:17:42 PM PDT 24
Finished Jun 26 05:17:47 PM PDT 24
Peak memory 206136 kb
Host smart-78a3278d-6dd8-4664-ae4d-9908a849b4e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41585
98955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.4158598955
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.2065996769
Short name T935
Test name
Test status
Simulation time 3984168024 ps
CPU time 28.15 seconds
Started Jun 26 05:17:42 PM PDT 24
Finished Jun 26 05:18:15 PM PDT 24
Peak memory 206540 kb
Host smart-e5ffcf1f-5b12-4d09-ab43-6bfda188bb8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20659
96769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.2065996769
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.854759596
Short name T366
Test name
Test status
Simulation time 5330262351 ps
CPU time 49.98 seconds
Started Jun 26 05:17:48 PM PDT 24
Finished Jun 26 05:18:41 PM PDT 24
Peak memory 206552 kb
Host smart-c35a87ef-7513-4f9d-a1c0-144592fbd7b2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=854759596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.854759596
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.2281525228
Short name T1737
Test name
Test status
Simulation time 153529655 ps
CPU time 0.8 seconds
Started Jun 26 05:17:50 PM PDT 24
Finished Jun 26 05:17:54 PM PDT 24
Peak memory 206136 kb
Host smart-9f65445f-067c-46cb-9791-f35c81556efd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2281525228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.2281525228
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.1146613585
Short name T473
Test name
Test status
Simulation time 183305633 ps
CPU time 0.81 seconds
Started Jun 26 05:17:43 PM PDT 24
Finished Jun 26 05:17:48 PM PDT 24
Peak memory 206084 kb
Host smart-a3aa352a-9452-427d-ac85-51ee1d001689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11466
13585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.1146613585
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.1537435786
Short name T2418
Test name
Test status
Simulation time 209204014 ps
CPU time 0.88 seconds
Started Jun 26 05:17:49 PM PDT 24
Finished Jun 26 05:17:53 PM PDT 24
Peak memory 205844 kb
Host smart-e46a20d7-94c8-48be-870b-4ddb549fb9b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15374
35786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.1537435786
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.1020491871
Short name T1980
Test name
Test status
Simulation time 189579069 ps
CPU time 0.86 seconds
Started Jun 26 05:17:44 PM PDT 24
Finished Jun 26 05:17:49 PM PDT 24
Peak memory 206212 kb
Host smart-8bcd7ff7-cd60-46d1-bf1c-c157c8a8fb61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10204
91871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.1020491871
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.1257425129
Short name T1842
Test name
Test status
Simulation time 170562751 ps
CPU time 0.81 seconds
Started Jun 26 05:17:43 PM PDT 24
Finished Jun 26 05:17:47 PM PDT 24
Peak memory 206180 kb
Host smart-ab76a2b6-5509-4322-b0f8-bbedac306085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12574
25129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.1257425129
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.137625891
Short name T697
Test name
Test status
Simulation time 198618031 ps
CPU time 0.86 seconds
Started Jun 26 05:17:49 PM PDT 24
Finished Jun 26 05:17:53 PM PDT 24
Peak memory 206024 kb
Host smart-c8ce6839-be58-4e40-ae36-ba81777d739b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13762
5891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.137625891
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.2297189867
Short name T187
Test name
Test status
Simulation time 170876168 ps
CPU time 0.9 seconds
Started Jun 26 05:17:44 PM PDT 24
Finished Jun 26 05:17:48 PM PDT 24
Peak memory 206184 kb
Host smart-a04a049b-bcd3-430f-9bab-b7722f73418b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22971
89867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.2297189867
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.1394695506
Short name T624
Test name
Test status
Simulation time 240343916 ps
CPU time 0.96 seconds
Started Jun 26 05:17:44 PM PDT 24
Finished Jun 26 05:17:49 PM PDT 24
Peak memory 206220 kb
Host smart-73023922-e260-489d-8b9d-eb13300aad45
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1394695506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.1394695506
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.2640046315
Short name T34
Test name
Test status
Simulation time 151723817 ps
CPU time 0.76 seconds
Started Jun 26 05:17:44 PM PDT 24
Finished Jun 26 05:17:49 PM PDT 24
Peak memory 206196 kb
Host smart-ba2ac68e-f1c9-49c6-9c5c-3e2943dafb49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26400
46315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.2640046315
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.247854818
Short name T2377
Test name
Test status
Simulation time 52211079 ps
CPU time 0.68 seconds
Started Jun 26 05:17:43 PM PDT 24
Finished Jun 26 05:17:48 PM PDT 24
Peak memory 206212 kb
Host smart-d5462da2-f8c0-481e-b054-157da850fca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24785
4818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.247854818
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.3331645146
Short name T85
Test name
Test status
Simulation time 12939176516 ps
CPU time 29.63 seconds
Started Jun 26 05:17:42 PM PDT 24
Finished Jun 26 05:18:15 PM PDT 24
Peak memory 206540 kb
Host smart-3af917c3-dbaf-45ff-9573-d1d4af3a2e62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33316
45146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.3331645146
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.346495014
Short name T1851
Test name
Test status
Simulation time 215103499 ps
CPU time 0.84 seconds
Started Jun 26 05:17:47 PM PDT 24
Finished Jun 26 05:17:51 PM PDT 24
Peak memory 206120 kb
Host smart-c6c0f06b-3950-46d1-91ac-adf8f1ed4cbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34649
5014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.346495014
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.4008778333
Short name T671
Test name
Test status
Simulation time 183923032 ps
CPU time 0.88 seconds
Started Jun 26 05:17:42 PM PDT 24
Finished Jun 26 05:17:47 PM PDT 24
Peak memory 206144 kb
Host smart-c05dad08-481d-4cec-9e5f-ddbce9f630e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40087
78333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.4008778333
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.3613899632
Short name T1791
Test name
Test status
Simulation time 242232276 ps
CPU time 0.96 seconds
Started Jun 26 05:17:50 PM PDT 24
Finished Jun 26 05:17:53 PM PDT 24
Peak memory 206228 kb
Host smart-263f15b9-a83e-48ce-bac9-4d87c02a8d9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36138
99632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.3613899632
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.89661478
Short name T2270
Test name
Test status
Simulation time 166420907 ps
CPU time 0.79 seconds
Started Jun 26 05:17:43 PM PDT 24
Finished Jun 26 05:17:48 PM PDT 24
Peak memory 206192 kb
Host smart-599e6b29-ff3f-4514-b819-38770348afd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89661
478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.89661478
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.1343707844
Short name T1860
Test name
Test status
Simulation time 140792398 ps
CPU time 0.77 seconds
Started Jun 26 05:17:47 PM PDT 24
Finished Jun 26 05:17:51 PM PDT 24
Peak memory 206116 kb
Host smart-4b82b3c8-f422-4a6f-927b-116e284af9f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13437
07844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.1343707844
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.1867269073
Short name T959
Test name
Test status
Simulation time 147305630 ps
CPU time 0.81 seconds
Started Jun 26 05:17:42 PM PDT 24
Finished Jun 26 05:17:47 PM PDT 24
Peak memory 206132 kb
Host smart-afe61404-d229-4e02-934c-094b123d94ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18672
69073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.1867269073
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.852550648
Short name T2252
Test name
Test status
Simulation time 200361553 ps
CPU time 0.81 seconds
Started Jun 26 05:17:45 PM PDT 24
Finished Jun 26 05:17:49 PM PDT 24
Peak memory 206148 kb
Host smart-efbb24da-7e8e-4716-bd26-f1264d8c7493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85255
0648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.852550648
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.2858976932
Short name T2392
Test name
Test status
Simulation time 270703077 ps
CPU time 0.94 seconds
Started Jun 26 05:17:43 PM PDT 24
Finished Jun 26 05:17:48 PM PDT 24
Peak memory 206224 kb
Host smart-6a1ece93-065a-4b62-a989-cc9d7c9348d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28589
76932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.2858976932
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.1212886693
Short name T899
Test name
Test status
Simulation time 6505653348 ps
CPU time 185.68 seconds
Started Jun 26 05:17:44 PM PDT 24
Finished Jun 26 05:20:53 PM PDT 24
Peak memory 206724 kb
Host smart-0e3e06ce-be33-494c-8097-9ca3262abc5e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1212886693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.1212886693
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.876844967
Short name T1104
Test name
Test status
Simulation time 190948044 ps
CPU time 0.82 seconds
Started Jun 26 05:17:43 PM PDT 24
Finished Jun 26 05:17:48 PM PDT 24
Peak memory 206148 kb
Host smart-e750f4b8-f1e4-460c-8cb7-e0900b7751bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87684
4967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.876844967
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.509324308
Short name T2339
Test name
Test status
Simulation time 166650653 ps
CPU time 0.79 seconds
Started Jun 26 05:17:43 PM PDT 24
Finished Jun 26 05:17:48 PM PDT 24
Peak memory 206124 kb
Host smart-8f2d21c6-cb8e-4110-9a9b-db624c49f146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50932
4308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.509324308
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.1365712490
Short name T619
Test name
Test status
Simulation time 3199718357 ps
CPU time 30.08 seconds
Started Jun 26 05:17:46 PM PDT 24
Finished Jun 26 05:18:19 PM PDT 24
Peak memory 206424 kb
Host smart-fd4e05d2-1b49-4249-8754-1c662e9752b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13657
12490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.1365712490
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.2224415547
Short name T1086
Test name
Test status
Simulation time 3650722540 ps
CPU time 4.13 seconds
Started Jun 26 05:17:51 PM PDT 24
Finished Jun 26 05:17:58 PM PDT 24
Peak memory 206196 kb
Host smart-09e272ea-5bd5-4f4b-a118-e4a984376f47
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2224415547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.2224415547
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.3051861512
Short name T2120
Test name
Test status
Simulation time 13345886263 ps
CPU time 13.19 seconds
Started Jun 26 05:17:53 PM PDT 24
Finished Jun 26 05:18:09 PM PDT 24
Peak memory 206316 kb
Host smart-4f973193-bd31-4b45-858d-74dc4c8aa351
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3051861512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.3051861512
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.2943097760
Short name T989
Test name
Test status
Simulation time 23350265808 ps
CPU time 24.07 seconds
Started Jun 26 05:17:51 PM PDT 24
Finished Jun 26 05:18:19 PM PDT 24
Peak memory 206276 kb
Host smart-a89fd49c-8597-41a9-bd38-3a4e50e4a292
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2943097760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.2943097760
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.2662457348
Short name T1753
Test name
Test status
Simulation time 211153098 ps
CPU time 0.87 seconds
Started Jun 26 05:17:50 PM PDT 24
Finished Jun 26 05:17:54 PM PDT 24
Peak memory 206220 kb
Host smart-47fb3b23-65e1-42b0-9d0d-f4d299604015
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26624
57348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.2662457348
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.3807440516
Short name T2214
Test name
Test status
Simulation time 199423595 ps
CPU time 0.79 seconds
Started Jun 26 05:17:51 PM PDT 24
Finished Jun 26 05:17:56 PM PDT 24
Peak memory 206184 kb
Host smart-816043b0-ffa5-4012-97df-a4589f49956c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38074
40516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.3807440516
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.588364546
Short name T1952
Test name
Test status
Simulation time 405469794 ps
CPU time 1.31 seconds
Started Jun 26 05:17:50 PM PDT 24
Finished Jun 26 05:17:54 PM PDT 24
Peak memory 206168 kb
Host smart-d319f9eb-49d9-42d8-8e87-80c4c3d3f8b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58836
4546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.588364546
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.2885804581
Short name T1960
Test name
Test status
Simulation time 566280694 ps
CPU time 1.56 seconds
Started Jun 26 05:17:51 PM PDT 24
Finished Jun 26 05:17:55 PM PDT 24
Peak memory 206204 kb
Host smart-e1dc44e8-99e6-4804-bb87-91f9f0d2660a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28858
04581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.2885804581
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.3305644040
Short name T1827
Test name
Test status
Simulation time 19547823402 ps
CPU time 40.94 seconds
Started Jun 26 05:17:52 PM PDT 24
Finished Jun 26 05:18:37 PM PDT 24
Peak memory 206512 kb
Host smart-d4940ee5-377e-4eac-8cb8-61c53cd214e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33056
44040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.3305644040
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.3320969117
Short name T926
Test name
Test status
Simulation time 414497174 ps
CPU time 1.34 seconds
Started Jun 26 05:17:52 PM PDT 24
Finished Jun 26 05:17:58 PM PDT 24
Peak memory 206212 kb
Host smart-1702ae1b-05f1-4352-ac60-8193558ab7ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33209
69117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.3320969117
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.4048754635
Short name T2006
Test name
Test status
Simulation time 146107220 ps
CPU time 0.76 seconds
Started Jun 26 05:17:51 PM PDT 24
Finished Jun 26 05:17:55 PM PDT 24
Peak memory 206172 kb
Host smart-7d40a4b6-1134-47fc-9af7-5574f96a5bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40487
54635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.4048754635
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.3834113100
Short name T1723
Test name
Test status
Simulation time 51016733 ps
CPU time 0.65 seconds
Started Jun 26 05:17:51 PM PDT 24
Finished Jun 26 05:17:55 PM PDT 24
Peak memory 206140 kb
Host smart-5d180949-ed52-4e04-b00e-65896ec74b60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38341
13100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.3834113100
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.2073555656
Short name T2451
Test name
Test status
Simulation time 784272500 ps
CPU time 1.83 seconds
Started Jun 26 05:17:52 PM PDT 24
Finished Jun 26 05:17:57 PM PDT 24
Peak memory 206712 kb
Host smart-701f7c0b-b9b3-49ac-b19e-9897d49aa159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20735
55656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.2073555656
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.1206985067
Short name T2032
Test name
Test status
Simulation time 270105791 ps
CPU time 1.69 seconds
Started Jun 26 05:17:50 PM PDT 24
Finished Jun 26 05:17:55 PM PDT 24
Peak memory 206376 kb
Host smart-0a144b6f-94d0-49a7-9b59-10d1c5247801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12069
85067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.1206985067
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.1799555252
Short name T453
Test name
Test status
Simulation time 245314604 ps
CPU time 0.91 seconds
Started Jun 26 05:17:58 PM PDT 24
Finished Jun 26 05:18:01 PM PDT 24
Peak memory 206136 kb
Host smart-2cf16fa0-2977-490a-9c4d-230abd155943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17995
55252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.1799555252
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.2586011660
Short name T1805
Test name
Test status
Simulation time 183656844 ps
CPU time 0.84 seconds
Started Jun 26 05:17:59 PM PDT 24
Finished Jun 26 05:18:02 PM PDT 24
Peak memory 206440 kb
Host smart-f10af785-6d1e-4cab-a071-571b5dbf698e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25860
11660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.2586011660
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.2955524267
Short name T1714
Test name
Test status
Simulation time 169984006 ps
CPU time 0.84 seconds
Started Jun 26 05:17:50 PM PDT 24
Finished Jun 26 05:17:54 PM PDT 24
Peak memory 206220 kb
Host smart-84f35b04-f035-4c99-969d-7531cc5acc7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29555
24267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.2955524267
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_invalid_sync.1836376703
Short name T2289
Test name
Test status
Simulation time 6626177788 ps
CPU time 61.65 seconds
Started Jun 26 05:17:51 PM PDT 24
Finished Jun 26 05:18:57 PM PDT 24
Peak memory 206480 kb
Host smart-7ebfd0e5-d4ff-4949-88b2-8da5c0890d22
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1836376703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.1836376703
Directory /workspace/26.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.504856724
Short name T720
Test name
Test status
Simulation time 220018265 ps
CPU time 0.87 seconds
Started Jun 26 05:17:50 PM PDT 24
Finished Jun 26 05:17:54 PM PDT 24
Peak memory 206164 kb
Host smart-e8137718-1011-4f9a-8174-b31ca7572d5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50485
6724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.504856724
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.2641169937
Short name T2256
Test name
Test status
Simulation time 23296933977 ps
CPU time 22.79 seconds
Started Jun 26 05:17:51 PM PDT 24
Finished Jun 26 05:18:18 PM PDT 24
Peak memory 206296 kb
Host smart-b4e0ad07-80b1-43cb-aca2-a06e6194fdee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26411
69937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.2641169937
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.1286915723
Short name T2540
Test name
Test status
Simulation time 3306197232 ps
CPU time 3.59 seconds
Started Jun 26 05:17:52 PM PDT 24
Finished Jun 26 05:17:59 PM PDT 24
Peak memory 206136 kb
Host smart-9d387a63-591d-4e9d-9ec1-fa229db16063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12869
15723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.1286915723
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.3454105753
Short name T1978
Test name
Test status
Simulation time 8530043973 ps
CPU time 59.48 seconds
Started Jun 26 05:17:52 PM PDT 24
Finished Jun 26 05:18:55 PM PDT 24
Peak memory 206596 kb
Host smart-1e853ff0-13b5-40f1-81a5-72cae72501ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34541
05753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.3454105753
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.2244043055
Short name T1862
Test name
Test status
Simulation time 5628601329 ps
CPU time 156.51 seconds
Started Jun 26 05:17:51 PM PDT 24
Finished Jun 26 05:20:31 PM PDT 24
Peak memory 206564 kb
Host smart-c1f1ded3-5cd7-4ee5-9619-a863995dedc5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2244043055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.2244043055
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.3437676054
Short name T713
Test name
Test status
Simulation time 259582649 ps
CPU time 0.9 seconds
Started Jun 26 05:18:06 PM PDT 24
Finished Jun 26 05:18:10 PM PDT 24
Peak memory 205856 kb
Host smart-d2240c84-c31f-4034-958a-7ef9bdde54d1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3437676054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.3437676054
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.1334692798
Short name T1732
Test name
Test status
Simulation time 191315665 ps
CPU time 0.87 seconds
Started Jun 26 05:17:51 PM PDT 24
Finished Jun 26 05:17:55 PM PDT 24
Peak memory 206132 kb
Host smart-244fb488-0217-4aaf-8ac2-8cd25615f5e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13346
92798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.1334692798
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.711845624
Short name T1006
Test name
Test status
Simulation time 5110533898 ps
CPU time 37.54 seconds
Started Jun 26 05:17:50 PM PDT 24
Finished Jun 26 05:18:30 PM PDT 24
Peak memory 206584 kb
Host smart-109b266b-4514-413b-9d5b-66b2996162bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71184
5624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.711845624
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.2512018558
Short name T756
Test name
Test status
Simulation time 4139579633 ps
CPU time 112.27 seconds
Started Jun 26 05:17:51 PM PDT 24
Finished Jun 26 05:19:47 PM PDT 24
Peak memory 206440 kb
Host smart-cceed6f2-3874-4d1c-bd1e-da8d3c436888
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2512018558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.2512018558
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.3080601955
Short name T955
Test name
Test status
Simulation time 169016847 ps
CPU time 0.8 seconds
Started Jun 26 05:18:04 PM PDT 24
Finished Jun 26 05:18:09 PM PDT 24
Peak memory 206144 kb
Host smart-8095b32e-925b-4002-b1f5-d2ea770dee56
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3080601955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.3080601955
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.1459483056
Short name T329
Test name
Test status
Simulation time 183332690 ps
CPU time 0.84 seconds
Started Jun 26 05:19:08 PM PDT 24
Finished Jun 26 05:19:12 PM PDT 24
Peak memory 206180 kb
Host smart-eb8927bf-9896-45af-8d40-48d6c71c5610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14594
83056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.1459483056
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.4137206313
Short name T507
Test name
Test status
Simulation time 187454639 ps
CPU time 0.82 seconds
Started Jun 26 05:17:52 PM PDT 24
Finished Jun 26 05:17:57 PM PDT 24
Peak memory 206108 kb
Host smart-49810233-d402-441a-81a2-4632e5b27983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41372
06313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.4137206313
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.2796370655
Short name T1564
Test name
Test status
Simulation time 181687940 ps
CPU time 0.8 seconds
Started Jun 26 05:17:49 PM PDT 24
Finished Jun 26 05:17:53 PM PDT 24
Peak memory 206196 kb
Host smart-e488a35b-81e7-4f47-ba1e-bb125938f162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27963
70655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.2796370655
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.3494906128
Short name T1036
Test name
Test status
Simulation time 180132793 ps
CPU time 0.77 seconds
Started Jun 26 05:17:50 PM PDT 24
Finished Jun 26 05:17:55 PM PDT 24
Peak memory 206172 kb
Host smart-f200388e-b5de-4a41-854b-be55862e9ff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34949
06128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.3494906128
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.2851250249
Short name T1653
Test name
Test status
Simulation time 155645849 ps
CPU time 0.81 seconds
Started Jun 26 05:18:00 PM PDT 24
Finished Jun 26 05:18:02 PM PDT 24
Peak memory 206448 kb
Host smart-64d9e738-63ef-45d1-a5a7-38931be611d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28512
50249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.2851250249
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.8548732
Short name T1454
Test name
Test status
Simulation time 223246778 ps
CPU time 0.88 seconds
Started Jun 26 05:18:05 PM PDT 24
Finished Jun 26 05:18:09 PM PDT 24
Peak memory 206036 kb
Host smart-a0ad0c5d-1579-4589-991d-31f5a6337d6e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=8548732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.8548732
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.754523584
Short name T2406
Test name
Test status
Simulation time 157743410 ps
CPU time 0.77 seconds
Started Jun 26 05:17:57 PM PDT 24
Finished Jun 26 05:18:00 PM PDT 24
Peak memory 206188 kb
Host smart-3d9b5b29-da72-4397-94b8-b5faa2267511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75452
3584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.754523584
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.2305409152
Short name T2467
Test name
Test status
Simulation time 46075760 ps
CPU time 0.67 seconds
Started Jun 26 05:17:56 PM PDT 24
Finished Jun 26 05:17:59 PM PDT 24
Peak memory 206172 kb
Host smart-72b7fa82-7cb1-4307-9a03-37f12579ba28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23054
09152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.2305409152
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.3146530313
Short name T298
Test name
Test status
Simulation time 14964383877 ps
CPU time 32.2 seconds
Started Jun 26 05:17:57 PM PDT 24
Finished Jun 26 05:18:32 PM PDT 24
Peak memory 206504 kb
Host smart-ea6eade0-a030-4ce6-a6ac-339175c08dc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31465
30313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.3146530313
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.2193536564
Short name T2218
Test name
Test status
Simulation time 160641049 ps
CPU time 0.8 seconds
Started Jun 26 05:17:57 PM PDT 24
Finished Jun 26 05:18:00 PM PDT 24
Peak memory 206172 kb
Host smart-7421e1c1-0db1-431b-9740-a5e52e82c9f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21935
36564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.2193536564
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.3197947740
Short name T789
Test name
Test status
Simulation time 263823077 ps
CPU time 0.96 seconds
Started Jun 26 05:17:58 PM PDT 24
Finished Jun 26 05:18:01 PM PDT 24
Peak memory 206208 kb
Host smart-1815d2d3-76c0-40ec-929a-c5bc9a09e6f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31979
47740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.3197947740
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.2856009914
Short name T982
Test name
Test status
Simulation time 194843444 ps
CPU time 0.8 seconds
Started Jun 26 05:17:57 PM PDT 24
Finished Jun 26 05:18:00 PM PDT 24
Peak memory 206196 kb
Host smart-a9763da5-0e93-4c5b-ac12-1598f1fb1c57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28560
09914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.2856009914
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.313903179
Short name T1239
Test name
Test status
Simulation time 161669014 ps
CPU time 0.75 seconds
Started Jun 26 05:17:58 PM PDT 24
Finished Jun 26 05:18:01 PM PDT 24
Peak memory 206120 kb
Host smart-0cf99488-90e0-428e-8bfd-96f2c8f56500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31390
3179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.313903179
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.1306799467
Short name T67
Test name
Test status
Simulation time 132349776 ps
CPU time 0.81 seconds
Started Jun 26 05:17:59 PM PDT 24
Finished Jun 26 05:18:02 PM PDT 24
Peak memory 206204 kb
Host smart-2d39c216-d5b9-4732-adc9-20fbced9c6c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13067
99467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.1306799467
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.3795933062
Short name T1755
Test name
Test status
Simulation time 150381336 ps
CPU time 0.8 seconds
Started Jun 26 05:17:57 PM PDT 24
Finished Jun 26 05:18:00 PM PDT 24
Peak memory 206204 kb
Host smart-d3ce465b-f7e4-4291-a78a-5e4125d872c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37959
33062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.3795933062
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.832675896
Short name T394
Test name
Test status
Simulation time 162902658 ps
CPU time 0.77 seconds
Started Jun 26 05:17:57 PM PDT 24
Finished Jun 26 05:18:00 PM PDT 24
Peak memory 206224 kb
Host smart-129df6bd-82e8-4410-b3f2-ed5a287206a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83267
5896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.832675896
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.4285165125
Short name T500
Test name
Test status
Simulation time 207969642 ps
CPU time 0.88 seconds
Started Jun 26 05:17:59 PM PDT 24
Finished Jun 26 05:18:02 PM PDT 24
Peak memory 206128 kb
Host smart-36703888-44b1-410b-84e0-7391409634b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42851
65125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.4285165125
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.601093277
Short name T2364
Test name
Test status
Simulation time 3768348948 ps
CPU time 27.06 seconds
Started Jun 26 05:17:58 PM PDT 24
Finished Jun 26 05:18:27 PM PDT 24
Peak memory 206476 kb
Host smart-dffaa411-2c1f-42d8-bafc-2528340ec18f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=601093277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.601093277
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.2495377052
Short name T2247
Test name
Test status
Simulation time 181465153 ps
CPU time 0.88 seconds
Started Jun 26 05:17:58 PM PDT 24
Finished Jun 26 05:18:01 PM PDT 24
Peak memory 206184 kb
Host smart-739c1628-58ed-4268-b56e-ab9880c4182f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24953
77052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.2495377052
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.1051235656
Short name T2510
Test name
Test status
Simulation time 139043565 ps
CPU time 0.74 seconds
Started Jun 26 05:17:58 PM PDT 24
Finished Jun 26 05:18:01 PM PDT 24
Peak memory 206176 kb
Host smart-df160513-25de-4813-8c98-b049f39579f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10512
35656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.1051235656
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.2235235917
Short name T4
Test name
Test status
Simulation time 5201190237 ps
CPU time 153.17 seconds
Started Jun 26 05:17:56 PM PDT 24
Finished Jun 26 05:20:31 PM PDT 24
Peak memory 206456 kb
Host smart-4392bc5e-6a4e-4ac7-a6de-2e729d917a0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22352
35917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.2235235917
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.1623387527
Short name T553
Test name
Test status
Simulation time 3478294909 ps
CPU time 4.11 seconds
Started Jun 26 05:18:04 PM PDT 24
Finished Jun 26 05:18:10 PM PDT 24
Peak memory 206516 kb
Host smart-302d3249-2dd5-45c0-a676-a39adbdf3f8d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1623387527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.1623387527
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.116131626
Short name T2210
Test name
Test status
Simulation time 13479533332 ps
CPU time 13.33 seconds
Started Jun 26 05:18:04 PM PDT 24
Finished Jun 26 05:18:20 PM PDT 24
Peak memory 206484 kb
Host smart-52dd56a6-db7b-4b3f-b1f0-3130d6487690
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=116131626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.116131626
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.464122041
Short name T1517
Test name
Test status
Simulation time 23380915961 ps
CPU time 22.25 seconds
Started Jun 26 05:18:04 PM PDT 24
Finished Jun 26 05:18:30 PM PDT 24
Peak memory 206476 kb
Host smart-469e4425-81e1-4ade-aff0-dbe65a5e95f5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=464122041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.464122041
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.2945910935
Short name T1546
Test name
Test status
Simulation time 152533230 ps
CPU time 0.8 seconds
Started Jun 26 05:18:04 PM PDT 24
Finished Jun 26 05:18:09 PM PDT 24
Peak memory 206228 kb
Host smart-4a30b048-6f46-4064-9985-4aa9c1a9351a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29459
10935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.2945910935
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.839991754
Short name T2285
Test name
Test status
Simulation time 143695919 ps
CPU time 0.78 seconds
Started Jun 26 05:18:02 PM PDT 24
Finished Jun 26 05:18:04 PM PDT 24
Peak memory 206120 kb
Host smart-b46df761-8529-4ede-9b6b-f6e4b9f6fa11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83999
1754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.839991754
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.2592099588
Short name T1073
Test name
Test status
Simulation time 355228982 ps
CPU time 1.16 seconds
Started Jun 26 05:18:04 PM PDT 24
Finished Jun 26 05:18:08 PM PDT 24
Peak memory 206208 kb
Host smart-c523d05a-37c3-499c-8458-cfdeef5608ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25920
99588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.2592099588
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.2386813319
Short name T1401
Test name
Test status
Simulation time 947181499 ps
CPU time 2.25 seconds
Started Jun 26 05:18:04 PM PDT 24
Finished Jun 26 05:18:09 PM PDT 24
Peak memory 206408 kb
Host smart-74cccacc-4721-4e8d-b4eb-1258d98c4302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23868
13319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.2386813319
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.4151326207
Short name T2115
Test name
Test status
Simulation time 22681977267 ps
CPU time 39.53 seconds
Started Jun 26 05:18:06 PM PDT 24
Finished Jun 26 05:18:49 PM PDT 24
Peak memory 206512 kb
Host smart-614378fa-bd06-4b84-a0cd-42485191f30e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41513
26207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.4151326207
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.1662846610
Short name T376
Test name
Test status
Simulation time 380519558 ps
CPU time 1.3 seconds
Started Jun 26 05:18:06 PM PDT 24
Finished Jun 26 05:18:10 PM PDT 24
Peak memory 206212 kb
Host smart-c8e6974e-f259-41e9-afd9-fed60ff64503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16628
46610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.1662846610
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.452322674
Short name T972
Test name
Test status
Simulation time 138095945 ps
CPU time 0.85 seconds
Started Jun 26 05:18:04 PM PDT 24
Finished Jun 26 05:18:07 PM PDT 24
Peak memory 206156 kb
Host smart-f4ef8064-a7e0-4aa2-9ade-25d5306a93ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45232
2674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.452322674
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.470247082
Short name T1427
Test name
Test status
Simulation time 40058117 ps
CPU time 0.65 seconds
Started Jun 26 05:18:06 PM PDT 24
Finished Jun 26 05:18:10 PM PDT 24
Peak memory 206136 kb
Host smart-5d386491-ee28-45df-a26e-6b35d7c413d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47024
7082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.470247082
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.412742910
Short name T1196
Test name
Test status
Simulation time 1007535801 ps
CPU time 2.14 seconds
Started Jun 26 05:18:04 PM PDT 24
Finished Jun 26 05:18:10 PM PDT 24
Peak memory 206384 kb
Host smart-419810be-ce7a-4db2-a6af-3c5e5824e2c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41274
2910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.412742910
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.861983804
Short name T1413
Test name
Test status
Simulation time 279750297 ps
CPU time 1.95 seconds
Started Jun 26 05:18:05 PM PDT 24
Finished Jun 26 05:18:10 PM PDT 24
Peak memory 206232 kb
Host smart-8eedce99-cca1-4dba-b551-b0b75741b8d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86198
3804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.861983804
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.2344044607
Short name T733
Test name
Test status
Simulation time 180523826 ps
CPU time 0.89 seconds
Started Jun 26 05:18:16 PM PDT 24
Finished Jun 26 05:18:19 PM PDT 24
Peak memory 206224 kb
Host smart-31e097ab-15ca-4613-aa0b-a6927542cc8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23440
44607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.2344044607
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.1271622534
Short name T495
Test name
Test status
Simulation time 145540206 ps
CPU time 0.74 seconds
Started Jun 26 05:18:17 PM PDT 24
Finished Jun 26 05:18:20 PM PDT 24
Peak memory 206220 kb
Host smart-68ff3c28-35cb-48a3-8de4-7ec5b16ac9b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12716
22534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.1271622534
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.3709691160
Short name T623
Test name
Test status
Simulation time 248154635 ps
CPU time 0.96 seconds
Started Jun 26 05:18:03 PM PDT 24
Finished Jun 26 05:18:06 PM PDT 24
Peak memory 206224 kb
Host smart-ffa3e07a-f72c-4275-aa93-5ba78cf6b2b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37096
91160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.3709691160
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.3737230578
Short name T72
Test name
Test status
Simulation time 9402313362 ps
CPU time 253.59 seconds
Started Jun 26 05:18:03 PM PDT 24
Finished Jun 26 05:22:19 PM PDT 24
Peak memory 206516 kb
Host smart-79246ec0-8af9-4a76-8a24-fe7be1040e14
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3737230578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.3737230578
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.917360571
Short name T1450
Test name
Test status
Simulation time 206491115 ps
CPU time 0.9 seconds
Started Jun 26 05:18:07 PM PDT 24
Finished Jun 26 05:18:11 PM PDT 24
Peak memory 206220 kb
Host smart-39ac24d0-c380-4f3b-b0a7-2a769ce8e8c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91736
0571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.917360571
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.1844115211
Short name T2072
Test name
Test status
Simulation time 23326168803 ps
CPU time 24.21 seconds
Started Jun 26 05:18:06 PM PDT 24
Finished Jun 26 05:18:33 PM PDT 24
Peak memory 205940 kb
Host smart-1007663b-f72d-45b3-b52b-76be3ec82571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18441
15211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.1844115211
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.429277028
Short name T1446
Test name
Test status
Simulation time 3286115666 ps
CPU time 3.73 seconds
Started Jun 26 05:18:03 PM PDT 24
Finished Jun 26 05:18:09 PM PDT 24
Peak memory 206240 kb
Host smart-b7bb45d4-f376-48c5-b51e-c5faa1481bd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42927
7028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.429277028
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.974827916
Short name T1539
Test name
Test status
Simulation time 9032819373 ps
CPU time 254.33 seconds
Started Jun 26 05:18:04 PM PDT 24
Finished Jun 26 05:22:21 PM PDT 24
Peak memory 206552 kb
Host smart-0c656a0b-e0c1-4d1b-b37b-faf9aecb9926
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97482
7916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.974827916
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.1128599702
Short name T1773
Test name
Test status
Simulation time 4526458283 ps
CPU time 31.37 seconds
Started Jun 26 05:18:09 PM PDT 24
Finished Jun 26 05:18:43 PM PDT 24
Peak memory 206428 kb
Host smart-0c6a438d-e4ba-412b-9dec-d9a486337471
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1128599702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.1128599702
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.4145203176
Short name T449
Test name
Test status
Simulation time 248717894 ps
CPU time 0.91 seconds
Started Jun 26 05:18:23 PM PDT 24
Finished Jun 26 05:18:26 PM PDT 24
Peak memory 206228 kb
Host smart-b020d4aa-b855-4f49-91ee-fb6a7fbec0c7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4145203176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.4145203176
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.344342295
Short name T422
Test name
Test status
Simulation time 212776633 ps
CPU time 0.85 seconds
Started Jun 26 05:18:04 PM PDT 24
Finished Jun 26 05:18:08 PM PDT 24
Peak memory 206224 kb
Host smart-6956c8b4-7517-42f8-812d-d598ba173f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34434
2295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.344342295
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.1888509754
Short name T1287
Test name
Test status
Simulation time 3740421014 ps
CPU time 101.06 seconds
Started Jun 26 05:18:04 PM PDT 24
Finished Jun 26 05:19:49 PM PDT 24
Peak memory 206484 kb
Host smart-0d482c9e-c7cb-4edd-81b3-9cae4349bef5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18885
09754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.1888509754
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.1212237425
Short name T812
Test name
Test status
Simulation time 8200053480 ps
CPU time 56.71 seconds
Started Jun 26 05:18:10 PM PDT 24
Finished Jun 26 05:19:09 PM PDT 24
Peak memory 206540 kb
Host smart-b1f92a6e-5891-4c6f-8014-e4f69c757bad
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1212237425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.1212237425
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.2920515092
Short name T2399
Test name
Test status
Simulation time 149340505 ps
CPU time 0.8 seconds
Started Jun 26 05:18:19 PM PDT 24
Finished Jun 26 05:18:23 PM PDT 24
Peak memory 206072 kb
Host smart-ab1881ff-3150-4ebe-a08c-5924c6e01d40
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2920515092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.2920515092
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.402931475
Short name T2165
Test name
Test status
Simulation time 181538692 ps
CPU time 0.8 seconds
Started Jun 26 05:18:04 PM PDT 24
Finished Jun 26 05:18:08 PM PDT 24
Peak memory 206180 kb
Host smart-929b2cc0-3b2e-4cfd-8370-a674c6bf61f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40293
1475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.402931475
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.2109042632
Short name T149
Test name
Test status
Simulation time 166441645 ps
CPU time 0.84 seconds
Started Jun 26 05:18:12 PM PDT 24
Finished Jun 26 05:18:15 PM PDT 24
Peak memory 206176 kb
Host smart-0451ae90-9996-4112-a531-0a766434f2f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21090
42632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.2109042632
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.3627915703
Short name T1350
Test name
Test status
Simulation time 169877902 ps
CPU time 0.83 seconds
Started Jun 26 05:18:12 PM PDT 24
Finished Jun 26 05:18:15 PM PDT 24
Peak memory 206120 kb
Host smart-f5d087d5-a0d2-4dbb-90ed-1185069f9a21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36279
15703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.3627915703
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.1883421724
Short name T2446
Test name
Test status
Simulation time 184763672 ps
CPU time 0.8 seconds
Started Jun 26 05:18:09 PM PDT 24
Finished Jun 26 05:18:12 PM PDT 24
Peak memory 206196 kb
Host smart-d3e8d645-79ee-4ecf-a9ea-becc8f548aa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18834
21724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.1883421724
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.3210302755
Short name T1655
Test name
Test status
Simulation time 153877825 ps
CPU time 0.8 seconds
Started Jun 26 05:18:11 PM PDT 24
Finished Jun 26 05:18:14 PM PDT 24
Peak memory 206172 kb
Host smart-2b65c921-1e04-40be-9205-ca560f277bc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32103
02755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.3210302755
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.388758494
Short name T2301
Test name
Test status
Simulation time 158255346 ps
CPU time 0.8 seconds
Started Jun 26 05:18:15 PM PDT 24
Finished Jun 26 05:18:17 PM PDT 24
Peak memory 206048 kb
Host smart-94695318-49db-4d9f-9855-2d85015268b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38875
8494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.388758494
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.1993368829
Short name T1353
Test name
Test status
Simulation time 198365963 ps
CPU time 0.89 seconds
Started Jun 26 05:18:11 PM PDT 24
Finished Jun 26 05:18:13 PM PDT 24
Peak memory 206120 kb
Host smart-6dfba9fd-4f5b-4815-bf2e-0373a2faba59
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1993368829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.1993368829
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.3554394703
Short name T1140
Test name
Test status
Simulation time 211263524 ps
CPU time 0.85 seconds
Started Jun 26 05:18:15 PM PDT 24
Finished Jun 26 05:18:17 PM PDT 24
Peak memory 206204 kb
Host smart-91e7d544-c2e2-40be-bc6f-3991b7fe357b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35543
94703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.3554394703
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.1933794570
Short name T1434
Test name
Test status
Simulation time 60963496 ps
CPU time 0.67 seconds
Started Jun 26 05:18:12 PM PDT 24
Finished Jun 26 05:18:15 PM PDT 24
Peak memory 206204 kb
Host smart-0ea9ee78-8b0b-4f7d-901f-d1dab6db576a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19337
94570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.1933794570
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.203325681
Short name T2052
Test name
Test status
Simulation time 14555832965 ps
CPU time 31.97 seconds
Started Jun 26 05:18:12 PM PDT 24
Finished Jun 26 05:18:46 PM PDT 24
Peak memory 206564 kb
Host smart-843ad8a1-c257-4e34-b9a9-9027713bab66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20332
5681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.203325681
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.717238671
Short name T1809
Test name
Test status
Simulation time 186259200 ps
CPU time 0.85 seconds
Started Jun 26 05:18:12 PM PDT 24
Finished Jun 26 05:18:15 PM PDT 24
Peak memory 206124 kb
Host smart-3fe3bf33-e77a-483f-be91-915cfc5dd95a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71723
8671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.717238671
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.1963856295
Short name T1603
Test name
Test status
Simulation time 177057244 ps
CPU time 0.83 seconds
Started Jun 26 05:18:10 PM PDT 24
Finished Jun 26 05:18:13 PM PDT 24
Peak memory 206192 kb
Host smart-09d47f1a-86d9-4cae-9d9e-95f5ab9e6cb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19638
56295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.1963856295
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.894693243
Short name T1101
Test name
Test status
Simulation time 214124681 ps
CPU time 0.84 seconds
Started Jun 26 05:18:17 PM PDT 24
Finished Jun 26 05:18:20 PM PDT 24
Peak memory 206132 kb
Host smart-28788015-4a1f-41ee-aa95-0fbf4a4c433e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89469
3243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.894693243
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.1497695535
Short name T1898
Test name
Test status
Simulation time 169110036 ps
CPU time 0.79 seconds
Started Jun 26 05:18:10 PM PDT 24
Finished Jun 26 05:18:13 PM PDT 24
Peak memory 206100 kb
Host smart-d1cf6e4d-c7f1-4ca4-b680-5d60152e7e82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14976
95535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.1497695535
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.1519248574
Short name T1599
Test name
Test status
Simulation time 143472686 ps
CPU time 0.76 seconds
Started Jun 26 05:18:13 PM PDT 24
Finished Jun 26 05:18:16 PM PDT 24
Peak memory 206124 kb
Host smart-8bbab914-84c0-4736-b45b-3250568153a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15192
48574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.1519248574
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.688929138
Short name T1369
Test name
Test status
Simulation time 163043329 ps
CPU time 0.83 seconds
Started Jun 26 05:18:11 PM PDT 24
Finished Jun 26 05:18:14 PM PDT 24
Peak memory 206136 kb
Host smart-09f41ece-755a-44fb-87de-e01aa851742d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68892
9138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.688929138
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.1986858556
Short name T1997
Test name
Test status
Simulation time 154556515 ps
CPU time 0.78 seconds
Started Jun 26 05:18:10 PM PDT 24
Finished Jun 26 05:18:13 PM PDT 24
Peak memory 206192 kb
Host smart-30786034-d162-483f-8bf5-f43f2c680eda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19868
58556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.1986858556
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.4173954178
Short name T2147
Test name
Test status
Simulation time 212083193 ps
CPU time 0.92 seconds
Started Jun 26 05:18:10 PM PDT 24
Finished Jun 26 05:18:13 PM PDT 24
Peak memory 206232 kb
Host smart-7bee7a7f-e364-42d0-a4a9-7dce83801843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41739
54178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.4173954178
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.2066746622
Short name T2204
Test name
Test status
Simulation time 6950805704 ps
CPU time 49.73 seconds
Started Jun 26 05:18:15 PM PDT 24
Finished Jun 26 05:19:06 PM PDT 24
Peak memory 206396 kb
Host smart-4260d83b-3e79-4ecc-8535-68b073215b3e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2066746622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.2066746622
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.3664831364
Short name T950
Test name
Test status
Simulation time 161455582 ps
CPU time 0.81 seconds
Started Jun 26 05:18:10 PM PDT 24
Finished Jun 26 05:18:12 PM PDT 24
Peak memory 206128 kb
Host smart-9e7f768e-5147-4316-a28a-4c0cc8805f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36648
31364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.3664831364
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.1246454794
Short name T348
Test name
Test status
Simulation time 177702991 ps
CPU time 0.83 seconds
Started Jun 26 05:18:12 PM PDT 24
Finished Jun 26 05:18:15 PM PDT 24
Peak memory 206204 kb
Host smart-2d0b6a29-1800-4ac9-a466-0a4d3c77ada1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12464
54794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.1246454794
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.140749964
Short name T2539
Test name
Test status
Simulation time 4118591865 ps
CPU time 29.02 seconds
Started Jun 26 05:18:12 PM PDT 24
Finished Jun 26 05:18:42 PM PDT 24
Peak memory 206496 kb
Host smart-eeecfa3c-b31c-453a-8517-f5003d893e9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14074
9964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.140749964
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.2867638992
Short name T2410
Test name
Test status
Simulation time 3775593038 ps
CPU time 4.63 seconds
Started Jun 26 05:18:17 PM PDT 24
Finished Jun 26 05:18:23 PM PDT 24
Peak memory 206500 kb
Host smart-9199f372-4691-40d1-8c08-6475c968498b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2867638992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.2867638992
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.1289485419
Short name T678
Test name
Test status
Simulation time 13362172972 ps
CPU time 14.82 seconds
Started Jun 26 05:18:18 PM PDT 24
Finished Jun 26 05:18:35 PM PDT 24
Peak memory 206576 kb
Host smart-72d5f5ea-3ac7-44c5-b19f-07509086af58
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1289485419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.1289485419
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.2274508990
Short name T2346
Test name
Test status
Simulation time 23384867411 ps
CPU time 24.63 seconds
Started Jun 26 05:18:20 PM PDT 24
Finished Jun 26 05:18:48 PM PDT 24
Peak memory 206516 kb
Host smart-976a0517-8491-4a70-a4f3-332241472c1a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2274508990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.2274508990
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.1391263499
Short name T1305
Test name
Test status
Simulation time 189036961 ps
CPU time 0.91 seconds
Started Jun 26 05:18:17 PM PDT 24
Finished Jun 26 05:18:21 PM PDT 24
Peak memory 206176 kb
Host smart-5dfaa477-eaae-4558-9efa-71fdd18a2533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13912
63499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.1391263499
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.3875683899
Short name T1931
Test name
Test status
Simulation time 158398420 ps
CPU time 0.82 seconds
Started Jun 26 05:18:17 PM PDT 24
Finished Jun 26 05:18:21 PM PDT 24
Peak memory 206204 kb
Host smart-2ddd5e37-3c07-44ca-9e51-007a0380ddef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38756
83899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.3875683899
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.7399793
Short name T1792
Test name
Test status
Simulation time 407454264 ps
CPU time 1.29 seconds
Started Jun 26 05:18:19 PM PDT 24
Finished Jun 26 05:18:24 PM PDT 24
Peak memory 206056 kb
Host smart-11875803-2072-4b81-90b5-bd6ad702d4ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73997
93 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.7399793
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.2574815854
Short name T172
Test name
Test status
Simulation time 1290778087 ps
CPU time 2.73 seconds
Started Jun 26 05:18:16 PM PDT 24
Finished Jun 26 05:18:21 PM PDT 24
Peak memory 206448 kb
Host smart-9fc81219-74e7-4c5c-b158-6c4e8850e328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25748
15854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.2574815854
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.2389926865
Short name T1588
Test name
Test status
Simulation time 12776124948 ps
CPU time 28.94 seconds
Started Jun 26 05:18:16 PM PDT 24
Finished Jun 26 05:18:47 PM PDT 24
Peak memory 206476 kb
Host smart-c441383c-8edf-49e8-8c8c-1c3df2e18cc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23899
26865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.2389926865
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.232280760
Short name T1189
Test name
Test status
Simulation time 475016866 ps
CPU time 1.42 seconds
Started Jun 26 05:18:20 PM PDT 24
Finished Jun 26 05:18:25 PM PDT 24
Peak memory 206400 kb
Host smart-4ad56200-33ec-4769-ac9c-3a3f1684abbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23228
0760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.232280760
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.3370510986
Short name T2326
Test name
Test status
Simulation time 202478114 ps
CPU time 0.8 seconds
Started Jun 26 05:18:18 PM PDT 24
Finished Jun 26 05:18:23 PM PDT 24
Peak memory 206208 kb
Host smart-4c9ab233-32da-4bef-9feb-09397dea549a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33705
10986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.3370510986
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.4153087836
Short name T1919
Test name
Test status
Simulation time 43438693 ps
CPU time 0.67 seconds
Started Jun 26 05:18:17 PM PDT 24
Finished Jun 26 05:18:20 PM PDT 24
Peak memory 206184 kb
Host smart-b491b8e1-49ad-4779-9f8b-8b3adc02a3a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41530
87836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.4153087836
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.32727432
Short name T2264
Test name
Test status
Simulation time 876237010 ps
CPU time 2.37 seconds
Started Jun 26 05:18:18 PM PDT 24
Finished Jun 26 05:18:24 PM PDT 24
Peak memory 206360 kb
Host smart-9d593ffb-3fd5-4197-aa2a-006865a4a357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32727
432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.32727432
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.1330988330
Short name T603
Test name
Test status
Simulation time 208144817 ps
CPU time 2.35 seconds
Started Jun 26 05:18:20 PM PDT 24
Finished Jun 26 05:18:26 PM PDT 24
Peak memory 206644 kb
Host smart-e379b25e-5ce9-4b22-9eb4-b4732392fb37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13309
88330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.1330988330
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.4225553083
Short name T1226
Test name
Test status
Simulation time 198063796 ps
CPU time 0.85 seconds
Started Jun 26 05:18:26 PM PDT 24
Finished Jun 26 05:18:30 PM PDT 24
Peak memory 206216 kb
Host smart-e8a62179-d967-44ca-871d-ca06f4c4b404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42255
53083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.4225553083
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.1548117860
Short name T793
Test name
Test status
Simulation time 167516679 ps
CPU time 0.8 seconds
Started Jun 26 05:18:26 PM PDT 24
Finished Jun 26 05:18:31 PM PDT 24
Peak memory 206132 kb
Host smart-16e5c59a-7da2-4cf7-8b5e-ad5db3627859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15481
17860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.1548117860
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.160317239
Short name T854
Test name
Test status
Simulation time 241910158 ps
CPU time 0.93 seconds
Started Jun 26 05:18:17 PM PDT 24
Finished Jun 26 05:18:20 PM PDT 24
Peak memory 206220 kb
Host smart-bb1f5e27-e412-4bf5-aeaf-8c29677124fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16031
7239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.160317239
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.686195198
Short name T498
Test name
Test status
Simulation time 244106426 ps
CPU time 0.93 seconds
Started Jun 26 05:18:17 PM PDT 24
Finished Jun 26 05:18:20 PM PDT 24
Peak memory 206208 kb
Host smart-6532b15d-48c3-4190-95d6-1d0547d8bbcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68619
5198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.686195198
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.1172367725
Short name T2186
Test name
Test status
Simulation time 23353979872 ps
CPU time 22.72 seconds
Started Jun 26 05:18:19 PM PDT 24
Finished Jun 26 05:18:45 PM PDT 24
Peak memory 206316 kb
Host smart-dcf4f451-47c8-424b-b89d-d8f60e1b19dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11723
67725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.1172367725
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.2765704772
Short name T368
Test name
Test status
Simulation time 3337755162 ps
CPU time 3.84 seconds
Started Jun 26 05:18:20 PM PDT 24
Finished Jun 26 05:18:27 PM PDT 24
Peak memory 206448 kb
Host smart-5f9d7641-62ee-40e3-a13f-f1d1d92d2805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27657
04772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.2765704772
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.893690433
Short name T2050
Test name
Test status
Simulation time 7858340314 ps
CPU time 214.25 seconds
Started Jun 26 05:18:25 PM PDT 24
Finished Jun 26 05:22:02 PM PDT 24
Peak memory 206584 kb
Host smart-2a504735-1ba9-4c6c-a5ab-93f703f5f70e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89369
0433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.893690433
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.2618187108
Short name T724
Test name
Test status
Simulation time 3230299970 ps
CPU time 84.64 seconds
Started Jun 26 05:18:25 PM PDT 24
Finished Jun 26 05:19:53 PM PDT 24
Peak memory 206476 kb
Host smart-d33945d5-83d0-4a2a-9f57-e6c61bc40d9a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2618187108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.2618187108
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.3695934918
Short name T1062
Test name
Test status
Simulation time 243404229 ps
CPU time 0.89 seconds
Started Jun 26 05:18:25 PM PDT 24
Finished Jun 26 05:18:29 PM PDT 24
Peak memory 206196 kb
Host smart-28569b4d-effe-4d86-a142-2fbc3b6a2ee9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3695934918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.3695934918
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.3307118508
Short name T2552
Test name
Test status
Simulation time 186417090 ps
CPU time 0.87 seconds
Started Jun 26 05:18:27 PM PDT 24
Finished Jun 26 05:18:31 PM PDT 24
Peak memory 206176 kb
Host smart-cfe3ac50-5acd-407a-bf11-31cc4bcc574e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33071
18508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.3307118508
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.2973032169
Short name T2290
Test name
Test status
Simulation time 4252241581 ps
CPU time 117.81 seconds
Started Jun 26 05:18:24 PM PDT 24
Finished Jun 26 05:20:24 PM PDT 24
Peak memory 206396 kb
Host smart-ffbe3dad-19c4-4f5c-a8d8-1b0a085178d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29730
32169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.2973032169
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.544688977
Short name T2142
Test name
Test status
Simulation time 2998405597 ps
CPU time 21.45 seconds
Started Jun 26 05:18:25 PM PDT 24
Finished Jun 26 05:18:50 PM PDT 24
Peak memory 206656 kb
Host smart-d0f2df05-1e78-4a30-86c8-d378cc2b2101
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=544688977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.544688977
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.672642547
Short name T1817
Test name
Test status
Simulation time 146719484 ps
CPU time 0.81 seconds
Started Jun 26 05:18:24 PM PDT 24
Finished Jun 26 05:18:27 PM PDT 24
Peak memory 206216 kb
Host smart-a89b6b42-cb06-49a5-b953-d8d21cf33824
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=672642547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.672642547
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.1408548579
Short name T995
Test name
Test status
Simulation time 179830410 ps
CPU time 0.77 seconds
Started Jun 26 05:18:29 PM PDT 24
Finished Jun 26 05:18:33 PM PDT 24
Peak memory 206120 kb
Host smart-38284197-f581-4f87-9085-0c6b9abaa6ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14085
48579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.1408548579
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.3272838803
Short name T141
Test name
Test status
Simulation time 205815657 ps
CPU time 0.86 seconds
Started Jun 26 05:18:24 PM PDT 24
Finished Jun 26 05:18:27 PM PDT 24
Peak memory 206180 kb
Host smart-8ad10e04-f502-4d2c-a9bd-d1aec188f451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32728
38803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.3272838803
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.72025402
Short name T1411
Test name
Test status
Simulation time 181474550 ps
CPU time 0.84 seconds
Started Jun 26 05:18:29 PM PDT 24
Finished Jun 26 05:18:32 PM PDT 24
Peak memory 206132 kb
Host smart-42de42a9-4bb3-43cb-8346-00730a320e50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72025
402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.72025402
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.1098897163
Short name T1927
Test name
Test status
Simulation time 238390835 ps
CPU time 0.92 seconds
Started Jun 26 05:18:30 PM PDT 24
Finished Jun 26 05:18:33 PM PDT 24
Peak memory 206208 kb
Host smart-3cd62f5c-ade8-4b80-878e-8cf95b8f3a60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10988
97163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.1098897163
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.841153791
Short name T2001
Test name
Test status
Simulation time 161700525 ps
CPU time 0.8 seconds
Started Jun 26 05:18:26 PM PDT 24
Finished Jun 26 05:18:30 PM PDT 24
Peak memory 206216 kb
Host smart-f6a31d1b-b074-4387-9393-da11374d13b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84115
3791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.841153791
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.698999693
Short name T866
Test name
Test status
Simulation time 216649924 ps
CPU time 0.9 seconds
Started Jun 26 05:18:24 PM PDT 24
Finished Jun 26 05:18:27 PM PDT 24
Peak memory 206200 kb
Host smart-3a413ed9-c270-4147-a2d4-359517d57389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69899
9693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.698999693
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.2695230597
Short name T1422
Test name
Test status
Simulation time 268730692 ps
CPU time 0.98 seconds
Started Jun 26 05:18:24 PM PDT 24
Finished Jun 26 05:18:28 PM PDT 24
Peak memory 206228 kb
Host smart-ca3e9296-2f49-46ed-8459-22334774a0f3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2695230597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.2695230597
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.2731735339
Short name T2056
Test name
Test status
Simulation time 194409056 ps
CPU time 0.87 seconds
Started Jun 26 05:18:27 PM PDT 24
Finished Jun 26 05:18:31 PM PDT 24
Peak memory 206176 kb
Host smart-0480a14e-ebf6-4a9e-adb9-72606ae62b70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27317
35339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.2731735339
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.1280443429
Short name T22
Test name
Test status
Simulation time 35200036 ps
CPU time 0.65 seconds
Started Jun 26 05:18:26 PM PDT 24
Finished Jun 26 05:18:31 PM PDT 24
Peak memory 206120 kb
Host smart-75817918-4193-4af1-849c-573e7af7d58e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12804
43429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.1280443429
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.114539101
Short name T264
Test name
Test status
Simulation time 11778290492 ps
CPU time 29.53 seconds
Started Jun 26 05:18:26 PM PDT 24
Finished Jun 26 05:19:00 PM PDT 24
Peak memory 206472 kb
Host smart-cc97965e-edd2-488f-888e-f8b0354333d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11453
9101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.114539101
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.2290892267
Short name T1522
Test name
Test status
Simulation time 215093501 ps
CPU time 0.86 seconds
Started Jun 26 05:18:26 PM PDT 24
Finished Jun 26 05:18:30 PM PDT 24
Peak memory 206112 kb
Host smart-071c8524-8ea7-4e81-a875-f612a63b9c62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22908
92267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.2290892267
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.557376205
Short name T1357
Test name
Test status
Simulation time 187289220 ps
CPU time 0.86 seconds
Started Jun 26 05:18:25 PM PDT 24
Finished Jun 26 05:18:29 PM PDT 24
Peak memory 206108 kb
Host smart-ddd427ac-8a63-4128-8fac-3efc52eccd45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55737
6205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.557376205
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.3329891743
Short name T616
Test name
Test status
Simulation time 210857108 ps
CPU time 0.88 seconds
Started Jun 26 05:18:24 PM PDT 24
Finished Jun 26 05:18:28 PM PDT 24
Peak memory 206200 kb
Host smart-19186189-1188-4e4e-b4f4-7a6aa3f91f12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33298
91743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.3329891743
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.3945583269
Short name T1607
Test name
Test status
Simulation time 199606946 ps
CPU time 0.84 seconds
Started Jun 26 05:18:28 PM PDT 24
Finished Jun 26 05:18:32 PM PDT 24
Peak memory 206120 kb
Host smart-99b96066-f2cf-4ecb-aa05-5c8dcc7ba83e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39455
83269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.3945583269
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.3197954459
Short name T499
Test name
Test status
Simulation time 200271752 ps
CPU time 0.82 seconds
Started Jun 26 05:18:25 PM PDT 24
Finished Jun 26 05:18:29 PM PDT 24
Peak memory 206176 kb
Host smart-4f890d2c-3c02-4a1d-b769-3b1498b1320f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31979
54459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.3197954459
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.572711340
Short name T2140
Test name
Test status
Simulation time 152916904 ps
CPU time 0.78 seconds
Started Jun 26 05:18:29 PM PDT 24
Finished Jun 26 05:18:33 PM PDT 24
Peak memory 206116 kb
Host smart-254aefe5-cd74-4326-aa1d-7f1c350ccceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57271
1340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.572711340
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.3615787611
Short name T607
Test name
Test status
Simulation time 180097500 ps
CPU time 0.82 seconds
Started Jun 26 05:18:24 PM PDT 24
Finished Jun 26 05:18:27 PM PDT 24
Peak memory 206236 kb
Host smart-5b5f0f12-3077-41fd-85d0-c485e4ce919c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36157
87611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.3615787611
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.860958052
Short name T2069
Test name
Test status
Simulation time 226060932 ps
CPU time 0.9 seconds
Started Jun 26 05:18:24 PM PDT 24
Finished Jun 26 05:18:26 PM PDT 24
Peak memory 206148 kb
Host smart-29ebf1a4-7a97-4b1e-be06-1ae8b1eaa99a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86095
8052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.860958052
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.2828312889
Short name T996
Test name
Test status
Simulation time 5646417691 ps
CPU time 39.37 seconds
Started Jun 26 05:18:27 PM PDT 24
Finished Jun 26 05:19:09 PM PDT 24
Peak memory 206464 kb
Host smart-372f3c10-0a9f-41a4-8472-450fa9d80f05
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2828312889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.2828312889
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.272847474
Short name T2444
Test name
Test status
Simulation time 183965617 ps
CPU time 0.82 seconds
Started Jun 26 05:18:25 PM PDT 24
Finished Jun 26 05:18:29 PM PDT 24
Peak memory 206228 kb
Host smart-73eb7049-2465-441c-8ced-6a5946aadc73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27284
7474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.272847474
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.3278370132
Short name T2479
Test name
Test status
Simulation time 212667653 ps
CPU time 0.81 seconds
Started Jun 26 05:18:24 PM PDT 24
Finished Jun 26 05:18:28 PM PDT 24
Peak memory 206124 kb
Host smart-e9bdf703-edd9-4a3a-9086-02d86e0796e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32783
70132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.3278370132
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.3269406340
Short name T1810
Test name
Test status
Simulation time 4429487028 ps
CPU time 117.42 seconds
Started Jun 26 05:18:30 PM PDT 24
Finished Jun 26 05:20:30 PM PDT 24
Peak memory 206508 kb
Host smart-f703f443-534f-46a7-aa2b-330a7b416f7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32694
06340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.3269406340
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.1276751319
Short name T229
Test name
Test status
Simulation time 3809254378 ps
CPU time 4.66 seconds
Started Jun 26 05:18:29 PM PDT 24
Finished Jun 26 05:18:36 PM PDT 24
Peak memory 206456 kb
Host smart-c05e2ad4-fe48-4aa7-9451-42944c4da987
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1276751319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.1276751319
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.2552925403
Short name T7
Test name
Test status
Simulation time 13417971438 ps
CPU time 12.7 seconds
Started Jun 26 05:18:26 PM PDT 24
Finished Jun 26 05:18:43 PM PDT 24
Peak memory 206244 kb
Host smart-89cf9336-d6ab-40e3-a017-e89bb3714500
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2552925403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.2552925403
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.3041687120
Short name T880
Test name
Test status
Simulation time 23406814120 ps
CPU time 23.47 seconds
Started Jun 26 05:18:25 PM PDT 24
Finished Jun 26 05:18:52 PM PDT 24
Peak memory 206328 kb
Host smart-73b83bfe-1914-4b0e-9e04-6972d0209972
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3041687120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.3041687120
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.1181122504
Short name T758
Test name
Test status
Simulation time 146908132 ps
CPU time 0.81 seconds
Started Jun 26 05:18:25 PM PDT 24
Finished Jun 26 05:18:30 PM PDT 24
Peak memory 206136 kb
Host smart-f81107da-162c-4350-ae4d-157c9dd41a2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11811
22504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.1181122504
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.1143164140
Short name T1568
Test name
Test status
Simulation time 142580928 ps
CPU time 0.81 seconds
Started Jun 26 05:18:26 PM PDT 24
Finished Jun 26 05:18:30 PM PDT 24
Peak memory 206120 kb
Host smart-b69d6e54-7d56-456d-8192-8fa4abdfad77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11431
64140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.1143164140
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.3226015361
Short name T2222
Test name
Test status
Simulation time 360302443 ps
CPU time 1.2 seconds
Started Jun 26 05:18:23 PM PDT 24
Finished Jun 26 05:18:26 PM PDT 24
Peak memory 206212 kb
Host smart-ad796401-d8d5-4e73-8b65-551ecf571b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32260
15361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.3226015361
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.1508510427
Short name T689
Test name
Test status
Simulation time 1044327396 ps
CPU time 2.34 seconds
Started Jun 26 05:18:32 PM PDT 24
Finished Jun 26 05:18:36 PM PDT 24
Peak memory 206408 kb
Host smart-4cdc8fd8-6d12-4a50-bf81-18269effd5aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15085
10427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.1508510427
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.3413923210
Short name T1240
Test name
Test status
Simulation time 8431891198 ps
CPU time 17.03 seconds
Started Jun 26 05:18:31 PM PDT 24
Finished Jun 26 05:18:50 PM PDT 24
Peak memory 206448 kb
Host smart-8f7d7927-2bab-4747-8a79-350fc3b813b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34139
23210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.3413923210
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.4034362571
Short name T1216
Test name
Test status
Simulation time 436092383 ps
CPU time 1.3 seconds
Started Jun 26 05:18:30 PM PDT 24
Finished Jun 26 05:18:33 PM PDT 24
Peak memory 206196 kb
Host smart-cc08a1f3-7a6a-450d-abc6-54e2adc1f466
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40343
62571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.4034362571
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.1908375429
Short name T2191
Test name
Test status
Simulation time 160311471 ps
CPU time 0.78 seconds
Started Jun 26 05:18:35 PM PDT 24
Finished Jun 26 05:18:37 PM PDT 24
Peak memory 206120 kb
Host smart-1204bea3-27c4-4951-9d9c-db05d6e26987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19083
75429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.1908375429
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.308993018
Short name T258
Test name
Test status
Simulation time 73284996 ps
CPU time 0.69 seconds
Started Jun 26 05:18:32 PM PDT 24
Finished Jun 26 05:18:34 PM PDT 24
Peak memory 206128 kb
Host smart-5a8f061d-cb62-4233-86a9-ae2b1d7ac1e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30899
3018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.308993018
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.2650468329
Short name T1179
Test name
Test status
Simulation time 1045977448 ps
CPU time 2.32 seconds
Started Jun 26 05:18:35 PM PDT 24
Finished Jun 26 05:18:39 PM PDT 24
Peak memory 206408 kb
Host smart-9220ed87-db3a-409b-a5a4-f72402a6a2a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26504
68329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.2650468329
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.4273281572
Short name T1215
Test name
Test status
Simulation time 266201489 ps
CPU time 1.84 seconds
Started Jun 26 05:18:30 PM PDT 24
Finished Jun 26 05:18:34 PM PDT 24
Peak memory 206368 kb
Host smart-7c8fb709-0bbe-4c8a-918e-b038b4833dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42732
81572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.4273281572
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.465499437
Short name T115
Test name
Test status
Simulation time 248081729 ps
CPU time 0.96 seconds
Started Jun 26 05:18:38 PM PDT 24
Finished Jun 26 05:18:40 PM PDT 24
Peak memory 206192 kb
Host smart-0c3564fd-ce8b-4fc5-bc67-51b5d6bc082a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46549
9437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.465499437
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.4290145598
Short name T578
Test name
Test status
Simulation time 194559806 ps
CPU time 0.78 seconds
Started Jun 26 05:18:38 PM PDT 24
Finished Jun 26 05:18:40 PM PDT 24
Peak memory 206148 kb
Host smart-fb3e819c-f6a4-487f-9ae9-5eaf001079f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42901
45598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.4290145598
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.1209826848
Short name T653
Test name
Test status
Simulation time 244021830 ps
CPU time 0.89 seconds
Started Jun 26 05:18:29 PM PDT 24
Finished Jun 26 05:18:32 PM PDT 24
Peak memory 206196 kb
Host smart-8dcb0bdc-2d17-4d0b-83be-94541d284841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12098
26848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.1209826848
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.646049777
Short name T1303
Test name
Test status
Simulation time 244348911 ps
CPU time 0.91 seconds
Started Jun 26 05:18:33 PM PDT 24
Finished Jun 26 05:18:36 PM PDT 24
Peak memory 206220 kb
Host smart-bbc87c14-1590-4c90-9703-86b15b5eb837
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64604
9777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.646049777
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.2678786962
Short name T595
Test name
Test status
Simulation time 23326742099 ps
CPU time 22.73 seconds
Started Jun 26 05:18:32 PM PDT 24
Finished Jun 26 05:18:57 PM PDT 24
Peak memory 206308 kb
Host smart-875b5365-07ab-4863-a3f9-098ee6472eb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26787
86962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.2678786962
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.2039716569
Short name T1331
Test name
Test status
Simulation time 3348559217 ps
CPU time 3.58 seconds
Started Jun 26 05:18:29 PM PDT 24
Finished Jun 26 05:18:35 PM PDT 24
Peak memory 206132 kb
Host smart-2a1b4a99-f4d3-494d-8047-d9d51be8d6c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20397
16569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.2039716569
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.2767230899
Short name T1462
Test name
Test status
Simulation time 8979585417 ps
CPU time 232.79 seconds
Started Jun 26 05:18:32 PM PDT 24
Finished Jun 26 05:22:27 PM PDT 24
Peak memory 206456 kb
Host smart-ad297db1-d21d-4f09-a2b8-a5cd570910b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27672
30899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.2767230899
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.3001490416
Short name T1134
Test name
Test status
Simulation time 3644726629 ps
CPU time 36.98 seconds
Started Jun 26 05:18:32 PM PDT 24
Finished Jun 26 05:19:11 PM PDT 24
Peak memory 206384 kb
Host smart-b518642b-680f-4193-9a23-4e530b3a7a0e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3001490416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.3001490416
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.488636192
Short name T535
Test name
Test status
Simulation time 256758385 ps
CPU time 0.93 seconds
Started Jun 26 05:18:39 PM PDT 24
Finished Jun 26 05:18:41 PM PDT 24
Peak memory 206152 kb
Host smart-a53a557d-bf31-4189-abf5-f7df1b022a3b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=488636192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.488636192
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.2896929205
Short name T1082
Test name
Test status
Simulation time 185329808 ps
CPU time 0.84 seconds
Started Jun 26 05:18:37 PM PDT 24
Finished Jun 26 05:18:38 PM PDT 24
Peak memory 206172 kb
Host smart-51d63c9e-af13-4501-9ae0-777cf3e8bb40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28969
29205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.2896929205
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.1089976612
Short name T708
Test name
Test status
Simulation time 3458791721 ps
CPU time 23.92 seconds
Started Jun 26 05:18:31 PM PDT 24
Finished Jun 26 05:18:57 PM PDT 24
Peak memory 206536 kb
Host smart-54265b5a-c89d-4623-a096-e2e542537d97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10899
76612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.1089976612
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.821222379
Short name T1938
Test name
Test status
Simulation time 3336058185 ps
CPU time 86.96 seconds
Started Jun 26 05:18:37 PM PDT 24
Finished Jun 26 05:20:06 PM PDT 24
Peak memory 206428 kb
Host smart-d46234da-75f3-41bc-b3bb-c842884abc25
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=821222379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.821222379
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.3996736152
Short name T1783
Test name
Test status
Simulation time 174617144 ps
CPU time 0.8 seconds
Started Jun 26 05:18:40 PM PDT 24
Finished Jun 26 05:18:42 PM PDT 24
Peak memory 206148 kb
Host smart-1b41c95e-ca26-4c20-8efa-8988c04b0975
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3996736152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.3996736152
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.4137820366
Short name T858
Test name
Test status
Simulation time 161675317 ps
CPU time 0.8 seconds
Started Jun 26 05:18:38 PM PDT 24
Finished Jun 26 05:18:40 PM PDT 24
Peak memory 206176 kb
Host smart-f5769bf8-e41c-4bce-b765-c91bb26a4de5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41378
20366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.4137820366
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.2832573007
Short name T2194
Test name
Test status
Simulation time 189827769 ps
CPU time 0.83 seconds
Started Jun 26 05:18:31 PM PDT 24
Finished Jun 26 05:18:34 PM PDT 24
Peak memory 206176 kb
Host smart-dca70a6e-a1d9-4325-8647-d55a2f20884a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28325
73007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.2832573007
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.2561645200
Short name T1141
Test name
Test status
Simulation time 171142849 ps
CPU time 0.82 seconds
Started Jun 26 05:18:30 PM PDT 24
Finished Jun 26 05:18:33 PM PDT 24
Peak memory 206176 kb
Host smart-ae68ba05-41a0-460f-8113-05f1680de86f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25616
45200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.2561645200
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.1067299643
Short name T1244
Test name
Test status
Simulation time 183000871 ps
CPU time 0.83 seconds
Started Jun 26 05:18:33 PM PDT 24
Finished Jun 26 05:18:36 PM PDT 24
Peak memory 206196 kb
Host smart-86b10616-5f65-49fe-97da-359b89318dd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10672
99643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.1067299643
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.2965282242
Short name T779
Test name
Test status
Simulation time 142459630 ps
CPU time 0.8 seconds
Started Jun 26 05:18:34 PM PDT 24
Finished Jun 26 05:18:37 PM PDT 24
Peak memory 206120 kb
Host smart-e039a0aa-5c01-4d75-a672-a856f6f9045e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29652
82242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.2965282242
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.3682237122
Short name T1871
Test name
Test status
Simulation time 153569830 ps
CPU time 0.8 seconds
Started Jun 26 05:18:40 PM PDT 24
Finished Jun 26 05:18:42 PM PDT 24
Peak memory 206084 kb
Host smart-c0edb559-dbfa-4ef2-90af-35d8e3f10322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36822
37122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.3682237122
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.519838591
Short name T1709
Test name
Test status
Simulation time 293064877 ps
CPU time 1.02 seconds
Started Jun 26 05:18:38 PM PDT 24
Finished Jun 26 05:18:40 PM PDT 24
Peak memory 206196 kb
Host smart-6fcd6f33-5453-4fe9-b570-6f3cd85d6d35
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=519838591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.519838591
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.2763974103
Short name T2205
Test name
Test status
Simulation time 191034232 ps
CPU time 0.79 seconds
Started Jun 26 05:18:34 PM PDT 24
Finished Jun 26 05:18:36 PM PDT 24
Peak memory 206128 kb
Host smart-00e050fb-3137-49ef-9e7a-925836fd59ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27639
74103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.2763974103
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.2661347804
Short name T31
Test name
Test status
Simulation time 84052751 ps
CPU time 0.71 seconds
Started Jun 26 05:18:43 PM PDT 24
Finished Jun 26 05:18:44 PM PDT 24
Peak memory 206092 kb
Host smart-7076a628-afdf-4c5b-8461-6e51d522b081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26613
47804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.2661347804
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.4167193855
Short name T1043
Test name
Test status
Simulation time 11110641894 ps
CPU time 27.25 seconds
Started Jun 26 05:18:30 PM PDT 24
Finished Jun 26 05:19:00 PM PDT 24
Peak memory 206476 kb
Host smart-2efb55c3-9b5d-4544-ae83-87861a7c675d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41671
93855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.4167193855
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.4198457634
Short name T2117
Test name
Test status
Simulation time 196348483 ps
CPU time 0.83 seconds
Started Jun 26 05:18:32 PM PDT 24
Finished Jun 26 05:18:35 PM PDT 24
Peak memory 206112 kb
Host smart-47f90e66-457b-42e3-b91e-f2e175f44556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41984
57634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.4198457634
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.603234162
Short name T1110
Test name
Test status
Simulation time 200703283 ps
CPU time 0.85 seconds
Started Jun 26 05:18:35 PM PDT 24
Finished Jun 26 05:18:37 PM PDT 24
Peak memory 206212 kb
Host smart-51b5b269-4def-40a0-be48-c5e4ab3c6a1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60323
4162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.603234162
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.3031655583
Short name T1586
Test name
Test status
Simulation time 223165790 ps
CPU time 0.86 seconds
Started Jun 26 05:18:45 PM PDT 24
Finished Jun 26 05:18:47 PM PDT 24
Peak memory 206148 kb
Host smart-75396ae9-e8ee-49c1-b951-4e4eebdf0e13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30316
55583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.3031655583
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.1025782325
Short name T287
Test name
Test status
Simulation time 170686783 ps
CPU time 0.85 seconds
Started Jun 26 05:18:35 PM PDT 24
Finished Jun 26 05:18:37 PM PDT 24
Peak memory 206124 kb
Host smart-1a7a6424-c3db-477c-8a86-5ab7af760b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10257
82325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.1025782325
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.2376573154
Short name T1665
Test name
Test status
Simulation time 196015510 ps
CPU time 0.82 seconds
Started Jun 26 05:18:29 PM PDT 24
Finished Jun 26 05:18:33 PM PDT 24
Peak memory 206228 kb
Host smart-83c5ce46-24ed-4976-8466-5b1501a6d060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23765
73154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.2376573154
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.172724441
Short name T1813
Test name
Test status
Simulation time 186229023 ps
CPU time 0.78 seconds
Started Jun 26 05:18:41 PM PDT 24
Finished Jun 26 05:18:42 PM PDT 24
Peak memory 206116 kb
Host smart-17ad1fa3-9488-4f9d-98d3-131ca8672082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17272
4441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.172724441
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.3652216765
Short name T2201
Test name
Test status
Simulation time 163476305 ps
CPU time 0.83 seconds
Started Jun 26 05:18:30 PM PDT 24
Finished Jun 26 05:18:33 PM PDT 24
Peak memory 206140 kb
Host smart-9394849e-9ef6-427b-aed5-4dd70c524ca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36522
16765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.3652216765
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.2135243971
Short name T1972
Test name
Test status
Simulation time 220827656 ps
CPU time 0.92 seconds
Started Jun 26 05:18:33 PM PDT 24
Finished Jun 26 05:18:36 PM PDT 24
Peak memory 206132 kb
Host smart-e9c4a6ef-c8c4-49c5-9bba-5302136cd725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21352
43971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.2135243971
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.3958865018
Short name T1431
Test name
Test status
Simulation time 5446224319 ps
CPU time 53.5 seconds
Started Jun 26 05:18:32 PM PDT 24
Finished Jun 26 05:19:27 PM PDT 24
Peak memory 206532 kb
Host smart-97a3a9fb-8604-4800-b1ab-4528d99f7fc7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3958865018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.3958865018
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.2931264975
Short name T648
Test name
Test status
Simulation time 191069346 ps
CPU time 0.85 seconds
Started Jun 26 05:18:29 PM PDT 24
Finished Jun 26 05:18:33 PM PDT 24
Peak memory 206212 kb
Host smart-44e72d1e-706a-4e15-a76b-bd29102d94e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29312
64975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.2931264975
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.2557815381
Short name T1592
Test name
Test status
Simulation time 178177327 ps
CPU time 0.77 seconds
Started Jun 26 05:18:30 PM PDT 24
Finished Jun 26 05:18:33 PM PDT 24
Peak memory 206160 kb
Host smart-16615797-5aec-41fb-9172-da58b06e5181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25578
15381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.2557815381
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.2910911551
Short name T1648
Test name
Test status
Simulation time 3523196015 ps
CPU time 24.47 seconds
Started Jun 26 05:18:34 PM PDT 24
Finished Jun 26 05:19:00 PM PDT 24
Peak memory 206448 kb
Host smart-c1a0c122-aace-4457-b880-d3159a6b3bce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29109
11551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.2910911551
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.67857966
Short name T2249
Test name
Test status
Simulation time 4362247024 ps
CPU time 4.81 seconds
Started Jun 26 05:11:26 PM PDT 24
Finished Jun 26 05:11:32 PM PDT 24
Peak memory 206500 kb
Host smart-08e7e34a-4db2-4b55-b32d-2abf40241663
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=67857966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.67857966
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.3763388262
Short name T1150
Test name
Test status
Simulation time 13309440614 ps
CPU time 12.85 seconds
Started Jun 26 05:11:23 PM PDT 24
Finished Jun 26 05:11:36 PM PDT 24
Peak memory 206320 kb
Host smart-67df4e02-d668-4741-b150-62a9cc816b16
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3763388262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.3763388262
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.3472416312
Short name T1567
Test name
Test status
Simulation time 23354421683 ps
CPU time 21.46 seconds
Started Jun 26 05:11:23 PM PDT 24
Finished Jun 26 05:11:45 PM PDT 24
Peak memory 206416 kb
Host smart-008a7d02-013d-420f-b5d6-a6943f6a0987
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3472416312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.3472416312
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.389451486
Short name T2031
Test name
Test status
Simulation time 152198667 ps
CPU time 0.76 seconds
Started Jun 26 05:11:24 PM PDT 24
Finished Jun 26 05:11:26 PM PDT 24
Peak memory 206244 kb
Host smart-05c3ad81-ecdd-4707-9560-a7b6f3d9dc5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38945
1486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.389451486
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.2041759571
Short name T51
Test name
Test status
Simulation time 180107303 ps
CPU time 0.84 seconds
Started Jun 26 05:11:23 PM PDT 24
Finished Jun 26 05:11:25 PM PDT 24
Peak memory 206180 kb
Host smart-985010a9-a19d-4766-8f5a-cc745d619fc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20417
59571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.2041759571
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.2996780643
Short name T59
Test name
Test status
Simulation time 154418584 ps
CPU time 0.79 seconds
Started Jun 26 05:11:25 PM PDT 24
Finished Jun 26 05:11:27 PM PDT 24
Peak memory 206104 kb
Host smart-4a8034d7-876f-41b3-9e11-cd7ebc8dbad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29967
80643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.2996780643
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.1862675886
Short name T2040
Test name
Test status
Simulation time 209918234 ps
CPU time 0.84 seconds
Started Jun 26 05:11:22 PM PDT 24
Finished Jun 26 05:11:24 PM PDT 24
Peak memory 206124 kb
Host smart-32cd535a-9484-4bf8-a1f6-1ca14b42a29a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18626
75886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.1862675886
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.3833663272
Short name T1674
Test name
Test status
Simulation time 242775945 ps
CPU time 1.01 seconds
Started Jun 26 05:11:24 PM PDT 24
Finished Jun 26 05:11:26 PM PDT 24
Peak memory 206228 kb
Host smart-335a7036-47b9-4f3d-a01f-e93526db1c62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38336
63272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.3833663272
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.2250324765
Short name T1807
Test name
Test status
Simulation time 977632036 ps
CPU time 2.14 seconds
Started Jun 26 05:11:25 PM PDT 24
Finished Jun 26 05:11:27 PM PDT 24
Peak memory 206420 kb
Host smart-48688728-2398-41b0-a4a5-e6fe69c470b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22503
24765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.2250324765
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.3439013776
Short name T2240
Test name
Test status
Simulation time 11370992015 ps
CPU time 22.2 seconds
Started Jun 26 05:11:23 PM PDT 24
Finished Jun 26 05:11:46 PM PDT 24
Peak memory 206432 kb
Host smart-76507f76-15cd-4bfa-b96f-2b11583e5b11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34390
13776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.3439013776
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.3749152184
Short name T1274
Test name
Test status
Simulation time 456584272 ps
CPU time 1.26 seconds
Started Jun 26 05:11:25 PM PDT 24
Finished Jun 26 05:11:27 PM PDT 24
Peak memory 206120 kb
Host smart-f1323f88-92b3-4b00-840c-e0ca1402f6fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37491
52184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.3749152184
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.2784226592
Short name T1950
Test name
Test status
Simulation time 180824368 ps
CPU time 0.81 seconds
Started Jun 26 05:11:25 PM PDT 24
Finished Jun 26 05:11:27 PM PDT 24
Peak memory 206120 kb
Host smart-eef5c8fd-8b15-4f3a-ac49-1ecc1f5b6c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27842
26592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.2784226592
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.2222363681
Short name T1870
Test name
Test status
Simulation time 50727384 ps
CPU time 0.67 seconds
Started Jun 26 05:11:34 PM PDT 24
Finished Jun 26 05:11:35 PM PDT 24
Peak memory 206116 kb
Host smart-f29487f3-1eda-443d-b4b4-414478a78830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22223
63681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.2222363681
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.2986814660
Short name T2456
Test name
Test status
Simulation time 962553383 ps
CPU time 2.33 seconds
Started Jun 26 05:11:24 PM PDT 24
Finished Jun 26 05:11:27 PM PDT 24
Peak memory 206380 kb
Host smart-17728502-01ad-462b-95fc-1e27ad5e5f68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29868
14660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.2986814660
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.2524322172
Short name T1856
Test name
Test status
Simulation time 283983370 ps
CPU time 1.86 seconds
Started Jun 26 05:11:32 PM PDT 24
Finished Jun 26 05:11:34 PM PDT 24
Peak memory 206404 kb
Host smart-19300b1b-33b6-457e-872f-1e4f0e68bf96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25243
22172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.2524322172
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.3617836644
Short name T1453
Test name
Test status
Simulation time 180615346 ps
CPU time 0.81 seconds
Started Jun 26 05:11:48 PM PDT 24
Finished Jun 26 05:11:54 PM PDT 24
Peak memory 206140 kb
Host smart-c02ecbab-4684-4985-9895-8692068070e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36178
36644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.3617836644
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.3056326079
Short name T116
Test name
Test status
Simulation time 145178573 ps
CPU time 0.77 seconds
Started Jun 26 05:11:46 PM PDT 24
Finished Jun 26 05:11:48 PM PDT 24
Peak memory 206180 kb
Host smart-635b8775-a944-4203-900b-42030a2d0b3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30563
26079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.3056326079
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.2512809223
Short name T1563
Test name
Test status
Simulation time 221144931 ps
CPU time 0.9 seconds
Started Jun 26 05:11:33 PM PDT 24
Finished Jun 26 05:11:35 PM PDT 24
Peak memory 206396 kb
Host smart-dea2d3d6-e882-491c-96d7-185874d29c6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25128
09223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.2512809223
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.445827192
Short name T910
Test name
Test status
Simulation time 194286094 ps
CPU time 0.84 seconds
Started Jun 26 05:11:31 PM PDT 24
Finished Jun 26 05:11:33 PM PDT 24
Peak memory 206196 kb
Host smart-8698e71a-005f-4332-b29a-37b99d1508f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44582
7192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.445827192
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.66489241
Short name T438
Test name
Test status
Simulation time 23309163693 ps
CPU time 26.05 seconds
Started Jun 26 05:11:33 PM PDT 24
Finished Jun 26 05:12:00 PM PDT 24
Peak memory 206568 kb
Host smart-d2dd6cb1-ca21-4793-8cbe-30c86bf696e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66489
241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.66489241
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.2964252162
Short name T1509
Test name
Test status
Simulation time 3269783180 ps
CPU time 3.74 seconds
Started Jun 26 05:11:31 PM PDT 24
Finished Jun 26 05:11:36 PM PDT 24
Peak memory 206204 kb
Host smart-6b17ff6d-a30c-4933-b98f-5dcc71861ed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29642
52162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.2964252162
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.2936187404
Short name T1853
Test name
Test status
Simulation time 9274399243 ps
CPU time 88.73 seconds
Started Jun 26 05:11:31 PM PDT 24
Finished Jun 26 05:13:01 PM PDT 24
Peak memory 206512 kb
Host smart-7c9bef3e-4763-42ae-ac62-29edf3692543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29361
87404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.2936187404
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.499289286
Short name T1956
Test name
Test status
Simulation time 4522970612 ps
CPU time 135.79 seconds
Started Jun 26 05:11:32 PM PDT 24
Finished Jun 26 05:13:49 PM PDT 24
Peak memory 206500 kb
Host smart-979a992c-7432-4fb6-8d77-e9f68239ad0c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=499289286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.499289286
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.3936255791
Short name T2096
Test name
Test status
Simulation time 268600494 ps
CPU time 0.91 seconds
Started Jun 26 05:11:49 PM PDT 24
Finished Jun 26 05:11:55 PM PDT 24
Peak memory 206196 kb
Host smart-e5ab284a-3a0b-4b6a-9bee-9f91a9a697d8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3936255791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.3936255791
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.185521570
Short name T633
Test name
Test status
Simulation time 183909518 ps
CPU time 0.88 seconds
Started Jun 26 05:11:33 PM PDT 24
Finished Jun 26 05:11:34 PM PDT 24
Peak memory 206212 kb
Host smart-d4978b17-930f-4314-b70f-c6e0841b537f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18552
1570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.185521570
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.2902187040
Short name T1113
Test name
Test status
Simulation time 7527374944 ps
CPU time 55.24 seconds
Started Jun 26 05:11:33 PM PDT 24
Finished Jun 26 05:12:29 PM PDT 24
Peak memory 206488 kb
Host smart-7dd050de-a292-436f-9272-eb366af8e909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29021
87040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.2902187040
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.2843626061
Short name T919
Test name
Test status
Simulation time 5704113283 ps
CPU time 171.55 seconds
Started Jun 26 05:11:32 PM PDT 24
Finished Jun 26 05:14:25 PM PDT 24
Peak memory 206500 kb
Host smart-cfba4cbd-7d1a-415a-8711-6a2f42fe2b81
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2843626061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.2843626061
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.1739317417
Short name T1596
Test name
Test status
Simulation time 154528221 ps
CPU time 0.78 seconds
Started Jun 26 05:11:47 PM PDT 24
Finished Jun 26 05:11:53 PM PDT 24
Peak memory 206228 kb
Host smart-8fea12cd-97e7-426c-81f7-c880f35d8a4a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1739317417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.1739317417
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.1423864374
Short name T2100
Test name
Test status
Simulation time 150122004 ps
CPU time 0.8 seconds
Started Jun 26 05:11:32 PM PDT 24
Finished Jun 26 05:11:34 PM PDT 24
Peak memory 206136 kb
Host smart-be96b741-b995-4e71-af14-ffeac6c6753b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14238
64374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.1423864374
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.2857453063
Short name T2549
Test name
Test status
Simulation time 253734049 ps
CPU time 0.91 seconds
Started Jun 26 05:11:42 PM PDT 24
Finished Jun 26 05:11:44 PM PDT 24
Peak memory 206176 kb
Host smart-70424940-8879-4d99-8607-8a19b093ad80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28574
53063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.2857453063
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.3591840982
Short name T1252
Test name
Test status
Simulation time 177307441 ps
CPU time 0.83 seconds
Started Jun 26 05:11:39 PM PDT 24
Finished Jun 26 05:11:41 PM PDT 24
Peak memory 206224 kb
Host smart-e8fec336-217f-46e1-b85d-ce2d6fc84510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35918
40982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.3591840982
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.267376639
Short name T1051
Test name
Test status
Simulation time 156783445 ps
CPU time 0.76 seconds
Started Jun 26 05:11:41 PM PDT 24
Finished Jun 26 05:11:42 PM PDT 24
Peak memory 206188 kb
Host smart-ccb305fb-0550-48e4-a6f1-ec30307c224e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26737
6639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.267376639
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.4089455257
Short name T1600
Test name
Test status
Simulation time 221830424 ps
CPU time 0.84 seconds
Started Jun 26 05:11:47 PM PDT 24
Finished Jun 26 05:11:54 PM PDT 24
Peak memory 206120 kb
Host smart-6cc18764-4858-483b-8390-21f7b8de75fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40894
55257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.4089455257
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.1531198521
Short name T2159
Test name
Test status
Simulation time 195084957 ps
CPU time 0.82 seconds
Started Jun 26 05:11:48 PM PDT 24
Finished Jun 26 05:11:54 PM PDT 24
Peak memory 206232 kb
Host smart-2b910e5e-99b8-4891-85e8-dcba0a4716b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15311
98521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.1531198521
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.563383220
Short name T605
Test name
Test status
Simulation time 210615554 ps
CPU time 0.91 seconds
Started Jun 26 05:11:47 PM PDT 24
Finished Jun 26 05:11:53 PM PDT 24
Peak memory 206232 kb
Host smart-93ea8161-9e5d-432e-8639-17868e49fbc1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=563383220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.563383220
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.2928557119
Short name T2057
Test name
Test status
Simulation time 232585013 ps
CPU time 0.91 seconds
Started Jun 26 05:11:48 PM PDT 24
Finished Jun 26 05:11:54 PM PDT 24
Peak memory 206116 kb
Host smart-004f316a-c9a8-48ac-94ae-ad7e817f95c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29285
57119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.2928557119
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.3310212015
Short name T2075
Test name
Test status
Simulation time 147022680 ps
CPU time 0.73 seconds
Started Jun 26 05:11:47 PM PDT 24
Finished Jun 26 05:11:53 PM PDT 24
Peak memory 206120 kb
Host smart-d3b02e1a-fd93-44b5-a82e-4fb2f9d3aacd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33102
12015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.3310212015
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.599353263
Short name T2461
Test name
Test status
Simulation time 40446133 ps
CPU time 0.66 seconds
Started Jun 26 05:11:46 PM PDT 24
Finished Jun 26 05:11:48 PM PDT 24
Peak memory 206196 kb
Host smart-cb9752d7-e48e-455c-ba64-bfdff6970d53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59935
3263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.599353263
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.3982576297
Short name T266
Test name
Test status
Simulation time 12891509900 ps
CPU time 26.38 seconds
Started Jun 26 05:11:40 PM PDT 24
Finished Jun 26 05:12:07 PM PDT 24
Peak memory 206460 kb
Host smart-9552a41f-95cd-43dc-a381-f15c5fd68b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39825
76297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.3982576297
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.381196987
Short name T856
Test name
Test status
Simulation time 227358726 ps
CPU time 0.9 seconds
Started Jun 26 05:11:39 PM PDT 24
Finished Jun 26 05:11:40 PM PDT 24
Peak memory 206168 kb
Host smart-9f1769fb-222d-42cc-a59d-7e26c133df95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38119
6987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.381196987
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.607559910
Short name T2103
Test name
Test status
Simulation time 183981780 ps
CPU time 0.83 seconds
Started Jun 26 05:11:47 PM PDT 24
Finished Jun 26 05:11:54 PM PDT 24
Peak memory 206124 kb
Host smart-bc6800bf-e078-4ffc-9aaa-24768ada6a16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60755
9910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.607559910
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.1517433069
Short name T2102
Test name
Test status
Simulation time 4462101343 ps
CPU time 112.5 seconds
Started Jun 26 05:11:47 PM PDT 24
Finished Jun 26 05:13:45 PM PDT 24
Peak memory 206484 kb
Host smart-4489866e-0b46-4c36-ba75-64e940fe646d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1517433069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.1517433069
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.3006043789
Short name T2281
Test name
Test status
Simulation time 7232436090 ps
CPU time 184.63 seconds
Started Jun 26 05:11:42 PM PDT 24
Finished Jun 26 05:14:47 PM PDT 24
Peak memory 206444 kb
Host smart-df0bc9b2-acbc-4b9f-a46d-aabaa4b3c2fc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3006043789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.3006043789
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.720914850
Short name T1841
Test name
Test status
Simulation time 16245515442 ps
CPU time 114.48 seconds
Started Jun 26 05:11:47 PM PDT 24
Finished Jun 26 05:13:45 PM PDT 24
Peak memory 206496 kb
Host smart-226fb318-b2d0-4919-8e10-a4695c373f8e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=720914850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.720914850
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.1435170416
Short name T1998
Test name
Test status
Simulation time 182930876 ps
CPU time 0.84 seconds
Started Jun 26 05:11:49 PM PDT 24
Finished Jun 26 05:11:55 PM PDT 24
Peak memory 206140 kb
Host smart-eba8d7aa-5df0-49e2-81cd-07fa64976b9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14351
70416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.1435170416
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.2031138542
Short name T2570
Test name
Test status
Simulation time 152086509 ps
CPU time 0.81 seconds
Started Jun 26 05:11:39 PM PDT 24
Finished Jun 26 05:11:41 PM PDT 24
Peak memory 206216 kb
Host smart-cc687c4c-c765-4f56-b547-d42752e468e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20311
38542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.2031138542
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.1652008343
Short name T536
Test name
Test status
Simulation time 209316252 ps
CPU time 0.85 seconds
Started Jun 26 05:11:47 PM PDT 24
Finished Jun 26 05:11:53 PM PDT 24
Peak memory 206212 kb
Host smart-87004942-bd19-40ee-9f73-d79ff4a6e968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16520
08343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.1652008343
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.1072510964
Short name T2380
Test name
Test status
Simulation time 153671967 ps
CPU time 0.79 seconds
Started Jun 26 05:11:49 PM PDT 24
Finished Jun 26 05:11:55 PM PDT 24
Peak memory 206212 kb
Host smart-2aa9e732-6fa6-475a-8699-0fce351ad0a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10725
10964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.1072510964
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.3928530121
Short name T199
Test name
Test status
Simulation time 397348577 ps
CPU time 1.2 seconds
Started Jun 26 05:11:49 PM PDT 24
Finished Jun 26 05:11:55 PM PDT 24
Peak memory 223860 kb
Host smart-ada91b19-a567-4d81-8175-86b3bbbccdae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3928530121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.3928530121
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.3346306057
Short name T48
Test name
Test status
Simulation time 390276293 ps
CPU time 1.19 seconds
Started Jun 26 05:11:39 PM PDT 24
Finished Jun 26 05:11:41 PM PDT 24
Peak memory 206176 kb
Host smart-f01418bd-9ac6-48ea-8297-83966b580767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33463
06057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.3346306057
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.4130022713
Short name T524
Test name
Test status
Simulation time 160142608 ps
CPU time 0.82 seconds
Started Jun 26 05:11:48 PM PDT 24
Finished Jun 26 05:11:54 PM PDT 24
Peak memory 206176 kb
Host smart-08da34fb-f2f8-4487-9553-b4843e83daa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41300
22713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.4130022713
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.566394692
Short name T2132
Test name
Test status
Simulation time 147639603 ps
CPU time 0.75 seconds
Started Jun 26 05:11:49 PM PDT 24
Finished Jun 26 05:11:54 PM PDT 24
Peak memory 206212 kb
Host smart-a40be30a-8cc1-4735-a636-c31c725f77b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56639
4692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.566394692
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.1991284541
Short name T776
Test name
Test status
Simulation time 254792988 ps
CPU time 0.95 seconds
Started Jun 26 05:11:46 PM PDT 24
Finished Jun 26 05:11:48 PM PDT 24
Peak memory 206204 kb
Host smart-baa0f605-8436-4e2a-af5e-cb54b77080f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19912
84541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.1991284541
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.3315930895
Short name T1971
Test name
Test status
Simulation time 3505743387 ps
CPU time 94.31 seconds
Started Jun 26 05:11:39 PM PDT 24
Finished Jun 26 05:13:14 PM PDT 24
Peak memory 206496 kb
Host smart-d4792f10-6048-4ebc-b5b8-d2c9a15964dd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3315930895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.3315930895
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.3695613709
Short name T923
Test name
Test status
Simulation time 226279913 ps
CPU time 0.86 seconds
Started Jun 26 05:11:47 PM PDT 24
Finished Jun 26 05:11:51 PM PDT 24
Peak memory 206196 kb
Host smart-50b52625-9df3-4e44-96de-002a1c6d3661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36956
13709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.3695613709
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.2151461213
Short name T577
Test name
Test status
Simulation time 183660328 ps
CPU time 0.78 seconds
Started Jun 26 05:11:41 PM PDT 24
Finished Jun 26 05:11:42 PM PDT 24
Peak memory 206228 kb
Host smart-171dad04-724b-4e36-8b16-af193a4fc67d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21514
61213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.2151461213
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.3107577738
Short name T2423
Test name
Test status
Simulation time 5605965162 ps
CPU time 42.87 seconds
Started Jun 26 05:11:50 PM PDT 24
Finished Jun 26 05:12:37 PM PDT 24
Peak memory 206576 kb
Host smart-129167c2-cddc-493e-9d46-44f8f16567e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31075
77738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.3107577738
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.3269384673
Short name T2033
Test name
Test status
Simulation time 11965682513 ps
CPU time 237.76 seconds
Started Jun 26 05:11:47 PM PDT 24
Finished Jun 26 05:15:49 PM PDT 24
Peak memory 206652 kb
Host smart-4e73756c-18e8-4c6d-8395-6e9c36dea8f5
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3269384673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.3269384673
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.118136952
Short name T971
Test name
Test status
Simulation time 3978688069 ps
CPU time 4.8 seconds
Started Jun 26 05:18:38 PM PDT 24
Finished Jun 26 05:18:44 PM PDT 24
Peak memory 206284 kb
Host smart-eb297a68-6ca1-4459-ade1-e70c1c84c7f5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=118136952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.118136952
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.1555391693
Short name T1406
Test name
Test status
Simulation time 13334043932 ps
CPU time 11.93 seconds
Started Jun 26 05:18:39 PM PDT 24
Finished Jun 26 05:18:52 PM PDT 24
Peak memory 206536 kb
Host smart-6f4810e6-540c-48eb-a11b-1b59a3bf2db0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1555391693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.1555391693
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.424731232
Short name T205
Test name
Test status
Simulation time 23316669989 ps
CPU time 27.61 seconds
Started Jun 26 05:18:40 PM PDT 24
Finished Jun 26 05:19:09 PM PDT 24
Peak memory 206512 kb
Host smart-b275ab9c-e013-4582-8267-20a6e148bce0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=424731232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.424731232
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.523508412
Short name T1251
Test name
Test status
Simulation time 185273028 ps
CPU time 0.83 seconds
Started Jun 26 05:18:38 PM PDT 24
Finished Jun 26 05:18:40 PM PDT 24
Peak memory 206148 kb
Host smart-a82eca7b-3345-47aa-9b39-e657fcfa4bdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52350
8412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.523508412
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.2322875716
Short name T1518
Test name
Test status
Simulation time 153722223 ps
CPU time 0.81 seconds
Started Jun 26 05:18:40 PM PDT 24
Finished Jun 26 05:18:42 PM PDT 24
Peak memory 206204 kb
Host smart-3dad4e9b-41e5-424f-8445-b458a3f6a0a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23228
75716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.2322875716
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.4034204952
Short name T185
Test name
Test status
Simulation time 482442964 ps
CPU time 1.51 seconds
Started Jun 26 05:18:38 PM PDT 24
Finished Jun 26 05:18:40 PM PDT 24
Peak memory 206296 kb
Host smart-c235431e-2c26-4cb7-b8ae-8e37c949604c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40342
04952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.4034204952
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.3861917820
Short name T2335
Test name
Test status
Simulation time 984068192 ps
CPU time 2.46 seconds
Started Jun 26 05:18:41 PM PDT 24
Finished Jun 26 05:18:44 PM PDT 24
Peak memory 206408 kb
Host smart-f8abd269-9a43-4667-aca1-821a57311d57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38619
17820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.3861917820
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.140037951
Short name T2008
Test name
Test status
Simulation time 21801801058 ps
CPU time 39.9 seconds
Started Jun 26 05:18:38 PM PDT 24
Finished Jun 26 05:19:19 PM PDT 24
Peak memory 206492 kb
Host smart-1f8e9d4f-ec9d-41ac-ba67-6959f3096c97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14003
7951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.140037951
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.3488902938
Short name T89
Test name
Test status
Simulation time 380633354 ps
CPU time 1.16 seconds
Started Jun 26 05:18:45 PM PDT 24
Finished Jun 26 05:18:47 PM PDT 24
Peak memory 206220 kb
Host smart-6ebfa995-1d6f-45e3-baf8-45f73848cf14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34889
02938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.3488902938
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.3203067986
Short name T1246
Test name
Test status
Simulation time 141129802 ps
CPU time 0.78 seconds
Started Jun 26 05:18:37 PM PDT 24
Finished Jun 26 05:18:39 PM PDT 24
Peak memory 206116 kb
Host smart-3872b93e-695d-43a1-a9ba-c1c0cf08a164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32030
67986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.3203067986
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.3453380471
Short name T2099
Test name
Test status
Simulation time 33224099 ps
CPU time 0.66 seconds
Started Jun 26 05:18:39 PM PDT 24
Finished Jun 26 05:18:40 PM PDT 24
Peak memory 206212 kb
Host smart-d876f325-3cb6-4254-9125-d1fa65a56304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34533
80471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.3453380471
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.3516407544
Short name T1307
Test name
Test status
Simulation time 993810979 ps
CPU time 2.27 seconds
Started Jun 26 05:18:45 PM PDT 24
Finished Jun 26 05:18:48 PM PDT 24
Peak memory 206412 kb
Host smart-e5c49b29-60b9-44e1-9068-775050134edf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35164
07544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.3516407544
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.262683518
Short name T1122
Test name
Test status
Simulation time 252473558 ps
CPU time 1.72 seconds
Started Jun 26 05:18:45 PM PDT 24
Finished Jun 26 05:18:48 PM PDT 24
Peak memory 206316 kb
Host smart-56b196f7-0174-4290-94ca-9282bd7f5b0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26268
3518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.262683518
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.4080626766
Short name T1481
Test name
Test status
Simulation time 246217066 ps
CPU time 0.91 seconds
Started Jun 26 05:18:47 PM PDT 24
Finished Jun 26 05:18:50 PM PDT 24
Peak memory 206444 kb
Host smart-4f774e13-2841-4d44-9c1a-89e4ab0fd53b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40806
26766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.4080626766
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.737417751
Short name T2521
Test name
Test status
Simulation time 148576243 ps
CPU time 0.76 seconds
Started Jun 26 05:18:47 PM PDT 24
Finished Jun 26 05:18:51 PM PDT 24
Peak memory 206176 kb
Host smart-0f4fcc13-51c3-46ba-ad25-d426ee4220a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73741
7751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.737417751
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.3490071997
Short name T2411
Test name
Test status
Simulation time 286991903 ps
CPU time 0.91 seconds
Started Jun 26 05:18:38 PM PDT 24
Finished Jun 26 05:18:40 PM PDT 24
Peak memory 206188 kb
Host smart-374f3070-53ec-4f2e-82da-3f79bb9f2684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34900
71997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.3490071997
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_invalid_sync.1235941624
Short name T2477
Test name
Test status
Simulation time 6200549590 ps
CPU time 42.56 seconds
Started Jun 26 05:18:38 PM PDT 24
Finished Jun 26 05:19:22 PM PDT 24
Peak memory 206600 kb
Host smart-bfc25751-c268-4e94-89ae-187c766d8de8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1235941624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.1235941624
Directory /workspace/30.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.3035139020
Short name T658
Test name
Test status
Simulation time 180536808 ps
CPU time 0.83 seconds
Started Jun 26 05:18:46 PM PDT 24
Finished Jun 26 05:18:48 PM PDT 24
Peak memory 206120 kb
Host smart-4474c1b9-6493-45be-a72b-f92e020b3fd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30351
39020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.3035139020
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.660726238
Short name T1100
Test name
Test status
Simulation time 23300974927 ps
CPU time 25.01 seconds
Started Jun 26 05:18:37 PM PDT 24
Finished Jun 26 05:19:03 PM PDT 24
Peak memory 206328 kb
Host smart-30deac24-e8f5-433d-ae2d-29baac68cc60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66072
6238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.660726238
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.1977257731
Short name T1263
Test name
Test status
Simulation time 3268547253 ps
CPU time 3.45 seconds
Started Jun 26 05:18:38 PM PDT 24
Finished Jun 26 05:18:43 PM PDT 24
Peak memory 206232 kb
Host smart-ffd49c69-c636-4401-bc30-63a8f668a771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19772
57731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.1977257731
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.1084634591
Short name T651
Test name
Test status
Simulation time 8429397261 ps
CPU time 83.56 seconds
Started Jun 26 05:18:39 PM PDT 24
Finished Jun 26 05:20:04 PM PDT 24
Peak memory 206516 kb
Host smart-c5de314d-e138-445d-b337-9bbe34cb2b29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10846
34591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.1084634591
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.1306770294
Short name T1555
Test name
Test status
Simulation time 4327313381 ps
CPU time 114.33 seconds
Started Jun 26 05:18:38 PM PDT 24
Finished Jun 26 05:20:33 PM PDT 24
Peak memory 206536 kb
Host smart-a726f3a6-af60-49de-a995-b1cbc9ebfbcc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1306770294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.1306770294
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.912511296
Short name T2559
Test name
Test status
Simulation time 245851803 ps
CPU time 0.93 seconds
Started Jun 26 05:18:49 PM PDT 24
Finished Jun 26 05:18:51 PM PDT 24
Peak memory 206248 kb
Host smart-3c9bfef7-8018-45d9-be7d-392faefecd96
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=912511296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.912511296
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.3747703583
Short name T1047
Test name
Test status
Simulation time 231175420 ps
CPU time 0.88 seconds
Started Jun 26 05:18:39 PM PDT 24
Finished Jun 26 05:18:41 PM PDT 24
Peak memory 206180 kb
Host smart-b5d61cce-f975-452b-8a71-0eac4ef0c4db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37477
03583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.3747703583
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.686802393
Short name T2255
Test name
Test status
Simulation time 5809200036 ps
CPU time 44.27 seconds
Started Jun 26 05:18:43 PM PDT 24
Finished Jun 26 05:19:28 PM PDT 24
Peak memory 206396 kb
Host smart-e9b986a7-dc58-427c-9377-a01f70132d5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68680
2393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.686802393
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.348430262
Short name T1010
Test name
Test status
Simulation time 4963085688 ps
CPU time 47.07 seconds
Started Jun 26 05:18:40 PM PDT 24
Finished Jun 26 05:19:28 PM PDT 24
Peak memory 206452 kb
Host smart-69f12607-7c23-4faa-b258-fa9619d6bec3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=348430262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.348430262
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.1657126860
Short name T350
Test name
Test status
Simulation time 218266754 ps
CPU time 0.83 seconds
Started Jun 26 05:18:46 PM PDT 24
Finished Jun 26 05:18:49 PM PDT 24
Peak memory 206248 kb
Host smart-66a0086a-132b-4122-a4fb-51b9e83efec8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1657126860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.1657126860
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.1147697559
Short name T1264
Test name
Test status
Simulation time 153784129 ps
CPU time 0.79 seconds
Started Jun 26 05:18:45 PM PDT 24
Finished Jun 26 05:18:46 PM PDT 24
Peak memory 206128 kb
Host smart-77a7391e-e44a-45d5-9419-514624a8a675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11476
97559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.1147697559
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.1398104671
Short name T373
Test name
Test status
Simulation time 181129125 ps
CPU time 0.85 seconds
Started Jun 26 05:18:45 PM PDT 24
Finished Jun 26 05:18:47 PM PDT 24
Peak memory 206152 kb
Host smart-73123e9c-2f42-4cc3-b1ce-cd38ce9a7391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13981
04671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.1398104671
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.2147545230
Short name T1638
Test name
Test status
Simulation time 179068837 ps
CPU time 0.88 seconds
Started Jun 26 05:18:44 PM PDT 24
Finished Jun 26 05:18:46 PM PDT 24
Peak memory 206124 kb
Host smart-1bdd183c-f0b8-4e8c-bdd1-97fb893d476f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21475
45230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.2147545230
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.3207328175
Short name T538
Test name
Test status
Simulation time 166720997 ps
CPU time 0.8 seconds
Started Jun 26 05:18:47 PM PDT 24
Finished Jun 26 05:18:50 PM PDT 24
Peak memory 206204 kb
Host smart-244887e7-cc5d-4840-b2b6-ccf5c2e35259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32073
28175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.3207328175
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.4048951930
Short name T1578
Test name
Test status
Simulation time 202242014 ps
CPU time 0.86 seconds
Started Jun 26 05:18:48 PM PDT 24
Finished Jun 26 05:18:50 PM PDT 24
Peak memory 206192 kb
Host smart-ddcb4b3f-c105-4078-939a-194d8fc41d97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40489
51930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.4048951930
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.1243062899
Short name T640
Test name
Test status
Simulation time 249593292 ps
CPU time 1.01 seconds
Started Jun 26 05:18:46 PM PDT 24
Finished Jun 26 05:18:49 PM PDT 24
Peak memory 206224 kb
Host smart-7f2b45af-6cb0-423a-9fef-786f0573121c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1243062899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.1243062899
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.2004040958
Short name T198
Test name
Test status
Simulation time 144312499 ps
CPU time 0.78 seconds
Started Jun 26 05:18:47 PM PDT 24
Finished Jun 26 05:18:50 PM PDT 24
Peak memory 206096 kb
Host smart-18058d95-5307-4435-83ad-e658c40c09d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20040
40958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.2004040958
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.2432074624
Short name T1119
Test name
Test status
Simulation time 47363382 ps
CPU time 0.69 seconds
Started Jun 26 05:18:48 PM PDT 24
Finished Jun 26 05:18:50 PM PDT 24
Peak memory 206112 kb
Host smart-30b02b03-7cef-43f4-a48a-9d2dd5e0ea7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24320
74624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.2432074624
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.2631440244
Short name T715
Test name
Test status
Simulation time 23503203783 ps
CPU time 52.69 seconds
Started Jun 26 05:18:50 PM PDT 24
Finished Jun 26 05:19:43 PM PDT 24
Peak memory 206588 kb
Host smart-5582fceb-514d-404b-ace0-e204d591f2db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26314
40244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.2631440244
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.1344887938
Short name T691
Test name
Test status
Simulation time 221087227 ps
CPU time 0.89 seconds
Started Jun 26 05:18:47 PM PDT 24
Finished Jun 26 05:18:49 PM PDT 24
Peak memory 206120 kb
Host smart-a85a3492-1f32-4ed0-ac36-9b2b77635c4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13448
87938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.1344887938
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.197510267
Short name T1710
Test name
Test status
Simulation time 199469619 ps
CPU time 0.87 seconds
Started Jun 26 05:18:47 PM PDT 24
Finished Jun 26 05:18:49 PM PDT 24
Peak memory 206220 kb
Host smart-9abf5863-2af9-42bf-9b96-a5fdb141ecea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19751
0267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.197510267
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.3637846202
Short name T669
Test name
Test status
Simulation time 242317118 ps
CPU time 0.9 seconds
Started Jun 26 05:18:48 PM PDT 24
Finished Jun 26 05:18:51 PM PDT 24
Peak memory 206196 kb
Host smart-dccbdfca-71e5-4ae8-a6f8-9f46ff02095f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36378
46202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.3637846202
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.814646399
Short name T526
Test name
Test status
Simulation time 144428809 ps
CPU time 0.75 seconds
Started Jun 26 05:18:47 PM PDT 24
Finished Jun 26 05:18:50 PM PDT 24
Peak memory 206092 kb
Host smart-0357e65d-b2f7-4f4a-b2a8-533106dc9d0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81464
6399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.814646399
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.374422378
Short name T233
Test name
Test status
Simulation time 147786183 ps
CPU time 0.78 seconds
Started Jun 26 05:18:48 PM PDT 24
Finished Jun 26 05:18:50 PM PDT 24
Peak memory 206200 kb
Host smart-5b13490e-e3d3-482b-a687-1707e6cd81ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37442
2378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.374422378
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.3236384855
Short name T754
Test name
Test status
Simulation time 175120816 ps
CPU time 0.81 seconds
Started Jun 26 05:18:45 PM PDT 24
Finished Jun 26 05:18:47 PM PDT 24
Peak memory 206120 kb
Host smart-968a2c3a-a09b-4b25-8dfd-72d9532ac45a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32363
84855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.3236384855
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.4032227139
Short name T512
Test name
Test status
Simulation time 152049989 ps
CPU time 0.8 seconds
Started Jun 26 05:18:51 PM PDT 24
Finished Jun 26 05:18:52 PM PDT 24
Peak memory 206140 kb
Host smart-a97ef4bd-1f00-4bdb-aece-7792a8ff3a41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40322
27139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.4032227139
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.2610037861
Short name T2206
Test name
Test status
Simulation time 251049303 ps
CPU time 0.96 seconds
Started Jun 26 05:18:46 PM PDT 24
Finished Jun 26 05:18:48 PM PDT 24
Peak memory 206232 kb
Host smart-9b99a2e7-7cc7-4b6f-8d9f-91eabede8de5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26100
37861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.2610037861
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.2444331074
Short name T1235
Test name
Test status
Simulation time 7350544565 ps
CPU time 198.3 seconds
Started Jun 26 05:18:46 PM PDT 24
Finished Jun 26 05:22:06 PM PDT 24
Peak memory 206424 kb
Host smart-9a54edf8-db94-4734-860b-787c065980a9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2444331074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.2444331074
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.3009695968
Short name T1482
Test name
Test status
Simulation time 172020045 ps
CPU time 0.86 seconds
Started Jun 26 05:18:47 PM PDT 24
Finished Jun 26 05:18:50 PM PDT 24
Peak memory 206172 kb
Host smart-acca61c0-9c5e-4455-a402-a77f834507e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30096
95968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.3009695968
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.2128818739
Short name T696
Test name
Test status
Simulation time 167972187 ps
CPU time 0.81 seconds
Started Jun 26 05:18:47 PM PDT 24
Finished Jun 26 05:18:49 PM PDT 24
Peak memory 206440 kb
Host smart-6eea4819-9ac4-4a3c-a02b-76db07a61e7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21288
18739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.2128818739
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.2691189924
Short name T1372
Test name
Test status
Simulation time 3763508979 ps
CPU time 36.61 seconds
Started Jun 26 05:18:46 PM PDT 24
Finished Jun 26 05:19:23 PM PDT 24
Peak memory 206496 kb
Host smart-50cb5411-87c7-4efd-8c25-9fdc00ce84c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26911
89924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.2691189924
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.1350683364
Short name T14
Test name
Test status
Simulation time 3814471958 ps
CPU time 4.3 seconds
Started Jun 26 05:18:48 PM PDT 24
Finished Jun 26 05:18:54 PM PDT 24
Peak memory 206496 kb
Host smart-c50ce672-8391-46b7-9bf3-0733e27f3ef6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1350683364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.1350683364
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.1803637907
Short name T2430
Test name
Test status
Simulation time 13358091829 ps
CPU time 12.01 seconds
Started Jun 26 05:18:55 PM PDT 24
Finished Jun 26 05:19:09 PM PDT 24
Peak memory 206428 kb
Host smart-4877b5d2-b30a-4dc9-9068-9e9f017d0aed
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1803637907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.1803637907
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.2792373569
Short name T1984
Test name
Test status
Simulation time 23335961712 ps
CPU time 25.36 seconds
Started Jun 26 05:18:52 PM PDT 24
Finished Jun 26 05:19:19 PM PDT 24
Peak memory 206328 kb
Host smart-5ed57d3b-8160-49ef-8169-cc447af6e8a0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2792373569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.2792373569
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.433388878
Short name T2550
Test name
Test status
Simulation time 195867808 ps
CPU time 0.9 seconds
Started Jun 26 05:19:01 PM PDT 24
Finished Jun 26 05:19:04 PM PDT 24
Peak memory 206216 kb
Host smart-49026cc0-3efe-4ad0-8f0b-51ff07485294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43338
8878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.433388878
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.1228915682
Short name T2007
Test name
Test status
Simulation time 142490707 ps
CPU time 0.74 seconds
Started Jun 26 05:18:53 PM PDT 24
Finished Jun 26 05:18:55 PM PDT 24
Peak memory 206192 kb
Host smart-b455b2fa-4662-4adb-af1f-1878a28736bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12289
15682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.1228915682
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.887996783
Short name T2420
Test name
Test status
Simulation time 256910331 ps
CPU time 1 seconds
Started Jun 26 05:19:01 PM PDT 24
Finished Jun 26 05:19:04 PM PDT 24
Peak memory 206204 kb
Host smart-0d17035d-8f25-4e0b-9427-96e470cca1cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88799
6783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.887996783
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.2358394832
Short name T2569
Test name
Test status
Simulation time 425177962 ps
CPU time 1.25 seconds
Started Jun 26 05:18:54 PM PDT 24
Finished Jun 26 05:18:58 PM PDT 24
Peak memory 206140 kb
Host smart-669f5cb4-2f59-4b7d-97a5-d396080e13f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23583
94832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.2358394832
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.2644600220
Short name T1958
Test name
Test status
Simulation time 13968987421 ps
CPU time 25.27 seconds
Started Jun 26 05:18:51 PM PDT 24
Finished Jun 26 05:19:18 PM PDT 24
Peak memory 206504 kb
Host smart-9fdf6445-f17c-4942-875f-bbe8aef0dd2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26446
00220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.2644600220
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.2446081552
Short name T1823
Test name
Test status
Simulation time 387736616 ps
CPU time 1.25 seconds
Started Jun 26 05:18:54 PM PDT 24
Finished Jun 26 05:18:57 PM PDT 24
Peak memory 206216 kb
Host smart-d038f324-31ac-4e8f-9697-f86dc7fb8aab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24460
81552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.2446081552
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.4090803214
Short name T550
Test name
Test status
Simulation time 176622274 ps
CPU time 0.79 seconds
Started Jun 26 05:19:02 PM PDT 24
Finished Jun 26 05:19:05 PM PDT 24
Peak memory 206196 kb
Host smart-9aa9c738-8ba1-4338-bbed-e3db587d49f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40908
03214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.4090803214
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.3339819769
Short name T2207
Test name
Test status
Simulation time 74044939 ps
CPU time 0.69 seconds
Started Jun 26 05:18:57 PM PDT 24
Finished Jun 26 05:18:58 PM PDT 24
Peak memory 206220 kb
Host smart-9b0f4cb0-424d-4254-94da-82f77bc09f75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33398
19769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.3339819769
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.3461351743
Short name T2235
Test name
Test status
Simulation time 842442077 ps
CPU time 2.27 seconds
Started Jun 26 05:18:54 PM PDT 24
Finished Jun 26 05:18:58 PM PDT 24
Peak memory 206468 kb
Host smart-318b684d-4bdb-44c5-8fc2-87c07b1f0f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34613
51743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.3461351743
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.2147691454
Short name T1995
Test name
Test status
Simulation time 160913989 ps
CPU time 1.26 seconds
Started Jun 26 05:18:53 PM PDT 24
Finished Jun 26 05:18:56 PM PDT 24
Peak memory 206400 kb
Host smart-298a7979-7656-4c8c-8c92-c46abc6b6c55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21476
91454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.2147691454
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.2179318532
Short name T425
Test name
Test status
Simulation time 233788597 ps
CPU time 0.96 seconds
Started Jun 26 05:19:02 PM PDT 24
Finished Jun 26 05:19:05 PM PDT 24
Peak memory 206192 kb
Host smart-6bc0d17a-e953-4977-a82f-9098ad726698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21793
18532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.2179318532
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.4126352036
Short name T1558
Test name
Test status
Simulation time 148147546 ps
CPU time 0.76 seconds
Started Jun 26 05:19:04 PM PDT 24
Finished Jun 26 05:19:06 PM PDT 24
Peak memory 206188 kb
Host smart-3acfb296-4b87-4852-9d5f-716285ed4bdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41263
52036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.4126352036
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.3652817241
Short name T2452
Test name
Test status
Simulation time 187779869 ps
CPU time 0.84 seconds
Started Jun 26 05:18:54 PM PDT 24
Finished Jun 26 05:18:56 PM PDT 24
Peak memory 206188 kb
Host smart-71a7485b-a698-4634-bc5d-37cf1358f56f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36528
17241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.3652817241
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.2582122693
Short name T2567
Test name
Test status
Simulation time 200081314 ps
CPU time 0.84 seconds
Started Jun 26 05:18:53 PM PDT 24
Finished Jun 26 05:18:55 PM PDT 24
Peak memory 206108 kb
Host smart-d28eaa28-714b-432a-ad32-14222fd87d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25821
22693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.2582122693
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.1652848417
Short name T2489
Test name
Test status
Simulation time 23337070246 ps
CPU time 22.32 seconds
Started Jun 26 05:18:53 PM PDT 24
Finished Jun 26 05:19:16 PM PDT 24
Peak memory 206216 kb
Host smart-f10f328d-0552-4b8b-a23a-7d4849e348ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16528
48417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.1652848417
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.4044007253
Short name T859
Test name
Test status
Simulation time 3314487074 ps
CPU time 3.91 seconds
Started Jun 26 05:18:53 PM PDT 24
Finished Jun 26 05:18:59 PM PDT 24
Peak memory 206232 kb
Host smart-68e32a0e-4b91-44b8-9c45-8a68a2d4812d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40440
07253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.4044007253
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.1415696943
Short name T161
Test name
Test status
Simulation time 6388302241 ps
CPU time 171.51 seconds
Started Jun 26 05:18:54 PM PDT 24
Finished Jun 26 05:21:48 PM PDT 24
Peak memory 206476 kb
Host smart-d67ad42a-af65-4942-904d-3d7f6177cb62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14156
96943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.1415696943
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.2579361177
Short name T1151
Test name
Test status
Simulation time 6941763237 ps
CPU time 60.6 seconds
Started Jun 26 05:18:53 PM PDT 24
Finished Jun 26 05:19:55 PM PDT 24
Peak memory 206504 kb
Host smart-d0c48969-4b4c-458c-8e3f-f363b9a71439
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2579361177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.2579361177
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.3128874395
Short name T747
Test name
Test status
Simulation time 251861329 ps
CPU time 0.93 seconds
Started Jun 26 05:19:01 PM PDT 24
Finished Jun 26 05:19:04 PM PDT 24
Peak memory 206216 kb
Host smart-ee92fb17-d5e1-4097-9a9f-e2b6f578b583
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3128874395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.3128874395
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.3756538270
Short name T980
Test name
Test status
Simulation time 230242424 ps
CPU time 0.94 seconds
Started Jun 26 05:18:54 PM PDT 24
Finished Jun 26 05:18:56 PM PDT 24
Peak memory 206196 kb
Host smart-d7c9e2df-3314-489b-af57-0fb23f81a375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37565
38270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.3756538270
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.683464217
Short name T1948
Test name
Test status
Simulation time 5392111074 ps
CPU time 51.93 seconds
Started Jun 26 05:18:53 PM PDT 24
Finished Jun 26 05:19:47 PM PDT 24
Peak memory 206520 kb
Host smart-f1cd0013-a56f-4115-afbc-429fd376c5a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68346
4217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.683464217
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.2912265260
Short name T917
Test name
Test status
Simulation time 5199195015 ps
CPU time 46.75 seconds
Started Jun 26 05:18:52 PM PDT 24
Finished Jun 26 05:19:40 PM PDT 24
Peak memory 206524 kb
Host smart-dc076440-cb10-4c50-b180-c4bbc92f7d75
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2912265260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.2912265260
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.3988683503
Short name T752
Test name
Test status
Simulation time 180240630 ps
CPU time 0.84 seconds
Started Jun 26 05:19:01 PM PDT 24
Finished Jun 26 05:19:04 PM PDT 24
Peak memory 206228 kb
Host smart-47f29cda-b51c-4df3-aed1-7e568e5cc5fe
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3988683503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.3988683503
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.3649159784
Short name T1917
Test name
Test status
Simulation time 157927985 ps
CPU time 0.77 seconds
Started Jun 26 05:18:53 PM PDT 24
Finished Jun 26 05:18:55 PM PDT 24
Peak memory 206200 kb
Host smart-ec11fff6-b47f-4d85-b60d-d59fe45b2e78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36491
59784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.3649159784
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.1769572687
Short name T97
Test name
Test status
Simulation time 225271807 ps
CPU time 0.9 seconds
Started Jun 26 05:18:55 PM PDT 24
Finished Jun 26 05:18:58 PM PDT 24
Peak memory 206192 kb
Host smart-e7a531a9-f63d-42b2-a237-da74a1562c4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17695
72687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.1769572687
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.4234073668
Short name T1985
Test name
Test status
Simulation time 165443671 ps
CPU time 0.78 seconds
Started Jun 26 05:18:53 PM PDT 24
Finished Jun 26 05:18:55 PM PDT 24
Peak memory 206124 kb
Host smart-12185c84-4bfc-4649-886f-b1ec7b009d6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42340
73668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.4234073668
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.3554723236
Short name T540
Test name
Test status
Simulation time 174260302 ps
CPU time 0.79 seconds
Started Jun 26 05:19:01 PM PDT 24
Finished Jun 26 05:19:03 PM PDT 24
Peak memory 206196 kb
Host smart-e54f3f17-3454-49da-a9dc-3d231dda20d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35547
23236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.3554723236
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.2937904698
Short name T847
Test name
Test status
Simulation time 150348115 ps
CPU time 0.81 seconds
Started Jun 26 05:19:01 PM PDT 24
Finished Jun 26 05:19:03 PM PDT 24
Peak memory 206100 kb
Host smart-e64a32b7-83aa-4148-9db4-e073198dc023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29379
04698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.2937904698
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.279479658
Short name T576
Test name
Test status
Simulation time 185726175 ps
CPU time 0.86 seconds
Started Jun 26 05:18:54 PM PDT 24
Finished Jun 26 05:18:57 PM PDT 24
Peak memory 206148 kb
Host smart-03eff275-466d-41e8-9f30-95a850fe453a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=279479658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.279479658
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.408148483
Short name T2480
Test name
Test status
Simulation time 161120958 ps
CPU time 0.82 seconds
Started Jun 26 05:18:53 PM PDT 24
Finished Jun 26 05:18:55 PM PDT 24
Peak memory 206224 kb
Host smart-9b532b15-5865-40aa-a539-1a836320e888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40814
8483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.408148483
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.578504955
Short name T1544
Test name
Test status
Simulation time 36514959 ps
CPU time 0.65 seconds
Started Jun 26 05:19:04 PM PDT 24
Finished Jun 26 05:19:06 PM PDT 24
Peak memory 206180 kb
Host smart-e2983be1-9b2b-42e8-b74f-0808bc43a6c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57850
4955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.578504955
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.3054481084
Short name T985
Test name
Test status
Simulation time 22309751563 ps
CPU time 47.33 seconds
Started Jun 26 05:18:55 PM PDT 24
Finished Jun 26 05:19:44 PM PDT 24
Peak memory 206544 kb
Host smart-628b7b64-1150-4da9-8be0-695970ee4e6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30544
81084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.3054481084
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.1550168661
Short name T563
Test name
Test status
Simulation time 160452512 ps
CPU time 0.81 seconds
Started Jun 26 05:19:08 PM PDT 24
Finished Jun 26 05:19:10 PM PDT 24
Peak memory 206196 kb
Host smart-5c240f21-007c-4e51-8ed3-66eb0f5c6f7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15501
68661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.1550168661
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.1859814618
Short name T936
Test name
Test status
Simulation time 229665408 ps
CPU time 0.85 seconds
Started Jun 26 05:19:07 PM PDT 24
Finished Jun 26 05:19:09 PM PDT 24
Peak memory 206212 kb
Host smart-f3f9bfff-7045-4b06-958b-7586a27a0fa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18598
14618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.1859814618
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.3261123942
Short name T1602
Test name
Test status
Simulation time 173665180 ps
CPU time 0.86 seconds
Started Jun 26 05:19:03 PM PDT 24
Finished Jun 26 05:19:06 PM PDT 24
Peak memory 206148 kb
Host smart-f98826ab-1800-4255-a97f-805d9953e189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32611
23942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.3261123942
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.3625881385
Short name T1383
Test name
Test status
Simulation time 187220467 ps
CPU time 0.81 seconds
Started Jun 26 05:19:01 PM PDT 24
Finished Jun 26 05:19:04 PM PDT 24
Peak memory 206168 kb
Host smart-fec11b92-beeb-43f4-8819-7ccd2bb77915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36258
81385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.3625881385
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.32188190
Short name T2554
Test name
Test status
Simulation time 170910252 ps
CPU time 0.8 seconds
Started Jun 26 05:18:59 PM PDT 24
Finished Jun 26 05:19:00 PM PDT 24
Peak memory 206208 kb
Host smart-e569732b-5cbf-4c00-b1b2-a068a2da8be5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32188
190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.32188190
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.3321361500
Short name T928
Test name
Test status
Simulation time 156704903 ps
CPU time 0.81 seconds
Started Jun 26 05:19:00 PM PDT 24
Finished Jun 26 05:19:02 PM PDT 24
Peak memory 206204 kb
Host smart-6c721f1e-fbcb-4dbc-afa5-a586dc55a30b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33213
61500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.3321361500
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.1231534135
Short name T1214
Test name
Test status
Simulation time 186521850 ps
CPU time 0.82 seconds
Started Jun 26 05:19:01 PM PDT 24
Finished Jun 26 05:19:04 PM PDT 24
Peak memory 206224 kb
Host smart-826d0214-f386-46e3-aac0-4c9265d117ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12315
34135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.1231534135
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.718595204
Short name T1466
Test name
Test status
Simulation time 204148093 ps
CPU time 0.9 seconds
Started Jun 26 05:19:00 PM PDT 24
Finished Jun 26 05:19:03 PM PDT 24
Peak memory 206220 kb
Host smart-109b4977-0dd4-4fcb-8b92-3e65e6a62aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71859
5204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.718595204
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.1857573657
Short name T788
Test name
Test status
Simulation time 4330040993 ps
CPU time 115.01 seconds
Started Jun 26 05:19:00 PM PDT 24
Finished Jun 26 05:20:56 PM PDT 24
Peak memory 206452 kb
Host smart-a15e5606-5a68-43df-97ee-a80a8d3b8f96
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1857573657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.1857573657
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.3212685755
Short name T761
Test name
Test status
Simulation time 164067524 ps
CPU time 0.8 seconds
Started Jun 26 05:19:01 PM PDT 24
Finished Jun 26 05:19:03 PM PDT 24
Peak memory 206212 kb
Host smart-5d7ca3b0-b347-4b34-809b-65fd125652b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32126
85755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.3212685755
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.1296546448
Short name T2400
Test name
Test status
Simulation time 171846801 ps
CPU time 0.94 seconds
Started Jun 26 05:19:03 PM PDT 24
Finished Jun 26 05:19:06 PM PDT 24
Peak memory 206224 kb
Host smart-f98961f5-3ecc-4893-ac1e-d0c89832d2d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12965
46448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.1296546448
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.2602359000
Short name T291
Test name
Test status
Simulation time 3852169259 ps
CPU time 29.3 seconds
Started Jun 26 05:19:01 PM PDT 24
Finished Jun 26 05:19:33 PM PDT 24
Peak memory 206460 kb
Host smart-1b1f8b4d-646a-4ce3-9bb2-6be989ded4d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26023
59000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.2602359000
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.1936361038
Short name T2329
Test name
Test status
Simulation time 3609348430 ps
CPU time 3.95 seconds
Started Jun 26 05:19:03 PM PDT 24
Finished Jun 26 05:19:08 PM PDT 24
Peak memory 206284 kb
Host smart-40bb5464-5fa3-45df-b339-13f1c045072c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1936361038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.1936361038
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.3454667715
Short name T1364
Test name
Test status
Simulation time 13347873325 ps
CPU time 12.61 seconds
Started Jun 26 05:19:03 PM PDT 24
Finished Jun 26 05:19:17 PM PDT 24
Peak memory 206336 kb
Host smart-6226b69d-05ad-4733-9dbc-7b6933b67abd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3454667715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.3454667715
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.3043546108
Short name T2580
Test name
Test status
Simulation time 23394680275 ps
CPU time 22.42 seconds
Started Jun 26 05:19:00 PM PDT 24
Finished Jun 26 05:19:24 PM PDT 24
Peak memory 206508 kb
Host smart-00257082-d207-4813-97b3-0432decfb895
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3043546108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.3043546108
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.488654515
Short name T1930
Test name
Test status
Simulation time 188954171 ps
CPU time 0.79 seconds
Started Jun 26 05:19:00 PM PDT 24
Finished Jun 26 05:19:03 PM PDT 24
Peak memory 206224 kb
Host smart-1be8fa93-ca9c-448c-bc00-070b9e7c3f1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48865
4515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.488654515
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.65683492
Short name T1804
Test name
Test status
Simulation time 157702068 ps
CPU time 0.78 seconds
Started Jun 26 05:19:03 PM PDT 24
Finished Jun 26 05:19:05 PM PDT 24
Peak memory 206128 kb
Host smart-3cb5a7b8-758a-4d8d-a7a4-9c9c51be510b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65683
492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.65683492
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.3937951528
Short name T2424
Test name
Test status
Simulation time 229133310 ps
CPU time 1.06 seconds
Started Jun 26 05:19:07 PM PDT 24
Finished Jun 26 05:19:10 PM PDT 24
Peak memory 206124 kb
Host smart-e6462d0c-fcd6-4da3-a241-bb59186a153c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39379
51528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.3937951528
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.136037396
Short name T2345
Test name
Test status
Simulation time 527868608 ps
CPU time 1.36 seconds
Started Jun 26 05:19:08 PM PDT 24
Finished Jun 26 05:19:12 PM PDT 24
Peak memory 206136 kb
Host smart-5b4740fa-346e-47b6-9ab4-27fb851092a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13603
7396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.136037396
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.3389469136
Short name T189
Test name
Test status
Simulation time 8990468264 ps
CPU time 17.13 seconds
Started Jun 26 05:19:09 PM PDT 24
Finished Jun 26 05:19:29 PM PDT 24
Peak memory 206480 kb
Host smart-5dc0c969-a4b4-4509-8f71-295f8a15d148
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33894
69136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.3389469136
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.3875743542
Short name T2230
Test name
Test status
Simulation time 504871760 ps
CPU time 1.56 seconds
Started Jun 26 05:19:08 PM PDT 24
Finished Jun 26 05:19:12 PM PDT 24
Peak memory 206180 kb
Host smart-3a26b51f-4a94-4d77-9419-48feb1bdd38d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38757
43542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.3875743542
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.4118978566
Short name T459
Test name
Test status
Simulation time 173087845 ps
CPU time 0.85 seconds
Started Jun 26 05:19:09 PM PDT 24
Finished Jun 26 05:19:12 PM PDT 24
Peak memory 206168 kb
Host smart-dcd15ab0-b9b8-4d9d-b991-83c982c15e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41189
78566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.4118978566
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.3942830930
Short name T1370
Test name
Test status
Simulation time 24266672 ps
CPU time 0.63 seconds
Started Jun 26 05:19:06 PM PDT 24
Finished Jun 26 05:19:08 PM PDT 24
Peak memory 206228 kb
Host smart-718de285-e03c-4660-b721-429479572bed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39428
30930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.3942830930
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.3707282487
Short name T2259
Test name
Test status
Simulation time 960803636 ps
CPU time 2.33 seconds
Started Jun 26 05:19:09 PM PDT 24
Finished Jun 26 05:19:14 PM PDT 24
Peak memory 206488 kb
Host smart-2044c428-d958-4a2c-80c5-8258f472037e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37072
82487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.3707282487
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.1609170124
Short name T2177
Test name
Test status
Simulation time 175050153 ps
CPU time 1.78 seconds
Started Jun 26 05:19:13 PM PDT 24
Finished Jun 26 05:19:16 PM PDT 24
Peak memory 206320 kb
Host smart-36ccb1bd-b798-40d1-af92-7db7dcc6a7d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16091
70124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.1609170124
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.829377549
Short name T1579
Test name
Test status
Simulation time 219414850 ps
CPU time 0.89 seconds
Started Jun 26 05:19:15 PM PDT 24
Finished Jun 26 05:19:18 PM PDT 24
Peak memory 206180 kb
Host smart-fdca91e1-0047-46f3-9e93-e825c90435a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82937
7549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.829377549
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.1064326226
Short name T1982
Test name
Test status
Simulation time 155248627 ps
CPU time 0.76 seconds
Started Jun 26 05:19:18 PM PDT 24
Finished Jun 26 05:19:21 PM PDT 24
Peak memory 206144 kb
Host smart-44f72281-6faa-4ed3-9ca6-a322cd906d8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10643
26226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.1064326226
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.3743309775
Short name T1328
Test name
Test status
Simulation time 188403071 ps
CPU time 0.84 seconds
Started Jun 26 05:19:14 PM PDT 24
Finished Jun 26 05:19:16 PM PDT 24
Peak memory 206140 kb
Host smart-4daebd33-583e-4a90-905a-b72bb6beff71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37433
09775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.3743309775
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_invalid_sync.1057990712
Short name T1727
Test name
Test status
Simulation time 7590810207 ps
CPU time 209.4 seconds
Started Jun 26 05:19:07 PM PDT 24
Finished Jun 26 05:22:38 PM PDT 24
Peak memory 206516 kb
Host smart-3cce0257-7de9-491c-96ec-36fa762ecdc6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1057990712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.1057990712
Directory /workspace/32.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.2211590656
Short name T954
Test name
Test status
Simulation time 191381823 ps
CPU time 0.91 seconds
Started Jun 26 05:19:07 PM PDT 24
Finished Jun 26 05:19:10 PM PDT 24
Peak memory 206132 kb
Host smart-52c20f88-190c-4749-b4a7-08d0d58081e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22115
90656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.2211590656
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.3329098539
Short name T727
Test name
Test status
Simulation time 23341954686 ps
CPU time 26.43 seconds
Started Jun 26 05:19:10 PM PDT 24
Finished Jun 26 05:19:38 PM PDT 24
Peak memory 206292 kb
Host smart-dae747b2-fbb0-41ed-9398-132dcc4305ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33290
98539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.3329098539
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.1606751128
Short name T2352
Test name
Test status
Simulation time 3334460009 ps
CPU time 3.78 seconds
Started Jun 26 05:19:09 PM PDT 24
Finished Jun 26 05:19:16 PM PDT 24
Peak memory 206248 kb
Host smart-7453af4b-3c76-4d25-b479-c2a1f3f9d8f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16067
51128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.1606751128
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.698423649
Short name T1581
Test name
Test status
Simulation time 9035800807 ps
CPU time 81.22 seconds
Started Jun 26 05:19:09 PM PDT 24
Finished Jun 26 05:20:33 PM PDT 24
Peak memory 206520 kb
Host smart-6fbda93e-bc0c-4945-a53a-3a89d9f88f1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69842
3649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.698423649
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.3365041084
Short name T951
Test name
Test status
Simulation time 3168699401 ps
CPU time 23.12 seconds
Started Jun 26 05:19:08 PM PDT 24
Finished Jun 26 05:19:32 PM PDT 24
Peak memory 206468 kb
Host smart-c02953cf-2343-43f9-8b02-c008b4e1ded3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3365041084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.3365041084
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.1139966133
Short name T566
Test name
Test status
Simulation time 245973188 ps
CPU time 1.05 seconds
Started Jun 26 05:19:17 PM PDT 24
Finished Jun 26 05:19:21 PM PDT 24
Peak memory 206144 kb
Host smart-27bca652-1bcf-465a-9693-78acca6171ba
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1139966133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.1139966133
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.3140377596
Short name T2042
Test name
Test status
Simulation time 195095075 ps
CPU time 0.85 seconds
Started Jun 26 05:19:09 PM PDT 24
Finished Jun 26 05:19:12 PM PDT 24
Peak memory 206132 kb
Host smart-5f7639d1-f23d-40ec-81b9-e9fc459bebb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31403
77596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.3140377596
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.3678107092
Short name T902
Test name
Test status
Simulation time 4547073058 ps
CPU time 128.37 seconds
Started Jun 26 05:19:08 PM PDT 24
Finished Jun 26 05:21:19 PM PDT 24
Peak memory 206520 kb
Host smart-adc725b9-331d-4438-bae1-149b270e0cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36781
07092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.3678107092
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.1064371901
Short name T1075
Test name
Test status
Simulation time 6976357735 ps
CPU time 51.79 seconds
Started Jun 26 05:19:06 PM PDT 24
Finished Jun 26 05:19:59 PM PDT 24
Peak memory 206604 kb
Host smart-5e3383a4-edee-4f9d-926b-1116df015b26
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1064371901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.1064371901
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.2014500231
Short name T2563
Test name
Test status
Simulation time 164581914 ps
CPU time 0.77 seconds
Started Jun 26 05:19:14 PM PDT 24
Finished Jun 26 05:19:17 PM PDT 24
Peak memory 206136 kb
Host smart-7e1e7e75-396b-4619-b30c-b3ee27adf556
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2014500231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.2014500231
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.2965371275
Short name T1278
Test name
Test status
Simulation time 143709124 ps
CPU time 0.76 seconds
Started Jun 26 05:19:07 PM PDT 24
Finished Jun 26 05:19:09 PM PDT 24
Peak memory 206128 kb
Host smart-d205e7c9-71ff-4a51-b50b-b6f0236734b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29653
71275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.2965371275
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.4019580601
Short name T404
Test name
Test status
Simulation time 193932759 ps
CPU time 0.9 seconds
Started Jun 26 05:19:06 PM PDT 24
Finished Jun 26 05:19:08 PM PDT 24
Peak memory 206148 kb
Host smart-8d2140d9-f509-4bd2-b1da-200c8d67c2a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40195
80601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.4019580601
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.1793829798
Short name T20
Test name
Test status
Simulation time 188009395 ps
CPU time 0.81 seconds
Started Jun 26 05:19:08 PM PDT 24
Finished Jun 26 05:19:11 PM PDT 24
Peak memory 206228 kb
Host smart-61fd186d-e86a-4c85-92e8-f1942845a7db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17938
29798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.1793829798
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.990833126
Short name T2337
Test name
Test status
Simulation time 166777240 ps
CPU time 0.79 seconds
Started Jun 26 05:19:09 PM PDT 24
Finished Jun 26 05:19:12 PM PDT 24
Peak memory 206212 kb
Host smart-c2fc7edb-c12b-4162-826c-9a6ac6fa3243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99083
3126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.990833126
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.35072669
Short name T2501
Test name
Test status
Simulation time 203096653 ps
CPU time 0.88 seconds
Started Jun 26 05:19:09 PM PDT 24
Finished Jun 26 05:19:12 PM PDT 24
Peak memory 206196 kb
Host smart-0515d352-c008-4e31-ac47-352acfe6de75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35072
669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.35072669
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.3276437328
Short name T1537
Test name
Test status
Simulation time 290456576 ps
CPU time 1.05 seconds
Started Jun 26 05:19:08 PM PDT 24
Finished Jun 26 05:19:11 PM PDT 24
Peak memory 206192 kb
Host smart-5fcb34a1-a718-4a9d-9b1d-299573a3c3a9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3276437328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.3276437328
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.2334858067
Short name T755
Test name
Test status
Simulation time 211797660 ps
CPU time 0.78 seconds
Started Jun 26 05:19:08 PM PDT 24
Finished Jun 26 05:19:11 PM PDT 24
Peak memory 206120 kb
Host smart-e5c0bdf6-1ba5-4443-8ed0-201dc468564b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23348
58067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.2334858067
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.2870741514
Short name T1739
Test name
Test status
Simulation time 53545720 ps
CPU time 0.73 seconds
Started Jun 26 05:19:05 PM PDT 24
Finished Jun 26 05:19:07 PM PDT 24
Peak memory 206204 kb
Host smart-3c32a8c6-4e26-46c6-86bc-288e4c241db3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28707
41514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.2870741514
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.2405473968
Short name T296
Test name
Test status
Simulation time 13639882354 ps
CPU time 27.46 seconds
Started Jun 26 05:19:14 PM PDT 24
Finished Jun 26 05:19:43 PM PDT 24
Peak memory 206492 kb
Host smart-88aaa490-108d-4785-b580-aa732d96d4fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24054
73968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.2405473968
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.1925065685
Short name T1487
Test name
Test status
Simulation time 145812687 ps
CPU time 0.87 seconds
Started Jun 26 05:19:07 PM PDT 24
Finished Jun 26 05:19:09 PM PDT 24
Peak memory 206392 kb
Host smart-326e9f40-6404-4f38-9e68-d3105d226a93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19250
65685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.1925065685
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.2701611189
Short name T2279
Test name
Test status
Simulation time 229942808 ps
CPU time 1.01 seconds
Started Jun 26 05:19:08 PM PDT 24
Finished Jun 26 05:19:11 PM PDT 24
Peak memory 206396 kb
Host smart-dc8566ed-062c-41f5-8d43-76788f49250c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27016
11189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.2701611189
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.1218079328
Short name T2215
Test name
Test status
Simulation time 239182828 ps
CPU time 0.88 seconds
Started Jun 26 05:19:15 PM PDT 24
Finished Jun 26 05:19:18 PM PDT 24
Peak memory 206104 kb
Host smart-0daa5328-b36b-490e-9c78-c0f916372200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12180
79328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.1218079328
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.658940009
Short name T554
Test name
Test status
Simulation time 171210600 ps
CPU time 0.83 seconds
Started Jun 26 05:19:07 PM PDT 24
Finished Jun 26 05:19:09 PM PDT 24
Peak memory 206228 kb
Host smart-147d69d2-53cb-498b-8207-5e31e4125b1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65894
0009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.658940009
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.1601023842
Short name T1212
Test name
Test status
Simulation time 186314603 ps
CPU time 0.79 seconds
Started Jun 26 05:19:06 PM PDT 24
Finished Jun 26 05:19:08 PM PDT 24
Peak memory 206096 kb
Host smart-3f1a6489-d8df-4ecf-8d36-aacb8342e70f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16010
23842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.1601023842
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.75796801
Short name T808
Test name
Test status
Simulation time 143324062 ps
CPU time 0.75 seconds
Started Jun 26 05:19:07 PM PDT 24
Finished Jun 26 05:19:09 PM PDT 24
Peak memory 206116 kb
Host smart-e7c1fb0d-51a6-420e-9350-43202eba15cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75796
801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.75796801
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.1171124570
Short name T1506
Test name
Test status
Simulation time 147963543 ps
CPU time 0.76 seconds
Started Jun 26 05:19:08 PM PDT 24
Finished Jun 26 05:19:11 PM PDT 24
Peak memory 206208 kb
Host smart-efca36b4-ca71-4f8d-a332-03561a1649a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11711
24570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.1171124570
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.2927784604
Short name T631
Test name
Test status
Simulation time 241831770 ps
CPU time 0.97 seconds
Started Jun 26 05:19:07 PM PDT 24
Finished Jun 26 05:19:09 PM PDT 24
Peak memory 206192 kb
Host smart-472b9d1f-d455-4615-8488-d8c6f1f199ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29277
84604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.2927784604
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.1015236878
Short name T1256
Test name
Test status
Simulation time 5930290741 ps
CPU time 171.28 seconds
Started Jun 26 05:19:07 PM PDT 24
Finished Jun 26 05:22:00 PM PDT 24
Peak memory 206484 kb
Host smart-9eb9c66b-219e-49da-97ca-8810e41e9b2d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1015236878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.1015236878
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.1023790970
Short name T1324
Test name
Test status
Simulation time 144945936 ps
CPU time 0.82 seconds
Started Jun 26 05:19:10 PM PDT 24
Finished Jun 26 05:19:13 PM PDT 24
Peak memory 206180 kb
Host smart-502f1184-adbe-4c71-b81f-d57dfdadc799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10237
90970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.1023790970
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.972122047
Short name T2299
Test name
Test status
Simulation time 163153029 ps
CPU time 0.79 seconds
Started Jun 26 05:19:08 PM PDT 24
Finished Jun 26 05:19:11 PM PDT 24
Peak memory 206176 kb
Host smart-129221b5-5d60-4615-9645-7a4f6b20b5de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97212
2047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.972122047
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.1427510950
Short name T531
Test name
Test status
Simulation time 4468140505 ps
CPU time 127.13 seconds
Started Jun 26 05:19:06 PM PDT 24
Finished Jun 26 05:21:15 PM PDT 24
Peak memory 206540 kb
Host smart-9692c8e1-4cb8-4a68-aa0d-4b37abddcc61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14275
10950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.1427510950
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.3950419369
Short name T1503
Test name
Test status
Simulation time 3618618995 ps
CPU time 5.29 seconds
Started Jun 26 05:19:16 PM PDT 24
Finished Jun 26 05:19:24 PM PDT 24
Peak memory 206468 kb
Host smart-8a4310ba-0025-4a83-8aca-43372cbf2fd6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3950419369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.3950419369
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.667478746
Short name T946
Test name
Test status
Simulation time 13337273455 ps
CPU time 15.78 seconds
Started Jun 26 05:19:16 PM PDT 24
Finished Jun 26 05:19:34 PM PDT 24
Peak memory 206244 kb
Host smart-9d3bff84-1bd9-4751-bea9-53cf0199c451
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=667478746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.667478746
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.2148351431
Short name T1322
Test name
Test status
Simulation time 23479211895 ps
CPU time 31.55 seconds
Started Jun 26 05:19:15 PM PDT 24
Finished Jun 26 05:19:49 PM PDT 24
Peak memory 206560 kb
Host smart-8f5f662d-9c1a-49de-a600-7b8e196fbcc2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2148351431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.2148351431
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.920421834
Short name T1044
Test name
Test status
Simulation time 163412182 ps
CPU time 0.83 seconds
Started Jun 26 05:19:16 PM PDT 24
Finished Jun 26 05:19:20 PM PDT 24
Peak memory 206188 kb
Host smart-60b0d0ff-fbf7-4eaf-8814-2394da1dc01b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92042
1834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.920421834
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.3583188995
Short name T667
Test name
Test status
Simulation time 232010711 ps
CPU time 0.82 seconds
Started Jun 26 05:19:15 PM PDT 24
Finished Jun 26 05:19:19 PM PDT 24
Peak memory 206192 kb
Host smart-eaf92413-9c29-4b27-ab44-0acec8692539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35831
88995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.3583188995
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.58370628
Short name T848
Test name
Test status
Simulation time 323025191 ps
CPU time 1.17 seconds
Started Jun 26 05:19:16 PM PDT 24
Finished Jun 26 05:19:20 PM PDT 24
Peak memory 206180 kb
Host smart-543efa0e-25ff-4960-9f10-1820435b24b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58370
628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.58370628
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.3219027238
Short name T107
Test name
Test status
Simulation time 1407171930 ps
CPU time 3.28 seconds
Started Jun 26 05:19:13 PM PDT 24
Finished Jun 26 05:19:18 PM PDT 24
Peak memory 206408 kb
Host smart-f15931b9-fb07-46f5-bce2-c3e431a1dd16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32190
27238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.3219027238
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.3339566423
Short name T1460
Test name
Test status
Simulation time 12651093491 ps
CPU time 23.73 seconds
Started Jun 26 05:19:16 PM PDT 24
Finished Jun 26 05:19:42 PM PDT 24
Peak memory 206528 kb
Host smart-3d144967-ba5a-4a35-8a47-37d1c9c51ca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33395
66423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.3339566423
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.1676689794
Short name T2422
Test name
Test status
Simulation time 308187076 ps
CPU time 1.09 seconds
Started Jun 26 05:19:20 PM PDT 24
Finished Jun 26 05:19:23 PM PDT 24
Peak memory 206184 kb
Host smart-c29d7e5d-1f24-46c6-85bb-8e1b83f325a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16766
89794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.1676689794
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.2092154302
Short name T704
Test name
Test status
Simulation time 145031076 ps
CPU time 0.75 seconds
Started Jun 26 05:19:16 PM PDT 24
Finished Jun 26 05:19:20 PM PDT 24
Peak memory 206212 kb
Host smart-66d60cc8-97ff-4e5a-8cde-899f7ea15833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20921
54302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.2092154302
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.3673365083
Short name T591
Test name
Test status
Simulation time 41730193 ps
CPU time 0.72 seconds
Started Jun 26 05:19:16 PM PDT 24
Finished Jun 26 05:19:19 PM PDT 24
Peak memory 206220 kb
Host smart-18fd2124-3fcb-44ba-9a74-a1c93b33fa6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36733
65083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.3673365083
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.3631603864
Short name T600
Test name
Test status
Simulation time 982138048 ps
CPU time 2.58 seconds
Started Jun 26 05:19:15 PM PDT 24
Finished Jun 26 05:19:20 PM PDT 24
Peak memory 206428 kb
Host smart-bc601db4-7840-4d60-8082-494bda2a1582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36316
03864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.3631603864
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.3804676278
Short name T2229
Test name
Test status
Simulation time 299569269 ps
CPU time 1.68 seconds
Started Jun 26 05:19:13 PM PDT 24
Finished Jun 26 05:19:15 PM PDT 24
Peak memory 206504 kb
Host smart-1cea9d5c-9c3c-4637-9ee5-4e0ee3f524a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38046
76278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.3804676278
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.11165317
Short name T2093
Test name
Test status
Simulation time 218463094 ps
CPU time 0.88 seconds
Started Jun 26 05:19:31 PM PDT 24
Finished Jun 26 05:19:32 PM PDT 24
Peak memory 206224 kb
Host smart-9fb09827-fe1b-4749-815d-6f25e8f0dc1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11165
317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.11165317
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.1183407806
Short name T1642
Test name
Test status
Simulation time 161936794 ps
CPU time 0.76 seconds
Started Jun 26 05:19:22 PM PDT 24
Finished Jun 26 05:19:25 PM PDT 24
Peak memory 206096 kb
Host smart-6ede24e5-ca85-418c-9553-b71819378ed5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11834
07806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.1183407806
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.3534962980
Short name T1224
Test name
Test status
Simulation time 187271054 ps
CPU time 0.86 seconds
Started Jun 26 05:19:15 PM PDT 24
Finished Jun 26 05:19:19 PM PDT 24
Peak memory 206140 kb
Host smart-11844112-adb6-4206-a4a5-ccb746aaad1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35349
62980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.3534962980
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_invalid_sync.3767504537
Short name T225
Test name
Test status
Simulation time 5347459864 ps
CPU time 152.91 seconds
Started Jun 26 05:19:16 PM PDT 24
Finished Jun 26 05:21:52 PM PDT 24
Peak memory 206516 kb
Host smart-9ce48f22-41ab-47de-bafd-2f5438adb49b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3767504537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.3767504537
Directory /workspace/33.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.899305012
Short name T53
Test name
Test status
Simulation time 264062030 ps
CPU time 0.87 seconds
Started Jun 26 05:19:16 PM PDT 24
Finished Jun 26 05:19:19 PM PDT 24
Peak memory 206176 kb
Host smart-617af32b-9122-4304-a065-d8567ae5bfe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89930
5012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.899305012
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.1037383225
Short name T1936
Test name
Test status
Simulation time 23338734018 ps
CPU time 23.48 seconds
Started Jun 26 05:19:14 PM PDT 24
Finished Jun 26 05:19:39 PM PDT 24
Peak memory 206288 kb
Host smart-0c866911-9b43-4ac3-9b79-5fd394e89c23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10373
83225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.1037383225
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.2164209557
Short name T634
Test name
Test status
Simulation time 3323011922 ps
CPU time 3.4 seconds
Started Jun 26 05:19:17 PM PDT 24
Finished Jun 26 05:19:23 PM PDT 24
Peak memory 206216 kb
Host smart-f2b7440c-b59e-4b0c-93d4-509b3f53b299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21642
09557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.2164209557
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.2300505069
Short name T2195
Test name
Test status
Simulation time 9890123776 ps
CPU time 269.7 seconds
Started Jun 26 05:19:15 PM PDT 24
Finished Jun 26 05:23:48 PM PDT 24
Peak memory 206508 kb
Host smart-2e844ad2-522b-4c60-b945-060ad1d55d29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23005
05069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.2300505069
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.1669347971
Short name T891
Test name
Test status
Simulation time 4998159806 ps
CPU time 36.91 seconds
Started Jun 26 05:19:17 PM PDT 24
Finished Jun 26 05:19:57 PM PDT 24
Peak memory 206500 kb
Host smart-10654092-6f37-4e9f-81ae-898a5e0b328e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1669347971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.1669347971
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.3122007962
Short name T2049
Test name
Test status
Simulation time 271725132 ps
CPU time 0.92 seconds
Started Jun 26 05:19:25 PM PDT 24
Finished Jun 26 05:19:27 PM PDT 24
Peak memory 206220 kb
Host smart-415a2601-3eed-4b34-8b7b-9bb15014229a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3122007962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.3122007962
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.3938239178
Short name T2454
Test name
Test status
Simulation time 189696366 ps
CPU time 0.86 seconds
Started Jun 26 05:19:20 PM PDT 24
Finished Jun 26 05:19:23 PM PDT 24
Peak memory 206184 kb
Host smart-18ad74e0-63bb-4548-bd6e-6eb9d22e8781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39382
39178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.3938239178
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.1066115338
Short name T80
Test name
Test status
Simulation time 6285474318 ps
CPU time 60.61 seconds
Started Jun 26 05:19:14 PM PDT 24
Finished Jun 26 05:20:17 PM PDT 24
Peak memory 206520 kb
Host smart-59ae766f-74ee-4e3d-87dc-09a61e8cba06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10661
15338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.1066115338
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.3482616715
Short name T2450
Test name
Test status
Simulation time 5353247245 ps
CPU time 145.88 seconds
Started Jun 26 05:19:20 PM PDT 24
Finished Jun 26 05:21:48 PM PDT 24
Peak memory 206508 kb
Host smart-b4568051-6678-40f3-ace2-2991c8eb888a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3482616715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.3482616715
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.764485143
Short name T519
Test name
Test status
Simulation time 150492563 ps
CPU time 0.77 seconds
Started Jun 26 05:19:25 PM PDT 24
Finished Jun 26 05:19:27 PM PDT 24
Peak memory 206220 kb
Host smart-78e660ee-05c6-4908-bfa7-061bdfcade65
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=764485143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.764485143
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.3743318808
Short name T16
Test name
Test status
Simulation time 145418280 ps
CPU time 0.81 seconds
Started Jun 26 05:19:16 PM PDT 24
Finished Jun 26 05:19:19 PM PDT 24
Peak memory 206212 kb
Host smart-cc50aeb7-cd7b-47d2-868f-130733f6c309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37433
18808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.3743318808
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.2182876520
Short name T134
Test name
Test status
Simulation time 227361052 ps
CPU time 0.89 seconds
Started Jun 26 05:19:23 PM PDT 24
Finished Jun 26 05:19:26 PM PDT 24
Peak memory 206116 kb
Host smart-1c518880-53da-4c4c-8d93-0c1e3570902e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21828
76520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.2182876520
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.1262727580
Short name T1021
Test name
Test status
Simulation time 145236614 ps
CPU time 0.83 seconds
Started Jun 26 05:19:16 PM PDT 24
Finished Jun 26 05:19:20 PM PDT 24
Peak memory 206212 kb
Host smart-e005a5c7-632a-4566-8219-fcac15ac195c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12627
27580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.1262727580
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.1669934714
Short name T840
Test name
Test status
Simulation time 190461772 ps
CPU time 0.87 seconds
Started Jun 26 05:19:15 PM PDT 24
Finished Jun 26 05:19:19 PM PDT 24
Peak memory 206220 kb
Host smart-a631d537-d5b5-4b3d-a0be-c1fc14c258db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16699
34714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.1669934714
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.4063266310
Short name T1812
Test name
Test status
Simulation time 183851254 ps
CPU time 0.83 seconds
Started Jun 26 05:19:20 PM PDT 24
Finished Jun 26 05:19:23 PM PDT 24
Peak memory 206176 kb
Host smart-893e9aad-f229-42e3-8099-e66d0e581559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40632
66310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.4063266310
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.2500444930
Short name T1662
Test name
Test status
Simulation time 145491166 ps
CPU time 0.77 seconds
Started Jun 26 05:19:19 PM PDT 24
Finished Jun 26 05:19:22 PM PDT 24
Peak memory 206136 kb
Host smart-7d3f65f8-fdec-48ec-b4cd-6f9c295ef2b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25004
44930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.2500444930
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.3819777219
Short name T1400
Test name
Test status
Simulation time 198864897 ps
CPU time 0.88 seconds
Started Jun 26 05:19:13 PM PDT 24
Finished Jun 26 05:19:15 PM PDT 24
Peak memory 206140 kb
Host smart-5b33867d-0dfa-46d5-93ae-c90c40627be1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3819777219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.3819777219
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.237805395
Short name T2130
Test name
Test status
Simulation time 181576158 ps
CPU time 0.84 seconds
Started Jun 26 05:19:25 PM PDT 24
Finished Jun 26 05:19:27 PM PDT 24
Peak memory 206132 kb
Host smart-484c9cc9-35ac-4495-b4e6-bc29aeec8f51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23780
5395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.237805395
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.2046720384
Short name T2071
Test name
Test status
Simulation time 50459736 ps
CPU time 0.64 seconds
Started Jun 26 05:19:21 PM PDT 24
Finished Jun 26 05:19:24 PM PDT 24
Peak memory 206172 kb
Host smart-9939b24b-3211-4585-9218-4b01df47e8cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20467
20384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.2046720384
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.3444569556
Short name T299
Test name
Test status
Simulation time 22415217733 ps
CPU time 48.29 seconds
Started Jun 26 05:19:19 PM PDT 24
Finished Jun 26 05:20:10 PM PDT 24
Peak memory 206516 kb
Host smart-fcd39a9c-53a4-47ae-a01f-fac8afb7fd43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34445
69556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.3444569556
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.658198547
Short name T1410
Test name
Test status
Simulation time 198936022 ps
CPU time 0.87 seconds
Started Jun 26 05:19:22 PM PDT 24
Finished Jun 26 05:19:25 PM PDT 24
Peak memory 206108 kb
Host smart-921d58f1-e171-460a-bd17-f29f88f7ca7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65819
8547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.658198547
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.1679219898
Short name T1261
Test name
Test status
Simulation time 241789236 ps
CPU time 0.88 seconds
Started Jun 26 05:19:21 PM PDT 24
Finished Jun 26 05:19:25 PM PDT 24
Peak memory 206188 kb
Host smart-e301aaf5-cb78-4ed6-afbf-e0d66a5eb577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16792
19898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.1679219898
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.913950465
Short name T1362
Test name
Test status
Simulation time 188221462 ps
CPU time 0.83 seconds
Started Jun 26 05:19:21 PM PDT 24
Finished Jun 26 05:19:25 PM PDT 24
Peak memory 206152 kb
Host smart-13a45991-1e4e-4d98-8ce2-ebc0d4d888ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91395
0465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.913950465
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.3105806388
Short name T2356
Test name
Test status
Simulation time 148245103 ps
CPU time 0.8 seconds
Started Jun 26 05:19:21 PM PDT 24
Finished Jun 26 05:19:25 PM PDT 24
Peak memory 206232 kb
Host smart-926e1d62-83bb-47a4-bedf-558a7669cab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31058
06388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.3105806388
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.1627294608
Short name T1826
Test name
Test status
Simulation time 158726591 ps
CPU time 0.79 seconds
Started Jun 26 05:19:20 PM PDT 24
Finished Jun 26 05:19:24 PM PDT 24
Peak memory 206148 kb
Host smart-c3b46c29-195d-4595-9d66-30bccbdb48b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16272
94608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.1627294608
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.3925671130
Short name T1907
Test name
Test status
Simulation time 191827822 ps
CPU time 0.8 seconds
Started Jun 26 05:19:21 PM PDT 24
Finished Jun 26 05:19:25 PM PDT 24
Peak memory 206124 kb
Host smart-4cb33e9a-f1d6-42e4-a4b2-e424bfd23ce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39256
71130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.3925671130
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.2110188724
Short name T786
Test name
Test status
Simulation time 152718212 ps
CPU time 0.8 seconds
Started Jun 26 05:19:23 PM PDT 24
Finished Jun 26 05:19:26 PM PDT 24
Peak memory 206140 kb
Host smart-ec2be78b-d59d-41f3-9873-ff0f048dcd0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21101
88724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.2110188724
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.1332253058
Short name T1925
Test name
Test status
Simulation time 257025105 ps
CPU time 1.03 seconds
Started Jun 26 05:19:21 PM PDT 24
Finished Jun 26 05:19:24 PM PDT 24
Peak memory 206192 kb
Host smart-843bbb41-730d-4b75-b867-e5ec08735617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13322
53058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.1332253058
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.3096204305
Short name T392
Test name
Test status
Simulation time 3600926794 ps
CPU time 34.68 seconds
Started Jun 26 05:19:22 PM PDT 24
Finished Jun 26 05:19:59 PM PDT 24
Peak memory 206500 kb
Host smart-995358ce-9ed8-42d1-a995-58910082a736
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3096204305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.3096204305
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.2056413580
Short name T374
Test name
Test status
Simulation time 198983029 ps
CPU time 0.84 seconds
Started Jun 26 05:19:23 PM PDT 24
Finished Jun 26 05:19:26 PM PDT 24
Peak memory 206176 kb
Host smart-98452c2b-0b84-4abb-8638-1ae9bc2d629c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20564
13580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.2056413580
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.3838968632
Short name T1716
Test name
Test status
Simulation time 229670335 ps
CPU time 0.91 seconds
Started Jun 26 05:19:32 PM PDT 24
Finished Jun 26 05:19:35 PM PDT 24
Peak memory 206172 kb
Host smart-8257175d-871d-4427-acd6-081061f87669
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38389
68632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.3838968632
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.1967460736
Short name T1492
Test name
Test status
Simulation time 5831814072 ps
CPU time 54.8 seconds
Started Jun 26 05:19:22 PM PDT 24
Finished Jun 26 05:20:19 PM PDT 24
Peak memory 206512 kb
Host smart-70c989d7-b56f-4393-89cd-f9a43e6cb311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19674
60736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.1967460736
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.3113924124
Short name T1408
Test name
Test status
Simulation time 3612865997 ps
CPU time 4.32 seconds
Started Jun 26 05:19:22 PM PDT 24
Finished Jun 26 05:19:28 PM PDT 24
Peak memory 206208 kb
Host smart-25cfe994-0e97-4098-9eeb-456f3d0b2b25
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3113924124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.3113924124
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.3183337012
Short name T2522
Test name
Test status
Simulation time 13403606831 ps
CPU time 12.58 seconds
Started Jun 26 05:19:29 PM PDT 24
Finished Jun 26 05:19:42 PM PDT 24
Peak memory 206308 kb
Host smart-97386172-792c-4033-b072-f43b2b7ab26b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3183337012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.3183337012
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.75857382
Short name T901
Test name
Test status
Simulation time 23371913691 ps
CPU time 23.39 seconds
Started Jun 26 05:19:21 PM PDT 24
Finished Jun 26 05:19:47 PM PDT 24
Peak memory 206248 kb
Host smart-8b1a7d8d-8030-4b75-abdb-968c5344488b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=75857382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.75857382
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.2523446261
Short name T81
Test name
Test status
Simulation time 151253516 ps
CPU time 0.79 seconds
Started Jun 26 05:19:22 PM PDT 24
Finished Jun 26 05:19:25 PM PDT 24
Peak memory 206208 kb
Host smart-4c9a5bf6-1c2d-4f33-be12-40da933be645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25234
46261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.2523446261
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.2560191703
Short name T354
Test name
Test status
Simulation time 158273715 ps
CPU time 0.75 seconds
Started Jun 26 05:19:19 PM PDT 24
Finished Jun 26 05:19:23 PM PDT 24
Peak memory 206116 kb
Host smart-7ca4ecc6-349c-4190-861e-0ffad92742d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25601
91703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.2560191703
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.4031667602
Short name T2197
Test name
Test status
Simulation time 254289444 ps
CPU time 0.96 seconds
Started Jun 26 05:19:31 PM PDT 24
Finished Jun 26 05:19:33 PM PDT 24
Peak memory 206200 kb
Host smart-730a1f8f-2e7d-4ac0-ab53-b6b7c62ad414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40316
67602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.4031667602
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.1125950680
Short name T1030
Test name
Test status
Simulation time 409607570 ps
CPU time 1.11 seconds
Started Jun 26 05:19:32 PM PDT 24
Finished Jun 26 05:19:34 PM PDT 24
Peak memory 206192 kb
Host smart-d50e7115-1c33-469e-b4d9-d7fd44ee8e58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11259
50680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.1125950680
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.3842058461
Short name T91
Test name
Test status
Simulation time 15470683002 ps
CPU time 31.26 seconds
Started Jun 26 05:19:21 PM PDT 24
Finished Jun 26 05:19:55 PM PDT 24
Peak memory 206552 kb
Host smart-6153f829-0e65-4192-87c8-a593b5763078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38420
58461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.3842058461
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.1806483066
Short name T1867
Test name
Test status
Simulation time 507405043 ps
CPU time 1.39 seconds
Started Jun 26 05:19:23 PM PDT 24
Finished Jun 26 05:19:26 PM PDT 24
Peak memory 206176 kb
Host smart-ad13cd7f-aa4d-4c4b-a93a-291ee77b6480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18064
83066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.1806483066
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.3872719281
Short name T2375
Test name
Test status
Simulation time 139341606 ps
CPU time 0.75 seconds
Started Jun 26 05:19:33 PM PDT 24
Finished Jun 26 05:19:36 PM PDT 24
Peak memory 206172 kb
Host smart-384c5f74-5b44-42ae-8a16-c0113d62db3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38727
19281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.3872719281
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.714829998
Short name T888
Test name
Test status
Simulation time 43682967 ps
CPU time 0.67 seconds
Started Jun 26 05:19:34 PM PDT 24
Finished Jun 26 05:19:36 PM PDT 24
Peak memory 206440 kb
Host smart-ac8d33f6-d71b-4f18-a59e-f155f4239e7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71482
9998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.714829998
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.366864035
Short name T702
Test name
Test status
Simulation time 1003408235 ps
CPU time 2.24 seconds
Started Jun 26 05:19:33 PM PDT 24
Finished Jun 26 05:19:37 PM PDT 24
Peak memory 206384 kb
Host smart-6c8eb92e-0d15-4386-968e-1842933f0b83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36686
4035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.366864035
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.2968499283
Short name T2472
Test name
Test status
Simulation time 180146619 ps
CPU time 1.39 seconds
Started Jun 26 05:19:34 PM PDT 24
Finished Jun 26 05:19:37 PM PDT 24
Peak memory 206384 kb
Host smart-371b0cb1-9ce6-4440-918b-aceba7201567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29684
99283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.2968499283
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.2988305238
Short name T731
Test name
Test status
Simulation time 184004837 ps
CPU time 0.84 seconds
Started Jun 26 05:19:33 PM PDT 24
Finished Jun 26 05:19:36 PM PDT 24
Peak memory 206188 kb
Host smart-73d1df68-0331-4f14-86da-aa48b257437c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29883
05238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.2988305238
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.57448791
Short name T431
Test name
Test status
Simulation time 138698483 ps
CPU time 0.75 seconds
Started Jun 26 05:19:31 PM PDT 24
Finished Jun 26 05:19:33 PM PDT 24
Peak memory 206184 kb
Host smart-0cc1de7e-8db0-4321-af32-0a2b2a26e1d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57448
791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.57448791
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.469341615
Short name T2076
Test name
Test status
Simulation time 238191007 ps
CPU time 0.97 seconds
Started Jun 26 05:19:32 PM PDT 24
Finished Jun 26 05:19:35 PM PDT 24
Peak memory 206136 kb
Host smart-798a1b8d-73e0-4ef8-a76e-8032e15e1bda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46934
1615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.469341615
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.2004989137
Short name T1065
Test name
Test status
Simulation time 194559159 ps
CPU time 0.89 seconds
Started Jun 26 05:19:30 PM PDT 24
Finished Jun 26 05:19:32 PM PDT 24
Peak memory 206224 kb
Host smart-2391a1a5-3961-4bca-ba0a-d33c2d5dc88a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20049
89137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.2004989137
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.2778734665
Short name T784
Test name
Test status
Simulation time 23290603819 ps
CPU time 26.75 seconds
Started Jun 26 05:19:30 PM PDT 24
Finished Jun 26 05:19:57 PM PDT 24
Peak memory 206324 kb
Host smart-e3b3cf51-f394-4ffb-9946-a65d9e15aa1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27787
34665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.2778734665
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.3977518448
Short name T1160
Test name
Test status
Simulation time 3347118682 ps
CPU time 3.91 seconds
Started Jun 26 05:19:34 PM PDT 24
Finished Jun 26 05:19:40 PM PDT 24
Peak memory 206228 kb
Host smart-c46f5798-e148-4804-9500-65bc83c2b9bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39775
18448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.3977518448
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.1439740991
Short name T1461
Test name
Test status
Simulation time 11969821090 ps
CPU time 118.61 seconds
Started Jun 26 05:19:34 PM PDT 24
Finished Jun 26 05:21:35 PM PDT 24
Peak memory 206548 kb
Host smart-581d4cdb-2692-4cc4-ad52-8bfae0d8693e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14397
40991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.1439740991
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.3541694601
Short name T1128
Test name
Test status
Simulation time 7699727880 ps
CPU time 76.27 seconds
Started Jun 26 05:19:32 PM PDT 24
Finished Jun 26 05:20:49 PM PDT 24
Peak memory 206536 kb
Host smart-4ba2b039-6221-45ee-a146-a85709ca4092
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3541694601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.3541694601
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.751567393
Short name T1947
Test name
Test status
Simulation time 262502188 ps
CPU time 0.94 seconds
Started Jun 26 05:19:33 PM PDT 24
Finished Jun 26 05:19:36 PM PDT 24
Peak memory 206228 kb
Host smart-c48d6400-78a1-49ef-8372-4e75a53e339b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=751567393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.751567393
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.1659122229
Short name T1781
Test name
Test status
Simulation time 200391830 ps
CPU time 0.87 seconds
Started Jun 26 05:19:32 PM PDT 24
Finished Jun 26 05:19:35 PM PDT 24
Peak memory 206212 kb
Host smart-fc80cd39-c21f-4c23-9dc3-12b3097b880f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16591
22229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.1659122229
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.706421016
Short name T984
Test name
Test status
Simulation time 4399744860 ps
CPU time 121.19 seconds
Started Jun 26 05:19:33 PM PDT 24
Finished Jun 26 05:21:37 PM PDT 24
Peak memory 206504 kb
Host smart-f5176521-a5a6-4ab9-871f-d13fdd833612
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70642
1016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.706421016
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.670873796
Short name T1200
Test name
Test status
Simulation time 5149458334 ps
CPU time 38.84 seconds
Started Jun 26 05:19:35 PM PDT 24
Finished Jun 26 05:20:16 PM PDT 24
Peak memory 206496 kb
Host smart-4b55cab1-1563-4ba3-8579-6659615c3dc7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=670873796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.670873796
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.1647519158
Short name T613
Test name
Test status
Simulation time 159477645 ps
CPU time 0.77 seconds
Started Jun 26 05:19:31 PM PDT 24
Finished Jun 26 05:19:33 PM PDT 24
Peak memory 206228 kb
Host smart-92737f9f-e088-46bc-a997-73213067cb68
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1647519158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.1647519158
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.882782027
Short name T853
Test name
Test status
Simulation time 165458379 ps
CPU time 0.8 seconds
Started Jun 26 05:19:34 PM PDT 24
Finished Jun 26 05:19:37 PM PDT 24
Peak memory 206124 kb
Host smart-d3c117c3-6ed1-4084-a042-18b25f22ba7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88278
2027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.882782027
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.1638569726
Short name T145
Test name
Test status
Simulation time 178659751 ps
CPU time 0.83 seconds
Started Jun 26 05:19:32 PM PDT 24
Finished Jun 26 05:19:34 PM PDT 24
Peak memory 206124 kb
Host smart-a34ffec6-bf24-470b-82a1-1399ac20355f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16385
69726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.1638569726
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.3571881473
Short name T1171
Test name
Test status
Simulation time 177211923 ps
CPU time 0.79 seconds
Started Jun 26 05:19:31 PM PDT 24
Finished Jun 26 05:19:32 PM PDT 24
Peak memory 206396 kb
Host smart-f9bd2993-a615-42ab-944b-6a4a262e6eda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35718
81473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.3571881473
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.2544736205
Short name T997
Test name
Test status
Simulation time 178292790 ps
CPU time 0.91 seconds
Started Jun 26 05:19:34 PM PDT 24
Finished Jun 26 05:19:37 PM PDT 24
Peak memory 206232 kb
Host smart-d4ac3b5d-454f-486d-ad68-1a44add3235a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25447
36205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.2544736205
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.651703933
Short name T1448
Test name
Test status
Simulation time 176627010 ps
CPU time 0.8 seconds
Started Jun 26 05:19:32 PM PDT 24
Finished Jun 26 05:19:34 PM PDT 24
Peak memory 206204 kb
Host smart-9c895c91-05f7-4276-b5cd-f6c35421e956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65170
3933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.651703933
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.345097724
Short name T1820
Test name
Test status
Simulation time 150335635 ps
CPU time 0.76 seconds
Started Jun 26 05:19:31 PM PDT 24
Finished Jun 26 05:19:33 PM PDT 24
Peak memory 206220 kb
Host smart-173294c7-eccd-4ec7-97d0-4313d5cf0f26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34509
7724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.345097724
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.929874137
Short name T1646
Test name
Test status
Simulation time 253769555 ps
CPU time 1.02 seconds
Started Jun 26 05:19:33 PM PDT 24
Finished Jun 26 05:19:36 PM PDT 24
Peak memory 206232 kb
Host smart-b4613e7b-ee5f-4da6-bd45-4cc723469f72
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=929874137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.929874137
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.2831356849
Short name T2448
Test name
Test status
Simulation time 142170533 ps
CPU time 0.76 seconds
Started Jun 26 05:19:33 PM PDT 24
Finished Jun 26 05:19:36 PM PDT 24
Peak memory 206448 kb
Host smart-004b1ad9-303c-446f-8925-56a8d8a49c33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28313
56849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.2831356849
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.3404864555
Short name T1869
Test name
Test status
Simulation time 32758484 ps
CPU time 0.67 seconds
Started Jun 26 05:19:33 PM PDT 24
Finished Jun 26 05:19:36 PM PDT 24
Peak memory 206440 kb
Host smart-329dd4ab-f9db-472a-bb3f-3e4325ba5dc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34048
64555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.3404864555
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.1231553859
Short name T2419
Test name
Test status
Simulation time 22891713621 ps
CPU time 49.74 seconds
Started Jun 26 05:19:33 PM PDT 24
Finished Jun 26 05:20:24 PM PDT 24
Peak memory 206524 kb
Host smart-27299bf1-26b1-4f9d-b1b7-fe5611f4bb78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12315
53859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.1231553859
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.1309426599
Short name T292
Test name
Test status
Simulation time 194490408 ps
CPU time 0.86 seconds
Started Jun 26 05:19:32 PM PDT 24
Finished Jun 26 05:19:34 PM PDT 24
Peak memory 206132 kb
Host smart-c7ecaa63-7e1d-4675-9c17-cc0ec32b681e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13094
26599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.1309426599
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.2679207591
Short name T654
Test name
Test status
Simulation time 212644902 ps
CPU time 0.85 seconds
Started Jun 26 05:19:32 PM PDT 24
Finished Jun 26 05:19:34 PM PDT 24
Peak memory 206140 kb
Host smart-46a6d4c5-2339-4783-8636-ec6898629b05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26792
07591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.2679207591
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.3995479190
Short name T560
Test name
Test status
Simulation time 211958092 ps
CPU time 0.86 seconds
Started Jun 26 05:19:32 PM PDT 24
Finished Jun 26 05:19:34 PM PDT 24
Peak memory 206192 kb
Host smart-12c6c287-4811-4350-806d-e21ab1a37773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39954
79190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.3995479190
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.2931088480
Short name T1576
Test name
Test status
Simulation time 144031343 ps
CPU time 0.79 seconds
Started Jun 26 05:19:34 PM PDT 24
Finished Jun 26 05:19:37 PM PDT 24
Peak memory 206120 kb
Host smart-f6d9ebf0-b757-4622-97ff-6047a257e329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29310
88480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.2931088480
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.576177245
Short name T1344
Test name
Test status
Simulation time 166081335 ps
CPU time 0.8 seconds
Started Jun 26 05:19:34 PM PDT 24
Finished Jun 26 05:19:36 PM PDT 24
Peak memory 206176 kb
Host smart-4aa5490b-3bdc-4283-8b65-99cd994a86d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57617
7245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.576177245
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.2038746456
Short name T2189
Test name
Test status
Simulation time 156702959 ps
CPU time 0.77 seconds
Started Jun 26 05:19:28 PM PDT 24
Finished Jun 26 05:19:29 PM PDT 24
Peak memory 206168 kb
Host smart-6a29effe-4204-43e4-9aaa-c3415f80f93a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20387
46456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.2038746456
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.2821469329
Short name T556
Test name
Test status
Simulation time 175025498 ps
CPU time 0.87 seconds
Started Jun 26 05:19:35 PM PDT 24
Finished Jun 26 05:19:38 PM PDT 24
Peak memory 206244 kb
Host smart-818aaf6b-ec43-451f-93ba-82f3b1fe096a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28214
69329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.2821469329
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.2566808433
Short name T1211
Test name
Test status
Simulation time 279393193 ps
CPU time 1.03 seconds
Started Jun 26 05:19:33 PM PDT 24
Finished Jun 26 05:19:36 PM PDT 24
Peak memory 206224 kb
Host smart-b19c6c38-5a8a-4c19-82be-5f22a30298f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25668
08433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.2566808433
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.1193540309
Short name T260
Test name
Test status
Simulation time 3514905305 ps
CPU time 25.18 seconds
Started Jun 26 05:19:33 PM PDT 24
Finished Jun 26 05:20:00 PM PDT 24
Peak memory 206352 kb
Host smart-39a32d75-bc4e-4705-aaf8-f9135b672864
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1193540309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.1193540309
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.2621915669
Short name T523
Test name
Test status
Simulation time 190157019 ps
CPU time 0.8 seconds
Started Jun 26 05:19:32 PM PDT 24
Finished Jun 26 05:19:35 PM PDT 24
Peak memory 206212 kb
Host smart-10211729-4ff9-4b6b-afd5-bf6c99910a00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26219
15669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.2621915669
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.1227878212
Short name T819
Test name
Test status
Simulation time 160708115 ps
CPU time 0.82 seconds
Started Jun 26 05:19:32 PM PDT 24
Finished Jun 26 05:19:34 PM PDT 24
Peak memory 206120 kb
Host smart-58dce1ce-6e51-41ec-b649-b2fe6cfe37dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12278
78212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.1227878212
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.3672797964
Short name T966
Test name
Test status
Simulation time 4584158123 ps
CPU time 33.18 seconds
Started Jun 26 05:19:33 PM PDT 24
Finished Jun 26 05:20:08 PM PDT 24
Peak memory 206744 kb
Host smart-ddafd492-04f7-4d15-8fe7-8cbcc725fc18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36727
97964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.3672797964
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.1338278249
Short name T2458
Test name
Test status
Simulation time 4362477753 ps
CPU time 4.98 seconds
Started Jun 26 05:19:36 PM PDT 24
Finished Jun 26 05:19:43 PM PDT 24
Peak memory 206264 kb
Host smart-0a7fc6fc-88aa-4e92-9b7d-f40cd7ebfa20
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1338278249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.1338278249
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.2467832868
Short name T2044
Test name
Test status
Simulation time 13400407274 ps
CPU time 12.42 seconds
Started Jun 26 05:19:38 PM PDT 24
Finished Jun 26 05:19:52 PM PDT 24
Peak memory 206348 kb
Host smart-e8106276-f1b6-49b3-a7c5-7e6e1c3b3371
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2467832868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.2467832868
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.4043973858
Short name T579
Test name
Test status
Simulation time 23419755856 ps
CPU time 21.57 seconds
Started Jun 26 05:19:37 PM PDT 24
Finished Jun 26 05:20:01 PM PDT 24
Peak memory 206580 kb
Host smart-3ae4010c-dfb1-4dbe-a687-e33712d9fed0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4043973858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.4043973858
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.1453143453
Short name T1704
Test name
Test status
Simulation time 147713443 ps
CPU time 0.77 seconds
Started Jun 26 05:19:35 PM PDT 24
Finished Jun 26 05:19:38 PM PDT 24
Peak memory 206176 kb
Host smart-b0735fa6-4f46-4233-936a-800fabbfc9be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14531
43453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.1453143453
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.3709132724
Short name T55
Test name
Test status
Simulation time 185796080 ps
CPU time 0.83 seconds
Started Jun 26 05:19:36 PM PDT 24
Finished Jun 26 05:19:39 PM PDT 24
Peak memory 206204 kb
Host smart-d2cf1a4f-f2a3-4d4b-9980-e2e0118d0b48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37091
32724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.3709132724
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.780458891
Short name T1585
Test name
Test status
Simulation time 514086174 ps
CPU time 1.54 seconds
Started Jun 26 05:19:40 PM PDT 24
Finished Jun 26 05:19:42 PM PDT 24
Peak memory 206400 kb
Host smart-a870d5d5-2a5f-4d83-b402-731a4472462a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78045
8891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.780458891
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.1212193998
Short name T2233
Test name
Test status
Simulation time 419457672 ps
CPU time 1.18 seconds
Started Jun 26 05:19:38 PM PDT 24
Finished Jun 26 05:19:40 PM PDT 24
Peak memory 206224 kb
Host smart-0fe63edb-1731-4c4e-8ecb-ab1893431914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12121
93998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.1212193998
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.450842196
Short name T943
Test name
Test status
Simulation time 19014206081 ps
CPU time 34.91 seconds
Started Jun 26 05:19:37 PM PDT 24
Finished Jun 26 05:20:14 PM PDT 24
Peak memory 206420 kb
Host smart-04bb42d2-e3dc-4876-9123-ca7cef5ab40b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45084
2196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.450842196
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.2563905473
Short name T1994
Test name
Test status
Simulation time 355468943 ps
CPU time 1.18 seconds
Started Jun 26 05:19:41 PM PDT 24
Finished Jun 26 05:19:43 PM PDT 24
Peak memory 206124 kb
Host smart-330528c4-6bbf-47c7-aaa1-322f8932296c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25639
05473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.2563905473
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.833039873
Short name T1295
Test name
Test status
Simulation time 155529324 ps
CPU time 0.87 seconds
Started Jun 26 05:19:37 PM PDT 24
Finished Jun 26 05:19:40 PM PDT 24
Peak memory 206116 kb
Host smart-46180977-c726-4fa9-b06e-b54691ef531a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83303
9873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.833039873
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.1872833425
Short name T1266
Test name
Test status
Simulation time 55505915 ps
CPU time 0.68 seconds
Started Jun 26 05:19:36 PM PDT 24
Finished Jun 26 05:19:39 PM PDT 24
Peak memory 206212 kb
Host smart-22febd7e-fdc3-4313-a79c-453d627c6d95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18728
33425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.1872833425
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.1479329205
Short name T1391
Test name
Test status
Simulation time 973620062 ps
CPU time 2.21 seconds
Started Jun 26 05:19:36 PM PDT 24
Finished Jun 26 05:19:40 PM PDT 24
Peak memory 206400 kb
Host smart-50de817b-0838-4d05-ba7f-317f2380d973
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14793
29205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.1479329205
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.4255816612
Short name T2291
Test name
Test status
Simulation time 297191111 ps
CPU time 2.05 seconds
Started Jun 26 05:19:37 PM PDT 24
Finished Jun 26 05:19:41 PM PDT 24
Peak memory 206404 kb
Host smart-259457e1-89f9-447b-b8f7-af13576d397f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42558
16612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.4255816612
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.881764015
Short name T1157
Test name
Test status
Simulation time 257790626 ps
CPU time 0.9 seconds
Started Jun 26 05:19:47 PM PDT 24
Finished Jun 26 05:19:50 PM PDT 24
Peak memory 206140 kb
Host smart-8d374fed-a2bd-441f-993e-d44eaf8a5714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88176
4015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.881764015
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.2048738915
Short name T1037
Test name
Test status
Simulation time 166061153 ps
CPU time 0.75 seconds
Started Jun 26 05:19:47 PM PDT 24
Finished Jun 26 05:19:49 PM PDT 24
Peak memory 206140 kb
Host smart-8aab8f70-e7e8-41f9-881e-a55ba753944f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20487
38915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.2048738915
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.2497169613
Short name T627
Test name
Test status
Simulation time 163521651 ps
CPU time 0.8 seconds
Started Jun 26 05:19:37 PM PDT 24
Finished Jun 26 05:19:40 PM PDT 24
Peak memory 206128 kb
Host smart-32258e72-a1ee-497f-8ef7-930e0327947f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24971
69613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.2497169613
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_invalid_sync.877058124
Short name T493
Test name
Test status
Simulation time 7447950052 ps
CPU time 50.81 seconds
Started Jun 26 05:19:35 PM PDT 24
Finished Jun 26 05:20:29 PM PDT 24
Peak memory 206480 kb
Host smart-01bf0bf9-5be4-43d7-b776-f18a2aed2884
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=877058124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.877058124
Directory /workspace/35.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.3358800014
Short name T569
Test name
Test status
Simulation time 168687508 ps
CPU time 0.86 seconds
Started Jun 26 05:19:35 PM PDT 24
Finished Jun 26 05:19:38 PM PDT 24
Peak memory 206188 kb
Host smart-4f28e54e-ea8b-4612-8fae-3522cacbc572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33588
00014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.3358800014
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.2680550418
Short name T1671
Test name
Test status
Simulation time 23287663720 ps
CPU time 24.71 seconds
Started Jun 26 05:19:41 PM PDT 24
Finished Jun 26 05:20:06 PM PDT 24
Peak memory 206236 kb
Host smart-33cf48b4-df20-4d66-bf73-ce372af2b82d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26805
50418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.2680550418
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.1385789402
Short name T1225
Test name
Test status
Simulation time 3311989556 ps
CPU time 3.95 seconds
Started Jun 26 05:19:40 PM PDT 24
Finished Jun 26 05:19:45 PM PDT 24
Peak memory 206264 kb
Host smart-4001a99c-f67a-4f46-8f9a-900248885601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13857
89402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.1385789402
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.52394005
Short name T485
Test name
Test status
Simulation time 7030635989 ps
CPU time 68.35 seconds
Started Jun 26 05:19:35 PM PDT 24
Finished Jun 26 05:20:45 PM PDT 24
Peak memory 206452 kb
Host smart-d378fa29-0bbc-4170-b435-367a8d608a13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52394
005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.52394005
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.3841875432
Short name T385
Test name
Test status
Simulation time 6813937535 ps
CPU time 46.21 seconds
Started Jun 26 05:19:37 PM PDT 24
Finished Jun 26 05:20:25 PM PDT 24
Peak memory 206636 kb
Host smart-e1ad3dd8-06a8-4642-826a-299ab6b75043
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3841875432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.3841875432
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.1724022273
Short name T2302
Test name
Test status
Simulation time 236559044 ps
CPU time 0.92 seconds
Started Jun 26 05:19:44 PM PDT 24
Finished Jun 26 05:19:46 PM PDT 24
Peak memory 206144 kb
Host smart-8b2762c1-421b-4054-941d-e3b48e74967e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1724022273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.1724022273
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.55311734
Short name T570
Test name
Test status
Simulation time 186582251 ps
CPU time 0.83 seconds
Started Jun 26 05:19:37 PM PDT 24
Finished Jun 26 05:19:40 PM PDT 24
Peak memory 206080 kb
Host smart-fba2c130-ce20-4e50-bbcb-185bf5532205
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55311
734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.55311734
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.2516710439
Short name T1484
Test name
Test status
Simulation time 5844710249 ps
CPU time 54.56 seconds
Started Jun 26 05:19:35 PM PDT 24
Finished Jun 26 05:20:31 PM PDT 24
Peak memory 206592 kb
Host smart-507139fc-5ff5-44ab-8d6b-4978f7b00f8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25167
10439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.2516710439
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.1509079015
Short name T1133
Test name
Test status
Simulation time 4451960883 ps
CPU time 116.46 seconds
Started Jun 26 05:19:40 PM PDT 24
Finished Jun 26 05:21:37 PM PDT 24
Peak memory 206564 kb
Host smart-d1303438-52b7-453a-afca-1089000716e6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1509079015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.1509079015
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.2473390571
Short name T487
Test name
Test status
Simulation time 159912746 ps
CPU time 0.78 seconds
Started Jun 26 05:19:44 PM PDT 24
Finished Jun 26 05:19:46 PM PDT 24
Peak memory 206212 kb
Host smart-12ad5237-0e77-4938-82bf-5da6f983e07c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2473390571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.2473390571
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.3671725699
Short name T2268
Test name
Test status
Simulation time 195045520 ps
CPU time 0.88 seconds
Started Jun 26 05:19:42 PM PDT 24
Finished Jun 26 05:19:44 PM PDT 24
Peak memory 206128 kb
Host smart-3ba19be2-27f3-46dc-8d8d-3eaed4449085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36717
25699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.3671725699
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.3031995604
Short name T133
Test name
Test status
Simulation time 218653307 ps
CPU time 0.89 seconds
Started Jun 26 05:19:42 PM PDT 24
Finished Jun 26 05:19:44 PM PDT 24
Peak memory 206128 kb
Host smart-6c89516c-5004-4466-87d2-56ac6dc0523a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30319
95604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.3031995604
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.387415641
Short name T1389
Test name
Test status
Simulation time 161600237 ps
CPU time 0.81 seconds
Started Jun 26 05:19:37 PM PDT 24
Finished Jun 26 05:19:40 PM PDT 24
Peak memory 206140 kb
Host smart-2b64ddf4-887f-4f7a-a155-b09ac718e937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38741
5641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.387415641
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.2991434508
Short name T1821
Test name
Test status
Simulation time 163968125 ps
CPU time 0.76 seconds
Started Jun 26 05:19:37 PM PDT 24
Finished Jun 26 05:19:40 PM PDT 24
Peak memory 206200 kb
Host smart-72b0a9d4-d26f-46b4-a6db-d59ff10a176d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29914
34508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.2991434508
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.10824328
Short name T223
Test name
Test status
Simulation time 204246425 ps
CPU time 0.88 seconds
Started Jun 26 05:19:38 PM PDT 24
Finished Jun 26 05:19:40 PM PDT 24
Peak memory 206216 kb
Host smart-366cb3a8-ab76-4db4-ba59-9cb3c9f191a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10824
328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.10824328
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.4280755196
Short name T1386
Test name
Test status
Simulation time 155136290 ps
CPU time 0.79 seconds
Started Jun 26 05:19:43 PM PDT 24
Finished Jun 26 05:19:44 PM PDT 24
Peak memory 206200 kb
Host smart-e7065742-3cc1-4e9c-9d86-ff21f4668abc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42807
55196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.4280755196
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.4155521220
Short name T367
Test name
Test status
Simulation time 207322877 ps
CPU time 0.85 seconds
Started Jun 26 05:19:36 PM PDT 24
Finished Jun 26 05:19:39 PM PDT 24
Peak memory 206144 kb
Host smart-97ce4f9a-4544-47c4-ad5b-f4b57c7a397c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4155521220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.4155521220
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.1809054389
Short name T1850
Test name
Test status
Simulation time 185710004 ps
CPU time 0.82 seconds
Started Jun 26 05:19:36 PM PDT 24
Finished Jun 26 05:19:38 PM PDT 24
Peak memory 206116 kb
Host smart-bbbccc05-d230-4c98-8199-48f80931224f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18090
54389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.1809054389
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.1676953432
Short name T1090
Test name
Test status
Simulation time 59076113 ps
CPU time 0.68 seconds
Started Jun 26 05:19:46 PM PDT 24
Finished Jun 26 05:19:48 PM PDT 24
Peak memory 206120 kb
Host smart-78c0d35b-7a07-4aff-9386-b4f508b89d94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16769
53432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.1676953432
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.700474677
Short name T246
Test name
Test status
Simulation time 6957488385 ps
CPU time 16.28 seconds
Started Jun 26 05:19:39 PM PDT 24
Finished Jun 26 05:19:57 PM PDT 24
Peak memory 206596 kb
Host smart-e50fa782-bbb8-45c1-b95d-abb47de94167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70047
4677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.700474677
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.1686664612
Short name T2323
Test name
Test status
Simulation time 206090765 ps
CPU time 0.89 seconds
Started Jun 26 05:19:38 PM PDT 24
Finished Jun 26 05:19:40 PM PDT 24
Peak memory 206172 kb
Host smart-b8cb9a7e-f5f0-4be7-b072-4dc0b0f9d287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16866
64612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.1686664612
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.589627038
Short name T803
Test name
Test status
Simulation time 186398584 ps
CPU time 0.84 seconds
Started Jun 26 05:19:49 PM PDT 24
Finished Jun 26 05:19:52 PM PDT 24
Peak memory 206212 kb
Host smart-85c50e0e-eabf-4cf9-8043-a84b395bc135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58962
7038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.589627038
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.3288033520
Short name T875
Test name
Test status
Simulation time 208225069 ps
CPU time 0.83 seconds
Started Jun 26 05:19:50 PM PDT 24
Finished Jun 26 05:19:52 PM PDT 24
Peak memory 206224 kb
Host smart-625536ec-e94b-44b5-8c9b-9f42985b8626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32880
33520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.3288033520
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.2409934048
Short name T1254
Test name
Test status
Simulation time 146429427 ps
CPU time 0.82 seconds
Started Jun 26 05:19:43 PM PDT 24
Finished Jun 26 05:19:45 PM PDT 24
Peak memory 206180 kb
Host smart-5a8b2d6c-898a-4343-bee6-73e32ca68684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24099
34048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.2409934048
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.970757866
Short name T688
Test name
Test status
Simulation time 193283714 ps
CPU time 0.8 seconds
Started Jun 26 05:19:48 PM PDT 24
Finished Jun 26 05:19:50 PM PDT 24
Peak memory 206100 kb
Host smart-be53792a-d200-4b69-b7a8-bed2e599407b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97075
7866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.970757866
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.2679294232
Short name T2055
Test name
Test status
Simulation time 192758525 ps
CPU time 0.82 seconds
Started Jun 26 05:19:50 PM PDT 24
Finished Jun 26 05:19:52 PM PDT 24
Peak memory 206196 kb
Host smart-54386595-828b-4cef-b0fc-e268d5ba39ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26792
94232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.2679294232
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.1990496907
Short name T717
Test name
Test status
Simulation time 193227550 ps
CPU time 0.85 seconds
Started Jun 26 05:19:48 PM PDT 24
Finished Jun 26 05:19:50 PM PDT 24
Peak memory 206216 kb
Host smart-297b0986-4611-47b8-8ca3-750d9d1235c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19904
96907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.1990496907
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.71307993
Short name T1334
Test name
Test status
Simulation time 248068594 ps
CPU time 0.98 seconds
Started Jun 26 05:19:45 PM PDT 24
Finished Jun 26 05:19:47 PM PDT 24
Peak memory 206168 kb
Host smart-5e25baf7-45ba-4da0-91af-cf7ae1a099fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71307
993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.71307993
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.2860702766
Short name T2018
Test name
Test status
Simulation time 5473198263 ps
CPU time 145.9 seconds
Started Jun 26 05:19:44 PM PDT 24
Finished Jun 26 05:22:11 PM PDT 24
Peak memory 206508 kb
Host smart-60dd03d1-0c73-4799-936f-709cef54924b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2860702766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.2860702766
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.382554612
Short name T593
Test name
Test status
Simulation time 188718990 ps
CPU time 0.79 seconds
Started Jun 26 05:19:43 PM PDT 24
Finished Jun 26 05:19:44 PM PDT 24
Peak memory 206208 kb
Host smart-537b7022-99c3-469e-8f3d-1b6a00154d35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38255
4612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.382554612
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.1862080697
Short name T1678
Test name
Test status
Simulation time 192889335 ps
CPU time 0.84 seconds
Started Jun 26 05:19:46 PM PDT 24
Finished Jun 26 05:19:48 PM PDT 24
Peak memory 206204 kb
Host smart-1f479686-a85b-4014-898e-cd8b6e57fb6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18620
80697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.1862080697
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.634265101
Short name T2325
Test name
Test status
Simulation time 4003217077 ps
CPU time 29.58 seconds
Started Jun 26 05:19:47 PM PDT 24
Finished Jun 26 05:20:18 PM PDT 24
Peak memory 206364 kb
Host smart-23f975a6-1e6b-4a23-8522-6bc1500d9a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63426
5101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.634265101
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.3404753344
Short name T1872
Test name
Test status
Simulation time 3642863730 ps
CPU time 5.24 seconds
Started Jun 26 05:19:47 PM PDT 24
Finished Jun 26 05:19:54 PM PDT 24
Peak memory 206420 kb
Host smart-af7f881a-6a5d-4c16-9466-3de62bc42d6e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3404753344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.3404753344
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.706023916
Short name T2358
Test name
Test status
Simulation time 13380527070 ps
CPU time 13.59 seconds
Started Jun 26 05:19:44 PM PDT 24
Finished Jun 26 05:19:59 PM PDT 24
Peak memory 206328 kb
Host smart-637889ef-8653-4e28-a74f-bc5918af939b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=706023916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.706023916
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.3067489450
Short name T1794
Test name
Test status
Simulation time 23374483418 ps
CPU time 24.25 seconds
Started Jun 26 05:19:44 PM PDT 24
Finished Jun 26 05:20:10 PM PDT 24
Peak memory 206584 kb
Host smart-0037c8de-18b8-4dd5-9a5e-9e0166dd90be
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3067489450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.3067489450
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.2532678873
Short name T1458
Test name
Test status
Simulation time 194950921 ps
CPU time 0.82 seconds
Started Jun 26 05:19:47 PM PDT 24
Finished Jun 26 05:19:49 PM PDT 24
Peak memory 206124 kb
Host smart-d1b36507-e414-42e8-be77-5dd3f6817305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25326
78873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.2532678873
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.1126373297
Short name T2153
Test name
Test status
Simulation time 144570005 ps
CPU time 0.76 seconds
Started Jun 26 05:19:48 PM PDT 24
Finished Jun 26 05:19:50 PM PDT 24
Peak memory 206120 kb
Host smart-011147aa-7b66-406b-9a9e-3bbfd52b4989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11263
73297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.1126373297
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.2885208896
Short name T164
Test name
Test status
Simulation time 403151739 ps
CPU time 1.22 seconds
Started Jun 26 05:19:45 PM PDT 24
Finished Jun 26 05:19:48 PM PDT 24
Peak memory 206208 kb
Host smart-4bc84a8d-0155-48b3-abc3-dd69a8e0277e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28852
08896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.2885208896
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.3275893852
Short name T542
Test name
Test status
Simulation time 538068725 ps
CPU time 1.48 seconds
Started Jun 26 05:19:48 PM PDT 24
Finished Jun 26 05:19:50 PM PDT 24
Peak memory 206140 kb
Host smart-263500b6-0b6e-414e-8877-fee31663eff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32758
93852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.3275893852
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.652561196
Short name T181
Test name
Test status
Simulation time 12592084357 ps
CPU time 23.2 seconds
Started Jun 26 05:19:45 PM PDT 24
Finished Jun 26 05:20:09 PM PDT 24
Peak memory 206600 kb
Host smart-4ec09e40-d485-4ed1-9219-5d0f5a31f68e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65256
1196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.652561196
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.3990405385
Short name T960
Test name
Test status
Simulation time 337619183 ps
CPU time 1.12 seconds
Started Jun 26 05:19:46 PM PDT 24
Finished Jun 26 05:19:48 PM PDT 24
Peak memory 206212 kb
Host smart-27879b3a-1fc3-4293-a110-9d8b4c5b041f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39904
05385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.3990405385
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.1964805821
Short name T1477
Test name
Test status
Simulation time 147218000 ps
CPU time 0.75 seconds
Started Jun 26 05:19:44 PM PDT 24
Finished Jun 26 05:19:46 PM PDT 24
Peak memory 206200 kb
Host smart-32728c25-2fe6-4cc0-b30c-47320142a251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19648
05821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.1964805821
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.769491611
Short name T1020
Test name
Test status
Simulation time 34827974 ps
CPU time 0.68 seconds
Started Jun 26 05:19:43 PM PDT 24
Finished Jun 26 05:19:45 PM PDT 24
Peak memory 206216 kb
Host smart-c48771b3-3009-43f4-b56a-72661dd28f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76949
1611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.769491611
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.1233588689
Short name T351
Test name
Test status
Simulation time 866606413 ps
CPU time 2.08 seconds
Started Jun 26 05:19:46 PM PDT 24
Finished Jun 26 05:19:49 PM PDT 24
Peak memory 206416 kb
Host smart-0a359b7e-fc6e-4901-a5cb-53c7a375bb7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12335
88689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.1233588689
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.2045728484
Short name T2296
Test name
Test status
Simulation time 178339297 ps
CPU time 2.06 seconds
Started Jun 26 05:19:47 PM PDT 24
Finished Jun 26 05:19:50 PM PDT 24
Peak memory 206424 kb
Host smart-1084b2b8-82a2-4261-bddf-851fa02b28eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20457
28484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.2045728484
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.75656482
Short name T2123
Test name
Test status
Simulation time 203638198 ps
CPU time 0.84 seconds
Started Jun 26 05:19:53 PM PDT 24
Finished Jun 26 05:19:55 PM PDT 24
Peak memory 206196 kb
Host smart-5ee9100f-e558-4a04-8864-eeedd713ba12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75656
482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.75656482
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.3627500261
Short name T1111
Test name
Test status
Simulation time 147966071 ps
CPU time 0.76 seconds
Started Jun 26 05:19:51 PM PDT 24
Finished Jun 26 05:19:53 PM PDT 24
Peak memory 206132 kb
Host smart-dcd53050-8d9c-4e22-b3bc-e70e387e6ca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36275
00261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.3627500261
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.4281237185
Short name T339
Test name
Test status
Simulation time 206889775 ps
CPU time 0.88 seconds
Started Jun 26 05:19:47 PM PDT 24
Finished Jun 26 05:19:50 PM PDT 24
Peak memory 206140 kb
Host smart-e886eed7-3b38-4bb7-a83f-5b5758936d6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42812
37185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.4281237185
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.1882544919
Short name T52
Test name
Test status
Simulation time 248219338 ps
CPU time 0.92 seconds
Started Jun 26 05:19:49 PM PDT 24
Finished Jun 26 05:19:51 PM PDT 24
Peak memory 206128 kb
Host smart-2f44af45-70bb-4376-afc7-372bcf340b60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18825
44919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.1882544919
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.14208880
Short name T461
Test name
Test status
Simulation time 23329509133 ps
CPU time 24.3 seconds
Started Jun 26 05:19:52 PM PDT 24
Finished Jun 26 05:20:18 PM PDT 24
Peak memory 206300 kb
Host smart-5143abe8-1b50-486c-b4a7-93c70414ab83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14208
880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.14208880
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.2068001384
Short name T1641
Test name
Test status
Simulation time 3307495165 ps
CPU time 3.74 seconds
Started Jun 26 05:19:49 PM PDT 24
Finished Jun 26 05:19:54 PM PDT 24
Peak memory 206180 kb
Host smart-f34a2d2b-f0ae-4cd8-a9bd-1a534c8815c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20680
01384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.2068001384
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.1348824443
Short name T763
Test name
Test status
Simulation time 11154091363 ps
CPU time 313.99 seconds
Started Jun 26 05:19:51 PM PDT 24
Finished Jun 26 05:25:07 PM PDT 24
Peak memory 206516 kb
Host smart-95b760b9-0d0c-4124-b62a-d769aa7d7712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13488
24443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.1348824443
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.565684946
Short name T1943
Test name
Test status
Simulation time 5655021215 ps
CPU time 51.08 seconds
Started Jun 26 05:19:50 PM PDT 24
Finished Jun 26 05:20:43 PM PDT 24
Peak memory 206440 kb
Host smart-fbc7f81d-a117-4709-80af-ad1a5533f158
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=565684946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.565684946
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.3625972323
Short name T947
Test name
Test status
Simulation time 299748879 ps
CPU time 0.93 seconds
Started Jun 26 05:19:52 PM PDT 24
Finished Jun 26 05:19:55 PM PDT 24
Peak memory 206248 kb
Host smart-980c4ffc-aba6-4bb9-8fbe-ef13f6128a3c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3625972323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.3625972323
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.2671530881
Short name T1713
Test name
Test status
Simulation time 196985590 ps
CPU time 0.87 seconds
Started Jun 26 05:19:50 PM PDT 24
Finished Jun 26 05:19:52 PM PDT 24
Peak memory 206156 kb
Host smart-6d918308-93d9-4092-96f5-5d644b9494c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26715
30881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.2671530881
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.2738469821
Short name T1420
Test name
Test status
Simulation time 3817104845 ps
CPU time 27.34 seconds
Started Jun 26 05:19:47 PM PDT 24
Finished Jun 26 05:20:16 PM PDT 24
Peak memory 206440 kb
Host smart-8044eb6f-7ba0-4f66-abe8-8d1d09705ac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27384
69821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.2738469821
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.1350465319
Short name T684
Test name
Test status
Simulation time 3119824508 ps
CPU time 86.72 seconds
Started Jun 26 05:19:51 PM PDT 24
Finished Jun 26 05:21:19 PM PDT 24
Peak memory 206392 kb
Host smart-9ba5415c-7e6b-4e47-9aee-9debc91b0dc3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1350465319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.1350465319
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.1441794593
Short name T217
Test name
Test status
Simulation time 154533821 ps
CPU time 0.85 seconds
Started Jun 26 05:19:54 PM PDT 24
Finished Jun 26 05:19:56 PM PDT 24
Peak memory 206248 kb
Host smart-b5ba02ac-965a-4e91-8116-8bd91c3bf578
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1441794593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.1441794593
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.936906894
Short name T665
Test name
Test status
Simulation time 191932809 ps
CPU time 0.82 seconds
Started Jun 26 05:19:52 PM PDT 24
Finished Jun 26 05:19:54 PM PDT 24
Peak memory 206104 kb
Host smart-c04332ee-d684-4d23-9b30-2c13a8213b9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93690
6894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.936906894
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.3376989769
Short name T120
Test name
Test status
Simulation time 202655317 ps
CPU time 0.84 seconds
Started Jun 26 05:19:52 PM PDT 24
Finished Jun 26 05:19:55 PM PDT 24
Peak memory 206176 kb
Host smart-b111ae54-d55a-4480-aa4d-e048a785f63c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33769
89769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.3376989769
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.413528060
Short name T78
Test name
Test status
Simulation time 172654675 ps
CPU time 0.83 seconds
Started Jun 26 05:19:51 PM PDT 24
Finished Jun 26 05:19:53 PM PDT 24
Peak memory 206224 kb
Host smart-343004d7-e74f-43df-bad2-dcba626f85d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41352
8060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.413528060
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.1105868478
Short name T2443
Test name
Test status
Simulation time 201748800 ps
CPU time 0.83 seconds
Started Jun 26 05:19:51 PM PDT 24
Finished Jun 26 05:19:53 PM PDT 24
Peak memory 206120 kb
Host smart-832e9d11-f5c5-4563-bd74-06b5924a8568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11058
68478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.1105868478
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.4127564684
Short name T2065
Test name
Test status
Simulation time 165305191 ps
CPU time 0.77 seconds
Started Jun 26 05:19:50 PM PDT 24
Finished Jun 26 05:19:53 PM PDT 24
Peak memory 206120 kb
Host smart-eaa68926-b4c7-4241-83bc-b93d310b9d50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41275
64684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.4127564684
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.2340229726
Short name T698
Test name
Test status
Simulation time 182858168 ps
CPU time 0.84 seconds
Started Jun 26 05:19:49 PM PDT 24
Finished Jun 26 05:19:51 PM PDT 24
Peak memory 206212 kb
Host smart-be0741b5-333a-4f5a-9805-dd78fdb87d7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23402
29726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.2340229726
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.2315679160
Short name T1724
Test name
Test status
Simulation time 214889440 ps
CPU time 0.92 seconds
Started Jun 26 05:19:54 PM PDT 24
Finished Jun 26 05:19:56 PM PDT 24
Peak memory 206216 kb
Host smart-59536ecc-19ae-4706-85ed-baca2aa1b594
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2315679160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.2315679160
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.3457997689
Short name T1769
Test name
Test status
Simulation time 168866275 ps
CPU time 0.75 seconds
Started Jun 26 05:19:49 PM PDT 24
Finished Jun 26 05:19:51 PM PDT 24
Peak memory 206124 kb
Host smart-c63c9c8c-9057-4384-98af-3229b260d1c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34579
97689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.3457997689
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.3130744185
Short name T2061
Test name
Test status
Simulation time 44521774 ps
CPU time 0.68 seconds
Started Jun 26 05:19:50 PM PDT 24
Finished Jun 26 05:19:52 PM PDT 24
Peak memory 206188 kb
Host smart-35f1c22b-efe5-4fe4-9ba4-9d787259256a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31307
44185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.3130744185
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.392611933
Short name T254
Test name
Test status
Simulation time 10167706260 ps
CPU time 22.28 seconds
Started Jun 26 05:19:50 PM PDT 24
Finished Jun 26 05:20:14 PM PDT 24
Peak memory 206492 kb
Host smart-537ccbd2-9351-4eb4-b2bd-2fdd29c9e626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39261
1933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.392611933
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.3818404902
Short name T670
Test name
Test status
Simulation time 150953405 ps
CPU time 0.8 seconds
Started Jun 26 05:19:52 PM PDT 24
Finished Jun 26 05:19:55 PM PDT 24
Peak memory 206212 kb
Host smart-d667e2af-3fdf-477b-be9f-620b8937c73c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38184
04902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.3818404902
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.242814268
Short name T892
Test name
Test status
Simulation time 156377098 ps
CPU time 0.8 seconds
Started Jun 26 05:19:51 PM PDT 24
Finished Jun 26 05:19:53 PM PDT 24
Peak memory 206132 kb
Host smart-9cbd19ee-f69a-4570-8821-c077b02e7562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24281
4268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.242814268
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.1740615547
Short name T328
Test name
Test status
Simulation time 189155531 ps
CPU time 0.84 seconds
Started Jun 26 05:19:51 PM PDT 24
Finished Jun 26 05:19:53 PM PDT 24
Peak memory 206144 kb
Host smart-921d857a-d275-4cbc-b257-a8cad452a873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17406
15547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.1740615547
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.2429146565
Short name T746
Test name
Test status
Simulation time 188489442 ps
CPU time 0.97 seconds
Started Jun 26 05:19:52 PM PDT 24
Finished Jun 26 05:19:54 PM PDT 24
Peak memory 206140 kb
Host smart-feb5ab9d-cb57-4b73-910a-75045e6f20b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24291
46565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.2429146565
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.388465660
Short name T1419
Test name
Test status
Simulation time 193508034 ps
CPU time 0.88 seconds
Started Jun 26 05:19:54 PM PDT 24
Finished Jun 26 05:19:56 PM PDT 24
Peak memory 206204 kb
Host smart-0468ac3e-a45b-4477-9d48-71a1f832ce79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38846
5660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.388465660
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.3919452834
Short name T1439
Test name
Test status
Simulation time 173381256 ps
CPU time 0.8 seconds
Started Jun 26 05:19:52 PM PDT 24
Finished Jun 26 05:19:55 PM PDT 24
Peak memory 206132 kb
Host smart-bfdb4170-fa00-4adf-97c5-3e288a691bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39194
52834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.3919452834
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.3017210569
Short name T1297
Test name
Test status
Simulation time 199877168 ps
CPU time 0.83 seconds
Started Jun 26 05:19:52 PM PDT 24
Finished Jun 26 05:19:54 PM PDT 24
Peak memory 206180 kb
Host smart-9bdcd189-e416-4a6d-ba2c-a3718bcf700b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30172
10569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.3017210569
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.24159146
Short name T893
Test name
Test status
Simulation time 238105179 ps
CPU time 0.9 seconds
Started Jun 26 05:19:52 PM PDT 24
Finished Jun 26 05:19:54 PM PDT 24
Peak memory 206184 kb
Host smart-184a8010-8ce3-422b-81a5-fda12fa406b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24159
146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.24159146
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.2612592173
Short name T2545
Test name
Test status
Simulation time 6557428375 ps
CPU time 182.97 seconds
Started Jun 26 05:19:53 PM PDT 24
Finished Jun 26 05:22:57 PM PDT 24
Peak memory 206520 kb
Host smart-cc71ab37-f053-4ac6-aa97-b71e312b6cf0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2612592173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.2612592173
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.3238052981
Short name T2312
Test name
Test status
Simulation time 176642802 ps
CPU time 0.78 seconds
Started Jun 26 05:19:52 PM PDT 24
Finished Jun 26 05:19:55 PM PDT 24
Peak memory 206100 kb
Host smart-060bd1a8-ac1b-48ca-8ef5-b49465fe1baa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32380
52981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.3238052981
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.3196084685
Short name T2353
Test name
Test status
Simulation time 231885627 ps
CPU time 0.88 seconds
Started Jun 26 05:19:52 PM PDT 24
Finished Jun 26 05:19:55 PM PDT 24
Peak memory 206224 kb
Host smart-4dbb4e79-4a59-4b9b-8c02-ec67e948ad6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31960
84685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.3196084685
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.1450039201
Short name T335
Test name
Test status
Simulation time 6758816813 ps
CPU time 51.71 seconds
Started Jun 26 05:19:51 PM PDT 24
Finished Jun 26 05:20:44 PM PDT 24
Peak memory 206464 kb
Host smart-05e15d32-8d53-4371-aa37-31b48422d261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14500
39201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.1450039201
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.902804130
Short name T711
Test name
Test status
Simulation time 3536699475 ps
CPU time 4.46 seconds
Started Jun 26 05:20:00 PM PDT 24
Finished Jun 26 05:20:06 PM PDT 24
Peak memory 206200 kb
Host smart-e7a94345-a111-4f80-aed8-7d4f356eee8f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=902804130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.902804130
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.1275685117
Short name T568
Test name
Test status
Simulation time 13362874485 ps
CPU time 12.25 seconds
Started Jun 26 05:20:00 PM PDT 24
Finished Jun 26 05:20:13 PM PDT 24
Peak memory 206320 kb
Host smart-23966baf-9580-4629-a891-a0b0e3657a8f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1275685117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.1275685117
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.2655344135
Short name T2330
Test name
Test status
Simulation time 23353493982 ps
CPU time 23.39 seconds
Started Jun 26 05:20:00 PM PDT 24
Finished Jun 26 05:20:24 PM PDT 24
Peak memory 206296 kb
Host smart-f09d042f-b192-4a86-8683-a0c2e7b969fb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2655344135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.2655344135
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.2383529152
Short name T506
Test name
Test status
Simulation time 171040994 ps
CPU time 0.84 seconds
Started Jun 26 05:19:59 PM PDT 24
Finished Jun 26 05:20:01 PM PDT 24
Peak memory 206132 kb
Host smart-2fd15d37-b9a6-46e4-a38b-8edc19683abf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23835
29152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.2383529152
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.3113518236
Short name T590
Test name
Test status
Simulation time 185305685 ps
CPU time 0.86 seconds
Started Jun 26 05:20:00 PM PDT 24
Finished Jun 26 05:20:03 PM PDT 24
Peak memory 206172 kb
Host smart-e444e35b-c23e-4c67-9d4d-58cfb6c329c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31135
18236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.3113518236
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.781832776
Short name T1207
Test name
Test status
Simulation time 443075355 ps
CPU time 1.45 seconds
Started Jun 26 05:19:59 PM PDT 24
Finished Jun 26 05:20:01 PM PDT 24
Peak memory 206232 kb
Host smart-d6bb95bc-778b-4454-869f-ac622c4231ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78183
2776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.781832776
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.554273824
Short name T1371
Test name
Test status
Simulation time 1205181077 ps
CPU time 2.67 seconds
Started Jun 26 05:20:02 PM PDT 24
Finished Jun 26 05:20:06 PM PDT 24
Peak memory 206408 kb
Host smart-23f20774-63a4-44f9-a5a2-194c11f6d458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55427
3824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.554273824
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.233027834
Short name T2470
Test name
Test status
Simulation time 15706442928 ps
CPU time 34.24 seconds
Started Jun 26 05:19:59 PM PDT 24
Finished Jun 26 05:20:35 PM PDT 24
Peak memory 206580 kb
Host smart-393389db-b289-4699-9c0d-7e7bc3d54929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23302
7834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.233027834
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.911493513
Short name T742
Test name
Test status
Simulation time 434319114 ps
CPU time 1.28 seconds
Started Jun 26 05:20:02 PM PDT 24
Finished Jun 26 05:20:04 PM PDT 24
Peak memory 206404 kb
Host smart-f6e8d53e-c114-446c-bfdc-bc993b5665bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91149
3513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.911493513
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.1924621069
Short name T908
Test name
Test status
Simulation time 226158652 ps
CPU time 0.8 seconds
Started Jun 26 05:19:59 PM PDT 24
Finished Jun 26 05:20:00 PM PDT 24
Peak memory 206112 kb
Host smart-a50014e1-dbf1-4ac4-a635-bcc9acb84e39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19246
21069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.1924621069
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.1464507562
Short name T1198
Test name
Test status
Simulation time 56800529 ps
CPU time 0.71 seconds
Started Jun 26 05:20:02 PM PDT 24
Finished Jun 26 05:20:05 PM PDT 24
Peak memory 206180 kb
Host smart-2eb927f1-fa54-4565-8a7e-099b8219b6ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14645
07562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.1464507562
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.2089832114
Short name T2182
Test name
Test status
Simulation time 911719694 ps
CPU time 2.22 seconds
Started Jun 26 05:19:57 PM PDT 24
Finished Jun 26 05:20:00 PM PDT 24
Peak memory 206376 kb
Host smart-8d53d313-5f76-4e0c-83e6-7bc612256046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20898
32114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.2089832114
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.3744118054
Short name T1168
Test name
Test status
Simulation time 224937965 ps
CPU time 1.36 seconds
Started Jun 26 05:19:58 PM PDT 24
Finished Jun 26 05:20:00 PM PDT 24
Peak memory 206276 kb
Host smart-c1d1084f-32b7-421e-91bb-17514d0fba95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37441
18054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.3744118054
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.3247824759
Short name T582
Test name
Test status
Simulation time 178757223 ps
CPU time 0.91 seconds
Started Jun 26 05:20:12 PM PDT 24
Finished Jun 26 05:20:14 PM PDT 24
Peak memory 206236 kb
Host smart-c999657c-f271-48c2-a09a-9c774eabca46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32478
24759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.3247824759
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.1465340816
Short name T1148
Test name
Test status
Simulation time 145987720 ps
CPU time 0.86 seconds
Started Jun 26 05:20:06 PM PDT 24
Finished Jun 26 05:20:08 PM PDT 24
Peak memory 206224 kb
Host smart-ecfe7f60-17e0-497b-8c41-219e5d24d90b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14653
40816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.1465340816
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.910764164
Short name T1056
Test name
Test status
Simulation time 239223745 ps
CPU time 0.95 seconds
Started Jun 26 05:20:03 PM PDT 24
Finished Jun 26 05:20:06 PM PDT 24
Peak memory 206392 kb
Host smart-7d16ed54-1542-41eb-b113-3b85d4ff20fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91076
4164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.910764164
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.4168287688
Short name T261
Test name
Test status
Simulation time 6181768894 ps
CPU time 171.81 seconds
Started Jun 26 05:19:59 PM PDT 24
Finished Jun 26 05:22:52 PM PDT 24
Peak memory 206484 kb
Host smart-a61bb9dc-69c6-4193-be75-f4925f67e4c4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4168287688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.4168287688
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.1961023634
Short name T2161
Test name
Test status
Simulation time 205793308 ps
CPU time 0.88 seconds
Started Jun 26 05:19:57 PM PDT 24
Finished Jun 26 05:19:58 PM PDT 24
Peak memory 206184 kb
Host smart-a1415d86-ee18-4976-a3e8-4e5f7139c0d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19610
23634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.1961023634
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.2470316544
Short name T488
Test name
Test status
Simulation time 23317269013 ps
CPU time 30.39 seconds
Started Jun 26 05:20:00 PM PDT 24
Finished Jun 26 05:20:32 PM PDT 24
Peak memory 206324 kb
Host smart-307435c4-97c5-45b6-833b-b59bb4464329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24703
16544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.2470316544
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.2074785600
Short name T2547
Test name
Test status
Simulation time 3337806280 ps
CPU time 3.64 seconds
Started Jun 26 05:20:00 PM PDT 24
Finished Jun 26 05:20:05 PM PDT 24
Peak memory 206180 kb
Host smart-f06deae3-01f6-456a-a9e2-67a52c478bb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20747
85600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.2074785600
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.928664859
Short name T2283
Test name
Test status
Simulation time 13390467022 ps
CPU time 93.5 seconds
Started Jun 26 05:20:00 PM PDT 24
Finished Jun 26 05:21:36 PM PDT 24
Peak memory 206536 kb
Host smart-852d9b42-f176-46ed-a4c7-0afa2aeeed54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92866
4859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.928664859
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.4226088409
Short name T2413
Test name
Test status
Simulation time 7190604346 ps
CPU time 54.57 seconds
Started Jun 26 05:20:00 PM PDT 24
Finished Jun 26 05:20:56 PM PDT 24
Peak memory 206504 kb
Host smart-911b52de-c78e-4877-a883-13c1c54a7b25
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4226088409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.4226088409
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.899958389
Short name T481
Test name
Test status
Simulation time 236553650 ps
CPU time 0.87 seconds
Started Jun 26 05:20:06 PM PDT 24
Finished Jun 26 05:20:09 PM PDT 24
Peak memory 206196 kb
Host smart-45ab5b59-ea1e-46b7-9ab0-8a2932c16494
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=899958389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.899958389
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.4218360760
Short name T1402
Test name
Test status
Simulation time 207005032 ps
CPU time 0.91 seconds
Started Jun 26 05:19:59 PM PDT 24
Finished Jun 26 05:20:01 PM PDT 24
Peak memory 206212 kb
Host smart-3f0894bc-2c88-4610-8370-147fa041dbfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42183
60760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.4218360760
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.1800549215
Short name T466
Test name
Test status
Simulation time 6267499514 ps
CPU time 47.99 seconds
Started Jun 26 05:20:00 PM PDT 24
Finished Jun 26 05:20:50 PM PDT 24
Peak memory 206496 kb
Host smart-89d3d97a-476f-4ad9-b505-852ca612dbe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18005
49215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.1800549215
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.3277257341
Short name T333
Test name
Test status
Simulation time 3928629744 ps
CPU time 109.43 seconds
Started Jun 26 05:20:03 PM PDT 24
Finished Jun 26 05:21:53 PM PDT 24
Peak memory 206444 kb
Host smart-24e6f08f-e573-4394-9310-55b046c15da7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3277257341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.3277257341
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.127566760
Short name T2246
Test name
Test status
Simulation time 168833404 ps
CPU time 0.81 seconds
Started Jun 26 05:20:07 PM PDT 24
Finished Jun 26 05:20:10 PM PDT 24
Peak memory 206168 kb
Host smart-1efec3a6-5aec-434a-9ef0-f0008d665da6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=127566760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.127566760
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.3252663742
Short name T1728
Test name
Test status
Simulation time 142209959 ps
CPU time 0.82 seconds
Started Jun 26 05:20:00 PM PDT 24
Finished Jun 26 05:20:03 PM PDT 24
Peak memory 206204 kb
Host smart-60cd1925-4776-4707-bc6d-a4490a5dfd47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32526
63742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.3252663742
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.3094059728
Short name T1059
Test name
Test status
Simulation time 170823906 ps
CPU time 0.83 seconds
Started Jun 26 05:19:59 PM PDT 24
Finished Jun 26 05:20:01 PM PDT 24
Peak memory 206196 kb
Host smart-c2c30cd4-e282-42d8-b2a5-13067647f7cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30940
59728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.3094059728
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.868191240
Short name T1032
Test name
Test status
Simulation time 196222635 ps
CPU time 0.88 seconds
Started Jun 26 05:19:58 PM PDT 24
Finished Jun 26 05:20:00 PM PDT 24
Peak memory 206140 kb
Host smart-aa19f122-d64b-4c72-b8c7-614aa84fbd3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86819
1240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.868191240
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.1906918953
Short name T2498
Test name
Test status
Simulation time 173128939 ps
CPU time 0.8 seconds
Started Jun 26 05:20:00 PM PDT 24
Finished Jun 26 05:20:03 PM PDT 24
Peak memory 206208 kb
Host smart-eb773266-c085-4086-82db-f43951eb0419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19069
18953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.1906918953
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.325975468
Short name T2179
Test name
Test status
Simulation time 192815294 ps
CPU time 0.84 seconds
Started Jun 26 05:20:02 PM PDT 24
Finished Jun 26 05:20:04 PM PDT 24
Peak memory 206392 kb
Host smart-7d4e6571-772b-46f9-a4c1-0391072aa0ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32597
5468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.325975468
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.3675302971
Short name T169
Test name
Test status
Simulation time 140318759 ps
CPU time 0.74 seconds
Started Jun 26 05:20:06 PM PDT 24
Finished Jun 26 05:20:07 PM PDT 24
Peak memory 206124 kb
Host smart-ae0cda18-c411-4326-a0a3-fbf4f9dea6e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36753
02971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.3675302971
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.1295142586
Short name T2295
Test name
Test status
Simulation time 196179349 ps
CPU time 0.88 seconds
Started Jun 26 05:20:07 PM PDT 24
Finished Jun 26 05:20:10 PM PDT 24
Peak memory 206196 kb
Host smart-5ed1fca6-0e84-42c5-bb33-80629ebfdfe9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1295142586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.1295142586
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.4005509895
Short name T1902
Test name
Test status
Simulation time 148279317 ps
CPU time 0.76 seconds
Started Jun 26 05:20:06 PM PDT 24
Finished Jun 26 05:20:09 PM PDT 24
Peak memory 206164 kb
Host smart-82407614-619e-4d13-bb9f-d9f4332e5e18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40055
09895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.4005509895
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.2018963969
Short name T695
Test name
Test status
Simulation time 32758951 ps
CPU time 0.68 seconds
Started Jun 26 05:20:07 PM PDT 24
Finished Jun 26 05:20:10 PM PDT 24
Peak memory 206120 kb
Host smart-6c2e9abd-aa68-4cab-b69e-dd793e7e9f12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20189
63969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.2018963969
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.1388849115
Short name T2125
Test name
Test status
Simulation time 9443349662 ps
CPU time 20.18 seconds
Started Jun 26 05:20:07 PM PDT 24
Finished Jun 26 05:20:30 PM PDT 24
Peak memory 206536 kb
Host smart-0c4481ed-8816-442f-9c15-813d192f1f6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13888
49115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.1388849115
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.2961133606
Short name T1935
Test name
Test status
Simulation time 162624638 ps
CPU time 0.83 seconds
Started Jun 26 05:20:06 PM PDT 24
Finished Jun 26 05:20:08 PM PDT 24
Peak memory 206124 kb
Host smart-20213826-fa87-47f4-a87c-2388751998d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29611
33606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.2961133606
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.484918768
Short name T929
Test name
Test status
Simulation time 209960267 ps
CPU time 0.83 seconds
Started Jun 26 05:20:12 PM PDT 24
Finished Jun 26 05:20:14 PM PDT 24
Peak memory 206232 kb
Host smart-549aa6d3-6199-495f-b8f9-b3201d60ad1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48491
8768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.484918768
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.3047969283
Short name T1538
Test name
Test status
Simulation time 165863878 ps
CPU time 0.77 seconds
Started Jun 26 05:20:07 PM PDT 24
Finished Jun 26 05:20:10 PM PDT 24
Peak memory 206148 kb
Host smart-6b008232-3319-478e-ac55-428580b5440f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30479
69283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.3047969283
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.3375405055
Short name T562
Test name
Test status
Simulation time 160645581 ps
CPU time 0.82 seconds
Started Jun 26 05:20:06 PM PDT 24
Finished Jun 26 05:20:08 PM PDT 24
Peak memory 206128 kb
Host smart-08db6612-7261-4ecb-9476-95a3e3838151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33754
05055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.3375405055
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.2968117710
Short name T1125
Test name
Test status
Simulation time 168751947 ps
CPU time 0.84 seconds
Started Jun 26 05:20:05 PM PDT 24
Finished Jun 26 05:20:07 PM PDT 24
Peak memory 206208 kb
Host smart-6cbf4316-69ff-4070-af83-dae1e155a931
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29681
17710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.2968117710
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.444716342
Short name T1798
Test name
Test status
Simulation time 167289394 ps
CPU time 0.78 seconds
Started Jun 26 05:20:06 PM PDT 24
Finished Jun 26 05:20:09 PM PDT 24
Peak memory 206112 kb
Host smart-3489a0aa-a4b0-462d-830f-ec3c02b81594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44471
6342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.444716342
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.1878165212
Short name T1442
Test name
Test status
Simulation time 168566801 ps
CPU time 0.79 seconds
Started Jun 26 05:20:08 PM PDT 24
Finished Jun 26 05:20:11 PM PDT 24
Peak memory 206212 kb
Host smart-fdac843e-8dca-43d9-b5a3-529e7acd6db9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18781
65212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.1878165212
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.2484729776
Short name T2014
Test name
Test status
Simulation time 239327409 ps
CPU time 0.99 seconds
Started Jun 26 05:20:07 PM PDT 24
Finished Jun 26 05:20:10 PM PDT 24
Peak memory 206096 kb
Host smart-8764be0c-38e2-4e99-b8f6-28e5adb91f75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24847
29776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.2484729776
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.2478387360
Short name T1857
Test name
Test status
Simulation time 3561420881 ps
CPU time 99.39 seconds
Started Jun 26 05:20:08 PM PDT 24
Finished Jun 26 05:21:50 PM PDT 24
Peak memory 206372 kb
Host smart-a43ef3a7-f144-406d-90a0-be2d3644e795
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2478387360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.2478387360
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.866776660
Short name T614
Test name
Test status
Simulation time 187612357 ps
CPU time 0.83 seconds
Started Jun 26 05:20:06 PM PDT 24
Finished Jun 26 05:20:09 PM PDT 24
Peak memory 206176 kb
Host smart-2d3fa651-28a5-43df-8ea2-ca67ff993a37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86677
6660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.866776660
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.2451868061
Short name T1473
Test name
Test status
Simulation time 189150691 ps
CPU time 0.9 seconds
Started Jun 26 05:20:08 PM PDT 24
Finished Jun 26 05:20:11 PM PDT 24
Peak memory 206112 kb
Host smart-55c71e69-45cf-46c7-8e88-3a8e96fd3b87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24518
68061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.2451868061
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.3618097457
Short name T750
Test name
Test status
Simulation time 4521738928 ps
CPU time 45.71 seconds
Started Jun 26 05:20:08 PM PDT 24
Finished Jun 26 05:20:56 PM PDT 24
Peak memory 206500 kb
Host smart-45c5e530-8cd5-4270-a613-5c88ae96a40b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36180
97457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.3618097457
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.3268347960
Short name T785
Test name
Test status
Simulation time 3416878763 ps
CPU time 4.58 seconds
Started Jun 26 05:20:07 PM PDT 24
Finished Jun 26 05:20:14 PM PDT 24
Peak memory 206572 kb
Host smart-31b17f3e-fd09-4bb0-b820-47cd63cbbc20
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3268347960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.3268347960
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.616274819
Short name T2487
Test name
Test status
Simulation time 13331913530 ps
CPU time 12.76 seconds
Started Jun 26 05:20:07 PM PDT 24
Finished Jun 26 05:20:22 PM PDT 24
Peak memory 206584 kb
Host smart-84245b91-9476-4458-8445-e7f5c732967a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=616274819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.616274819
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.2379205225
Short name T2367
Test name
Test status
Simulation time 23326572783 ps
CPU time 27.75 seconds
Started Jun 26 05:20:07 PM PDT 24
Finished Jun 26 05:20:37 PM PDT 24
Peak memory 206328 kb
Host smart-2ea5b9e6-0540-47e8-b839-27ad6aa6fbf4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2379205225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.2379205225
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.861514272
Short name T1172
Test name
Test status
Simulation time 164947917 ps
CPU time 0.78 seconds
Started Jun 26 05:20:09 PM PDT 24
Finished Jun 26 05:20:12 PM PDT 24
Peak memory 206140 kb
Host smart-2c4999ab-b257-4ecb-98de-3df2c8202801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86151
4272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.861514272
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.1776087248
Short name T1957
Test name
Test status
Simulation time 154097110 ps
CPU time 0.75 seconds
Started Jun 26 05:20:09 PM PDT 24
Finished Jun 26 05:20:12 PM PDT 24
Peak memory 206176 kb
Host smart-e3d70005-2023-4eb3-af62-c8c2b574d4d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17760
87248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.1776087248
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.2965067972
Short name T1556
Test name
Test status
Simulation time 175612827 ps
CPU time 0.84 seconds
Started Jun 26 05:20:08 PM PDT 24
Finished Jun 26 05:20:11 PM PDT 24
Peak memory 206208 kb
Host smart-ee74fdd0-6011-45f5-aa2a-483a23eb9446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29650
67972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.2965067972
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.4120610201
Short name T1397
Test name
Test status
Simulation time 899651982 ps
CPU time 2.14 seconds
Started Jun 26 05:20:07 PM PDT 24
Finished Jun 26 05:20:10 PM PDT 24
Peak memory 206476 kb
Host smart-97c85059-5ced-4396-bfda-98eb554b3bd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41206
10201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.4120610201
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.751547065
Short name T2499
Test name
Test status
Simulation time 9407924944 ps
CPU time 17.48 seconds
Started Jun 26 05:20:09 PM PDT 24
Finished Jun 26 05:20:29 PM PDT 24
Peak memory 206504 kb
Host smart-3b45a754-ae0c-4005-a740-bb3bd68b64c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75154
7065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.751547065
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.2154311626
Short name T1659
Test name
Test status
Simulation time 395174164 ps
CPU time 1.32 seconds
Started Jun 26 05:20:09 PM PDT 24
Finished Jun 26 05:20:12 PM PDT 24
Peak memory 206128 kb
Host smart-00678344-b63b-442b-acea-87493531af53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21543
11626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.2154311626
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.3250491074
Short name T1940
Test name
Test status
Simulation time 143798309 ps
CPU time 0.73 seconds
Started Jun 26 05:20:09 PM PDT 24
Finished Jun 26 05:20:12 PM PDT 24
Peak memory 206172 kb
Host smart-5f649385-5dc1-4077-a57f-bce71959e363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32504
91074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.3250491074
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.3432678458
Short name T1220
Test name
Test status
Simulation time 38675257 ps
CPU time 0.65 seconds
Started Jun 26 05:20:06 PM PDT 24
Finished Jun 26 05:20:08 PM PDT 24
Peak memory 206232 kb
Host smart-b631ca53-d3fd-42e2-bccb-336fafbde4df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34326
78458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.3432678458
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.1245409152
Short name T2426
Test name
Test status
Simulation time 777979619 ps
CPU time 2.11 seconds
Started Jun 26 05:20:13 PM PDT 24
Finished Jun 26 05:20:15 PM PDT 24
Peak memory 206492 kb
Host smart-94f032e3-72eb-4c33-bba4-8c611d2a37ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12454
09152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.1245409152
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.89665337
Short name T829
Test name
Test status
Simulation time 160433634 ps
CPU time 1.43 seconds
Started Jun 26 05:20:06 PM PDT 24
Finished Jun 26 05:20:08 PM PDT 24
Peak memory 206404 kb
Host smart-dffa77e6-4b4c-4ffd-9b1c-dff182160d28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89665
337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.89665337
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.2997526645
Short name T18
Test name
Test status
Simulation time 230952577 ps
CPU time 0.92 seconds
Started Jun 26 05:20:17 PM PDT 24
Finished Jun 26 05:20:21 PM PDT 24
Peak memory 206216 kb
Host smart-edc23206-840d-4663-8f6b-35c34342f4fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29975
26645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.2997526645
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.3520123822
Short name T2334
Test name
Test status
Simulation time 143160770 ps
CPU time 0.78 seconds
Started Jun 26 05:20:14 PM PDT 24
Finished Jun 26 05:20:15 PM PDT 24
Peak memory 206104 kb
Host smart-4b911205-a66a-417f-9ab6-e05385f03237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35201
23822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.3520123822
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.2020761610
Short name T886
Test name
Test status
Simulation time 204040245 ps
CPU time 0.88 seconds
Started Jun 26 05:20:07 PM PDT 24
Finished Jun 26 05:20:10 PM PDT 24
Peak memory 206148 kb
Host smart-16861063-cb71-41ad-b91c-9fd2eb1ffd18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20207
61610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.2020761610
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.1771195284
Short name T26
Test name
Test status
Simulation time 9727554257 ps
CPU time 68.28 seconds
Started Jun 26 05:20:05 PM PDT 24
Finished Jun 26 05:21:15 PM PDT 24
Peak memory 206528 kb
Host smart-16d46541-82f1-4453-b0a7-2d3df8541b91
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1771195284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.1771195284
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.3666829645
Short name T360
Test name
Test status
Simulation time 193092343 ps
CPU time 0.86 seconds
Started Jun 26 05:20:06 PM PDT 24
Finished Jun 26 05:20:09 PM PDT 24
Peak memory 206396 kb
Host smart-66f91efc-9afb-4dd0-9040-94d8fa7358fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36668
29645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.3666829645
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.1191616684
Short name T1557
Test name
Test status
Simulation time 23330996161 ps
CPU time 26.64 seconds
Started Jun 26 05:20:15 PM PDT 24
Finished Jun 26 05:20:43 PM PDT 24
Peak memory 206320 kb
Host smart-da1b8912-1d7c-4614-a429-4e8fb6bf9190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11916
16684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.1191616684
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.104320280
Short name T1249
Test name
Test status
Simulation time 3263226249 ps
CPU time 4.12 seconds
Started Jun 26 05:20:15 PM PDT 24
Finished Jun 26 05:20:21 PM PDT 24
Peak memory 206280 kb
Host smart-e586d748-9839-41a9-90f8-0a1354e91ac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10432
0280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.104320280
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.522903643
Short name T2203
Test name
Test status
Simulation time 9586111399 ps
CPU time 88.56 seconds
Started Jun 26 05:20:14 PM PDT 24
Finished Jun 26 05:21:44 PM PDT 24
Peak memory 214744 kb
Host smart-dd5ec67b-febe-419b-8029-3fe6286c59a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52290
3643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.522903643
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.710613441
Short name T1547
Test name
Test status
Simulation time 3629400865 ps
CPU time 24.71 seconds
Started Jun 26 05:20:13 PM PDT 24
Finished Jun 26 05:20:38 PM PDT 24
Peak memory 206456 kb
Host smart-024b19c9-de0d-4808-8cf1-71285e3e1942
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=710613441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.710613441
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.3181129785
Short name T153
Test name
Test status
Simulation time 244731513 ps
CPU time 0.91 seconds
Started Jun 26 05:20:20 PM PDT 24
Finished Jun 26 05:20:27 PM PDT 24
Peak memory 206216 kb
Host smart-785a6fb1-11b8-47c7-94ee-375f927c248a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3181129785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.3181129785
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.1417413264
Short name T1616
Test name
Test status
Simulation time 188087613 ps
CPU time 0.87 seconds
Started Jun 26 05:20:17 PM PDT 24
Finished Jun 26 05:20:20 PM PDT 24
Peak memory 206212 kb
Host smart-10c045b1-b770-4376-a146-d92ace8492f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14174
13264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.1417413264
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.2029407349
Short name T1031
Test name
Test status
Simulation time 7466837345 ps
CPU time 54.4 seconds
Started Jun 26 05:20:16 PM PDT 24
Finished Jun 26 05:21:12 PM PDT 24
Peak memory 206436 kb
Host smart-13291e29-0a7e-4843-85b7-27601d064ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20294
07349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.2029407349
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.966261471
Short name T1185
Test name
Test status
Simulation time 3010371400 ps
CPU time 26.53 seconds
Started Jun 26 05:20:15 PM PDT 24
Finished Jun 26 05:20:43 PM PDT 24
Peak memory 206488 kb
Host smart-ed8981ec-1d53-4c9b-b29a-dbc98a26a705
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=966261471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.966261471
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.1504790013
Short name T1751
Test name
Test status
Simulation time 176595622 ps
CPU time 0.79 seconds
Started Jun 26 05:20:17 PM PDT 24
Finished Jun 26 05:20:19 PM PDT 24
Peak memory 206208 kb
Host smart-660a7fc3-5d9e-4756-a03a-c2408a94b40f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1504790013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.1504790013
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.1111558133
Short name T1910
Test name
Test status
Simulation time 168598688 ps
CPU time 0.77 seconds
Started Jun 26 05:20:16 PM PDT 24
Finished Jun 26 05:20:18 PM PDT 24
Peak memory 206180 kb
Host smart-d4fb5e72-48d0-4b9b-aec6-d9997dec6463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11115
58133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.1111558133
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.2252015125
Short name T2328
Test name
Test status
Simulation time 210854541 ps
CPU time 0.84 seconds
Started Jun 26 05:20:15 PM PDT 24
Finished Jun 26 05:20:17 PM PDT 24
Peak memory 206232 kb
Host smart-a2f7df76-99b5-43cd-a05d-79b0e29a048a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22520
15125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.2252015125
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.2405090361
Short name T1178
Test name
Test status
Simulation time 192661579 ps
CPU time 0.87 seconds
Started Jun 26 05:20:14 PM PDT 24
Finished Jun 26 05:20:16 PM PDT 24
Peak memory 206224 kb
Host smart-4adde57a-e861-4eda-80e1-474a4bc23211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24050
90361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.2405090361
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.2085241558
Short name T2407
Test name
Test status
Simulation time 157723036 ps
CPU time 0.77 seconds
Started Jun 26 05:20:18 PM PDT 24
Finished Jun 26 05:20:22 PM PDT 24
Peak memory 206444 kb
Host smart-bce75c37-0394-4c79-bb34-9aae7992a096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20852
41558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.2085241558
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.2632982688
Short name T1424
Test name
Test status
Simulation time 164628557 ps
CPU time 0.84 seconds
Started Jun 26 05:20:14 PM PDT 24
Finished Jun 26 05:20:16 PM PDT 24
Peak memory 206132 kb
Host smart-07f3326c-82e5-475d-b933-ce9f77e33f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26329
82688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.2632982688
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.2244124583
Short name T988
Test name
Test status
Simulation time 158636189 ps
CPU time 0.78 seconds
Started Jun 26 05:20:14 PM PDT 24
Finished Jun 26 05:20:16 PM PDT 24
Peak memory 206196 kb
Host smart-0a0df1c9-9b4b-4a52-96a7-c45c9d762334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22441
24583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.2244124583
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.833221249
Short name T1387
Test name
Test status
Simulation time 210103022 ps
CPU time 0.91 seconds
Started Jun 26 05:20:14 PM PDT 24
Finished Jun 26 05:20:16 PM PDT 24
Peak memory 206196 kb
Host smart-079f25ab-9973-4a6f-b802-34c8d58ae8e3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=833221249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.833221249
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.3221015388
Short name T1041
Test name
Test status
Simulation time 140586011 ps
CPU time 0.8 seconds
Started Jun 26 05:20:17 PM PDT 24
Finished Jun 26 05:20:20 PM PDT 24
Peak memory 206132 kb
Host smart-1f081d3e-0b85-42df-8855-92cd7f1d2d9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32210
15388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.3221015388
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.188116995
Short name T2414
Test name
Test status
Simulation time 45455514 ps
CPU time 0.66 seconds
Started Jun 26 05:20:21 PM PDT 24
Finished Jun 26 05:20:27 PM PDT 24
Peak memory 206192 kb
Host smart-7f8495c1-2bfe-4116-a4a4-1f556b5f53ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18811
6995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.188116995
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.1730675777
Short name T1173
Test name
Test status
Simulation time 6240083620 ps
CPU time 14.41 seconds
Started Jun 26 05:20:13 PM PDT 24
Finished Jun 26 05:20:28 PM PDT 24
Peak memory 206588 kb
Host smart-042f55aa-9eb3-4944-838d-a2ce3d621ff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17306
75777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.1730675777
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.2207691447
Short name T841
Test name
Test status
Simulation time 217369012 ps
CPU time 0.82 seconds
Started Jun 26 05:20:14 PM PDT 24
Finished Jun 26 05:20:16 PM PDT 24
Peak memory 206392 kb
Host smart-f6bc92b9-d3be-4c72-a70c-7e480155c4be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22076
91447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.2207691447
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.2520432592
Short name T2578
Test name
Test status
Simulation time 219318485 ps
CPU time 0.92 seconds
Started Jun 26 05:20:16 PM PDT 24
Finished Jun 26 05:20:18 PM PDT 24
Peak memory 206180 kb
Host smart-7bdbd082-a1b9-409e-8ac8-defe44ce42db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25204
32592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.2520432592
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.3093754985
Short name T1879
Test name
Test status
Simulation time 266201892 ps
CPU time 0.93 seconds
Started Jun 26 05:20:16 PM PDT 24
Finished Jun 26 05:20:19 PM PDT 24
Peak memory 206232 kb
Host smart-cb50ea4c-c2f9-4c49-8074-17af1bdfd7ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30937
54985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.3093754985
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.3682418845
Short name T1893
Test name
Test status
Simulation time 166255025 ps
CPU time 0.85 seconds
Started Jun 26 05:20:15 PM PDT 24
Finished Jun 26 05:20:18 PM PDT 24
Peak memory 206176 kb
Host smart-d3eefa5a-1734-4203-9676-c5881030db55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36824
18845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.3682418845
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.2719308628
Short name T400
Test name
Test status
Simulation time 187576821 ps
CPU time 0.88 seconds
Started Jun 26 05:20:17 PM PDT 24
Finished Jun 26 05:20:20 PM PDT 24
Peak memory 206444 kb
Host smart-9e502107-f0e9-479c-af27-e3e0ec654aac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27193
08628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.2719308628
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.1171773149
Short name T2351
Test name
Test status
Simulation time 163526680 ps
CPU time 0.78 seconds
Started Jun 26 05:20:21 PM PDT 24
Finished Jun 26 05:20:27 PM PDT 24
Peak memory 206192 kb
Host smart-6396a196-ace4-4f90-a53e-1d11be2782c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11717
73149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.1171773149
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.3246193758
Short name T1221
Test name
Test status
Simulation time 192943937 ps
CPU time 0.8 seconds
Started Jun 26 05:20:16 PM PDT 24
Finished Jun 26 05:20:19 PM PDT 24
Peak memory 206132 kb
Host smart-e74139b4-364d-4835-b815-18f7d956da84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32461
93758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.3246193758
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.1120706553
Short name T2037
Test name
Test status
Simulation time 242559313 ps
CPU time 0.92 seconds
Started Jun 26 05:20:17 PM PDT 24
Finished Jun 26 05:20:20 PM PDT 24
Peak memory 206444 kb
Host smart-1488b2ff-0856-4bdc-a9e2-453bf81d163a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11207
06553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.1120706553
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.2055369237
Short name T1459
Test name
Test status
Simulation time 6069038551 ps
CPU time 49.02 seconds
Started Jun 26 05:20:14 PM PDT 24
Finished Jun 26 05:21:05 PM PDT 24
Peak memory 206500 kb
Host smart-daff4d1d-2fdc-49a7-88b7-484976e556e5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2055369237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.2055369237
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.203679498
Short name T2184
Test name
Test status
Simulation time 191323075 ps
CPU time 0.84 seconds
Started Jun 26 05:20:18 PM PDT 24
Finished Jun 26 05:20:21 PM PDT 24
Peak memory 206128 kb
Host smart-185ec43f-a554-494c-a482-62e237ba1638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20367
9498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.203679498
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.2815007565
Short name T1920
Test name
Test status
Simulation time 161723137 ps
CPU time 0.83 seconds
Started Jun 26 05:20:17 PM PDT 24
Finished Jun 26 05:20:20 PM PDT 24
Peak memory 206124 kb
Host smart-a7e14df7-995a-42aa-aedb-4c36ba5d035c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28150
07565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.2815007565
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.479628190
Short name T2485
Test name
Test status
Simulation time 3272023984 ps
CPU time 23.02 seconds
Started Jun 26 05:20:15 PM PDT 24
Finished Jun 26 05:20:40 PM PDT 24
Peak memory 206496 kb
Host smart-9dfcc1ba-d623-4c0a-bb94-ff043c3146d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47962
8190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.479628190
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.3977973831
Short name T1570
Test name
Test status
Simulation time 4368861847 ps
CPU time 6.11 seconds
Started Jun 26 05:20:20 PM PDT 24
Finished Jun 26 05:20:32 PM PDT 24
Peak memory 206368 kb
Host smart-1d71e8c4-5e88-451b-b126-c051a80d1e30
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3977973831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.3977973831
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.3222742196
Short name T9
Test name
Test status
Simulation time 13392399955 ps
CPU time 13.05 seconds
Started Jun 26 05:20:21 PM PDT 24
Finished Jun 26 05:20:40 PM PDT 24
Peak memory 206348 kb
Host smart-6f09a56c-6d30-441b-9003-a2d77538f5a1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3222742196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.3222742196
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.4270453284
Short name T2144
Test name
Test status
Simulation time 23371763431 ps
CPU time 28.33 seconds
Started Jun 26 05:20:14 PM PDT 24
Finished Jun 26 05:20:44 PM PDT 24
Peak memory 206328 kb
Host smart-a720206f-d267-47dc-88bb-259af647c43a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4270453284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.4270453284
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.2376009661
Short name T2357
Test name
Test status
Simulation time 159561601 ps
CPU time 0.82 seconds
Started Jun 26 05:20:16 PM PDT 24
Finished Jun 26 05:20:19 PM PDT 24
Peak memory 206208 kb
Host smart-31543475-10c0-4987-98d9-7cbc189ee386
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23760
09661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.2376009661
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.467056358
Short name T2385
Test name
Test status
Simulation time 191958242 ps
CPU time 0.9 seconds
Started Jun 26 05:20:18 PM PDT 24
Finished Jun 26 05:20:24 PM PDT 24
Peak memory 206168 kb
Host smart-05dd0714-1f5b-4fd9-b551-7785a6ebaab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46705
6358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.467056358
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.1476642225
Short name T1054
Test name
Test status
Simulation time 605433415 ps
CPU time 1.73 seconds
Started Jun 26 05:20:20 PM PDT 24
Finished Jun 26 05:20:27 PM PDT 24
Peak memory 206428 kb
Host smart-fec9c14a-4fbc-4a4f-8745-9d7e3a046a2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14766
42225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.1476642225
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.3357432330
Short name T1243
Test name
Test status
Simulation time 1166748863 ps
CPU time 2.56 seconds
Started Jun 26 05:20:20 PM PDT 24
Finished Jun 26 05:20:27 PM PDT 24
Peak memory 206348 kb
Host smart-9f97f310-9772-4084-a0ca-dc3531389ee2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33574
32330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.3357432330
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.1816533416
Short name T1080
Test name
Test status
Simulation time 5964405733 ps
CPU time 12.69 seconds
Started Jun 26 05:20:19 PM PDT 24
Finished Jun 26 05:20:37 PM PDT 24
Peak memory 206448 kb
Host smart-b8d94e14-b290-42ca-afa6-27233d00729f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18165
33416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.1816533416
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.203832338
Short name T1384
Test name
Test status
Simulation time 469201846 ps
CPU time 1.41 seconds
Started Jun 26 05:20:20 PM PDT 24
Finished Jun 26 05:20:26 PM PDT 24
Peak memory 206196 kb
Host smart-35c9714c-ac0f-4a92-bc73-d1adadee7c53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20383
2338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.203832338
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.3554007032
Short name T539
Test name
Test status
Simulation time 144018392 ps
CPU time 0.74 seconds
Started Jun 26 05:20:21 PM PDT 24
Finished Jun 26 05:20:28 PM PDT 24
Peak memory 206188 kb
Host smart-20f57454-e45c-423f-a842-a3f2d98231e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35540
07032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.3554007032
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.3615158065
Short name T412
Test name
Test status
Simulation time 42284377 ps
CPU time 0.65 seconds
Started Jun 26 05:20:20 PM PDT 24
Finished Jun 26 05:20:25 PM PDT 24
Peak memory 206224 kb
Host smart-a81dab02-6e19-4af6-a7da-a38375064176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36151
58065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.3615158065
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.2420795120
Short name T382
Test name
Test status
Simulation time 892856897 ps
CPU time 2.09 seconds
Started Jun 26 05:20:20 PM PDT 24
Finished Jun 26 05:20:27 PM PDT 24
Peak memory 206324 kb
Host smart-606d1d00-e2c1-46f6-bc24-6898b2124e0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24207
95120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.2420795120
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.3439607781
Short name T194
Test name
Test status
Simulation time 164173626 ps
CPU time 1.64 seconds
Started Jun 26 05:20:22 PM PDT 24
Finished Jun 26 05:20:29 PM PDT 24
Peak memory 206332 kb
Host smart-b54863e8-c514-4c6f-9fab-6779b274b434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34396
07781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.3439607781
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.3420068769
Short name T1552
Test name
Test status
Simulation time 207663561 ps
CPU time 0.86 seconds
Started Jun 26 05:20:27 PM PDT 24
Finished Jun 26 05:20:33 PM PDT 24
Peak memory 206212 kb
Host smart-aaccabde-f760-4056-abef-91170f6d6eb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34200
68769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.3420068769
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.1227766770
Short name T1530
Test name
Test status
Simulation time 139995917 ps
CPU time 0.79 seconds
Started Jun 26 05:20:39 PM PDT 24
Finished Jun 26 05:20:41 PM PDT 24
Peak memory 206116 kb
Host smart-61d0ddff-6f81-4369-a363-2c9c621ad13a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12277
66770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.1227766770
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.4013708004
Short name T346
Test name
Test status
Simulation time 191235876 ps
CPU time 0.83 seconds
Started Jun 26 05:20:19 PM PDT 24
Finished Jun 26 05:20:25 PM PDT 24
Peak memory 206212 kb
Host smart-423a9361-5610-45b8-8d3d-d075925580ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40137
08004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.4013708004
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_invalid_sync.1322741205
Short name T1191
Test name
Test status
Simulation time 8857215000 ps
CPU time 66.31 seconds
Started Jun 26 05:20:21 PM PDT 24
Finished Jun 26 05:21:32 PM PDT 24
Peak memory 206560 kb
Host smart-e6819316-40f4-4610-9fa1-5e5b2e3868ce
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1322741205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_invalid_sync.1322741205
Directory /workspace/39.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.2105393642
Short name T537
Test name
Test status
Simulation time 218350050 ps
CPU time 0.91 seconds
Started Jun 26 05:20:24 PM PDT 24
Finished Jun 26 05:20:31 PM PDT 24
Peak memory 206048 kb
Host smart-5c6a7028-97af-4ffa-b8b0-debcfb2be358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21053
93642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.2105393642
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.3060990864
Short name T2548
Test name
Test status
Simulation time 23359430258 ps
CPU time 24.61 seconds
Started Jun 26 05:20:20 PM PDT 24
Finished Jun 26 05:20:50 PM PDT 24
Peak memory 206236 kb
Host smart-8ab3d890-5101-4d3c-ae7e-0a4256fe65c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30609
90864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.3060990864
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.2292282168
Short name T2108
Test name
Test status
Simulation time 3326275569 ps
CPU time 3.9 seconds
Started Jun 26 05:20:22 PM PDT 24
Finished Jun 26 05:20:32 PM PDT 24
Peak memory 206224 kb
Host smart-221700bb-9e3f-4230-90f8-e7aadef0d5e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22922
82168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.2292282168
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.3526580223
Short name T2041
Test name
Test status
Simulation time 4202190813 ps
CPU time 110.94 seconds
Started Jun 26 05:20:20 PM PDT 24
Finished Jun 26 05:22:16 PM PDT 24
Peak memory 206440 kb
Host smart-98cf8707-4f7c-4d95-84b1-a74a5f5b1f17
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3526580223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.3526580223
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.299090830
Short name T987
Test name
Test status
Simulation time 248647741 ps
CPU time 1.01 seconds
Started Jun 26 05:20:41 PM PDT 24
Finished Jun 26 05:20:43 PM PDT 24
Peak memory 206144 kb
Host smart-268177ec-92fb-4949-94ce-f535193ae552
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=299090830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.299090830
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.2597185289
Short name T1692
Test name
Test status
Simulation time 236724388 ps
CPU time 0.92 seconds
Started Jun 26 05:20:24 PM PDT 24
Finished Jun 26 05:20:31 PM PDT 24
Peak memory 206232 kb
Host smart-e600a063-3062-444c-ab99-cdfc93fd8bff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25971
85289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.2597185289
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.2735645225
Short name T1449
Test name
Test status
Simulation time 5602498086 ps
CPU time 155.47 seconds
Started Jun 26 05:20:22 PM PDT 24
Finished Jun 26 05:23:03 PM PDT 24
Peak memory 206536 kb
Host smart-2353dde9-1527-4e84-8ee2-cfc5fe86b47d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27356
45225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.2735645225
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.3682856363
Short name T2023
Test name
Test status
Simulation time 4617405565 ps
CPU time 127.33 seconds
Started Jun 26 05:20:20 PM PDT 24
Finished Jun 26 05:22:33 PM PDT 24
Peak memory 206452 kb
Host smart-c14fafff-70bb-4a57-b37d-f72b3e3fd6ae
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3682856363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.3682856363
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.3858956351
Short name T738
Test name
Test status
Simulation time 163751284 ps
CPU time 0.79 seconds
Started Jun 26 05:20:28 PM PDT 24
Finished Jun 26 05:20:34 PM PDT 24
Peak memory 206136 kb
Host smart-ed80a3d8-978b-4003-ac37-14b53e93711e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3858956351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.3858956351
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.3912228469
Short name T757
Test name
Test status
Simulation time 145441746 ps
CPU time 0.78 seconds
Started Jun 26 05:20:21 PM PDT 24
Finished Jun 26 05:20:28 PM PDT 24
Peak memory 206084 kb
Host smart-d88dba1c-d76b-413e-b57d-350463014f1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39122
28469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.3912228469
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.686785713
Short name T136
Test name
Test status
Simulation time 210927761 ps
CPU time 0.84 seconds
Started Jun 26 05:20:19 PM PDT 24
Finished Jun 26 05:20:25 PM PDT 24
Peak memory 206204 kb
Host smart-e8c674f4-b3c5-4763-a912-aa224c69eadb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68678
5713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.686785713
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.2004530704
Short name T511
Test name
Test status
Simulation time 167967202 ps
CPU time 0.76 seconds
Started Jun 26 05:20:21 PM PDT 24
Finished Jun 26 05:20:28 PM PDT 24
Peak memory 206224 kb
Host smart-095713c4-169f-41a2-b11f-60447ae2bc50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20045
30704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.2004530704
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.1302705141
Short name T1126
Test name
Test status
Simulation time 188283490 ps
CPU time 0.84 seconds
Started Jun 26 05:20:21 PM PDT 24
Finished Jun 26 05:20:27 PM PDT 24
Peak memory 206124 kb
Host smart-9c4321d6-8c2b-4f9f-b17e-a5e3831892da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13027
05141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.1302705141
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.1550242299
Short name T2080
Test name
Test status
Simulation time 207349559 ps
CPU time 0.88 seconds
Started Jun 26 05:20:20 PM PDT 24
Finished Jun 26 05:20:27 PM PDT 24
Peak memory 206124 kb
Host smart-2f1262d1-3298-4323-90cf-823469a71c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15502
42299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.1550242299
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.1843741118
Short name T862
Test name
Test status
Simulation time 152416872 ps
CPU time 0.75 seconds
Started Jun 26 05:20:27 PM PDT 24
Finished Jun 26 05:20:33 PM PDT 24
Peak memory 206204 kb
Host smart-efeda167-b36c-4a61-a626-1bf3d3595d10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18437
41118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.1843741118
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.4209980218
Short name T1017
Test name
Test status
Simulation time 274285740 ps
CPU time 0.97 seconds
Started Jun 26 05:20:22 PM PDT 24
Finished Jun 26 05:20:29 PM PDT 24
Peak memory 206216 kb
Host smart-f0ea2479-495e-4522-b552-ee8642789cfc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4209980218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.4209980218
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.3186611391
Short name T1349
Test name
Test status
Simulation time 137941783 ps
CPU time 0.77 seconds
Started Jun 26 05:20:25 PM PDT 24
Finished Jun 26 05:20:32 PM PDT 24
Peak memory 206112 kb
Host smart-9b424734-5111-4fc0-a6cc-e3f92ac80801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31866
11391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.3186611391
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.2640621390
Short name T32
Test name
Test status
Simulation time 66238079 ps
CPU time 0.72 seconds
Started Jun 26 05:20:31 PM PDT 24
Finished Jun 26 05:20:35 PM PDT 24
Peak memory 206120 kb
Host smart-fb9c8c70-856e-4e57-b6e5-77e3dad76597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26406
21390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.2640621390
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.4243292290
Short name T1247
Test name
Test status
Simulation time 15373708153 ps
CPU time 35.4 seconds
Started Jun 26 05:20:26 PM PDT 24
Finished Jun 26 05:21:07 PM PDT 24
Peak memory 206624 kb
Host smart-fb4e0e35-ff43-4576-90a3-a00e5219c946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42432
92290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.4243292290
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.3790931479
Short name T2039
Test name
Test status
Simulation time 178573154 ps
CPU time 0.81 seconds
Started Jun 26 05:20:22 PM PDT 24
Finished Jun 26 05:20:30 PM PDT 24
Peak memory 206120 kb
Host smart-d6f54eb6-3166-4f42-b50a-a73087b48551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37909
31479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.3790931479
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.3467266505
Short name T1942
Test name
Test status
Simulation time 209133094 ps
CPU time 0.86 seconds
Started Jun 26 05:20:24 PM PDT 24
Finished Jun 26 05:20:31 PM PDT 24
Peak memory 206224 kb
Host smart-ba1a4a46-8d17-424f-9631-5a25b7cace23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34672
66505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.3467266505
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.3701581233
Short name T2324
Test name
Test status
Simulation time 227318957 ps
CPU time 0.94 seconds
Started Jun 26 05:20:27 PM PDT 24
Finished Jun 26 05:20:33 PM PDT 24
Peak memory 206156 kb
Host smart-93285e56-0171-46ff-afbe-1c92679ed167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37015
81233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.3701581233
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.807252051
Short name T716
Test name
Test status
Simulation time 226268707 ps
CPU time 0.85 seconds
Started Jun 26 05:20:22 PM PDT 24
Finished Jun 26 05:20:29 PM PDT 24
Peak memory 206208 kb
Host smart-7c126817-87f9-4ee9-bdaf-c145da993552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80725
2051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.807252051
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.318371237
Short name T2187
Test name
Test status
Simulation time 155506656 ps
CPU time 0.87 seconds
Started Jun 26 05:20:26 PM PDT 24
Finished Jun 26 05:20:33 PM PDT 24
Peak memory 206212 kb
Host smart-205fb040-9a46-4729-b32e-fce10b7f3ac0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31837
1237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.318371237
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.3049804691
Short name T781
Test name
Test status
Simulation time 174979033 ps
CPU time 0.81 seconds
Started Jun 26 05:20:28 PM PDT 24
Finished Jun 26 05:20:34 PM PDT 24
Peak memory 206168 kb
Host smart-a2372dac-2f88-4a13-a072-17b6f09d36aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30498
04691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.3049804691
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.3392988154
Short name T1912
Test name
Test status
Simulation time 149882557 ps
CPU time 0.77 seconds
Started Jun 26 05:20:30 PM PDT 24
Finished Jun 26 05:20:34 PM PDT 24
Peak memory 206224 kb
Host smart-7525e61f-35be-49dd-be3e-ac6d8b9c7fe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33929
88154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.3392988154
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.2137348840
Short name T771
Test name
Test status
Simulation time 175126514 ps
CPU time 0.92 seconds
Started Jun 26 05:20:23 PM PDT 24
Finished Jun 26 05:20:30 PM PDT 24
Peak memory 206188 kb
Host smart-f837f1d5-a033-43c4-afdc-48edde37f985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21373
48840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.2137348840
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.1738095716
Short name T606
Test name
Test status
Simulation time 5661273845 ps
CPU time 51.14 seconds
Started Jun 26 05:20:24 PM PDT 24
Finished Jun 26 05:21:21 PM PDT 24
Peak memory 206424 kb
Host smart-1fceb398-da1c-4d6d-97ec-8b4df7fb3e82
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1738095716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.1738095716
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.867537158
Short name T628
Test name
Test status
Simulation time 151051213 ps
CPU time 0.81 seconds
Started Jun 26 05:20:27 PM PDT 24
Finished Jun 26 05:20:33 PM PDT 24
Peak memory 206192 kb
Host smart-a2ef1fcb-c966-481c-a36f-21ea776d9070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86753
7158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.867537158
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.3220466778
Short name T1495
Test name
Test status
Simulation time 177947734 ps
CPU time 0.84 seconds
Started Jun 26 05:20:21 PM PDT 24
Finished Jun 26 05:20:28 PM PDT 24
Peak memory 206204 kb
Host smart-8e746a34-3c9f-4def-82d6-bbbab48c4c99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32204
66778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.3220466778
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.777268102
Short name T1415
Test name
Test status
Simulation time 5674158709 ps
CPU time 54.48 seconds
Started Jun 26 05:20:26 PM PDT 24
Finished Jun 26 05:21:26 PM PDT 24
Peak memory 206588 kb
Host smart-d85835ae-0b8f-44b0-a3d1-9e7d369d8d9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77726
8102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.777268102
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.197630739
Short name T2021
Test name
Test status
Simulation time 4046826567 ps
CPU time 4.47 seconds
Started Jun 26 05:11:47 PM PDT 24
Finished Jun 26 05:11:57 PM PDT 24
Peak memory 206212 kb
Host smart-92c60a11-e0d0-4e8c-af9f-0bf1a3a9d485
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=197630739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.197630739
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.3100749652
Short name T800
Test name
Test status
Simulation time 13360637970 ps
CPU time 13.39 seconds
Started Jun 26 05:11:52 PM PDT 24
Finished Jun 26 05:12:09 PM PDT 24
Peak memory 206244 kb
Host smart-ecb6c0e6-2c74-4fe4-a4e7-8fd78a834e82
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3100749652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.3100749652
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.3025257362
Short name T1926
Test name
Test status
Simulation time 23357746339 ps
CPU time 21.92 seconds
Started Jun 26 05:11:53 PM PDT 24
Finished Jun 26 05:12:18 PM PDT 24
Peak memory 206492 kb
Host smart-0d771097-4618-4bae-9ae8-e7a09fa8bf88
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3025257362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.3025257362
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.3455085776
Short name T1650
Test name
Test status
Simulation time 147760000 ps
CPU time 0.8 seconds
Started Jun 26 05:11:54 PM PDT 24
Finished Jun 26 05:11:57 PM PDT 24
Peak memory 206144 kb
Host smart-5794c8a7-4836-4a7a-b6c4-0a1e8d5f7f44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34550
85776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.3455085776
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.3458003976
Short name T45
Test name
Test status
Simulation time 159023187 ps
CPU time 0.77 seconds
Started Jun 26 05:11:52 PM PDT 24
Finished Jun 26 05:11:56 PM PDT 24
Peak memory 206224 kb
Host smart-caa94b8e-8ef6-4d84-9c2b-c84ebd3dd91e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34580
03976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.3458003976
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.823046897
Short name T83
Test name
Test status
Simulation time 140661813 ps
CPU time 0.76 seconds
Started Jun 26 05:11:53 PM PDT 24
Finished Jun 26 05:11:57 PM PDT 24
Peak memory 206204 kb
Host smart-8b0feef5-be3a-437d-99e6-f76a4c21472d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82304
6897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.823046897
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.64747114
Short name T827
Test name
Test status
Simulation time 154957556 ps
CPU time 0.79 seconds
Started Jun 26 05:11:53 PM PDT 24
Finished Jun 26 05:11:57 PM PDT 24
Peak memory 206208 kb
Host smart-92eed3a0-fcbd-45d5-9cee-1fad245908bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64747
114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.64747114
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.216322445
Short name T2010
Test name
Test status
Simulation time 549819734 ps
CPU time 1.5 seconds
Started Jun 26 05:11:54 PM PDT 24
Finished Jun 26 05:11:58 PM PDT 24
Peak memory 206484 kb
Host smart-8a9bb64a-c730-4e31-975e-e89946a08d69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21632
2445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.216322445
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_device_address.3066067125
Short name T905
Test name
Test status
Simulation time 15302908949 ps
CPU time 25.92 seconds
Started Jun 26 05:11:52 PM PDT 24
Finished Jun 26 05:12:21 PM PDT 24
Peak memory 206452 kb
Host smart-19d57a86-da34-4377-8d2f-1ee0360fc53a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30660
67125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.3066067125
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.4113418408
Short name T1091
Test name
Test status
Simulation time 442584533 ps
CPU time 1.3 seconds
Started Jun 26 05:11:56 PM PDT 24
Finished Jun 26 05:11:59 PM PDT 24
Peak memory 206116 kb
Host smart-f4376353-a095-493f-90b7-6ae3aa4e27f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41134
18408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.4113418408
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.3820208598
Short name T1937
Test name
Test status
Simulation time 146552598 ps
CPU time 0.76 seconds
Started Jun 26 05:11:55 PM PDT 24
Finished Jun 26 05:11:58 PM PDT 24
Peak memory 206088 kb
Host smart-6f6c757c-8587-48e1-90df-847d824b4894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38202
08598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.3820208598
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.1645876726
Short name T1806
Test name
Test status
Simulation time 35394998 ps
CPU time 0.64 seconds
Started Jun 26 05:11:53 PM PDT 24
Finished Jun 26 05:11:56 PM PDT 24
Peak memory 206136 kb
Host smart-99e817e2-f807-4b7e-8ae9-fbedf01ecb1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16458
76726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.1645876726
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.680667098
Short name T1390
Test name
Test status
Simulation time 1008970713 ps
CPU time 2.26 seconds
Started Jun 26 05:11:52 PM PDT 24
Finished Jun 26 05:11:58 PM PDT 24
Peak memory 206456 kb
Host smart-ded1576b-71d0-4f34-bcc4-acdb0d2b4008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68066
7098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.680667098
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.234472912
Short name T1039
Test name
Test status
Simulation time 248306284 ps
CPU time 1.48 seconds
Started Jun 26 05:11:57 PM PDT 24
Finished Jun 26 05:12:00 PM PDT 24
Peak memory 206448 kb
Host smart-3bb3cb80-20ae-4a4d-a683-0238efe9188b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23447
2912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.234472912
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.858153099
Short name T2173
Test name
Test status
Simulation time 224230812 ps
CPU time 0.87 seconds
Started Jun 26 05:12:18 PM PDT 24
Finished Jun 26 05:12:20 PM PDT 24
Peak memory 206224 kb
Host smart-83c2d184-fda9-4b9f-bb6f-62a050d48cf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85815
3099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.858153099
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.186576425
Short name T530
Test name
Test status
Simulation time 136626051 ps
CPU time 0.78 seconds
Started Jun 26 05:12:20 PM PDT 24
Finished Jun 26 05:12:22 PM PDT 24
Peak memory 206192 kb
Host smart-964d9631-6255-430c-82ea-16ce6da2838d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18657
6425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.186576425
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.1032166419
Short name T1053
Test name
Test status
Simulation time 221170348 ps
CPU time 1 seconds
Started Jun 26 05:12:01 PM PDT 24
Finished Jun 26 05:12:03 PM PDT 24
Peak memory 206224 kb
Host smart-9784a898-c9d3-40bf-a1f5-1a43231ed57c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10321
66419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.1032166419
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_invalid_sync.2707497481
Short name T1217
Test name
Test status
Simulation time 8266911768 ps
CPU time 56.16 seconds
Started Jun 26 05:12:00 PM PDT 24
Finished Jun 26 05:12:57 PM PDT 24
Peak memory 206612 kb
Host smart-518c88e6-4e25-4d85-bbd3-5046f4132c5e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2707497481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_invalid_sync.2707497481
Directory /workspace/4.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.3748103813
Short name T1085
Test name
Test status
Simulation time 226158225 ps
CPU time 0.91 seconds
Started Jun 26 05:12:03 PM PDT 24
Finished Jun 26 05:12:04 PM PDT 24
Peak memory 206172 kb
Host smart-7b85dea2-1715-4f19-9323-81058e07eb6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37481
03813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.3748103813
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.389400911
Short name T1337
Test name
Test status
Simulation time 23338636471 ps
CPU time 27 seconds
Started Jun 26 05:12:02 PM PDT 24
Finished Jun 26 05:12:29 PM PDT 24
Peak memory 206292 kb
Host smart-6966a5f4-e38c-4e09-b017-a27971c8c43d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38940
0911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.389400911
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.3782158695
Short name T835
Test name
Test status
Simulation time 3349925879 ps
CPU time 3.83 seconds
Started Jun 26 05:12:00 PM PDT 24
Finished Jun 26 05:12:05 PM PDT 24
Peak memory 206176 kb
Host smart-76a6f7ad-5853-416e-b171-5240faa9a346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37821
58695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.3782158695
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.3434797256
Short name T2241
Test name
Test status
Simulation time 7125080004 ps
CPU time 185.06 seconds
Started Jun 26 05:12:01 PM PDT 24
Finished Jun 26 05:15:06 PM PDT 24
Peak memory 206516 kb
Host smart-0106cfd4-67ce-43cb-8234-e0889d761be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34347
97256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.3434797256
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.1947366476
Short name T482
Test name
Test status
Simulation time 5691662922 ps
CPU time 54.12 seconds
Started Jun 26 05:12:02 PM PDT 24
Finished Jun 26 05:12:57 PM PDT 24
Peak memory 206560 kb
Host smart-85227a67-beab-4917-9ea8-ecb763db3b22
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1947366476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.1947366476
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.786872487
Short name T907
Test name
Test status
Simulation time 251201409 ps
CPU time 0.9 seconds
Started Jun 26 05:12:19 PM PDT 24
Finished Jun 26 05:12:20 PM PDT 24
Peak memory 206136 kb
Host smart-843d57ed-62da-49d7-9fd2-98dd3b5b6af2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=786872487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.786872487
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.1504457314
Short name T1559
Test name
Test status
Simulation time 179319979 ps
CPU time 0.82 seconds
Started Jun 26 05:12:00 PM PDT 24
Finished Jun 26 05:12:01 PM PDT 24
Peak memory 206120 kb
Host smart-28563ed8-af51-410d-9f46-39440cca90af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15044
57314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.1504457314
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.2620082323
Short name T2060
Test name
Test status
Simulation time 5875099845 ps
CPU time 56.2 seconds
Started Jun 26 05:12:01 PM PDT 24
Finished Jun 26 05:12:58 PM PDT 24
Peak memory 206596 kb
Host smart-1cd39ad6-2e35-4b4a-b744-44eba30bfa3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26200
82323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.2620082323
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.3329613709
Short name T2460
Test name
Test status
Simulation time 6166789047 ps
CPU time 53.68 seconds
Started Jun 26 05:12:04 PM PDT 24
Finished Jun 26 05:12:58 PM PDT 24
Peak memory 206448 kb
Host smart-50f52468-984a-4530-9cce-18ee9a81b592
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3329613709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.3329613709
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.1947785863
Short name T1346
Test name
Test status
Simulation time 158563420 ps
CPU time 0.8 seconds
Started Jun 26 05:12:17 PM PDT 24
Finished Jun 26 05:12:19 PM PDT 24
Peak memory 206168 kb
Host smart-e6cbbfa3-8d59-47f1-b939-4fa3951b3f47
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1947785863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.1947785863
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.3233476663
Short name T2541
Test name
Test status
Simulation time 213258624 ps
CPU time 0.81 seconds
Started Jun 26 05:12:03 PM PDT 24
Finished Jun 26 05:12:04 PM PDT 24
Peak memory 206180 kb
Host smart-a0240e67-0ef4-431b-b645-948410e13282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32334
76663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.3233476663
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.2477921381
Short name T2190
Test name
Test status
Simulation time 185341252 ps
CPU time 0.86 seconds
Started Jun 26 05:12:00 PM PDT 24
Finished Jun 26 05:12:01 PM PDT 24
Peak memory 206232 kb
Host smart-d998a6fa-649a-4d33-99a7-d0c17ae9bb09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24779
21381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.2477921381
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.1533095847
Short name T1163
Test name
Test status
Simulation time 199526597 ps
CPU time 0.88 seconds
Started Jun 26 05:12:03 PM PDT 24
Finished Jun 26 05:12:05 PM PDT 24
Peak memory 206112 kb
Host smart-02f14d16-e3dc-47a1-a5cc-cb1fc645617f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15330
95847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.1533095847
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.3809006950
Short name T371
Test name
Test status
Simulation time 204675121 ps
CPU time 0.91 seconds
Started Jun 26 05:12:00 PM PDT 24
Finished Jun 26 05:12:02 PM PDT 24
Peak memory 206224 kb
Host smart-12270a05-0efb-41b5-a347-8a1d6194bda5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38090
06950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.3809006950
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.867733309
Short name T1777
Test name
Test status
Simulation time 148673711 ps
CPU time 0.76 seconds
Started Jun 26 05:12:11 PM PDT 24
Finished Jun 26 05:12:12 PM PDT 24
Peak memory 206216 kb
Host smart-a2e9a82f-821d-4f3a-a80f-8e4a80f68cbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86773
3309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.867733309
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.1712046647
Short name T635
Test name
Test status
Simulation time 162558996 ps
CPU time 0.79 seconds
Started Jun 26 05:12:15 PM PDT 24
Finished Jun 26 05:12:17 PM PDT 24
Peak memory 206148 kb
Host smart-f1b347f3-b45f-466c-8895-7c4d47fff51e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17120
46647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.1712046647
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.3235111082
Short name T2087
Test name
Test status
Simulation time 236910023 ps
CPU time 0.98 seconds
Started Jun 26 05:12:10 PM PDT 24
Finished Jun 26 05:12:12 PM PDT 24
Peak memory 206160 kb
Host smart-bf76ab35-b4f9-4ee1-906b-741aa17585ab
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3235111082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.3235111082
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.3214033586
Short name T41
Test name
Test status
Simulation time 196725790 ps
CPU time 0.9 seconds
Started Jun 26 05:12:09 PM PDT 24
Finished Jun 26 05:12:11 PM PDT 24
Peak memory 206200 kb
Host smart-90ab40dd-838e-46f6-ad0a-e8b2339df57c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32140
33586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.3214033586
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.3803436497
Short name T1181
Test name
Test status
Simulation time 139793547 ps
CPU time 0.81 seconds
Started Jun 26 05:12:12 PM PDT 24
Finished Jun 26 05:12:14 PM PDT 24
Peak memory 206448 kb
Host smart-19d8ccf3-de86-4527-9fc3-d6118517d014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38034
36497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.3803436497
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.1480542411
Short name T1702
Test name
Test status
Simulation time 47073359 ps
CPU time 0.69 seconds
Started Jun 26 05:12:21 PM PDT 24
Finished Jun 26 05:12:22 PM PDT 24
Peak memory 206092 kb
Host smart-de4b36b1-3ebb-476b-a9a9-18d7d279aee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14805
42411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.1480542411
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.3896991769
Short name T2551
Test name
Test status
Simulation time 17533239449 ps
CPU time 40.94 seconds
Started Jun 26 05:12:11 PM PDT 24
Finished Jun 26 05:12:53 PM PDT 24
Peak memory 206552 kb
Host smart-b21742d7-b8f0-41e7-8846-509e9812448f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38969
91769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.3896991769
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.69975604
Short name T1615
Test name
Test status
Simulation time 207621560 ps
CPU time 0.83 seconds
Started Jun 26 05:12:10 PM PDT 24
Finished Jun 26 05:12:12 PM PDT 24
Peak memory 206132 kb
Host smart-7a17c7c3-33c3-46ac-b9c9-f6d3d77eeb8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69975
604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.69975604
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.24203794
Short name T1884
Test name
Test status
Simulation time 197714310 ps
CPU time 0.92 seconds
Started Jun 26 05:12:10 PM PDT 24
Finished Jun 26 05:12:11 PM PDT 24
Peak memory 206192 kb
Host smart-bbd8f0b3-5886-4e0f-a315-4d0da2628649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24203
794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.24203794
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.4290245524
Short name T1863
Test name
Test status
Simulation time 8968847352 ps
CPU time 57.02 seconds
Started Jun 26 05:12:10 PM PDT 24
Finished Jun 26 05:13:08 PM PDT 24
Peak memory 206444 kb
Host smart-33b6aded-4bad-4b3f-a045-cc650f8977e0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4290245524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.4290245524
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.1211540114
Short name T687
Test name
Test status
Simulation time 12364882031 ps
CPU time 66.35 seconds
Started Jun 26 05:12:11 PM PDT 24
Finished Jun 26 05:13:18 PM PDT 24
Peak memory 206816 kb
Host smart-b6a95241-c07e-4cc2-a666-ea313a7fa4a4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1211540114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.1211540114
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.2072403032
Short name T1535
Test name
Test status
Simulation time 7278957984 ps
CPU time 37.69 seconds
Started Jun 26 05:12:10 PM PDT 24
Finished Jun 26 05:12:48 PM PDT 24
Peak memory 206604 kb
Host smart-868526bf-b5ac-420a-b882-c2d56bcdf839
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2072403032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.2072403032
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.443178982
Short name T1513
Test name
Test status
Simulation time 202829513 ps
CPU time 0.87 seconds
Started Jun 26 05:12:17 PM PDT 24
Finished Jun 26 05:12:18 PM PDT 24
Peak memory 206188 kb
Host smart-4dde9ae3-0560-4732-99f8-10fb5261c7a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44317
8982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.443178982
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.1655109237
Short name T2449
Test name
Test status
Simulation time 199004265 ps
CPU time 0.89 seconds
Started Jun 26 05:12:10 PM PDT 24
Finished Jun 26 05:12:12 PM PDT 24
Peak memory 206212 kb
Host smart-5e72af56-cdad-4be7-9318-073c902b7020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16551
09237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.1655109237
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.1720240924
Short name T983
Test name
Test status
Simulation time 153075751 ps
CPU time 0.83 seconds
Started Jun 26 05:12:10 PM PDT 24
Finished Jun 26 05:12:11 PM PDT 24
Peak memory 206224 kb
Host smart-b15a3d10-8506-46b8-9a88-5c94a8312344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17202
40924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.1720240924
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.3309535936
Short name T68
Test name
Test status
Simulation time 155203780 ps
CPU time 0.87 seconds
Started Jun 26 05:12:10 PM PDT 24
Finished Jun 26 05:12:12 PM PDT 24
Peak memory 206168 kb
Host smart-19adc91f-b0a4-443d-8eaf-f0c8f2bfdfa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33095
35936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.3309535936
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.2204971045
Short name T215
Test name
Test status
Simulation time 419133240 ps
CPU time 1.28 seconds
Started Jun 26 05:12:15 PM PDT 24
Finished Jun 26 05:12:17 PM PDT 24
Peak memory 225028 kb
Host smart-3f33ca7f-eba5-4c2d-ace4-bdfb1a69bccc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2204971045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.2204971045
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.574368929
Short name T2066
Test name
Test status
Simulation time 426286768 ps
CPU time 1.31 seconds
Started Jun 26 05:12:10 PM PDT 24
Finished Jun 26 05:12:13 PM PDT 24
Peak memory 206232 kb
Host smart-4a96c177-d09f-4e16-99fa-4810c19546b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57436
8929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.574368929
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.3630828539
Short name T1093
Test name
Test status
Simulation time 156619867 ps
CPU time 0.76 seconds
Started Jun 26 05:12:16 PM PDT 24
Finished Jun 26 05:12:18 PM PDT 24
Peak memory 206172 kb
Host smart-3c59b667-689d-471a-92cb-c77436ca4a9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36308
28539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.3630828539
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.366342687
Short name T775
Test name
Test status
Simulation time 172152981 ps
CPU time 0.79 seconds
Started Jun 26 05:12:16 PM PDT 24
Finished Jun 26 05:12:18 PM PDT 24
Peak memory 206116 kb
Host smart-3712c752-b342-4a00-9186-132f9d629ebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36634
2687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.366342687
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.4070487528
Short name T821
Test name
Test status
Simulation time 187534369 ps
CPU time 0.87 seconds
Started Jun 26 05:12:12 PM PDT 24
Finished Jun 26 05:12:13 PM PDT 24
Peak memory 206140 kb
Host smart-06235dbc-8678-471f-a34d-318630418d0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40704
87528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.4070487528
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.1180168304
Short name T1012
Test name
Test status
Simulation time 4229828163 ps
CPU time 33.12 seconds
Started Jun 26 05:12:09 PM PDT 24
Finished Jun 26 05:12:43 PM PDT 24
Peak memory 206432 kb
Host smart-ca2f70b3-b9f9-4fd2-b9ba-c959fda5a1f2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1180168304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.1180168304
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.1477288227
Short name T1656
Test name
Test status
Simulation time 162822688 ps
CPU time 0.77 seconds
Started Jun 26 05:12:17 PM PDT 24
Finished Jun 26 05:12:18 PM PDT 24
Peak memory 206180 kb
Host smart-6b0d99aa-d0bd-456a-9469-52b600df8b32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14772
88227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.1477288227
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.1589617395
Short name T1876
Test name
Test status
Simulation time 155445322 ps
CPU time 0.77 seconds
Started Jun 26 05:12:11 PM PDT 24
Finished Jun 26 05:12:12 PM PDT 24
Peak memory 206228 kb
Host smart-f21fe6fa-0a3e-4e66-a821-4c7030b3ac0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15896
17395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.1589617395
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.1660919911
Short name T2582
Test name
Test status
Simulation time 5073905296 ps
CPU time 138.1 seconds
Started Jun 26 05:12:16 PM PDT 24
Finished Jun 26 05:14:34 PM PDT 24
Peak memory 206420 kb
Host smart-847272f3-b39a-48db-8025-be71c8419169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16609
19911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.1660919911
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.2788057225
Short name T166
Test name
Test status
Simulation time 13270665175 ps
CPU time 281.49 seconds
Started Jun 26 05:12:15 PM PDT 24
Finished Jun 26 05:16:57 PM PDT 24
Peak memory 206592 kb
Host smart-0e4bdb5a-e1d7-4896-be71-d43ec0e8e27e
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2788057225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.2788057225
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.1640865434
Short name T1330
Test name
Test status
Simulation time 4070103850 ps
CPU time 5.81 seconds
Started Jun 26 05:20:26 PM PDT 24
Finished Jun 26 05:20:38 PM PDT 24
Peak memory 206212 kb
Host smart-471454fc-a7dd-4270-a3b9-817e3d42de88
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1640865434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.1640865434
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.1527564344
Short name T216
Test name
Test status
Simulation time 13339682829 ps
CPU time 13 seconds
Started Jun 26 05:20:29 PM PDT 24
Finished Jun 26 05:20:46 PM PDT 24
Peak memory 206424 kb
Host smart-a614d729-7674-4107-b754-47e3623508e5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1527564344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.1527564344
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.3793928571
Short name T2425
Test name
Test status
Simulation time 23365714021 ps
CPU time 22.28 seconds
Started Jun 26 05:20:31 PM PDT 24
Finished Jun 26 05:20:57 PM PDT 24
Peak memory 206320 kb
Host smart-05b75abe-6cbf-440c-87dc-c8ae180999c2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3793928571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.3793928571
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.1534521424
Short name T364
Test name
Test status
Simulation time 168274984 ps
CPU time 0.77 seconds
Started Jun 26 05:20:30 PM PDT 24
Finished Jun 26 05:20:34 PM PDT 24
Peak memory 206216 kb
Host smart-c9e29b48-6d6e-4e41-9c92-1c7300b86246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15345
21424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.1534521424
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.4100983355
Short name T1441
Test name
Test status
Simulation time 156471993 ps
CPU time 0.77 seconds
Started Jun 26 05:20:26 PM PDT 24
Finished Jun 26 05:20:32 PM PDT 24
Peak memory 206172 kb
Host smart-f2f0cded-6d47-4d46-872d-8c1ee0350b3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41009
83355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.4100983355
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.2480154435
Short name T2020
Test name
Test status
Simulation time 595352775 ps
CPU time 1.73 seconds
Started Jun 26 05:20:30 PM PDT 24
Finished Jun 26 05:20:35 PM PDT 24
Peak memory 206472 kb
Host smart-7996f0cd-8440-4c21-b9b9-c99291bbdf20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24801
54435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.2480154435
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.2419619879
Short name T2034
Test name
Test status
Simulation time 1204530623 ps
CPU time 2.69 seconds
Started Jun 26 05:20:30 PM PDT 24
Finished Jun 26 05:20:37 PM PDT 24
Peak memory 206496 kb
Host smart-55230e47-f404-43ee-81bf-9d2b09880efa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24196
19879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.2419619879
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.1125978894
Short name T850
Test name
Test status
Simulation time 9949387131 ps
CPU time 20 seconds
Started Jun 26 05:20:30 PM PDT 24
Finished Jun 26 05:20:54 PM PDT 24
Peak memory 206452 kb
Host smart-ca9a9e0e-f4c6-41e4-b068-2314f9def2b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11259
78894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.1125978894
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.1171944264
Short name T1052
Test name
Test status
Simulation time 351872454 ps
CPU time 1.15 seconds
Started Jun 26 05:20:31 PM PDT 24
Finished Jun 26 05:20:35 PM PDT 24
Peak memory 206212 kb
Host smart-2daf5438-23d8-48ea-abbf-e37ee9c6c0be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11719
44264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.1171944264
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.3878941724
Short name T1964
Test name
Test status
Simulation time 167031191 ps
CPU time 0.76 seconds
Started Jun 26 05:20:27 PM PDT 24
Finished Jun 26 05:20:33 PM PDT 24
Peak memory 206120 kb
Host smart-1a196f3f-05eb-4f29-9974-ec08942d6722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38789
41724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.3878941724
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.1495621039
Short name T383
Test name
Test status
Simulation time 61391943 ps
CPU time 0.69 seconds
Started Jun 26 05:20:27 PM PDT 24
Finished Jun 26 05:20:33 PM PDT 24
Peak memory 206220 kb
Host smart-b9115e1a-e480-46fc-9c9e-0f30296ac9cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14956
21039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.1495621039
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.2002872909
Short name T2127
Test name
Test status
Simulation time 951593667 ps
CPU time 2.03 seconds
Started Jun 26 05:20:27 PM PDT 24
Finished Jun 26 05:20:34 PM PDT 24
Peak memory 206332 kb
Host smart-cd380639-63e7-4746-b4d9-711dd0a2da5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20028
72909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.2002872909
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.1885023543
Short name T2223
Test name
Test status
Simulation time 175496269 ps
CPU time 1.73 seconds
Started Jun 26 05:20:30 PM PDT 24
Finished Jun 26 05:20:35 PM PDT 24
Peak memory 206288 kb
Host smart-9c881bdb-8e47-4d26-aaf1-77c5964ab641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18850
23543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.1885023543
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.359053307
Short name T1897
Test name
Test status
Simulation time 213465133 ps
CPU time 0.95 seconds
Started Jun 26 05:20:40 PM PDT 24
Finished Jun 26 05:20:42 PM PDT 24
Peak memory 206108 kb
Host smart-bacb7a2f-5722-4f2a-bda1-f3987da0aec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35905
3307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.359053307
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.856159683
Short name T1707
Test name
Test status
Simulation time 145610130 ps
CPU time 0.78 seconds
Started Jun 26 05:20:35 PM PDT 24
Finished Jun 26 05:20:37 PM PDT 24
Peak memory 206140 kb
Host smart-c80054c5-b53c-4df1-839b-43e3390eac56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85615
9683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.856159683
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.268711343
Short name T1635
Test name
Test status
Simulation time 197081751 ps
CPU time 0.88 seconds
Started Jun 26 05:20:31 PM PDT 24
Finished Jun 26 05:20:35 PM PDT 24
Peak memory 206136 kb
Host smart-b27fb4ed-2236-4578-a413-6e772429471e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26871
1343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.268711343
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_invalid_sync.496444008
Short name T1469
Test name
Test status
Simulation time 6540537216 ps
CPU time 184.01 seconds
Started Jun 26 05:20:40 PM PDT 24
Finished Jun 26 05:23:45 PM PDT 24
Peak memory 206432 kb
Host smart-bc2b1602-c8ae-4a4d-9a82-5a1c68a21a6d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=496444008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.496444008
Directory /workspace/40.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.2197127554
Short name T583
Test name
Test status
Simulation time 243281007 ps
CPU time 0.9 seconds
Started Jun 26 05:20:27 PM PDT 24
Finished Jun 26 05:20:33 PM PDT 24
Peak memory 206204 kb
Host smart-2fe15fcf-59ad-47e3-b131-e04d6024a467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21971
27554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.2197127554
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.560598387
Short name T1573
Test name
Test status
Simulation time 23309941765 ps
CPU time 25.08 seconds
Started Jun 26 05:20:27 PM PDT 24
Finished Jun 26 05:20:57 PM PDT 24
Peak memory 206328 kb
Host smart-1bd44451-49da-4979-b4c6-c1e899e3391a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56059
8387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.560598387
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.3129989029
Short name T1164
Test name
Test status
Simulation time 3319580313 ps
CPU time 3.73 seconds
Started Jun 26 05:20:27 PM PDT 24
Finished Jun 26 05:20:36 PM PDT 24
Peak memory 206228 kb
Host smart-1da79b1f-7907-4175-9ae3-2d42690e0107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31299
89029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.3129989029
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.3482135033
Short name T2262
Test name
Test status
Simulation time 11052519297 ps
CPU time 298.9 seconds
Started Jun 26 05:20:28 PM PDT 24
Finished Jun 26 05:25:32 PM PDT 24
Peak memory 206548 kb
Host smart-1e3e5e55-b43b-482b-83ce-9ce963229a7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34821
35033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.3482135033
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.1694551321
Short name T2149
Test name
Test status
Simulation time 7873019518 ps
CPU time 225.09 seconds
Started Jun 26 05:20:39 PM PDT 24
Finished Jun 26 05:24:25 PM PDT 24
Peak memory 206436 kb
Host smart-97e05e00-6504-41c6-92fd-e410801bde3b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1694551321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.1694551321
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.3119837844
Short name T1797
Test name
Test status
Simulation time 301030026 ps
CPU time 0.91 seconds
Started Jun 26 05:20:41 PM PDT 24
Finished Jun 26 05:20:43 PM PDT 24
Peak memory 206236 kb
Host smart-f274fca2-78e3-42c5-bd5f-9ed354d5a7d3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3119837844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.3119837844
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.3575654061
Short name T2494
Test name
Test status
Simulation time 193648174 ps
CPU time 0.86 seconds
Started Jun 26 05:20:28 PM PDT 24
Finished Jun 26 05:20:34 PM PDT 24
Peak memory 206180 kb
Host smart-65b618c3-5aef-4492-986a-c7fa2fb77f90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35756
54061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.3575654061
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.3642649680
Short name T826
Test name
Test status
Simulation time 4126436455 ps
CPU time 36.24 seconds
Started Jun 26 05:20:31 PM PDT 24
Finished Jun 26 05:21:11 PM PDT 24
Peak memory 206476 kb
Host smart-0aeefb19-5891-43ea-ba7a-654ca3bbb61b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36426
49680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.3642649680
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.3708341527
Short name T218
Test name
Test status
Simulation time 4050374720 ps
CPU time 29.25 seconds
Started Jun 26 05:20:30 PM PDT 24
Finished Jun 26 05:21:03 PM PDT 24
Peak memory 206472 kb
Host smart-64b481db-0d8a-4640-b36e-1c852d4e60c7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3708341527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.3708341527
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.2233598329
Short name T1875
Test name
Test status
Simulation time 147606418 ps
CPU time 0.82 seconds
Started Jun 26 05:20:36 PM PDT 24
Finished Jun 26 05:20:38 PM PDT 24
Peak memory 206144 kb
Host smart-3c251626-bd13-4d79-9731-1060b3a5b7b0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2233598329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.2233598329
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.660484315
Short name T1379
Test name
Test status
Simulation time 153762830 ps
CPU time 0.79 seconds
Started Jun 26 05:20:27 PM PDT 24
Finished Jun 26 05:20:33 PM PDT 24
Peak memory 206184 kb
Host smart-f395d7a7-b23f-47a5-959e-e3b7496c4739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66048
4315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.660484315
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.307700879
Short name T124
Test name
Test status
Simulation time 197912250 ps
CPU time 0.84 seconds
Started Jun 26 05:20:31 PM PDT 24
Finished Jun 26 05:20:35 PM PDT 24
Peak memory 206216 kb
Host smart-3a33acc4-970c-4153-8615-a385810b75aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30770
0879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.307700879
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.863343060
Short name T2134
Test name
Test status
Simulation time 180406374 ps
CPU time 0.82 seconds
Started Jun 26 05:20:35 PM PDT 24
Finished Jun 26 05:20:37 PM PDT 24
Peak memory 206224 kb
Host smart-7e7e7bbb-7d26-4574-b3ad-33c5562d5f33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86334
3060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.863343060
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.3133761993
Short name T442
Test name
Test status
Simulation time 216527480 ps
CPU time 0.8 seconds
Started Jun 26 05:20:36 PM PDT 24
Finished Jun 26 05:20:39 PM PDT 24
Peak memory 206180 kb
Host smart-fa0e3b3e-c8ef-4111-a7ea-cf7e771c4dc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31337
61993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.3133761993
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.1164244681
Short name T1443
Test name
Test status
Simulation time 179855658 ps
CPU time 0.85 seconds
Started Jun 26 05:20:37 PM PDT 24
Finished Jun 26 05:20:40 PM PDT 24
Peak memory 206188 kb
Host smart-824ce3ba-9ba3-4d17-a403-187935e12d71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11642
44681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.1164244681
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.2007990646
Short name T1939
Test name
Test status
Simulation time 194661130 ps
CPU time 0.85 seconds
Started Jun 26 05:20:41 PM PDT 24
Finished Jun 26 05:20:43 PM PDT 24
Peak memory 206220 kb
Host smart-caec29e5-7714-4970-85aa-902c28c96891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20079
90646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.2007990646
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.1526993331
Short name T1014
Test name
Test status
Simulation time 303284813 ps
CPU time 1.02 seconds
Started Jun 26 05:20:38 PM PDT 24
Finished Jun 26 05:20:40 PM PDT 24
Peak memory 206152 kb
Host smart-28ba49e4-6229-49af-a38d-26335c0ea05f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1526993331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.1526993331
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.2142900575
Short name T1706
Test name
Test status
Simulation time 215779045 ps
CPU time 0.8 seconds
Started Jun 26 05:20:39 PM PDT 24
Finished Jun 26 05:20:41 PM PDT 24
Peak memory 206228 kb
Host smart-3ed481b6-a90e-41b4-b10f-898da46d370a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21429
00575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.2142900575
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.2956646055
Short name T1789
Test name
Test status
Simulation time 45459763 ps
CPU time 0.66 seconds
Started Jun 26 05:20:38 PM PDT 24
Finished Jun 26 05:20:40 PM PDT 24
Peak memory 206172 kb
Host smart-3d63159e-8e32-4075-b3f9-3622835090f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29566
46055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.2956646055
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.1252220006
Short name T1510
Test name
Test status
Simulation time 11157811580 ps
CPU time 23.08 seconds
Started Jun 26 05:20:44 PM PDT 24
Finished Jun 26 05:21:10 PM PDT 24
Peak memory 206460 kb
Host smart-2e090322-e7f2-4a96-9771-5643a365eed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12522
20006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.1252220006
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.1525211821
Short name T2106
Test name
Test status
Simulation time 231154518 ps
CPU time 0.92 seconds
Started Jun 26 05:20:37 PM PDT 24
Finished Jun 26 05:20:40 PM PDT 24
Peak memory 206120 kb
Host smart-142692b9-e508-4e8f-a19f-42a819b14dd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15252
11821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.1525211821
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.2490772788
Short name T1834
Test name
Test status
Simulation time 249819995 ps
CPU time 0.89 seconds
Started Jun 26 05:20:39 PM PDT 24
Finished Jun 26 05:20:41 PM PDT 24
Peak memory 206244 kb
Host smart-6e0cd63d-03e8-484c-8881-0821e626f0c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24907
72788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.2490772788
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.2986325232
Short name T1435
Test name
Test status
Simulation time 246667483 ps
CPU time 0.92 seconds
Started Jun 26 05:20:35 PM PDT 24
Finished Jun 26 05:20:37 PM PDT 24
Peak memory 206232 kb
Host smart-3a0ce538-c73e-4da5-b7f4-078382092a2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29863
25232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.2986325232
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.3831818751
Short name T290
Test name
Test status
Simulation time 213605956 ps
CPU time 0.86 seconds
Started Jun 26 05:20:34 PM PDT 24
Finished Jun 26 05:20:37 PM PDT 24
Peak memory 206128 kb
Host smart-535a973d-d786-4edc-a16e-00d098b99496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38318
18751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.3831818751
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.870755078
Short name T845
Test name
Test status
Simulation time 188955296 ps
CPU time 0.83 seconds
Started Jun 26 05:20:37 PM PDT 24
Finished Jun 26 05:20:39 PM PDT 24
Peak memory 206188 kb
Host smart-122c339e-a586-46d7-b968-e7be4f97dcb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87075
5078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.870755078
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.2641506076
Short name T408
Test name
Test status
Simulation time 166203391 ps
CPU time 0.78 seconds
Started Jun 26 05:20:36 PM PDT 24
Finished Jun 26 05:20:37 PM PDT 24
Peak memory 206196 kb
Host smart-705dd1ec-2a5c-4dc7-b97c-2b4a933774d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26415
06076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.2641506076
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.553976638
Short name T2505
Test name
Test status
Simulation time 152670967 ps
CPU time 0.77 seconds
Started Jun 26 05:20:40 PM PDT 24
Finished Jun 26 05:20:41 PM PDT 24
Peak memory 206112 kb
Host smart-a0c4c329-aeaf-46cd-ba46-d336f9d6788a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55397
6638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.553976638
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.2947381460
Short name T377
Test name
Test status
Simulation time 220871011 ps
CPU time 0.93 seconds
Started Jun 26 05:20:37 PM PDT 24
Finished Jun 26 05:20:39 PM PDT 24
Peak memory 206228 kb
Host smart-49ee5854-8657-4262-91d3-0726c11bfc73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29473
81460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.2947381460
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.1000395689
Short name T158
Test name
Test status
Simulation time 5137325815 ps
CPU time 46.28 seconds
Started Jun 26 05:20:37 PM PDT 24
Finished Jun 26 05:21:24 PM PDT 24
Peak memory 206520 kb
Host smart-c75e5ab0-421e-4e05-9351-d1d7a3bc6d57
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1000395689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.1000395689
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.2164983055
Short name T2282
Test name
Test status
Simulation time 191296451 ps
CPU time 0.84 seconds
Started Jun 26 05:20:36 PM PDT 24
Finished Jun 26 05:20:37 PM PDT 24
Peak memory 206200 kb
Host smart-5aa053df-2ac3-4bac-bbd5-6c2cc5e63301
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21649
83055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.2164983055
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.1109317748
Short name T2175
Test name
Test status
Simulation time 188943678 ps
CPU time 0.79 seconds
Started Jun 26 05:20:36 PM PDT 24
Finished Jun 26 05:20:39 PM PDT 24
Peak memory 206184 kb
Host smart-aeacfea9-ab2f-4cbb-8a98-6ea268b9fb61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11093
17748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.1109317748
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.1028470781
Short name T2116
Test name
Test status
Simulation time 3422780601 ps
CPU time 23.51 seconds
Started Jun 26 05:20:37 PM PDT 24
Finished Jun 26 05:21:02 PM PDT 24
Peak memory 206456 kb
Host smart-883b2716-86ba-4be4-9825-f43be95ca4f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10284
70781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.1028470781
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.2262235390
Short name T1296
Test name
Test status
Simulation time 4178428538 ps
CPU time 5.32 seconds
Started Jun 26 05:20:35 PM PDT 24
Finished Jun 26 05:20:42 PM PDT 24
Peak memory 206472 kb
Host smart-eaf254e6-ce9c-4195-8f62-9c4bccc8ddb5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2262235390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.2262235390
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.3669171293
Short name T1969
Test name
Test status
Simulation time 13356461867 ps
CPU time 13.57 seconds
Started Jun 26 05:20:37 PM PDT 24
Finished Jun 26 05:20:52 PM PDT 24
Peak memory 206336 kb
Host smart-1daf0ecf-1e17-4ef2-bb0d-f77f710163e1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3669171293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.3669171293
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.2464553087
Short name T1493
Test name
Test status
Simulation time 23415735254 ps
CPU time 23.78 seconds
Started Jun 26 05:20:38 PM PDT 24
Finished Jun 26 05:21:03 PM PDT 24
Peak memory 206240 kb
Host smart-33654dfa-21a5-4ff6-8af4-59a390122190
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2464553087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.2464553087
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.1335452970
Short name T2416
Test name
Test status
Simulation time 148728324 ps
CPU time 0.84 seconds
Started Jun 26 05:20:42 PM PDT 24
Finished Jun 26 05:20:44 PM PDT 24
Peak memory 206120 kb
Host smart-2bba2c5c-78d6-4fe3-bb33-759c866fd814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13354
52970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.1335452970
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.2954964337
Short name T1026
Test name
Test status
Simulation time 176994809 ps
CPU time 0.86 seconds
Started Jun 26 05:20:41 PM PDT 24
Finished Jun 26 05:20:43 PM PDT 24
Peak memory 206088 kb
Host smart-e4c96577-da2d-4551-a1f8-4e0190dec773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29549
64337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.2954964337
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.3486216832
Short name T2114
Test name
Test status
Simulation time 431794072 ps
CPU time 1.48 seconds
Started Jun 26 05:20:35 PM PDT 24
Finished Jun 26 05:20:38 PM PDT 24
Peak memory 206176 kb
Host smart-0ab5b6db-cfbc-4ac1-98b6-07504b76db7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34862
16832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.3486216832
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_device_address.2487980391
Short name T93
Test name
Test status
Simulation time 6789346035 ps
CPU time 12.53 seconds
Started Jun 26 05:20:36 PM PDT 24
Finished Jun 26 05:20:50 PM PDT 24
Peak memory 206504 kb
Host smart-e7a30e4a-a972-43c6-b0b6-59256003849d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24879
80391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.2487980391
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.3774958428
Short name T527
Test name
Test status
Simulation time 329146532 ps
CPU time 1.3 seconds
Started Jun 26 05:20:41 PM PDT 24
Finished Jun 26 05:20:44 PM PDT 24
Peak memory 206232 kb
Host smart-0cbcbf9e-ee4c-4fcf-9a82-3cc47cb716d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37749
58428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.3774958428
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.406334302
Short name T37
Test name
Test status
Simulation time 139693081 ps
CPU time 0.75 seconds
Started Jun 26 05:20:36 PM PDT 24
Finished Jun 26 05:20:38 PM PDT 24
Peak memory 206160 kb
Host smart-8accc7c7-1cd7-4e8a-b153-3ee3f0c1da13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40633
4302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.406334302
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.1683725450
Short name T918
Test name
Test status
Simulation time 62750623 ps
CPU time 0.8 seconds
Started Jun 26 05:20:36 PM PDT 24
Finished Jun 26 05:20:38 PM PDT 24
Peak memory 206184 kb
Host smart-a97437b4-c74c-4bff-a533-ec38cd37af35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16837
25450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.1683725450
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.2350455531
Short name T336
Test name
Test status
Simulation time 967206565 ps
CPU time 2.24 seconds
Started Jun 26 05:20:38 PM PDT 24
Finished Jun 26 05:20:41 PM PDT 24
Peak memory 206360 kb
Host smart-65bacecc-16ea-479e-a701-d104b3c11a62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23504
55531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.2350455531
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.1754828497
Short name T1013
Test name
Test status
Simulation time 250826251 ps
CPU time 1.83 seconds
Started Jun 26 05:20:44 PM PDT 24
Finished Jun 26 05:20:48 PM PDT 24
Peak memory 206396 kb
Host smart-89efacff-1fe6-43c7-a26f-7bb2950e2829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17548
28497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.1754828497
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.1121510342
Short name T2242
Test name
Test status
Simulation time 248986045 ps
CPU time 0.91 seconds
Started Jun 26 05:20:53 PM PDT 24
Finished Jun 26 05:20:55 PM PDT 24
Peak memory 206212 kb
Host smart-989a7e60-e1d0-45b2-9c03-42ac90b9e786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11215
10342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.1121510342
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.1305639108
Short name T1628
Test name
Test status
Simulation time 158880192 ps
CPU time 0.82 seconds
Started Jun 26 05:20:55 PM PDT 24
Finished Jun 26 05:20:58 PM PDT 24
Peak memory 206224 kb
Host smart-601eb0f5-964c-4db1-8100-c7fa1b21d496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13056
39108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.1305639108
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.3412034449
Short name T1222
Test name
Test status
Simulation time 250456087 ps
CPU time 0.94 seconds
Started Jun 26 05:20:42 PM PDT 24
Finished Jun 26 05:20:44 PM PDT 24
Peak memory 206212 kb
Host smart-49be97d6-65a8-4238-980a-e88d9081c39a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34120
34449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.3412034449
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.3976757467
Short name T2150
Test name
Test status
Simulation time 228919152 ps
CPU time 0.9 seconds
Started Jun 26 05:20:44 PM PDT 24
Finished Jun 26 05:20:47 PM PDT 24
Peak memory 206116 kb
Host smart-019cea78-4109-4282-8d60-178b5e96bf2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39767
57467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.3976757467
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.690297022
Short name T643
Test name
Test status
Simulation time 23356952299 ps
CPU time 28.66 seconds
Started Jun 26 05:20:42 PM PDT 24
Finished Jun 26 05:21:12 PM PDT 24
Peak memory 206324 kb
Host smart-287270d1-f868-4388-8be9-ee245d3219da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69029
7022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.690297022
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.1819689959
Short name T341
Test name
Test status
Simulation time 3357140759 ps
CPU time 4.22 seconds
Started Jun 26 05:20:44 PM PDT 24
Finished Jun 26 05:20:50 PM PDT 24
Peak memory 206280 kb
Host smart-018e7b59-f109-43b2-8b87-e2fd15ff0bd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18196
89959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.1819689959
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.3696575956
Short name T1891
Test name
Test status
Simulation time 6055802920 ps
CPU time 55.12 seconds
Started Jun 26 05:20:41 PM PDT 24
Finished Jun 26 05:21:38 PM PDT 24
Peak memory 206464 kb
Host smart-c2a30ea7-8bab-42cd-b52c-2c1d322ed3cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36965
75956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.3696575956
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.1782970767
Short name T484
Test name
Test status
Simulation time 7020867081 ps
CPU time 65.43 seconds
Started Jun 26 05:20:46 PM PDT 24
Finished Jun 26 05:21:53 PM PDT 24
Peak memory 206500 kb
Host smart-9fa376d0-cfb0-49a1-8b17-bf2bd0f3fff0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1782970767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.1782970767
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.2013008095
Short name T2529
Test name
Test status
Simulation time 249584363 ps
CPU time 0.99 seconds
Started Jun 26 05:20:54 PM PDT 24
Finished Jun 26 05:20:57 PM PDT 24
Peak memory 206136 kb
Host smart-d204ae0b-0cb4-42bb-b08e-5e873d4e564d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2013008095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.2013008095
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.1170141306
Short name T1913
Test name
Test status
Simulation time 208797076 ps
CPU time 0.97 seconds
Started Jun 26 05:20:58 PM PDT 24
Finished Jun 26 05:21:04 PM PDT 24
Peak memory 206448 kb
Host smart-d1c1e277-d8be-4c67-b5a3-09fcc8a12d42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11701
41306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.1170141306
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.726357697
Short name T159
Test name
Test status
Simulation time 3644132207 ps
CPU time 101.22 seconds
Started Jun 26 05:20:55 PM PDT 24
Finished Jun 26 05:22:39 PM PDT 24
Peak memory 206420 kb
Host smart-3a1d8470-cb7f-4645-ae00-dfeb22da3500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72635
7697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.726357697
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.1161304334
Short name T1990
Test name
Test status
Simulation time 3694481433 ps
CPU time 100.96 seconds
Started Jun 26 05:20:45 PM PDT 24
Finished Jun 26 05:22:27 PM PDT 24
Peak memory 206468 kb
Host smart-756b9c26-ed99-4703-ba9a-9d9041137e65
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1161304334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.1161304334
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.1988326562
Short name T1718
Test name
Test status
Simulation time 164001534 ps
CPU time 0.8 seconds
Started Jun 26 05:20:55 PM PDT 24
Finished Jun 26 05:20:58 PM PDT 24
Peak memory 206140 kb
Host smart-0d87a76a-dc5d-4603-87e0-665ecb952129
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1988326562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.1988326562
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.1413419230
Short name T1790
Test name
Test status
Simulation time 148341017 ps
CPU time 0.76 seconds
Started Jun 26 05:20:43 PM PDT 24
Finished Jun 26 05:20:45 PM PDT 24
Peak memory 206128 kb
Host smart-54a7f9ae-80fe-41cf-ae48-e0512457ce4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14134
19230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.1413419230
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.2796767855
Short name T1987
Test name
Test status
Simulation time 176887304 ps
CPU time 0.83 seconds
Started Jun 26 05:20:55 PM PDT 24
Finished Jun 26 05:20:59 PM PDT 24
Peak memory 206176 kb
Host smart-8c97578a-d49e-4192-9885-5d3c31f30d45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27967
67855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.2796767855
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.2339229207
Short name T2275
Test name
Test status
Simulation time 192395205 ps
CPU time 0.87 seconds
Started Jun 26 05:20:53 PM PDT 24
Finished Jun 26 05:20:55 PM PDT 24
Peak memory 206116 kb
Host smart-37e59b2e-bffe-4f67-be04-cf67f0c3b69e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23392
29207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.2339229207
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.3784972307
Short name T1050
Test name
Test status
Simulation time 157985545 ps
CPU time 0.77 seconds
Started Jun 26 05:20:48 PM PDT 24
Finished Jun 26 05:20:49 PM PDT 24
Peak memory 206124 kb
Host smart-05787190-71cb-4543-b097-e1f6b161e1d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37849
72307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.3784972307
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.2194138688
Short name T1004
Test name
Test status
Simulation time 183295381 ps
CPU time 0.81 seconds
Started Jun 26 05:20:45 PM PDT 24
Finished Jun 26 05:20:48 PM PDT 24
Peak memory 206116 kb
Host smart-cbdf3d47-f98f-440c-afa1-ddea1601d16a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21941
38688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.2194138688
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.1762429547
Short name T642
Test name
Test status
Simulation time 147069289 ps
CPU time 0.89 seconds
Started Jun 26 05:20:43 PM PDT 24
Finished Jun 26 05:20:45 PM PDT 24
Peak memory 206196 kb
Host smart-71a6e052-54f5-4e90-945a-6387d82274b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17624
29547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.1762429547
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.1392892399
Short name T1572
Test name
Test status
Simulation time 224418520 ps
CPU time 0.93 seconds
Started Jun 26 05:20:44 PM PDT 24
Finished Jun 26 05:20:47 PM PDT 24
Peak memory 206228 kb
Host smart-01c15581-fd12-42c2-8ef3-6b483259064a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1392892399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.1392892399
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.257066581
Short name T496
Test name
Test status
Simulation time 154468668 ps
CPU time 0.76 seconds
Started Jun 26 05:20:43 PM PDT 24
Finished Jun 26 05:20:45 PM PDT 24
Peak memory 206180 kb
Host smart-8dd9441f-493c-4941-93f1-ef6a02f5e3f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25706
6581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.257066581
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.3542046326
Short name T1232
Test name
Test status
Simulation time 57064550 ps
CPU time 0.66 seconds
Started Jun 26 05:20:54 PM PDT 24
Finished Jun 26 05:20:56 PM PDT 24
Peak memory 206120 kb
Host smart-8476226d-88c9-4163-b821-7a7919ca9551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35420
46326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.3542046326
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.2951562784
Short name T2469
Test name
Test status
Simulation time 16328825210 ps
CPU time 37.21 seconds
Started Jun 26 05:20:42 PM PDT 24
Finished Jun 26 05:21:20 PM PDT 24
Peak memory 206452 kb
Host smart-0daa42a2-0ca1-4c3d-8e74-965e37a96c82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29515
62784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.2951562784
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.1110880411
Short name T2170
Test name
Test status
Simulation time 168741300 ps
CPU time 0.84 seconds
Started Jun 26 05:20:57 PM PDT 24
Finished Jun 26 05:21:03 PM PDT 24
Peak memory 206224 kb
Host smart-7372106f-fe81-46da-a843-614b0713eb1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11108
80411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.1110880411
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.3695979604
Short name T516
Test name
Test status
Simulation time 208318154 ps
CPU time 0.9 seconds
Started Jun 26 05:20:54 PM PDT 24
Finished Jun 26 05:20:57 PM PDT 24
Peak memory 206224 kb
Host smart-220c4fe1-1011-4cab-b8f0-72308f371e2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36959
79604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.3695979604
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.3413962096
Short name T2313
Test name
Test status
Simulation time 197338769 ps
CPU time 0.82 seconds
Started Jun 26 05:20:53 PM PDT 24
Finished Jun 26 05:20:55 PM PDT 24
Peak memory 206156 kb
Host smart-1640881c-a912-426c-aa0c-562e8f329fa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34139
62096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.3413962096
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.421419174
Short name T349
Test name
Test status
Simulation time 164436195 ps
CPU time 0.78 seconds
Started Jun 26 05:20:42 PM PDT 24
Finished Jun 26 05:20:45 PM PDT 24
Peak memory 206208 kb
Host smart-30868aed-3576-4967-bb10-813e67cc335b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42141
9174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.421419174
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.892069020
Short name T1024
Test name
Test status
Simulation time 167583381 ps
CPU time 0.77 seconds
Started Jun 26 05:20:43 PM PDT 24
Finished Jun 26 05:20:46 PM PDT 24
Peak memory 206212 kb
Host smart-d491cea9-e447-4f2b-afa6-dcd85e4d0e5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89206
9020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.892069020
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.821489963
Short name T610
Test name
Test status
Simulation time 158161079 ps
CPU time 0.77 seconds
Started Jun 26 05:20:55 PM PDT 24
Finished Jun 26 05:20:59 PM PDT 24
Peak memory 206228 kb
Host smart-0b83f1cf-ef70-4f4f-ae8c-6dd2d8268413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82148
9963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.821489963
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.2400593175
Short name T592
Test name
Test status
Simulation time 155761276 ps
CPU time 0.83 seconds
Started Jun 26 05:20:42 PM PDT 24
Finished Jun 26 05:20:44 PM PDT 24
Peak memory 206096 kb
Host smart-fd8cf3da-de8e-4ba3-8bad-65d71cf1cbb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24005
93175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.2400593175
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.1688611936
Short name T574
Test name
Test status
Simulation time 201326842 ps
CPU time 0.87 seconds
Started Jun 26 05:20:44 PM PDT 24
Finished Jun 26 05:20:47 PM PDT 24
Peak memory 206232 kb
Host smart-30ee7a38-a1a6-4e8b-822a-468bad483b64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16886
11936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.1688611936
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.3369186367
Short name T2403
Test name
Test status
Simulation time 4903389906 ps
CPU time 134.02 seconds
Started Jun 26 05:20:55 PM PDT 24
Finished Jun 26 05:23:11 PM PDT 24
Peak memory 206436 kb
Host smart-c7fab774-c66d-4fb1-b299-a0366d690f76
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3369186367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.3369186367
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.1310525622
Short name T707
Test name
Test status
Simulation time 150656051 ps
CPU time 0.8 seconds
Started Jun 26 05:20:44 PM PDT 24
Finished Jun 26 05:20:46 PM PDT 24
Peak memory 206128 kb
Host smart-75054fe6-d709-4092-a2c8-b3f47468a1f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13105
25622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.1310525622
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.2238764709
Short name T1521
Test name
Test status
Simulation time 177173141 ps
CPU time 0.78 seconds
Started Jun 26 05:20:43 PM PDT 24
Finished Jun 26 05:20:45 PM PDT 24
Peak memory 206128 kb
Host smart-7a5b40ce-0f46-4670-9e1e-8e38be01587b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22387
64709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.2238764709
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.1977097187
Short name T963
Test name
Test status
Simulation time 6043962258 ps
CPU time 42.25 seconds
Started Jun 26 05:20:59 PM PDT 24
Finished Jun 26 05:21:47 PM PDT 24
Peak memory 206504 kb
Host smart-876e0640-ad55-4851-95a8-43fd79389429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19770
97187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.1977097187
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.3693664040
Short name T830
Test name
Test status
Simulation time 4277548565 ps
CPU time 4.5 seconds
Started Jun 26 05:20:56 PM PDT 24
Finished Jun 26 05:21:04 PM PDT 24
Peak memory 206560 kb
Host smart-8b8f6afa-b046-4dd2-91f9-6604b3ec7cb7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3693664040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.3693664040
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.3190374392
Short name T2202
Test name
Test status
Simulation time 13460805612 ps
CPU time 13.24 seconds
Started Jun 26 05:20:56 PM PDT 24
Finished Jun 26 05:21:12 PM PDT 24
Peak memory 206560 kb
Host smart-6c80cd0e-4e20-47c7-98f7-88cc320043fd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3190374392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.3190374392
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.2134447888
Short name T545
Test name
Test status
Simulation time 23408803944 ps
CPU time 25.3 seconds
Started Jun 26 05:20:55 PM PDT 24
Finished Jun 26 05:21:24 PM PDT 24
Peak memory 206300 kb
Host smart-c59631db-0e50-4365-afee-49e1716a0771
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2134447888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.2134447888
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.3058401710
Short name T1177
Test name
Test status
Simulation time 140344525 ps
CPU time 0.76 seconds
Started Jun 26 05:20:55 PM PDT 24
Finished Jun 26 05:20:58 PM PDT 24
Peak memory 206180 kb
Host smart-9e37b93b-bcb2-40cb-86b1-e1ef5d95f350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30584
01710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.3058401710
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.757956788
Short name T2349
Test name
Test status
Simulation time 138276269 ps
CPU time 0.79 seconds
Started Jun 26 05:20:57 PM PDT 24
Finished Jun 26 05:21:02 PM PDT 24
Peak memory 206212 kb
Host smart-ff217f0a-c195-417e-b411-32cd30b3256c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75795
6788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.757956788
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.1362743364
Short name T2119
Test name
Test status
Simulation time 454305438 ps
CPU time 1.48 seconds
Started Jun 26 05:20:56 PM PDT 24
Finished Jun 26 05:21:01 PM PDT 24
Peak memory 206184 kb
Host smart-486b3db8-6123-4385-8849-f51aa8946124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13627
43364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.1362743364
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.3123323243
Short name T1412
Test name
Test status
Simulation time 549217982 ps
CPU time 1.43 seconds
Started Jun 26 05:20:56 PM PDT 24
Finished Jun 26 05:21:01 PM PDT 24
Peak memory 206112 kb
Host smart-8f406f09-bb16-464c-850a-0c3e6635dfc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31233
23243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.3123323243
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.2522193835
Short name T109
Test name
Test status
Simulation time 22774474021 ps
CPU time 43.33 seconds
Started Jun 26 05:20:56 PM PDT 24
Finished Jun 26 05:21:42 PM PDT 24
Peak memory 206532 kb
Host smart-a6708fe9-e4a0-43ef-b364-f5394ca7db89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25221
93835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.2522193835
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.923706720
Short name T1764
Test name
Test status
Simulation time 371179021 ps
CPU time 1.16 seconds
Started Jun 26 05:20:54 PM PDT 24
Finished Jun 26 05:20:57 PM PDT 24
Peak memory 206224 kb
Host smart-a827c982-258a-4123-b3d2-09dbc1962bfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92370
6720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.923706720
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.671820814
Short name T1361
Test name
Test status
Simulation time 133036948 ps
CPU time 0.72 seconds
Started Jun 26 05:20:56 PM PDT 24
Finished Jun 26 05:21:00 PM PDT 24
Peak memory 206112 kb
Host smart-159835bc-5fdb-48df-9066-3f69be9db79a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67182
0814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.671820814
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.2037344955
Short name T1166
Test name
Test status
Simulation time 46586866 ps
CPU time 0.69 seconds
Started Jun 26 05:20:55 PM PDT 24
Finished Jun 26 05:20:57 PM PDT 24
Peak memory 206184 kb
Host smart-3993fa8b-cb12-4b65-8821-aba8fe602353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20373
44955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.2037344955
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.2937688604
Short name T2257
Test name
Test status
Simulation time 1001332941 ps
CPU time 2.26 seconds
Started Jun 26 05:20:55 PM PDT 24
Finished Jun 26 05:21:00 PM PDT 24
Peak memory 206416 kb
Host smart-ff9761c1-779b-4b48-94eb-600f711d9edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29376
88604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.2937688604
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.805973465
Short name T1795
Test name
Test status
Simulation time 194606339 ps
CPU time 1.28 seconds
Started Jun 26 05:20:54 PM PDT 24
Finished Jun 26 05:20:58 PM PDT 24
Peak memory 206368 kb
Host smart-2e24e041-1a1d-4bc6-974d-be02182d635c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80597
3465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.805973465
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.167134850
Short name T792
Test name
Test status
Simulation time 207238422 ps
CPU time 0.85 seconds
Started Jun 26 05:21:00 PM PDT 24
Finished Jun 26 05:21:07 PM PDT 24
Peak memory 206184 kb
Host smart-e04fc021-bce4-4369-ab21-034687925fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16713
4850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.167134850
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.1267758816
Short name T1681
Test name
Test status
Simulation time 145844674 ps
CPU time 0.75 seconds
Started Jun 26 05:21:02 PM PDT 24
Finished Jun 26 05:21:09 PM PDT 24
Peak memory 206192 kb
Host smart-31e286a0-4755-46b7-9acd-f0cdb85c090d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12677
58816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.1267758816
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.3050284327
Short name T451
Test name
Test status
Simulation time 216778277 ps
CPU time 0.83 seconds
Started Jun 26 05:20:59 PM PDT 24
Finished Jun 26 05:21:06 PM PDT 24
Peak memory 206140 kb
Host smart-09272d3d-c3f8-4c4c-93ee-3390527a3fdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30502
84327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.3050284327
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.3835828363
Short name T1905
Test name
Test status
Simulation time 160938224 ps
CPU time 0.78 seconds
Started Jun 26 05:20:54 PM PDT 24
Finished Jun 26 05:20:57 PM PDT 24
Peak memory 206160 kb
Host smart-10cf05d7-2a0f-4fec-878c-b7ce2fcce887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38358
28363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.3835828363
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.2297672045
Short name T561
Test name
Test status
Simulation time 23325701024 ps
CPU time 22.93 seconds
Started Jun 26 05:20:54 PM PDT 24
Finished Jun 26 05:21:19 PM PDT 24
Peak memory 206236 kb
Host smart-3f92ff92-7f3f-45a2-832c-1cb7efafb537
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22976
72045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.2297672045
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.2304303462
Short name T334
Test name
Test status
Simulation time 3300814048 ps
CPU time 3.73 seconds
Started Jun 26 05:20:59 PM PDT 24
Finished Jun 26 05:21:09 PM PDT 24
Peak memory 206180 kb
Host smart-04ede689-3d75-4c72-b575-dce3e86efd5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23043
03462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.2304303462
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.251046645
Short name T1903
Test name
Test status
Simulation time 7571730497 ps
CPU time 68.4 seconds
Started Jun 26 05:20:58 PM PDT 24
Finished Jun 26 05:22:11 PM PDT 24
Peak memory 206572 kb
Host smart-5d15395f-99de-409c-90b8-91afd8e4861f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25104
6645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.251046645
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.1014424918
Short name T2491
Test name
Test status
Simulation time 4484755114 ps
CPU time 117.96 seconds
Started Jun 26 05:20:55 PM PDT 24
Finished Jun 26 05:22:55 PM PDT 24
Peak memory 206484 kb
Host smart-d3c57ade-067f-4036-806d-4b147af3d228
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1014424918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.1014424918
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.4028458073
Short name T389
Test name
Test status
Simulation time 253636575 ps
CPU time 0.95 seconds
Started Jun 26 05:21:03 PM PDT 24
Finished Jun 26 05:21:11 PM PDT 24
Peak memory 206144 kb
Host smart-d2604aea-3af3-4f80-b315-3c1645ab7984
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4028458073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.4028458073
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.2653020903
Short name T77
Test name
Test status
Simulation time 200221992 ps
CPU time 0.88 seconds
Started Jun 26 05:20:57 PM PDT 24
Finished Jun 26 05:21:01 PM PDT 24
Peak memory 206220 kb
Host smart-9dc9fada-26fc-4216-b012-ef288e61e1d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26530
20903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.2653020903
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.1096974219
Short name T2354
Test name
Test status
Simulation time 5820263823 ps
CPU time 168.86 seconds
Started Jun 26 05:20:56 PM PDT 24
Finished Jun 26 05:23:49 PM PDT 24
Peak memory 206464 kb
Host smart-37b8e862-1f3d-47f4-91cf-1647e08dc365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10969
74219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.1096974219
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.3765730463
Short name T510
Test name
Test status
Simulation time 6768303363 ps
CPU time 62.66 seconds
Started Jun 26 05:20:56 PM PDT 24
Finished Jun 26 05:22:02 PM PDT 24
Peak memory 206452 kb
Host smart-a84b26c7-497b-49e2-911c-4492eeac8cd7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3765730463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.3765730463
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.3681485628
Short name T1965
Test name
Test status
Simulation time 150036062 ps
CPU time 0.79 seconds
Started Jun 26 05:21:04 PM PDT 24
Finished Jun 26 05:21:11 PM PDT 24
Peak memory 206220 kb
Host smart-c86e4f4a-456e-4493-bb9e-02bb95876f9e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3681485628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.3681485628
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.2599820592
Short name T1078
Test name
Test status
Simulation time 167855667 ps
CPU time 0.8 seconds
Started Jun 26 05:20:57 PM PDT 24
Finished Jun 26 05:21:01 PM PDT 24
Peak memory 206196 kb
Host smart-1d7f2c6f-29e7-44e9-a6e0-8f76f6105628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25998
20592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.2599820592
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.4066203851
Short name T2138
Test name
Test status
Simulation time 179378744 ps
CPU time 0.8 seconds
Started Jun 26 05:20:57 PM PDT 24
Finished Jun 26 05:21:02 PM PDT 24
Peak memory 206132 kb
Host smart-b35f1c12-48b2-4464-9d47-97869c77ddb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40662
03851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.4066203851
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.1510132058
Short name T2409
Test name
Test status
Simulation time 160628061 ps
CPU time 0.82 seconds
Started Jun 26 05:20:57 PM PDT 24
Finished Jun 26 05:21:01 PM PDT 24
Peak memory 206148 kb
Host smart-b021ea66-3b39-4933-918e-4d8478a43a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15101
32058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.1510132058
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.4138694662
Short name T863
Test name
Test status
Simulation time 243263325 ps
CPU time 0.82 seconds
Started Jun 26 05:20:56 PM PDT 24
Finished Jun 26 05:21:00 PM PDT 24
Peak memory 206196 kb
Host smart-108afa9c-c8f6-484f-960c-52fd75d3d354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41386
94662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.4138694662
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.1707349886
Short name T362
Test name
Test status
Simulation time 174547175 ps
CPU time 0.82 seconds
Started Jun 26 05:20:56 PM PDT 24
Finished Jun 26 05:21:00 PM PDT 24
Peak memory 206128 kb
Host smart-cb1515e9-0eec-41c4-b490-1e610c0ca918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17073
49886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.1707349886
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.3496836909
Short name T842
Test name
Test status
Simulation time 148284502 ps
CPU time 0.77 seconds
Started Jun 26 05:21:03 PM PDT 24
Finished Jun 26 05:21:10 PM PDT 24
Peak memory 206188 kb
Host smart-6311162b-0150-4922-b219-6b950066751b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34968
36909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.3496836909
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.2281705461
Short name T515
Test name
Test status
Simulation time 230455509 ps
CPU time 0.96 seconds
Started Jun 26 05:20:57 PM PDT 24
Finished Jun 26 05:21:02 PM PDT 24
Peak memory 206232 kb
Host smart-6598d699-cfcf-48d7-9f90-35f28158e947
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2281705461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.2281705461
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.935773207
Short name T645
Test name
Test status
Simulation time 151161610 ps
CPU time 0.78 seconds
Started Jun 26 05:20:54 PM PDT 24
Finished Jun 26 05:20:56 PM PDT 24
Peak memory 206084 kb
Host smart-1088d407-61d7-4e0d-ac6c-ac8966dfa166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93577
3207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.935773207
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.465648672
Short name T2250
Test name
Test status
Simulation time 36114459 ps
CPU time 0.66 seconds
Started Jun 26 05:21:01 PM PDT 24
Finished Jun 26 05:21:08 PM PDT 24
Peak memory 206168 kb
Host smart-7ba8911a-6a66-4463-ae21-db4293ab644a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46564
8672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.465648672
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.2580322914
Short name T2512
Test name
Test status
Simulation time 14542761833 ps
CPU time 34.36 seconds
Started Jun 26 05:20:56 PM PDT 24
Finished Jun 26 05:21:33 PM PDT 24
Peak memory 206592 kb
Host smart-1b3cb859-3597-4aee-9c5b-69d4fbbd4c84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25803
22914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.2580322914
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.3957395032
Short name T1395
Test name
Test status
Simulation time 163641246 ps
CPU time 0.87 seconds
Started Jun 26 05:20:55 PM PDT 24
Finished Jun 26 05:20:59 PM PDT 24
Peak memory 206208 kb
Host smart-69409b8d-2dc4-4755-8f68-92ae39a0bbbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39573
95032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.3957395032
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.4266996770
Short name T372
Test name
Test status
Simulation time 271677635 ps
CPU time 0.91 seconds
Started Jun 26 05:20:57 PM PDT 24
Finished Jun 26 05:21:01 PM PDT 24
Peak memory 206180 kb
Host smart-ed6eb860-579c-4195-a853-08803043f683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42669
96770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.4266996770
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.20301875
Short name T1098
Test name
Test status
Simulation time 153207638 ps
CPU time 0.8 seconds
Started Jun 26 05:21:00 PM PDT 24
Finished Jun 26 05:21:08 PM PDT 24
Peak memory 206244 kb
Host smart-c8a04fdf-4c83-48a3-acfa-37e7bb1e52b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20301
875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.20301875
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.767600548
Short name T1966
Test name
Test status
Simulation time 173465498 ps
CPU time 0.81 seconds
Started Jun 26 05:20:56 PM PDT 24
Finished Jun 26 05:21:00 PM PDT 24
Peak memory 206176 kb
Host smart-e60621bf-ae95-4056-b05d-81d8de992eaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76760
0548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.767600548
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.3882441024
Short name T573
Test name
Test status
Simulation time 134076582 ps
CPU time 0.72 seconds
Started Jun 26 05:20:59 PM PDT 24
Finished Jun 26 05:21:06 PM PDT 24
Peak memory 206124 kb
Host smart-cf745b99-5cb7-415c-8baa-2d2cc4317703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38824
41024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.3882441024
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.2601181724
Short name T774
Test name
Test status
Simulation time 167645962 ps
CPU time 0.81 seconds
Started Jun 26 05:20:59 PM PDT 24
Finished Jun 26 05:21:06 PM PDT 24
Peak memory 206120 kb
Host smart-4359dc3f-16c2-4793-9281-dfc53db467db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26011
81724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.2601181724
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.865091679
Short name T363
Test name
Test status
Simulation time 168759413 ps
CPU time 0.79 seconds
Started Jun 26 05:21:03 PM PDT 24
Finished Jun 26 05:21:10 PM PDT 24
Peak memory 206244 kb
Host smart-da6c12ac-b83d-4181-bc55-cf4dc94bd3b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86509
1679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.865091679
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.3135294089
Short name T904
Test name
Test status
Simulation time 236635993 ps
CPU time 0.96 seconds
Started Jun 26 05:20:56 PM PDT 24
Finished Jun 26 05:21:00 PM PDT 24
Peak memory 206212 kb
Host smart-3d12ad77-0ef2-48c3-b3f1-89725e498dc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31352
94089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.3135294089
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.1387749992
Short name T706
Test name
Test status
Simulation time 5721991180 ps
CPU time 41.11 seconds
Started Jun 26 05:20:56 PM PDT 24
Finished Jun 26 05:21:40 PM PDT 24
Peak memory 206484 kb
Host smart-de6b4825-d8d2-43bb-bdf8-452ce4876b36
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1387749992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.1387749992
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.487872649
Short name T1009
Test name
Test status
Simulation time 189844345 ps
CPU time 0.83 seconds
Started Jun 26 05:20:58 PM PDT 24
Finished Jun 26 05:21:04 PM PDT 24
Peak memory 206200 kb
Host smart-5be321a2-7904-4c3d-839b-5274b65df463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48787
2649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.487872649
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.4044071414
Short name T1630
Test name
Test status
Simulation time 5136219006 ps
CPU time 148.31 seconds
Started Jun 26 05:21:01 PM PDT 24
Finished Jun 26 05:23:36 PM PDT 24
Peak memory 206472 kb
Host smart-38ce449f-ba77-4a34-9580-bb395ae6e995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40440
71414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.4044071414
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.977398712
Short name T2372
Test name
Test status
Simulation time 4106833131 ps
CPU time 5.69 seconds
Started Jun 26 05:21:03 PM PDT 24
Finished Jun 26 05:21:16 PM PDT 24
Peak memory 206280 kb
Host smart-543ec392-a700-49c3-a90a-67ae9961d781
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=977398712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.977398712
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.3509192994
Short name T1883
Test name
Test status
Simulation time 13350537209 ps
CPU time 13.1 seconds
Started Jun 26 05:21:08 PM PDT 24
Finished Jun 26 05:21:26 PM PDT 24
Peak memory 206464 kb
Host smart-cf7d6847-f44e-41f4-9ec4-8a79e42a4d9c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3509192994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.3509192994
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.771170910
Short name T1320
Test name
Test status
Simulation time 23413622593 ps
CPU time 24.52 seconds
Started Jun 26 05:21:03 PM PDT 24
Finished Jun 26 05:21:34 PM PDT 24
Peak memory 206536 kb
Host smart-0691f308-901e-4f11-94a9-128be650f585
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=771170910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.771170910
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.2618795346
Short name T1465
Test name
Test status
Simulation time 175937734 ps
CPU time 0.87 seconds
Started Jun 26 05:21:06 PM PDT 24
Finished Jun 26 05:21:12 PM PDT 24
Peak memory 206176 kb
Host smart-d5027c17-ac78-4567-b26e-f99e048935d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26187
95346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.2618795346
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.723723328
Short name T604
Test name
Test status
Simulation time 177096501 ps
CPU time 0.81 seconds
Started Jun 26 05:21:00 PM PDT 24
Finished Jun 26 05:21:07 PM PDT 24
Peak memory 206124 kb
Host smart-96397506-af13-4d4f-ba3d-1d9f5fa445ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72372
3328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.723723328
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.3094523506
Short name T1301
Test name
Test status
Simulation time 334748421 ps
CPU time 1.16 seconds
Started Jun 26 05:21:04 PM PDT 24
Finished Jun 26 05:21:11 PM PDT 24
Peak memory 206124 kb
Host smart-1278cbd6-c398-4b59-8772-0040c9abac5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30945
23506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.3094523506
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.507225678
Short name T2104
Test name
Test status
Simulation time 1267668343 ps
CPU time 2.77 seconds
Started Jun 26 05:21:04 PM PDT 24
Finished Jun 26 05:21:13 PM PDT 24
Peak memory 206336 kb
Host smart-a6c310cd-1831-4535-8b2f-7f55e9aec85a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50722
5678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.507225678
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.3648810215
Short name T1468
Test name
Test status
Simulation time 10818871509 ps
CPU time 20.27 seconds
Started Jun 26 05:21:04 PM PDT 24
Finished Jun 26 05:21:30 PM PDT 24
Peak memory 206508 kb
Host smart-f6875147-d73f-4c9e-bd28-d4de463dd73a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36488
10215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.3648810215
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.599188147
Short name T1343
Test name
Test status
Simulation time 318044699 ps
CPU time 1.15 seconds
Started Jun 26 05:21:03 PM PDT 24
Finished Jun 26 05:21:10 PM PDT 24
Peak memory 206184 kb
Host smart-a682aaf8-617e-40be-8c48-76b93ca02e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59918
8147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.599188147
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.369054915
Short name T410
Test name
Test status
Simulation time 164782038 ps
CPU time 0.79 seconds
Started Jun 26 05:21:05 PM PDT 24
Finished Jun 26 05:21:11 PM PDT 24
Peak memory 206116 kb
Host smart-b3a8d7d6-017f-42e8-8c83-48311a97b92c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36905
4915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.369054915
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.3406355746
Short name T1308
Test name
Test status
Simulation time 37229947 ps
CPU time 0.67 seconds
Started Jun 26 05:21:01 PM PDT 24
Finished Jun 26 05:21:08 PM PDT 24
Peak memory 206184 kb
Host smart-9a424af4-c551-4acf-a5ed-d6a6d46027e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34063
55746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.3406355746
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.3658401310
Short name T1106
Test name
Test status
Simulation time 921791663 ps
CPU time 2.14 seconds
Started Jun 26 05:21:05 PM PDT 24
Finished Jun 26 05:21:13 PM PDT 24
Peak memory 206404 kb
Host smart-0f89378f-b1d9-4611-9bbd-a51efe42110a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36584
01310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.3658401310
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.3645131699
Short name T597
Test name
Test status
Simulation time 281796789 ps
CPU time 1.95 seconds
Started Jun 26 05:21:03 PM PDT 24
Finished Jun 26 05:21:11 PM PDT 24
Peak memory 206324 kb
Host smart-43542ab6-e6d7-4be5-ba14-6a44034eec20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36451
31699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.3645131699
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.1165146263
Short name T2486
Test name
Test status
Simulation time 205768217 ps
CPU time 0.91 seconds
Started Jun 26 05:21:13 PM PDT 24
Finished Jun 26 05:21:17 PM PDT 24
Peak memory 206400 kb
Host smart-bfa82cef-b116-4e74-a013-d5b5e0afd34b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11651
46263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.1165146263
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.3444987852
Short name T2074
Test name
Test status
Simulation time 136233935 ps
CPU time 0.81 seconds
Started Jun 26 05:21:10 PM PDT 24
Finished Jun 26 05:21:14 PM PDT 24
Peak memory 205920 kb
Host smart-ad97af7d-dbaf-42c7-903f-fd3a9c97b70a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34449
87852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.3444987852
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.646571337
Short name T2396
Test name
Test status
Simulation time 216654734 ps
CPU time 0.95 seconds
Started Jun 26 05:21:03 PM PDT 24
Finished Jun 26 05:21:10 PM PDT 24
Peak memory 206184 kb
Host smart-9544d535-05b1-454f-b134-b458d0d50ccf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64657
1337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.646571337
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_invalid_sync.1531652985
Short name T1452
Test name
Test status
Simulation time 5486046789 ps
CPU time 38.34 seconds
Started Jun 26 05:21:00 PM PDT 24
Finished Jun 26 05:21:44 PM PDT 24
Peak memory 206532 kb
Host smart-33bde12b-45ed-4069-85b5-6a26b5e99356
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1531652985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.1531652985
Directory /workspace/43.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.3011765524
Short name T1859
Test name
Test status
Simulation time 217591265 ps
CPU time 0.89 seconds
Started Jun 26 05:21:03 PM PDT 24
Finished Jun 26 05:21:10 PM PDT 24
Peak memory 206184 kb
Host smart-d1320dc3-ac83-4d17-a0e8-52106aa22f03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30117
65524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.3011765524
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.3179241923
Short name T1553
Test name
Test status
Simulation time 23281601726 ps
CPU time 25.23 seconds
Started Jun 26 05:21:01 PM PDT 24
Finished Jun 26 05:21:33 PM PDT 24
Peak memory 206264 kb
Host smart-c50ed78d-dc02-45dd-a44c-9544cb0186b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31792
41923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.3179241923
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.3122477466
Short name T326
Test name
Test status
Simulation time 3346884224 ps
CPU time 4.09 seconds
Started Jun 26 05:21:00 PM PDT 24
Finished Jun 26 05:21:11 PM PDT 24
Peak memory 206280 kb
Host smart-645aaa67-b281-4ca4-80a2-3bb21c0a11ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31224
77466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.3122477466
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.3676416621
Short name T994
Test name
Test status
Simulation time 8118905676 ps
CPU time 64.16 seconds
Started Jun 26 05:21:01 PM PDT 24
Finished Jun 26 05:22:12 PM PDT 24
Peak memory 206516 kb
Host smart-bd7e98ee-b28d-44ba-862a-e5789b23f7ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36764
16621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.3676416621
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.1492332997
Short name T2318
Test name
Test status
Simulation time 8181071484 ps
CPU time 78.31 seconds
Started Jun 26 05:21:03 PM PDT 24
Finished Jun 26 05:22:28 PM PDT 24
Peak memory 206548 kb
Host smart-f11f4f26-8949-40d8-a15a-dbfdddf0bda9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1492332997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.1492332997
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.2097288633
Short name T895
Test name
Test status
Simulation time 298405192 ps
CPU time 0.95 seconds
Started Jun 26 05:21:14 PM PDT 24
Finished Jun 26 05:21:18 PM PDT 24
Peak memory 206144 kb
Host smart-49476396-66ce-4b35-9541-31e2491bf7c8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2097288633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.2097288633
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.2971491603
Short name T1885
Test name
Test status
Simulation time 209012308 ps
CPU time 0.94 seconds
Started Jun 26 05:21:03 PM PDT 24
Finished Jun 26 05:21:10 PM PDT 24
Peak memory 206448 kb
Host smart-7d4671ff-52bf-49e3-a4ad-e68c8937d83a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29714
91603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.2971491603
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.2350534882
Short name T683
Test name
Test status
Simulation time 5773037973 ps
CPU time 155.02 seconds
Started Jun 26 05:21:03 PM PDT 24
Finished Jun 26 05:23:45 PM PDT 24
Peak memory 206752 kb
Host smart-899324d5-cc4a-4bfa-b74d-485785ab183d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23505
34882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.2350534882
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.3774404717
Short name T1159
Test name
Test status
Simulation time 4788909447 ps
CPU time 133.34 seconds
Started Jun 26 05:21:03 PM PDT 24
Finished Jun 26 05:23:22 PM PDT 24
Peak memory 206440 kb
Host smart-a545a9ca-5458-4cf8-9324-17a224ac7c17
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3774404717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.3774404717
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.946858391
Short name T877
Test name
Test status
Simulation time 163924513 ps
CPU time 0.79 seconds
Started Jun 26 05:21:07 PM PDT 24
Finished Jun 26 05:21:12 PM PDT 24
Peak memory 206228 kb
Host smart-eb32789d-4d75-436a-a083-d738aa0704f0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=946858391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.946858391
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.753535462
Short name T1304
Test name
Test status
Simulation time 144143213 ps
CPU time 0.78 seconds
Started Jun 26 05:21:01 PM PDT 24
Finished Jun 26 05:21:08 PM PDT 24
Peak memory 206120 kb
Host smart-ac68ef8d-2d0e-495e-b1d0-3e8809e3ae9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75353
5462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.753535462
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.2053872113
Short name T1617
Test name
Test status
Simulation time 189119459 ps
CPU time 0.88 seconds
Started Jun 26 05:21:13 PM PDT 24
Finished Jun 26 05:21:17 PM PDT 24
Peak memory 206396 kb
Host smart-dfd43adc-2452-4ce7-a4cf-879f4513b91c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20538
72113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.2053872113
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.785222309
Short name T2504
Test name
Test status
Simulation time 193366759 ps
CPU time 0.89 seconds
Started Jun 26 05:21:08 PM PDT 24
Finished Jun 26 05:21:14 PM PDT 24
Peak memory 206184 kb
Host smart-f084f92e-fbfc-4b9b-aa33-d664214bba00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78522
2309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.785222309
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.1683748490
Short name T1566
Test name
Test status
Simulation time 174716248 ps
CPU time 0.78 seconds
Started Jun 26 05:21:06 PM PDT 24
Finished Jun 26 05:21:12 PM PDT 24
Peak memory 206120 kb
Host smart-aa729e09-72bd-4205-857a-8eaab5a3d62d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16837
48490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.1683748490
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.3437998
Short name T2474
Test name
Test status
Simulation time 149255334 ps
CPU time 0.78 seconds
Started Jun 26 05:21:09 PM PDT 24
Finished Jun 26 05:21:14 PM PDT 24
Peak memory 206212 kb
Host smart-6c1d5e7f-aec0-484c-93fb-8589d2525f17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34379
98 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.3437998
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.2701099022
Short name T801
Test name
Test status
Simulation time 213230862 ps
CPU time 0.9 seconds
Started Jun 26 05:21:06 PM PDT 24
Finished Jun 26 05:21:12 PM PDT 24
Peak memory 206228 kb
Host smart-448f0ff4-691e-4903-9424-55c3a6dce939
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2701099022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.2701099022
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.1469924416
Short name T1114
Test name
Test status
Simulation time 139490146 ps
CPU time 0.74 seconds
Started Jun 26 05:21:12 PM PDT 24
Finished Jun 26 05:21:16 PM PDT 24
Peak memory 206420 kb
Host smart-731a21a9-7461-4b8e-8149-d622b107bcc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14699
24416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.1469924416
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.2768049584
Short name T1838
Test name
Test status
Simulation time 67243391 ps
CPU time 0.66 seconds
Started Jun 26 05:21:13 PM PDT 24
Finished Jun 26 05:21:17 PM PDT 24
Peak memory 206204 kb
Host smart-7c183ae5-a02d-4661-aaf6-31635d83646e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27680
49584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.2768049584
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.1989941694
Short name T1071
Test name
Test status
Simulation time 6791730355 ps
CPU time 16.45 seconds
Started Jun 26 05:21:10 PM PDT 24
Finished Jun 26 05:21:30 PM PDT 24
Peak memory 206476 kb
Host smart-f0626c36-e1a1-48c6-8bc1-4ce8f8fdbbb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19899
41694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.1989941694
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.1534714729
Short name T2555
Test name
Test status
Simulation time 172629013 ps
CPU time 0.83 seconds
Started Jun 26 05:21:09 PM PDT 24
Finished Jun 26 05:21:14 PM PDT 24
Peak memory 206216 kb
Host smart-ff2c72dc-702c-4cb6-bbd3-486caca89ae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15347
14729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.1534714729
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.75194775
Short name T501
Test name
Test status
Simulation time 209478716 ps
CPU time 0.94 seconds
Started Jun 26 05:21:07 PM PDT 24
Finished Jun 26 05:21:12 PM PDT 24
Peak memory 206184 kb
Host smart-500904e6-428f-4cc3-b751-939857dc2de9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75194
775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.75194775
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.3132753126
Short name T2568
Test name
Test status
Simulation time 242063047 ps
CPU time 0.91 seconds
Started Jun 26 05:21:10 PM PDT 24
Finished Jun 26 05:21:14 PM PDT 24
Peak memory 206148 kb
Host smart-abe7966e-b07a-40b9-a545-c4bc7244db7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31327
53126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.3132753126
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.2304995319
Short name T2511
Test name
Test status
Simulation time 177517081 ps
CPU time 0.81 seconds
Started Jun 26 05:21:10 PM PDT 24
Finished Jun 26 05:21:14 PM PDT 24
Peak memory 205976 kb
Host smart-402382a5-cbaf-4428-b0bd-843e5e360a40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23049
95319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.2304995319
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.2247131022
Short name T388
Test name
Test status
Simulation time 145541526 ps
CPU time 0.77 seconds
Started Jun 26 05:21:08 PM PDT 24
Finished Jun 26 05:21:13 PM PDT 24
Peak memory 206228 kb
Host smart-d505aaa5-586e-430c-b9e0-a2815da5c86c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22471
31022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.2247131022
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.1563206225
Short name T470
Test name
Test status
Simulation time 155517520 ps
CPU time 0.82 seconds
Started Jun 26 05:21:09 PM PDT 24
Finished Jun 26 05:21:14 PM PDT 24
Peak memory 206204 kb
Host smart-c5798210-0eea-45be-b129-beed4a4ddd4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15632
06225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.1563206225
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.491219781
Short name T1801
Test name
Test status
Simulation time 157602319 ps
CPU time 0.76 seconds
Started Jun 26 05:21:08 PM PDT 24
Finished Jun 26 05:21:13 PM PDT 24
Peak memory 206192 kb
Host smart-184c0e64-e16f-42aa-8874-d07474cc3d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49121
9781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.491219781
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.1912037029
Short name T728
Test name
Test status
Simulation time 209335090 ps
CPU time 0.9 seconds
Started Jun 26 05:21:14 PM PDT 24
Finished Jun 26 05:21:18 PM PDT 24
Peak memory 206224 kb
Host smart-922a218a-c399-43bf-b25b-a0f2fa2ccf05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19120
37029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.1912037029
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.3645505389
Short name T2141
Test name
Test status
Simulation time 6035744097 ps
CPU time 44.79 seconds
Started Jun 26 05:21:09 PM PDT 24
Finished Jun 26 05:21:58 PM PDT 24
Peak memory 206512 kb
Host smart-81601181-4e94-43c5-a67b-690a3b915e9c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3645505389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.3645505389
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.3356866160
Short name T2231
Test name
Test status
Simulation time 202489297 ps
CPU time 0.84 seconds
Started Jun 26 05:21:06 PM PDT 24
Finished Jun 26 05:21:12 PM PDT 24
Peak memory 206084 kb
Host smart-57772a82-f06e-457f-94fc-a308203301b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33568
66160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.3356866160
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.3298982325
Short name T1300
Test name
Test status
Simulation time 177322639 ps
CPU time 0.81 seconds
Started Jun 26 05:21:08 PM PDT 24
Finished Jun 26 05:21:13 PM PDT 24
Peak memory 206172 kb
Host smart-75962f3a-eec9-499a-b3c8-ab5836dcbc2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32989
82325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.3298982325
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.2584075876
Short name T2135
Test name
Test status
Simulation time 4769362028 ps
CPU time 43.56 seconds
Started Jun 26 05:21:12 PM PDT 24
Finished Jun 26 05:21:58 PM PDT 24
Peak memory 206492 kb
Host smart-0c30934e-7d0c-4df2-8fb3-0ed63a301591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25840
75876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.2584075876
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.2426907305
Short name T1007
Test name
Test status
Simulation time 4405645195 ps
CPU time 5.06 seconds
Started Jun 26 05:21:12 PM PDT 24
Finished Jun 26 05:21:20 PM PDT 24
Peak memory 206516 kb
Host smart-01aeb11c-5536-4e2f-84e0-a857eb146011
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2426907305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.2426907305
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.434901063
Short name T2500
Test name
Test status
Simulation time 13364427950 ps
CPU time 11.77 seconds
Started Jun 26 05:21:10 PM PDT 24
Finished Jun 26 05:21:25 PM PDT 24
Peak memory 206512 kb
Host smart-90582fc6-90b3-4a3e-9002-7665cc405efa
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=434901063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.434901063
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.2676164643
Short name T851
Test name
Test status
Simulation time 23435152937 ps
CPU time 21.27 seconds
Started Jun 26 05:21:15 PM PDT 24
Finished Jun 26 05:21:38 PM PDT 24
Peak memory 206428 kb
Host smart-2a197b67-c6d4-4ed9-892b-3da8c331e2a0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2676164643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.2676164643
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.1072565163
Short name T725
Test name
Test status
Simulation time 187273662 ps
CPU time 0.79 seconds
Started Jun 26 05:21:08 PM PDT 24
Finished Jun 26 05:21:13 PM PDT 24
Peak memory 206220 kb
Host smart-b66e4989-0437-4145-9c8a-959edbf757d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10725
65163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.1072565163
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.533874106
Short name T57
Test name
Test status
Simulation time 159979149 ps
CPU time 0.82 seconds
Started Jun 26 05:21:18 PM PDT 24
Finished Jun 26 05:21:22 PM PDT 24
Peak memory 206204 kb
Host smart-78cca65f-0bea-43bb-b6f1-f66cd7ce4e50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53387
4106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.533874106
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.2200683889
Short name T2219
Test name
Test status
Simulation time 344001351 ps
CPU time 1.22 seconds
Started Jun 26 05:21:09 PM PDT 24
Finished Jun 26 05:21:14 PM PDT 24
Peak memory 206208 kb
Host smart-b07e3f36-2cee-4d91-8051-e831b980d85d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22006
83889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.2200683889
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.3192084212
Short name T183
Test name
Test status
Simulation time 1146299143 ps
CPU time 2.57 seconds
Started Jun 26 05:21:10 PM PDT 24
Finished Jun 26 05:21:16 PM PDT 24
Peak memory 206316 kb
Host smart-653223e7-c345-477e-bd4f-b90e86a70566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31920
84212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.3192084212
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.3039192838
Short name T95
Test name
Test status
Simulation time 12146810067 ps
CPU time 22.49 seconds
Started Jun 26 05:21:08 PM PDT 24
Finished Jun 26 05:21:35 PM PDT 24
Peak memory 206436 kb
Host smart-24fa50d9-061b-4c5a-8ecb-acb5cbd03529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30391
92838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.3039192838
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.4120397430
Short name T2428
Test name
Test status
Simulation time 317530314 ps
CPU time 1.21 seconds
Started Jun 26 05:21:13 PM PDT 24
Finished Jun 26 05:21:17 PM PDT 24
Peak memory 206400 kb
Host smart-eb4641b6-0fbb-4d4e-afb7-38300306e187
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41203
97430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.4120397430
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.1305309567
Short name T423
Test name
Test status
Simulation time 152817763 ps
CPU time 0.79 seconds
Started Jun 26 05:21:08 PM PDT 24
Finished Jun 26 05:21:13 PM PDT 24
Peak memory 206188 kb
Host smart-6f7376e4-9f65-4103-aad1-24a831ef9edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13053
09567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.1305309567
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.1621327784
Short name T1103
Test name
Test status
Simulation time 35775944 ps
CPU time 0.67 seconds
Started Jun 26 05:21:14 PM PDT 24
Finished Jun 26 05:21:18 PM PDT 24
Peak memory 206064 kb
Host smart-09ac7dcb-56f5-46fb-a431-8178746371bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16213
27784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.1621327784
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.3044544555
Short name T340
Test name
Test status
Simulation time 1010780676 ps
CPU time 2.45 seconds
Started Jun 26 05:21:07 PM PDT 24
Finished Jun 26 05:21:14 PM PDT 24
Peak memory 206372 kb
Host smart-3179928f-c6f5-47f5-9844-17bc39b70b4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30445
44555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.3044544555
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.1542262983
Short name T1
Test name
Test status
Simulation time 186009263 ps
CPU time 2.11 seconds
Started Jun 26 05:21:14 PM PDT 24
Finished Jun 26 05:21:19 PM PDT 24
Peak memory 206176 kb
Host smart-dc6c13b7-3ae9-4347-b4f0-328b392b6cf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15422
62983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.1542262983
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.1679568288
Short name T2188
Test name
Test status
Simulation time 203812012 ps
CPU time 0.88 seconds
Started Jun 26 05:21:17 PM PDT 24
Finished Jun 26 05:21:21 PM PDT 24
Peak memory 206224 kb
Host smart-5ae82de6-87f3-4065-ab58-40cf50c29a19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16795
68288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.1679568288
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.2441805247
Short name T1414
Test name
Test status
Simulation time 141606585 ps
CPU time 0.75 seconds
Started Jun 26 05:21:16 PM PDT 24
Finished Jun 26 05:21:20 PM PDT 24
Peak memory 206224 kb
Host smart-1f395be2-7068-4462-9d6e-3dea1e993b13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24418
05247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.2441805247
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.2920349825
Short name T2401
Test name
Test status
Simulation time 229587684 ps
CPU time 0.87 seconds
Started Jun 26 05:21:15 PM PDT 24
Finished Jun 26 05:21:18 PM PDT 24
Peak memory 206140 kb
Host smart-ef947dfb-42e0-4b44-899f-57bc759449b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29203
49825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.2920349825
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.288410581
Short name T1280
Test name
Test status
Simulation time 232697836 ps
CPU time 0.85 seconds
Started Jun 26 05:21:17 PM PDT 24
Finished Jun 26 05:21:21 PM PDT 24
Peak memory 206228 kb
Host smart-b9a1c18b-73a4-46b1-97d6-9ba6a36fd99e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28841
0581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.288410581
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.3962106597
Short name T2524
Test name
Test status
Simulation time 23292489247 ps
CPU time 23.54 seconds
Started Jun 26 05:21:15 PM PDT 24
Finished Jun 26 05:21:41 PM PDT 24
Peak memory 206320 kb
Host smart-e2e2ee18-9725-42e8-aae7-2ce1dc1c455b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39621
06597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.3962106597
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.3465120069
Short name T2208
Test name
Test status
Simulation time 3301446097 ps
CPU time 4.25 seconds
Started Jun 26 05:21:16 PM PDT 24
Finished Jun 26 05:21:23 PM PDT 24
Peak memory 206224 kb
Host smart-9173e52a-0140-4152-9dbf-307654e91822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34651
20069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.3465120069
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.1061815706
Short name T986
Test name
Test status
Simulation time 7987172346 ps
CPU time 61.05 seconds
Started Jun 26 05:21:15 PM PDT 24
Finished Jun 26 05:22:19 PM PDT 24
Peak memory 206488 kb
Host smart-837bffc9-dd7f-43e8-ac5a-2445bf974b03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10618
15706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.1061815706
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.2473372785
Short name T76
Test name
Test status
Simulation time 3918976287 ps
CPU time 108.8 seconds
Started Jun 26 05:21:17 PM PDT 24
Finished Jun 26 05:23:09 PM PDT 24
Peak memory 206516 kb
Host smart-af3c2069-01ed-40a3-99cf-fd010c26f935
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2473372785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.2473372785
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.975942788
Short name T1680
Test name
Test status
Simulation time 236953465 ps
CPU time 0.92 seconds
Started Jun 26 05:21:16 PM PDT 24
Finished Jun 26 05:21:20 PM PDT 24
Peak memory 206196 kb
Host smart-88613648-4e08-4d5c-b71f-037d8a87a399
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=975942788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.975942788
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.3279737892
Short name T1526
Test name
Test status
Simulation time 196506409 ps
CPU time 0.86 seconds
Started Jun 26 05:21:14 PM PDT 24
Finished Jun 26 05:21:17 PM PDT 24
Peak memory 206120 kb
Host smart-8039a39e-ab92-4173-8e40-776d66364eb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32797
37892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.3279737892
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.583544120
Short name T1201
Test name
Test status
Simulation time 3688058000 ps
CPU time 27.43 seconds
Started Jun 26 05:21:14 PM PDT 24
Finished Jun 26 05:21:45 PM PDT 24
Peak memory 206508 kb
Host smart-3e024eb2-de6b-4af0-95d3-1b457f407ef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58354
4120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.583544120
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.3802118454
Short name T472
Test name
Test status
Simulation time 7136924767 ps
CPU time 51.41 seconds
Started Jun 26 05:21:15 PM PDT 24
Finished Jun 26 05:22:09 PM PDT 24
Peak memory 206596 kb
Host smart-4fef207b-8621-4b9c-8202-3103412c390f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3802118454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.3802118454
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.3398499116
Short name T405
Test name
Test status
Simulation time 227556395 ps
CPU time 0.82 seconds
Started Jun 26 05:21:23 PM PDT 24
Finished Jun 26 05:21:26 PM PDT 24
Peak memory 206228 kb
Host smart-762112a8-f913-4d4d-a93d-41946f60cc37
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3398499116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.3398499116
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.2049176485
Short name T762
Test name
Test status
Simulation time 148447594 ps
CPU time 0.8 seconds
Started Jun 26 05:21:18 PM PDT 24
Finished Jun 26 05:21:22 PM PDT 24
Peak memory 206204 kb
Host smart-351317f0-f16d-4d1d-ae2b-46e43966985c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20491
76485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.2049176485
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.3408607265
Short name T147
Test name
Test status
Simulation time 229156658 ps
CPU time 0.9 seconds
Started Jun 26 05:21:15 PM PDT 24
Finished Jun 26 05:21:19 PM PDT 24
Peak memory 206124 kb
Host smart-8c24d0d3-dbf6-49ed-aeed-a85d1e1eb8e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34086
07265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.3408607265
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.1669075964
Short name T2286
Test name
Test status
Simulation time 165420398 ps
CPU time 0.82 seconds
Started Jun 26 05:21:15 PM PDT 24
Finished Jun 26 05:21:19 PM PDT 24
Peak memory 206220 kb
Host smart-7d9184ea-d2cf-4466-84a5-2ec0887d561a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16690
75964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.1669075964
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.2045253673
Short name T1868
Test name
Test status
Simulation time 230841711 ps
CPU time 0.82 seconds
Started Jun 26 05:21:15 PM PDT 24
Finished Jun 26 05:21:19 PM PDT 24
Peak memory 206208 kb
Host smart-169d2ef0-53cc-4ef9-a646-9131ac888384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20452
53673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.2045253673
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.785250021
Short name T839
Test name
Test status
Simulation time 235793445 ps
CPU time 0.89 seconds
Started Jun 26 05:21:15 PM PDT 24
Finished Jun 26 05:21:19 PM PDT 24
Peak memory 206124 kb
Host smart-1608e064-ff2c-4c4f-b7e9-fc4431ea26d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78525
0021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.785250021
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.921680695
Short name T795
Test name
Test status
Simulation time 174884775 ps
CPU time 0.81 seconds
Started Jun 26 05:21:16 PM PDT 24
Finished Jun 26 05:21:20 PM PDT 24
Peak memory 206148 kb
Host smart-8a64a08f-6ddd-4c23-af0e-25865e8a8933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92168
0695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.921680695
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.1283344758
Short name T1011
Test name
Test status
Simulation time 195704533 ps
CPU time 0.89 seconds
Started Jun 26 05:21:14 PM PDT 24
Finished Jun 26 05:21:17 PM PDT 24
Peak memory 206196 kb
Host smart-7d2f3d37-15ca-42e8-8bac-052f280fa324
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1283344758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.1283344758
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.1702232232
Short name T2415
Test name
Test status
Simulation time 149637378 ps
CPU time 0.78 seconds
Started Jun 26 05:21:17 PM PDT 24
Finished Jun 26 05:21:21 PM PDT 24
Peak memory 206220 kb
Host smart-c26974f2-51da-4c48-89e7-0f4d5039c361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17022
32232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.1702232232
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.3276968617
Short name T809
Test name
Test status
Simulation time 74928843 ps
CPU time 0.67 seconds
Started Jun 26 05:21:13 PM PDT 24
Finished Jun 26 05:21:17 PM PDT 24
Peak memory 206176 kb
Host smart-3a531f24-0a75-4b59-93bf-2e1e9b92a56b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32769
68617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.3276968617
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.3223845618
Short name T86
Test name
Test status
Simulation time 6509102003 ps
CPU time 17.46 seconds
Started Jun 26 05:21:13 PM PDT 24
Finished Jun 26 05:21:33 PM PDT 24
Peak memory 206604 kb
Host smart-924c3793-599c-4e6b-bace-4fcdca15ac18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32238
45618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.3223845618
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.1243679449
Short name T1818
Test name
Test status
Simulation time 195534446 ps
CPU time 0.81 seconds
Started Jun 26 05:21:15 PM PDT 24
Finished Jun 26 05:21:19 PM PDT 24
Peak memory 206128 kb
Host smart-bd71d861-5d36-44c1-a784-f2e42d5f12ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12436
79449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.1243679449
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.2442626794
Short name T344
Test name
Test status
Simulation time 289649652 ps
CPU time 0.97 seconds
Started Jun 26 05:21:13 PM PDT 24
Finished Jun 26 05:21:17 PM PDT 24
Peak memory 206184 kb
Host smart-1c25daf1-46b9-44c8-b092-01f86e370fdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24426
26794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.2442626794
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.1718906352
Short name T1928
Test name
Test status
Simulation time 174805286 ps
CPU time 0.79 seconds
Started Jun 26 05:21:17 PM PDT 24
Finished Jun 26 05:21:21 PM PDT 24
Peak memory 206216 kb
Host smart-2338cb51-374d-4f80-9901-f65dd025b8cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17189
06352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.1718906352
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.3660961
Short name T646
Test name
Test status
Simulation time 178307516 ps
CPU time 0.82 seconds
Started Jun 26 05:21:16 PM PDT 24
Finished Jun 26 05:21:20 PM PDT 24
Peak memory 206132 kb
Host smart-a6d98d37-bf1e-40df-bf58-6fed772467c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36609
61 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.3660961
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.1593957824
Short name T659
Test name
Test status
Simulation time 163995620 ps
CPU time 0.79 seconds
Started Jun 26 05:21:16 PM PDT 24
Finished Jun 26 05:21:20 PM PDT 24
Peak memory 206208 kb
Host smart-282a4632-7e67-4b17-aa1d-d26020911573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15939
57824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.1593957824
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.1509145713
Short name T2348
Test name
Test status
Simulation time 172679820 ps
CPU time 0.81 seconds
Started Jun 26 05:21:17 PM PDT 24
Finished Jun 26 05:21:21 PM PDT 24
Peak memory 206112 kb
Host smart-34d38f42-40d0-42eb-8595-58decf3e2ff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15091
45713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.1509145713
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.2011019085
Short name T1584
Test name
Test status
Simulation time 149716823 ps
CPU time 0.76 seconds
Started Jun 26 05:21:15 PM PDT 24
Finished Jun 26 05:21:19 PM PDT 24
Peak memory 206192 kb
Host smart-43acb776-5ab5-40fe-9e93-7b01f36f881d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20110
19085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.2011019085
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.2875621995
Short name T1705
Test name
Test status
Simulation time 166006876 ps
CPU time 0.84 seconds
Started Jun 26 05:21:17 PM PDT 24
Finished Jun 26 05:21:21 PM PDT 24
Peak memory 206132 kb
Host smart-48ef2afb-f99f-417d-838b-b26b94db3d54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28756
21995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.2875621995
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.290052357
Short name T1730
Test name
Test status
Simulation time 4841966201 ps
CPU time 134.71 seconds
Started Jun 26 05:21:16 PM PDT 24
Finished Jun 26 05:23:34 PM PDT 24
Peak memory 206576 kb
Host smart-e48d8966-17f1-4ff7-8daf-f1cdf3582f29
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=290052357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.290052357
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.3603594709
Short name T1691
Test name
Test status
Simulation time 172889928 ps
CPU time 0.77 seconds
Started Jun 26 05:21:15 PM PDT 24
Finished Jun 26 05:21:18 PM PDT 24
Peak memory 206212 kb
Host smart-85c9539d-ba25-4c04-b3d6-72b4055e4549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36035
94709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.3603594709
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.2679409933
Short name T999
Test name
Test status
Simulation time 162414516 ps
CPU time 0.85 seconds
Started Jun 26 05:21:15 PM PDT 24
Finished Jun 26 05:21:19 PM PDT 24
Peak memory 206212 kb
Host smart-4aa1f56d-d459-42f6-b1c3-adee73e8c2bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26794
09933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.2679409933
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.2584819086
Short name T834
Test name
Test status
Simulation time 4018647110 ps
CPU time 107.37 seconds
Started Jun 26 05:21:17 PM PDT 24
Finished Jun 26 05:23:08 PM PDT 24
Peak memory 206356 kb
Host smart-d5e8d4fb-7d1a-4a17-b45d-752afe0569a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25848
19086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.2584819086
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.3587403157
Short name T2154
Test name
Test status
Simulation time 4582585605 ps
CPU time 5.48 seconds
Started Jun 26 05:21:17 PM PDT 24
Finished Jun 26 05:21:26 PM PDT 24
Peak memory 206504 kb
Host smart-8317d4f2-4e63-4370-a63c-c4d50e1fe622
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3587403157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.3587403157
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.3124588084
Short name T2564
Test name
Test status
Simulation time 13363101313 ps
CPU time 12.89 seconds
Started Jun 26 05:21:16 PM PDT 24
Finished Jun 26 05:21:32 PM PDT 24
Peak memory 206328 kb
Host smart-c0970626-afca-47e8-a25a-5f87d05e0e1a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3124588084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.3124588084
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.1461150893
Short name T1022
Test name
Test status
Simulation time 23326125107 ps
CPU time 24.61 seconds
Started Jun 26 05:21:18 PM PDT 24
Finished Jun 26 05:21:46 PM PDT 24
Peak memory 206348 kb
Host smart-2f25af8a-b8d5-48bc-ae1e-766d3f982c04
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1461150893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.1461150893
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.3855692681
Short name T1257
Test name
Test status
Simulation time 198825635 ps
CPU time 0.84 seconds
Started Jun 26 05:21:21 PM PDT 24
Finished Jun 26 05:21:23 PM PDT 24
Peak memory 206212 kb
Host smart-95308262-ba6d-405a-8f5d-b861eaa4e1c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38556
92681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.3855692681
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.2829479360
Short name T1629
Test name
Test status
Simulation time 180936770 ps
CPU time 0.75 seconds
Started Jun 26 05:21:23 PM PDT 24
Finished Jun 26 05:21:26 PM PDT 24
Peak memory 206204 kb
Host smart-b4721c01-62ca-428c-a28f-86b569d0c603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28294
79360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.2829479360
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.3218580417
Short name T1848
Test name
Test status
Simulation time 425223738 ps
CPU time 1.46 seconds
Started Jun 26 05:21:13 PM PDT 24
Finished Jun 26 05:21:18 PM PDT 24
Peak memory 206124 kb
Host smart-257e1ff5-1f26-4129-8af8-d808df7ef8bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32185
80417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.3218580417
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.2396046112
Short name T176
Test name
Test status
Simulation time 413227429 ps
CPU time 1.13 seconds
Started Jun 26 05:21:16 PM PDT 24
Finished Jun 26 05:21:21 PM PDT 24
Peak memory 206140 kb
Host smart-380e0aea-e646-4e0f-9bab-350ef4011bec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23960
46112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.2396046112
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.1450853719
Short name T1534
Test name
Test status
Simulation time 11454756383 ps
CPU time 23.1 seconds
Started Jun 26 05:21:21 PM PDT 24
Finished Jun 26 05:21:45 PM PDT 24
Peak memory 206508 kb
Host smart-1d9f982d-e768-41c6-8c78-96c84455fafa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14508
53719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.1450853719
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.4048282784
Short name T2172
Test name
Test status
Simulation time 347826902 ps
CPU time 1.17 seconds
Started Jun 26 05:21:13 PM PDT 24
Finished Jun 26 05:21:17 PM PDT 24
Peak memory 206128 kb
Host smart-06db80a3-3147-4808-95cd-35623bbe5ec2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40482
82784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.4048282784
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.2261755402
Short name T1736
Test name
Test status
Simulation time 151814601 ps
CPU time 0.79 seconds
Started Jun 26 05:21:13 PM PDT 24
Finished Jun 26 05:21:17 PM PDT 24
Peak memory 206200 kb
Host smart-0713d67f-7519-4f4e-a1d4-af67cc2188d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22617
55402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.2261755402
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.3018202115
Short name T2224
Test name
Test status
Simulation time 108928959 ps
CPU time 0.71 seconds
Started Jun 26 05:21:24 PM PDT 24
Finished Jun 26 05:21:28 PM PDT 24
Peak memory 206180 kb
Host smart-4c6ded00-a2a8-4b48-a562-462ab0c5fcc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30182
02115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.3018202115
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.1816738449
Short name T2315
Test name
Test status
Simulation time 793299457 ps
CPU time 1.97 seconds
Started Jun 26 05:21:16 PM PDT 24
Finished Jun 26 05:21:22 PM PDT 24
Peak memory 206348 kb
Host smart-a20681e9-ba79-489d-b85a-02a0bbf688e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18167
38449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.1816738449
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.89041318
Short name T1498
Test name
Test status
Simulation time 307199779 ps
CPU time 1.92 seconds
Started Jun 26 05:21:21 PM PDT 24
Finished Jun 26 05:21:25 PM PDT 24
Peak memory 206344 kb
Host smart-a0f41e2a-89cd-4e33-88f4-d37603a51663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89041
318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.89041318
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.4153147882
Short name T686
Test name
Test status
Simulation time 215796867 ps
CPU time 0.85 seconds
Started Jun 26 05:21:23 PM PDT 24
Finished Jun 26 05:21:26 PM PDT 24
Peak memory 206188 kb
Host smart-6d1a1b67-8622-4768-99ac-2a4d1df7c27a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41531
47882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.4153147882
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.1968592840
Short name T2363
Test name
Test status
Simulation time 141624447 ps
CPU time 0.77 seconds
Started Jun 26 05:21:23 PM PDT 24
Finished Jun 26 05:21:27 PM PDT 24
Peak memory 206128 kb
Host smart-8ec4eca8-2139-4b55-9201-9b510aecfb5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19685
92840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.1968592840
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.3531979807
Short name T1776
Test name
Test status
Simulation time 259828254 ps
CPU time 0.97 seconds
Started Jun 26 05:21:23 PM PDT 24
Finished Jun 26 05:21:27 PM PDT 24
Peak memory 206132 kb
Host smart-a0206f6a-9a32-43c5-ac56-7a9bce233688
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35319
79807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.3531979807
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_invalid_sync.70830462
Short name T1788
Test name
Test status
Simulation time 8455213567 ps
CPU time 65.4 seconds
Started Jun 26 05:21:24 PM PDT 24
Finished Jun 26 05:22:32 PM PDT 24
Peak memory 206472 kb
Host smart-4902588f-2f37-4142-8bd3-1755eb2eeb40
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=70830462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.70830462
Directory /workspace/45.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.568539771
Short name T455
Test name
Test status
Simulation time 214909621 ps
CPU time 0.87 seconds
Started Jun 26 05:21:25 PM PDT 24
Finished Jun 26 05:21:28 PM PDT 24
Peak memory 206168 kb
Host smart-9e484d00-16e3-4bde-82b7-04cae2eb6c70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56853
9771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.568539771
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.2856110434
Short name T710
Test name
Test status
Simulation time 23386998912 ps
CPU time 30.44 seconds
Started Jun 26 05:21:21 PM PDT 24
Finished Jun 26 05:21:53 PM PDT 24
Peak memory 206292 kb
Host smart-b8b44efe-9420-436b-bbd3-1ca43710f24f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28561
10434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.2856110434
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.3488455729
Short name T2148
Test name
Test status
Simulation time 3330877876 ps
CPU time 3.74 seconds
Started Jun 26 05:21:23 PM PDT 24
Finished Jun 26 05:21:29 PM PDT 24
Peak memory 206180 kb
Host smart-63e8085d-fe81-454d-acbe-7a8158b62c49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34884
55729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.3488455729
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.2441298961
Short name T753
Test name
Test status
Simulation time 6413730187 ps
CPU time 61.01 seconds
Started Jun 26 05:21:21 PM PDT 24
Finished Jun 26 05:22:24 PM PDT 24
Peak memory 206508 kb
Host smart-924c04fc-58ce-41d7-9ceb-fe4c61778f73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24412
98961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.2441298961
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.2615141608
Short name T864
Test name
Test status
Simulation time 4673424736 ps
CPU time 118.86 seconds
Started Jun 26 05:21:21 PM PDT 24
Finished Jun 26 05:23:22 PM PDT 24
Peak memory 206448 kb
Host smart-13e5149f-f2c4-42d2-970b-32ead6098d82
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2615141608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.2615141608
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.3572562732
Short name T1237
Test name
Test status
Simulation time 252207575 ps
CPU time 0.97 seconds
Started Jun 26 05:21:24 PM PDT 24
Finished Jun 26 05:21:27 PM PDT 24
Peak memory 206248 kb
Host smart-90d341aa-c085-4510-aff2-e23e4256c456
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3572562732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.3572562732
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.12266802
Short name T75
Test name
Test status
Simulation time 210101699 ps
CPU time 0.89 seconds
Started Jun 26 05:21:21 PM PDT 24
Finished Jun 26 05:21:24 PM PDT 24
Peak memory 206208 kb
Host smart-b336f421-a40c-45f3-8632-1e37d956a073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12266
802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.12266802
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.3117396008
Short name T714
Test name
Test status
Simulation time 4884377750 ps
CPU time 133.78 seconds
Started Jun 26 05:21:21 PM PDT 24
Finished Jun 26 05:23:37 PM PDT 24
Peak memory 206460 kb
Host smart-5802456b-27ce-4e67-ad74-0a51a18cc022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31173
96008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.3117396008
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.1241694900
Short name T2002
Test name
Test status
Simulation time 3152800867 ps
CPU time 23.06 seconds
Started Jun 26 05:21:23 PM PDT 24
Finished Jun 26 05:21:48 PM PDT 24
Peak memory 206480 kb
Host smart-dff3f04e-7fd5-4318-b6dd-c856550c8194
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1241694900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.1241694900
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.3055072662
Short name T736
Test name
Test status
Simulation time 183709170 ps
CPU time 0.83 seconds
Started Jun 26 05:21:23 PM PDT 24
Finished Jun 26 05:21:26 PM PDT 24
Peak memory 206240 kb
Host smart-ec2a9e5a-c1f3-410f-b686-5e30e60cf73e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3055072662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.3055072662
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.989238435
Short name T1846
Test name
Test status
Simulation time 162935584 ps
CPU time 0.8 seconds
Started Jun 26 05:21:22 PM PDT 24
Finished Jun 26 05:21:25 PM PDT 24
Peak memory 206216 kb
Host smart-acde9b72-aeea-4310-9eb3-3069c7c4ea4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98923
8435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.989238435
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.3414049077
Short name T144
Test name
Test status
Simulation time 268207323 ps
CPU time 1.03 seconds
Started Jun 26 05:21:23 PM PDT 24
Finished Jun 26 05:21:26 PM PDT 24
Peak memory 206080 kb
Host smart-833ea887-7436-4892-9711-f3ecffd2f931
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34140
49077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.3414049077
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.227631276
Short name T2371
Test name
Test status
Simulation time 186976605 ps
CPU time 0.84 seconds
Started Jun 26 05:21:24 PM PDT 24
Finished Jun 26 05:21:27 PM PDT 24
Peak memory 206140 kb
Host smart-652df662-0063-4b12-b262-6d09ace8d4c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22763
1276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.227631276
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.172101082
Short name T2185
Test name
Test status
Simulation time 188938167 ps
CPU time 0.85 seconds
Started Jun 26 05:21:24 PM PDT 24
Finished Jun 26 05:21:28 PM PDT 24
Peak memory 206160 kb
Host smart-a1bf26e5-3a7b-463f-8793-dd43e31c2b4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17210
1082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.172101082
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.3479548053
Short name T2373
Test name
Test status
Simulation time 150025489 ps
CPU time 0.77 seconds
Started Jun 26 05:21:23 PM PDT 24
Finished Jun 26 05:21:26 PM PDT 24
Peak memory 206128 kb
Host smart-cc35ab94-d53f-46f4-a078-9c5054cd8f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34795
48053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.3479548053
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.16134443
Short name T1694
Test name
Test status
Simulation time 197807053 ps
CPU time 0.81 seconds
Started Jun 26 05:21:23 PM PDT 24
Finished Jun 26 05:21:26 PM PDT 24
Peak memory 206232 kb
Host smart-d785e63e-76d7-417e-affd-723a351ebff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16134
443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.16134443
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.632512351
Short name T2046
Test name
Test status
Simulation time 244487650 ps
CPU time 0.93 seconds
Started Jun 26 05:21:24 PM PDT 24
Finished Jun 26 05:21:28 PM PDT 24
Peak memory 206232 kb
Host smart-44f00648-846f-4920-bd8c-0c1a5af26b1a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=632512351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.632512351
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.3884236521
Short name T2265
Test name
Test status
Simulation time 144516143 ps
CPU time 0.79 seconds
Started Jun 26 05:21:21 PM PDT 24
Finished Jun 26 05:21:24 PM PDT 24
Peak memory 206208 kb
Host smart-6907c3fb-f7d1-4cf5-b8ed-25fbff830ef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38842
36521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.3884236521
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.3772801297
Short name T2437
Test name
Test status
Simulation time 51329874 ps
CPU time 0.69 seconds
Started Jun 26 05:21:24 PM PDT 24
Finished Jun 26 05:21:27 PM PDT 24
Peak memory 206204 kb
Host smart-89edf761-f3df-4381-a30d-2b0dcb261a43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37728
01297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.3772801297
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.1170011424
Short name T2307
Test name
Test status
Simulation time 17338407658 ps
CPU time 37.9 seconds
Started Jun 26 05:21:23 PM PDT 24
Finished Jun 26 05:22:03 PM PDT 24
Peak memory 206416 kb
Host smart-49e1b4ea-42a5-4d9c-b303-b5bb26710943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11700
11424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.1170011424
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.328206898
Short name T1340
Test name
Test status
Simulation time 145359539 ps
CPU time 0.77 seconds
Started Jun 26 05:21:22 PM PDT 24
Finished Jun 26 05:21:24 PM PDT 24
Peak memory 206176 kb
Host smart-e224c4d4-7881-4f14-b34b-a4b4e325cfa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32820
6898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.328206898
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.3243873575
Short name T632
Test name
Test status
Simulation time 210627616 ps
CPU time 0.98 seconds
Started Jun 26 05:21:25 PM PDT 24
Finished Jun 26 05:21:29 PM PDT 24
Peak memory 206204 kb
Host smart-695b0300-a6a6-4af2-a3de-6285f66c8026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32438
73575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.3243873575
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.2811570796
Short name T534
Test name
Test status
Simulation time 181398050 ps
CPU time 0.82 seconds
Started Jun 26 05:21:23 PM PDT 24
Finished Jun 26 05:21:26 PM PDT 24
Peak memory 206196 kb
Host smart-023b4ede-ff5e-4ec1-804e-65a4c3b3c886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28115
70796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.2811570796
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.3909585777
Short name T1803
Test name
Test status
Simulation time 165756977 ps
CPU time 0.85 seconds
Started Jun 26 05:21:23 PM PDT 24
Finished Jun 26 05:21:26 PM PDT 24
Peak memory 206220 kb
Host smart-c64bd41d-78a2-4e2e-994b-3515f6e40ddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39095
85777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.3909585777
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.569792571
Short name T2118
Test name
Test status
Simulation time 165141782 ps
CPU time 0.81 seconds
Started Jun 26 05:21:23 PM PDT 24
Finished Jun 26 05:21:26 PM PDT 24
Peak memory 206132 kb
Host smart-e8614a6f-b1f1-4679-b855-1dc13c96873b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56979
2571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.569792571
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.3537746998
Short name T1490
Test name
Test status
Simulation time 148621417 ps
CPU time 0.74 seconds
Started Jun 26 05:21:25 PM PDT 24
Finished Jun 26 05:21:28 PM PDT 24
Peak memory 206204 kb
Host smart-b34f9c94-adc6-496d-a8ad-64ff14248efa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35377
46998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.3537746998
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.2903519529
Short name T1888
Test name
Test status
Simulation time 158285872 ps
CPU time 0.78 seconds
Started Jun 26 05:21:25 PM PDT 24
Finished Jun 26 05:21:28 PM PDT 24
Peak memory 206188 kb
Host smart-94c0536f-cad5-4143-98bf-5b2cbc9bb603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29035
19529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.2903519529
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.2080777657
Short name T421
Test name
Test status
Simulation time 180247554 ps
CPU time 0.9 seconds
Started Jun 26 05:21:23 PM PDT 24
Finished Jun 26 05:21:26 PM PDT 24
Peak memory 206192 kb
Host smart-23ff8545-92c1-4bdb-af53-22ab02aacfed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20807
77657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.2080777657
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.2105564206
Short name T2440
Test name
Test status
Simulation time 4644905910 ps
CPU time 32.9 seconds
Started Jun 26 05:21:21 PM PDT 24
Finished Jun 26 05:21:56 PM PDT 24
Peak memory 206480 kb
Host smart-e1206a73-9763-4755-838c-99004425dec5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2105564206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.2105564206
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.1326977735
Short name T1514
Test name
Test status
Simulation time 164765611 ps
CPU time 0.78 seconds
Started Jun 26 05:21:25 PM PDT 24
Finished Jun 26 05:21:29 PM PDT 24
Peak memory 206176 kb
Host smart-aa5cac80-0c2a-437f-bd6e-e9bd946a9dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13269
77735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.1326977735
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.3512649926
Short name T395
Test name
Test status
Simulation time 159586294 ps
CPU time 0.79 seconds
Started Jun 26 05:21:24 PM PDT 24
Finished Jun 26 05:21:28 PM PDT 24
Peak memory 206172 kb
Host smart-2a401171-ef94-40fc-8a91-2ee27d41330a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35126
49926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.3512649926
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.460288560
Short name T1536
Test name
Test status
Simulation time 5473621573 ps
CPU time 155.08 seconds
Started Jun 26 05:21:22 PM PDT 24
Finished Jun 26 05:23:59 PM PDT 24
Peak memory 206508 kb
Host smart-b8f26875-134a-44f8-8f42-283c2bc9856b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46028
8560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.460288560
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.1540714568
Short name T446
Test name
Test status
Simulation time 3591665438 ps
CPU time 4.15 seconds
Started Jun 26 05:21:33 PM PDT 24
Finished Jun 26 05:21:39 PM PDT 24
Peak memory 206384 kb
Host smart-508a3917-c596-4352-b010-060fab1a8e47
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1540714568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.1540714568
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.2010961181
Short name T1284
Test name
Test status
Simulation time 13435589566 ps
CPU time 12.93 seconds
Started Jun 26 05:21:31 PM PDT 24
Finished Jun 26 05:21:46 PM PDT 24
Peak memory 206560 kb
Host smart-0c90a855-6e91-49cc-b75e-c4bfd074e524
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2010961181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.2010961181
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.514412243
Short name T2343
Test name
Test status
Simulation time 23355198518 ps
CPU time 23.65 seconds
Started Jun 26 05:21:30 PM PDT 24
Finished Jun 26 05:21:55 PM PDT 24
Peak memory 206244 kb
Host smart-5f772f24-8d16-44db-834b-d2c6ac3e8ada
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=514412243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.514412243
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.1204418574
Short name T682
Test name
Test status
Simulation time 149272427 ps
CPU time 0.79 seconds
Started Jun 26 05:21:32 PM PDT 24
Finished Jun 26 05:21:35 PM PDT 24
Peak memory 206196 kb
Host smart-351e8a4c-b668-4f4d-8f8f-3abd5d4083c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12044
18574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.1204418574
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.2932451993
Short name T797
Test name
Test status
Simulation time 180087293 ps
CPU time 0.79 seconds
Started Jun 26 05:21:31 PM PDT 24
Finished Jun 26 05:21:33 PM PDT 24
Peak memory 206212 kb
Host smart-21cd249c-15ed-4bb6-961b-1bf8b4b9b6c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29324
51993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.2932451993
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.3099714874
Short name T2059
Test name
Test status
Simulation time 549829445 ps
CPU time 1.54 seconds
Started Jun 26 05:21:31 PM PDT 24
Finished Jun 26 05:21:35 PM PDT 24
Peak memory 206460 kb
Host smart-dae1362b-2021-4713-b7c7-2355a16771a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30997
14874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.3099714874
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.3243657709
Short name T811
Test name
Test status
Simulation time 1547193712 ps
CPU time 3.29 seconds
Started Jun 26 05:21:30 PM PDT 24
Finished Jun 26 05:21:35 PM PDT 24
Peak memory 206324 kb
Host smart-a07cfccb-747f-4708-82ce-10551a6d4907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32436
57709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.3243657709
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.2499270650
Short name T1360
Test name
Test status
Simulation time 15182500052 ps
CPU time 29.5 seconds
Started Jun 26 05:21:33 PM PDT 24
Finished Jun 26 05:22:04 PM PDT 24
Peak memory 206480 kb
Host smart-7f3135f8-be60-48de-921a-64becec730f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24992
70650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.2499270650
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.537067660
Short name T1613
Test name
Test status
Simulation time 382089210 ps
CPU time 1.15 seconds
Started Jun 26 05:21:31 PM PDT 24
Finished Jun 26 05:21:35 PM PDT 24
Peak memory 206144 kb
Host smart-0475f73b-05e9-4406-973e-2ecdcbed74a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53706
7660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.537067660
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.993077473
Short name T1382
Test name
Test status
Simulation time 148307638 ps
CPU time 0.78 seconds
Started Jun 26 05:21:30 PM PDT 24
Finished Jun 26 05:21:33 PM PDT 24
Peak memory 206200 kb
Host smart-c512df35-74eb-490a-abb7-9d8596f9c701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99307
7473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.993077473
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.4266399836
Short name T1698
Test name
Test status
Simulation time 38964706 ps
CPU time 0.69 seconds
Started Jun 26 05:21:30 PM PDT 24
Finished Jun 26 05:21:32 PM PDT 24
Peak memory 206240 kb
Host smart-610b8350-5a77-4722-9b11-2f01a045a5ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42663
99836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.4266399836
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.1737643176
Short name T1800
Test name
Test status
Simulation time 878071757 ps
CPU time 2.14 seconds
Started Jun 26 05:21:33 PM PDT 24
Finished Jun 26 05:21:37 PM PDT 24
Peak memory 206496 kb
Host smart-a206f065-389a-4260-8a2a-7ff1677b291b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17376
43176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.1737643176
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.3855399455
Short name T1975
Test name
Test status
Simulation time 198769153 ps
CPU time 1.93 seconds
Started Jun 26 05:21:33 PM PDT 24
Finished Jun 26 05:21:37 PM PDT 24
Peak memory 206296 kb
Host smart-5ba46332-d356-4cde-b672-85182e536020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38553
99455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.3855399455
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.2125544249
Short name T1105
Test name
Test status
Simulation time 243512408 ps
CPU time 0.91 seconds
Started Jun 26 05:21:34 PM PDT 24
Finished Jun 26 05:21:36 PM PDT 24
Peak memory 206224 kb
Host smart-652e95e1-c38a-4a34-aa2a-9611fbf0cccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21255
44249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.2125544249
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.1405762163
Short name T117
Test name
Test status
Simulation time 142784813 ps
CPU time 0.75 seconds
Started Jun 26 05:21:38 PM PDT 24
Finished Jun 26 05:21:41 PM PDT 24
Peak memory 206244 kb
Host smart-124a26ae-cba2-4b4f-8629-c99fa84fe765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14057
62163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.1405762163
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.1628527897
Short name T2365
Test name
Test status
Simulation time 198437782 ps
CPU time 0.86 seconds
Started Jun 26 05:21:31 PM PDT 24
Finished Jun 26 05:21:34 PM PDT 24
Peak memory 206224 kb
Host smart-ef9269e0-1a1a-48dd-bd8c-f21c633d1f24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16285
27897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.1628527897
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.3269500366
Short name T1574
Test name
Test status
Simulation time 252350937 ps
CPU time 0.89 seconds
Started Jun 26 05:21:33 PM PDT 24
Finished Jun 26 05:21:35 PM PDT 24
Peak memory 206096 kb
Host smart-d3dd722e-68e5-46b4-bbba-c2864a668441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32695
00366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.3269500366
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.2246194802
Short name T2121
Test name
Test status
Simulation time 23294008340 ps
CPU time 22.86 seconds
Started Jun 26 05:21:32 PM PDT 24
Finished Jun 26 05:21:56 PM PDT 24
Peak memory 206320 kb
Host smart-0d28d440-9cd7-47e1-9e96-7b3fc6f9adfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22461
94802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.2246194802
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.3726074143
Short name T1583
Test name
Test status
Simulation time 3361617139 ps
CPU time 3.76 seconds
Started Jun 26 05:21:29 PM PDT 24
Finished Jun 26 05:21:34 PM PDT 24
Peak memory 206184 kb
Host smart-0e986d90-03d8-4ed8-bf22-db660be966e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37260
74143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.3726074143
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.2065896029
Short name T2309
Test name
Test status
Simulation time 8885823812 ps
CPU time 245.66 seconds
Started Jun 26 05:21:30 PM PDT 24
Finished Jun 26 05:25:37 PM PDT 24
Peak memory 206552 kb
Host smart-9edf0ace-7b22-4141-8120-021eef68b3cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20658
96029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.2065896029
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.3424896700
Short name T1562
Test name
Test status
Simulation time 7318301156 ps
CPU time 71.31 seconds
Started Jun 26 05:21:37 PM PDT 24
Finished Jun 26 05:22:52 PM PDT 24
Peak memory 206476 kb
Host smart-e1b7ffef-404b-4034-9e45-fb44c3d480cf
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3424896700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.3424896700
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.1739822786
Short name T1120
Test name
Test status
Simulation time 244507636 ps
CPU time 0.94 seconds
Started Jun 26 05:21:43 PM PDT 24
Finished Jun 26 05:21:49 PM PDT 24
Peak memory 206196 kb
Host smart-7481640c-aec5-40d0-9d23-4a587a571bba
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1739822786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.1739822786
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.2873102045
Short name T2272
Test name
Test status
Simulation time 197708554 ps
CPU time 0.96 seconds
Started Jun 26 05:21:29 PM PDT 24
Finished Jun 26 05:21:31 PM PDT 24
Peak memory 206204 kb
Host smart-7d341a46-a66e-4bff-a589-62e36547f600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28731
02045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.2873102045
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.4016222639
Short name T2157
Test name
Test status
Simulation time 5271720261 ps
CPU time 49.63 seconds
Started Jun 26 05:21:42 PM PDT 24
Finished Jun 26 05:22:36 PM PDT 24
Peak memory 206552 kb
Host smart-3ec2cb4f-c8c7-439e-a080-566b49578c87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40162
22639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.4016222639
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.3234793887
Short name T1597
Test name
Test status
Simulation time 4579268191 ps
CPU time 32.08 seconds
Started Jun 26 05:21:38 PM PDT 24
Finished Jun 26 05:22:14 PM PDT 24
Peak memory 206500 kb
Host smart-aa4ba2e0-1e6d-49df-8983-68a513e32cbb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3234793887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.3234793887
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.2565518736
Short name T1186
Test name
Test status
Simulation time 168788846 ps
CPU time 0.81 seconds
Started Jun 26 05:21:45 PM PDT 24
Finished Jun 26 05:21:50 PM PDT 24
Peak memory 206236 kb
Host smart-5feea4e0-35f2-47af-82b9-f14f0bf9cdd2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2565518736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.2565518736
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.3829624976
Short name T927
Test name
Test status
Simulation time 150988671 ps
CPU time 0.83 seconds
Started Jun 26 05:21:35 PM PDT 24
Finished Jun 26 05:21:38 PM PDT 24
Peak memory 206176 kb
Host smart-7d1cd9e5-6bf1-4c7b-a82d-8aa8443bd84f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38296
24976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.3829624976
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.1145234187
Short name T132
Test name
Test status
Simulation time 217961298 ps
CPU time 0.82 seconds
Started Jun 26 05:21:41 PM PDT 24
Finished Jun 26 05:21:46 PM PDT 24
Peak memory 206164 kb
Host smart-514df1d7-ac24-4b12-a9bf-ed339bb43c15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11452
34187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.1145234187
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.245103785
Short name T625
Test name
Test status
Simulation time 189986025 ps
CPU time 0.88 seconds
Started Jun 26 05:21:36 PM PDT 24
Finished Jun 26 05:21:39 PM PDT 24
Peak memory 206124 kb
Host smart-04392ff3-b00b-4e29-81b3-dac87e8df6d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24510
3785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.245103785
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.3859696275
Short name T552
Test name
Test status
Simulation time 179325295 ps
CPU time 0.83 seconds
Started Jun 26 05:21:42 PM PDT 24
Finished Jun 26 05:21:47 PM PDT 24
Peak memory 206228 kb
Host smart-475af5b8-8256-4f9d-90d0-26c24f947102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38596
96275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.3859696275
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.1375846734
Short name T1738
Test name
Test status
Simulation time 210917729 ps
CPU time 0.87 seconds
Started Jun 26 05:21:42 PM PDT 24
Finished Jun 26 05:21:47 PM PDT 24
Peak memory 206228 kb
Host smart-27b85b44-9b2f-453a-b43b-9efb437f62ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13758
46734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.1375846734
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.491425646
Short name T82
Test name
Test status
Simulation time 150887229 ps
CPU time 0.77 seconds
Started Jun 26 05:21:36 PM PDT 24
Finished Jun 26 05:21:38 PM PDT 24
Peak memory 206156 kb
Host smart-6c43cd54-8a74-456d-8c92-2b1ff7b0f98a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49142
5646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.491425646
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.3522229335
Short name T931
Test name
Test status
Simulation time 260962754 ps
CPU time 1.01 seconds
Started Jun 26 05:21:35 PM PDT 24
Finished Jun 26 05:21:38 PM PDT 24
Peak memory 206200 kb
Host smart-2fabdc11-3c5f-4ebe-8058-dc7eabff0b83
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3522229335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.3522229335
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.2114630371
Short name T615
Test name
Test status
Simulation time 159334400 ps
CPU time 0.76 seconds
Started Jun 26 05:21:38 PM PDT 24
Finished Jun 26 05:21:41 PM PDT 24
Peak memory 206232 kb
Host smart-f30b8ff4-9c1c-45a5-9a02-217fedd8fd47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21146
30371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.2114630371
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.3748749945
Short name T1311
Test name
Test status
Simulation time 57218683 ps
CPU time 0.68 seconds
Started Jun 26 05:21:36 PM PDT 24
Finished Jun 26 05:21:39 PM PDT 24
Peak memory 206200 kb
Host smart-033328ff-f213-456c-a8c5-e566beec1380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37487
49945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.3748749945
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.1362951633
Short name T2553
Test name
Test status
Simulation time 18284634922 ps
CPU time 38.14 seconds
Started Jun 26 05:21:36 PM PDT 24
Finished Jun 26 05:22:16 PM PDT 24
Peak memory 206780 kb
Host smart-496edb32-72fb-4c6e-81d3-eb603b2f5ef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13629
51633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.1362951633
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.3077325854
Short name T978
Test name
Test status
Simulation time 160143315 ps
CPU time 0.84 seconds
Started Jun 26 05:21:38 PM PDT 24
Finished Jun 26 05:21:42 PM PDT 24
Peak memory 206120 kb
Host smart-420c5636-0341-4ef3-a335-3ceed2d0a81e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30773
25854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.3077325854
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.135630155
Short name T415
Test name
Test status
Simulation time 154018879 ps
CPU time 0.82 seconds
Started Jun 26 05:21:34 PM PDT 24
Finished Jun 26 05:21:36 PM PDT 24
Peak memory 206136 kb
Host smart-975ea532-1d49-416f-879c-5a4a6531f545
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13563
0155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.135630155
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.4058730821
Short name T445
Test name
Test status
Simulation time 235624208 ps
CPU time 0.82 seconds
Started Jun 26 05:21:36 PM PDT 24
Finished Jun 26 05:21:39 PM PDT 24
Peak memory 206144 kb
Host smart-6b1b7158-bb0a-432a-9c1f-8d7d12602125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40587
30821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.4058730821
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.3652243107
Short name T2035
Test name
Test status
Simulation time 178737557 ps
CPU time 0.79 seconds
Started Jun 26 05:21:41 PM PDT 24
Finished Jun 26 05:21:45 PM PDT 24
Peak memory 206212 kb
Host smart-e54cf128-37de-4c21-a351-793b01783312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36522
43107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.3652243107
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.2323351508
Short name T1019
Test name
Test status
Simulation time 139985037 ps
CPU time 0.77 seconds
Started Jun 26 05:21:36 PM PDT 24
Finished Jun 26 05:21:38 PM PDT 24
Peak memory 206208 kb
Host smart-3a8aea64-be9a-42bf-87d2-96df12c61052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23233
51508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.2323351508
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.2368595990
Short name T1087
Test name
Test status
Simulation time 194788931 ps
CPU time 0.86 seconds
Started Jun 26 05:21:35 PM PDT 24
Finished Jun 26 05:21:37 PM PDT 24
Peak memory 206068 kb
Host smart-6c2f5645-d6a9-40c4-be72-7c2e37bac9de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23685
95990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.2368595990
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.516384794
Short name T2253
Test name
Test status
Simulation time 214202057 ps
CPU time 0.85 seconds
Started Jun 26 05:21:37 PM PDT 24
Finished Jun 26 05:21:41 PM PDT 24
Peak memory 206116 kb
Host smart-0d035fb1-3e47-45b8-b7b0-8bad59cf1b9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51638
4794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.516384794
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.3672214265
Short name T27
Test name
Test status
Simulation time 285343306 ps
CPU time 0.98 seconds
Started Jun 26 05:21:37 PM PDT 24
Finished Jun 26 05:21:41 PM PDT 24
Peak memory 206148 kb
Host smart-54454739-7b17-4a0e-913e-1b8d7c6d56d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36722
14265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.3672214265
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.236096988
Short name T1508
Test name
Test status
Simulation time 5593493537 ps
CPU time 54.27 seconds
Started Jun 26 05:21:44 PM PDT 24
Finished Jun 26 05:22:43 PM PDT 24
Peak memory 206620 kb
Host smart-a4e1dc3f-3461-4635-a9ec-0eab73c7aeaf
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=236096988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.236096988
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.460109104
Short name T1436
Test name
Test status
Simulation time 194689934 ps
CPU time 0.85 seconds
Started Jun 26 05:21:35 PM PDT 24
Finished Jun 26 05:21:38 PM PDT 24
Peak memory 206200 kb
Host smart-b8f439d5-618e-421b-96fe-acdb7dd31a16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46010
9104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.460109104
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.905340966
Short name T1725
Test name
Test status
Simulation time 161137646 ps
CPU time 0.82 seconds
Started Jun 26 05:21:37 PM PDT 24
Finished Jun 26 05:21:41 PM PDT 24
Peak memory 206228 kb
Host smart-468c95ce-b710-4677-8d79-c071082a422f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90534
0966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.905340966
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.2906556583
Short name T1306
Test name
Test status
Simulation time 5242272616 ps
CPU time 150.25 seconds
Started Jun 26 05:21:37 PM PDT 24
Finished Jun 26 05:24:10 PM PDT 24
Peak memory 206508 kb
Host smart-0490a91a-892f-4af8-b1cc-870788d6eadf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29065
56583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.2906556583
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.1707589923
Short name T1697
Test name
Test status
Simulation time 3501393060 ps
CPU time 4.21 seconds
Started Jun 26 05:21:41 PM PDT 24
Finished Jun 26 05:21:49 PM PDT 24
Peak memory 206208 kb
Host smart-81c78aad-6d03-4ab4-a326-961b7cb77d28
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1707589923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.1707589923
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.1009372900
Short name T584
Test name
Test status
Simulation time 13405283782 ps
CPU time 15.46 seconds
Started Jun 26 05:21:43 PM PDT 24
Finished Jun 26 05:22:02 PM PDT 24
Peak memory 206336 kb
Host smart-9dfbf2f7-a157-40c6-8023-df867d558beb
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1009372900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.1009372900
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.4150118056
Short name T2305
Test name
Test status
Simulation time 23363212761 ps
CPU time 23.91 seconds
Started Jun 26 05:21:44 PM PDT 24
Finished Jun 26 05:22:12 PM PDT 24
Peak memory 206492 kb
Host smart-6346a14c-a4e4-4034-a96a-0456c28344ac
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4150118056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.4150118056
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.1238538095
Short name T1143
Test name
Test status
Simulation time 155903236 ps
CPU time 0.81 seconds
Started Jun 26 05:21:43 PM PDT 24
Finished Jun 26 05:21:48 PM PDT 24
Peak memory 206448 kb
Host smart-8b21de1e-7df6-4135-bad5-2e857761d0e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12385
38095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.1238538095
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.2418140660
Short name T1621
Test name
Test status
Simulation time 161500905 ps
CPU time 0.78 seconds
Started Jun 26 05:21:42 PM PDT 24
Finished Jun 26 05:21:47 PM PDT 24
Peak memory 206196 kb
Host smart-8b32ff6e-d3f8-484b-a859-886d0af2c7df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24181
40660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.2418140660
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.2835178870
Short name T2417
Test name
Test status
Simulation time 394220764 ps
CPU time 1.27 seconds
Started Jun 26 05:21:43 PM PDT 24
Finished Jun 26 05:21:48 PM PDT 24
Peak memory 206124 kb
Host smart-f7a4ff74-c1c0-4b24-908a-d9b1365f0bfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28351
78870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.2835178870
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.931843346
Short name T177
Test name
Test status
Simulation time 1218361313 ps
CPU time 2.67 seconds
Started Jun 26 05:21:45 PM PDT 24
Finished Jun 26 05:21:52 PM PDT 24
Peak memory 206508 kb
Host smart-5662d3ce-654d-478a-a586-113bd7eb41d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93184
3346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.931843346
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.3257273500
Short name T1182
Test name
Test status
Simulation time 16118869021 ps
CPU time 30.12 seconds
Started Jun 26 05:21:45 PM PDT 24
Finished Jun 26 05:22:19 PM PDT 24
Peak memory 206600 kb
Host smart-78d7ffe0-4574-42df-a9a1-69325ff8250c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32572
73500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.3257273500
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.174613551
Short name T849
Test name
Test status
Simulation time 478169919 ps
CPU time 1.53 seconds
Started Jun 26 05:21:46 PM PDT 24
Finished Jun 26 05:21:51 PM PDT 24
Peak memory 206252 kb
Host smart-5c1f1a1c-df72-4022-ac3b-ba86f5265bc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17461
3551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.174613551
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.4147819769
Short name T1721
Test name
Test status
Simulation time 146392775 ps
CPU time 0.85 seconds
Started Jun 26 05:21:45 PM PDT 24
Finished Jun 26 05:21:50 PM PDT 24
Peak memory 206196 kb
Host smart-be19e7f4-e083-456a-97cb-4781847a7f64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41478
19769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.4147819769
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.582132012
Short name T2350
Test name
Test status
Simulation time 61922740 ps
CPU time 0.67 seconds
Started Jun 26 05:21:42 PM PDT 24
Finished Jun 26 05:21:47 PM PDT 24
Peak memory 206148 kb
Host smart-e1fe67a3-6b5a-4d80-872b-cdbe3b8f4f85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58213
2012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.582132012
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.1884407767
Short name T474
Test name
Test status
Simulation time 855249276 ps
CPU time 1.91 seconds
Started Jun 26 05:21:45 PM PDT 24
Finished Jun 26 05:21:51 PM PDT 24
Peak memory 206404 kb
Host smart-6f519905-1c7d-4a31-8cd4-c6278d0a444d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18844
07767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.1884407767
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.4092633898
Short name T641
Test name
Test status
Simulation time 320995641 ps
CPU time 2.07 seconds
Started Jun 26 05:21:44 PM PDT 24
Finished Jun 26 05:21:50 PM PDT 24
Peak memory 206424 kb
Host smart-43cfc6bf-3fe6-48b5-bf5e-4bb6582ec14b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40926
33898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.4092633898
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.299939627
Short name T861
Test name
Test status
Simulation time 269523022 ps
CPU time 0.92 seconds
Started Jun 26 05:21:54 PM PDT 24
Finished Jun 26 05:21:58 PM PDT 24
Peak memory 205724 kb
Host smart-2981dd91-be5f-43d1-98fe-8f05aef40747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29993
9627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.299939627
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.475121324
Short name T690
Test name
Test status
Simulation time 132659912 ps
CPU time 0.75 seconds
Started Jun 26 05:22:07 PM PDT 24
Finished Jun 26 05:22:12 PM PDT 24
Peak memory 206180 kb
Host smart-e8523ab8-813e-4234-98e4-f58bac044c62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47512
1324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.475121324
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.1090147727
Short name T608
Test name
Test status
Simulation time 205674462 ps
CPU time 0.88 seconds
Started Jun 26 05:21:43 PM PDT 24
Finished Jun 26 05:21:48 PM PDT 24
Peak memory 206188 kb
Host smart-f2bee5c0-af2e-4876-a4c8-24f1ebb8a9bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10901
47727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.1090147727
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_invalid_sync.3409677274
Short name T224
Test name
Test status
Simulation time 9054107132 ps
CPU time 66.92 seconds
Started Jun 26 05:21:44 PM PDT 24
Finished Jun 26 05:22:55 PM PDT 24
Peak memory 206448 kb
Host smart-67ef9802-0374-4ee0-a504-5e614bd5214d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3409677274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.3409677274
Directory /workspace/47.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.2936576664
Short name T2542
Test name
Test status
Simulation time 268486721 ps
CPU time 0.9 seconds
Started Jun 26 05:21:44 PM PDT 24
Finished Jun 26 05:21:49 PM PDT 24
Peak memory 206116 kb
Host smart-eff2641c-ed08-4251-8104-56e89937a953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29365
76664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.2936576664
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.2596850204
Short name T357
Test name
Test status
Simulation time 23282928342 ps
CPU time 27.79 seconds
Started Jun 26 05:21:42 PM PDT 24
Finished Jun 26 05:22:14 PM PDT 24
Peak memory 206308 kb
Host smart-37d1899e-940c-4591-90d3-e7767d21e8b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25968
50204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.2596850204
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.2302888208
Short name T2124
Test name
Test status
Simulation time 3324955160 ps
CPU time 3.78 seconds
Started Jun 26 05:21:44 PM PDT 24
Finished Jun 26 05:21:52 PM PDT 24
Peak memory 206244 kb
Host smart-2421a865-678a-4f06-a9c0-e716557e860d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23028
88208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.2302888208
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.638965386
Short name T860
Test name
Test status
Simulation time 11679623226 ps
CPU time 110.73 seconds
Started Jun 26 05:21:43 PM PDT 24
Finished Jun 26 05:23:37 PM PDT 24
Peak memory 206468 kb
Host smart-5d449c07-48db-47c3-9e5a-8035113af4ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63896
5386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.638965386
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.768408492
Short name T1657
Test name
Test status
Simulation time 5089747670 ps
CPU time 137.81 seconds
Started Jun 26 05:21:42 PM PDT 24
Finished Jun 26 05:24:04 PM PDT 24
Peak memory 206552 kb
Host smart-bc52ca5f-3d00-4a36-81e4-5ac85e2eeba2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=768408492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.768408492
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.2329528553
Short name T2537
Test name
Test status
Simulation time 248629992 ps
CPU time 0.97 seconds
Started Jun 26 05:21:51 PM PDT 24
Finished Jun 26 05:21:54 PM PDT 24
Peak memory 206416 kb
Host smart-b0750590-9b25-4e69-95ad-446a7014fd1b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2329528553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.2329528553
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.2816728845
Short name T589
Test name
Test status
Simulation time 195139913 ps
CPU time 0.84 seconds
Started Jun 26 05:21:44 PM PDT 24
Finished Jun 26 05:21:50 PM PDT 24
Peak memory 206120 kb
Host smart-1c84d26b-f556-4bce-acd2-fa0cb3f1a261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28167
28845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.2816728845
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.59570489
Short name T1193
Test name
Test status
Simulation time 6100459310 ps
CPU time 55.17 seconds
Started Jun 26 05:21:43 PM PDT 24
Finished Jun 26 05:22:42 PM PDT 24
Peak memory 206532 kb
Host smart-6446297b-1489-42fe-a64d-48718071861a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59570
489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.59570489
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.4287145898
Short name T2513
Test name
Test status
Simulation time 7632841955 ps
CPU time 217.06 seconds
Started Jun 26 05:21:42 PM PDT 24
Finished Jun 26 05:25:23 PM PDT 24
Peak memory 206460 kb
Host smart-23499502-21b7-4848-b34a-0aeb08dcdf6e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4287145898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.4287145898
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.3080080012
Short name T2122
Test name
Test status
Simulation time 156464250 ps
CPU time 0.78 seconds
Started Jun 26 05:21:50 PM PDT 24
Finished Jun 26 05:21:53 PM PDT 24
Peak memory 206228 kb
Host smart-7958e2a5-c33a-4edc-a786-a2329891f171
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3080080012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.3080080012
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.3696462524
Short name T221
Test name
Test status
Simulation time 166975902 ps
CPU time 0.8 seconds
Started Jun 26 05:21:43 PM PDT 24
Finished Jun 26 05:21:48 PM PDT 24
Peak memory 206180 kb
Host smart-858590ab-3636-4b64-9adb-26a6a6cee481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36964
62524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.3696462524
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.24874826
Short name T139
Test name
Test status
Simulation time 219139560 ps
CPU time 0.83 seconds
Started Jun 26 05:21:44 PM PDT 24
Finished Jun 26 05:21:49 PM PDT 24
Peak memory 206220 kb
Host smart-991e35f3-51d0-4259-b264-55481eac47a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24874
826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.24874826
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.374130783
Short name T2129
Test name
Test status
Simulation time 163183149 ps
CPU time 0.8 seconds
Started Jun 26 05:21:44 PM PDT 24
Finished Jun 26 05:21:49 PM PDT 24
Peak memory 206148 kb
Host smart-e4435ebb-ddef-4cf4-8e81-bfa42ae5ee36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37413
0783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.374130783
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.3627038266
Short name T2562
Test name
Test status
Simulation time 173649342 ps
CPU time 0.85 seconds
Started Jun 26 05:21:50 PM PDT 24
Finished Jun 26 05:21:53 PM PDT 24
Peak memory 206208 kb
Host smart-dc64365a-20c0-46d0-86cb-65517dd3618d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36270
38266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.3627038266
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.3138002582
Short name T2151
Test name
Test status
Simulation time 166023231 ps
CPU time 0.81 seconds
Started Jun 26 05:21:50 PM PDT 24
Finished Jun 26 05:21:54 PM PDT 24
Peak memory 206128 kb
Host smart-3988be06-ac8a-4d86-b352-3e88ab9619f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31380
02582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.3138002582
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.166817242
Short name T2556
Test name
Test status
Simulation time 154551357 ps
CPU time 0.77 seconds
Started Jun 26 05:21:48 PM PDT 24
Finished Jun 26 05:21:51 PM PDT 24
Peak memory 206152 kb
Host smart-917f61b3-f18d-4e47-a38c-34192125d0fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16681
7242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.166817242
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.3629891734
Short name T1561
Test name
Test status
Simulation time 264983851 ps
CPU time 1.01 seconds
Started Jun 26 05:21:50 PM PDT 24
Finished Jun 26 05:21:53 PM PDT 24
Peak memory 206100 kb
Host smart-3661db8d-b299-4284-999e-fd4958fd70d9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3629891734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.3629891734
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.1775371453
Short name T1142
Test name
Test status
Simulation time 150416393 ps
CPU time 0.77 seconds
Started Jun 26 05:21:57 PM PDT 24
Finished Jun 26 05:22:01 PM PDT 24
Peak memory 206196 kb
Host smart-23ff12ca-376c-4015-ad3b-ebbd2198b47f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17753
71453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.1775371453
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.1632420948
Short name T29
Test name
Test status
Simulation time 36496950 ps
CPU time 0.66 seconds
Started Jun 26 05:21:51 PM PDT 24
Finished Jun 26 05:21:55 PM PDT 24
Peak memory 205624 kb
Host smart-d668184b-5783-4ec0-9a9d-50ec8dd8e636
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16324
20948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.1632420948
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.3411106390
Short name T2398
Test name
Test status
Simulation time 18110722823 ps
CPU time 45.88 seconds
Started Jun 26 05:21:50 PM PDT 24
Finished Jun 26 05:22:37 PM PDT 24
Peak memory 206592 kb
Host smart-5a797875-dc23-46ae-b149-9bcbe6fa3d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34111
06390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.3411106390
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.3068370739
Short name T594
Test name
Test status
Simulation time 176578999 ps
CPU time 0.93 seconds
Started Jun 26 05:21:54 PM PDT 24
Finished Jun 26 05:21:59 PM PDT 24
Peak memory 206208 kb
Host smart-6f3d9c56-397c-4aa5-bfe4-97f0553846a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30683
70739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.3068370739
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.2578634519
Short name T2198
Test name
Test status
Simulation time 171238134 ps
CPU time 0.81 seconds
Started Jun 26 05:21:54 PM PDT 24
Finished Jun 26 05:21:59 PM PDT 24
Peak memory 206216 kb
Host smart-b906b3af-8cab-4bcf-ba10-1b7d34096a09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25786
34519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.2578634519
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.3116893876
Short name T815
Test name
Test status
Simulation time 220180802 ps
CPU time 0.84 seconds
Started Jun 26 05:21:52 PM PDT 24
Finished Jun 26 05:21:56 PM PDT 24
Peak memory 206196 kb
Host smart-66a6aed3-95fb-4ac1-ae8d-be4922b1219d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31168
93876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.3116893876
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.2689701614
Short name T1955
Test name
Test status
Simulation time 215023768 ps
CPU time 0.88 seconds
Started Jun 26 05:21:49 PM PDT 24
Finished Jun 26 05:21:52 PM PDT 24
Peak memory 206212 kb
Host smart-8788fd0f-1a10-4bbf-acb4-424c26bf047c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26897
01614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.2689701614
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.2107502350
Short name T1569
Test name
Test status
Simulation time 148271960 ps
CPU time 0.76 seconds
Started Jun 26 05:21:54 PM PDT 24
Finished Jun 26 05:21:58 PM PDT 24
Peak memory 206124 kb
Host smart-68d4d841-30d2-41d8-bca1-56130d3455ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21075
02350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.2107502350
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.1677822897
Short name T751
Test name
Test status
Simulation time 155509690 ps
CPU time 0.81 seconds
Started Jun 26 05:21:51 PM PDT 24
Finished Jun 26 05:21:55 PM PDT 24
Peak memory 206168 kb
Host smart-bf798731-df36-44b4-aa43-0030d4eda672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16778
22897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.1677822897
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.3704134347
Short name T958
Test name
Test status
Simulation time 180128281 ps
CPU time 0.83 seconds
Started Jun 26 05:21:53 PM PDT 24
Finished Jun 26 05:21:58 PM PDT 24
Peak memory 206140 kb
Host smart-189f025e-dc89-48cc-9c3b-10f1e56522a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37041
34347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.3704134347
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.3846256249
Short name T2340
Test name
Test status
Simulation time 243786098 ps
CPU time 0.98 seconds
Started Jun 26 05:21:50 PM PDT 24
Finished Jun 26 05:21:52 PM PDT 24
Peak memory 206184 kb
Host smart-da1f07c9-f547-40a3-b446-c131e151f135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38462
56249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.3846256249
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.2849145394
Short name T602
Test name
Test status
Simulation time 3926272694 ps
CPU time 103.12 seconds
Started Jun 26 05:21:52 PM PDT 24
Finished Jun 26 05:23:39 PM PDT 24
Peak memory 206448 kb
Host smart-6348fdd5-f33b-4094-bbd7-69b24b33bb36
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2849145394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.2849145394
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.1835736095
Short name T355
Test name
Test status
Simulation time 187080522 ps
CPU time 0.85 seconds
Started Jun 26 05:21:51 PM PDT 24
Finished Jun 26 05:21:54 PM PDT 24
Peak memory 206116 kb
Host smart-c507e2f6-b5f8-4191-81e4-9f2d5f358beb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18357
36095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.1835736095
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.205558218
Short name T729
Test name
Test status
Simulation time 206187314 ps
CPU time 0.88 seconds
Started Jun 26 05:21:49 PM PDT 24
Finished Jun 26 05:21:52 PM PDT 24
Peak memory 206208 kb
Host smart-91dcf140-e92f-4e90-8600-c4105bad8023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20555
8218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.205558218
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.543679618
Short name T932
Test name
Test status
Simulation time 6135760676 ps
CPU time 41.92 seconds
Started Jun 26 05:21:54 PM PDT 24
Finished Jun 26 05:22:40 PM PDT 24
Peak memory 206568 kb
Host smart-b59e2d25-1c87-4214-9ff1-183689496f1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54367
9618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.543679618
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.673711689
Short name T2266
Test name
Test status
Simulation time 4318387747 ps
CPU time 4.46 seconds
Started Jun 26 05:21:53 PM PDT 24
Finished Jun 26 05:22:01 PM PDT 24
Peak memory 206440 kb
Host smart-35405603-4969-4e2c-832b-0c99b776ab63
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=673711689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.673711689
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.4286273770
Short name T2101
Test name
Test status
Simulation time 13382422806 ps
CPU time 13.82 seconds
Started Jun 26 05:21:51 PM PDT 24
Finished Jun 26 05:22:08 PM PDT 24
Peak memory 206296 kb
Host smart-93df59ca-1a1f-4e71-b48a-9edd888d2a98
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4286273770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.4286273770
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.4271213105
Short name T520
Test name
Test status
Simulation time 23303097539 ps
CPU time 22.61 seconds
Started Jun 26 05:21:52 PM PDT 24
Finished Jun 26 05:22:19 PM PDT 24
Peak memory 206308 kb
Host smart-a519f203-a1ea-4014-8d3c-f35e392303a0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4271213105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.4271213105
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.1669756093
Short name T1352
Test name
Test status
Simulation time 170468235 ps
CPU time 0.88 seconds
Started Jun 26 05:21:53 PM PDT 24
Finished Jun 26 05:21:57 PM PDT 24
Peak memory 206224 kb
Host smart-d3bf386e-ffb4-441f-abf9-938b5f54832e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16697
56093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.1669756093
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.2835172475
Short name T1425
Test name
Test status
Simulation time 145412764 ps
CPU time 0.82 seconds
Started Jun 26 05:21:56 PM PDT 24
Finished Jun 26 05:22:00 PM PDT 24
Peak memory 206196 kb
Host smart-9ebd1aa4-f888-488c-bf78-a69dba38939e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28351
72475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.2835172475
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.2312643871
Short name T106
Test name
Test status
Simulation time 260881271 ps
CPU time 0.97 seconds
Started Jun 26 05:21:51 PM PDT 24
Finished Jun 26 05:21:55 PM PDT 24
Peak memory 206096 kb
Host smart-7068570c-3f11-4536-970d-e6536ea2d7f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23126
43871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.2312643871
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.2655215901
Short name T1081
Test name
Test status
Simulation time 1190476704 ps
CPU time 2.61 seconds
Started Jun 26 05:21:51 PM PDT 24
Finished Jun 26 05:21:57 PM PDT 24
Peak memory 206316 kb
Host smart-b2333c9e-226e-4ce8-a99e-75b07bf1d57c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26552
15901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.2655215901
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.434882650
Short name T188
Test name
Test status
Simulation time 16489804263 ps
CPU time 29.88 seconds
Started Jun 26 05:21:56 PM PDT 24
Finished Jun 26 05:22:29 PM PDT 24
Peak memory 206500 kb
Host smart-ce9dc4d0-e97b-4a67-9b53-9bdd10f109fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43488
2650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.434882650
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.1431050791
Short name T514
Test name
Test status
Simulation time 519306580 ps
CPU time 1.5 seconds
Started Jun 26 05:21:51 PM PDT 24
Finished Jun 26 05:21:55 PM PDT 24
Peak memory 206124 kb
Host smart-5c6aeb76-ccbe-4494-915f-a59ff044d4b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14310
50791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.1431050791
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.2315578077
Short name T906
Test name
Test status
Simulation time 156170250 ps
CPU time 0.78 seconds
Started Jun 26 05:21:51 PM PDT 24
Finished Jun 26 05:21:54 PM PDT 24
Peak memory 206200 kb
Host smart-bcacf048-cbe4-40ea-85ea-617584024cb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23155
78077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.2315578077
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.1040920200
Short name T1774
Test name
Test status
Simulation time 44827096 ps
CPU time 0.65 seconds
Started Jun 26 05:21:55 PM PDT 24
Finished Jun 26 05:21:59 PM PDT 24
Peak memory 206232 kb
Host smart-29e4a308-3d09-4f3c-ac8d-37d4bb3a0ee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10409
20200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.1040920200
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.2217135957
Short name T558
Test name
Test status
Simulation time 849806260 ps
CPU time 1.97 seconds
Started Jun 26 05:21:54 PM PDT 24
Finished Jun 26 05:21:59 PM PDT 24
Peak memory 205952 kb
Host smart-404f67b7-fb6b-4e98-ba12-4e11c4761b9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22171
35957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.2217135957
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.3056796900
Short name T1661
Test name
Test status
Simulation time 287460414 ps
CPU time 1.51 seconds
Started Jun 26 05:21:51 PM PDT 24
Finished Jun 26 05:21:56 PM PDT 24
Peak memory 206420 kb
Host smart-816c6947-6b45-4e67-9325-9664f0dc030f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30567
96900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.3056796900
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.554698640
Short name T403
Test name
Test status
Simulation time 236062942 ps
CPU time 0.88 seconds
Started Jun 26 05:21:58 PM PDT 24
Finished Jun 26 05:22:02 PM PDT 24
Peak memory 206148 kb
Host smart-e40bcb36-05e2-4f5d-9623-2ca1ced21ca4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55469
8640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.554698640
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.1645856049
Short name T547
Test name
Test status
Simulation time 160766028 ps
CPU time 0.82 seconds
Started Jun 26 05:21:57 PM PDT 24
Finished Jun 26 05:22:01 PM PDT 24
Peak memory 206184 kb
Host smart-e749a7b8-bdfa-4add-947c-53555b006387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16458
56049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.1645856049
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.1126048185
Short name T1968
Test name
Test status
Simulation time 239133790 ps
CPU time 0.89 seconds
Started Jun 26 05:21:51 PM PDT 24
Finished Jun 26 05:21:54 PM PDT 24
Peak memory 206224 kb
Host smart-490f3851-9ba5-4db9-90c0-4130d0ee8bab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11260
48185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.1126048185
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.1802239409
Short name T799
Test name
Test status
Simulation time 198475481 ps
CPU time 0.83 seconds
Started Jun 26 05:21:52 PM PDT 24
Finished Jun 26 05:21:56 PM PDT 24
Peak memory 206184 kb
Host smart-8623b615-2e8e-4ec6-a565-854b433413eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18022
39409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.1802239409
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.3106816433
Short name T543
Test name
Test status
Simulation time 23293762698 ps
CPU time 25.42 seconds
Started Jun 26 05:21:51 PM PDT 24
Finished Jun 26 05:22:20 PM PDT 24
Peak memory 205724 kb
Host smart-b27577ce-1b85-465b-a804-c7fae48eaed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31068
16433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.3106816433
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.1405530958
Short name T352
Test name
Test status
Simulation time 3332854154 ps
CPU time 3.84 seconds
Started Jun 26 05:21:50 PM PDT 24
Finished Jun 26 05:21:56 PM PDT 24
Peak memory 206252 kb
Host smart-c389e712-d03b-438b-a9a9-d9c62fdb7925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14055
30958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.1405530958
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.1118308030
Short name T1700
Test name
Test status
Simulation time 8016944704 ps
CPU time 55.55 seconds
Started Jun 26 05:21:51 PM PDT 24
Finished Jun 26 05:22:50 PM PDT 24
Peak memory 206548 kb
Host smart-e8b0bc84-d462-4bdf-8348-f8ecf9569517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11183
08030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.1118308030
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.2812455533
Short name T735
Test name
Test status
Simulation time 4964983039 ps
CPU time 32.98 seconds
Started Jun 26 05:21:53 PM PDT 24
Finished Jun 26 05:22:30 PM PDT 24
Peak memory 206452 kb
Host smart-76920bd2-0840-441d-a32a-c85a8c5fb0e5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2812455533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.2812455533
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.2492013048
Short name T555
Test name
Test status
Simulation time 234333395 ps
CPU time 0.88 seconds
Started Jun 26 05:22:00 PM PDT 24
Finished Jun 26 05:22:05 PM PDT 24
Peak memory 206116 kb
Host smart-5a58d006-0c10-4be5-938c-9daf6906440a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2492013048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.2492013048
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.889503904
Short name T1768
Test name
Test status
Simulation time 183205690 ps
CPU time 0.84 seconds
Started Jun 26 05:21:54 PM PDT 24
Finished Jun 26 05:21:58 PM PDT 24
Peak memory 206136 kb
Host smart-d218b5d3-8281-445e-82b6-f5658091dfcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88950
3904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.889503904
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.519908930
Short name T2294
Test name
Test status
Simulation time 4893267116 ps
CPU time 46.38 seconds
Started Jun 26 05:21:53 PM PDT 24
Finished Jun 26 05:22:43 PM PDT 24
Peak memory 206444 kb
Host smart-63b1b82a-b03c-48ed-950c-a538ce2af6ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51990
8930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.519908930
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.94962770
Short name T962
Test name
Test status
Simulation time 3703746515 ps
CPU time 36.09 seconds
Started Jun 26 05:21:51 PM PDT 24
Finished Jun 26 05:22:30 PM PDT 24
Peak memory 206436 kb
Host smart-050162af-4a4c-416f-ae5c-53724f83e0ee
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=94962770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.94962770
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.2541313196
Short name T332
Test name
Test status
Simulation time 150204650 ps
CPU time 0.79 seconds
Started Jun 26 05:21:58 PM PDT 24
Finished Jun 26 05:22:03 PM PDT 24
Peak memory 206228 kb
Host smart-0b086dbf-1965-42b8-ad85-2faf4bd6606b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2541313196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.2541313196
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.102763588
Short name T1983
Test name
Test status
Simulation time 216372804 ps
CPU time 0.85 seconds
Started Jun 26 05:21:52 PM PDT 24
Finished Jun 26 05:21:56 PM PDT 24
Peak memory 206132 kb
Host smart-5ff91e00-4923-4212-b1ca-50d9fb91ec2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10276
3588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.102763588
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.346923035
Short name T1594
Test name
Test status
Simulation time 234410690 ps
CPU time 0.88 seconds
Started Jun 26 05:21:51 PM PDT 24
Finished Jun 26 05:21:54 PM PDT 24
Peak memory 206192 kb
Host smart-24e7e301-9b72-493d-be90-7b3b6a2f88b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34692
3035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.346923035
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.4116374410
Short name T914
Test name
Test status
Simulation time 156574547 ps
CPU time 0.76 seconds
Started Jun 26 05:21:50 PM PDT 24
Finished Jun 26 05:21:53 PM PDT 24
Peak memory 206140 kb
Host smart-736419f1-26ca-4af4-88c5-c2765290fccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41163
74410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.4116374410
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.3423423587
Short name T1417
Test name
Test status
Simulation time 198403100 ps
CPU time 0.84 seconds
Started Jun 26 05:21:54 PM PDT 24
Finished Jun 26 05:21:59 PM PDT 24
Peak memory 206224 kb
Host smart-655c3029-0172-4f4c-a313-c4e49d96e0ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34234
23587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.3423423587
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.761067171
Short name T2408
Test name
Test status
Simulation time 185398752 ps
CPU time 0.84 seconds
Started Jun 26 05:21:51 PM PDT 24
Finished Jun 26 05:21:55 PM PDT 24
Peak memory 206172 kb
Host smart-4b442141-395b-42ff-bc11-c9ed9c81b87d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76106
7171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.761067171
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.1707448913
Short name T968
Test name
Test status
Simulation time 157272390 ps
CPU time 0.83 seconds
Started Jun 26 05:21:58 PM PDT 24
Finished Jun 26 05:22:02 PM PDT 24
Peak memory 206176 kb
Host smart-389e7f48-7476-417a-b1a2-a71efb7104a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17074
48913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.1707448913
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.1067755752
Short name T1565
Test name
Test status
Simulation time 207401226 ps
CPU time 0.86 seconds
Started Jun 26 05:21:53 PM PDT 24
Finished Jun 26 05:21:58 PM PDT 24
Peak memory 206144 kb
Host smart-19e1bb39-6ca5-4d56-b587-6f7b41dbcc94
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1067755752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.1067755752
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.3130006307
Short name T1351
Test name
Test status
Simulation time 138382892 ps
CPU time 0.77 seconds
Started Jun 26 05:22:02 PM PDT 24
Finished Jun 26 05:22:07 PM PDT 24
Peak memory 206212 kb
Host smart-55669959-e67d-49c2-8a04-c21a78787a46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31300
06307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.3130006307
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.910323382
Short name T2227
Test name
Test status
Simulation time 46143219 ps
CPU time 0.67 seconds
Started Jun 26 05:22:02 PM PDT 24
Finished Jun 26 05:22:06 PM PDT 24
Peak memory 206120 kb
Host smart-301ca102-8722-4926-8e4c-66e438a3e9ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91032
3382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.910323382
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.3788074341
Short name T262
Test name
Test status
Simulation time 20998042192 ps
CPU time 45.88 seconds
Started Jun 26 05:22:00 PM PDT 24
Finished Jun 26 05:22:50 PM PDT 24
Peak memory 206512 kb
Host smart-5a9566b0-5e46-487a-922d-dde3bcde06b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37880
74341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.3788074341
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.3301259901
Short name T2013
Test name
Test status
Simulation time 157426370 ps
CPU time 0.79 seconds
Started Jun 26 05:21:58 PM PDT 24
Finished Jun 26 05:22:02 PM PDT 24
Peak memory 206200 kb
Host smart-a232372e-38d8-4cb2-8010-f04a821c1892
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33012
59901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.3301259901
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.3083470518
Short name T1228
Test name
Test status
Simulation time 264225752 ps
CPU time 0.89 seconds
Started Jun 26 05:21:59 PM PDT 24
Finished Jun 26 05:22:04 PM PDT 24
Peak memory 206140 kb
Host smart-04d876f0-d468-4b4d-81e8-9f7b09f6d681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30834
70518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.3083470518
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.1508697544
Short name T1479
Test name
Test status
Simulation time 234116992 ps
CPU time 0.93 seconds
Started Jun 26 05:21:59 PM PDT 24
Finished Jun 26 05:22:04 PM PDT 24
Peak memory 206200 kb
Host smart-97e82a78-2daa-4007-b9f0-9fea10614da2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15086
97544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.1508697544
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.3376609421
Short name T1068
Test name
Test status
Simulation time 169000295 ps
CPU time 0.79 seconds
Started Jun 26 05:21:59 PM PDT 24
Finished Jun 26 05:22:04 PM PDT 24
Peak memory 206120 kb
Host smart-5e3e8fad-424d-490b-96c7-6fb70819709b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33766
09421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.3376609421
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.339794349
Short name T2251
Test name
Test status
Simulation time 255247881 ps
CPU time 0.84 seconds
Started Jun 26 05:22:00 PM PDT 24
Finished Jun 26 05:22:05 PM PDT 24
Peak memory 206100 kb
Host smart-c9a95dc4-937f-43b9-bfbf-9c29bb4de099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33979
4349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.339794349
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.3774170315
Short name T428
Test name
Test status
Simulation time 159416001 ps
CPU time 0.78 seconds
Started Jun 26 05:21:59 PM PDT 24
Finished Jun 26 05:22:04 PM PDT 24
Peak memory 206204 kb
Host smart-b6ca797d-5a8e-40e2-a737-f976ddb85b51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37741
70315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.3774170315
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.33059706
Short name T508
Test name
Test status
Simulation time 185431879 ps
CPU time 0.79 seconds
Started Jun 26 05:21:58 PM PDT 24
Finished Jun 26 05:22:03 PM PDT 24
Peak memory 206192 kb
Host smart-9402472a-d9e4-446e-af3f-4c07c3c19fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33059
706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.33059706
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.248290055
Short name T1381
Test name
Test status
Simulation time 208914546 ps
CPU time 0.91 seconds
Started Jun 26 05:21:59 PM PDT 24
Finished Jun 26 05:22:03 PM PDT 24
Peak memory 206144 kb
Host smart-d895bf13-bb95-44a4-9af8-0768b163b133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24829
0055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.248290055
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.4030774473
Short name T1378
Test name
Test status
Simulation time 4750606745 ps
CPU time 34.76 seconds
Started Jun 26 05:22:03 PM PDT 24
Finished Jun 26 05:22:41 PM PDT 24
Peak memory 206428 kb
Host smart-66751749-5aab-40ac-830b-057340e43403
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4030774473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.4030774473
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.2863348614
Short name T151
Test name
Test status
Simulation time 213148028 ps
CPU time 0.9 seconds
Started Jun 26 05:21:58 PM PDT 24
Finished Jun 26 05:22:03 PM PDT 24
Peak memory 206188 kb
Host smart-67e96a32-3a88-4e72-a60c-5e5b8e7e5bcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28633
48614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.2863348614
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.444186795
Short name T2232
Test name
Test status
Simulation time 199888843 ps
CPU time 0.86 seconds
Started Jun 26 05:21:59 PM PDT 24
Finished Jun 26 05:22:04 PM PDT 24
Peak memory 206124 kb
Host smart-b89f7240-c001-4b98-a8b7-56dacc20bf68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44418
6795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.444186795
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.3867390168
Short name T1620
Test name
Test status
Simulation time 3388421591 ps
CPU time 91.56 seconds
Started Jun 26 05:21:57 PM PDT 24
Finished Jun 26 05:23:32 PM PDT 24
Peak memory 206464 kb
Host smart-5a1c89d9-bcfc-4569-8496-ea2e37606580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38673
90168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.3867390168
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.2177286588
Short name T13
Test name
Test status
Simulation time 3693408824 ps
CPU time 4.29 seconds
Started Jun 26 05:21:59 PM PDT 24
Finished Jun 26 05:22:07 PM PDT 24
Peak memory 206460 kb
Host smart-d5526723-c5c3-4ff9-9d9b-7e8081b7898e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2177286588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.2177286588
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.968871819
Short name T2536
Test name
Test status
Simulation time 13390050336 ps
CPU time 15.98 seconds
Started Jun 26 05:21:58 PM PDT 24
Finished Jun 26 05:22:17 PM PDT 24
Peak memory 206440 kb
Host smart-6d032020-8d5f-45d4-bae7-985f590fe3f8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=968871819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.968871819
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.896223280
Short name T2146
Test name
Test status
Simulation time 23366459337 ps
CPU time 20.7 seconds
Started Jun 26 05:21:58 PM PDT 24
Finished Jun 26 05:22:22 PM PDT 24
Peak memory 206460 kb
Host smart-fafb7260-f56d-42a7-aa0a-48c00c6914c2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=896223280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.896223280
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.1497324899
Short name T160
Test name
Test status
Simulation time 185847128 ps
CPU time 0.85 seconds
Started Jun 26 05:22:01 PM PDT 24
Finished Jun 26 05:22:06 PM PDT 24
Peak memory 206204 kb
Host smart-b50d87fa-fa7d-4390-8866-434709403ab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14973
24899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.1497324899
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.3862733438
Short name T1139
Test name
Test status
Simulation time 163387292 ps
CPU time 0.82 seconds
Started Jun 26 05:22:01 PM PDT 24
Finished Jun 26 05:22:06 PM PDT 24
Peak memory 206204 kb
Host smart-cd79261f-5b29-4eba-b483-3f465822720a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38627
33438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.3862733438
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.99156703
Short name T171
Test name
Test status
Simulation time 606100644 ps
CPU time 1.73 seconds
Started Jun 26 05:22:01 PM PDT 24
Finished Jun 26 05:22:07 PM PDT 24
Peak memory 206384 kb
Host smart-7389e57b-e8fb-4923-890d-a664e6e94c30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99156
703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.99156703
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.3106554950
Short name T870
Test name
Test status
Simulation time 845837305 ps
CPU time 1.9 seconds
Started Jun 26 05:22:00 PM PDT 24
Finished Jun 26 05:22:06 PM PDT 24
Peak memory 206384 kb
Host smart-746f647d-0c77-4845-bd6b-3bcff5c61cbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31065
54950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.3106554950
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.3726704374
Short name T2439
Test name
Test status
Simulation time 6744575204 ps
CPU time 12.38 seconds
Started Jun 26 05:22:00 PM PDT 24
Finished Jun 26 05:22:16 PM PDT 24
Peak memory 206532 kb
Host smart-2973a3ba-228d-48e3-a9c5-ae975888a481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37267
04374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.3726704374
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.1693363272
Short name T1074
Test name
Test status
Simulation time 399417495 ps
CPU time 1.34 seconds
Started Jun 26 05:22:01 PM PDT 24
Finished Jun 26 05:22:06 PM PDT 24
Peak memory 206204 kb
Host smart-b9aa02f5-091e-4e5e-b64e-67c872dd812e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16933
63272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.1693363272
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.3759112353
Short name T477
Test name
Test status
Simulation time 138911177 ps
CPU time 0.77 seconds
Started Jun 26 05:22:02 PM PDT 24
Finished Jun 26 05:22:06 PM PDT 24
Peak memory 206212 kb
Host smart-7b45beac-b9cf-4abd-a730-66b0d8c23aec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37591
12353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.3759112353
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.4251473512
Short name T2086
Test name
Test status
Simulation time 57750247 ps
CPU time 0.68 seconds
Started Jun 26 05:21:58 PM PDT 24
Finished Jun 26 05:22:03 PM PDT 24
Peak memory 206220 kb
Host smart-48931803-aee0-455a-ae57-bc3a51896a87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42514
73512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.4251473512
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.929668425
Short name T2171
Test name
Test status
Simulation time 1000078680 ps
CPU time 2.11 seconds
Started Jun 26 05:22:01 PM PDT 24
Finished Jun 26 05:22:07 PM PDT 24
Peak memory 206336 kb
Host smart-1de23186-4f3b-4dfb-bd1d-ead125f08db5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92966
8425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.929668425
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.3494463680
Short name T2180
Test name
Test status
Simulation time 292340422 ps
CPU time 2.03 seconds
Started Jun 26 05:21:58 PM PDT 24
Finished Jun 26 05:22:03 PM PDT 24
Peak memory 206456 kb
Host smart-8a6e2870-f036-49e5-ae06-1f683c63f794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34944
63680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.3494463680
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.1189045444
Short name T2248
Test name
Test status
Simulation time 164026530 ps
CPU time 0.83 seconds
Started Jun 26 05:22:04 PM PDT 24
Finished Jun 26 05:22:08 PM PDT 24
Peak memory 206096 kb
Host smart-c83b3d55-d1f9-4da1-b813-89d4c5125629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11890
45444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.1189045444
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.1114282723
Short name T567
Test name
Test status
Simulation time 191409565 ps
CPU time 0.8 seconds
Started Jun 26 05:22:09 PM PDT 24
Finished Jun 26 05:22:13 PM PDT 24
Peak memory 206224 kb
Host smart-26732ae4-4cf2-4e08-8b19-95173e1071e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11142
82723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.1114282723
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.2507288026
Short name T2506
Test name
Test status
Simulation time 220036009 ps
CPU time 0.9 seconds
Started Jun 26 05:22:02 PM PDT 24
Finished Jun 26 05:22:07 PM PDT 24
Peak memory 206140 kb
Host smart-f6ac8448-caf2-4de2-b584-fc996bde7431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25072
88026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.2507288026
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_invalid_sync.2022079391
Short name T1398
Test name
Test status
Simulation time 5849692156 ps
CPU time 162.15 seconds
Started Jun 26 05:21:59 PM PDT 24
Finished Jun 26 05:24:45 PM PDT 24
Peak memory 206548 kb
Host smart-318ff7f2-39c2-45cd-8bf9-dad361cfa442
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2022079391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.2022079391
Directory /workspace/49.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.1838274624
Short name T930
Test name
Test status
Simulation time 167674231 ps
CPU time 0.82 seconds
Started Jun 26 05:21:59 PM PDT 24
Finished Jun 26 05:22:03 PM PDT 24
Peak memory 206192 kb
Host smart-a5dbd8c4-8747-4a62-b1ec-0e2b76048c23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18382
74624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.1838274624
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.697012713
Short name T1392
Test name
Test status
Simulation time 23320418622 ps
CPU time 23.73 seconds
Started Jun 26 05:22:00 PM PDT 24
Finished Jun 26 05:22:28 PM PDT 24
Peak memory 206296 kb
Host smart-a12b5056-2dfc-40d4-84f4-e2e9815c2a23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69701
2713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.697012713
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.1865059853
Short name T2514
Test name
Test status
Simulation time 3336961126 ps
CPU time 3.55 seconds
Started Jun 26 05:21:58 PM PDT 24
Finished Jun 26 05:22:05 PM PDT 24
Peak memory 206252 kb
Host smart-15706baf-ed87-43b2-bc9d-3b3b8078afa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18650
59853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.1865059853
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.2640647764
Short name T1601
Test name
Test status
Simulation time 13095404195 ps
CPU time 93.55 seconds
Started Jun 26 05:21:59 PM PDT 24
Finished Jun 26 05:23:37 PM PDT 24
Peak memory 206504 kb
Host smart-137a7ff2-d259-47b8-b448-1caf5ed61c45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26406
47764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.2640647764
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.1858620173
Short name T1380
Test name
Test status
Simulation time 4536221188 ps
CPU time 33.56 seconds
Started Jun 26 05:21:58 PM PDT 24
Finished Jun 26 05:22:36 PM PDT 24
Peak memory 206576 kb
Host smart-2f65bbe5-a674-4863-89ec-8f466bbced56
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1858620173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.1858620173
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.3538052210
Short name T1896
Test name
Test status
Simulation time 274347182 ps
CPU time 0.97 seconds
Started Jun 26 05:22:06 PM PDT 24
Finished Jun 26 05:22:11 PM PDT 24
Peak memory 206148 kb
Host smart-a6202f83-5219-4816-89b5-cab5e2b7b232
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3538052210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.3538052210
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.3412013619
Short name T1394
Test name
Test status
Simulation time 199891687 ps
CPU time 0.86 seconds
Started Jun 26 05:21:59 PM PDT 24
Finished Jun 26 05:22:04 PM PDT 24
Peak memory 206184 kb
Host smart-f2e7fad9-4d83-4ba5-ab44-970a3d5aba8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34120
13619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.3412013619
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.1865422813
Short name T990
Test name
Test status
Simulation time 6051494962 ps
CPU time 42.54 seconds
Started Jun 26 05:22:02 PM PDT 24
Finished Jun 26 05:22:49 PM PDT 24
Peak memory 206516 kb
Host smart-502c198b-ba6b-4f16-9ffd-9526153d5425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18654
22813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.1865422813
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.1080663749
Short name T1474
Test name
Test status
Simulation time 5458300007 ps
CPU time 148.63 seconds
Started Jun 26 05:22:00 PM PDT 24
Finished Jun 26 05:24:32 PM PDT 24
Peak memory 206556 kb
Host smart-d4f7daf7-f85c-43e3-9d58-0d032168462a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1080663749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.1080663749
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.945690576
Short name T909
Test name
Test status
Simulation time 157314062 ps
CPU time 0.82 seconds
Started Jun 26 05:22:05 PM PDT 24
Finished Jun 26 05:22:10 PM PDT 24
Peak memory 206228 kb
Host smart-a19e2827-66a8-4720-b1f3-470ad7e174ce
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=945690576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.945690576
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.4250483309
Short name T922
Test name
Test status
Simulation time 159971912 ps
CPU time 0.8 seconds
Started Jun 26 05:21:57 PM PDT 24
Finished Jun 26 05:22:01 PM PDT 24
Peak memory 206168 kb
Host smart-684aff09-a349-4f5b-9585-d7266ca06900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42504
83309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.4250483309
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.2053315440
Short name T135
Test name
Test status
Simulation time 246238091 ps
CPU time 0.91 seconds
Started Jun 26 05:21:59 PM PDT 24
Finished Jun 26 05:22:03 PM PDT 24
Peak memory 206220 kb
Host smart-a4c1f210-fb0e-4812-80e2-48bee787de85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20533
15440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.2053315440
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.3519062306
Short name T2483
Test name
Test status
Simulation time 225401244 ps
CPU time 0.9 seconds
Started Jun 26 05:21:59 PM PDT 24
Finished Jun 26 05:22:03 PM PDT 24
Peak memory 206232 kb
Host smart-9a8955f6-adc1-47db-8e23-c97ea84e47e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35190
62306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.3519062306
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.4003090615
Short name T358
Test name
Test status
Simulation time 218255176 ps
CPU time 0.86 seconds
Started Jun 26 05:21:59 PM PDT 24
Finished Jun 26 05:22:04 PM PDT 24
Peak memory 206168 kb
Host smart-32a0c9ce-1ea2-4c4e-9753-70923431d966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40030
90615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.4003090615
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.2798102068
Short name T419
Test name
Test status
Simulation time 160139330 ps
CPU time 0.83 seconds
Started Jun 26 05:22:03 PM PDT 24
Finished Jun 26 05:22:07 PM PDT 24
Peak memory 206120 kb
Host smart-e0c194a9-91cd-44e1-bac6-f43a53b70ab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27981
02068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.2798102068
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.3984610884
Short name T2199
Test name
Test status
Simulation time 164464151 ps
CPU time 0.81 seconds
Started Jun 26 05:22:05 PM PDT 24
Finished Jun 26 05:22:10 PM PDT 24
Peak memory 206200 kb
Host smart-155b0f73-82c5-40fb-ae83-c3a10623f52a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39846
10884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.3984610884
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.1211971891
Short name T427
Test name
Test status
Simulation time 223739761 ps
CPU time 0.93 seconds
Started Jun 26 05:21:57 PM PDT 24
Finished Jun 26 05:22:01 PM PDT 24
Peak memory 206232 kb
Host smart-cd783d10-0954-4dd8-9b46-dfba04ad1987
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1211971891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.1211971891
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.3889783165
Short name T1170
Test name
Test status
Simulation time 148832205 ps
CPU time 0.74 seconds
Started Jun 26 05:22:04 PM PDT 24
Finished Jun 26 05:22:08 PM PDT 24
Peak memory 206204 kb
Host smart-b124c28d-6059-42d4-90ea-c903173e47ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38897
83165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.3889783165
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.4020142639
Short name T2561
Test name
Test status
Simulation time 47296657 ps
CPU time 0.67 seconds
Started Jun 26 05:22:04 PM PDT 24
Finished Jun 26 05:22:09 PM PDT 24
Peak memory 206116 kb
Host smart-56eb9156-5c1f-4498-85a2-01a02d393f36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40201
42639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.4020142639
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.211176124
Short name T1203
Test name
Test status
Simulation time 10862581569 ps
CPU time 22.46 seconds
Started Jun 26 05:22:09 PM PDT 24
Finished Jun 26 05:22:36 PM PDT 24
Peak memory 206548 kb
Host smart-bae525fd-4048-4d50-91b5-91e4ed2c63b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21117
6124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.211176124
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.2123897393
Short name T1430
Test name
Test status
Simulation time 179044316 ps
CPU time 0.92 seconds
Started Jun 26 05:22:03 PM PDT 24
Finished Jun 26 05:22:08 PM PDT 24
Peak memory 206124 kb
Host smart-d2007f98-7370-4265-8adf-0e6dcf9c980f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21238
97393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.2123897393
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.1132571579
Short name T772
Test name
Test status
Simulation time 184855870 ps
CPU time 0.8 seconds
Started Jun 26 05:22:06 PM PDT 24
Finished Jun 26 05:22:11 PM PDT 24
Peak memory 206140 kb
Host smart-34a980f8-a24b-4b84-9f0c-c28af738664e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11325
71579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.1132571579
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.1642203244
Short name T921
Test name
Test status
Simulation time 227034535 ps
CPU time 0.93 seconds
Started Jun 26 05:22:06 PM PDT 24
Finished Jun 26 05:22:11 PM PDT 24
Peak memory 206148 kb
Host smart-b8fb605b-0f88-436f-8878-cbf98c6b8e2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16422
03244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.1642203244
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.223131573
Short name T1580
Test name
Test status
Simulation time 155187552 ps
CPU time 0.76 seconds
Started Jun 26 05:22:04 PM PDT 24
Finished Jun 26 05:22:09 PM PDT 24
Peak memory 206168 kb
Host smart-0481d8e6-46f7-4f68-9ded-e707c18a8e7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22313
1573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.223131573
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.2932947367
Short name T1647
Test name
Test status
Simulation time 221354760 ps
CPU time 0.86 seconds
Started Jun 26 05:22:03 PM PDT 24
Finished Jun 26 05:22:08 PM PDT 24
Peak memory 206136 kb
Host smart-beff6a5e-b56a-46e2-947d-444b16f427b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29329
47367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.2932947367
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.1785499167
Short name T974
Test name
Test status
Simulation time 157491814 ps
CPU time 0.77 seconds
Started Jun 26 05:22:03 PM PDT 24
Finished Jun 26 05:22:08 PM PDT 24
Peak memory 206204 kb
Host smart-133d66aa-78f5-4804-8737-a65525d1d4b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17854
99167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.1785499167
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.2536829249
Short name T1784
Test name
Test status
Simulation time 206434626 ps
CPU time 0.83 seconds
Started Jun 26 05:22:03 PM PDT 24
Finished Jun 26 05:22:08 PM PDT 24
Peak memory 206212 kb
Host smart-45b15387-b85e-4e6f-b9c5-dda2569e87af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25368
29249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.2536829249
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.2452103303
Short name T2025
Test name
Test status
Simulation time 204701962 ps
CPU time 0.86 seconds
Started Jun 26 05:22:09 PM PDT 24
Finished Jun 26 05:22:13 PM PDT 24
Peak memory 206132 kb
Host smart-d0b913bf-ad2f-418e-835c-c060d79edbc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24521
03303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.2452103303
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.1753693958
Short name T2543
Test name
Test status
Simulation time 3543868884 ps
CPU time 23.37 seconds
Started Jun 26 05:22:04 PM PDT 24
Finished Jun 26 05:22:31 PM PDT 24
Peak memory 206460 kb
Host smart-deae336f-fa52-4618-82a4-d2e54955664a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1753693958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.1753693958
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.757913092
Short name T1270
Test name
Test status
Simulation time 157588444 ps
CPU time 0.79 seconds
Started Jun 26 05:22:06 PM PDT 24
Finished Jun 26 05:22:10 PM PDT 24
Peak memory 206100 kb
Host smart-d1ea2429-8254-4e35-ad0a-63b95a326ba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75791
3092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.757913092
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.1744121301
Short name T1991
Test name
Test status
Simulation time 230881185 ps
CPU time 0.93 seconds
Started Jun 26 05:22:04 PM PDT 24
Finished Jun 26 05:22:09 PM PDT 24
Peak memory 206204 kb
Host smart-c4986fd0-ed36-4d36-b50a-a3261e3a08be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17441
21301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.1744121301
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.1727655732
Short name T548
Test name
Test status
Simulation time 4791469588 ps
CPU time 138.3 seconds
Started Jun 26 05:22:06 PM PDT 24
Finished Jun 26 05:24:28 PM PDT 24
Peak memory 206480 kb
Host smart-632b45a0-0227-454a-abe1-234221bc4384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17276
55732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.1727655732
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.2731672524
Short name T1761
Test name
Test status
Simulation time 3798334804 ps
CPU time 4.53 seconds
Started Jun 26 05:12:21 PM PDT 24
Finished Jun 26 05:12:26 PM PDT 24
Peak memory 206256 kb
Host smart-44082205-3840-4774-9ebd-7814a390059f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2731672524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.2731672524
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.3332605927
Short name T2389
Test name
Test status
Simulation time 13525214764 ps
CPU time 12.68 seconds
Started Jun 26 05:12:16 PM PDT 24
Finished Jun 26 05:12:30 PM PDT 24
Peak memory 206428 kb
Host smart-ba728d57-1cfc-47ca-8bce-d02a516af6af
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3332605927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.3332605927
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.4147909305
Short name T991
Test name
Test status
Simulation time 23361200712 ps
CPU time 22 seconds
Started Jun 26 05:12:17 PM PDT 24
Finished Jun 26 05:12:40 PM PDT 24
Peak memory 206560 kb
Host smart-6cc8fed6-b497-4f60-9337-6806f88aa24a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4147909305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.4147909305
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.428412195
Short name T1268
Test name
Test status
Simulation time 166669089 ps
CPU time 0.82 seconds
Started Jun 26 05:12:18 PM PDT 24
Finished Jun 26 05:12:20 PM PDT 24
Peak memory 206224 kb
Host smart-689a68ed-a4e2-4baa-92e0-21f0bbb378bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42841
2195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.428412195
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.2379612989
Short name T790
Test name
Test status
Simulation time 145114775 ps
CPU time 0.74 seconds
Started Jun 26 05:12:17 PM PDT 24
Finished Jun 26 05:12:19 PM PDT 24
Peak memory 206112 kb
Host smart-9a85c4fb-25ef-4a47-807a-4c82e7205428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23796
12989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.2379612989
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.1471254601
Short name T885
Test name
Test status
Simulation time 386335792 ps
CPU time 1.27 seconds
Started Jun 26 05:12:24 PM PDT 24
Finished Jun 26 05:12:26 PM PDT 24
Peak memory 206092 kb
Host smart-1907eba4-d052-4cad-8a2b-bfb85a5b2a47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14712
54601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.1471254601
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.537253741
Short name T2169
Test name
Test status
Simulation time 1528406968 ps
CPU time 3.16 seconds
Started Jun 26 05:12:23 PM PDT 24
Finished Jun 26 05:12:27 PM PDT 24
Peak memory 206456 kb
Host smart-0d6c4497-2cd5-4494-bf5b-adec13f05f02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53725
3741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.537253741
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.1420181248
Short name T1660
Test name
Test status
Simulation time 7125775274 ps
CPU time 13.85 seconds
Started Jun 26 05:12:24 PM PDT 24
Finished Jun 26 05:12:39 PM PDT 24
Peak memory 206452 kb
Host smart-4f8f754c-39ee-4091-8bb2-6d4cd12b4add
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14201
81248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.1420181248
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.1780439814
Short name T749
Test name
Test status
Simulation time 400950827 ps
CPU time 1.31 seconds
Started Jun 26 05:12:25 PM PDT 24
Finished Jun 26 05:12:27 PM PDT 24
Peak memory 206224 kb
Host smart-cdc51370-c8e1-4e47-a4f5-6018e8260385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17804
39814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.1780439814
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.408696070
Short name T1945
Test name
Test status
Simulation time 142022371 ps
CPU time 0.75 seconds
Started Jun 26 05:12:24 PM PDT 24
Finished Jun 26 05:12:25 PM PDT 24
Peak memory 206392 kb
Host smart-1a84e487-f3a5-4647-aeb1-5d82f2e33450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40869
6070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.408696070
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.1763285003
Short name T1830
Test name
Test status
Simulation time 37222666 ps
CPU time 0.71 seconds
Started Jun 26 05:12:23 PM PDT 24
Finished Jun 26 05:12:24 PM PDT 24
Peak memory 206136 kb
Host smart-779b2313-e7e7-4e03-baa4-9a99e06b4849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17632
85003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.1763285003
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.1378902858
Short name T390
Test name
Test status
Simulation time 1162224023 ps
CPU time 2.63 seconds
Started Jun 26 05:12:23 PM PDT 24
Finished Jun 26 05:12:27 PM PDT 24
Peak memory 206428 kb
Host smart-7a1463b4-a47e-4416-ac60-28cee5c6d2f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13789
02858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.1378902858
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.1803901464
Short name T409
Test name
Test status
Simulation time 184716130 ps
CPU time 1.9 seconds
Started Jun 26 05:12:24 PM PDT 24
Finished Jun 26 05:12:27 PM PDT 24
Peak memory 206432 kb
Host smart-6b34d56a-6ed0-4952-ad09-5a9f639a4c51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18039
01464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.1803901464
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.244811194
Short name T1115
Test name
Test status
Simulation time 228435149 ps
CPU time 0.84 seconds
Started Jun 26 05:12:47 PM PDT 24
Finished Jun 26 05:12:49 PM PDT 24
Peak memory 206140 kb
Host smart-e685178e-1aca-456e-969e-7b05b0094da7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24481
1194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.244811194
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.931419430
Short name T1929
Test name
Test status
Simulation time 143267113 ps
CPU time 0.74 seconds
Started Jun 26 05:12:48 PM PDT 24
Finished Jun 26 05:12:50 PM PDT 24
Peak memory 206136 kb
Host smart-1c229701-af79-4a8b-92ac-9620fd8a27f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93141
9430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.931419430
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.2571447190
Short name T1223
Test name
Test status
Simulation time 236936205 ps
CPU time 0.95 seconds
Started Jun 26 05:12:37 PM PDT 24
Finished Jun 26 05:12:39 PM PDT 24
Peak memory 206180 kb
Host smart-2c8b1902-14ba-4b7d-b493-207e8aa61ad6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25714
47190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.2571447190
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_invalid_sync.166984195
Short name T2518
Test name
Test status
Simulation time 7134120195 ps
CPU time 181.63 seconds
Started Jun 26 05:12:36 PM PDT 24
Finished Jun 26 05:15:39 PM PDT 24
Peak memory 206408 kb
Host smart-3602980f-4a64-46a6-a17d-75247403c47a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=166984195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.166984195
Directory /workspace/5.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.877670106
Short name T443
Test name
Test status
Simulation time 224055487 ps
CPU time 0.88 seconds
Started Jun 26 05:12:36 PM PDT 24
Finished Jun 26 05:12:38 PM PDT 24
Peak memory 206128 kb
Host smart-b3a7417c-dbd6-4573-b79a-d08c06648152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87767
0106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.877670106
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.1878257290
Short name T2534
Test name
Test status
Simulation time 23327353184 ps
CPU time 23.51 seconds
Started Jun 26 05:12:39 PM PDT 24
Finished Jun 26 05:13:03 PM PDT 24
Peak memory 206308 kb
Host smart-5120645b-4c97-455e-b0ab-b73d56bd4daf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18782
57290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.1878257290
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.1685090458
Short name T222
Test name
Test status
Simulation time 3320223291 ps
CPU time 3.73 seconds
Started Jun 26 05:12:34 PM PDT 24
Finished Jun 26 05:12:39 PM PDT 24
Peak memory 206248 kb
Host smart-03e66d1b-9600-41c1-9582-c7aefbfd056b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16850
90458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.1685090458
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.700606438
Short name T155
Test name
Test status
Simulation time 11121859406 ps
CPU time 305.99 seconds
Started Jun 26 05:12:35 PM PDT 24
Finished Jun 26 05:17:42 PM PDT 24
Peak memory 206480 kb
Host smart-22a071f5-a6b8-486e-9507-4d1730766935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70060
6438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.700606438
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.2544960782
Short name T1478
Test name
Test status
Simulation time 5319130428 ps
CPU time 153.25 seconds
Started Jun 26 05:12:36 PM PDT 24
Finished Jun 26 05:15:11 PM PDT 24
Peak memory 206500 kb
Host smart-9d4f8499-96ab-4c13-b225-3542e3f167cb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2544960782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.2544960782
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.4015046775
Short name T2176
Test name
Test status
Simulation time 317362305 ps
CPU time 0.96 seconds
Started Jun 26 05:12:42 PM PDT 24
Finished Jun 26 05:12:44 PM PDT 24
Peak memory 206144 kb
Host smart-2817b270-0727-49da-8483-c418e74afa1d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4015046775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.4015046775
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.3996732340
Short name T375
Test name
Test status
Simulation time 186027241 ps
CPU time 0.85 seconds
Started Jun 26 05:12:37 PM PDT 24
Finished Jun 26 05:12:39 PM PDT 24
Peak memory 206212 kb
Host smart-93afad4f-0f2a-4757-abfe-8498682063ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39967
32340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.3996732340
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.4193181943
Short name T478
Test name
Test status
Simulation time 6352696994 ps
CPU time 61.23 seconds
Started Jun 26 05:12:40 PM PDT 24
Finished Jun 26 05:13:42 PM PDT 24
Peak memory 206532 kb
Host smart-9dd8dfa3-af75-417f-9f03-b7f7dc08181f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41931
81943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.4193181943
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.3384356832
Short name T666
Test name
Test status
Simulation time 5621116978 ps
CPU time 146.32 seconds
Started Jun 26 05:12:34 PM PDT 24
Finished Jun 26 05:15:01 PM PDT 24
Peak memory 206456 kb
Host smart-55e1a93f-e599-47d4-aaff-8faae0230082
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3384356832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.3384356832
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.951607874
Short name T549
Test name
Test status
Simulation time 217016006 ps
CPU time 0.82 seconds
Started Jun 26 05:12:40 PM PDT 24
Finished Jun 26 05:12:41 PM PDT 24
Peak memory 206116 kb
Host smart-2b416c4c-3f4b-4ce8-9b05-facf311406f4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=951607874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.951607874
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.1799256089
Short name T1882
Test name
Test status
Simulation time 177268955 ps
CPU time 0.83 seconds
Started Jun 26 05:12:39 PM PDT 24
Finished Jun 26 05:12:40 PM PDT 24
Peak memory 206448 kb
Host smart-6cb1ca1c-458f-428f-872c-0a67eaaf5fb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17992
56089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.1799256089
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.2842265059
Short name T129
Test name
Test status
Simulation time 212350443 ps
CPU time 0.84 seconds
Started Jun 26 05:12:39 PM PDT 24
Finished Jun 26 05:12:40 PM PDT 24
Peak memory 206232 kb
Host smart-f914e9ea-08d0-40f2-8e14-3078217559a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28422
65059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.2842265059
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.2319214474
Short name T295
Test name
Test status
Simulation time 212928345 ps
CPU time 0.87 seconds
Started Jun 26 05:12:36 PM PDT 24
Finished Jun 26 05:12:38 PM PDT 24
Peak memory 206140 kb
Host smart-693d5c86-a9cb-4b84-84f8-57396fff85fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23192
14474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.2319214474
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.622784424
Short name T2107
Test name
Test status
Simulation time 212657020 ps
CPU time 0.82 seconds
Started Jun 26 05:12:40 PM PDT 24
Finished Jun 26 05:12:41 PM PDT 24
Peak memory 206236 kb
Host smart-561321ea-6a90-463e-b196-094e06957b89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62278
4424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.622784424
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.2712394211
Short name T1609
Test name
Test status
Simulation time 183863408 ps
CPU time 0.84 seconds
Started Jun 26 05:12:35 PM PDT 24
Finished Jun 26 05:12:37 PM PDT 24
Peak memory 206224 kb
Host smart-543f9319-2c91-42fe-8bd3-6c4791d21e11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27123
94211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.2712394211
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.551019327
Short name T1475
Test name
Test status
Simulation time 153859457 ps
CPU time 0.77 seconds
Started Jun 26 05:12:44 PM PDT 24
Finished Jun 26 05:12:45 PM PDT 24
Peak memory 206200 kb
Host smart-44283933-3518-49d2-ad88-f02506b27974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55101
9327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.551019327
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.765301223
Short name T1524
Test name
Test status
Simulation time 203312826 ps
CPU time 0.86 seconds
Started Jun 26 05:12:38 PM PDT 24
Finished Jun 26 05:12:39 PM PDT 24
Peak memory 206224 kb
Host smart-c883e866-ec9d-4c42-aad0-33465e91d5f8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=765301223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.765301223
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.911318826
Short name T1283
Test name
Test status
Simulation time 158184367 ps
CPU time 0.78 seconds
Started Jun 26 05:12:37 PM PDT 24
Finished Jun 26 05:12:39 PM PDT 24
Peak memory 206108 kb
Host smart-784e4e24-1faa-44bc-8b6c-301bb3c45f49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91131
8826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.911318826
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.565570439
Short name T1437
Test name
Test status
Simulation time 39819133 ps
CPU time 0.71 seconds
Started Jun 26 05:12:41 PM PDT 24
Finished Jun 26 05:12:42 PM PDT 24
Peak memory 206096 kb
Host smart-ddee8d4d-be8e-49c3-87d0-62139fe7abf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56557
0439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.565570439
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.3496327418
Short name T1946
Test name
Test status
Simulation time 9853818959 ps
CPU time 21.66 seconds
Started Jun 26 05:12:37 PM PDT 24
Finished Jun 26 05:13:00 PM PDT 24
Peak memory 206604 kb
Host smart-5b0f0850-950b-46b9-aeba-91b380b40378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34963
27418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.3496327418
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.1411372870
Short name T1999
Test name
Test status
Simulation time 184045378 ps
CPU time 0.9 seconds
Started Jun 26 05:12:37 PM PDT 24
Finished Jun 26 05:12:39 PM PDT 24
Peak memory 206196 kb
Host smart-98e380a9-a7ac-4118-a32e-d628150fa0f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14113
72870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.1411372870
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.1256257261
Short name T414
Test name
Test status
Simulation time 205550049 ps
CPU time 0.82 seconds
Started Jun 26 05:12:35 PM PDT 24
Finished Jun 26 05:12:37 PM PDT 24
Peak memory 206144 kb
Host smart-8a8b5a7d-026a-4ea8-b9cc-c7df2128dde8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12562
57261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.1256257261
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.2162105195
Short name T2517
Test name
Test status
Simulation time 20867857772 ps
CPU time 565.4 seconds
Started Jun 26 05:12:36 PM PDT 24
Finished Jun 26 05:22:03 PM PDT 24
Peak memory 206504 kb
Host smart-fdf41791-89c3-4a18-99d8-92246ab565b6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2162105195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.2162105195
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.2907972848
Short name T174
Test name
Test status
Simulation time 10541120036 ps
CPU time 55.58 seconds
Started Jun 26 05:12:35 PM PDT 24
Finished Jun 26 05:13:31 PM PDT 24
Peak memory 206592 kb
Host smart-11dc4bd0-53c5-4e35-8551-0aeec8208231
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2907972848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.2907972848
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.4230744550
Short name T1525
Test name
Test status
Simulation time 20262324100 ps
CPU time 147.83 seconds
Started Jun 26 05:12:43 PM PDT 24
Finished Jun 26 05:15:12 PM PDT 24
Peak memory 205816 kb
Host smart-fb1907c3-21e5-4514-92fe-ac8cc5171d82
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4230744550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.4230744550
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.1171436614
Short name T402
Test name
Test status
Simulation time 232709590 ps
CPU time 0.94 seconds
Started Jun 26 05:12:43 PM PDT 24
Finished Jun 26 05:12:45 PM PDT 24
Peak memory 205432 kb
Host smart-8aef713b-63b5-45ac-82d2-2ea12b2ddb19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11714
36614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.1171436614
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.1860749130
Short name T1234
Test name
Test status
Simulation time 177482761 ps
CPU time 0.82 seconds
Started Jun 26 05:12:40 PM PDT 24
Finished Jun 26 05:12:41 PM PDT 24
Peak memory 206204 kb
Host smart-e34d576b-a4eb-4876-b4d4-131d9390d5de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18607
49130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.1860749130
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.1419938745
Short name T1502
Test name
Test status
Simulation time 178918772 ps
CPU time 0.78 seconds
Started Jun 26 05:12:47 PM PDT 24
Finished Jun 26 05:12:49 PM PDT 24
Peak memory 206128 kb
Host smart-d1929ed1-3707-4449-9ef7-cb2a3c22ace7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14199
38745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.1419938745
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.786331938
Short name T2393
Test name
Test status
Simulation time 158766923 ps
CPU time 0.75 seconds
Started Jun 26 05:12:42 PM PDT 24
Finished Jun 26 05:12:44 PM PDT 24
Peak memory 206220 kb
Host smart-842e3734-ceda-4f84-a5b5-bd55e07eb90d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78633
1938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.786331938
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.968507032
Short name T2064
Test name
Test status
Simulation time 149771199 ps
CPU time 0.74 seconds
Started Jun 26 05:12:47 PM PDT 24
Finished Jun 26 05:12:48 PM PDT 24
Peak memory 206140 kb
Host smart-1fbd957f-5744-4b8f-9972-f9e831782c08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96850
7032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.968507032
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.1876620522
Short name T2434
Test name
Test status
Simulation time 247541018 ps
CPU time 0.93 seconds
Started Jun 26 05:12:44 PM PDT 24
Finished Jun 26 05:12:46 PM PDT 24
Peak memory 206192 kb
Host smart-96c2c051-38fa-497b-a2db-c93e1799bac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18766
20522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.1876620522
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.1743671826
Short name T2111
Test name
Test status
Simulation time 3985399773 ps
CPU time 114.31 seconds
Started Jun 26 05:12:41 PM PDT 24
Finished Jun 26 05:14:36 PM PDT 24
Peak memory 206468 kb
Host smart-8ff9906a-4a8e-4975-a3e8-cd4aab1cc1e2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1743671826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.1743671826
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.1627709375
Short name T876
Test name
Test status
Simulation time 167662900 ps
CPU time 0.83 seconds
Started Jun 26 05:12:41 PM PDT 24
Finished Jun 26 05:12:43 PM PDT 24
Peak memory 206212 kb
Host smart-e9d61106-f370-4d12-9fdc-3b28aff1fef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16277
09375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.1627709375
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.3458866545
Short name T1690
Test name
Test status
Simulation time 158245082 ps
CPU time 0.78 seconds
Started Jun 26 05:12:44 PM PDT 24
Finished Jun 26 05:12:45 PM PDT 24
Peak memory 206176 kb
Host smart-2998efdb-b800-4464-9bc1-b16abe7f97b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34588
66545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.3458866545
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.1918387519
Short name T1959
Test name
Test status
Simulation time 5668319663 ps
CPU time 152.7 seconds
Started Jun 26 05:12:40 PM PDT 24
Finished Jun 26 05:15:13 PM PDT 24
Peak memory 206480 kb
Host smart-0738becd-3fc5-4a1f-b634-11e63db04ff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19183
87519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.1918387519
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.437122251
Short name T1778
Test name
Test status
Simulation time 3719636055 ps
CPU time 4.26 seconds
Started Jun 26 05:12:43 PM PDT 24
Finished Jun 26 05:12:48 PM PDT 24
Peak memory 206444 kb
Host smart-c4d2ced1-58eb-4f7a-9be2-6bf764baf621
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=437122251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.437122251
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.559340341
Short name T2236
Test name
Test status
Simulation time 13462060877 ps
CPU time 14.59 seconds
Started Jun 26 05:12:42 PM PDT 24
Finished Jun 26 05:12:57 PM PDT 24
Peak memory 206428 kb
Host smart-c1450bf5-6f5e-4feb-91ae-a7101007a6d4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=559340341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.559340341
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.2589652640
Short name T890
Test name
Test status
Simulation time 23295222802 ps
CPU time 22.46 seconds
Started Jun 26 05:12:48 PM PDT 24
Finished Jun 26 05:13:12 PM PDT 24
Peak memory 206240 kb
Host smart-bb7d9962-adb4-4c7c-a361-3aa4e450db85
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2589652640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.2589652640
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.1118518243
Short name T2239
Test name
Test status
Simulation time 158404481 ps
CPU time 0.77 seconds
Started Jun 26 05:12:47 PM PDT 24
Finished Jun 26 05:12:49 PM PDT 24
Peak memory 206148 kb
Host smart-e446fd2a-7315-4559-ba3b-619a1d89a5c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11185
18243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.1118518243
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.964409713
Short name T957
Test name
Test status
Simulation time 214824718 ps
CPU time 0.8 seconds
Started Jun 26 05:12:40 PM PDT 24
Finished Jun 26 05:12:42 PM PDT 24
Peak memory 206116 kb
Host smart-96c43134-a460-40af-9aa9-8f6ba6ff8899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96440
9713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.964409713
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.2281786074
Short name T1366
Test name
Test status
Simulation time 195219290 ps
CPU time 0.89 seconds
Started Jun 26 05:12:47 PM PDT 24
Finished Jun 26 05:12:48 PM PDT 24
Peak memory 206172 kb
Host smart-a100d639-ae9a-4fcc-acc9-d3817baa17e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22817
86074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.2281786074
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.1401979118
Short name T1604
Test name
Test status
Simulation time 1132455040 ps
CPU time 2.68 seconds
Started Jun 26 05:12:48 PM PDT 24
Finished Jun 26 05:12:52 PM PDT 24
Peak memory 206496 kb
Host smart-cf87efcd-5b44-4f32-869f-217141cfd2c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14019
79118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.1401979118
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.3331971855
Short name T2280
Test name
Test status
Simulation time 501438212 ps
CPU time 1.43 seconds
Started Jun 26 05:12:47 PM PDT 24
Finished Jun 26 05:12:50 PM PDT 24
Peak memory 206228 kb
Host smart-5fd0345a-dff4-4b44-807f-36dd86ca56bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33319
71855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.3331971855
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.2164851140
Short name T1799
Test name
Test status
Simulation time 136984024 ps
CPU time 0.76 seconds
Started Jun 26 05:12:46 PM PDT 24
Finished Jun 26 05:12:47 PM PDT 24
Peak memory 206124 kb
Host smart-5367007f-79ee-4fbe-9d08-6e5b53894aff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21648
51140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.2164851140
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.3403958553
Short name T245
Test name
Test status
Simulation time 46531222 ps
CPU time 0.65 seconds
Started Jun 26 05:12:48 PM PDT 24
Finished Jun 26 05:12:50 PM PDT 24
Peak memory 206136 kb
Host smart-ca9ee9e1-3be9-41bd-9b6d-8914c1984329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34039
58553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.3403958553
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.2191578802
Short name T347
Test name
Test status
Simulation time 761826995 ps
CPU time 1.82 seconds
Started Jun 26 05:12:51 PM PDT 24
Finished Jun 26 05:12:53 PM PDT 24
Peak memory 206328 kb
Host smart-9622fa34-509d-4bdb-8dec-6a038829d768
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21915
78802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.2191578802
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.1058147064
Short name T1210
Test name
Test status
Simulation time 172344432 ps
CPU time 1.5 seconds
Started Jun 26 05:12:46 PM PDT 24
Finished Jun 26 05:12:49 PM PDT 24
Peak memory 206468 kb
Host smart-f1e7a85f-3f79-4650-a1fd-2c0431763569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10581
47064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.1058147064
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.2747735088
Short name T1374
Test name
Test status
Simulation time 214861705 ps
CPU time 0.89 seconds
Started Jun 26 05:13:07 PM PDT 24
Finished Jun 26 05:13:09 PM PDT 24
Peak memory 205664 kb
Host smart-6ce59a1f-f084-4d01-b033-a3f5e49926e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27477
35088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.2747735088
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.2280151751
Short name T976
Test name
Test status
Simulation time 141382599 ps
CPU time 0.77 seconds
Started Jun 26 05:13:02 PM PDT 24
Finished Jun 26 05:13:04 PM PDT 24
Peak memory 206148 kb
Host smart-813f02d3-ef47-4080-a19e-da936fe4e79b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22801
51751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.2280151751
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.1207244023
Short name T1664
Test name
Test status
Simulation time 216408004 ps
CPU time 0.85 seconds
Started Jun 26 05:12:51 PM PDT 24
Finished Jun 26 05:12:52 PM PDT 24
Peak memory 206140 kb
Host smart-b785f717-211a-44bc-9491-0f361fb677c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12072
44023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.1207244023
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_invalid_sync.146677137
Short name T541
Test name
Test status
Simulation time 6404196504 ps
CPU time 163.78 seconds
Started Jun 26 05:12:49 PM PDT 24
Finished Jun 26 05:15:34 PM PDT 24
Peak memory 206484 kb
Host smart-d7ca6621-f821-4a34-8406-ec28036f3d8f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=146677137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.146677137
Directory /workspace/6.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.1005634362
Short name T585
Test name
Test status
Simulation time 178414240 ps
CPU time 0.85 seconds
Started Jun 26 05:12:48 PM PDT 24
Finished Jun 26 05:12:50 PM PDT 24
Peak memory 206136 kb
Host smart-02b062f2-50d6-4622-bfcd-5f8e25454a86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10056
34362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.1005634362
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.262221118
Short name T2310
Test name
Test status
Simulation time 23314181378 ps
CPU time 28.5 seconds
Started Jun 26 05:12:51 PM PDT 24
Finished Jun 26 05:13:20 PM PDT 24
Peak memory 206248 kb
Host smart-eeb92665-162a-47ac-8085-b298fb17d7c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26222
1118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.262221118
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.492308897
Short name T2028
Test name
Test status
Simulation time 3321518015 ps
CPU time 4.9 seconds
Started Jun 26 05:12:46 PM PDT 24
Finished Jun 26 05:12:52 PM PDT 24
Peak memory 206184 kb
Host smart-b9193aba-f222-4033-8f14-a8e28ae2e9a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49230
8897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.492308897
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.1450518597
Short name T1682
Test name
Test status
Simulation time 9007142889 ps
CPU time 62.05 seconds
Started Jun 26 05:12:57 PM PDT 24
Finished Jun 26 05:14:01 PM PDT 24
Peak memory 206824 kb
Host smart-ababcd43-2b0d-4ea3-85d2-9401101498dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14505
18597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.1450518597
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.1969553873
Short name T2394
Test name
Test status
Simulation time 4110533694 ps
CPU time 112.11 seconds
Started Jun 26 05:12:57 PM PDT 24
Finished Jun 26 05:14:50 PM PDT 24
Peak memory 206516 kb
Host smart-75576e6e-61b5-4504-b02c-9e155d58b35c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1969553873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.1969553873
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.3306862625
Short name T1750
Test name
Test status
Simulation time 248900291 ps
CPU time 0.89 seconds
Started Jun 26 05:13:04 PM PDT 24
Finished Jun 26 05:13:06 PM PDT 24
Peak memory 206228 kb
Host smart-523e8df6-356c-470d-8eee-69a709aba77f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3306862625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.3306862625
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.1507982367
Short name T2163
Test name
Test status
Simulation time 235823501 ps
CPU time 0.86 seconds
Started Jun 26 05:12:58 PM PDT 24
Finished Jun 26 05:13:00 PM PDT 24
Peak memory 206192 kb
Host smart-e2d2904e-fb58-4224-9bfd-8f3e5f89e5ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15079
82367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.1507982367
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.2848507123
Short name T709
Test name
Test status
Simulation time 4730588446 ps
CPU time 126.66 seconds
Started Jun 26 05:12:56 PM PDT 24
Finished Jun 26 05:15:03 PM PDT 24
Peak memory 206500 kb
Host smart-fef66d26-0a75-48d2-b96c-d1b0b0fc13f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28485
07123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.2848507123
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.4545726
Short name T2388
Test name
Test status
Simulation time 4948538693 ps
CPU time 44.04 seconds
Started Jun 26 05:12:56 PM PDT 24
Finished Jun 26 05:13:41 PM PDT 24
Peak memory 206520 kb
Host smart-b8aad6b2-a65c-4871-ac70-52655b35d699
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4545726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.4545726
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.4287795550
Short name T677
Test name
Test status
Simulation time 217407548 ps
CPU time 0.85 seconds
Started Jun 26 05:13:05 PM PDT 24
Finished Jun 26 05:13:07 PM PDT 24
Peak memory 206248 kb
Host smart-bdeea12f-5422-4e06-8284-5778512e1d21
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4287795550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.4287795550
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.2486473175
Short name T1976
Test name
Test status
Simulation time 150591641 ps
CPU time 0.8 seconds
Started Jun 26 05:12:55 PM PDT 24
Finished Jun 26 05:12:57 PM PDT 24
Peak memory 206116 kb
Host smart-c3307ef4-bd1f-44a6-bb88-a6a9e9e33bbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24864
73175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.2486473175
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.1516048871
Short name T2360
Test name
Test status
Simulation time 187154976 ps
CPU time 0.85 seconds
Started Jun 26 05:12:55 PM PDT 24
Finished Jun 26 05:12:57 PM PDT 24
Peak memory 206252 kb
Host smart-67cca441-0d2e-4bf9-9f23-fc44c1eb2158
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15160
48871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.1516048871
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.459886460
Short name T1605
Test name
Test status
Simulation time 174670506 ps
CPU time 0.9 seconds
Started Jun 26 05:12:56 PM PDT 24
Finished Jun 26 05:12:58 PM PDT 24
Peak memory 206140 kb
Host smart-3c41b837-c813-42e0-b123-1d7226257027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45988
6460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.459886460
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.2803987083
Short name T424
Test name
Test status
Simulation time 188589504 ps
CPU time 0.78 seconds
Started Jun 26 05:12:55 PM PDT 24
Finished Jun 26 05:12:57 PM PDT 24
Peak memory 206216 kb
Host smart-5f9d25eb-f03d-4dd3-b09d-48466acd57eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28039
87083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.2803987083
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.2625369982
Short name T1890
Test name
Test status
Simulation time 170339518 ps
CPU time 0.79 seconds
Started Jun 26 05:12:56 PM PDT 24
Finished Jun 26 05:12:58 PM PDT 24
Peak memory 206120 kb
Host smart-137b014d-da9c-4296-bc87-d60c473304ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26253
69982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.2625369982
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.3492290609
Short name T184
Test name
Test status
Simulation time 144788763 ps
CPU time 0.77 seconds
Started Jun 26 05:13:05 PM PDT 24
Finished Jun 26 05:13:07 PM PDT 24
Peak memory 206124 kb
Host smart-fd833572-3809-454d-a7c2-ae23ee881f97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34922
90609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.3492290609
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.732910889
Short name T1293
Test name
Test status
Simulation time 214832510 ps
CPU time 0.95 seconds
Started Jun 26 05:12:55 PM PDT 24
Finished Jun 26 05:12:57 PM PDT 24
Peak memory 206212 kb
Host smart-9839d792-2801-4cc1-b4bc-69bcd31f5e74
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=732910889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.732910889
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.3391071888
Short name T681
Test name
Test status
Simulation time 146822333 ps
CPU time 0.81 seconds
Started Jun 26 05:12:57 PM PDT 24
Finished Jun 26 05:12:59 PM PDT 24
Peak memory 206196 kb
Host smart-e84bd533-de87-4838-b1c5-12e8d23e65d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33910
71888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.3391071888
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.1660785974
Short name T1494
Test name
Test status
Simulation time 78582536 ps
CPU time 0.65 seconds
Started Jun 26 05:13:05 PM PDT 24
Finished Jun 26 05:13:07 PM PDT 24
Peak memory 206120 kb
Host smart-3f6bd893-ca13-409f-842e-2406a3be4c61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16607
85974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.1660785974
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.3989599801
Short name T297
Test name
Test status
Simulation time 20265008407 ps
CPU time 43.88 seconds
Started Jun 26 05:12:57 PM PDT 24
Finished Jun 26 05:13:42 PM PDT 24
Peak memory 206464 kb
Host smart-5b770e99-8d9e-4839-9d38-7ebd7228d88f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39895
99801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.3989599801
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.2059947022
Short name T639
Test name
Test status
Simulation time 183736389 ps
CPU time 0.83 seconds
Started Jun 26 05:12:56 PM PDT 24
Finished Jun 26 05:12:58 PM PDT 24
Peak memory 206096 kb
Host smart-3517bcf5-8ca9-470a-bea2-359f1754299e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20599
47022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.2059947022
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.3554276392
Short name T1421
Test name
Test status
Simulation time 198800239 ps
CPU time 0.86 seconds
Started Jun 26 05:12:56 PM PDT 24
Finished Jun 26 05:12:58 PM PDT 24
Peak memory 206224 kb
Host smart-6399d612-e381-48ed-8ff8-4d1665ec87d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35542
76392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.3554276392
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.3207158007
Short name T2516
Test name
Test status
Simulation time 13577873764 ps
CPU time 85.96 seconds
Started Jun 26 05:12:58 PM PDT 24
Finished Jun 26 05:14:25 PM PDT 24
Peak memory 206508 kb
Host smart-7b0f4518-31bb-4d95-91c0-6292d38d8c67
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3207158007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.3207158007
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.818638583
Short name T173
Test name
Test status
Simulation time 7383203430 ps
CPU time 66.32 seconds
Started Jun 26 05:12:55 PM PDT 24
Finished Jun 26 05:14:02 PM PDT 24
Peak memory 206528 kb
Host smart-787e533c-f50e-4f7c-9592-70708aa145fa
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=818638583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.818638583
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.291572379
Short name T1633
Test name
Test status
Simulation time 8307507302 ps
CPU time 36.98 seconds
Started Jun 26 05:12:55 PM PDT 24
Finished Jun 26 05:13:32 PM PDT 24
Peak memory 206480 kb
Host smart-898988ca-d88f-482a-a936-4e0c4cba2986
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=291572379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.291572379
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.3810857019
Short name T2576
Test name
Test status
Simulation time 200947355 ps
CPU time 0.9 seconds
Started Jun 26 05:13:02 PM PDT 24
Finished Jun 26 05:13:04 PM PDT 24
Peak memory 206200 kb
Host smart-6d5e2013-6922-4a5a-9090-f902fabb45df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38108
57019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.3810857019
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.3098684122
Short name T1153
Test name
Test status
Simulation time 228744742 ps
CPU time 0.86 seconds
Started Jun 26 05:12:55 PM PDT 24
Finished Jun 26 05:12:57 PM PDT 24
Peak memory 206208 kb
Host smart-1d8813b8-96c9-4fd2-abd7-e6bd25b2b123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30986
84122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.3098684122
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.3880460473
Short name T2005
Test name
Test status
Simulation time 241625538 ps
CPU time 0.86 seconds
Started Jun 26 05:12:56 PM PDT 24
Finished Jun 26 05:12:59 PM PDT 24
Peak memory 206220 kb
Host smart-333f1cc7-07f5-4516-8c4b-db8845f26ce1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38804
60473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.3880460473
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.4010406315
Short name T2088
Test name
Test status
Simulation time 160111297 ps
CPU time 0.84 seconds
Started Jun 26 05:13:07 PM PDT 24
Finished Jun 26 05:13:09 PM PDT 24
Peak memory 205396 kb
Host smart-d1d2ab3e-5eb7-4923-a747-2ad4dcf08c23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40104
06315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.4010406315
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.1691634626
Short name T1096
Test name
Test status
Simulation time 185376311 ps
CPU time 0.8 seconds
Started Jun 26 05:13:05 PM PDT 24
Finished Jun 26 05:13:08 PM PDT 24
Peak memory 206224 kb
Host smart-74d23acd-e9ad-4a38-8016-fbcc4e162a0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16916
34626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.1691634626
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.560134288
Short name T434
Test name
Test status
Simulation time 302240659 ps
CPU time 1.04 seconds
Started Jun 26 05:13:03 PM PDT 24
Finished Jun 26 05:13:05 PM PDT 24
Peak memory 206204 kb
Host smart-0451582d-fdcc-4c2f-8da9-887658282043
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56013
4288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.560134288
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.3218235808
Short name T1023
Test name
Test status
Simulation time 3148684229 ps
CPU time 21.3 seconds
Started Jun 26 05:13:04 PM PDT 24
Finished Jun 26 05:13:27 PM PDT 24
Peak memory 206408 kb
Host smart-ead51980-762f-4c12-a49e-5bb7f9a85c9d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3218235808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.3218235808
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.640111923
Short name T2078
Test name
Test status
Simulation time 143122008 ps
CPU time 0.81 seconds
Started Jun 26 05:13:04 PM PDT 24
Finished Jun 26 05:13:05 PM PDT 24
Peak memory 206128 kb
Host smart-f423a1fe-d377-4ccb-b9b5-7b7a318c18fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64011
1923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.640111923
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.2568008845
Short name T1262
Test name
Test status
Simulation time 190408280 ps
CPU time 0.85 seconds
Started Jun 26 05:13:05 PM PDT 24
Finished Jun 26 05:13:08 PM PDT 24
Peak memory 206208 kb
Host smart-5bbce026-e4ed-4a21-8d71-d5cfb8274aa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25680
08845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.2568008845
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.3776828296
Short name T1828
Test name
Test status
Simulation time 3984812567 ps
CPU time 110.95 seconds
Started Jun 26 05:13:04 PM PDT 24
Finished Jun 26 05:14:56 PM PDT 24
Peak memory 206468 kb
Host smart-1af4d89c-4581-4bc6-8449-34170e71dbb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37768
28296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.3776828296
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.2180969279
Short name T900
Test name
Test status
Simulation time 3523828050 ps
CPU time 4.19 seconds
Started Jun 26 05:13:05 PM PDT 24
Finished Jun 26 05:13:10 PM PDT 24
Peak memory 206280 kb
Host smart-ac5f297d-cd20-4a58-977d-3b1abeac9b53
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2180969279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.2180969279
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.2591109450
Short name T2077
Test name
Test status
Simulation time 13514628967 ps
CPU time 12.5 seconds
Started Jun 26 05:13:05 PM PDT 24
Finished Jun 26 05:13:19 PM PDT 24
Peak memory 206520 kb
Host smart-a3b67d9c-d8a6-4950-9ec7-ca161770d0b2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2591109450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.2591109450
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.483124310
Short name T1749
Test name
Test status
Simulation time 23275590322 ps
CPU time 24.15 seconds
Started Jun 26 05:13:04 PM PDT 24
Finished Jun 26 05:13:30 PM PDT 24
Peak memory 206328 kb
Host smart-981a1d70-27a2-473a-aa45-cbd10852b501
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=483124310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.483124310
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.1008337563
Short name T1500
Test name
Test status
Simulation time 180482533 ps
CPU time 0.87 seconds
Started Jun 26 05:13:03 PM PDT 24
Finished Jun 26 05:13:05 PM PDT 24
Peak memory 206196 kb
Host smart-343b4022-a463-4e5a-bb51-7fc94ca9ca00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10083
37563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.1008337563
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.2484713902
Short name T1746
Test name
Test status
Simulation time 163341103 ps
CPU time 0.81 seconds
Started Jun 26 05:13:04 PM PDT 24
Finished Jun 26 05:13:06 PM PDT 24
Peak memory 206116 kb
Host smart-911864e1-91fa-42fd-acd1-d0056464007c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24847
13902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.2484713902
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.3336256182
Short name T2507
Test name
Test status
Simulation time 321027089 ps
CPU time 1.11 seconds
Started Jun 26 05:13:12 PM PDT 24
Finished Jun 26 05:13:13 PM PDT 24
Peak memory 206124 kb
Host smart-386f8770-e82d-42b7-8dc7-8ec64f465882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33362
56182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.3336256182
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.3487520814
Short name T1747
Test name
Test status
Simulation time 683424753 ps
CPU time 1.65 seconds
Started Jun 26 05:13:13 PM PDT 24
Finished Jun 26 05:13:15 PM PDT 24
Peak memory 206400 kb
Host smart-bcaf9ef7-bbb0-4fa8-8f3c-1633489aaa69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34875
20814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.3487520814
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.590315624
Short name T705
Test name
Test status
Simulation time 15957688404 ps
CPU time 32.92 seconds
Started Jun 26 05:13:11 PM PDT 24
Finished Jun 26 05:13:45 PM PDT 24
Peak memory 206540 kb
Host smart-382479f0-310e-4505-a5ae-73c0811cc569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59031
5624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.590315624
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.161842343
Short name T732
Test name
Test status
Simulation time 402543195 ps
CPU time 1.3 seconds
Started Jun 26 05:13:11 PM PDT 24
Finished Jun 26 05:13:13 PM PDT 24
Peak memory 206240 kb
Host smart-f161d90b-3810-4870-87a4-ca3b3f0c9489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16184
2343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.161842343
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.2298231486
Short name T832
Test name
Test status
Simulation time 176821987 ps
CPU time 0.8 seconds
Started Jun 26 05:13:11 PM PDT 24
Finished Jun 26 05:13:12 PM PDT 24
Peak memory 206200 kb
Host smart-f5bc0cd3-885f-449b-80ad-961ef8f79a10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22982
31486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.2298231486
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.2953670856
Short name T2316
Test name
Test status
Simulation time 99641490 ps
CPU time 0.69 seconds
Started Jun 26 05:13:18 PM PDT 24
Finished Jun 26 05:13:19 PM PDT 24
Peak memory 206136 kb
Host smart-80c670ed-4e65-4c29-a525-e723b870ab0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29536
70856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.2953670856
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.3980407837
Short name T768
Test name
Test status
Simulation time 841033064 ps
CPU time 2.01 seconds
Started Jun 26 05:13:22 PM PDT 24
Finished Jun 26 05:13:25 PM PDT 24
Peak memory 206340 kb
Host smart-f35ad460-0bfc-48c2-ac70-91578d5e4bbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39804
07837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.3980407837
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.2922195537
Short name T857
Test name
Test status
Simulation time 157758517 ps
CPU time 1.38 seconds
Started Jun 26 05:13:22 PM PDT 24
Finished Jun 26 05:13:24 PM PDT 24
Peak memory 206404 kb
Host smart-ccc45699-a35e-4f7a-b4fc-d279f2455d07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29221
95537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.2922195537
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.3503340175
Short name T433
Test name
Test status
Simulation time 241098263 ps
CPU time 0.93 seconds
Started Jun 26 05:13:28 PM PDT 24
Finished Jun 26 05:13:30 PM PDT 24
Peak memory 206184 kb
Host smart-7541fc8a-f5b8-40d3-a3be-455b475d9a8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35033
40175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.3503340175
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.3351889388
Short name T1229
Test name
Test status
Simulation time 145958287 ps
CPU time 0.78 seconds
Started Jun 26 05:13:29 PM PDT 24
Finished Jun 26 05:13:31 PM PDT 24
Peak memory 206212 kb
Host smart-fbc35aca-6f6e-46d2-bd62-a6037fd9fca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33518
89388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.3351889388
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.2355690751
Short name T1779
Test name
Test status
Simulation time 239079075 ps
CPU time 0.89 seconds
Started Jun 26 05:13:21 PM PDT 24
Finished Jun 26 05:13:23 PM PDT 24
Peak memory 206216 kb
Host smart-8ca9383d-783e-4574-85f2-d76626fb5d57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23556
90751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.2355690751
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_invalid_sync.4282225165
Short name T1550
Test name
Test status
Simulation time 7378827249 ps
CPU time 59.62 seconds
Started Jun 26 05:13:18 PM PDT 24
Finished Jun 26 05:14:18 PM PDT 24
Peak memory 206548 kb
Host smart-0758fede-a6f9-4e1a-8b76-2c33f7d1e392
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4282225165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_invalid_sync.4282225165
Directory /workspace/7.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.506770653
Short name T719
Test name
Test status
Simulation time 226599190 ps
CPU time 0.89 seconds
Started Jun 26 05:13:21 PM PDT 24
Finished Jun 26 05:13:22 PM PDT 24
Peak memory 206212 kb
Host smart-f8b5a3bb-7bf0-4b56-9dc7-b10017359a8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50677
0653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.506770653
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.3606160669
Short name T331
Test name
Test status
Simulation time 23311759249 ps
CPU time 20.47 seconds
Started Jun 26 05:13:19 PM PDT 24
Finished Jun 26 05:13:40 PM PDT 24
Peak memory 206244 kb
Host smart-029a8c5c-75d4-4cff-a173-a1d876c6fecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36061
60669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.3606160669
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.3087150528
Short name T1670
Test name
Test status
Simulation time 3298162295 ps
CPU time 3.57 seconds
Started Jun 26 05:13:20 PM PDT 24
Finished Jun 26 05:13:24 PM PDT 24
Peak memory 206272 kb
Host smart-fe3b965e-29bb-487f-842e-36324fe8d076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30871
50528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.3087150528
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.2385267304
Short name T1504
Test name
Test status
Simulation time 9580224787 ps
CPU time 263.05 seconds
Started Jun 26 05:13:21 PM PDT 24
Finished Jun 26 05:17:45 PM PDT 24
Peak memory 206568 kb
Host smart-c8e3ef89-6645-42da-a36d-159c79fd4d1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23852
67304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.2385267304
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.2142501603
Short name T836
Test name
Test status
Simulation time 6661250298 ps
CPU time 63.56 seconds
Started Jun 26 05:13:19 PM PDT 24
Finished Jun 26 05:14:23 PM PDT 24
Peak memory 206572 kb
Host smart-c4fc7881-440b-4c05-8d2e-eee1ba2fac88
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2142501603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.2142501603
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.4241014485
Short name T2342
Test name
Test status
Simulation time 240568320 ps
CPU time 1.03 seconds
Started Jun 26 05:13:29 PM PDT 24
Finished Jun 26 05:13:31 PM PDT 24
Peak memory 206144 kb
Host smart-29f17bc3-2855-4fc3-9f08-29fd396c2185
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4241014485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.4241014485
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.3650372613
Short name T998
Test name
Test status
Simulation time 198756456 ps
CPU time 0.85 seconds
Started Jun 26 05:13:20 PM PDT 24
Finished Jun 26 05:13:22 PM PDT 24
Peak memory 206100 kb
Host smart-cb2bb801-e8b2-43a8-914d-39ccc38e5d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36503
72613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.3650372613
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.1238252238
Short name T581
Test name
Test status
Simulation time 5146540270 ps
CPU time 52.27 seconds
Started Jun 26 05:13:19 PM PDT 24
Finished Jun 26 05:14:11 PM PDT 24
Peak memory 206524 kb
Host smart-5ab7e806-c076-491c-95f8-4ca159a1905b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12382
52238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.1238252238
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.474360309
Short name T915
Test name
Test status
Simulation time 4671935084 ps
CPU time 42.69 seconds
Started Jun 26 05:13:21 PM PDT 24
Finished Jun 26 05:14:05 PM PDT 24
Peak memory 206544 kb
Host smart-7577d708-b062-4627-9622-d52398cb6e5b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=474360309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.474360309
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.3745555725
Short name T1046
Test name
Test status
Simulation time 152516611 ps
CPU time 0.78 seconds
Started Jun 26 05:13:27 PM PDT 24
Finished Jun 26 05:13:29 PM PDT 24
Peak memory 206144 kb
Host smart-b59bd0ec-fa1c-4ed1-8bb7-247125386cc0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3745555725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.3745555725
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.573337694
Short name T622
Test name
Test status
Simulation time 143420612 ps
CPU time 0.78 seconds
Started Jun 26 05:13:21 PM PDT 24
Finished Jun 26 05:13:22 PM PDT 24
Peak memory 206132 kb
Host smart-4a198351-7402-4ac3-9bbf-f15a3f3f4153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57333
7694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.573337694
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.385675775
Short name T2245
Test name
Test status
Simulation time 209092210 ps
CPU time 0.96 seconds
Started Jun 26 05:13:21 PM PDT 24
Finished Jun 26 05:13:24 PM PDT 24
Peak memory 206216 kb
Host smart-2b83df79-cbe5-461b-ad9e-469fd44fbf45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38567
5775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.385675775
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.2294377334
Short name T1067
Test name
Test status
Simulation time 155573438 ps
CPU time 0.82 seconds
Started Jun 26 05:13:19 PM PDT 24
Finished Jun 26 05:13:21 PM PDT 24
Peak memory 206128 kb
Host smart-71fd23c7-ee51-481e-9b03-5ad33dbd26d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22943
77334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.2294377334
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.1167303685
Short name T551
Test name
Test status
Simulation time 210509023 ps
CPU time 0.81 seconds
Started Jun 26 05:13:20 PM PDT 24
Finished Jun 26 05:13:22 PM PDT 24
Peak memory 206116 kb
Host smart-48f6f331-d750-41fa-8663-606c2ab151f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11673
03685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.1167303685
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.734078581
Short name T100
Test name
Test status
Simulation time 213736694 ps
CPU time 0.92 seconds
Started Jun 26 05:13:22 PM PDT 24
Finished Jun 26 05:13:24 PM PDT 24
Peak memory 206208 kb
Host smart-df6c78f1-a151-4665-819e-acbfa5bcadbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73407
8581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.734078581
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.147225484
Short name T1276
Test name
Test status
Simulation time 165387925 ps
CPU time 0.91 seconds
Started Jun 26 05:13:28 PM PDT 24
Finished Jun 26 05:13:29 PM PDT 24
Peak memory 206140 kb
Host smart-fe4f16be-eddb-43c3-857d-7a58587e9956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14722
5484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.147225484
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.2271775836
Short name T2136
Test name
Test status
Simulation time 237386473 ps
CPU time 1.06 seconds
Started Jun 26 05:13:21 PM PDT 24
Finished Jun 26 05:13:24 PM PDT 24
Peak memory 206136 kb
Host smart-592857c7-65f5-4adc-863b-0b904345b5a4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2271775836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.2271775836
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.1523317804
Short name T2384
Test name
Test status
Simulation time 164201733 ps
CPU time 0.78 seconds
Started Jun 26 05:13:21 PM PDT 24
Finished Jun 26 05:13:22 PM PDT 24
Peak memory 206212 kb
Host smart-ba811307-aec0-45b3-b781-4df6849864f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15233
17804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.1523317804
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.2733669363
Short name T2027
Test name
Test status
Simulation time 40152703 ps
CPU time 0.65 seconds
Started Jun 26 05:13:27 PM PDT 24
Finished Jun 26 05:13:28 PM PDT 24
Peak memory 206204 kb
Host smart-48df54e2-c044-4697-a30d-3c52f67d6553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27336
69363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.2733669363
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.138768155
Short name T692
Test name
Test status
Simulation time 9826105191 ps
CPU time 21.72 seconds
Started Jun 26 05:13:21 PM PDT 24
Finished Jun 26 05:13:43 PM PDT 24
Peak memory 206456 kb
Host smart-132b00f9-6a5d-4958-9040-eb10c0bdde9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13876
8155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.138768155
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.1280052394
Short name T463
Test name
Test status
Simulation time 210575485 ps
CPU time 0.87 seconds
Started Jun 26 05:13:22 PM PDT 24
Finished Jun 26 05:13:24 PM PDT 24
Peak memory 206200 kb
Host smart-473ff7d4-a6ca-4598-bfc5-458f1971b44c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12800
52394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.1280052394
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.4277170890
Short name T2526
Test name
Test status
Simulation time 269640913 ps
CPU time 0.95 seconds
Started Jun 26 05:13:18 PM PDT 24
Finished Jun 26 05:13:20 PM PDT 24
Peak memory 206216 kb
Host smart-9181f0d6-64de-4c06-8a03-19c8eff7cdaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42771
70890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.4277170890
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.1792178120
Short name T420
Test name
Test status
Simulation time 10524204314 ps
CPU time 65.54 seconds
Started Jun 26 05:13:26 PM PDT 24
Finished Jun 26 05:14:32 PM PDT 24
Peak memory 206464 kb
Host smart-bf68d65f-0bfb-4fd4-9529-690311c8c1cf
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1792178120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.1792178120
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.3548682118
Short name T2011
Test name
Test status
Simulation time 12592576561 ps
CPU time 246.21 seconds
Started Jun 26 05:13:26 PM PDT 24
Finished Jun 26 05:17:33 PM PDT 24
Peak memory 206424 kb
Host smart-dc115d6d-7368-479a-b15a-11eb4731af93
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3548682118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.3548682118
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.4068641768
Short name T2070
Test name
Test status
Simulation time 12221412232 ps
CPU time 81.73 seconds
Started Jun 26 05:13:28 PM PDT 24
Finished Jun 26 05:14:50 PM PDT 24
Peak memory 206436 kb
Host smart-806e4b1f-82fa-431f-a9a1-6ba868d2d122
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4068641768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.4068641768
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.1166242963
Short name T1094
Test name
Test status
Simulation time 176407655 ps
CPU time 0.8 seconds
Started Jun 26 05:13:28 PM PDT 24
Finished Jun 26 05:13:30 PM PDT 24
Peak memory 206200 kb
Host smart-05a665a9-480a-4b01-a30b-4d817ad14beb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11662
42963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.1166242963
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.1987371573
Short name T1064
Test name
Test status
Simulation time 174645691 ps
CPU time 0.87 seconds
Started Jun 26 05:13:25 PM PDT 24
Finished Jun 26 05:13:27 PM PDT 24
Peak memory 206192 kb
Host smart-43777c63-482c-4cd6-b98a-21e0d0401858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19873
71573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.1987371573
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.2770683589
Short name T680
Test name
Test status
Simulation time 155288373 ps
CPU time 0.75 seconds
Started Jun 26 05:13:27 PM PDT 24
Finished Jun 26 05:13:29 PM PDT 24
Peak memory 206212 kb
Host smart-ad9595b0-5423-47a3-a90c-fd215b0c1975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27706
83589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.2770683589
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.2074838185
Short name T1915
Test name
Test status
Simulation time 164167595 ps
CPU time 0.78 seconds
Started Jun 26 05:13:28 PM PDT 24
Finished Jun 26 05:13:30 PM PDT 24
Peak memory 206116 kb
Host smart-5d8790ad-d6dc-413c-9508-ed9338ca3930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20748
38185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.2074838185
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.880462187
Short name T42
Test name
Test status
Simulation time 168005276 ps
CPU time 0.82 seconds
Started Jun 26 05:13:29 PM PDT 24
Finished Jun 26 05:13:31 PM PDT 24
Peak memory 206212 kb
Host smart-1c06072d-ec7b-4460-b3b4-97b9aa776791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88046
2187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.880462187
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.2425147594
Short name T2083
Test name
Test status
Simulation time 240136525 ps
CPU time 1.02 seconds
Started Jun 26 05:13:29 PM PDT 24
Finished Jun 26 05:13:31 PM PDT 24
Peak memory 206224 kb
Host smart-24911409-e849-4dc7-888e-a82afb3b5893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24251
47594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.2425147594
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.3575844706
Short name T743
Test name
Test status
Simulation time 4206049350 ps
CPU time 30.16 seconds
Started Jun 26 05:13:29 PM PDT 24
Finished Jun 26 05:14:00 PM PDT 24
Peak memory 206532 kb
Host smart-b1c56aa4-5515-44a2-8660-365ec0926888
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3575844706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.3575844706
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.1633143856
Short name T492
Test name
Test status
Simulation time 154795527 ps
CPU time 0.79 seconds
Started Jun 26 05:13:26 PM PDT 24
Finished Jun 26 05:13:28 PM PDT 24
Peak memory 206128 kb
Host smart-a96fbb0f-cf27-47e8-9820-671881370c7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16331
43856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.1633143856
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.4223912402
Short name T1209
Test name
Test status
Simulation time 204888055 ps
CPU time 0.81 seconds
Started Jun 26 05:13:30 PM PDT 24
Finished Jun 26 05:13:32 PM PDT 24
Peak memory 206208 kb
Host smart-c5b6a4ab-1f1f-42e6-96c8-9548a907492a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42239
12402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.4223912402
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.1425954377
Short name T2091
Test name
Test status
Simulation time 4964209233 ps
CPU time 134.82 seconds
Started Jun 26 05:13:29 PM PDT 24
Finished Jun 26 05:15:45 PM PDT 24
Peak memory 206508 kb
Host smart-3751762b-ade2-4536-a92b-a849139fe64d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14259
54377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.1425954377
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.450214621
Short name T2459
Test name
Test status
Simulation time 4316099159 ps
CPU time 4.83 seconds
Started Jun 26 05:13:36 PM PDT 24
Finished Jun 26 05:13:42 PM PDT 24
Peak memory 206368 kb
Host smart-967a8b5b-7e29-4181-9ea4-250ade67684e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=450214621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.450214621
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.859755894
Short name T1208
Test name
Test status
Simulation time 13388669378 ps
CPU time 12.05 seconds
Started Jun 26 05:13:34 PM PDT 24
Finished Jun 26 05:13:47 PM PDT 24
Peak memory 206296 kb
Host smart-166fa4a0-d9ad-41f3-bc4a-c86d0e89e88c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=859755894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.859755894
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.430605064
Short name T230
Test name
Test status
Simulation time 23356584611 ps
CPU time 23.06 seconds
Started Jun 26 05:13:38 PM PDT 24
Finished Jun 26 05:14:02 PM PDT 24
Peak memory 206600 kb
Host smart-4626196d-7807-49cd-a9f6-fffb70a38cc0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=430605064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.430605064
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.3931826312
Short name T2029
Test name
Test status
Simulation time 208687799 ps
CPU time 0.91 seconds
Started Jun 26 05:13:36 PM PDT 24
Finished Jun 26 05:13:38 PM PDT 24
Peak memory 206396 kb
Host smart-714550d0-b1ff-4bfb-b79c-71bfc8d1787a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39318
26312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.3931826312
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.1854689523
Short name T1451
Test name
Test status
Simulation time 146020982 ps
CPU time 0.75 seconds
Started Jun 26 05:13:35 PM PDT 24
Finished Jun 26 05:13:37 PM PDT 24
Peak memory 206204 kb
Host smart-606d421a-e468-43d5-a8ba-7084b13aaa48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18546
89523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.1854689523
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.869852507
Short name T1711
Test name
Test status
Simulation time 442469237 ps
CPU time 1.36 seconds
Started Jun 26 05:13:38 PM PDT 24
Finished Jun 26 05:13:40 PM PDT 24
Peak memory 206212 kb
Host smart-7aee924d-9cd0-42f0-98c0-278fddabd9ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86985
2507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.869852507
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.500930784
Short name T1914
Test name
Test status
Simulation time 1271815354 ps
CPU time 2.79 seconds
Started Jun 26 05:13:34 PM PDT 24
Finished Jun 26 05:13:38 PM PDT 24
Peak memory 206456 kb
Host smart-0e4aa2cd-f62b-435d-a140-9dea3835ecbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50093
0784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.500930784
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.1267408995
Short name T1248
Test name
Test status
Simulation time 17924304207 ps
CPU time 32.33 seconds
Started Jun 26 05:13:37 PM PDT 24
Finished Jun 26 05:14:11 PM PDT 24
Peak memory 206512 kb
Host smart-b00e11c5-8c71-4d22-ab76-992ec3fa268e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12674
08995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.1267408995
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.722174633
Short name T1637
Test name
Test status
Simulation time 461921014 ps
CPU time 1.44 seconds
Started Jun 26 05:13:34 PM PDT 24
Finished Jun 26 05:13:36 PM PDT 24
Peak memory 206200 kb
Host smart-0e18a859-91c2-4792-92da-9a9ea97adc0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72217
4633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.722174633
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.3968827376
Short name T2535
Test name
Test status
Simulation time 148773899 ps
CPU time 0.79 seconds
Started Jun 26 05:13:36 PM PDT 24
Finished Jun 26 05:13:38 PM PDT 24
Peak memory 206200 kb
Host smart-29609ef7-a970-4bc0-82fa-ef60f4faf1c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39688
27376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.3968827376
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.3892055756
Short name T1775
Test name
Test status
Simulation time 44029304 ps
CPU time 0.66 seconds
Started Jun 26 05:13:36 PM PDT 24
Finished Jun 26 05:13:38 PM PDT 24
Peak memory 206124 kb
Host smart-3371a189-7eea-4d30-8bda-941f940e6cb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38920
55756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.3892055756
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.877982485
Short name T1066
Test name
Test status
Simulation time 786503362 ps
CPU time 1.86 seconds
Started Jun 26 05:13:38 PM PDT 24
Finished Jun 26 05:13:41 PM PDT 24
Peak memory 206424 kb
Host smart-168afb88-92bf-4c76-8af5-09566d2bfa0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87798
2485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.877982485
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.2800500507
Short name T1197
Test name
Test status
Simulation time 194364400 ps
CPU time 2.14 seconds
Started Jun 26 05:13:35 PM PDT 24
Finished Jun 26 05:13:39 PM PDT 24
Peak memory 206384 kb
Host smart-941b484f-eed3-489a-a232-d13521031883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28005
00507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.2800500507
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.4057256291
Short name T1137
Test name
Test status
Simulation time 281218195 ps
CPU time 0.9 seconds
Started Jun 26 05:13:48 PM PDT 24
Finished Jun 26 05:13:49 PM PDT 24
Peak memory 206224 kb
Host smart-d3083d17-a216-4c1b-b482-4db12e2bfdb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40572
56291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.4057256291
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.3333488392
Short name T1499
Test name
Test status
Simulation time 138970547 ps
CPU time 0.8 seconds
Started Jun 26 05:13:50 PM PDT 24
Finished Jun 26 05:13:52 PM PDT 24
Peak memory 206136 kb
Host smart-e558427f-e9d3-4fa6-a1b2-78269cb89ab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33334
88392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.3333488392
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.635596693
Short name T1418
Test name
Test status
Simulation time 157348857 ps
CPU time 0.81 seconds
Started Jun 26 05:13:39 PM PDT 24
Finished Jun 26 05:13:41 PM PDT 24
Peak memory 206188 kb
Host smart-39603872-907e-4e0e-a051-81c184b50793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63559
6693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.635596693
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.3035804317
Short name T1684
Test name
Test status
Simulation time 174776905 ps
CPU time 0.83 seconds
Started Jun 26 05:13:35 PM PDT 24
Finished Jun 26 05:13:36 PM PDT 24
Peak memory 206124 kb
Host smart-1545cf67-a431-494e-89a0-f884fbbffac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30358
04317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.3035804317
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.396078135
Short name T2178
Test name
Test status
Simulation time 23358603090 ps
CPU time 24.45 seconds
Started Jun 26 05:13:36 PM PDT 24
Finished Jun 26 05:14:01 PM PDT 24
Peak memory 206236 kb
Host smart-ddb06dd6-0ba3-4224-97ca-e676c927513e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39607
8135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.396078135
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.1750885493
Short name T1219
Test name
Test status
Simulation time 3378265207 ps
CPU time 3.98 seconds
Started Jun 26 05:13:37 PM PDT 24
Finished Jun 26 05:13:42 PM PDT 24
Peak memory 206284 kb
Host smart-bd65e125-c6ec-4428-ae22-3e5f289cfd79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17508
85493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.1750885493
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.3655046693
Short name T740
Test name
Test status
Simulation time 12249738451 ps
CPU time 115.54 seconds
Started Jun 26 05:13:36 PM PDT 24
Finished Jun 26 05:15:33 PM PDT 24
Peak memory 206548 kb
Host smart-87373786-a5c7-46a7-a640-6713634dd639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36550
46693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.3655046693
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.2097453919
Short name T2200
Test name
Test status
Simulation time 6848349291 ps
CPU time 49.2 seconds
Started Jun 26 05:13:36 PM PDT 24
Finished Jun 26 05:14:26 PM PDT 24
Peak memory 206500 kb
Host smart-206e6930-da36-4e87-9865-148f1c806f5b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2097453919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.2097453919
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.4011243303
Short name T2126
Test name
Test status
Simulation time 233907641 ps
CPU time 0.85 seconds
Started Jun 26 05:13:50 PM PDT 24
Finished Jun 26 05:13:52 PM PDT 24
Peak memory 206248 kb
Host smart-eb5d8a2d-cf58-46a3-af70-1e615f0d18b6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4011243303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.4011243303
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.2718648570
Short name T1285
Test name
Test status
Simulation time 202989908 ps
CPU time 0.84 seconds
Started Jun 26 05:13:35 PM PDT 24
Finished Jun 26 05:13:37 PM PDT 24
Peak memory 206212 kb
Host smart-4c4b92d2-de09-473d-90cd-d2fb8b46ab8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27186
48570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.2718648570
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.2061855576
Short name T2079
Test name
Test status
Simulation time 3977746533 ps
CPU time 36.69 seconds
Started Jun 26 05:13:34 PM PDT 24
Finished Jun 26 05:14:12 PM PDT 24
Peak memory 206520 kb
Host smart-9973dc2a-081d-4082-ad2a-441878a1b1db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20618
55576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.2061855576
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.3308145696
Short name T2024
Test name
Test status
Simulation time 3915686273 ps
CPU time 28.22 seconds
Started Jun 26 05:13:33 PM PDT 24
Finished Jun 26 05:14:02 PM PDT 24
Peak memory 206464 kb
Host smart-8e9303f6-7a1c-4df5-90a9-f8642c8a7a94
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3308145696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.3308145696
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.3545438546
Short name T1589
Test name
Test status
Simulation time 149802729 ps
CPU time 0.82 seconds
Started Jun 26 05:14:02 PM PDT 24
Finished Jun 26 05:14:04 PM PDT 24
Peak memory 206228 kb
Host smart-340c0c0e-9ace-4beb-b9f1-bee2e72e938f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3545438546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.3545438546
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.2783359287
Short name T767
Test name
Test status
Simulation time 200191660 ps
CPU time 0.79 seconds
Started Jun 26 05:13:33 PM PDT 24
Finished Jun 26 05:13:35 PM PDT 24
Peak memory 206200 kb
Host smart-9599e3a4-23ba-4ee4-91d1-dde66f677fae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27833
59287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.2783359287
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.2360935446
Short name T121
Test name
Test status
Simulation time 194396929 ps
CPU time 0.86 seconds
Started Jun 26 05:13:39 PM PDT 24
Finished Jun 26 05:13:40 PM PDT 24
Peak memory 206404 kb
Host smart-bd35672f-aedd-49e8-8e8c-bf56af137c93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23609
35446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.2360935446
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.1277848204
Short name T1808
Test name
Test status
Simulation time 186363569 ps
CPU time 0.89 seconds
Started Jun 26 05:13:39 PM PDT 24
Finished Jun 26 05:13:41 PM PDT 24
Peak memory 206192 kb
Host smart-22344812-4dcf-4484-b0cc-314bef746f3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12778
48204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.1277848204
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.4091707236
Short name T993
Test name
Test status
Simulation time 173440706 ps
CPU time 0.84 seconds
Started Jun 26 05:13:35 PM PDT 24
Finished Jun 26 05:13:37 PM PDT 24
Peak memory 206148 kb
Host smart-98f42c30-15d1-4b34-af6f-3d4ba817c1d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40917
07236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.4091707236
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.2339987260
Short name T739
Test name
Test status
Simulation time 170158898 ps
CPU time 0.78 seconds
Started Jun 26 05:13:34 PM PDT 24
Finished Jun 26 05:13:36 PM PDT 24
Peak memory 206184 kb
Host smart-fcf6f18b-7dc0-4a2f-89c6-e22f0b9b38e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23399
87260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.2339987260
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.2176699603
Short name T1373
Test name
Test status
Simulation time 175652906 ps
CPU time 0.78 seconds
Started Jun 26 05:13:42 PM PDT 24
Finished Jun 26 05:13:43 PM PDT 24
Peak memory 206156 kb
Host smart-3047ef4c-606d-46c3-89e7-9d0a22e461b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21766
99603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.2176699603
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.3597442774
Short name T1233
Test name
Test status
Simulation time 247333473 ps
CPU time 0.97 seconds
Started Jun 26 05:13:39 PM PDT 24
Finished Jun 26 05:13:41 PM PDT 24
Peak memory 206200 kb
Host smart-38949f8b-e7ad-49bb-a8a2-19ae0da5fadd
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3597442774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.3597442774
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.2177218022
Short name T867
Test name
Test status
Simulation time 142965679 ps
CPU time 0.77 seconds
Started Jun 26 05:13:34 PM PDT 24
Finished Jun 26 05:13:36 PM PDT 24
Peak memory 206172 kb
Host smart-2b7dede2-8ae5-45fb-abef-41bd949e70fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21772
18022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.2177218022
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.1920995537
Short name T1471
Test name
Test status
Simulation time 32627897 ps
CPU time 0.62 seconds
Started Jun 26 05:13:43 PM PDT 24
Finished Jun 26 05:13:44 PM PDT 24
Peak memory 206024 kb
Host smart-a6796205-2ac5-4206-9d67-dba5280c306d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19209
95537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.1920995537
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.3308621200
Short name T2226
Test name
Test status
Simulation time 8503786642 ps
CPU time 19.23 seconds
Started Jun 26 05:13:44 PM PDT 24
Finished Jun 26 05:14:04 PM PDT 24
Peak memory 206532 kb
Host smart-a7fbaea9-9aa7-4805-9fe1-642f60d84e55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33086
21200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.3308621200
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.654384692
Short name T657
Test name
Test status
Simulation time 186445286 ps
CPU time 0.85 seconds
Started Jun 26 05:13:45 PM PDT 24
Finished Jun 26 05:13:46 PM PDT 24
Peak memory 206196 kb
Host smart-bb422c25-6322-4bdc-a54e-bfa398b0bdc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65438
4692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.654384692
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.3520144041
Short name T2572
Test name
Test status
Simulation time 221368319 ps
CPU time 0.85 seconds
Started Jun 26 05:13:42 PM PDT 24
Finished Jun 26 05:13:44 PM PDT 24
Peak memory 206108 kb
Host smart-4522311a-ccac-405a-9114-172352d288ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35201
44041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.3520144041
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.1116980974
Short name T180
Test name
Test status
Simulation time 6800931686 ps
CPU time 46.74 seconds
Started Jun 26 05:13:41 PM PDT 24
Finished Jun 26 05:14:29 PM PDT 24
Peak memory 206456 kb
Host smart-db72f7c7-bda2-4e5d-8932-de23f392a3bc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1116980974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.1116980974
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.585842974
Short name T2381
Test name
Test status
Simulation time 9832882943 ps
CPU time 92.34 seconds
Started Jun 26 05:13:42 PM PDT 24
Finished Jun 26 05:15:16 PM PDT 24
Peak memory 206576 kb
Host smart-134f896b-da66-4e46-85c4-3691799b4881
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=585842974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.585842974
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.1676181532
Short name T1310
Test name
Test status
Simulation time 12504086511 ps
CPU time 67.27 seconds
Started Jun 26 05:13:43 PM PDT 24
Finished Jun 26 05:14:51 PM PDT 24
Peak memory 206724 kb
Host smart-98bd46d8-11c6-4f4e-8d8d-815a3e4c0d4f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1676181532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.1676181532
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.1648875334
Short name T1626
Test name
Test status
Simulation time 202230327 ps
CPU time 0.82 seconds
Started Jun 26 05:13:51 PM PDT 24
Finished Jun 26 05:13:53 PM PDT 24
Peak memory 206140 kb
Host smart-05c45bf8-aa6d-4efa-9ed0-1f1ba38fdbf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16488
75334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.1648875334
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.3376829934
Short name T1673
Test name
Test status
Simulation time 169746491 ps
CPU time 0.79 seconds
Started Jun 26 05:13:44 PM PDT 24
Finished Jun 26 05:13:45 PM PDT 24
Peak memory 206400 kb
Host smart-32d458e6-c74e-421d-a89e-e0a5c5f1d38f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33768
29934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.3376829934
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.3111825318
Short name T1623
Test name
Test status
Simulation time 155441278 ps
CPU time 0.79 seconds
Started Jun 26 05:13:43 PM PDT 24
Finished Jun 26 05:13:45 PM PDT 24
Peak memory 206204 kb
Host smart-dd3b29ea-26e7-48df-ab86-7af1c57106ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31118
25318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.3111825318
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.2715922306
Short name T2271
Test name
Test status
Simulation time 151086232 ps
CPU time 0.78 seconds
Started Jun 26 05:13:42 PM PDT 24
Finished Jun 26 05:13:44 PM PDT 24
Peak memory 206168 kb
Host smart-67f4187f-be3d-41f1-aeb1-ec723de41181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27159
22306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.2715922306
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.1066735385
Short name T1245
Test name
Test status
Simulation time 173483294 ps
CPU time 0.81 seconds
Started Jun 26 05:13:41 PM PDT 24
Finished Jun 26 05:13:42 PM PDT 24
Peak memory 206224 kb
Host smart-6bc05984-2477-429a-96a8-6e7ae60e1f0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10667
35385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.1066735385
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.3806296660
Short name T721
Test name
Test status
Simulation time 256309448 ps
CPU time 0.96 seconds
Started Jun 26 05:13:42 PM PDT 24
Finished Jun 26 05:13:44 PM PDT 24
Peak memory 206184 kb
Host smart-02e1dba2-db18-47c2-a0f8-736155350d8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38062
96660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.3806296660
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.2341270171
Short name T1894
Test name
Test status
Simulation time 4444875751 ps
CPU time 117.21 seconds
Started Jun 26 05:13:44 PM PDT 24
Finished Jun 26 05:15:41 PM PDT 24
Peak memory 206540 kb
Host smart-47e2c9aa-32fc-4d01-a07f-3109ac2a5616
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2341270171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.2341270171
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.2360791208
Short name T981
Test name
Test status
Simulation time 171509720 ps
CPU time 0.8 seconds
Started Jun 26 05:13:42 PM PDT 24
Finished Jun 26 05:13:44 PM PDT 24
Peak memory 206128 kb
Host smart-32bf94c1-6402-47ac-8d5e-e26b75579f60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23607
91208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.2360791208
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.2100563618
Short name T1529
Test name
Test status
Simulation time 175968223 ps
CPU time 0.79 seconds
Started Jun 26 05:13:43 PM PDT 24
Finished Jun 26 05:13:45 PM PDT 24
Peak memory 206172 kb
Host smart-c2bca27a-475b-443a-ab36-e1978d415f93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21005
63618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.2100563618
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.3999233907
Short name T817
Test name
Test status
Simulation time 4679810875 ps
CPU time 32.73 seconds
Started Jun 26 05:13:42 PM PDT 24
Finished Jun 26 05:14:16 PM PDT 24
Peak memory 206404 kb
Host smart-bcfd40b8-fa36-49ae-a7f9-e5928d42c8aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39992
33907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.3999233907
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.3823123171
Short name T486
Test name
Test status
Simulation time 3953714998 ps
CPU time 4.92 seconds
Started Jun 26 05:13:51 PM PDT 24
Finished Jun 26 05:13:56 PM PDT 24
Peak memory 206180 kb
Host smart-79a94b60-9c0f-44a6-a75f-7794932a2d9c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3823123171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.3823123171
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.3688448567
Short name T8
Test name
Test status
Simulation time 13422816683 ps
CPU time 11.69 seconds
Started Jun 26 05:13:51 PM PDT 24
Finished Jun 26 05:14:03 PM PDT 24
Peak memory 206468 kb
Host smart-1b4679e5-23f9-4b5c-b3fa-34036287b1ed
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3688448567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.3688448567
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.376682502
Short name T1077
Test name
Test status
Simulation time 23325480714 ps
CPU time 22.74 seconds
Started Jun 26 05:14:00 PM PDT 24
Finished Jun 26 05:14:23 PM PDT 24
Peak memory 206316 kb
Host smart-0db81e6e-2383-4fc1-a6bf-8cf01fd58d19
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=376682502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.376682502
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.738778214
Short name T2382
Test name
Test status
Simulation time 162320107 ps
CPU time 0.83 seconds
Started Jun 26 05:13:52 PM PDT 24
Finished Jun 26 05:13:54 PM PDT 24
Peak memory 206224 kb
Host smart-952374b1-cbc6-4425-9256-1c75cd12dbc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73877
8214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.738778214
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.558444903
Short name T1158
Test name
Test status
Simulation time 162516626 ps
CPU time 0.84 seconds
Started Jun 26 05:14:01 PM PDT 24
Finished Jun 26 05:14:02 PM PDT 24
Peak memory 206444 kb
Host smart-bc8a1c40-6aed-4aec-a964-05527bd92087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55844
4903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.558444903
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.3921566052
Short name T759
Test name
Test status
Simulation time 584555768 ps
CPU time 1.63 seconds
Started Jun 26 05:14:02 PM PDT 24
Finished Jun 26 05:14:05 PM PDT 24
Peak memory 206448 kb
Host smart-21dbe128-0140-4b1c-82b0-e61f3f20aa9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39215
66052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.3921566052
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.2318063450
Short name T979
Test name
Test status
Simulation time 783924887 ps
CPU time 2.03 seconds
Started Jun 26 05:13:49 PM PDT 24
Finished Jun 26 05:13:52 PM PDT 24
Peak memory 206316 kb
Host smart-2f9022df-d588-4429-b9a1-494b93ff35cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23180
63450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.2318063450
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.779157289
Short name T1187
Test name
Test status
Simulation time 6469065998 ps
CPU time 14.93 seconds
Started Jun 26 05:14:01 PM PDT 24
Finished Jun 26 05:14:17 PM PDT 24
Peak memory 206436 kb
Host smart-6793cf46-eb45-4f52-b9d7-7536a0bb2fcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77915
7289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.779157289
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.160220341
Short name T1901
Test name
Test status
Simulation time 459256793 ps
CPU time 1.47 seconds
Started Jun 26 05:14:00 PM PDT 24
Finished Jun 26 05:14:03 PM PDT 24
Peak memory 206124 kb
Host smart-cbb1298e-13c0-40df-8824-c957143e6203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16022
0341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.160220341
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.3635997042
Short name T2221
Test name
Test status
Simulation time 139162278 ps
CPU time 0.78 seconds
Started Jun 26 05:14:01 PM PDT 24
Finished Jun 26 05:14:04 PM PDT 24
Peak memory 206120 kb
Host smart-06d78c1e-0361-485d-905a-1d4df58b5fef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36359
97042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.3635997042
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.2946721975
Short name T1359
Test name
Test status
Simulation time 27027628 ps
CPU time 0.64 seconds
Started Jun 26 05:14:02 PM PDT 24
Finished Jun 26 05:14:04 PM PDT 24
Peak memory 206220 kb
Host smart-0111075e-5fe2-40d8-8add-9cca7e463682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29467
21975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.2946721975
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.2711310094
Short name T2238
Test name
Test status
Simulation time 893978847 ps
CPU time 2.13 seconds
Started Jun 26 05:14:01 PM PDT 24
Finished Jun 26 05:14:04 PM PDT 24
Peak memory 206428 kb
Host smart-d395840a-f238-447c-af7d-809984c71488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27113
10094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.2711310094
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.1959378588
Short name T1206
Test name
Test status
Simulation time 189134779 ps
CPU time 1.38 seconds
Started Jun 26 05:14:01 PM PDT 24
Finished Jun 26 05:14:04 PM PDT 24
Peak memory 206452 kb
Host smart-bdc4fc62-b5fc-4d0d-95a8-15eb46cd29e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19593
78588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.1959378588
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.3913435338
Short name T2465
Test name
Test status
Simulation time 209735208 ps
CPU time 0.85 seconds
Started Jun 26 05:14:10 PM PDT 24
Finished Jun 26 05:14:13 PM PDT 24
Peak memory 206140 kb
Host smart-64dda291-2cc7-412f-b7bc-cff32d49306e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39134
35338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.3913435338
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.1641169044
Short name T518
Test name
Test status
Simulation time 172138102 ps
CPU time 0.78 seconds
Started Jun 26 05:14:09 PM PDT 24
Finished Jun 26 05:14:11 PM PDT 24
Peak memory 206188 kb
Host smart-cd7dbe1c-9221-47fd-ab22-07daf8596799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16411
69044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.1641169044
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.1731194251
Short name T380
Test name
Test status
Simulation time 178158083 ps
CPU time 0.85 seconds
Started Jun 26 05:14:04 PM PDT 24
Finished Jun 26 05:14:06 PM PDT 24
Peak memory 206216 kb
Host smart-ea3c00ee-14ae-429f-8b9e-9e17c9037854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17311
94251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.1731194251
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.2837359944
Short name T1348
Test name
Test status
Simulation time 181219454 ps
CPU time 0.85 seconds
Started Jun 26 05:13:59 PM PDT 24
Finished Jun 26 05:14:01 PM PDT 24
Peak memory 206216 kb
Host smart-bc8ea771-9aeb-4b38-9310-b13353117933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28373
59944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.2837359944
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.3201416704
Short name T1388
Test name
Test status
Simulation time 23354947409 ps
CPU time 23.01 seconds
Started Jun 26 05:14:00 PM PDT 24
Finished Jun 26 05:14:24 PM PDT 24
Peak memory 206316 kb
Host smart-ea3b7c7c-ee7d-46af-8917-f8ca1bc4eed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32014
16704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.3201416704
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.982245659
Short name T1520
Test name
Test status
Simulation time 3346456292 ps
CPU time 3.94 seconds
Started Jun 26 05:14:02 PM PDT 24
Finished Jun 26 05:14:07 PM PDT 24
Peak memory 206288 kb
Host smart-cd1af80c-f377-4558-92ff-81faf9c3453c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98224
5659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.982245659
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.4132401431
Short name T457
Test name
Test status
Simulation time 9524272880 ps
CPU time 254.93 seconds
Started Jun 26 05:14:01 PM PDT 24
Finished Jun 26 05:18:17 PM PDT 24
Peak memory 206464 kb
Host smart-38656d1a-7e03-4c80-87c6-364bb3138794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41324
01431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.4132401431
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.266909306
Short name T911
Test name
Test status
Simulation time 5178141178 ps
CPU time 48.22 seconds
Started Jun 26 05:14:01 PM PDT 24
Finished Jun 26 05:14:51 PM PDT 24
Peak memory 206516 kb
Host smart-c512e63b-3aad-4fd8-a29f-3bc3cd6d430e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=266909306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.266909306
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.2129334325
Short name T1652
Test name
Test status
Simulation time 273612438 ps
CPU time 0.91 seconds
Started Jun 26 05:14:09 PM PDT 24
Finished Jun 26 05:14:13 PM PDT 24
Peak memory 206144 kb
Host smart-34816e29-0e65-4e64-8d80-642ab6484d23
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2129334325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.2129334325
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.1166094683
Short name T1457
Test name
Test status
Simulation time 200948842 ps
CPU time 0.86 seconds
Started Jun 26 05:14:04 PM PDT 24
Finished Jun 26 05:14:06 PM PDT 24
Peak memory 206204 kb
Host smart-fbee3d9c-a550-4a30-8a0a-82d409508f4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11660
94683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.1166094683
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.2823070712
Short name T162
Test name
Test status
Simulation time 7502812783 ps
CPU time 212.16 seconds
Started Jun 26 05:14:02 PM PDT 24
Finished Jun 26 05:17:36 PM PDT 24
Peak memory 206528 kb
Host smart-0ffb4342-b34f-4278-9946-8c91cf9d1350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28230
70712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.2823070712
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.563970478
Short name T525
Test name
Test status
Simulation time 4820061088 ps
CPU time 45.45 seconds
Started Jun 26 05:14:02 PM PDT 24
Finished Jun 26 05:14:49 PM PDT 24
Peak memory 206568 kb
Host smart-cdc111b5-ae6c-46b2-adc2-4bcaef01be9b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=563970478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.563970478
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.2986872047
Short name T2533
Test name
Test status
Simulation time 171550561 ps
CPU time 0.86 seconds
Started Jun 26 05:14:09 PM PDT 24
Finished Jun 26 05:14:12 PM PDT 24
Peak memory 206196 kb
Host smart-267e5038-ec5c-4a71-8397-ca21331cfe54
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2986872047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.2986872047
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.3244813449
Short name T1124
Test name
Test status
Simulation time 176177104 ps
CPU time 0.78 seconds
Started Jun 26 05:14:01 PM PDT 24
Finished Jun 26 05:14:04 PM PDT 24
Peak memory 206212 kb
Host smart-3a4868e7-27c4-46fc-9eb4-e0cd24680c87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32448
13449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.3244813449
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.976977531
Short name T137
Test name
Test status
Simulation time 207767049 ps
CPU time 0.88 seconds
Started Jun 26 05:13:59 PM PDT 24
Finished Jun 26 05:14:00 PM PDT 24
Peak memory 206152 kb
Host smart-81d06980-b850-4fe4-85ca-b1dbfbbafd65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97697
7531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.976977531
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.783722963
Short name T522
Test name
Test status
Simulation time 196327391 ps
CPU time 0.85 seconds
Started Jun 26 05:14:04 PM PDT 24
Finished Jun 26 05:14:06 PM PDT 24
Peak memory 206216 kb
Host smart-900acaf9-316f-4a43-8961-a9a291e8d80b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78372
2963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.783722963
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.1445201264
Short name T1281
Test name
Test status
Simulation time 181406956 ps
CPU time 0.82 seconds
Started Jun 26 05:14:00 PM PDT 24
Finished Jun 26 05:14:01 PM PDT 24
Peak memory 206128 kb
Host smart-449b4c6c-9c78-4b7e-9bf1-0113f1edacde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14452
01264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.1445201264
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.3897885776
Short name T1057
Test name
Test status
Simulation time 148531428 ps
CPU time 0.82 seconds
Started Jun 26 05:14:02 PM PDT 24
Finished Jun 26 05:14:04 PM PDT 24
Peak memory 206112 kb
Host smart-2b08aa01-26e7-42ce-aa06-691ed6149353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38978
85776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.3897885776
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.1739825480
Short name T168
Test name
Test status
Simulation time 168525016 ps
CPU time 0.79 seconds
Started Jun 26 05:14:08 PM PDT 24
Finished Jun 26 05:14:11 PM PDT 24
Peak memory 206212 kb
Host smart-c27b0380-7cd0-4257-af87-fb5ab5ac9a6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17398
25480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.1739825480
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.3738424217
Short name T1636
Test name
Test status
Simulation time 243181606 ps
CPU time 0.93 seconds
Started Jun 26 05:13:59 PM PDT 24
Finished Jun 26 05:14:00 PM PDT 24
Peak memory 206148 kb
Host smart-3dfc29a2-30f9-4971-9240-529a58b9a7e1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3738424217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.3738424217
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.1683921802
Short name T1627
Test name
Test status
Simulation time 157012432 ps
CPU time 0.76 seconds
Started Jun 26 05:14:07 PM PDT 24
Finished Jun 26 05:14:09 PM PDT 24
Peak memory 206180 kb
Host smart-0eb61b4d-647f-4b17-91b0-02a91fe2af16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16839
21802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.1683921802
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.123240708
Short name T1149
Test name
Test status
Simulation time 37230984 ps
CPU time 0.66 seconds
Started Jun 26 05:14:10 PM PDT 24
Finished Jun 26 05:14:13 PM PDT 24
Peak memory 206116 kb
Host smart-04ff7846-7f97-4b53-9391-5fa17b7e2c16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12324
0708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.123240708
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.2700985615
Short name T267
Test name
Test status
Simulation time 13441593398 ps
CPU time 31.67 seconds
Started Jun 26 05:14:03 PM PDT 24
Finished Jun 26 05:14:36 PM PDT 24
Peak memory 206456 kb
Host smart-96ab7763-1710-45d0-b25f-f091f367a302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27009
85615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.2700985615
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.315000394
Short name T1145
Test name
Test status
Simulation time 158984896 ps
CPU time 0.86 seconds
Started Jun 26 05:14:09 PM PDT 24
Finished Jun 26 05:14:12 PM PDT 24
Peak memory 206188 kb
Host smart-e9163f97-a1ea-4103-8f7a-5b1a226e992c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31500
0394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.315000394
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.2171202326
Short name T1748
Test name
Test status
Simulation time 211915877 ps
CPU time 0.87 seconds
Started Jun 26 05:14:07 PM PDT 24
Finished Jun 26 05:14:09 PM PDT 24
Peak memory 206192 kb
Host smart-9a3da3be-0bfa-47b3-a52b-840bc47e1a4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21712
02326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.2171202326
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.2787941289
Short name T1878
Test name
Test status
Simulation time 16611517980 ps
CPU time 86.72 seconds
Started Jun 26 05:14:06 PM PDT 24
Finished Jun 26 05:15:35 PM PDT 24
Peak memory 206580 kb
Host smart-236cbc50-230d-4240-b879-2fcc1ab2079c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2787941289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.2787941289
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.2600386959
Short name T167
Test name
Test status
Simulation time 14960292451 ps
CPU time 78.63 seconds
Started Jun 26 05:14:02 PM PDT 24
Finished Jun 26 05:15:22 PM PDT 24
Peak memory 206480 kb
Host smart-52e9cc94-50e0-4eae-95ad-b7c37ca146f0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2600386959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.2600386959
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.4080519342
Short name T406
Test name
Test status
Simulation time 12517278415 ps
CPU time 250.83 seconds
Started Jun 26 05:14:07 PM PDT 24
Finished Jun 26 05:18:20 PM PDT 24
Peak memory 206464 kb
Host smart-cc53ad3f-9b77-4203-86b2-dc7a8d03dfa3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4080519342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.4080519342
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.3407325196
Short name T652
Test name
Test status
Simulation time 191582514 ps
CPU time 0.84 seconds
Started Jun 26 05:14:11 PM PDT 24
Finished Jun 26 05:14:14 PM PDT 24
Peak memory 206232 kb
Host smart-cb4e2a6c-7afa-48b6-8c5e-e50fa2fab8e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34073
25196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.3407325196
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.4210864383
Short name T1608
Test name
Test status
Simulation time 155632607 ps
CPU time 0.74 seconds
Started Jun 26 05:14:07 PM PDT 24
Finished Jun 26 05:14:09 PM PDT 24
Peak memory 206176 kb
Host smart-0dff09e3-d2d2-4579-be99-985b2f877df1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42108
64383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.4210864383
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.2623002250
Short name T1485
Test name
Test status
Simulation time 191708915 ps
CPU time 0.79 seconds
Started Jun 26 05:14:07 PM PDT 24
Finished Jun 26 05:14:10 PM PDT 24
Peak memory 206180 kb
Host smart-6b439cf1-3c95-4184-aaa1-7a2325c1dd17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26230
02250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.2623002250
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.2338048749
Short name T1685
Test name
Test status
Simulation time 182254963 ps
CPU time 0.77 seconds
Started Jun 26 05:14:09 PM PDT 24
Finished Jun 26 05:14:12 PM PDT 24
Peak memory 206200 kb
Host smart-e6217363-4b89-498a-a6b1-f0be51e6d323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23380
48749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.2338048749
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.3871918635
Short name T2575
Test name
Test status
Simulation time 146943061 ps
CPU time 0.77 seconds
Started Jun 26 05:14:04 PM PDT 24
Finished Jun 26 05:14:06 PM PDT 24
Peak memory 206128 kb
Host smart-8e2b6b2f-3a32-43fc-8fda-81af6e7f34f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38719
18635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.3871918635
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.3721452547
Short name T2390
Test name
Test status
Simulation time 234639571 ps
CPU time 0.93 seconds
Started Jun 26 05:14:03 PM PDT 24
Finished Jun 26 05:14:05 PM PDT 24
Peak memory 206224 kb
Host smart-359c4917-b7db-4913-aeb6-1aaf4a41d541
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37214
52547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.3721452547
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.342841763
Short name T1861
Test name
Test status
Simulation time 3989826424 ps
CPU time 28.73 seconds
Started Jun 26 05:14:01 PM PDT 24
Finished Jun 26 05:14:32 PM PDT 24
Peak memory 206388 kb
Host smart-8374f13b-fbb4-49fc-9fe1-b0c5a085f9c3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=342841763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.342841763
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.1104785998
Short name T1686
Test name
Test status
Simulation time 191036893 ps
CPU time 0.8 seconds
Started Jun 26 05:14:06 PM PDT 24
Finished Jun 26 05:14:08 PM PDT 24
Peak memory 206180 kb
Host smart-1c4d296f-846f-4f1b-b9dc-cf184bbdb6ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11047
85998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.1104785998
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.1715058672
Short name T1034
Test name
Test status
Simulation time 172116550 ps
CPU time 0.78 seconds
Started Jun 26 05:14:07 PM PDT 24
Finished Jun 26 05:14:10 PM PDT 24
Peak memory 206176 kb
Host smart-988f4768-1b31-478c-b15c-9699a429c73b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17150
58672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.1715058672
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.3307188887
Short name T1676
Test name
Test status
Simulation time 4472999531 ps
CPU time 30.93 seconds
Started Jun 26 05:14:06 PM PDT 24
Finished Jun 26 05:14:38 PM PDT 24
Peak memory 206488 kb
Host smart-e7f2c8c9-a567-4f91-8568-22bbdd4782fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33071
88887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.3307188887
Directory /workspace/9.usbdev_streaming_out/latest
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