Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	120463	1		T1	2		T2	2		T3	3
all_values[1]	120463	1		T1	2		T2	2		T3	3
all_values[2]	120463	1		T1	2		T2	2		T3	3
all_values[3]	120463	1		T1	2		T2	2		T3	3
all_values[4]	120463	1		T1	2		T2	2		T3	3
all_values[5]	120463	1		T1	2		T2	2		T3	3
all_values[6]	120463	1		T1	2		T2	2		T3	3
all_values[7]	120463	1		T1	2		T2	2		T3	3
all_values[8]	120463	1		T1	2		T2	2		T3	3
all_values[9]	120463	1		T1	2		T2	2		T3	3
all_values[10]	120463	1		T1	2		T2	2		T3	3
all_values[11]	120463	1		T1	2		T2	2		T3	3
all_values[12]	120463	1		T1	2		T2	2		T3	3
all_values[13]	120463	1		T1	2		T2	2		T3	3
all_values[14]	120463	1		T1	2		T2	2		T3	3
all_values[15]	120463	1		T1	2		T2	2		T3	3
all_values[16]	120463	1		T1	2		T2	2		T3	3
all_values[17]	120463	1		T1	2		T2	2		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2161606	1		T1	36		T2	36		T3	54
auto[1]	6728	1		T28	2		T29	14		T31	4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2163629	1		T1	36		T2	36		T3	54
auto[1]	4705	1		T209	132		T206	72		T207	65

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	119500	1		T1	2		T2	2		T3	3
all_values[0]	auto[0]	auto[1]	133	1		T209	2		T207	3		T208	4
all_values[0]	auto[1]	auto[0]	705	1		T31	4		T33	3		T51	3
all_values[0]	auto[1]	auto[1]	125	1		T209	5		T206	5		T207	2
all_values[1]	auto[0]	auto[0]	118675	1		T1	2		T2	2		T3	3
all_values[1]	auto[0]	auto[1]	130	1		T209	2		T206	4		T207	3
all_values[1]	auto[1]	auto[0]	1521	1		T28	2		T29	14		T6	2
all_values[1]	auto[1]	auto[1]	137	1		T209	6		T206	1		T207	2
all_values[2]	auto[0]	auto[0]	120078	1		T1	2		T2	2		T3	3
all_values[2]	auto[0]	auto[1]	98	1		T209	6		T206	1		T208	1
all_values[2]	auto[1]	auto[0]	124	1		T40	2		T47	2		T48	2
all_values[2]	auto[1]	auto[1]	163	1		T209	2		T206	4		T208	4
all_values[3]	auto[0]	auto[0]	118759	1		T1	2		T2	2		T3	3
all_values[3]	auto[0]	auto[1]	134	1		T209	6		T206	1		T207	4
all_values[3]	auto[1]	auto[0]	1437	1		T68	1408		T207	1		T290	1
all_values[3]	auto[1]	auto[1]	133	1		T209	2		T206	4		T208	3
all_values[4]	auto[0]	auto[0]	120171	1		T1	2		T2	2		T3	3
all_values[4]	auto[0]	auto[1]	131	1		T209	3		T207	1		T291	3
all_values[4]	auto[1]	auto[0]	29	1		T69	2		T292	2		T290	1
all_values[4]	auto[1]	auto[1]	132	1		T209	5		T206	5		T207	4
all_values[5]	auto[0]	auto[0]	120174	1		T1	2		T2	2		T3	3
all_values[5]	auto[0]	auto[1]	122	1		T209	5		T207	3		T208	1
all_values[5]	auto[1]	auto[0]	23	1		T206	1		T208	1		T292	1
all_values[5]	auto[1]	auto[1]	144	1		T209	3		T206	4		T207	2
all_values[6]	auto[0]	auto[0]	120173	1		T1	2		T2	2		T3	3
all_values[6]	auto[0]	auto[1]	117	1		T209	3		T206	1		T208	5
all_values[6]	auto[1]	auto[0]	31	1		T290	6		T293	1		T294	1
all_values[6]	auto[1]	auto[1]	142	1		T209	5		T206	4		T207	4
all_values[7]	auto[0]	auto[0]	120174	1		T1	2		T2	2		T3	3
all_values[7]	auto[0]	auto[1]	134	1		T209	3		T206	1		T208	1
all_values[7]	auto[1]	auto[0]	40	1		T52	2		T53	2		T209	1
all_values[7]	auto[1]	auto[1]	115	1		T209	3		T206	3		T208	4
all_values[8]	auto[0]	auto[0]	120167	1		T1	2		T2	2		T3	3
all_values[8]	auto[0]	auto[1]	154	1		T209	6		T206	4		T207	4
all_values[8]	auto[1]	auto[0]	33	1		T54	11		T295	1		T296	4
all_values[8]	auto[1]	auto[1]	109	1		T209	2		T206	1		T207	1
all_values[9]	auto[0]	auto[0]	120147	1		T1	2		T2	2		T3	3
all_values[9]	auto[0]	auto[1]	124	1		T209	4		T207	1		T292	2
all_values[9]	auto[1]	auto[0]	49	1		T65	5		T66	5		T67	5
all_values[9]	auto[1]	auto[1]	143	1		T209	4		T207	4		T292	3
all_values[10]	auto[0]	auto[0]	120175	1		T1	2		T2	2		T3	3
all_values[10]	auto[0]	auto[1]	137	1		T209	5		T207	4		T208	3
all_values[10]	auto[1]	auto[0]	12	1		T291	1		T296	1		T297	1
all_values[10]	auto[1]	auto[1]	139	1		T209	1		T206	5		T207	1
all_values[11]	auto[0]	auto[0]	120071	1		T1	2		T2	2		T3	3
all_values[11]	auto[0]	auto[1]	127	1		T209	2		T206	1		T207	4
all_values[11]	auto[1]	auto[0]	136	1		T50	2		T74	2		T75	2
all_values[11]	auto[1]	auto[1]	129	1		T209	4		T206	3		T292	4
all_values[12]	auto[0]	auto[0]	120158	1		T1	2		T2	2		T3	3
all_values[12]	auto[0]	auto[1]	131	1		T209	7		T206	1		T207	1
all_values[12]	auto[1]	auto[0]	35	1		T76	3		T77	3		T78	3
all_values[12]	auto[1]	auto[1]	139	1		T206	4		T207	3		T292	4
all_values[13]	auto[0]	auto[0]	120171	1		T1	2		T2	2		T3	3
all_values[13]	auto[0]	auto[1]	131	1		T209	7		T207	2		T208	1
all_values[13]	auto[1]	auto[0]	34	1		T206	1		T208	1		T298	1
all_values[13]	auto[1]	auto[1]	127	1		T209	1		T206	4		T207	3
all_values[14]	auto[0]	auto[0]	120178	1		T1	2		T2	2		T3	3
all_values[14]	auto[0]	auto[1]	116	1		T209	1		T206	1		T208	3
all_values[14]	auto[1]	auto[0]	31	1		T207	5		T295	1		T299	1
all_values[14]	auto[1]	auto[1]	138	1		T209	5		T206	4		T208	2
all_values[15]	auto[0]	auto[0]	120173	1		T1	2		T2	2		T3	3
all_values[15]	auto[0]	auto[1]	135	1		T209	4		T208	4		T291	4
all_values[15]	auto[1]	auto[0]	30	1		T209	1		T207	1		T292	1
all_values[15]	auto[1]	auto[1]	125	1		T209	3		T206	3		T207	4
all_values[16]	auto[0]	auto[0]	120154	1		T1	2		T2	2		T3	3
all_values[16]	auto[0]	auto[1]	158	1		T209	5		T207	5		T208	5
all_values[16]	auto[1]	auto[0]	48	1		T70	8		T71	8		T72	8
all_values[16]	auto[1]	auto[1]	103	1		T209	3		T292	1		T291	3
all_values[17]	auto[0]	auto[0]	120183	1		T1	2		T2	2		T3	3
all_values[17]	auto[0]	auto[1]	113	1		T209	1		T206	3		T208	5
all_values[17]	auto[1]	auto[0]	30	1		T58	2		T59	2		T60	2
all_values[17]	auto[1]	auto[1]	137	1		T209	6		T292	3		T291	6