Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	120463	1		T1	2		T2	2		T3	3
all_pins[1]	120463	1		T1	2		T2	2		T3	3
all_pins[2]	120463	1		T1	2		T2	2		T3	3
all_pins[3]	120463	1		T1	2		T2	2		T3	3
all_pins[4]	120463	1		T1	2		T2	2		T3	3
all_pins[5]	120463	1		T1	2		T2	2		T3	3
all_pins[6]	120463	1		T1	2		T2	2		T3	3
all_pins[7]	120463	1		T1	2		T2	2		T3	3
all_pins[8]	120463	1		T1	2		T2	2		T3	3
all_pins[9]	120463	1		T1	2		T2	2		T3	3
all_pins[10]	120463	1		T1	2		T2	2		T3	3
all_pins[11]	120463	1		T1	2		T2	2		T3	3
all_pins[12]	120463	1		T1	2		T2	2		T3	3
all_pins[13]	120463	1		T1	2		T2	2		T3	3
all_pins[14]	120463	1		T1	2		T2	2		T3	3
all_pins[15]	120463	1		T1	2		T2	2		T3	3
all_pins[16]	120463	1		T1	2		T2	2		T3	3
all_pins[17]	120463	1		T1	2		T2	2		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2166147	1		T1	36		T2	36		T3	54
values[0x1]	2187	1		T28	1		T29	12		T31	1
transitions[0x0=>0x1]	1940	1		T28	1		T29	12		T31	1
transitions[0x1=>0x0]	1948	1		T28	1		T29	12		T31	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	120354	1		T1	2		T2	2		T3	3
all_pins[0]	values[0x1]	109	1		T31	1		T82	1		T250	1
all_pins[0]	transitions[0x0=>0x1]	97	1		T31	1		T82	1		T250	1
all_pins[0]	transitions[0x1=>0x0]	989	1		T28	1		T29	12		T6	1
all_pins[1]	values[0x0]	119462	1		T1	2		T2	2		T3	3
all_pins[1]	values[0x1]	1001	1		T28	1		T29	12		T6	1
all_pins[1]	transitions[0x0=>0x1]	986	1		T28	1		T29	12		T6	1
all_pins[1]	transitions[0x1=>0x0]	110	1		T40	1		T47	1		T48	1
all_pins[2]	values[0x0]	120338	1		T1	2		T2	2		T3	3
all_pins[2]	values[0x1]	125	1		T40	1		T47	1		T48	1
all_pins[2]	transitions[0x0=>0x1]	108	1		T40	1		T47	1		T48	1
all_pins[2]	transitions[0x1=>0x0]	43	1		T68	1		T208	2		T291	2
all_pins[3]	values[0x0]	120403	1		T1	2		T2	2		T3	3
all_pins[3]	values[0x1]	60	1		T68	1		T208	2		T291	3
all_pins[3]	transitions[0x0=>0x1]	52	1		T68	1		T208	2		T291	3
all_pins[3]	transitions[0x1=>0x0]	54	1		T69	1		T209	3		T206	1
all_pins[4]	values[0x0]	120401	1		T1	2		T2	2		T3	3
all_pins[4]	values[0x1]	62	1		T69	1		T209	3		T206	1
all_pins[4]	transitions[0x0=>0x1]	44	1		T69	1		T209	3		T206	1
all_pins[4]	transitions[0x1=>0x0]	56	1		T209	1		T206	1		T207	1
all_pins[5]	values[0x0]	120389	1		T1	2		T2	2		T3	3
all_pins[5]	values[0x1]	74	1		T209	1		T206	1		T207	2
all_pins[5]	transitions[0x0=>0x1]	55	1		T209	1		T206	1		T207	1
all_pins[5]	transitions[0x1=>0x0]	44	1		T209	3		T207	2		T291	2
all_pins[6]	values[0x0]	120400	1		T1	2		T2	2		T3	3
all_pins[6]	values[0x1]	63	1		T209	3		T207	3		T292	2
all_pins[6]	transitions[0x0=>0x1]	51	1		T209	2		T207	3		T292	2
all_pins[6]	transitions[0x1=>0x0]	39	1		T52	1		T53	1		T206	1
all_pins[7]	values[0x0]	120412	1		T1	2		T2	2		T3	3
all_pins[7]	values[0x1]	51	1		T52	1		T53	1		T209	1
all_pins[7]	transitions[0x0=>0x1]	39	1		T52	1		T53	1		T209	1
all_pins[7]	transitions[0x1=>0x0]	35	1		T54	1		T209	2		T292	1
all_pins[8]	values[0x0]	120416	1		T1	2		T2	2		T3	3
all_pins[8]	values[0x1]	47	1		T54	1		T209	2		T292	1
all_pins[8]	transitions[0x0=>0x1]	38	1		T54	1		T209	2		T292	1
all_pins[8]	transitions[0x1=>0x0]	62	1		T65	2		T66	2		T67	2
all_pins[9]	values[0x0]	120392	1		T1	2		T2	2		T3	3
all_pins[9]	values[0x1]	71	1		T65	2		T66	2		T67	2
all_pins[9]	transitions[0x0=>0x1]	62	1		T65	2		T66	2		T67	2
all_pins[9]	transitions[0x1=>0x0]	50	1		T206	2		T290	2		T293	1
all_pins[10]	values[0x0]	120404	1		T1	2		T2	2		T3	3
all_pins[10]	values[0x1]	59	1		T206	2		T207	1		T290	2
all_pins[10]	transitions[0x0=>0x1]	45	1		T206	2		T207	1		T290	2
all_pins[10]	transitions[0x1=>0x0]	94	1		T50	1		T74	1		T75	1
all_pins[11]	values[0x0]	120355	1		T1	2		T2	2		T3	3
all_pins[11]	values[0x1]	108	1		T50	1		T74	1		T75	1
all_pins[11]	transitions[0x0=>0x1]	95	1		T50	1		T74	1		T75	1
all_pins[11]	transitions[0x1=>0x0]	55	1		T76	1		T77	1		T78	1
all_pins[12]	values[0x0]	120395	1		T1	2		T2	2		T3	3
all_pins[12]	values[0x1]	68	1		T76	1		T77	1		T78	1
all_pins[12]	transitions[0x0=>0x1]	51	1		T76	1		T77	1		T78	1
all_pins[12]	transitions[0x1=>0x0]	39	1		T208	2		T291	2		T293	1
all_pins[13]	values[0x0]	120407	1		T1	2		T2	2		T3	3
all_pins[13]	values[0x1]	56	1		T207	2		T208	2		T291	2
all_pins[13]	transitions[0x0=>0x1]	41	1		T207	2		T208	2		T291	2
all_pins[13]	transitions[0x1=>0x0]	57	1		T209	1		T206	3		T208	1
all_pins[14]	values[0x0]	120391	1		T1	2		T2	2		T3	3
all_pins[14]	values[0x1]	72	1		T209	1		T206	3		T208	1
all_pins[14]	transitions[0x0=>0x1]	62	1		T209	1		T206	3		T208	1
all_pins[14]	transitions[0x1=>0x0]	39	1		T207	3		T208	1		T292	1
all_pins[15]	values[0x0]	120414	1		T1	2		T2	2		T3	3
all_pins[15]	values[0x1]	49	1		T207	3		T208	1		T292	1
all_pins[15]	transitions[0x0=>0x1]	45	1		T207	3		T208	1		T292	1
all_pins[15]	transitions[0x1=>0x0]	50	1		T70	4		T71	4		T72	4
all_pins[16]	values[0x0]	120409	1		T1	2		T2	2		T3	3
all_pins[16]	values[0x1]	54	1		T70	4		T71	4		T72	4
all_pins[16]	transitions[0x0=>0x1]	36	1		T70	4		T71	4		T72	4
all_pins[16]	transitions[0x1=>0x0]	40	1		T58	1		T59	1		T60	1
all_pins[17]	values[0x0]	120405	1		T1	2		T2	2		T3	3
all_pins[17]	values[0x1]	58	1		T58	1		T59	1		T60	1
all_pins[17]	transitions[0x0=>0x1]	33	1		T58	1		T59	1		T60	1
all_pins[17]	transitions[0x1=>0x0]	92	1		T31	1		T82	1		T250	1