Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	263	1		T209	7		T206	4		T207	4
all_values[1]	263	1		T209	7		T206	4		T207	4
all_values[2]	263	1		T209	7		T206	4		T207	4
all_values[3]	263	1		T209	7		T206	4		T207	4
all_values[4]	263	1		T209	7		T206	4		T207	4
all_values[5]	263	1		T209	7		T206	4		T207	4
all_values[6]	263	1		T209	7		T206	4		T207	4
all_values[7]	263	1		T209	7		T206	4		T207	4
all_values[8]	263	1		T209	7		T206	4		T207	4
all_values[9]	263	1		T209	7		T206	4		T207	4
all_values[10]	263	1		T209	7		T206	4		T207	4
all_values[11]	263	1		T209	7		T206	4		T207	4
all_values[12]	263	1		T209	7		T206	4		T207	4
all_values[13]	263	1		T209	7		T206	4		T207	4
all_values[14]	263	1		T209	7		T206	4		T207	4
all_values[15]	263	1		T209	7		T206	4		T207	4
all_values[16]	263	1		T209	7		T206	4		T207	4
all_values[17]	263	1		T209	7		T206	4		T207	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2578	1		T209	80		T206	30		T207	44
auto[1]	2156	1		T209	46		T206	42		T207	28

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	870	1		T209	12		T206	16		T207	21
auto[1]	3864	1		T209	114		T206	56		T207	51

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2818	1		T209	72		T206	46		T207	47
auto[1]	1916	1		T209	54		T206	26		T207	25

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	30	1		T209	1		T208	1		T292	2
all_values[0]	auto[0]	auto[0]	auto[1]	54	1		T209	1		T207	1		T208	1
all_values[0]	auto[0]	auto[1]	auto[0]	21	1		T292	2		T295	1		T300	1
all_values[0]	auto[0]	auto[1]	auto[1]	51	1		T209	3		T206	2		T207	1
all_values[0]	auto[1]	auto[0]	auto[1]	50	1		T207	1		T208	2		T291	2
all_values[0]	auto[1]	auto[1]	auto[1]	57	1		T209	2		T206	2		T207	1
all_values[1]	auto[0]	auto[0]	auto[0]	27	1		T292	1		T295	1		T299	3
all_values[1]	auto[0]	auto[0]	auto[1]	56	1		T209	2		T206	2		T207	1
all_values[1]	auto[0]	auto[1]	auto[0]	18	1		T292	1		T291	4		T301	1
all_values[1]	auto[0]	auto[1]	auto[1]	54	1		T209	3		T207	1		T208	2
all_values[1]	auto[1]	auto[0]	auto[1]	62	1		T209	2		T206	1		T207	1
all_values[1]	auto[1]	auto[1]	auto[1]	46	1		T206	1		T207	1		T208	1
all_values[2]	auto[0]	auto[0]	auto[0]	32	1		T207	2		T295	1		T299	1
all_values[2]	auto[0]	auto[0]	auto[1]	46	1		T209	2		T206	1		T208	2
all_values[2]	auto[0]	auto[1]	auto[0]	16	1		T207	2		T292	1		T299	1
all_values[2]	auto[0]	auto[1]	auto[1]	60	1		T209	1		T206	2		T208	1
all_values[2]	auto[1]	auto[0]	auto[1]	49	1		T209	3		T208	1		T291	1
all_values[2]	auto[1]	auto[1]	auto[1]	60	1		T209	1		T206	1		T292	2
all_values[3]	auto[0]	auto[0]	auto[0]	21	1		T207	1		T208	1		T292	1
all_values[3]	auto[0]	auto[0]	auto[1]	54	1		T209	3		T207	1		T208	1
all_values[3]	auto[0]	auto[1]	auto[0]	22	1		T290	1		T293	1		T299	1
all_values[3]	auto[0]	auto[1]	auto[1]	56	1		T209	1		T206	2		T208	1
all_values[3]	auto[1]	auto[0]	auto[1]	63	1		T209	3		T206	2		T207	2
all_values[3]	auto[1]	auto[1]	auto[1]	47	1		T291	4		T290	2		T302	3
all_values[4]	auto[0]	auto[0]	auto[0]	27	1		T208	1		T291	1		T290	1
all_values[4]	auto[0]	auto[0]	auto[1]	48	1		T209	1		T291	1		T290	1
all_values[4]	auto[0]	auto[1]	auto[0]	21	1		T292	2		T290	1		T294	2
all_values[4]	auto[0]	auto[1]	auto[1]	50	1		T209	1		T206	3		T207	2
all_values[4]	auto[1]	auto[0]	auto[1]	63	1		T209	2		T207	1		T291	2
all_values[4]	auto[1]	auto[1]	auto[1]	54	1		T209	3		T206	1		T207	1
all_values[5]	auto[0]	auto[0]	auto[0]	29	1		T208	1		T293	1		T302	1
all_values[5]	auto[0]	auto[0]	auto[1]	58	1		T209	4		T207	1		T208	1
all_values[5]	auto[0]	auto[1]	auto[0]	15	1		T206	1		T292	1		T293	1
all_values[5]	auto[0]	auto[1]	auto[1]	59	1		T209	1		T206	2		T207	1
all_values[5]	auto[1]	auto[0]	auto[1]	53	1		T209	2		T207	1		T208	1
all_values[5]	auto[1]	auto[1]	auto[1]	49	1		T206	1		T207	1		T292	2
all_values[6]	auto[0]	auto[0]	auto[0]	29	1		T207	1		T290	3		T293	1
all_values[6]	auto[0]	auto[0]	auto[1]	46	1		T209	1		T208	3		T291	1
all_values[6]	auto[0]	auto[1]	auto[0]	20	1		T290	4		T294	1		T297	4
all_values[6]	auto[0]	auto[1]	auto[1]	56	1		T209	1		T206	1		T207	2
all_values[6]	auto[1]	auto[0]	auto[1]	56	1		T209	3		T206	2		T208	1
all_values[6]	auto[1]	auto[1]	auto[1]	56	1		T209	2		T206	1		T207	1
all_values[7]	auto[0]	auto[0]	auto[0]	34	1		T209	1		T207	3		T291	4
all_values[7]	auto[0]	auto[0]	auto[1]	59	1		T209	1		T292	2		T291	2
all_values[7]	auto[0]	auto[1]	auto[0]	25	1		T209	1		T206	1		T207	1
all_values[7]	auto[0]	auto[1]	auto[1]	44	1		T209	1		T206	1		T208	2
all_values[7]	auto[1]	auto[0]	auto[1]	56	1		T209	1		T206	1		T208	1
all_values[7]	auto[1]	auto[1]	auto[1]	45	1		T209	2		T206	1		T208	1
all_values[8]	auto[0]	auto[0]	auto[0]	33	1		T208	2		T295	1		T298	1
all_values[8]	auto[0]	auto[0]	auto[1]	62	1		T209	3		T206	2		T207	1
all_values[8]	auto[0]	auto[1]	auto[0]	14	1		T295	1		T296	2		T303	1
all_values[8]	auto[0]	auto[1]	auto[1]	47	1		T209	1		T207	2		T290	2
all_values[8]	auto[1]	auto[0]	auto[1]	63	1		T209	2		T206	1		T207	1
all_values[8]	auto[1]	auto[1]	auto[1]	44	1		T209	1		T206	1		T292	1
all_values[9]	auto[0]	auto[0]	auto[0]	27	1		T206	3		T208	2		T293	1
all_values[9]	auto[0]	auto[0]	auto[1]	50	1		T207	2		T292	1		T290	1
all_values[9]	auto[0]	auto[1]	auto[0]	15	1		T206	1		T208	2		T290	1
all_values[9]	auto[0]	auto[1]	auto[1]	62	1		T209	2		T207	1		T292	1
all_values[9]	auto[1]	auto[0]	auto[1]	58	1		T209	4		T207	1		T292	2
all_values[9]	auto[1]	auto[1]	auto[1]	51	1		T209	1		T291	3		T290	2
all_values[10]	auto[0]	auto[0]	auto[0]	28	1		T209	2		T292	1		T293	1
all_values[10]	auto[0]	auto[0]	auto[1]	56	1		T209	3		T207	2		T208	1
all_values[10]	auto[0]	auto[1]	auto[0]	9	1		T291	1		T297	1		T304	2
all_values[10]	auto[0]	auto[1]	auto[1]	59	1		T206	3		T208	2		T292	1
all_values[10]	auto[1]	auto[0]	auto[1]	71	1		T209	1		T207	2		T208	1
all_values[10]	auto[1]	auto[1]	auto[1]	40	1		T209	1		T206	1		T291	1
all_values[11]	auto[0]	auto[0]	auto[0]	29	1		T209	2		T206	1		T207	1
all_values[11]	auto[0]	auto[0]	auto[1]	57	1		T209	1		T206	1		T207	1
all_values[11]	auto[0]	auto[1]	auto[0]	23	1		T208	1		T290	1		T294	1
all_values[11]	auto[0]	auto[1]	auto[1]	49	1		T209	2		T206	1		T292	3
all_values[11]	auto[1]	auto[0]	auto[1]	65	1		T209	2		T206	1		T207	2
all_values[11]	auto[1]	auto[1]	auto[1]	40	1		T208	1		T291	2		T290	1
all_values[12]	auto[0]	auto[0]	auto[0]	28	1		T209	1		T207	1		T208	1
all_values[12]	auto[0]	auto[0]	auto[1]	53	1		T209	3		T206	1		T208	1
all_values[12]	auto[0]	auto[1]	auto[0]	13	1		T208	1		T290	1		T293	1
all_values[12]	auto[0]	auto[1]	auto[1]	61	1		T206	1		T207	1		T292	2
all_values[12]	auto[1]	auto[0]	auto[1]	57	1		T209	3		T207	2		T291	1
all_values[12]	auto[1]	auto[1]	auto[1]	51	1		T206	2		T208	1		T292	1
all_values[13]	auto[0]	auto[0]	auto[0]	28	1		T208	1		T302	1		T298	1
all_values[13]	auto[0]	auto[0]	auto[1]	60	1		T209	5		T207	1		T208	1
all_values[13]	auto[0]	auto[1]	auto[0]	24	1		T206	1		T297	3		T305	2
all_values[13]	auto[0]	auto[1]	auto[1]	48	1		T209	1		T206	1		T207	1
all_values[13]	auto[1]	auto[0]	auto[1]	56	1		T209	1		T207	2		T208	1
all_values[13]	auto[1]	auto[1]	auto[1]	47	1		T206	2		T292	1		T290	1
all_values[14]	auto[0]	auto[0]	auto[0]	34	1		T209	2		T207	1		T291	1
all_values[14]	auto[0]	auto[0]	auto[1]	46	1		T206	1		T208	1		T292	1
all_values[14]	auto[0]	auto[1]	auto[0]	19	1		T207	3		T294	2		T301	2
all_values[14]	auto[0]	auto[1]	auto[1]	60	1		T209	3		T206	1		T292	1
all_values[14]	auto[1]	auto[0]	auto[1]	57	1		T209	1		T206	1		T208	1
all_values[14]	auto[1]	auto[1]	auto[1]	47	1		T209	1		T206	1		T208	2
all_values[15]	auto[0]	auto[0]	auto[0]	33	1		T209	1		T206	2		T207	1
all_values[15]	auto[0]	auto[0]	auto[1]	61	1		T209	1		T208	2		T291	2
all_values[15]	auto[0]	auto[1]	auto[0]	19	1		T292	1		T300	2		T294	1
all_values[15]	auto[0]	auto[1]	auto[1]	54	1		T209	2		T206	1		T207	1
all_values[15]	auto[1]	auto[0]	auto[1]	59	1		T209	3		T206	1		T208	2
all_values[15]	auto[1]	auto[1]	auto[1]	37	1		T207	2		T292	2		T291	3
all_values[16]	auto[0]	auto[0]	auto[0]	34	1		T206	2		T291	4		T295	2
all_values[16]	auto[0]	auto[0]	auto[1]	68	1		T209	2		T207	2		T208	2
all_values[16]	auto[0]	auto[1]	auto[0]	15	1		T206	2		T291	1		T295	1
all_values[16]	auto[0]	auto[1]	auto[1]	41	1		T209	2		T291	1		T290	4
all_values[16]	auto[1]	auto[0]	auto[1]	65	1		T209	3		T207	2		T208	2
all_values[16]	auto[1]	auto[1]	auto[1]	40	1		T292	1		T291	1		T290	3
all_values[17]	auto[0]	auto[0]	auto[0]	44	1		T209	1		T206	2		T207	2
all_values[17]	auto[0]	auto[0]	auto[1]	44	1		T206	1		T208	2		T290	2
all_values[17]	auto[0]	auto[1]	auto[0]	14	1		T207	2		T292	1		T294	1
all_values[17]	auto[0]	auto[1]	auto[1]	59	1		T209	2		T292	1		T291	3
all_values[17]	auto[1]	auto[0]	auto[1]	50	1		T206	1		T208	2		T291	3
all_values[17]	auto[1]	auto[1]	auto[1]	52	1		T209	4		T292	1		T291	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal