Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.56 97.84 93.79 97.44 75.00 96.26 98.17 96.40


Total test records in report: 2728
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T2576 /workspace/coverage/default/22.usbdev_in_stall.3031354909 Jun 27 06:38:28 PM PDT 24 Jun 27 06:38:34 PM PDT 24 144355459 ps
T2577 /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.791144160 Jun 27 06:35:47 PM PDT 24 Jun 27 06:38:23 PM PDT 24 5415710069 ps
T2578 /workspace/coverage/default/32.usbdev_bitstuff_err.2299268416 Jun 27 06:39:41 PM PDT 24 Jun 27 06:39:52 PM PDT 24 168621223 ps
T2579 /workspace/coverage/default/47.usbdev_phy_config_pinflip.2757590698 Jun 27 06:42:38 PM PDT 24 Jun 27 06:43:05 PM PDT 24 241692071 ps
T2580 /workspace/coverage/default/42.usbdev_min_length_out_transaction.3961333613 Jun 27 06:41:20 PM PDT 24 Jun 27 06:42:17 PM PDT 24 165513663 ps
T2581 /workspace/coverage/default/31.usbdev_alert_test.2369580272 Jun 27 06:39:42 PM PDT 24 Jun 27 06:39:53 PM PDT 24 33713370 ps
T2582 /workspace/coverage/default/4.usbdev_max_length_in_transaction.4176313877 Jun 27 06:34:54 PM PDT 24 Jun 27 06:35:05 PM PDT 24 243056080 ps
T2583 /workspace/coverage/default/20.usbdev_max_usb_traffic.3103339333 Jun 27 06:38:02 PM PDT 24 Jun 27 06:39:04 PM PDT 24 6301107330 ps
T2584 /workspace/coverage/default/29.usbdev_pkt_sent.1067998169 Jun 27 06:39:16 PM PDT 24 Jun 27 06:39:29 PM PDT 24 193415125 ps
T2585 /workspace/coverage/default/36.usbdev_in_trans.2635981481 Jun 27 06:40:38 PM PDT 24 Jun 27 06:40:59 PM PDT 24 230816553 ps
T2586 /workspace/coverage/default/47.usbdev_invalid_sync.869128237 Jun 27 06:42:40 PM PDT 24 Jun 27 06:43:57 PM PDT 24 6929386397 ps
T2587 /workspace/coverage/default/43.usbdev_stall_trans.2050466578 Jun 27 06:41:52 PM PDT 24 Jun 27 06:42:38 PM PDT 24 173095973 ps
T2588 /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.3705834660 Jun 27 06:40:50 PM PDT 24 Jun 27 06:41:38 PM PDT 24 141918396 ps
T2589 /workspace/coverage/default/24.usbdev_endpoint_access.1331910904 Jun 27 06:38:31 PM PDT 24 Jun 27 06:38:37 PM PDT 24 949009887 ps
T2590 /workspace/coverage/default/28.usbdev_aon_wake_disconnect.1737531598 Jun 27 06:39:16 PM PDT 24 Jun 27 06:39:33 PM PDT 24 4322527591 ps
T2591 /workspace/coverage/default/32.usbdev_phy_pins_sense.311141131 Jun 27 06:39:44 PM PDT 24 Jun 27 06:39:55 PM PDT 24 30731614 ps
T2592 /workspace/coverage/default/13.usbdev_pkt_sent.1785034715 Jun 27 06:37:02 PM PDT 24 Jun 27 06:37:12 PM PDT 24 240612621 ps
T2593 /workspace/coverage/default/2.usbdev_min_length_in_transaction.1699558100 Jun 27 06:34:45 PM PDT 24 Jun 27 06:34:56 PM PDT 24 169156920 ps
T2594 /workspace/coverage/default/46.usbdev_fifo_rst.22792569 Jun 27 06:42:20 PM PDT 24 Jun 27 06:42:57 PM PDT 24 332597164 ps
T2595 /workspace/coverage/default/23.usbdev_stall_trans.887313889 Jun 27 06:38:30 PM PDT 24 Jun 27 06:38:35 PM PDT 24 197696730 ps
T2596 /workspace/coverage/default/6.usbdev_streaming_out.2422066997 Jun 27 06:35:34 PM PDT 24 Jun 27 06:36:28 PM PDT 24 5432721153 ps
T2597 /workspace/coverage/default/47.usbdev_alert_test.3435753227 Jun 27 06:42:40 PM PDT 24 Jun 27 06:43:07 PM PDT 24 28471327 ps
T2598 /workspace/coverage/default/33.usbdev_low_speed_traffic.1387842167 Jun 27 06:39:59 PM PDT 24 Jun 27 06:41:35 PM PDT 24 9468381276 ps
T2599 /workspace/coverage/default/37.usbdev_rx_crc_err.1236273930 Jun 27 06:40:46 PM PDT 24 Jun 27 06:41:28 PM PDT 24 201960864 ps
T2600 /workspace/coverage/default/0.usbdev_aon_wake_resume.3627651338 Jun 27 06:34:21 PM PDT 24 Jun 27 06:34:49 PM PDT 24 23352326556 ps
T2601 /workspace/coverage/default/37.usbdev_endpoint_access.3133031555 Jun 27 06:40:45 PM PDT 24 Jun 27 06:41:26 PM PDT 24 937743423 ps
T2602 /workspace/coverage/default/31.usbdev_aon_wake_disconnect.2796486977 Jun 27 06:39:37 PM PDT 24 Jun 27 06:39:51 PM PDT 24 4096208737 ps
T2603 /workspace/coverage/default/4.usbdev_in_stall.3514029675 Jun 27 06:34:53 PM PDT 24 Jun 27 06:35:04 PM PDT 24 139940211 ps
T2604 /workspace/coverage/default/21.usbdev_endpoint_access.4078622537 Jun 27 06:38:09 PM PDT 24 Jun 27 06:38:16 PM PDT 24 854542972 ps
T2605 /workspace/coverage/default/35.usbdev_setup_stage.2954172111 Jun 27 06:40:35 PM PDT 24 Jun 27 06:40:49 PM PDT 24 143193994 ps
T2606 /workspace/coverage/default/41.usbdev_phy_config_pinflip.1439352574 Jun 27 06:41:19 PM PDT 24 Jun 27 06:42:18 PM PDT 24 225089041 ps
T2607 /workspace/coverage/default/21.usbdev_stall_trans.1720624703 Jun 27 06:38:09 PM PDT 24 Jun 27 06:38:16 PM PDT 24 159121324 ps
T2608 /workspace/coverage/default/17.usbdev_pkt_received.2840301892 Jun 27 06:37:28 PM PDT 24 Jun 27 06:37:36 PM PDT 24 158916513 ps
T2609 /workspace/coverage/default/21.usbdev_random_length_out_transaction.723283460 Jun 27 06:38:10 PM PDT 24 Jun 27 06:38:17 PM PDT 24 195951377 ps
T2610 /workspace/coverage/default/5.usbdev_aon_wake_disconnect.655089664 Jun 27 06:35:12 PM PDT 24 Jun 27 06:35:22 PM PDT 24 4396304054 ps
T2611 /workspace/coverage/default/37.usbdev_out_stall.712073838 Jun 27 06:40:51 PM PDT 24 Jun 27 06:41:39 PM PDT 24 194632925 ps
T2612 /workspace/coverage/default/34.usbdev_stall_priority_over_nak.3901262452 Jun 27 06:40:33 PM PDT 24 Jun 27 06:40:44 PM PDT 24 187740840 ps
T2613 /workspace/coverage/default/20.usbdev_pkt_received.1802683492 Jun 27 06:38:04 PM PDT 24 Jun 27 06:38:07 PM PDT 24 204239041 ps
T2614 /workspace/coverage/default/11.usbdev_smoke.3817788844 Jun 27 06:36:38 PM PDT 24 Jun 27 06:36:45 PM PDT 24 235523801 ps
T2615 /workspace/coverage/default/25.usbdev_in_trans.2852695792 Jun 27 06:38:51 PM PDT 24 Jun 27 06:38:53 PM PDT 24 243014341 ps
T2616 /workspace/coverage/default/22.usbdev_min_length_out_transaction.3787248667 Jun 27 06:38:24 PM PDT 24 Jun 27 06:38:28 PM PDT 24 146405681 ps
T2617 /workspace/coverage/default/33.usbdev_stall_trans.1439095840 Jun 27 06:40:01 PM PDT 24 Jun 27 06:40:05 PM PDT 24 159404038 ps
T2618 /workspace/coverage/default/14.usbdev_out_iso.2109487242 Jun 27 06:36:59 PM PDT 24 Jun 27 06:37:07 PM PDT 24 144190595 ps
T2619 /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.3258692466 Jun 27 06:40:32 PM PDT 24 Jun 27 06:40:42 PM PDT 24 168496387 ps
T2620 /workspace/coverage/default/5.usbdev_phy_pins_sense.2443762707 Jun 27 06:35:27 PM PDT 24 Jun 27 06:35:30 PM PDT 24 89939126 ps
T2621 /workspace/coverage/default/18.usbdev_max_length_in_transaction.1248479438 Jun 27 06:37:28 PM PDT 24 Jun 27 06:37:36 PM PDT 24 251589856 ps
T2622 /workspace/coverage/default/20.usbdev_data_toggle_clear.2471420813 Jun 27 06:38:03 PM PDT 24 Jun 27 06:38:07 PM PDT 24 285909549 ps
T2623 /workspace/coverage/default/7.usbdev_random_length_in_transaction.224113604 Jun 27 06:35:44 PM PDT 24 Jun 27 06:35:47 PM PDT 24 232053619 ps
T2624 /workspace/coverage/default/19.usbdev_out_stall.3374656605 Jun 27 06:37:45 PM PDT 24 Jun 27 06:37:49 PM PDT 24 160945043 ps
T2625 /workspace/coverage/default/18.usbdev_rx_crc_err.818298760 Jun 27 06:37:48 PM PDT 24 Jun 27 06:37:55 PM PDT 24 168536596 ps
T2626 /workspace/coverage/default/31.usbdev_stall_trans.1892779173 Jun 27 06:39:46 PM PDT 24 Jun 27 06:39:57 PM PDT 24 183318495 ps
T2627 /workspace/coverage/default/8.usbdev_fifo_rst.1765676820 Jun 27 06:35:47 PM PDT 24 Jun 27 06:35:52 PM PDT 24 242232460 ps
T2628 /workspace/coverage/default/8.usbdev_phy_pins_sense.3439771751 Jun 27 06:35:54 PM PDT 24 Jun 27 06:35:57 PM PDT 24 49698168 ps
T198 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1500360184 Jun 27 04:48:29 PM PDT 24 Jun 27 04:48:33 PM PDT 24 102320143 ps
T199 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.332507770 Jun 27 04:48:19 PM PDT 24 Jun 27 04:48:22 PM PDT 24 135566153 ps
T200 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3587180455 Jun 27 04:48:31 PM PDT 24 Jun 27 04:48:37 PM PDT 24 135973487 ps
T202 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1762500315 Jun 27 04:48:31 PM PDT 24 Jun 27 04:48:37 PM PDT 24 141714812 ps
T209 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2899523316 Jun 27 04:48:19 PM PDT 24 Jun 27 04:48:21 PM PDT 24 49449355 ps
T222 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.141642718 Jun 27 04:48:29 PM PDT 24 Jun 27 04:48:34 PM PDT 24 99121893 ps
T225 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.4022907482 Jun 27 04:48:28 PM PDT 24 Jun 27 04:48:32 PM PDT 24 197981633 ps
T260 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3806075686 Jun 27 04:48:28 PM PDT 24 Jun 27 04:48:31 PM PDT 24 73198476 ps
T226 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.357568697 Jun 27 04:48:10 PM PDT 24 Jun 27 04:48:12 PM PDT 24 76656536 ps
T261 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2697193292 Jun 27 04:48:30 PM PDT 24 Jun 27 04:48:34 PM PDT 24 61939049 ps
T223 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2006735267 Jun 27 04:48:32 PM PDT 24 Jun 27 04:48:40 PM PDT 24 455707685 ps
T262 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3138433728 Jun 27 04:47:47 PM PDT 24 Jun 27 04:47:50 PM PDT 24 84134683 ps
T224 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.437011093 Jun 27 04:48:30 PM PDT 24 Jun 27 04:48:40 PM PDT 24 2211509513 ps
T231 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2714776177 Jun 27 04:48:03 PM PDT 24 Jun 27 04:48:05 PM PDT 24 116244790 ps
T230 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.829801110 Jun 27 04:48:21 PM PDT 24 Jun 27 04:48:26 PM PDT 24 561534744 ps
T2629 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.344998643 Jun 27 04:47:56 PM PDT 24 Jun 27 04:48:01 PM PDT 24 104232077 ps
T273 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3054122276 Jun 27 04:48:30 PM PDT 24 Jun 27 04:48:35 PM PDT 24 122452257 ps
T206 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.574319766 Jun 27 04:48:06 PM PDT 24 Jun 27 04:48:08 PM PDT 24 53215557 ps
T280 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1079789352 Jun 27 04:48:31 PM PDT 24 Jun 27 04:48:40 PM PDT 24 725061956 ps
T274 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.126773694 Jun 27 04:48:31 PM PDT 24 Jun 27 04:48:37 PM PDT 24 76922562 ps
T275 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1446649488 Jun 27 04:48:21 PM PDT 24 Jun 27 04:48:24 PM PDT 24 67187745 ps
T207 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.408432380 Jun 27 04:48:28 PM PDT 24 Jun 27 04:48:32 PM PDT 24 50026367 ps
T232 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3723106883 Jun 27 04:48:35 PM PDT 24 Jun 27 04:48:42 PM PDT 24 193076081 ps
T233 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2777551922 Jun 27 04:48:20 PM PDT 24 Jun 27 04:48:24 PM PDT 24 173850137 ps
T244 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2034306570 Jun 27 04:48:01 PM PDT 24 Jun 27 04:48:04 PM PDT 24 137287457 ps
T208 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3180801839 Jun 27 04:48:27 PM PDT 24 Jun 27 04:48:29 PM PDT 24 45895115 ps
T2630 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1606328097 Jun 27 04:48:26 PM PDT 24 Jun 27 04:48:29 PM PDT 24 82511218 ps
T289 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.315129764 Jun 27 04:48:30 PM PDT 24 Jun 27 04:48:39 PM PDT 24 501107399 ps
T292 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3489055148 Jun 27 04:48:28 PM PDT 24 Jun 27 04:48:31 PM PDT 24 30178315 ps
T306 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2108299296 Jun 27 04:48:09 PM PDT 24 Jun 27 04:48:13 PM PDT 24 509700546 ps
T276 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1630166984 Jun 27 04:48:10 PM PDT 24 Jun 27 04:48:12 PM PDT 24 99480789 ps
T2631 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2805179121 Jun 27 04:48:09 PM PDT 24 Jun 27 04:48:13 PM PDT 24 113529548 ps
T277 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2928459228 Jun 27 04:48:21 PM PDT 24 Jun 27 04:48:23 PM PDT 24 61513158 ps
T263 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1138981389 Jun 27 04:48:13 PM PDT 24 Jun 27 04:48:24 PM PDT 24 1623233092 ps
T281 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2949518064 Jun 27 04:48:32 PM PDT 24 Jun 27 04:48:38 PM PDT 24 78448486 ps
T264 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2972725515 Jun 27 04:48:31 PM PDT 24 Jun 27 04:48:37 PM PDT 24 50637192 ps
T243 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1715956808 Jun 27 04:48:15 PM PDT 24 Jun 27 04:48:18 PM PDT 24 103668359 ps
T291 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2310465403 Jun 27 04:48:54 PM PDT 24 Jun 27 04:48:58 PM PDT 24 37211023 ps
T2632 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.2387245492 Jun 27 04:48:34 PM PDT 24 Jun 27 04:48:41 PM PDT 24 174899851 ps
T290 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2132541610 Jun 27 04:48:48 PM PDT 24 Jun 27 04:48:50 PM PDT 24 44755854 ps
T293 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.565311956 Jun 27 04:47:55 PM PDT 24 Jun 27 04:47:59 PM PDT 24 86555260 ps
T2633 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1055832483 Jun 27 04:47:49 PM PDT 24 Jun 27 04:47:53 PM PDT 24 82762286 ps
T2634 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.404297339 Jun 27 04:48:12 PM PDT 24 Jun 27 04:48:19 PM PDT 24 702176378 ps
T235 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1715665441 Jun 27 04:48:32 PM PDT 24 Jun 27 04:48:39 PM PDT 24 74506386 ps
T2635 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3977462861 Jun 27 04:48:27 PM PDT 24 Jun 27 04:48:29 PM PDT 24 91774137 ps
T308 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1731163680 Jun 27 04:48:30 PM PDT 24 Jun 27 04:48:38 PM PDT 24 728316254 ps
T238 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.4036663669 Jun 27 04:48:32 PM PDT 24 Jun 27 04:48:39 PM PDT 24 168813146 ps
T302 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.4084303083 Jun 27 04:48:27 PM PDT 24 Jun 27 04:48:30 PM PDT 24 86642658 ps
T265 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3064123333 Jun 27 04:48:33 PM PDT 24 Jun 27 04:48:40 PM PDT 24 97230176 ps
T307 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.904896649 Jun 27 04:48:41 PM PDT 24 Jun 27 04:48:47 PM PDT 24 725114775 ps
T2636 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.303897891 Jun 27 04:48:32 PM PDT 24 Jun 27 04:48:39 PM PDT 24 128472431 ps
T295 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.4082526283 Jun 27 04:48:49 PM PDT 24 Jun 27 04:48:52 PM PDT 24 52669387 ps
T236 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1956805865 Jun 27 04:48:32 PM PDT 24 Jun 27 04:48:39 PM PDT 24 295610108 ps
T2637 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2108094386 Jun 27 04:47:56 PM PDT 24 Jun 27 04:48:01 PM PDT 24 200591639 ps
T2638 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2940403223 Jun 27 04:48:29 PM PDT 24 Jun 27 04:48:34 PM PDT 24 112271476 ps
T2639 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.412268526 Jun 27 04:48:33 PM PDT 24 Jun 27 04:48:40 PM PDT 24 264854977 ps
T242 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.718220501 Jun 27 04:47:56 PM PDT 24 Jun 27 04:47:59 PM PDT 24 150418645 ps
T298 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.3785156602 Jun 27 04:48:23 PM PDT 24 Jun 27 04:48:24 PM PDT 24 39157551 ps
T237 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2146631168 Jun 27 04:48:30 PM PDT 24 Jun 27 04:48:36 PM PDT 24 134334143 ps
T287 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2807196594 Jun 27 04:48:13 PM PDT 24 Jun 27 04:48:19 PM PDT 24 541599358 ps
T299 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.906871806 Jun 27 04:48:32 PM PDT 24 Jun 27 04:48:39 PM PDT 24 66266771 ps
T2640 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1152088244 Jun 27 04:47:56 PM PDT 24 Jun 27 04:48:01 PM PDT 24 305725433 ps
T2641 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2498569619 Jun 27 04:48:26 PM PDT 24 Jun 27 04:48:29 PM PDT 24 127143106 ps
T2642 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1423486208 Jun 27 04:48:00 PM PDT 24 Jun 27 04:48:04 PM PDT 24 166635248 ps
T240 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.859667590 Jun 27 04:48:32 PM PDT 24 Jun 27 04:48:39 PM PDT 24 60991998 ps
T239 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1703254812 Jun 27 04:48:21 PM PDT 24 Jun 27 04:48:26 PM PDT 24 366597048 ps
T2643 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.199392783 Jun 27 04:48:29 PM PDT 24 Jun 27 04:48:35 PM PDT 24 110310164 ps
T2644 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2307925130 Jun 27 04:48:32 PM PDT 24 Jun 27 04:48:40 PM PDT 24 231683857 ps
T296 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3343251774 Jun 27 04:48:21 PM PDT 24 Jun 27 04:48:23 PM PDT 24 101390201 ps
T300 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1321475413 Jun 27 04:48:32 PM PDT 24 Jun 27 04:48:38 PM PDT 24 42705916 ps
T294 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.1204667469 Jun 27 04:48:31 PM PDT 24 Jun 27 04:48:37 PM PDT 24 42416029 ps
T303 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.4237680166 Jun 27 04:48:32 PM PDT 24 Jun 27 04:48:38 PM PDT 24 32631278 ps
T297 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3137523308 Jun 27 04:48:27 PM PDT 24 Jun 27 04:48:29 PM PDT 24 43924602 ps
T305 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1198421701 Jun 27 04:48:30 PM PDT 24 Jun 27 04:48:34 PM PDT 24 42950096 ps
T2645 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3277970978 Jun 27 04:48:29 PM PDT 24 Jun 27 04:48:35 PM PDT 24 655725547 ps
T241 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2232098389 Jun 27 04:48:09 PM PDT 24 Jun 27 04:48:14 PM PDT 24 297792665 ps
T2646 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2433042322 Jun 27 04:48:23 PM PDT 24 Jun 27 04:48:25 PM PDT 24 87812932 ps
T301 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1265526598 Jun 27 04:48:30 PM PDT 24 Jun 27 04:48:35 PM PDT 24 35429223 ps
T245 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2448546734 Jun 27 04:47:55 PM PDT 24 Jun 27 04:48:01 PM PDT 24 103352293 ps
T2647 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1701272185 Jun 27 04:48:26 PM PDT 24 Jun 27 04:48:29 PM PDT 24 223460081 ps
T304 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.452886985 Jun 27 04:48:30 PM PDT 24 Jun 27 04:48:35 PM PDT 24 41589942 ps
T2648 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.143840662 Jun 27 04:48:32 PM PDT 24 Jun 27 04:48:39 PM PDT 24 60855657 ps
T2649 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.446828633 Jun 27 04:48:13 PM PDT 24 Jun 27 04:48:16 PM PDT 24 85442005 ps
T2650 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3480172646 Jun 27 04:48:47 PM PDT 24 Jun 27 04:48:49 PM PDT 24 37954939 ps
T2651 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2938179902 Jun 27 04:47:51 PM PDT 24 Jun 27 04:47:53 PM PDT 24 56052018 ps
T2652 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3495515941 Jun 27 04:48:04 PM PDT 24 Jun 27 04:48:06 PM PDT 24 61621180 ps
T266 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1254819532 Jun 27 04:47:56 PM PDT 24 Jun 27 04:48:02 PM PDT 24 147615500 ps
T2653 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1609231317 Jun 27 04:48:30 PM PDT 24 Jun 27 04:48:35 PM PDT 24 38779333 ps
T267 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2487425750 Jun 27 04:48:10 PM PDT 24 Jun 27 04:48:15 PM PDT 24 819117114 ps
T2654 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.351064519 Jun 27 04:48:32 PM PDT 24 Jun 27 04:48:37 PM PDT 24 49916981 ps
T268 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2437234912 Jun 27 04:48:21 PM PDT 24 Jun 27 04:48:26 PM PDT 24 120441074 ps
T2655 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1385667970 Jun 27 04:47:57 PM PDT 24 Jun 27 04:48:08 PM PDT 24 1268712876 ps
T2656 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2180359868 Jun 27 04:48:32 PM PDT 24 Jun 27 04:48:42 PM PDT 24 480463497 ps
T2657 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3776926872 Jun 27 04:48:34 PM PDT 24 Jun 27 04:48:40 PM PDT 24 173699305 ps
T2658 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3678970545 Jun 27 04:48:31 PM PDT 24 Jun 27 04:48:36 PM PDT 24 51284900 ps
T2659 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1327764261 Jun 27 04:48:28 PM PDT 24 Jun 27 04:48:31 PM PDT 24 40260425 ps
T269 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2808413750 Jun 27 04:48:30 PM PDT 24 Jun 27 04:48:36 PM PDT 24 57762881 ps
T2660 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.4211967825 Jun 27 04:48:29 PM PDT 24 Jun 27 04:48:35 PM PDT 24 87923498 ps
T2661 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.517636390 Jun 27 04:48:21 PM PDT 24 Jun 27 04:48:23 PM PDT 24 121421662 ps
T2662 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3431944235 Jun 27 04:48:22 PM PDT 24 Jun 27 04:48:25 PM PDT 24 107247379 ps
T2663 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2946589751 Jun 27 04:48:31 PM PDT 24 Jun 27 04:48:36 PM PDT 24 37922739 ps
T2664 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.2772336577 Jun 27 04:48:28 PM PDT 24 Jun 27 04:48:31 PM PDT 24 35127901 ps
T2665 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1193824589 Jun 27 04:47:55 PM PDT 24 Jun 27 04:48:02 PM PDT 24 693164607 ps
T2666 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3443602045 Jun 27 04:48:32 PM PDT 24 Jun 27 04:48:40 PM PDT 24 212502579 ps
T2667 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3199303793 Jun 27 04:48:29 PM PDT 24 Jun 27 04:48:33 PM PDT 24 113611826 ps
T2668 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1542922406 Jun 27 04:47:51 PM PDT 24 Jun 27 04:48:05 PM PDT 24 3186181730 ps
T2669 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2839831067 Jun 27 04:48:27 PM PDT 24 Jun 27 04:48:29 PM PDT 24 84252919 ps
T2670 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2217138430 Jun 27 04:48:29 PM PDT 24 Jun 27 04:48:34 PM PDT 24 58944866 ps
T284 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3856318018 Jun 27 04:48:09 PM PDT 24 Jun 27 04:48:14 PM PDT 24 636493688 ps
T2671 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2688011562 Jun 27 04:48:22 PM PDT 24 Jun 27 04:48:26 PM PDT 24 249446380 ps
T272 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.141300902 Jun 27 04:48:00 PM PDT 24 Jun 27 04:48:03 PM PDT 24 117456843 ps
T270 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3437303742 Jun 27 04:48:11 PM PDT 24 Jun 27 04:48:14 PM PDT 24 81991677 ps
T2672 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.1069912406 Jun 27 04:48:55 PM PDT 24 Jun 27 04:48:59 PM PDT 24 122719431 ps
T286 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3377304622 Jun 27 04:48:30 PM PDT 24 Jun 27 04:48:38 PM PDT 24 397095847 ps
T285 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3599626020 Jun 27 04:48:20 PM PDT 24 Jun 27 04:48:25 PM PDT 24 852064174 ps
T2673 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3153928279 Jun 27 04:48:30 PM PDT 24 Jun 27 04:48:35 PM PDT 24 52538957 ps
T2674 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.32793168 Jun 27 04:48:13 PM PDT 24 Jun 27 04:48:20 PM PDT 24 670936787 ps
T2675 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2930618504 Jun 27 04:48:33 PM PDT 24 Jun 27 04:48:39 PM PDT 24 52213569 ps
T271 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3290951822 Jun 27 04:48:29 PM PDT 24 Jun 27 04:48:33 PM PDT 24 101334927 ps
T2676 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.314225190 Jun 27 04:48:32 PM PDT 24 Jun 27 04:48:38 PM PDT 24 66222627 ps
T2677 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2871890538 Jun 27 04:48:32 PM PDT 24 Jun 27 04:48:39 PM PDT 24 67968197 ps
T2678 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2556503277 Jun 27 04:48:19 PM PDT 24 Jun 27 04:48:22 PM PDT 24 154938735 ps
T2679 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.320215176 Jun 27 04:48:31 PM PDT 24 Jun 27 04:48:37 PM PDT 24 62173239 ps
T2680 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1966351841 Jun 27 04:48:28 PM PDT 24 Jun 27 04:48:33 PM PDT 24 204615594 ps
T2681 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3560334632 Jun 27 04:48:22 PM PDT 24 Jun 27 04:48:24 PM PDT 24 116973152 ps
T2682 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2494676648 Jun 27 04:48:29 PM PDT 24 Jun 27 04:48:34 PM PDT 24 78644526 ps
T2683 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.683539422 Jun 27 04:48:32 PM PDT 24 Jun 27 04:48:40 PM PDT 24 94040267 ps
T2684 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3465062832 Jun 27 04:48:29 PM PDT 24 Jun 27 04:48:37 PM PDT 24 555486895 ps
T2685 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1748135025 Jun 27 04:48:28 PM PDT 24 Jun 27 04:48:32 PM PDT 24 80631924 ps
T2686 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1423014379 Jun 27 04:48:33 PM PDT 24 Jun 27 04:48:41 PM PDT 24 510983433 ps
T2687 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1046660951 Jun 27 04:48:10 PM PDT 24 Jun 27 04:48:12 PM PDT 24 92600238 ps
T2688 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1290010104 Jun 27 04:48:32 PM PDT 24 Jun 27 04:48:39 PM PDT 24 33709169 ps
T2689 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1829793022 Jun 27 04:48:01 PM PDT 24 Jun 27 04:48:05 PM PDT 24 216025027 ps
T2690 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3779998006 Jun 27 04:48:29 PM PDT 24 Jun 27 04:48:34 PM PDT 24 72757064 ps
T2691 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2056820337 Jun 27 04:47:49 PM PDT 24 Jun 27 04:47:54 PM PDT 24 310464426 ps
T2692 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.696889959 Jun 27 04:48:50 PM PDT 24 Jun 27 04:48:53 PM PDT 24 63734339 ps
T2693 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.1116503045 Jun 27 04:48:32 PM PDT 24 Jun 27 04:48:38 PM PDT 24 53407874 ps
T2694 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.284994315 Jun 27 04:48:27 PM PDT 24 Jun 27 04:48:30 PM PDT 24 55903524 ps
T2695 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1007404510 Jun 27 04:48:32 PM PDT 24 Jun 27 04:48:38 PM PDT 24 147013026 ps
T2696 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2848062961 Jun 27 04:48:46 PM PDT 24 Jun 27 04:48:49 PM PDT 24 55507987 ps
T2697 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1787044969 Jun 27 04:47:56 PM PDT 24 Jun 27 04:48:00 PM PDT 24 48477798 ps
T2698 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2488571024 Jun 27 04:48:27 PM PDT 24 Jun 27 04:48:31 PM PDT 24 129741630 ps
T288 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1195239188 Jun 27 04:48:20 PM PDT 24 Jun 27 04:48:25 PM PDT 24 446847909 ps
T2699 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1863601185 Jun 27 04:48:08 PM PDT 24 Jun 27 04:48:10 PM PDT 24 36902319 ps
T2700 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2629929105 Jun 27 04:48:28 PM PDT 24 Jun 27 04:48:31 PM PDT 24 92122221 ps
T2701 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2372370820 Jun 27 04:48:22 PM PDT 24 Jun 27 04:48:25 PM PDT 24 114436827 ps
T2702 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1736820546 Jun 27 04:48:29 PM PDT 24 Jun 27 04:48:33 PM PDT 24 41805921 ps
T2703 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3218315843 Jun 27 04:48:10 PM PDT 24 Jun 27 04:48:13 PM PDT 24 71944375 ps
T2704 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2509801712 Jun 27 04:47:56 PM PDT 24 Jun 27 04:48:01 PM PDT 24 88829057 ps
T2705 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3524653374 Jun 27 04:47:48 PM PDT 24 Jun 27 04:47:51 PM PDT 24 55328425 ps
T2706 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3476929460 Jun 27 04:48:32 PM PDT 24 Jun 27 04:48:39 PM PDT 24 64927331 ps
T2707 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.48977812 Jun 27 04:48:31 PM PDT 24 Jun 27 04:48:36 PM PDT 24 49734278 ps
T2708 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.780853039 Jun 27 04:48:00 PM PDT 24 Jun 27 04:48:03 PM PDT 24 56086975 ps
T2709 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2252255337 Jun 27 04:48:27 PM PDT 24 Jun 27 04:48:30 PM PDT 24 37010562 ps
T2710 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3219812178 Jun 27 04:48:32 PM PDT 24 Jun 27 04:48:37 PM PDT 24 87559108 ps
T2711 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.257949712 Jun 27 04:48:28 PM PDT 24 Jun 27 04:48:31 PM PDT 24 113683758 ps
T2712 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2515163561 Jun 27 04:48:27 PM PDT 24 Jun 27 04:48:29 PM PDT 24 68514999 ps
T2713 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2191948710 Jun 27 04:48:27 PM PDT 24 Jun 27 04:48:29 PM PDT 24 105593619 ps
T2714 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3159913356 Jun 27 04:48:00 PM PDT 24 Jun 27 04:48:03 PM PDT 24 81631129 ps
T2715 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2223290340 Jun 27 04:48:26 PM PDT 24 Jun 27 04:48:29 PM PDT 24 156658307 ps
T2716 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.633497800 Jun 27 04:48:31 PM PDT 24 Jun 27 04:48:36 PM PDT 24 48684028 ps
T2717 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1208236652 Jun 27 04:48:32 PM PDT 24 Jun 27 04:48:38 PM PDT 24 39560656 ps
T2718 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1041342946 Jun 27 04:48:28 PM PDT 24 Jun 27 04:48:32 PM PDT 24 50821321 ps
T282 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2431213298 Jun 27 04:48:00 PM PDT 24 Jun 27 04:48:06 PM PDT 24 815648883 ps
T2719 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.4218493643 Jun 27 04:48:15 PM PDT 24 Jun 27 04:48:19 PM PDT 24 386847187 ps
T2720 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1644340852 Jun 27 04:48:35 PM PDT 24 Jun 27 04:48:41 PM PDT 24 62318180 ps
T2721 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2204618366 Jun 27 04:48:32 PM PDT 24 Jun 27 04:48:37 PM PDT 24 105280591 ps
T2722 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3695610584 Jun 27 04:48:35 PM PDT 24 Jun 27 04:48:44 PM PDT 24 525038418 ps
T2723 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3528688814 Jun 27 04:48:28 PM PDT 24 Jun 27 04:48:33 PM PDT 24 136875661 ps
T2724 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.733219556 Jun 27 04:48:28 PM PDT 24 Jun 27 04:48:32 PM PDT 24 36620223 ps
T2725 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2559625658 Jun 27 04:48:11 PM PDT 24 Jun 27 04:48:13 PM PDT 24 109518138 ps
T2726 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3191444130 Jun 27 04:48:32 PM PDT 24 Jun 27 04:48:40 PM PDT 24 188337675 ps
T2727 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2313208793 Jun 27 04:47:56 PM PDT 24 Jun 27 04:48:00 PM PDT 24 131652556 ps
T2728 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.626960376 Jun 27 04:48:32 PM PDT 24 Jun 27 04:48:42 PM PDT 24 756862668 ps
T283 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.4275783566 Jun 27 04:48:26 PM PDT 24 Jun 27 04:48:30 PM PDT 24 526044757 ps

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.3980733407
Short name T4
Test name
Test status
Simulation time 4200364479 ps
CPU time 114.17 seconds
Started Jun 27 06:38:28 PM PDT 24
Finished Jun 27 06:40:27 PM PDT 24
Peak memory 206440 kb
Host smart-2ef54541-5514-4271-b591-1bb8e63bb93b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3980733407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.3980733407
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.565311956
Short name T293
Test name
Test status
Simulation time 86555260 ps
CPU time 0.7 seconds
Started Jun 27 04:47:55 PM PDT 24
Finished Jun 27 04:47:59 PM PDT 24
Peak memory 205980 kb
Host smart-c838d23f-106c-4769-ac0c-e57609cc065e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=565311956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.565311956
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.2136940288
Short name T6
Test name
Test status
Simulation time 13328730138 ps
CPU time 13.64 seconds
Started Jun 27 06:34:42 PM PDT 24
Finished Jun 27 06:35:05 PM PDT 24
Peak memory 206348 kb
Host smart-0ebecb85-7f00-400b-a8f8-66d36aa90eba
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2136940288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.2136940288
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_device_address.2793677135
Short name T43
Test name
Test status
Simulation time 13663229055 ps
CPU time 25.95 seconds
Started Jun 27 06:37:17 PM PDT 24
Finished Jun 27 06:37:48 PM PDT 24
Peak memory 206420 kb
Host smart-f33f8438-ef61-43e1-ae3f-e9087d73497a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27936
77135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.2793677135
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2006735267
Short name T223
Test name
Test status
Simulation time 455707685 ps
CPU time 2.94 seconds
Started Jun 27 04:48:32 PM PDT 24
Finished Jun 27 04:48:40 PM PDT 24
Peak memory 206108 kb
Host smart-f06d7986-3948-421a-9d56-3052532e4bd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2006735267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.2006735267
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.1791710948
Short name T46
Test name
Test status
Simulation time 9772734457 ps
CPU time 255.31 seconds
Started Jun 27 06:34:23 PM PDT 24
Finished Jun 27 06:38:46 PM PDT 24
Peak memory 206424 kb
Host smart-ffe9b6a1-59d4-49c5-9144-a890cbee365d
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1791710948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.1791710948
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.1448809088
Short name T3
Test name
Test status
Simulation time 189134931 ps
CPU time 0.85 seconds
Started Jun 27 06:38:24 PM PDT 24
Finished Jun 27 06:38:28 PM PDT 24
Peak memory 206264 kb
Host smart-7070cd3b-305f-42a1-b563-c7073e3d99c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14488
09088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.1448809088
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2132541610
Short name T290
Test name
Test status
Simulation time 44755854 ps
CPU time 0.71 seconds
Started Jun 27 04:48:48 PM PDT 24
Finished Jun 27 04:48:50 PM PDT 24
Peak memory 206012 kb
Host smart-47fb5c9f-cc80-43a5-b714-983c0c313e20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2132541610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.2132541610
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.2279921906
Short name T470
Test name
Test status
Simulation time 217664471 ps
CPU time 0.93 seconds
Started Jun 27 06:36:40 PM PDT 24
Finished Jun 27 06:36:47 PM PDT 24
Peak memory 206268 kb
Host smart-8768e1a8-7529-4830-9a9e-0a0913a2c03e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22799
21906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.2279921906
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.3093895155
Short name T195
Test name
Test status
Simulation time 974506062 ps
CPU time 1.84 seconds
Started Jun 27 06:35:11 PM PDT 24
Finished Jun 27 06:35:18 PM PDT 24
Peak memory 223996 kb
Host smart-bf8c1896-bde1-4015-860b-ece5ab636c07
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3093895155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.3093895155
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.2185087130
Short name T105
Test name
Test status
Simulation time 443176074 ps
CPU time 1.45 seconds
Started Jun 27 06:40:34 PM PDT 24
Finished Jun 27 06:40:48 PM PDT 24
Peak memory 206268 kb
Host smart-86ea2078-58b2-4b33-b684-4b25ef794872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21850
87130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.2185087130
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.2122568779
Short name T20
Test name
Test status
Simulation time 218859443 ps
CPU time 0.86 seconds
Started Jun 27 06:36:06 PM PDT 24
Finished Jun 27 06:36:09 PM PDT 24
Peak memory 206260 kb
Host smart-d45d3169-9af1-41fd-92aa-654a1b0926f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21225
68779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.2122568779
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.1214052026
Short name T421
Test name
Test status
Simulation time 4125051040 ps
CPU time 4.92 seconds
Started Jun 27 06:43:03 PM PDT 24
Finished Jun 27 06:43:25 PM PDT 24
Peak memory 206440 kb
Host smart-5b754f5b-b192-4827-bb3f-39387640e178
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1214052026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.1214052026
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.332507770
Short name T199
Test name
Test status
Simulation time 135566153 ps
CPU time 2.92 seconds
Started Jun 27 04:48:19 PM PDT 24
Finished Jun 27 04:48:22 PM PDT 24
Peak memory 206172 kb
Host smart-1a205b20-97fe-408d-ad4f-baeb803576ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=332507770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.332507770
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.4237708056
Short name T26
Test name
Test status
Simulation time 28581984 ps
CPU time 0.66 seconds
Started Jun 27 06:40:51 PM PDT 24
Finished Jun 27 06:41:39 PM PDT 24
Peak memory 206116 kb
Host smart-3d6bbd10-8b2b-4320-b076-b662e5085fa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42377
08056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.4237708056
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.1187543377
Short name T47
Test name
Test status
Simulation time 140446639 ps
CPU time 0.76 seconds
Started Jun 27 06:38:50 PM PDT 24
Finished Jun 27 06:38:53 PM PDT 24
Peak memory 206248 kb
Host smart-69a6ddc9-76f4-4252-be6e-9df6b3c50949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11875
43377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.1187543377
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1198421701
Short name T305
Test name
Test status
Simulation time 42950096 ps
CPU time 0.72 seconds
Started Jun 27 04:48:30 PM PDT 24
Finished Jun 27 04:48:34 PM PDT 24
Peak memory 204808 kb
Host smart-00086c9a-4a37-441d-a7d8-2609a1c11710
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1198421701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.1198421701
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.589087146
Short name T79
Test name
Test status
Simulation time 322895271 ps
CPU time 1.07 seconds
Started Jun 27 06:34:24 PM PDT 24
Finished Jun 27 06:34:34 PM PDT 24
Peak memory 206272 kb
Host smart-05558fae-f552-4f95-aeb1-955708ce02f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58908
7146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.589087146
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.2953934611
Short name T49
Test name
Test status
Simulation time 20169369275 ps
CPU time 19.84 seconds
Started Jun 27 06:34:24 PM PDT 24
Finished Jun 27 06:34:53 PM PDT 24
Peak memory 206212 kb
Host smart-bb03ecc6-ffa0-4db3-8d11-16c96a45c595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29539
34611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.2953934611
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3138433728
Short name T262
Test name
Test status
Simulation time 84134683 ps
CPU time 1.01 seconds
Started Jun 27 04:47:47 PM PDT 24
Finished Jun 27 04:47:50 PM PDT 24
Peak memory 206180 kb
Host smart-8ac1da38-82fd-44b1-8e56-3146c86e9aaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3138433728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.3138433728
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1321475413
Short name T300
Test name
Test status
Simulation time 42705916 ps
CPU time 0.7 seconds
Started Jun 27 04:48:32 PM PDT 24
Finished Jun 27 04:48:38 PM PDT 24
Peak memory 205948 kb
Host smart-82af460f-cca0-47cc-b6c5-02cf6e3c6d59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1321475413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.1321475413
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.799457252
Short name T31
Test name
Test status
Simulation time 168231051 ps
CPU time 0.79 seconds
Started Jun 27 06:34:40 PM PDT 24
Finished Jun 27 06:34:45 PM PDT 24
Peak memory 206268 kb
Host smart-26b10ef9-acc4-4dc9-b6a9-a4fcba17d74a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79945
7252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.799457252
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.1924626631
Short name T603
Test name
Test status
Simulation time 230185030 ps
CPU time 0.82 seconds
Started Jun 27 06:38:09 PM PDT 24
Finished Jun 27 06:38:16 PM PDT 24
Peak memory 206280 kb
Host smart-d88406f7-60b9-4f4f-b613-b80f2c111a82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19246
26631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.1924626631
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2807196594
Short name T287
Test name
Test status
Simulation time 541599358 ps
CPU time 4.1 seconds
Started Jun 27 04:48:13 PM PDT 24
Finished Jun 27 04:48:19 PM PDT 24
Peak memory 206100 kb
Host smart-639730a6-6445-47df-82e8-947bdbdd5b3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2807196594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.2807196594
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.143840662
Short name T2648
Test name
Test status
Simulation time 60855657 ps
CPU time 0.73 seconds
Started Jun 27 04:48:32 PM PDT 24
Finished Jun 27 04:48:39 PM PDT 24
Peak memory 205772 kb
Host smart-1117b28e-b381-4247-afca-66d1d132c7df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=143840662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.143840662
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.123111000
Short name T8
Test name
Test status
Simulation time 13481964380 ps
CPU time 12.93 seconds
Started Jun 27 06:39:16 PM PDT 24
Finished Jun 27 06:39:42 PM PDT 24
Peak memory 206416 kb
Host smart-69914e60-8c15-4e54-9186-ade2220107dd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=123111000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.123111000
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.1969828479
Short name T45
Test name
Test status
Simulation time 11390524765 ps
CPU time 27.4 seconds
Started Jun 27 06:36:11 PM PDT 24
Finished Jun 27 06:36:42 PM PDT 24
Peak memory 206428 kb
Host smart-5db8ed26-5f48-4a9f-a1f7-daee12ae869d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19698
28479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.1969828479
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.829801110
Short name T230
Test name
Test status
Simulation time 561534744 ps
CPU time 2.91 seconds
Started Jun 27 04:48:21 PM PDT 24
Finished Jun 27 04:48:26 PM PDT 24
Peak memory 206400 kb
Host smart-4fc4d838-6d25-4584-bfc1-ea627d749f35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=829801110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.829801110
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2448546734
Short name T245
Test name
Test status
Simulation time 103352293 ps
CPU time 2.97 seconds
Started Jun 27 04:47:55 PM PDT 24
Finished Jun 27 04:48:01 PM PDT 24
Peak memory 221600 kb
Host smart-6990027f-2ed9-437d-b468-03932561154c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2448546734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2448546734
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.2455117251
Short name T61
Test name
Test status
Simulation time 1255093348 ps
CPU time 2.78 seconds
Started Jun 27 06:37:47 PM PDT 24
Finished Jun 27 06:37:55 PM PDT 24
Peak memory 206364 kb
Host smart-683ff1c1-003d-478f-b549-acbf8eb425da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24551
17251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.2455117251
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.2786917243
Short name T72
Test name
Test status
Simulation time 573237303 ps
CPU time 1.44 seconds
Started Jun 27 06:34:21 PM PDT 24
Finished Jun 27 06:34:28 PM PDT 24
Peak memory 206264 kb
Host smart-666a3b8a-66f3-4319-b0ed-e9d74d8290cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27869
17243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.2786917243
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.2765054880
Short name T151
Test name
Test status
Simulation time 8648048411 ps
CPU time 53.75 seconds
Started Jun 27 06:35:50 PM PDT 24
Finished Jun 27 06:36:48 PM PDT 24
Peak memory 206484 kb
Host smart-638699f4-4954-4458-aa3c-9933655cd091
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2765054880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.2765054880
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.2408889655
Short name T191
Test name
Test status
Simulation time 46861653 ps
CPU time 0.69 seconds
Started Jun 27 06:36:59 PM PDT 24
Finished Jun 27 06:37:07 PM PDT 24
Peak memory 206364 kb
Host smart-6e65719f-37a0-4a30-a208-472d4cd52e08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2408889655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.2408889655
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.3064374860
Short name T147
Test name
Test status
Simulation time 4395502626 ps
CPU time 41.76 seconds
Started Jun 27 06:38:53 PM PDT 24
Finished Jun 27 06:39:37 PM PDT 24
Peak memory 206384 kb
Host smart-a68fa541-c0ee-4063-8e87-be789733d1ac
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3064374860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.3064374860
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.3042115591
Short name T54
Test name
Test status
Simulation time 294681802 ps
CPU time 1.01 seconds
Started Jun 27 06:34:22 PM PDT 24
Finished Jun 27 06:34:30 PM PDT 24
Peak memory 206260 kb
Host smart-72ca2118-2ffc-49e3-aca7-dbc83a1828bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30421
15591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.3042115591
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.583651564
Short name T85
Test name
Test status
Simulation time 181603493 ps
CPU time 0.78 seconds
Started Jun 27 06:34:17 PM PDT 24
Finished Jun 27 06:34:20 PM PDT 24
Peak memory 206264 kb
Host smart-e604668f-fa98-4524-b819-b37804ea187c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58365
1564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.583651564
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.904896649
Short name T307
Test name
Test status
Simulation time 725114775 ps
CPU time 4.32 seconds
Started Jun 27 04:48:41 PM PDT 24
Finished Jun 27 04:48:47 PM PDT 24
Peak memory 206128 kb
Host smart-a0ae8ad4-f3d9-4dd1-836d-6330c80d0d8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=904896649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.904896649
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3137523308
Short name T297
Test name
Test status
Simulation time 43924602 ps
CPU time 0.67 seconds
Started Jun 27 04:48:27 PM PDT 24
Finished Jun 27 04:48:29 PM PDT 24
Peak memory 205908 kb
Host smart-0c24087d-c05c-42f0-b6f6-f772e7a7d830
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3137523308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.3137523308
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.357568697
Short name T226
Test name
Test status
Simulation time 76656536 ps
CPU time 0.94 seconds
Started Jun 27 04:48:10 PM PDT 24
Finished Jun 27 04:48:12 PM PDT 24
Peak memory 206040 kb
Host smart-03d04c3e-6d13-4e16-a34d-2970329dddc2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=357568697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.357568697
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.44957757
Short name T148
Test name
Test status
Simulation time 1428032753 ps
CPU time 2.86 seconds
Started Jun 27 06:34:44 PM PDT 24
Finished Jun 27 06:34:57 PM PDT 24
Peak memory 206380 kb
Host smart-6e8a0a11-98fb-492b-9c17-547b4ea4e496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44957
757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.44957757
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.2091511583
Short name T398
Test name
Test status
Simulation time 150139021 ps
CPU time 0.76 seconds
Started Jun 27 06:36:07 PM PDT 24
Finished Jun 27 06:36:12 PM PDT 24
Peak memory 206300 kb
Host smart-79236b02-f684-4d81-b74c-62b2eced33b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20915
11583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.2091511583
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.2035181309
Short name T188
Test name
Test status
Simulation time 424879568 ps
CPU time 2.49 seconds
Started Jun 27 06:34:38 PM PDT 24
Finished Jun 27 06:34:44 PM PDT 24
Peak memory 206440 kb
Host smart-0c61a640-ccfe-47c2-8866-65f5a649f6ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20351
81309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.2035181309
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.1923597596
Short name T150
Test name
Test status
Simulation time 14879778607 ps
CPU time 328.21 seconds
Started Jun 27 06:34:46 PM PDT 24
Finished Jun 27 06:40:25 PM PDT 24
Peak memory 206412 kb
Host smart-7bbd909a-d9a1-4efa-8ab0-d0f450cdb0ff
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1923597596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.1923597596
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.2648686298
Short name T67
Test name
Test status
Simulation time 131511639 ps
CPU time 0.74 seconds
Started Jun 27 06:34:41 PM PDT 24
Finished Jun 27 06:34:51 PM PDT 24
Peak memory 206220 kb
Host smart-949d6094-8bdf-4f7e-aa12-7fdfcd333748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26486
86298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.2648686298
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.2596962357
Short name T937
Test name
Test status
Simulation time 1142992038 ps
CPU time 2.7 seconds
Started Jun 27 06:42:53 PM PDT 24
Finished Jun 27 06:43:15 PM PDT 24
Peak memory 206384 kb
Host smart-b6deaea1-bc8b-4b11-aaf4-e394d79d29b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25969
62357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.2596962357
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.3765612879
Short name T142
Test name
Test status
Simulation time 4863083158 ps
CPU time 107.27 seconds
Started Jun 27 06:35:31 PM PDT 24
Finished Jun 27 06:37:23 PM PDT 24
Peak memory 206340 kb
Host smart-de877d47-e620-4c3f-a021-4f27aa3f908a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3765612879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.3765612879
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.2487007572
Short name T60
Test name
Test status
Simulation time 173390767 ps
CPU time 0.84 seconds
Started Jun 27 06:34:22 PM PDT 24
Finished Jun 27 06:34:30 PM PDT 24
Peak memory 206268 kb
Host smart-e6e71cb3-44d2-4d4c-b89b-aa85e63c0db0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24870
07572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.2487007572
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.3247040134
Short name T68
Test name
Test status
Simulation time 4162010352 ps
CPU time 9.5 seconds
Started Jun 27 06:34:21 PM PDT 24
Finished Jun 27 06:34:35 PM PDT 24
Peak memory 206472 kb
Host smart-2e4e8469-e034-46eb-b456-8463239c7012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32470
40134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.3247040134
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.1909861183
Short name T69
Test name
Test status
Simulation time 179515290 ps
CPU time 0.81 seconds
Started Jun 27 06:34:20 PM PDT 24
Finished Jun 27 06:34:23 PM PDT 24
Peak memory 206268 kb
Host smart-cd044be2-dbf0-4a78-9e33-4a0ebb2a2cc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19098
61183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.1909861183
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.3360526348
Short name T1443
Test name
Test status
Simulation time 158124797 ps
CPU time 0.79 seconds
Started Jun 27 06:34:25 PM PDT 24
Finished Jun 27 06:34:34 PM PDT 24
Peak memory 206264 kb
Host smart-4a5f67c2-74a0-4cac-aca8-d7b5fc172613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33605
26348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.3360526348
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.2130925274
Short name T883
Test name
Test status
Simulation time 42904629 ps
CPU time 0.66 seconds
Started Jun 27 06:36:05 PM PDT 24
Finished Jun 27 06:36:08 PM PDT 24
Peak memory 206260 kb
Host smart-db82dc68-99fa-4f68-b4d2-5cabe961d852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21309
25274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.2130925274
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.132129442
Short name T53
Test name
Test status
Simulation time 192502543 ps
CPU time 0.82 seconds
Started Jun 27 06:34:42 PM PDT 24
Finished Jun 27 06:34:52 PM PDT 24
Peak memory 206292 kb
Host smart-bf681d16-a2f2-45e0-8dfa-645f0e81b1ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13212
9442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.132129442
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.4006652434
Short name T116
Test name
Test status
Simulation time 237346328 ps
CPU time 0.93 seconds
Started Jun 27 06:34:23 PM PDT 24
Finished Jun 27 06:34:32 PM PDT 24
Peak memory 206304 kb
Host smart-59813b3d-2d93-4709-a006-d1e4aa9706ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40066
52434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.4006652434
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.1893947323
Short name T184
Test name
Test status
Simulation time 8108140909 ps
CPU time 34.34 seconds
Started Jun 27 06:34:23 PM PDT 24
Finished Jun 27 06:35:05 PM PDT 24
Peak memory 206476 kb
Host smart-60c4fd9d-f79c-4221-be35-20cad5ff99e0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1893947323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.1893947323
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.875293196
Short name T55
Test name
Test status
Simulation time 385804827 ps
CPU time 1.31 seconds
Started Jun 27 06:34:25 PM PDT 24
Finished Jun 27 06:34:35 PM PDT 24
Peak memory 206260 kb
Host smart-78575d6b-2529-4e8c-871b-1708d75ee154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87529
3196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.875293196
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.3857936573
Short name T134
Test name
Test status
Simulation time 217250405 ps
CPU time 0.85 seconds
Started Jun 27 06:34:43 PM PDT 24
Finished Jun 27 06:34:53 PM PDT 24
Peak memory 206276 kb
Host smart-4f3dbaea-e078-4d2f-bdc0-5112e4c33ec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38579
36573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.3857936573
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.94731584
Short name T2457
Test name
Test status
Simulation time 205103883 ps
CPU time 0.87 seconds
Started Jun 27 06:36:40 PM PDT 24
Finished Jun 27 06:36:47 PM PDT 24
Peak memory 206264 kb
Host smart-95eb4afe-18c5-4374-9be6-5883db376c15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94731
584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.94731584
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.1554593160
Short name T1306
Test name
Test status
Simulation time 17741968209 ps
CPU time 41.5 seconds
Started Jun 27 06:36:37 PM PDT 24
Finished Jun 27 06:37:23 PM PDT 24
Peak memory 206516 kb
Host smart-86195b03-e9fe-4151-afb2-f620fd98ab9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15545
93160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.1554593160
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.2694508384
Short name T119
Test name
Test status
Simulation time 214512108 ps
CPU time 0.85 seconds
Started Jun 27 06:36:53 PM PDT 24
Finished Jun 27 06:36:56 PM PDT 24
Peak memory 206288 kb
Host smart-c6871a48-ae9d-430c-b382-db4a689f03ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26945
08384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.2694508384
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.1309063987
Short name T127
Test name
Test status
Simulation time 202432095 ps
CPU time 0.83 seconds
Started Jun 27 06:37:01 PM PDT 24
Finished Jun 27 06:37:11 PM PDT 24
Peak memory 206304 kb
Host smart-199703b7-59ac-4067-8629-1472a838e5f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13090
63987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.1309063987
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.312992396
Short name T214
Test name
Test status
Simulation time 216162815 ps
CPU time 0.82 seconds
Started Jun 27 06:36:54 PM PDT 24
Finished Jun 27 06:36:59 PM PDT 24
Peak memory 206268 kb
Host smart-d6775b4b-818c-4a1e-8f6e-429d31738723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31299
2396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.312992396
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.557288175
Short name T1299
Test name
Test status
Simulation time 171936774 ps
CPU time 0.81 seconds
Started Jun 27 06:37:44 PM PDT 24
Finished Jun 27 06:37:47 PM PDT 24
Peak memory 206268 kb
Host smart-57f38660-d85a-474d-998b-ee288646c5ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55728
8175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.557288175
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.2453792942
Short name T136
Test name
Test status
Simulation time 232714442 ps
CPU time 0.96 seconds
Started Jun 27 06:38:07 PM PDT 24
Finished Jun 27 06:38:13 PM PDT 24
Peak memory 206224 kb
Host smart-9a4512e5-b9a0-4e34-84ee-3242c41cd26e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24537
92942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.2453792942
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.2230655267
Short name T139
Test name
Test status
Simulation time 237118359 ps
CPU time 0.89 seconds
Started Jun 27 06:38:23 PM PDT 24
Finished Jun 27 06:38:28 PM PDT 24
Peak memory 206284 kb
Host smart-7fd8a1f6-290f-4e9b-bcb2-20b015924cc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22306
55267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.2230655267
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.1488405932
Short name T114
Test name
Test status
Simulation time 185746327 ps
CPU time 0.8 seconds
Started Jun 27 06:38:33 PM PDT 24
Finished Jun 27 06:38:37 PM PDT 24
Peak memory 206280 kb
Host smart-9fcc824e-4789-4a62-af15-2786d63c9998
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14884
05932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.1488405932
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.3099740807
Short name T121
Test name
Test status
Simulation time 214607610 ps
CPU time 0.89 seconds
Started Jun 27 06:40:41 PM PDT 24
Finished Jun 27 06:41:12 PM PDT 24
Peak memory 206256 kb
Host smart-369c623b-ec1c-4c05-9311-fc370e9b782b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30997
40807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.3099740807
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1055832483
Short name T2633
Test name
Test status
Simulation time 82762286 ps
CPU time 1.94 seconds
Started Jun 27 04:47:49 PM PDT 24
Finished Jun 27 04:47:53 PM PDT 24
Peak memory 206172 kb
Host smart-1fd5f4cf-0a59-427e-955f-6bf4839bcb65
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1055832483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.1055832483
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1138981389
Short name T263
Test name
Test status
Simulation time 1623233092 ps
CPU time 8.54 seconds
Started Jun 27 04:48:13 PM PDT 24
Finished Jun 27 04:48:24 PM PDT 24
Peak memory 206068 kb
Host smart-31820157-9bde-409f-a8a7-bba836cedbff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1138981389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.1138981389
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1787044969
Short name T2697
Test name
Test status
Simulation time 48477798 ps
CPU time 0.77 seconds
Started Jun 27 04:47:56 PM PDT 24
Finished Jun 27 04:48:00 PM PDT 24
Peak memory 206028 kb
Host smart-202cc18d-7528-4e1c-8776-b794c35852d0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1787044969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1787044969
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.718220501
Short name T242
Test name
Test status
Simulation time 150418645 ps
CPU time 1.31 seconds
Started Jun 27 04:47:56 PM PDT 24
Finished Jun 27 04:47:59 PM PDT 24
Peak memory 214384 kb
Host smart-2669d4c9-a81c-4a97-b930-4ca7bf1cf852
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718220501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev
_csr_mem_rw_with_rand_reset.718220501
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.141300902
Short name T272
Test name
Test status
Simulation time 117456843 ps
CPU time 1.08 seconds
Started Jun 27 04:48:00 PM PDT 24
Finished Jun 27 04:48:03 PM PDT 24
Peak memory 206180 kb
Host smart-2dfcfa96-efb0-419b-81f0-a092fa709b48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=141300902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.141300902
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.574319766
Short name T206
Test name
Test status
Simulation time 53215557 ps
CPU time 0.64 seconds
Started Jun 27 04:48:06 PM PDT 24
Finished Jun 27 04:48:08 PM PDT 24
Peak memory 205884 kb
Host smart-18ca149e-65b7-4c95-990e-caa5fa18fd78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=574319766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.574319766
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3218315843
Short name T2703
Test name
Test status
Simulation time 71944375 ps
CPU time 2.3 seconds
Started Jun 27 04:48:10 PM PDT 24
Finished Jun 27 04:48:13 PM PDT 24
Peak memory 214368 kb
Host smart-0490d3d3-5aa8-4971-b808-a3ba7491418d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3218315843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.3218315843
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.32793168
Short name T2674
Test name
Test status
Simulation time 670936787 ps
CPU time 4.44 seconds
Started Jun 27 04:48:13 PM PDT 24
Finished Jun 27 04:48:20 PM PDT 24
Peak memory 205972 kb
Host smart-680edda8-89e5-4dc0-8787-efb79b625481
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=32793168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.32793168
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.780853039
Short name T2708
Test name
Test status
Simulation time 56086975 ps
CPU time 1.05 seconds
Started Jun 27 04:48:00 PM PDT 24
Finished Jun 27 04:48:03 PM PDT 24
Peak memory 205804 kb
Host smart-d6c8de13-8a52-4b94-8898-2d37ae7184ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=780853039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.780853039
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1715956808
Short name T243
Test name
Test status
Simulation time 103668359 ps
CPU time 1.97 seconds
Started Jun 27 04:48:15 PM PDT 24
Finished Jun 27 04:48:18 PM PDT 24
Peak memory 214324 kb
Host smart-704541f4-f615-4726-92c3-73017565323e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1715956808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.1715956808
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2056820337
Short name T2691
Test name
Test status
Simulation time 310464426 ps
CPU time 2.25 seconds
Started Jun 27 04:47:49 PM PDT 24
Finished Jun 27 04:47:54 PM PDT 24
Peak memory 206148 kb
Host smart-4dcda410-09c3-4c4a-b165-b9372aa3d3cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2056820337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.2056820337
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.344998643
Short name T2629
Test name
Test status
Simulation time 104232077 ps
CPU time 1.93 seconds
Started Jun 27 04:47:56 PM PDT 24
Finished Jun 27 04:48:01 PM PDT 24
Peak memory 206076 kb
Host smart-6ff92076-f70c-4a42-a024-579c21b0a1dd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=344998643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.344998643
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2487425750
Short name T267
Test name
Test status
Simulation time 819117114 ps
CPU time 4.44 seconds
Started Jun 27 04:48:10 PM PDT 24
Finished Jun 27 04:48:15 PM PDT 24
Peak memory 206144 kb
Host smart-a798b0e6-31a4-472c-8ddf-e5016f924d2e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2487425750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.2487425750
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.446828633
Short name T2649
Test name
Test status
Simulation time 85442005 ps
CPU time 0.85 seconds
Started Jun 27 04:48:13 PM PDT 24
Finished Jun 27 04:48:16 PM PDT 24
Peak memory 206028 kb
Host smart-84f12957-0489-4571-811a-312b160cfc0f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=446828633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.446828633
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2714776177
Short name T231
Test name
Test status
Simulation time 116244790 ps
CPU time 1.31 seconds
Started Jun 27 04:48:03 PM PDT 24
Finished Jun 27 04:48:05 PM PDT 24
Peak memory 214464 kb
Host smart-2850514c-455f-4005-bbda-81c0e5c92a3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714776177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.2714776177
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3495515941
Short name T2652
Test name
Test status
Simulation time 61621180 ps
CPU time 0.68 seconds
Started Jun 27 04:48:04 PM PDT 24
Finished Jun 27 04:48:06 PM PDT 24
Peak memory 205832 kb
Host smart-a4078ebb-18b6-45b6-b440-00a735ca3e1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3495515941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.3495515941
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2313208793
Short name T2727
Test name
Test status
Simulation time 131652556 ps
CPU time 1.55 seconds
Started Jun 27 04:47:56 PM PDT 24
Finished Jun 27 04:48:00 PM PDT 24
Peak memory 214216 kb
Host smart-02b09b42-ce64-4dd7-9618-fc8a02c36e1b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2313208793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2313208793
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1193824589
Short name T2665
Test name
Test status
Simulation time 693164607 ps
CPU time 4.68 seconds
Started Jun 27 04:47:55 PM PDT 24
Finished Jun 27 04:48:02 PM PDT 24
Peak memory 205944 kb
Host smart-cb7d9ada-f1cc-43b6-84b8-0b762a690f4b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1193824589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.1193824589
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1152088244
Short name T2640
Test name
Test status
Simulation time 305725433 ps
CPU time 1.7 seconds
Started Jun 27 04:47:56 PM PDT 24
Finished Jun 27 04:48:01 PM PDT 24
Peak memory 206136 kb
Host smart-603443be-9787-482e-866f-053220da13a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1152088244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.1152088244
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1423486208
Short name T2642
Test name
Test status
Simulation time 166635248 ps
CPU time 1.94 seconds
Started Jun 27 04:48:00 PM PDT 24
Finished Jun 27 04:48:04 PM PDT 24
Peak memory 221420 kb
Host smart-54132abf-c93c-4c18-af88-78a62fb184c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1423486208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.1423486208
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3856318018
Short name T284
Test name
Test status
Simulation time 636493688 ps
CPU time 2.87 seconds
Started Jun 27 04:48:09 PM PDT 24
Finished Jun 27 04:48:14 PM PDT 24
Peak memory 206176 kb
Host smart-be908dd6-c9cb-4bce-adb0-83d639b57456
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3856318018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.3856318018
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2372370820
Short name T2701
Test name
Test status
Simulation time 114436827 ps
CPU time 1.37 seconds
Started Jun 27 04:48:22 PM PDT 24
Finished Jun 27 04:48:25 PM PDT 24
Peak memory 214292 kb
Host smart-aada1330-f156-497e-96ca-96ce9441b133
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372370820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.2372370820
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2972725515
Short name T264
Test name
Test status
Simulation time 50637192 ps
CPU time 0.8 seconds
Started Jun 27 04:48:31 PM PDT 24
Finished Jun 27 04:48:37 PM PDT 24
Peak memory 206024 kb
Host smart-3cf5d12e-1f55-4e68-95cb-0aa424a8d540
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2972725515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.2972725515
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.4237680166
Short name T303
Test name
Test status
Simulation time 32631278 ps
CPU time 0.79 seconds
Started Jun 27 04:48:32 PM PDT 24
Finished Jun 27 04:48:38 PM PDT 24
Peak memory 205968 kb
Host smart-71d6edda-5224-4255-90e2-4b91c2eb9a6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4237680166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.4237680166
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3054122276
Short name T273
Test name
Test status
Simulation time 122452257 ps
CPU time 1.44 seconds
Started Jun 27 04:48:30 PM PDT 24
Finished Jun 27 04:48:35 PM PDT 24
Peak memory 206088 kb
Host smart-3e006cf6-6229-4641-a8ba-837fa2a7c440
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3054122276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.3054122276
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2556503277
Short name T2678
Test name
Test status
Simulation time 154938735 ps
CPU time 1.63 seconds
Started Jun 27 04:48:19 PM PDT 24
Finished Jun 27 04:48:22 PM PDT 24
Peak memory 206248 kb
Host smart-6cedbce1-d399-45b6-addf-bbc6c87d660d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2556503277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.2556503277
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3599626020
Short name T285
Test name
Test status
Simulation time 852064174 ps
CPU time 3.46 seconds
Started Jun 27 04:48:20 PM PDT 24
Finished Jun 27 04:48:25 PM PDT 24
Peak memory 206044 kb
Host smart-c51936f2-d1e9-4458-aad9-c38b60783a3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3599626020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.3599626020
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2629929105
Short name T2700
Test name
Test status
Simulation time 92122221 ps
CPU time 1.18 seconds
Started Jun 27 04:48:28 PM PDT 24
Finished Jun 27 04:48:31 PM PDT 24
Peak memory 214412 kb
Host smart-32ea81a8-07a7-4bc8-bbfb-9dbe211f1941
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629929105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.2629929105
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2871890538
Short name T2677
Test name
Test status
Simulation time 67968197 ps
CPU time 0.79 seconds
Started Jun 27 04:48:32 PM PDT 24
Finished Jun 27 04:48:39 PM PDT 24
Peak memory 206028 kb
Host smart-53b79287-0441-434d-bd80-5f83bceb66bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2871890538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.2871890538
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3343251774
Short name T296
Test name
Test status
Simulation time 101390201 ps
CPU time 0.78 seconds
Started Jun 27 04:48:21 PM PDT 24
Finished Jun 27 04:48:23 PM PDT 24
Peak memory 206012 kb
Host smart-a925aa19-b860-4e46-b8d6-07c9142d418d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3343251774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.3343251774
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2498569619
Short name T2641
Test name
Test status
Simulation time 127143106 ps
CPU time 1.18 seconds
Started Jun 27 04:48:26 PM PDT 24
Finished Jun 27 04:48:29 PM PDT 24
Peak memory 206120 kb
Host smart-170e0f86-8b23-417f-8f4f-1cad2dc1ec91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2498569619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.2498569619
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1701272185
Short name T2647
Test name
Test status
Simulation time 223460081 ps
CPU time 2.37 seconds
Started Jun 27 04:48:26 PM PDT 24
Finished Jun 27 04:48:29 PM PDT 24
Peak memory 222144 kb
Host smart-56f563b6-e4b9-4a85-84d7-af3d1a757c2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1701272185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.1701272185
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.4275783566
Short name T283
Test name
Test status
Simulation time 526044757 ps
CPU time 2.78 seconds
Started Jun 27 04:48:26 PM PDT 24
Finished Jun 27 04:48:30 PM PDT 24
Peak memory 206144 kb
Host smart-0908fb92-d8a9-4271-b1db-b1f16679b880
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4275783566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.4275783566
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.4022907482
Short name T225
Test name
Test status
Simulation time 197981633 ps
CPU time 2.17 seconds
Started Jun 27 04:48:28 PM PDT 24
Finished Jun 27 04:48:32 PM PDT 24
Peak memory 214328 kb
Host smart-6dfeec1f-c3f6-40c7-9728-55b337a96b56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022907482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.4022907482
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2191948710
Short name T2713
Test name
Test status
Simulation time 105593619 ps
CPU time 1.04 seconds
Started Jun 27 04:48:27 PM PDT 24
Finished Jun 27 04:48:29 PM PDT 24
Peak memory 206088 kb
Host smart-4bcc6705-6666-4b32-aaa8-95d3134a43a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2191948710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.2191948710
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.351064519
Short name T2654
Test name
Test status
Simulation time 49916981 ps
CPU time 0.73 seconds
Started Jun 27 04:48:32 PM PDT 24
Finished Jun 27 04:48:37 PM PDT 24
Peak memory 206008 kb
Host smart-2d57bff1-0fcc-4467-b934-131d1482cead
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=351064519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.351064519
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.517636390
Short name T2661
Test name
Test status
Simulation time 121421662 ps
CPU time 1.23 seconds
Started Jun 27 04:48:21 PM PDT 24
Finished Jun 27 04:48:23 PM PDT 24
Peak memory 206192 kb
Host smart-822ebaa2-d883-486d-8087-6af7e3b2313f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=517636390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.517636390
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.4036663669
Short name T238
Test name
Test status
Simulation time 168813146 ps
CPU time 1.77 seconds
Started Jun 27 04:48:32 PM PDT 24
Finished Jun 27 04:48:39 PM PDT 24
Peak memory 219224 kb
Host smart-2137c8e3-f000-4d93-a13a-18551394b1b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036663669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.4036663669
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.284994315
Short name T2694
Test name
Test status
Simulation time 55903524 ps
CPU time 0.83 seconds
Started Jun 27 04:48:27 PM PDT 24
Finished Jun 27 04:48:30 PM PDT 24
Peak memory 205952 kb
Host smart-d592097f-c103-4133-8a88-8be676e97120
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=284994315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.284994315
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2494676648
Short name T2682
Test name
Test status
Simulation time 78644526 ps
CPU time 0.71 seconds
Started Jun 27 04:48:29 PM PDT 24
Finished Jun 27 04:48:34 PM PDT 24
Peak memory 205856 kb
Host smart-ac440488-9c48-4120-862c-0f6123810d3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2494676648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.2494676648
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.320215176
Short name T2679
Test name
Test status
Simulation time 62173239 ps
CPU time 1.02 seconds
Started Jun 27 04:48:31 PM PDT 24
Finished Jun 27 04:48:37 PM PDT 24
Peak memory 206060 kb
Host smart-ce43313c-c082-4109-989c-2df2bf29b4ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=320215176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.320215176
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.4211967825
Short name T2660
Test name
Test status
Simulation time 87923498 ps
CPU time 2.41 seconds
Started Jun 27 04:48:29 PM PDT 24
Finished Jun 27 04:48:35 PM PDT 24
Peak memory 222048 kb
Host smart-4b137ff0-7a45-41f5-b137-8bd4912a2f7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4211967825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.4211967825
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3431944235
Short name T2662
Test name
Test status
Simulation time 107247379 ps
CPU time 1.35 seconds
Started Jun 27 04:48:22 PM PDT 24
Finished Jun 27 04:48:25 PM PDT 24
Peak memory 214400 kb
Host smart-8319c994-387b-4c02-a4c9-79b0fa6e0500
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431944235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.3431944235
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3806075686
Short name T260
Test name
Test status
Simulation time 73198476 ps
CPU time 1 seconds
Started Jun 27 04:48:28 PM PDT 24
Finished Jun 27 04:48:31 PM PDT 24
Peak memory 206008 kb
Host smart-035b1936-2928-4265-8f1a-2ddb21bc4130
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3806075686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.3806075686
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.412268526
Short name T2639
Test name
Test status
Simulation time 264854977 ps
CPU time 1.56 seconds
Started Jun 27 04:48:33 PM PDT 24
Finished Jun 27 04:48:40 PM PDT 24
Peak memory 206144 kb
Host smart-1b1843ef-a731-4923-9e62-9e135eca85f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=412268526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.412268526
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2688011562
Short name T2671
Test name
Test status
Simulation time 249446380 ps
CPU time 2.67 seconds
Started Jun 27 04:48:22 PM PDT 24
Finished Jun 27 04:48:26 PM PDT 24
Peak memory 214356 kb
Host smart-283b3065-b714-4ea4-bb61-88df5d58ab19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2688011562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.2688011562
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.315129764
Short name T289
Test name
Test status
Simulation time 501107399 ps
CPU time 4.11 seconds
Started Jun 27 04:48:30 PM PDT 24
Finished Jun 27 04:48:39 PM PDT 24
Peak memory 206200 kb
Host smart-c2597f4c-902f-4d62-941b-ee12d2afbc8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=315129764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.315129764
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1715665441
Short name T235
Test name
Test status
Simulation time 74506386 ps
CPU time 1.81 seconds
Started Jun 27 04:48:32 PM PDT 24
Finished Jun 27 04:48:39 PM PDT 24
Peak memory 214332 kb
Host smart-593e3a23-0d55-4e25-973f-c49aa18d5822
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715665441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.1715665441
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2949518064
Short name T281
Test name
Test status
Simulation time 78448486 ps
CPU time 0.78 seconds
Started Jun 27 04:48:32 PM PDT 24
Finished Jun 27 04:48:38 PM PDT 24
Peak memory 205556 kb
Host smart-dc77e851-b10d-4f91-a229-86f9ba13adc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2949518064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.2949518064
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2204618366
Short name T2721
Test name
Test status
Simulation time 105280591 ps
CPU time 0.79 seconds
Started Jun 27 04:48:32 PM PDT 24
Finished Jun 27 04:48:37 PM PDT 24
Peak memory 205980 kb
Host smart-ffac302f-db3a-45ad-9241-439f89753cc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2204618366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.2204618366
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.2387245492
Short name T2632
Test name
Test status
Simulation time 174899851 ps
CPU time 1.78 seconds
Started Jun 27 04:48:34 PM PDT 24
Finished Jun 27 04:48:41 PM PDT 24
Peak memory 206164 kb
Host smart-18ce80fc-ed4e-4ee7-948f-e2eb259c6f0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2387245492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.2387245492
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.683539422
Short name T2683
Test name
Test status
Simulation time 94040267 ps
CPU time 2.58 seconds
Started Jun 27 04:48:32 PM PDT 24
Finished Jun 27 04:48:40 PM PDT 24
Peak memory 222080 kb
Host smart-7793e361-a3b4-4ba9-9d9d-107c131aa58e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=683539422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.683539422
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3277970978
Short name T2645
Test name
Test status
Simulation time 655725547 ps
CPU time 3.06 seconds
Started Jun 27 04:48:29 PM PDT 24
Finished Jun 27 04:48:35 PM PDT 24
Peak memory 206100 kb
Host smart-6eb0af4d-2cf8-4694-8e35-dcad9921a4e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3277970978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.3277970978
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3587180455
Short name T200
Test name
Test status
Simulation time 135973487 ps
CPU time 1.19 seconds
Started Jun 27 04:48:31 PM PDT 24
Finished Jun 27 04:48:37 PM PDT 24
Peak memory 216244 kb
Host smart-bce478d0-dd14-489e-bbf6-dba7b604549c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587180455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.3587180455
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1446649488
Short name T275
Test name
Test status
Simulation time 67187745 ps
CPU time 0.9 seconds
Started Jun 27 04:48:21 PM PDT 24
Finished Jun 27 04:48:24 PM PDT 24
Peak memory 206060 kb
Host smart-756d209f-ff55-48ed-89de-f5151ad4462b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1446649488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.1446649488
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.3785156602
Short name T298
Test name
Test status
Simulation time 39157551 ps
CPU time 0.74 seconds
Started Jun 27 04:48:23 PM PDT 24
Finished Jun 27 04:48:24 PM PDT 24
Peak memory 206216 kb
Host smart-ce478100-6728-4e6c-8e62-8689288c203a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3785156602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.3785156602
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.199392783
Short name T2643
Test name
Test status
Simulation time 110310164 ps
CPU time 1.83 seconds
Started Jun 27 04:48:29 PM PDT 24
Finished Jun 27 04:48:35 PM PDT 24
Peak memory 206124 kb
Host smart-343919ab-29f7-4b7b-b913-ffc4be498468
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=199392783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.199392783
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1956805865
Short name T236
Test name
Test status
Simulation time 295610108 ps
CPU time 2.75 seconds
Started Jun 27 04:48:32 PM PDT 24
Finished Jun 27 04:48:39 PM PDT 24
Peak memory 221836 kb
Host smart-99121840-b87a-41e0-ad93-7e30dd451287
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1956805865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.1956805865
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1423014379
Short name T2686
Test name
Test status
Simulation time 510983433 ps
CPU time 2.74 seconds
Started Jun 27 04:48:33 PM PDT 24
Finished Jun 27 04:48:41 PM PDT 24
Peak memory 206104 kb
Host smart-76f8abcf-2a6b-4ddb-8ed1-280909715656
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1423014379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.1423014379
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1966351841
Short name T2680
Test name
Test status
Simulation time 204615594 ps
CPU time 1.84 seconds
Started Jun 27 04:48:28 PM PDT 24
Finished Jun 27 04:48:33 PM PDT 24
Peak memory 214296 kb
Host smart-d730f5c4-fa44-4b45-8208-36cf279f4bcc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966351841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.1966351841
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.3219812178
Short name T2710
Test name
Test status
Simulation time 87559108 ps
CPU time 0.82 seconds
Started Jun 27 04:48:32 PM PDT 24
Finished Jun 27 04:48:37 PM PDT 24
Peak memory 205960 kb
Host smart-3245bcbc-82d6-4caa-b57b-b99232bb7242
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3219812178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.3219812178
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1007404510
Short name T2695
Test name
Test status
Simulation time 147013026 ps
CPU time 1.03 seconds
Started Jun 27 04:48:32 PM PDT 24
Finished Jun 27 04:48:38 PM PDT 24
Peak memory 206128 kb
Host smart-e2a27b40-ef88-4be6-9aa7-238c37eedcb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1007404510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.1007404510
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3779998006
Short name T2690
Test name
Test status
Simulation time 72757064 ps
CPU time 1.73 seconds
Started Jun 27 04:48:29 PM PDT 24
Finished Jun 27 04:48:34 PM PDT 24
Peak memory 221812 kb
Host smart-f08a026c-6f78-4dc0-be6e-9a3c90a6886a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3779998006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.3779998006
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1500360184
Short name T198
Test name
Test status
Simulation time 102320143 ps
CPU time 1.32 seconds
Started Jun 27 04:48:29 PM PDT 24
Finished Jun 27 04:48:33 PM PDT 24
Peak memory 214220 kb
Host smart-7950d4ef-53a8-4b46-9160-be0331bb8f40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500360184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.1500360184
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1041342946
Short name T2718
Test name
Test status
Simulation time 50821321 ps
CPU time 0.85 seconds
Started Jun 27 04:48:28 PM PDT 24
Finished Jun 27 04:48:32 PM PDT 24
Peak memory 206028 kb
Host smart-34c336e7-00c5-4760-9655-81c99fde0cb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1041342946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.1041342946
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.1116503045
Short name T2693
Test name
Test status
Simulation time 53407874 ps
CPU time 0.67 seconds
Started Jun 27 04:48:32 PM PDT 24
Finished Jun 27 04:48:38 PM PDT 24
Peak memory 205916 kb
Host smart-4d4e77f5-2740-4ed5-9ee1-5fefe026b960
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1116503045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.1116503045
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3191444130
Short name T2726
Test name
Test status
Simulation time 188337675 ps
CPU time 1.39 seconds
Started Jun 27 04:48:32 PM PDT 24
Finished Jun 27 04:48:40 PM PDT 24
Peak memory 206032 kb
Host smart-653c3a89-7ff0-457d-a21c-fa2fa5761693
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3191444130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.3191444130
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2146631168
Short name T237
Test name
Test status
Simulation time 134334143 ps
CPU time 1.41 seconds
Started Jun 27 04:48:30 PM PDT 24
Finished Jun 27 04:48:36 PM PDT 24
Peak memory 206028 kb
Host smart-cbfabc61-13ed-4f8d-bd18-d97a0ecd42d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2146631168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.2146631168
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.626960376
Short name T2728
Test name
Test status
Simulation time 756862668 ps
CPU time 4.31 seconds
Started Jun 27 04:48:32 PM PDT 24
Finished Jun 27 04:48:42 PM PDT 24
Peak memory 205844 kb
Host smart-8e5b26d4-b796-4daf-bfc5-b3c795903d2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=626960376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.626960376
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.141642718
Short name T222
Test name
Test status
Simulation time 99121893 ps
CPU time 2.52 seconds
Started Jun 27 04:48:29 PM PDT 24
Finished Jun 27 04:48:34 PM PDT 24
Peak memory 214352 kb
Host smart-203b4534-a787-4e1d-a866-6aecc0c0006e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141642718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbde
v_csr_mem_rw_with_rand_reset.141642718
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3064123333
Short name T265
Test name
Test status
Simulation time 97230176 ps
CPU time 1 seconds
Started Jun 27 04:48:33 PM PDT 24
Finished Jun 27 04:48:40 PM PDT 24
Peak memory 206148 kb
Host smart-98d0e978-6b9e-4101-8d3b-ebdee5b7472f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3064123333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.3064123333
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.303897891
Short name T2636
Test name
Test status
Simulation time 128472431 ps
CPU time 1.57 seconds
Started Jun 27 04:48:32 PM PDT 24
Finished Jun 27 04:48:39 PM PDT 24
Peak memory 206040 kb
Host smart-fe6e38aa-a943-494a-81e8-57714b9765de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=303897891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.303897891
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3443602045
Short name T2666
Test name
Test status
Simulation time 212502579 ps
CPU time 2.07 seconds
Started Jun 27 04:48:32 PM PDT 24
Finished Jun 27 04:48:40 PM PDT 24
Peak memory 214120 kb
Host smart-660f19ff-07ed-4242-80ee-2337893c6e19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3443602045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3443602045
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1731163680
Short name T308
Test name
Test status
Simulation time 728316254 ps
CPU time 4.7 seconds
Started Jun 27 04:48:30 PM PDT 24
Finished Jun 27 04:48:38 PM PDT 24
Peak memory 206120 kb
Host smart-70ee321c-0b6d-4bbd-b857-cf77052cc619
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1731163680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.1731163680
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2509801712
Short name T2704
Test name
Test status
Simulation time 88829057 ps
CPU time 1.94 seconds
Started Jun 27 04:47:56 PM PDT 24
Finished Jun 27 04:48:01 PM PDT 24
Peak memory 206116 kb
Host smart-384fcab6-55d4-4b47-b8d3-be3cd338b74c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2509801712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.2509801712
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1385667970
Short name T2655
Test name
Test status
Simulation time 1268712876 ps
CPU time 8.67 seconds
Started Jun 27 04:47:57 PM PDT 24
Finished Jun 27 04:48:08 PM PDT 24
Peak memory 206128 kb
Host smart-6328a3d1-9e99-4aae-8c71-2be822b787cf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1385667970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.1385667970
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1046660951
Short name T2687
Test name
Test status
Simulation time 92600238 ps
CPU time 0.85 seconds
Started Jun 27 04:48:10 PM PDT 24
Finished Jun 27 04:48:12 PM PDT 24
Peak memory 206044 kb
Host smart-7d7fdbdf-1fd7-47d3-ae6b-e4cd54f49456
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1046660951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.1046660951
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2108094386
Short name T2637
Test name
Test status
Simulation time 200591639 ps
CPU time 1.96 seconds
Started Jun 27 04:47:56 PM PDT 24
Finished Jun 27 04:48:01 PM PDT 24
Peak memory 214436 kb
Host smart-faac1911-abb8-436f-b384-622079308b70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108094386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.2108094386
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1863601185
Short name T2699
Test name
Test status
Simulation time 36902319 ps
CPU time 0.8 seconds
Started Jun 27 04:48:08 PM PDT 24
Finished Jun 27 04:48:10 PM PDT 24
Peak memory 205916 kb
Host smart-d321a87c-44b6-42a8-a586-717100b92c72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1863601185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.1863601185
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2938179902
Short name T2651
Test name
Test status
Simulation time 56052018 ps
CPU time 0.68 seconds
Started Jun 27 04:47:51 PM PDT 24
Finished Jun 27 04:47:53 PM PDT 24
Peak memory 205992 kb
Host smart-21836603-6af5-4087-9df8-9c0e948676c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2938179902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.2938179902
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1829793022
Short name T2689
Test name
Test status
Simulation time 216025027 ps
CPU time 2.51 seconds
Started Jun 27 04:48:01 PM PDT 24
Finished Jun 27 04:48:05 PM PDT 24
Peak memory 222552 kb
Host smart-44a8ee50-8316-4088-9d01-e057418e1c91
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1829793022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.1829793022
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2805179121
Short name T2631
Test name
Test status
Simulation time 113529548 ps
CPU time 2.38 seconds
Started Jun 27 04:48:09 PM PDT 24
Finished Jun 27 04:48:13 PM PDT 24
Peak memory 205956 kb
Host smart-f04f4af6-6a2f-40ed-9cd6-5e1e0f970caf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2805179121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.2805179121
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3159913356
Short name T2714
Test name
Test status
Simulation time 81631129 ps
CPU time 1.17 seconds
Started Jun 27 04:48:00 PM PDT 24
Finished Jun 27 04:48:03 PM PDT 24
Peak memory 206200 kb
Host smart-36fc3c77-96f1-47a7-8731-a4a8472a8ee8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3159913356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.3159913356
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.4218493643
Short name T2719
Test name
Test status
Simulation time 386847187 ps
CPU time 3.41 seconds
Started Jun 27 04:48:15 PM PDT 24
Finished Jun 27 04:48:19 PM PDT 24
Peak memory 214272 kb
Host smart-a6ddfe9e-d763-4d16-9641-0ffc9dbe7d60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4218493643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.4218493643
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2108299296
Short name T306
Test name
Test status
Simulation time 509700546 ps
CPU time 2.77 seconds
Started Jun 27 04:48:09 PM PDT 24
Finished Jun 27 04:48:13 PM PDT 24
Peak memory 206000 kb
Host smart-fcb96cb5-4f29-494e-94ab-effb142ac93f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2108299296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.2108299296
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1327764261
Short name T2659
Test name
Test status
Simulation time 40260425 ps
CPU time 0.64 seconds
Started Jun 27 04:48:28 PM PDT 24
Finished Jun 27 04:48:31 PM PDT 24
Peak memory 206012 kb
Host smart-62034f56-41b6-4e26-a5c2-11874828a8d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1327764261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.1327764261
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.906871806
Short name T299
Test name
Test status
Simulation time 66266771 ps
CPU time 0.72 seconds
Started Jun 27 04:48:32 PM PDT 24
Finished Jun 27 04:48:39 PM PDT 24
Peak memory 205892 kb
Host smart-b35e77d1-d8db-4495-9aad-e5744d5f3b9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=906871806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.906871806
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1290010104
Short name T2688
Test name
Test status
Simulation time 33709169 ps
CPU time 0.66 seconds
Started Jun 27 04:48:32 PM PDT 24
Finished Jun 27 04:48:39 PM PDT 24
Peak memory 205880 kb
Host smart-974f1f5e-8324-4a08-9293-ca3c35cf6537
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1290010104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.1290010104
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.733219556
Short name T2724
Test name
Test status
Simulation time 36620223 ps
CPU time 0.65 seconds
Started Jun 27 04:48:28 PM PDT 24
Finished Jun 27 04:48:32 PM PDT 24
Peak memory 205976 kb
Host smart-df96bc64-3673-48bc-9f23-0b6b8cf25389
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=733219556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.733219556
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2946589751
Short name T2663
Test name
Test status
Simulation time 37922739 ps
CPU time 0.68 seconds
Started Jun 27 04:48:31 PM PDT 24
Finished Jun 27 04:48:36 PM PDT 24
Peak memory 205896 kb
Host smart-c2c39063-1c32-4fd6-9d01-e4d4ea9ac953
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2946589751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.2946589751
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1265526598
Short name T301
Test name
Test status
Simulation time 35429223 ps
CPU time 0.65 seconds
Started Jun 27 04:48:30 PM PDT 24
Finished Jun 27 04:48:35 PM PDT 24
Peak memory 206008 kb
Host smart-7d79245f-c397-4da2-9df3-2a9080aeb301
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1265526598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.1265526598
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2930618504
Short name T2675
Test name
Test status
Simulation time 52213569 ps
CPU time 0.74 seconds
Started Jun 27 04:48:33 PM PDT 24
Finished Jun 27 04:48:39 PM PDT 24
Peak memory 205968 kb
Host smart-3bdd6f6d-5c39-4288-8535-714ff73b8f40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2930618504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.2930618504
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2515163561
Short name T2712
Test name
Test status
Simulation time 68514999 ps
CPU time 0.69 seconds
Started Jun 27 04:48:27 PM PDT 24
Finished Jun 27 04:48:29 PM PDT 24
Peak memory 205908 kb
Host smart-9d76c502-58d8-40b7-b95f-ec4fbfbc6085
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2515163561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.2515163561
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3199303793
Short name T2667
Test name
Test status
Simulation time 113611826 ps
CPU time 0.8 seconds
Started Jun 27 04:48:29 PM PDT 24
Finished Jun 27 04:48:33 PM PDT 24
Peak memory 205988 kb
Host smart-dc7232b4-121a-4b33-88b4-7f39d2132241
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3199303793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.3199303793
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3437303742
Short name T270
Test name
Test status
Simulation time 81991677 ps
CPU time 1.93 seconds
Started Jun 27 04:48:11 PM PDT 24
Finished Jun 27 04:48:14 PM PDT 24
Peak memory 206060 kb
Host smart-091c17f0-1800-47da-919d-9a12f5cbe113
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3437303742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.3437303742
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1542922406
Short name T2668
Test name
Test status
Simulation time 3186181730 ps
CPU time 12.4 seconds
Started Jun 27 04:47:51 PM PDT 24
Finished Jun 27 04:48:05 PM PDT 24
Peak memory 206112 kb
Host smart-55b6eb33-5198-468e-9725-1b24b7f647bf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1542922406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.1542922406
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2559625658
Short name T2725
Test name
Test status
Simulation time 109518138 ps
CPU time 0.85 seconds
Started Jun 27 04:48:11 PM PDT 24
Finished Jun 27 04:48:13 PM PDT 24
Peak memory 206012 kb
Host smart-7a7e15b7-b191-467b-8aa8-277ed647f7fe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2559625658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.2559625658
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2034306570
Short name T244
Test name
Test status
Simulation time 137287457 ps
CPU time 1.23 seconds
Started Jun 27 04:48:01 PM PDT 24
Finished Jun 27 04:48:04 PM PDT 24
Peak memory 214252 kb
Host smart-ed4b259e-6895-4f51-8652-baad06a2f5d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034306570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.2034306570
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3524653374
Short name T2705
Test name
Test status
Simulation time 55328425 ps
CPU time 0.66 seconds
Started Jun 27 04:47:48 PM PDT 24
Finished Jun 27 04:47:51 PM PDT 24
Peak memory 205948 kb
Host smart-765b9db4-1c2a-4ebc-b802-1f77054ec079
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3524653374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.3524653374
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1254819532
Short name T266
Test name
Test status
Simulation time 147615500 ps
CPU time 2.21 seconds
Started Jun 27 04:47:56 PM PDT 24
Finished Jun 27 04:48:02 PM PDT 24
Peak memory 222456 kb
Host smart-6e008f5b-71d2-4ff6-9b03-18d801c57563
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1254819532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.1254819532
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.404297339
Short name T2634
Test name
Test status
Simulation time 702176378 ps
CPU time 4.69 seconds
Started Jun 27 04:48:12 PM PDT 24
Finished Jun 27 04:48:19 PM PDT 24
Peak memory 206004 kb
Host smart-98dc6cb5-2140-4829-8f0d-1d51c546bf81
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=404297339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.404297339
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1630166984
Short name T276
Test name
Test status
Simulation time 99480789 ps
CPU time 1.03 seconds
Started Jun 27 04:48:10 PM PDT 24
Finished Jun 27 04:48:12 PM PDT 24
Peak memory 206196 kb
Host smart-fa0e9937-a692-4b01-8041-cf3cf7279565
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1630166984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.1630166984
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2431213298
Short name T282
Test name
Test status
Simulation time 815648883 ps
CPU time 4.53 seconds
Started Jun 27 04:48:00 PM PDT 24
Finished Jun 27 04:48:06 PM PDT 24
Peak memory 206196 kb
Host smart-75d40157-3cb9-42b7-b598-068c5a52038a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2431213298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.2431213298
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.452886985
Short name T304
Test name
Test status
Simulation time 41589942 ps
CPU time 0.69 seconds
Started Jun 27 04:48:30 PM PDT 24
Finished Jun 27 04:48:35 PM PDT 24
Peak memory 205856 kb
Host smart-e2cada37-92c4-4ba8-b251-5c830fd66c51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=452886985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.452886985
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.3489055148
Short name T292
Test name
Test status
Simulation time 30178315 ps
CPU time 0.64 seconds
Started Jun 27 04:48:28 PM PDT 24
Finished Jun 27 04:48:31 PM PDT 24
Peak memory 205980 kb
Host smart-d6741f18-7cd8-4935-bd06-6e6504400761
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3489055148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.3489055148
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3180801839
Short name T208
Test name
Test status
Simulation time 45895115 ps
CPU time 0.66 seconds
Started Jun 27 04:48:27 PM PDT 24
Finished Jun 27 04:48:29 PM PDT 24
Peak memory 205908 kb
Host smart-3abbd5a7-c1cd-4280-8872-9c5fdddf1b2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3180801839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.3180801839
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2252255337
Short name T2709
Test name
Test status
Simulation time 37010562 ps
CPU time 0.69 seconds
Started Jun 27 04:48:27 PM PDT 24
Finished Jun 27 04:48:30 PM PDT 24
Peak memory 205988 kb
Host smart-20d6783a-cd91-4625-bcb5-95125e1f5911
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2252255337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.2252255337
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.2772336577
Short name T2664
Test name
Test status
Simulation time 35127901 ps
CPU time 0.66 seconds
Started Jun 27 04:48:28 PM PDT 24
Finished Jun 27 04:48:31 PM PDT 24
Peak memory 205932 kb
Host smart-8a8dfa46-79b7-47a7-9c32-eb3f6900ee48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2772336577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.2772336577
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3153928279
Short name T2673
Test name
Test status
Simulation time 52538957 ps
CPU time 0.72 seconds
Started Jun 27 04:48:30 PM PDT 24
Finished Jun 27 04:48:35 PM PDT 24
Peak memory 205852 kb
Host smart-e1064c5c-2d7a-48f5-8586-1cf9b217c211
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3153928279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.3153928279
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.4084303083
Short name T302
Test name
Test status
Simulation time 86642658 ps
CPU time 0.71 seconds
Started Jun 27 04:48:27 PM PDT 24
Finished Jun 27 04:48:30 PM PDT 24
Peak memory 205904 kb
Host smart-1f2b0ad4-750b-44b0-9a21-f90680771507
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4084303083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.4084303083
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.633497800
Short name T2716
Test name
Test status
Simulation time 48684028 ps
CPU time 0.7 seconds
Started Jun 27 04:48:31 PM PDT 24
Finished Jun 27 04:48:36 PM PDT 24
Peak memory 205888 kb
Host smart-00ae3e39-4193-4ba9-b0b6-b412f98309a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=633497800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.633497800
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3678970545
Short name T2658
Test name
Test status
Simulation time 51284900 ps
CPU time 0.67 seconds
Started Jun 27 04:48:31 PM PDT 24
Finished Jun 27 04:48:36 PM PDT 24
Peak memory 206012 kb
Host smart-2de3435c-268c-4a1c-901b-92b3276f699d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3678970545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.3678970545
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2217138430
Short name T2670
Test name
Test status
Simulation time 58944866 ps
CPU time 0.68 seconds
Started Jun 27 04:48:29 PM PDT 24
Finished Jun 27 04:48:34 PM PDT 24
Peak memory 205832 kb
Host smart-6e128df0-4668-4edf-b01c-e1e84e7b2158
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2217138430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.2217138430
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2437234912
Short name T268
Test name
Test status
Simulation time 120441074 ps
CPU time 3.41 seconds
Started Jun 27 04:48:21 PM PDT 24
Finished Jun 27 04:48:26 PM PDT 24
Peak memory 206096 kb
Host smart-7ddb1a09-1cec-4a08-a680-633818c320a9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2437234912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.2437234912
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3465062832
Short name T2684
Test name
Test status
Simulation time 555486895 ps
CPU time 4.43 seconds
Started Jun 27 04:48:29 PM PDT 24
Finished Jun 27 04:48:37 PM PDT 24
Peak memory 206112 kb
Host smart-dbf7dd7c-6226-4447-b22c-c3fb81c127fe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3465062832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.3465062832
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2808413750
Short name T269
Test name
Test status
Simulation time 57762881 ps
CPU time 0.94 seconds
Started Jun 27 04:48:30 PM PDT 24
Finished Jun 27 04:48:36 PM PDT 24
Peak memory 206028 kb
Host smart-0cb2f94d-8d02-4c14-b267-7031f099e364
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2808413750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.2808413750
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3776926872
Short name T2657
Test name
Test status
Simulation time 173699305 ps
CPU time 1.27 seconds
Started Jun 27 04:48:34 PM PDT 24
Finished Jun 27 04:48:40 PM PDT 24
Peak memory 214384 kb
Host smart-b949c935-a2e7-45cb-9f5c-6f5de94a3fa1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776926872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.3776926872
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3977462861
Short name T2635
Test name
Test status
Simulation time 91774137 ps
CPU time 0.97 seconds
Started Jun 27 04:48:27 PM PDT 24
Finished Jun 27 04:48:29 PM PDT 24
Peak memory 206084 kb
Host smart-af03ee45-6534-4c55-8482-7ed797b4e0f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3977462861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.3977462861
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1748135025
Short name T2685
Test name
Test status
Simulation time 80631924 ps
CPU time 2.2 seconds
Started Jun 27 04:48:28 PM PDT 24
Finished Jun 27 04:48:32 PM PDT 24
Peak memory 215484 kb
Host smart-a07626a6-547a-4fcd-a376-37f80e8b2115
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1748135025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.1748135025
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2180359868
Short name T2656
Test name
Test status
Simulation time 480463497 ps
CPU time 4.34 seconds
Started Jun 27 04:48:32 PM PDT 24
Finished Jun 27 04:48:42 PM PDT 24
Peak memory 206064 kb
Host smart-355df198-92b3-4536-81fd-69e00a68dde7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2180359868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.2180359868
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2940403223
Short name T2638
Test name
Test status
Simulation time 112271476 ps
CPU time 1.49 seconds
Started Jun 27 04:48:29 PM PDT 24
Finished Jun 27 04:48:34 PM PDT 24
Peak memory 205924 kb
Host smart-0874f016-451c-44c9-8746-8b9ec0371414
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2940403223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.2940403223
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2232098389
Short name T241
Test name
Test status
Simulation time 297792665 ps
CPU time 3.09 seconds
Started Jun 27 04:48:09 PM PDT 24
Finished Jun 27 04:48:14 PM PDT 24
Peak memory 221912 kb
Host smart-48e2df6f-b479-4c0c-9e3f-25a9c3fe23a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2232098389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.2232098389
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.1204667469
Short name T294
Test name
Test status
Simulation time 42416029 ps
CPU time 0.64 seconds
Started Jun 27 04:48:31 PM PDT 24
Finished Jun 27 04:48:37 PM PDT 24
Peak memory 205892 kb
Host smart-3803cafd-23c3-4175-8610-7488bec34d34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1204667469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.1204667469
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.48977812
Short name T2707
Test name
Test status
Simulation time 49734278 ps
CPU time 0.7 seconds
Started Jun 27 04:48:31 PM PDT 24
Finished Jun 27 04:48:36 PM PDT 24
Peak memory 205908 kb
Host smart-824147be-948c-4d72-9caf-34e8c991c164
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=48977812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.48977812
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1736820546
Short name T2702
Test name
Test status
Simulation time 41805921 ps
CPU time 0.67 seconds
Started Jun 27 04:48:29 PM PDT 24
Finished Jun 27 04:48:33 PM PDT 24
Peak memory 205840 kb
Host smart-5e6cb0f3-f124-4ce9-a94d-eb0f1c03153d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1736820546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.1736820546
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.696889959
Short name T2692
Test name
Test status
Simulation time 63734339 ps
CPU time 0.71 seconds
Started Jun 27 04:48:50 PM PDT 24
Finished Jun 27 04:48:53 PM PDT 24
Peak memory 205980 kb
Host smart-fd47481d-3db8-4b52-8cea-ab93aad2ffea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=696889959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.696889959
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2848062961
Short name T2696
Test name
Test status
Simulation time 55507987 ps
CPU time 0.68 seconds
Started Jun 27 04:48:46 PM PDT 24
Finished Jun 27 04:48:49 PM PDT 24
Peak memory 205944 kb
Host smart-06ab3628-c0e9-42f7-9153-c9d11d233170
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2848062961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.2848062961
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.1069912406
Short name T2672
Test name
Test status
Simulation time 122719431 ps
CPU time 0.74 seconds
Started Jun 27 04:48:55 PM PDT 24
Finished Jun 27 04:48:59 PM PDT 24
Peak memory 205856 kb
Host smart-3bd76f3f-1d8d-4a45-892a-fcc0ac82a42b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1069912406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.1069912406
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.4082526283
Short name T295
Test name
Test status
Simulation time 52669387 ps
CPU time 0.69 seconds
Started Jun 27 04:48:49 PM PDT 24
Finished Jun 27 04:48:52 PM PDT 24
Peak memory 205980 kb
Host smart-efb4bc3c-e152-4f75-9cbc-10312ca5439b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4082526283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.4082526283
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3480172646
Short name T2650
Test name
Test status
Simulation time 37954939 ps
CPU time 0.67 seconds
Started Jun 27 04:48:47 PM PDT 24
Finished Jun 27 04:48:49 PM PDT 24
Peak memory 205872 kb
Host smart-9392f478-a517-4d4d-9c5e-d1ffea61bd1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3480172646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.3480172646
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2310465403
Short name T291
Test name
Test status
Simulation time 37211023 ps
CPU time 0.7 seconds
Started Jun 27 04:48:54 PM PDT 24
Finished Jun 27 04:48:58 PM PDT 24
Peak memory 205896 kb
Host smart-6f6f5769-7e29-4e36-b7fb-a61520fd6375
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2310465403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.2310465403
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1606328097
Short name T2630
Test name
Test status
Simulation time 82511218 ps
CPU time 1.38 seconds
Started Jun 27 04:48:26 PM PDT 24
Finished Jun 27 04:48:29 PM PDT 24
Peak memory 214372 kb
Host smart-60440388-9037-4a82-8276-46ac29b8a81b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606328097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.1606328097
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.126773694
Short name T274
Test name
Test status
Simulation time 76922562 ps
CPU time 0.97 seconds
Started Jun 27 04:48:31 PM PDT 24
Finished Jun 27 04:48:37 PM PDT 24
Peak memory 206200 kb
Host smart-1802aebb-ef79-4f9b-a854-d3745eb355bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=126773694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.126773694
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.314225190
Short name T2676
Test name
Test status
Simulation time 66222627 ps
CPU time 0.84 seconds
Started Jun 27 04:48:32 PM PDT 24
Finished Jun 27 04:48:38 PM PDT 24
Peak memory 205980 kb
Host smart-16cfdad2-771d-4eef-87fb-0d6b8bea27e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=314225190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.314225190
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1762500315
Short name T202
Test name
Test status
Simulation time 141714812 ps
CPU time 1.58 seconds
Started Jun 27 04:48:31 PM PDT 24
Finished Jun 27 04:48:37 PM PDT 24
Peak memory 206116 kb
Host smart-77405df0-bc57-4fdf-938c-c0e169ddea3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1762500315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.1762500315
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2488571024
Short name T2698
Test name
Test status
Simulation time 129741630 ps
CPU time 1.56 seconds
Started Jun 27 04:48:27 PM PDT 24
Finished Jun 27 04:48:31 PM PDT 24
Peak memory 206176 kb
Host smart-c84bb2c3-d2bc-41ec-9a02-0df4c470d060
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2488571024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.2488571024
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3377304622
Short name T286
Test name
Test status
Simulation time 397095847 ps
CPU time 2.74 seconds
Started Jun 27 04:48:30 PM PDT 24
Finished Jun 27 04:48:38 PM PDT 24
Peak memory 206192 kb
Host smart-7ffd9c15-58ed-42e5-b4b0-6c97a0f33e5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3377304622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.3377304622
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2307925130
Short name T2644
Test name
Test status
Simulation time 231683857 ps
CPU time 2.7 seconds
Started Jun 27 04:48:32 PM PDT 24
Finished Jun 27 04:48:40 PM PDT 24
Peak memory 214344 kb
Host smart-6a48a165-5ca8-4e75-9629-c951d9691dd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307925130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.2307925130
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2839831067
Short name T2669
Test name
Test status
Simulation time 84252919 ps
CPU time 0.97 seconds
Started Jun 27 04:48:27 PM PDT 24
Finished Jun 27 04:48:29 PM PDT 24
Peak memory 206124 kb
Host smart-2f53e896-ebe4-46fd-bd3c-629c36260b30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2839831067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.2839831067
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1208236652
Short name T2717
Test name
Test status
Simulation time 39560656 ps
CPU time 0.71 seconds
Started Jun 27 04:48:32 PM PDT 24
Finished Jun 27 04:48:38 PM PDT 24
Peak memory 206008 kb
Host smart-c068f2f3-c1cd-4921-b4c2-ed493a3bb684
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1208236652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.1208236652
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2928459228
Short name T277
Test name
Test status
Simulation time 61513158 ps
CPU time 1.04 seconds
Started Jun 27 04:48:21 PM PDT 24
Finished Jun 27 04:48:23 PM PDT 24
Peak memory 206044 kb
Host smart-c522e1f7-f552-4703-81a9-84c1133d4d66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2928459228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.2928459228
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2223290340
Short name T2715
Test name
Test status
Simulation time 156658307 ps
CPU time 1.94 seconds
Started Jun 27 04:48:26 PM PDT 24
Finished Jun 27 04:48:29 PM PDT 24
Peak memory 206184 kb
Host smart-6cb2a217-064a-4d41-b7bf-cbedefbaf652
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2223290340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.2223290340
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3695610584
Short name T2722
Test name
Test status
Simulation time 525038418 ps
CPU time 4.03 seconds
Started Jun 27 04:48:35 PM PDT 24
Finished Jun 27 04:48:44 PM PDT 24
Peak memory 206176 kb
Host smart-30c7f484-1124-4c59-b620-091b2b43fd22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3695610584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.3695610584
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.257949712
Short name T2711
Test name
Test status
Simulation time 113683758 ps
CPU time 1.33 seconds
Started Jun 27 04:48:28 PM PDT 24
Finished Jun 27 04:48:31 PM PDT 24
Peak memory 214436 kb
Host smart-f01102e4-dc8c-403b-916c-621f4e656cf0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257949712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev
_csr_mem_rw_with_rand_reset.257949712
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3290951822
Short name T271
Test name
Test status
Simulation time 101334927 ps
CPU time 1.15 seconds
Started Jun 27 04:48:29 PM PDT 24
Finished Jun 27 04:48:33 PM PDT 24
Peak memory 205944 kb
Host smart-024205fc-b36a-4f81-ab83-c74c51d8c4d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3290951822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.3290951822
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2899523316
Short name T209
Test name
Test status
Simulation time 49449355 ps
CPU time 0.75 seconds
Started Jun 27 04:48:19 PM PDT 24
Finished Jun 27 04:48:21 PM PDT 24
Peak memory 205904 kb
Host smart-4cd0c163-ac7b-4bab-8ed2-8925103e6263
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2899523316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.2899523316
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1644340852
Short name T2720
Test name
Test status
Simulation time 62318180 ps
CPU time 1.07 seconds
Started Jun 27 04:48:35 PM PDT 24
Finished Jun 27 04:48:41 PM PDT 24
Peak memory 206128 kb
Host smart-04cce52e-bb63-4c6b-a456-e43db120f9c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1644340852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.1644340852
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3476929460
Short name T2706
Test name
Test status
Simulation time 64927331 ps
CPU time 1.47 seconds
Started Jun 27 04:48:32 PM PDT 24
Finished Jun 27 04:48:39 PM PDT 24
Peak memory 206196 kb
Host smart-5593b637-3b72-4763-90e8-5524379a7c79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3476929460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.3476929460
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.437011093
Short name T224
Test name
Test status
Simulation time 2211509513 ps
CPU time 6.04 seconds
Started Jun 27 04:48:30 PM PDT 24
Finished Jun 27 04:48:40 PM PDT 24
Peak memory 205096 kb
Host smart-481b2774-8522-4e63-94fb-89b66ac9bc8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=437011093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.437011093
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3723106883
Short name T232
Test name
Test status
Simulation time 193076081 ps
CPU time 1.9 seconds
Started Jun 27 04:48:35 PM PDT 24
Finished Jun 27 04:48:42 PM PDT 24
Peak memory 214384 kb
Host smart-f9109ba4-8c0c-4aab-b4c3-e88cd709b2dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723106883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.3723106883
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2433042322
Short name T2646
Test name
Test status
Simulation time 87812932 ps
CPU time 0.82 seconds
Started Jun 27 04:48:23 PM PDT 24
Finished Jun 27 04:48:25 PM PDT 24
Peak memory 206032 kb
Host smart-018d4a37-298e-4506-b41a-cca3ae842661
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2433042322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2433042322
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1609231317
Short name T2653
Test name
Test status
Simulation time 38779333 ps
CPU time 0.71 seconds
Started Jun 27 04:48:30 PM PDT 24
Finished Jun 27 04:48:35 PM PDT 24
Peak memory 206012 kb
Host smart-33e377a9-780f-4cbb-b64a-a7b3563833c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1609231317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.1609231317
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3560334632
Short name T2681
Test name
Test status
Simulation time 116973152 ps
CPU time 1.11 seconds
Started Jun 27 04:48:22 PM PDT 24
Finished Jun 27 04:48:24 PM PDT 24
Peak memory 206196 kb
Host smart-2fd0db50-6f31-4500-b78f-62ec8c1705f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3560334632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.3560334632
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.859667590
Short name T240
Test name
Test status
Simulation time 60991998 ps
CPU time 1.44 seconds
Started Jun 27 04:48:32 PM PDT 24
Finished Jun 27 04:48:39 PM PDT 24
Peak memory 206236 kb
Host smart-066bec4c-94b8-40c9-9129-49826fe12e5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=859667590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.859667590
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1195239188
Short name T288
Test name
Test status
Simulation time 446847909 ps
CPU time 3.18 seconds
Started Jun 27 04:48:20 PM PDT 24
Finished Jun 27 04:48:25 PM PDT 24
Peak memory 206364 kb
Host smart-8a46a0dd-ae99-42bd-98c4-aec940d240ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1195239188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.1195239188
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2777551922
Short name T233
Test name
Test status
Simulation time 173850137 ps
CPU time 1.73 seconds
Started Jun 27 04:48:20 PM PDT 24
Finished Jun 27 04:48:24 PM PDT 24
Peak memory 214420 kb
Host smart-4c22e7cd-398a-4171-9f1a-ddc8dfd9d967
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777551922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.2777551922
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2697193292
Short name T261
Test name
Test status
Simulation time 61939049 ps
CPU time 0.83 seconds
Started Jun 27 04:48:30 PM PDT 24
Finished Jun 27 04:48:34 PM PDT 24
Peak memory 205780 kb
Host smart-1978abd7-328d-48d0-b840-391156728ad3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2697193292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.2697193292
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.408432380
Short name T207
Test name
Test status
Simulation time 50026367 ps
CPU time 0.66 seconds
Started Jun 27 04:48:28 PM PDT 24
Finished Jun 27 04:48:32 PM PDT 24
Peak memory 206004 kb
Host smart-02452966-0c75-45fa-9587-ef8c71b48f87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=408432380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.408432380
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3528688814
Short name T2723
Test name
Test status
Simulation time 136875661 ps
CPU time 1.56 seconds
Started Jun 27 04:48:28 PM PDT 24
Finished Jun 27 04:48:33 PM PDT 24
Peak memory 206040 kb
Host smart-0e66a060-29ab-44a0-9b8c-8cef27968d24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3528688814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.3528688814
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.1703254812
Short name T239
Test name
Test status
Simulation time 366597048 ps
CPU time 3.53 seconds
Started Jun 27 04:48:21 PM PDT 24
Finished Jun 27 04:48:26 PM PDT 24
Peak memory 221864 kb
Host smart-76760d36-3c41-4a46-96ee-90210a35419f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1703254812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.1703254812
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1079789352
Short name T280
Test name
Test status
Simulation time 725061956 ps
CPU time 2.92 seconds
Started Jun 27 04:48:31 PM PDT 24
Finished Jun 27 04:48:40 PM PDT 24
Peak memory 206192 kb
Host smart-56f95681-adce-4100-96ae-5ea3dbc3d9ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1079789352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.1079789352
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.1145514348
Short name T961
Test name
Test status
Simulation time 49899719 ps
CPU time 0.68 seconds
Started Jun 27 06:34:45 PM PDT 24
Finished Jun 27 06:34:57 PM PDT 24
Peak memory 206368 kb
Host smart-4fb92b72-bc9e-4fae-9a7c-416a550eee15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1145514348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.1145514348
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.2043523992
Short name T1423
Test name
Test status
Simulation time 3427273021 ps
CPU time 3.75 seconds
Started Jun 27 06:34:18 PM PDT 24
Finished Jun 27 06:34:24 PM PDT 24
Peak memory 206436 kb
Host smart-01508dee-5efe-4e5c-aa94-1c0eed7a7bf2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2043523992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.2043523992
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.4132170976
Short name T1126
Test name
Test status
Simulation time 13406693849 ps
CPU time 13 seconds
Started Jun 27 06:34:20 PM PDT 24
Finished Jun 27 06:34:37 PM PDT 24
Peak memory 206420 kb
Host smart-04a15858-02cd-47b0-953f-7b251d66f089
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4132170976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.4132170976
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.3627651338
Short name T2600
Test name
Test status
Simulation time 23352326556 ps
CPU time 22.44 seconds
Started Jun 27 06:34:21 PM PDT 24
Finished Jun 27 06:34:49 PM PDT 24
Peak memory 206344 kb
Host smart-57d80022-9da4-481d-9ed8-5f2dbfac8214
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3627651338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.3627651338
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.502664596
Short name T2323
Test name
Test status
Simulation time 150833722 ps
CPU time 0.82 seconds
Started Jun 27 06:34:23 PM PDT 24
Finished Jun 27 06:34:31 PM PDT 24
Peak memory 206284 kb
Host smart-d038ee29-517e-443e-a977-dc0b0e3f45cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50266
4596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.502664596
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.3187165912
Short name T1625
Test name
Test status
Simulation time 145051303 ps
CPU time 0.76 seconds
Started Jun 27 06:34:23 PM PDT 24
Finished Jun 27 06:34:31 PM PDT 24
Peak memory 206276 kb
Host smart-5b42ce7e-fae0-4c00-bf89-d837473ea07a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31871
65912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.3187165912
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.4120017454
Short name T2260
Test name
Test status
Simulation time 502741666 ps
CPU time 1.42 seconds
Started Jun 27 06:34:17 PM PDT 24
Finished Jun 27 06:34:20 PM PDT 24
Peak memory 206256 kb
Host smart-8ef4c7ac-1cf7-4a7a-93d0-87e16bbfd514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41200
17454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.4120017454
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.673857377
Short name T103
Test name
Test status
Simulation time 493291666 ps
CPU time 1.29 seconds
Started Jun 27 06:34:21 PM PDT 24
Finished Jun 27 06:34:27 PM PDT 24
Peak memory 206264 kb
Host smart-4df4be92-9503-4b5c-b51c-9f9386222bb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67385
7377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.673857377
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.2830305632
Short name T1543
Test name
Test status
Simulation time 19007559952 ps
CPU time 38.32 seconds
Started Jun 27 06:34:24 PM PDT 24
Finished Jun 27 06:35:11 PM PDT 24
Peak memory 206476 kb
Host smart-0c926b76-fa94-40e6-bde5-978873aa040d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28303
05632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.2830305632
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.3323397422
Short name T1842
Test name
Test status
Simulation time 336793843 ps
CPU time 1.15 seconds
Started Jun 27 06:34:21 PM PDT 24
Finished Jun 27 06:34:27 PM PDT 24
Peak memory 206280 kb
Host smart-f912c213-3c5a-4aa6-b634-be088fee16bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33233
97422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.3323397422
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.3209812221
Short name T1505
Test name
Test status
Simulation time 134187391 ps
CPU time 0.79 seconds
Started Jun 27 06:34:21 PM PDT 24
Finished Jun 27 06:34:28 PM PDT 24
Peak memory 206276 kb
Host smart-5f8b1527-1702-4c8b-bf2f-e5b6616cc994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32098
12221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.3209812221
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.942209146
Short name T2299
Test name
Test status
Simulation time 5153022898 ps
CPU time 132.88 seconds
Started Jun 27 06:34:20 PM PDT 24
Finished Jun 27 06:36:37 PM PDT 24
Peak memory 206396 kb
Host smart-82706586-fb3a-4b58-8427-d4959dd69a87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94220
9146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.942209146
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_enable.728700953
Short name T2161
Test name
Test status
Simulation time 36977226 ps
CPU time 0.67 seconds
Started Jun 27 06:34:19 PM PDT 24
Finished Jun 27 06:34:22 PM PDT 24
Peak memory 206292 kb
Host smart-16bb52ed-4201-42f9-b333-f5b8283ebb82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72870
0953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.728700953
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.3645215647
Short name T2467
Test name
Test status
Simulation time 873248639 ps
CPU time 2.1 seconds
Started Jun 27 06:34:20 PM PDT 24
Finished Jun 27 06:34:26 PM PDT 24
Peak memory 206412 kb
Host smart-7769d29c-cacb-41da-80e5-fa4f3ad3f6a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36452
15647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.3645215647
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.3717401733
Short name T1171
Test name
Test status
Simulation time 300943766 ps
CPU time 1.82 seconds
Started Jun 27 06:34:21 PM PDT 24
Finished Jun 27 06:34:29 PM PDT 24
Peak memory 206336 kb
Host smart-c299df0e-6952-45da-b6c8-fb532750a937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37174
01733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.3717401733
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.3094801860
Short name T574
Test name
Test status
Simulation time 238083235 ps
CPU time 0.87 seconds
Started Jun 27 06:34:20 PM PDT 24
Finished Jun 27 06:34:25 PM PDT 24
Peak memory 206288 kb
Host smart-897ca7f1-a51c-4e95-b604-a795f21c715e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30948
01860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.3094801860
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.2536731476
Short name T1468
Test name
Test status
Simulation time 171354163 ps
CPU time 0.79 seconds
Started Jun 27 06:34:21 PM PDT 24
Finished Jun 27 06:34:28 PM PDT 24
Peak memory 206304 kb
Host smart-ed0ecf4d-1256-4e89-a842-7a3713b3ddde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25367
31476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.2536731476
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.1760465530
Short name T909
Test name
Test status
Simulation time 184566447 ps
CPU time 0.89 seconds
Started Jun 27 06:34:24 PM PDT 24
Finished Jun 27 06:34:34 PM PDT 24
Peak memory 206164 kb
Host smart-29e4bd38-3490-46cc-bb65-194f3f083b40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17604
65530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.1760465530
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.1438765204
Short name T2025
Test name
Test status
Simulation time 198058900 ps
CPU time 0.86 seconds
Started Jun 27 06:34:23 PM PDT 24
Finished Jun 27 06:34:32 PM PDT 24
Peak memory 206272 kb
Host smart-da7b5477-8299-41dc-a221-b7d7b87fa3eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14387
65204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.1438765204
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.852113569
Short name T71
Test name
Test status
Simulation time 536633032 ps
CPU time 1.42 seconds
Started Jun 27 06:34:22 PM PDT 24
Finished Jun 27 06:34:30 PM PDT 24
Peak memory 206296 kb
Host smart-126c7a89-cf89-4685-bf4a-300e20efc01e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85211
3569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.852113569
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.1550217346
Short name T606
Test name
Test status
Simulation time 23268223329 ps
CPU time 22.87 seconds
Started Jun 27 06:34:19 PM PDT 24
Finished Jun 27 06:34:44 PM PDT 24
Peak memory 206340 kb
Host smart-2a3cacd5-0910-45e3-ad95-0cc795dbd8a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15502
17346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.1550217346
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.4062024860
Short name T2307
Test name
Test status
Simulation time 3350984837 ps
CPU time 3.93 seconds
Started Jun 27 06:34:18 PM PDT 24
Finished Jun 27 06:34:24 PM PDT 24
Peak memory 206336 kb
Host smart-ad5ed1dd-96ef-499b-80f5-194aee06a340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40620
24860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.4062024860
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.2834875954
Short name T1883
Test name
Test status
Simulation time 8145104525 ps
CPU time 56.3 seconds
Started Jun 27 06:34:21 PM PDT 24
Finished Jun 27 06:35:22 PM PDT 24
Peak memory 206392 kb
Host smart-76074f37-56a6-4aa7-a3d8-5df25bfd80bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28348
75954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.2834875954
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.1662557474
Short name T1344
Test name
Test status
Simulation time 7332950286 ps
CPU time 51.23 seconds
Started Jun 27 06:34:20 PM PDT 24
Finished Jun 27 06:35:15 PM PDT 24
Peak memory 206492 kb
Host smart-32aaaf86-cd86-4292-a788-3d697cbbaccf
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1662557474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.1662557474
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.2417366044
Short name T2404
Test name
Test status
Simulation time 247248302 ps
CPU time 0.92 seconds
Started Jun 27 06:34:22 PM PDT 24
Finished Jun 27 06:34:30 PM PDT 24
Peak memory 206272 kb
Host smart-ac0edbbd-f05c-44eb-9504-a8fff40acb3e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2417366044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.2417366044
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.1540248122
Short name T464
Test name
Test status
Simulation time 200090799 ps
CPU time 0.84 seconds
Started Jun 27 06:34:20 PM PDT 24
Finished Jun 27 06:34:26 PM PDT 24
Peak memory 206276 kb
Host smart-de111186-d5e1-4aaf-97ad-5a345986b731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15402
48122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.1540248122
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.878579235
Short name T350
Test name
Test status
Simulation time 3514106382 ps
CPU time 32.64 seconds
Started Jun 27 06:34:21 PM PDT 24
Finished Jun 27 06:34:59 PM PDT 24
Peak memory 206340 kb
Host smart-5651b276-4a27-4de8-bccd-c678d9d8ca2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87857
9235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.878579235
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.3774518886
Short name T1371
Test name
Test status
Simulation time 5326034643 ps
CPU time 49.69 seconds
Started Jun 27 06:34:20 PM PDT 24
Finished Jun 27 06:35:12 PM PDT 24
Peak memory 206432 kb
Host smart-8619fe93-76a2-4908-8ccc-8b1fb0119404
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3774518886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.3774518886
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.1428490226
Short name T878
Test name
Test status
Simulation time 147241294 ps
CPU time 0.81 seconds
Started Jun 27 06:34:21 PM PDT 24
Finished Jun 27 06:34:27 PM PDT 24
Peak memory 206292 kb
Host smart-5a7ccb90-7759-49fa-a17c-ce1139961ec1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1428490226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.1428490226
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.3125456279
Short name T2130
Test name
Test status
Simulation time 174919972 ps
CPU time 0.79 seconds
Started Jun 27 06:34:21 PM PDT 24
Finished Jun 27 06:34:26 PM PDT 24
Peak memory 206212 kb
Host smart-350a8cb8-afe2-4234-a93d-f7f8e695dbb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31254
56279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.3125456279
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.3490827743
Short name T70
Test name
Test status
Simulation time 542740702 ps
CPU time 1.45 seconds
Started Jun 27 06:34:21 PM PDT 24
Finished Jun 27 06:34:27 PM PDT 24
Peak memory 206292 kb
Host smart-88e1d74f-0f70-42dc-8db7-0565610e5e7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34908
27743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.3490827743
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.672708392
Short name T1415
Test name
Test status
Simulation time 168857993 ps
CPU time 0.82 seconds
Started Jun 27 06:34:22 PM PDT 24
Finished Jun 27 06:34:30 PM PDT 24
Peak memory 206288 kb
Host smart-eb90b6c7-ee8b-41f2-a887-cb393b26e3f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67270
8392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.672708392
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.100732058
Short name T416
Test name
Test status
Simulation time 153407324 ps
CPU time 0.78 seconds
Started Jun 27 06:34:18 PM PDT 24
Finished Jun 27 06:34:20 PM PDT 24
Peak memory 206436 kb
Host smart-c534665a-cea6-42fe-80fd-62846ba3d4e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10073
2058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.100732058
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.2397825373
Short name T1955
Test name
Test status
Simulation time 165232952 ps
CPU time 0.84 seconds
Started Jun 27 06:34:21 PM PDT 24
Finished Jun 27 06:34:28 PM PDT 24
Peak memory 206280 kb
Host smart-de5e7644-26af-49aa-9f91-38892a8ea108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23978
25373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.2397825373
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.3336590982
Short name T179
Test name
Test status
Simulation time 171581511 ps
CPU time 0.79 seconds
Started Jun 27 06:34:22 PM PDT 24
Finished Jun 27 06:34:29 PM PDT 24
Peak memory 206300 kb
Host smart-c66791e5-81bd-4dc1-ac00-3da8659b33c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33365
90982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.3336590982
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.205752025
Short name T1984
Test name
Test status
Simulation time 168387644 ps
CPU time 0.83 seconds
Started Jun 27 06:34:21 PM PDT 24
Finished Jun 27 06:34:29 PM PDT 24
Peak memory 206264 kb
Host smart-4eb0fff8-7da0-4c46-a971-a7e03e041bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20575
2025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.205752025
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.1184313479
Short name T1514
Test name
Test status
Simulation time 219493084 ps
CPU time 0.86 seconds
Started Jun 27 06:34:23 PM PDT 24
Finished Jun 27 06:34:32 PM PDT 24
Peak memory 206292 kb
Host smart-562120ee-493e-4481-90cd-440ab28ed493
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1184313479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.1184313479
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.1646985668
Short name T204
Test name
Test status
Simulation time 213936306 ps
CPU time 0.91 seconds
Started Jun 27 06:34:22 PM PDT 24
Finished Jun 27 06:34:31 PM PDT 24
Peak memory 206280 kb
Host smart-2dfe5623-f2c7-4ed6-9e5a-9bd68db4c85f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16469
85668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.1646985668
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.3840086332
Short name T1949
Test name
Test status
Simulation time 233177736 ps
CPU time 0.97 seconds
Started Jun 27 06:34:22 PM PDT 24
Finished Jun 27 06:34:31 PM PDT 24
Peak memory 206276 kb
Host smart-5ed2330b-1719-4eca-a78c-0652532bd2a2
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3840086332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.3840086332
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.1397666750
Short name T205
Test name
Test status
Simulation time 243778788 ps
CPU time 0.96 seconds
Started Jun 27 06:34:23 PM PDT 24
Finished Jun 27 06:34:32 PM PDT 24
Peak memory 206296 kb
Host smart-2349d9be-3c9c-40cd-b06e-93af27767022
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1397666750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.1397666750
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.880575878
Short name T2378
Test name
Test status
Simulation time 145636740 ps
CPU time 0.77 seconds
Started Jun 27 06:34:23 PM PDT 24
Finished Jun 27 06:34:32 PM PDT 24
Peak memory 206244 kb
Host smart-162db615-3dae-4323-aefb-c54c094ced44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88057
5878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.880575878
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.246206964
Short name T2439
Test name
Test status
Simulation time 48638509 ps
CPU time 0.66 seconds
Started Jun 27 06:34:22 PM PDT 24
Finished Jun 27 06:34:30 PM PDT 24
Peak memory 206272 kb
Host smart-772c5689-7e42-48b2-be73-c3880fc49aa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24620
6964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.246206964
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.1555439924
Short name T1108
Test name
Test status
Simulation time 16779394403 ps
CPU time 34.44 seconds
Started Jun 27 06:34:22 PM PDT 24
Finished Jun 27 06:35:03 PM PDT 24
Peak memory 206420 kb
Host smart-03152354-6a94-43f2-9c32-fc3267ac7d1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15554
39924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.1555439924
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.2654090941
Short name T1267
Test name
Test status
Simulation time 240060057 ps
CPU time 0.91 seconds
Started Jun 27 06:34:23 PM PDT 24
Finished Jun 27 06:34:33 PM PDT 24
Peak memory 206228 kb
Host smart-703065b9-c305-4180-a44c-d435be815714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26540
90941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.2654090941
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.3186108795
Short name T2143
Test name
Test status
Simulation time 240667164 ps
CPU time 0.88 seconds
Started Jun 27 06:34:24 PM PDT 24
Finished Jun 27 06:34:33 PM PDT 24
Peak memory 206248 kb
Host smart-af658334-e85c-4a84-ba1c-8cf07d4f057d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31861
08795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.3186108795
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.1908204786
Short name T1158
Test name
Test status
Simulation time 17507405698 ps
CPU time 464.78 seconds
Started Jun 27 06:34:24 PM PDT 24
Finished Jun 27 06:42:17 PM PDT 24
Peak memory 206356 kb
Host smart-df9bd96a-bb3e-447f-ac92-91489239fa20
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1908204786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.1908204786
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.4266827456
Short name T631
Test name
Test status
Simulation time 7800203963 ps
CPU time 46.04 seconds
Started Jun 27 06:34:23 PM PDT 24
Finished Jun 27 06:35:17 PM PDT 24
Peak memory 206444 kb
Host smart-e1bde384-0d4f-4839-b8e2-f5322cce3d87
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4266827456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.4266827456
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.701273702
Short name T1650
Test name
Test status
Simulation time 185490107 ps
CPU time 0.81 seconds
Started Jun 27 06:34:24 PM PDT 24
Finished Jun 27 06:34:33 PM PDT 24
Peak memory 206244 kb
Host smart-c5dde301-8f69-492a-a1b3-5805e26a50d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70127
3702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.701273702
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.3361455201
Short name T251
Test name
Test status
Simulation time 174005942 ps
CPU time 0.79 seconds
Started Jun 27 06:34:21 PM PDT 24
Finished Jun 27 06:34:28 PM PDT 24
Peak memory 206272 kb
Host smart-7d1f4b9f-ab41-47ad-ba89-19ef3cbd0292
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33614
55201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.3361455201
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.2457886875
Short name T1764
Test name
Test status
Simulation time 140295254 ps
CPU time 0.74 seconds
Started Jun 27 06:34:23 PM PDT 24
Finished Jun 27 06:34:32 PM PDT 24
Peak memory 206248 kb
Host smart-9b996f93-5e93-45ab-9f0c-4f93b3dd37d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24578
86875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.2457886875
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.2700263549
Short name T211
Test name
Test status
Simulation time 366482812 ps
CPU time 1.12 seconds
Started Jun 27 06:34:34 PM PDT 24
Finished Jun 27 06:34:38 PM PDT 24
Peak memory 224056 kb
Host smart-fb74f99a-d6dd-42a5-ad9e-d98c8cd3290e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2700263549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.2700263549
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.2890163113
Short name T1345
Test name
Test status
Simulation time 149006820 ps
CPU time 0.8 seconds
Started Jun 27 06:34:24 PM PDT 24
Finished Jun 27 06:34:33 PM PDT 24
Peak memory 206256 kb
Host smart-f15868b1-5dd4-4c43-be11-fc8b27a11d95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28901
63113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.2890163113
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.1153305545
Short name T2282
Test name
Test status
Simulation time 149320706 ps
CPU time 0.79 seconds
Started Jun 27 06:34:25 PM PDT 24
Finished Jun 27 06:34:34 PM PDT 24
Peak memory 206280 kb
Host smart-e6783617-f51d-4790-a1c8-d1fb48965283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11533
05545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.1153305545
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.579051211
Short name T1469
Test name
Test status
Simulation time 271767685 ps
CPU time 0.98 seconds
Started Jun 27 06:34:24 PM PDT 24
Finished Jun 27 06:34:33 PM PDT 24
Peak memory 206252 kb
Host smart-7db6ce3a-146b-465b-bd9f-daf4df739c22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57905
1211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.579051211
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.3943768100
Short name T541
Test name
Test status
Simulation time 7120957870 ps
CPU time 196.62 seconds
Started Jun 27 06:34:22 PM PDT 24
Finished Jun 27 06:37:46 PM PDT 24
Peak memory 206444 kb
Host smart-b3e34c8c-764f-4a4b-be60-aa7ddc048c69
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3943768100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.3943768100
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.2058584362
Short name T1957
Test name
Test status
Simulation time 220752536 ps
CPU time 0.85 seconds
Started Jun 27 06:34:21 PM PDT 24
Finished Jun 27 06:34:26 PM PDT 24
Peak memory 206284 kb
Host smart-4f130d22-6d01-413f-b945-fabafc4b0a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20585
84362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.2058584362
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.2966192462
Short name T1554
Test name
Test status
Simulation time 151417638 ps
CPU time 0.77 seconds
Started Jun 27 06:34:24 PM PDT 24
Finished Jun 27 06:34:34 PM PDT 24
Peak memory 206236 kb
Host smart-4c0ac335-e778-456b-ad87-edc4a6e99259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29661
92462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.2966192462
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.3394979462
Short name T1054
Test name
Test status
Simulation time 4572311759 ps
CPU time 34.14 seconds
Started Jun 27 06:34:21 PM PDT 24
Finished Jun 27 06:35:01 PM PDT 24
Peak memory 206424 kb
Host smart-b3f766a6-a1bb-42f3-a5f3-9c09701054bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33949
79462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.3394979462
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.2223178233
Short name T1426
Test name
Test status
Simulation time 40194027 ps
CPU time 0.68 seconds
Started Jun 27 06:34:40 PM PDT 24
Finished Jun 27 06:34:46 PM PDT 24
Peak memory 206352 kb
Host smart-007920f8-3ce8-4aaf-99f2-a61e177e29c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2223178233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.2223178233
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.168580139
Short name T736
Test name
Test status
Simulation time 4035784840 ps
CPU time 4.46 seconds
Started Jun 27 06:34:40 PM PDT 24
Finished Jun 27 06:34:49 PM PDT 24
Peak memory 206408 kb
Host smart-0665d36b-5fe5-4b7a-bc23-3112d27032ef
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=168580139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.168580139
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.2692795888
Short name T1809
Test name
Test status
Simulation time 13380994802 ps
CPU time 13.33 seconds
Started Jun 27 06:34:36 PM PDT 24
Finished Jun 27 06:34:52 PM PDT 24
Peak memory 206336 kb
Host smart-222c4845-e613-4b3a-9530-c6d753e683e1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2692795888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.2692795888
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.286133190
Short name T1508
Test name
Test status
Simulation time 23318427254 ps
CPU time 21.13 seconds
Started Jun 27 06:34:38 PM PDT 24
Finished Jun 27 06:35:03 PM PDT 24
Peak memory 206420 kb
Host smart-3db18301-5785-4a36-a9a7-72a921b42834
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=286133190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.286133190
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.4186632908
Short name T946
Test name
Test status
Simulation time 200903968 ps
CPU time 0.84 seconds
Started Jun 27 06:34:36 PM PDT 24
Finished Jun 27 06:34:39 PM PDT 24
Peak memory 206272 kb
Host smart-abd89e5c-3c1a-46e2-bf19-a0afc7cef065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41866
32908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.4186632908
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.1228114968
Short name T59
Test name
Test status
Simulation time 155558610 ps
CPU time 0.84 seconds
Started Jun 27 06:34:37 PM PDT 24
Finished Jun 27 06:34:40 PM PDT 24
Peak memory 206292 kb
Host smart-c0b969b2-e066-4d99-a8e1-d1953394066f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12281
14968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.1228114968
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.4102322698
Short name T65
Test name
Test status
Simulation time 133978955 ps
CPU time 0.76 seconds
Started Jun 27 06:34:36 PM PDT 24
Finished Jun 27 06:34:39 PM PDT 24
Peak memory 206276 kb
Host smart-0ce883e6-51fe-490d-b2aa-202faaf7c95a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41023
22698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.4102322698
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.1648114168
Short name T2151
Test name
Test status
Simulation time 158542013 ps
CPU time 0.75 seconds
Started Jun 27 06:34:40 PM PDT 24
Finished Jun 27 06:34:47 PM PDT 24
Peak memory 206272 kb
Host smart-f6571301-5d63-447b-af8f-07ab15bd5818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16481
14168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.1648114168
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.4280204156
Short name T158
Test name
Test status
Simulation time 574737471 ps
CPU time 1.62 seconds
Started Jun 27 06:34:43 PM PDT 24
Finished Jun 27 06:34:54 PM PDT 24
Peak memory 206348 kb
Host smart-4e7f8718-ceb6-4ca0-ae12-a3921303baa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42802
04156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.4280204156
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.4057756268
Short name T186
Test name
Test status
Simulation time 819977380 ps
CPU time 1.84 seconds
Started Jun 27 06:34:37 PM PDT 24
Finished Jun 27 06:34:41 PM PDT 24
Peak memory 206444 kb
Host smart-5483e318-eae8-4cfd-9172-2bf4410eb5c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40577
56268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.4057756268
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.2714104526
Short name T2338
Test name
Test status
Simulation time 15224407192 ps
CPU time 28.34 seconds
Started Jun 27 06:34:46 PM PDT 24
Finished Jun 27 06:35:25 PM PDT 24
Peak memory 206396 kb
Host smart-458903ae-ee76-4c03-905c-d0415e11a7fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27141
04526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.2714104526
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.2124736971
Short name T1339
Test name
Test status
Simulation time 433732510 ps
CPU time 1.39 seconds
Started Jun 27 06:34:43 PM PDT 24
Finished Jun 27 06:34:54 PM PDT 24
Peak memory 206292 kb
Host smart-bc52630e-c6a4-4fe3-9061-050d9284f2b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21247
36971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.2124736971
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.1473826447
Short name T2215
Test name
Test status
Simulation time 140254015 ps
CPU time 0.74 seconds
Started Jun 27 06:34:43 PM PDT 24
Finished Jun 27 06:34:53 PM PDT 24
Peak memory 206272 kb
Host smart-04b1cf41-d00c-448a-967f-97064c2ce18d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14738
26447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.1473826447
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.3767478243
Short name T1553
Test name
Test status
Simulation time 52407203 ps
CPU time 0.66 seconds
Started Jun 27 06:34:37 PM PDT 24
Finished Jun 27 06:34:40 PM PDT 24
Peak memory 206280 kb
Host smart-5da7e2fa-be22-4331-bb2b-3eb813f48d57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37674
78243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.3767478243
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.2061682917
Short name T2512
Test name
Test status
Simulation time 944259829 ps
CPU time 2.21 seconds
Started Jun 27 06:34:45 PM PDT 24
Finished Jun 27 06:34:58 PM PDT 24
Peak memory 206444 kb
Host smart-c43054f8-1606-4ef0-8032-1f666bb108a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20616
82917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.2061682917
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.3604596856
Short name T2280
Test name
Test status
Simulation time 169284053 ps
CPU time 0.82 seconds
Started Jun 27 06:34:41 PM PDT 24
Finished Jun 27 06:34:49 PM PDT 24
Peak memory 206456 kb
Host smart-8f1df943-578b-4f17-bcdd-48949fe61725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36045
96856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.3604596856
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.2329571360
Short name T1271
Test name
Test status
Simulation time 173461928 ps
CPU time 0.74 seconds
Started Jun 27 06:34:37 PM PDT 24
Finished Jun 27 06:34:40 PM PDT 24
Peak memory 206252 kb
Host smart-144287cc-ea6b-45cd-8dda-c870b6e8e3b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23295
71360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.2329571360
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.533026521
Short name T2433
Test name
Test status
Simulation time 227537456 ps
CPU time 0.93 seconds
Started Jun 27 06:34:43 PM PDT 24
Finished Jun 27 06:34:54 PM PDT 24
Peak memory 206288 kb
Host smart-91361218-3445-4af0-b5f1-f372947c85ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53302
6521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.533026521
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.2819838902
Short name T1407
Test name
Test status
Simulation time 7894873039 ps
CPU time 51.58 seconds
Started Jun 27 06:34:41 PM PDT 24
Finished Jun 27 06:35:42 PM PDT 24
Peak memory 206452 kb
Host smart-bc3aed8b-2251-44e4-adff-a5f39304908b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2819838902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.2819838902
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.3161779228
Short name T989
Test name
Test status
Simulation time 169019995 ps
CPU time 0.85 seconds
Started Jun 27 06:34:41 PM PDT 24
Finished Jun 27 06:34:51 PM PDT 24
Peak memory 206276 kb
Host smart-2cd00efd-7ad5-4253-9757-4d750e9af787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31617
79228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.3161779228
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.1364659698
Short name T663
Test name
Test status
Simulation time 23267463627 ps
CPU time 20.99 seconds
Started Jun 27 06:34:38 PM PDT 24
Finished Jun 27 06:35:03 PM PDT 24
Peak memory 206336 kb
Host smart-2945202f-7c89-42d1-9ba7-20aac6baff3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13646
59698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.1364659698
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.2026831817
Short name T1449
Test name
Test status
Simulation time 3341611734 ps
CPU time 3.38 seconds
Started Jun 27 06:34:41 PM PDT 24
Finished Jun 27 06:34:51 PM PDT 24
Peak memory 206336 kb
Host smart-141831b8-20db-47e2-ab55-f2d8efb3de1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20268
31817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.2026831817
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.3140807416
Short name T248
Test name
Test status
Simulation time 7339508197 ps
CPU time 53.07 seconds
Started Jun 27 06:34:39 PM PDT 24
Finished Jun 27 06:35:36 PM PDT 24
Peak memory 206312 kb
Host smart-36d6d281-8eb3-475e-a66c-6bf78f99cb79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31408
07416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.3140807416
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.45458782
Short name T701
Test name
Test status
Simulation time 3241895635 ps
CPU time 84.18 seconds
Started Jun 27 06:34:43 PM PDT 24
Finished Jun 27 06:36:17 PM PDT 24
Peak memory 206440 kb
Host smart-bb11db87-9d7e-4cd8-a152-35df0a64aaf3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=45458782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.45458782
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.3263771582
Short name T1019
Test name
Test status
Simulation time 251359659 ps
CPU time 0.91 seconds
Started Jun 27 06:34:36 PM PDT 24
Finished Jun 27 06:34:39 PM PDT 24
Peak memory 206304 kb
Host smart-efff96bb-b335-4e20-b540-f77a6fa7ed60
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3263771582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.3263771582
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.2885897669
Short name T2424
Test name
Test status
Simulation time 205103676 ps
CPU time 0.87 seconds
Started Jun 27 06:34:43 PM PDT 24
Finished Jun 27 06:34:53 PM PDT 24
Peak memory 206284 kb
Host smart-128950ab-b366-4793-8e29-214e53017c5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28858
97669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.2885897669
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.3457013384
Short name T2425
Test name
Test status
Simulation time 6121727224 ps
CPU time 53.9 seconds
Started Jun 27 06:34:37 PM PDT 24
Finished Jun 27 06:35:33 PM PDT 24
Peak memory 206448 kb
Host smart-1d6320e6-cafb-4d7a-be11-86d6c2163c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34570
13384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.3457013384
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.2961487309
Short name T644
Test name
Test status
Simulation time 4826884142 ps
CPU time 44.3 seconds
Started Jun 27 06:34:45 PM PDT 24
Finished Jun 27 06:35:41 PM PDT 24
Peak memory 206460 kb
Host smart-1113d167-fda2-4aa8-9037-91ae8aceeb61
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2961487309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.2961487309
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.3970378006
Short name T2169
Test name
Test status
Simulation time 163936565 ps
CPU time 0.85 seconds
Started Jun 27 06:34:43 PM PDT 24
Finished Jun 27 06:34:54 PM PDT 24
Peak memory 206296 kb
Host smart-6e726bcf-68de-4e18-be2c-eb953f354154
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3970378006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.3970378006
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.2578777258
Short name T1632
Test name
Test status
Simulation time 163045401 ps
CPU time 0.72 seconds
Started Jun 27 06:34:39 PM PDT 24
Finished Jun 27 06:34:44 PM PDT 24
Peak memory 206256 kb
Host smart-46bada84-16cd-4519-9d82-4ba8954a7280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25787
77258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.2578777258
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.3550742403
Short name T1107
Test name
Test status
Simulation time 187923949 ps
CPU time 0.83 seconds
Started Jun 27 06:34:41 PM PDT 24
Finished Jun 27 06:34:50 PM PDT 24
Peak memory 206456 kb
Host smart-caf86041-6977-4ec0-b0c4-a2adc65537cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35507
42403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.3550742403
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.3261271820
Short name T973
Test name
Test status
Simulation time 198202619 ps
CPU time 0.89 seconds
Started Jun 27 06:34:40 PM PDT 24
Finished Jun 27 06:34:46 PM PDT 24
Peak memory 206256 kb
Host smart-f3377f5c-6845-4d2b-b044-67e163a5a40f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32612
71820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.3261271820
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.2818423692
Short name T2131
Test name
Test status
Simulation time 186527072 ps
CPU time 0.8 seconds
Started Jun 27 06:34:36 PM PDT 24
Finished Jun 27 06:34:39 PM PDT 24
Peak memory 206268 kb
Host smart-ea2aef46-d81a-4b82-bcce-f36f22ecd282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28184
23692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.2818423692
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.1973267569
Short name T1521
Test name
Test status
Simulation time 173797724 ps
CPU time 0.82 seconds
Started Jun 27 06:34:39 PM PDT 24
Finished Jun 27 06:34:44 PM PDT 24
Peak memory 206192 kb
Host smart-a1f8918f-e39e-4aca-9fc7-6a4d2e278ba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19732
67569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.1973267569
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.4141476013
Short name T1887
Test name
Test status
Simulation time 237931852 ps
CPU time 0.94 seconds
Started Jun 27 06:34:37 PM PDT 24
Finished Jun 27 06:34:41 PM PDT 24
Peak memory 206304 kb
Host smart-422ead99-52b8-4032-a07d-9e2d347696ac
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4141476013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.4141476013
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.1774301005
Short name T1648
Test name
Test status
Simulation time 198831748 ps
CPU time 0.96 seconds
Started Jun 27 06:34:39 PM PDT 24
Finished Jun 27 06:34:44 PM PDT 24
Peak memory 206276 kb
Host smart-c0dfe616-6c4b-481a-8145-1636faa6bfaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17743
01005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.1774301005
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.2321021164
Short name T1329
Test name
Test status
Simulation time 149948598 ps
CPU time 0.79 seconds
Started Jun 27 06:34:40 PM PDT 24
Finished Jun 27 06:34:47 PM PDT 24
Peak memory 206256 kb
Host smart-66581b69-099b-43f3-bfb1-160e490336e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23210
21164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.2321021164
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.341542775
Short name T34
Test name
Test status
Simulation time 56764635 ps
CPU time 0.68 seconds
Started Jun 27 06:34:45 PM PDT 24
Finished Jun 27 06:34:57 PM PDT 24
Peak memory 205876 kb
Host smart-5b5ce95d-47e5-4106-9d7b-790f1d126af0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34154
2775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.341542775
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.3259545130
Short name T1424
Test name
Test status
Simulation time 8463750882 ps
CPU time 19.57 seconds
Started Jun 27 06:34:40 PM PDT 24
Finished Jun 27 06:35:05 PM PDT 24
Peak memory 206516 kb
Host smart-daddc0df-f302-4ce9-b5a6-0874bcc30d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32595
45130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.3259545130
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.956727862
Short name T559
Test name
Test status
Simulation time 286122058 ps
CPU time 0.93 seconds
Started Jun 27 06:34:40 PM PDT 24
Finished Jun 27 06:34:47 PM PDT 24
Peak memory 206260 kb
Host smart-d57bdf82-f8e1-443b-9104-4b8ebe209506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95672
7862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.956727862
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.636477643
Short name T2253
Test name
Test status
Simulation time 11720487465 ps
CPU time 58.19 seconds
Started Jun 27 06:34:39 PM PDT 24
Finished Jun 27 06:35:41 PM PDT 24
Peak memory 206356 kb
Host smart-a505da7a-f774-4784-b570-9f8f8101641b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=636477643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.636477643
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.320435386
Short name T1878
Test name
Test status
Simulation time 9880716367 ps
CPU time 83.23 seconds
Started Jun 27 06:34:41 PM PDT 24
Finished Jun 27 06:36:12 PM PDT 24
Peak memory 206492 kb
Host smart-0fb5b735-c4c7-420f-a8ac-63a3d3a1a32d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=320435386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.320435386
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.4186802108
Short name T2237
Test name
Test status
Simulation time 16094606899 ps
CPU time 323.19 seconds
Started Jun 27 06:34:42 PM PDT 24
Finished Jun 27 06:40:14 PM PDT 24
Peak memory 206412 kb
Host smart-0fc5dd4c-ed27-4d22-b1c7-db3d3188f549
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4186802108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.4186802108
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.3113857957
Short name T693
Test name
Test status
Simulation time 148298809 ps
CPU time 0.77 seconds
Started Jun 27 06:34:46 PM PDT 24
Finished Jun 27 06:34:57 PM PDT 24
Peak memory 206280 kb
Host smart-a3a71344-e979-4db3-8cb2-8c3b816fd2fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31138
57957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.3113857957
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.1431259062
Short name T785
Test name
Test status
Simulation time 206734865 ps
CPU time 0.85 seconds
Started Jun 27 06:34:37 PM PDT 24
Finished Jun 27 06:34:40 PM PDT 24
Peak memory 206252 kb
Host smart-555e6a9f-397c-446d-8561-2904def525ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14312
59062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.1431259062
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.1209252422
Short name T2361
Test name
Test status
Simulation time 185558072 ps
CPU time 0.79 seconds
Started Jun 27 06:34:41 PM PDT 24
Finished Jun 27 06:34:49 PM PDT 24
Peak memory 206280 kb
Host smart-019fe4fd-c00e-4106-ad72-c9e5638cc2ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12092
52422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.1209252422
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.1017242305
Short name T2017
Test name
Test status
Simulation time 168600040 ps
CPU time 0.79 seconds
Started Jun 27 06:34:41 PM PDT 24
Finished Jun 27 06:34:50 PM PDT 24
Peak memory 206284 kb
Host smart-13e3ab5c-b19b-4fca-a111-ae233bcad3e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10172
42305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.1017242305
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.2794090474
Short name T196
Test name
Test status
Simulation time 717051998 ps
CPU time 1.75 seconds
Started Jun 27 06:34:40 PM PDT 24
Finished Jun 27 06:34:46 PM PDT 24
Peak memory 224028 kb
Host smart-54e8c6b4-665a-448e-be50-b4e06408ea46
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2794090474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.2794090474
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.1524185203
Short name T57
Test name
Test status
Simulation time 382933200 ps
CPU time 1.24 seconds
Started Jun 27 06:34:46 PM PDT 24
Finished Jun 27 06:34:57 PM PDT 24
Peak memory 206256 kb
Host smart-3f509ae7-1d83-4aa9-aba6-32ac8b499ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15241
85203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.1524185203
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.3055154526
Short name T1137
Test name
Test status
Simulation time 162189299 ps
CPU time 0.78 seconds
Started Jun 27 06:34:40 PM PDT 24
Finished Jun 27 06:34:45 PM PDT 24
Peak memory 206252 kb
Host smart-6a81774c-efc0-4c3f-9bb8-142ac4b695fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30551
54526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.3055154526
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.2228409930
Short name T661
Test name
Test status
Simulation time 233213088 ps
CPU time 0.89 seconds
Started Jun 27 06:34:43 PM PDT 24
Finished Jun 27 06:34:53 PM PDT 24
Peak memory 206292 kb
Host smart-3e95b301-2c6a-40e3-8371-ac050cd575cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22284
09930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.2228409930
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.4080641479
Short name T1064
Test name
Test status
Simulation time 230753558 ps
CPU time 0.96 seconds
Started Jun 27 06:34:45 PM PDT 24
Finished Jun 27 06:34:57 PM PDT 24
Peak memory 206272 kb
Host smart-16da486e-36e9-4a82-b521-2c5ae2950ab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40806
41479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.4080641479
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.2298507204
Short name T2350
Test name
Test status
Simulation time 3770626071 ps
CPU time 26.06 seconds
Started Jun 27 06:34:43 PM PDT 24
Finished Jun 27 06:35:19 PM PDT 24
Peak memory 206480 kb
Host smart-a0a015a6-7321-4527-9323-c234cc67e617
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2298507204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.2298507204
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.4066415461
Short name T1367
Test name
Test status
Simulation time 185903107 ps
CPU time 0.82 seconds
Started Jun 27 06:34:41 PM PDT 24
Finished Jun 27 06:34:50 PM PDT 24
Peak memory 206464 kb
Host smart-34c41c5c-6b67-4109-a00e-c24af19ef5dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40664
15461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.4066415461
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.2397507145
Short name T2270
Test name
Test status
Simulation time 179684003 ps
CPU time 0.87 seconds
Started Jun 27 06:34:40 PM PDT 24
Finished Jun 27 06:34:47 PM PDT 24
Peak memory 206252 kb
Host smart-16ced4ca-6b2f-4afe-beab-77aebb72b411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23975
07145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.2397507145
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.1033661626
Short name T454
Test name
Test status
Simulation time 4308240204 ps
CPU time 120.14 seconds
Started Jun 27 06:34:40 PM PDT 24
Finished Jun 27 06:36:45 PM PDT 24
Peak memory 206596 kb
Host smart-3abb2bd9-28a9-4997-8a81-ea80fdb50272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10336
61626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.1033661626
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.348313360
Short name T798
Test name
Test status
Simulation time 83746830 ps
CPU time 0.72 seconds
Started Jun 27 06:36:34 PM PDT 24
Finished Jun 27 06:36:37 PM PDT 24
Peak memory 206352 kb
Host smart-923ad383-db3f-4cfc-80b4-f8fdc6369dd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=348313360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.348313360
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.402318368
Short name T1203
Test name
Test status
Simulation time 3880177862 ps
CPU time 5.36 seconds
Started Jun 27 06:36:02 PM PDT 24
Finished Jun 27 06:36:10 PM PDT 24
Peak memory 206356 kb
Host smart-1c188d0d-4a30-4481-aed1-69d939bc4854
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=402318368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.402318368
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.1477779798
Short name T2045
Test name
Test status
Simulation time 13355507883 ps
CPU time 12.61 seconds
Started Jun 27 06:36:00 PM PDT 24
Finished Jun 27 06:36:13 PM PDT 24
Peak memory 206348 kb
Host smart-7149ea48-5e85-4d0d-8279-d43d10f759b9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1477779798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.1477779798
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.312740863
Short name T758
Test name
Test status
Simulation time 23302496262 ps
CPU time 24.01 seconds
Started Jun 27 06:36:03 PM PDT 24
Finished Jun 27 06:36:29 PM PDT 24
Peak memory 206312 kb
Host smart-cd747ccd-b600-4e16-b2dc-c550191d86aa
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=312740863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.312740863
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.1724145064
Short name T575
Test name
Test status
Simulation time 171852797 ps
CPU time 0.81 seconds
Started Jun 27 06:36:01 PM PDT 24
Finished Jun 27 06:36:03 PM PDT 24
Peak memory 206172 kb
Host smart-e8e48ec6-7fd6-4c42-99a7-b8a362e16d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17241
45064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.1724145064
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.3661038232
Short name T1690
Test name
Test status
Simulation time 166182293 ps
CPU time 0.86 seconds
Started Jun 27 06:36:00 PM PDT 24
Finished Jun 27 06:36:02 PM PDT 24
Peak memory 206428 kb
Host smart-a10feaea-d2fb-4cb0-8ca7-835db2f3b10f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36610
38232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.3661038232
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.1662562657
Short name T1139
Test name
Test status
Simulation time 305058460 ps
CPU time 1.1 seconds
Started Jun 27 06:36:01 PM PDT 24
Finished Jun 27 06:36:03 PM PDT 24
Peak memory 206280 kb
Host smart-fa6291df-5f0c-48da-bf82-ff2bee1a88b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16625
62657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.1662562657
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.1125865023
Short name T167
Test name
Test status
Simulation time 732836169 ps
CPU time 2.05 seconds
Started Jun 27 06:36:01 PM PDT 24
Finished Jun 27 06:36:04 PM PDT 24
Peak memory 206420 kb
Host smart-3bbf2cdd-ccfc-4fd2-99a3-4f70e3cbd77f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11258
65023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.1125865023
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.3143887627
Short name T174
Test name
Test status
Simulation time 8840954068 ps
CPU time 16.18 seconds
Started Jun 27 06:36:02 PM PDT 24
Finished Jun 27 06:36:21 PM PDT 24
Peak memory 206432 kb
Host smart-115d38d7-90c1-43a9-a9e3-3ae0ebbe5847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31438
87627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.3143887627
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.2221562119
Short name T534
Test name
Test status
Simulation time 455582232 ps
CPU time 1.38 seconds
Started Jun 27 06:36:00 PM PDT 24
Finished Jun 27 06:36:02 PM PDT 24
Peak memory 206256 kb
Host smart-81fd4157-b094-4c03-9a7a-1d5357dacc79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22215
62119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.2221562119
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.3748779797
Short name T2077
Test name
Test status
Simulation time 170241113 ps
CPU time 0.79 seconds
Started Jun 27 06:35:59 PM PDT 24
Finished Jun 27 06:36:01 PM PDT 24
Peak memory 206236 kb
Host smart-e8e42d61-a7a1-4460-b6a8-d0a32bbecbc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37487
79797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.3748779797
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.4225958008
Short name T451
Test name
Test status
Simulation time 39175486 ps
CPU time 0.65 seconds
Started Jun 27 06:36:03 PM PDT 24
Finished Jun 27 06:36:05 PM PDT 24
Peak memory 206252 kb
Host smart-0b1a4045-3b9b-4b25-b28a-7887849b51a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42259
58008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.4225958008
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.3836112688
Short name T2210
Test name
Test status
Simulation time 809155946 ps
CPU time 1.87 seconds
Started Jun 27 06:36:01 PM PDT 24
Finished Jun 27 06:36:04 PM PDT 24
Peak memory 206368 kb
Host smart-0fdcb214-f8e9-4d7b-a435-c7c8bf19f60c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38361
12688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.3836112688
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.879697121
Short name T750
Test name
Test status
Simulation time 409793648 ps
CPU time 2.47 seconds
Started Jun 27 06:36:02 PM PDT 24
Finished Jun 27 06:36:07 PM PDT 24
Peak memory 206368 kb
Host smart-1c8aa3a8-1a40-4017-a505-5654a7ef3121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87969
7121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.879697121
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.1674887865
Short name T585
Test name
Test status
Simulation time 231984185 ps
CPU time 0.85 seconds
Started Jun 27 06:36:02 PM PDT 24
Finished Jun 27 06:36:05 PM PDT 24
Peak memory 206188 kb
Host smart-de617210-cffc-41f1-9e02-8d4a5391876f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16748
87865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.1674887865
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.3960839512
Short name T1566
Test name
Test status
Simulation time 156204063 ps
CPU time 0.81 seconds
Started Jun 27 06:36:02 PM PDT 24
Finished Jun 27 06:36:05 PM PDT 24
Peak memory 206288 kb
Host smart-f2dcd2f3-9330-45e4-8f76-c8c5c5f08857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39608
39512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.3960839512
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.3984096407
Short name T569
Test name
Test status
Simulation time 175236921 ps
CPU time 0.85 seconds
Started Jun 27 06:36:02 PM PDT 24
Finished Jun 27 06:36:04 PM PDT 24
Peak memory 206280 kb
Host smart-861031e7-61b2-46dd-bd58-f456a7e1ab19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39840
96407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.3984096407
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_invalid_sync.3780384097
Short name T2561
Test name
Test status
Simulation time 8098258447 ps
CPU time 77.19 seconds
Started Jun 27 06:36:03 PM PDT 24
Finished Jun 27 06:37:23 PM PDT 24
Peak memory 206412 kb
Host smart-42799dba-771c-4725-848b-2c9f8ddb1d2c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3780384097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.3780384097
Directory /workspace/10.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.1366782001
Short name T1669
Test name
Test status
Simulation time 241758650 ps
CPU time 0.89 seconds
Started Jun 27 06:36:07 PM PDT 24
Finished Jun 27 06:36:11 PM PDT 24
Peak memory 206252 kb
Host smart-861e5683-f5d9-4732-a7a2-c7b3a2d6ceca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13667
82001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.1366782001
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.927690055
Short name T1762
Test name
Test status
Simulation time 23331097765 ps
CPU time 23.17 seconds
Started Jun 27 06:36:04 PM PDT 24
Finished Jun 27 06:36:30 PM PDT 24
Peak memory 206336 kb
Host smart-ce50857e-532e-46c8-b583-3bdc3dc28494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92769
0055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.927690055
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.4120747680
Short name T531
Test name
Test status
Simulation time 3330681399 ps
CPU time 4.07 seconds
Started Jun 27 06:36:02 PM PDT 24
Finished Jun 27 06:36:08 PM PDT 24
Peak memory 206332 kb
Host smart-81901616-502e-4b9c-84f2-b854d264a96b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41207
47680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.4120747680
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.2049296341
Short name T1602
Test name
Test status
Simulation time 8338726698 ps
CPU time 229.3 seconds
Started Jun 27 06:36:03 PM PDT 24
Finished Jun 27 06:39:54 PM PDT 24
Peak memory 206516 kb
Host smart-120870dd-91df-424f-b191-66779a2e1e38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20492
96341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.2049296341
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.3695173254
Short name T1714
Test name
Test status
Simulation time 3437621886 ps
CPU time 32.8 seconds
Started Jun 27 06:36:03 PM PDT 24
Finished Jun 27 06:36:38 PM PDT 24
Peak memory 206444 kb
Host smart-b55bab7d-284a-40ac-94bf-8b37c7e2179f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3695173254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.3695173254
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.2816180051
Short name T901
Test name
Test status
Simulation time 236011246 ps
CPU time 0.87 seconds
Started Jun 27 06:36:07 PM PDT 24
Finished Jun 27 06:36:11 PM PDT 24
Peak memory 206272 kb
Host smart-35c72041-a6da-4e81-97a8-2516b234c96f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2816180051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.2816180051
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.423092669
Short name T2046
Test name
Test status
Simulation time 191853926 ps
CPU time 0.88 seconds
Started Jun 27 06:36:07 PM PDT 24
Finished Jun 27 06:36:11 PM PDT 24
Peak memory 206260 kb
Host smart-90dc2a15-e8f4-4b85-971b-3a9c340ba7d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42309
2669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.423092669
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.174756377
Short name T474
Test name
Test status
Simulation time 5889805591 ps
CPU time 53.14 seconds
Started Jun 27 06:36:03 PM PDT 24
Finished Jun 27 06:36:58 PM PDT 24
Peak memory 206484 kb
Host smart-356b2bce-be69-4b97-9875-6454d8231577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17475
6377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.174756377
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.3916718067
Short name T2284
Test name
Test status
Simulation time 4839289783 ps
CPU time 34.01 seconds
Started Jun 27 06:36:06 PM PDT 24
Finished Jun 27 06:36:43 PM PDT 24
Peak memory 206264 kb
Host smart-70acbf7c-2402-4b2a-9b95-25a69345b9cf
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3916718067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.3916718067
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.2113480650
Short name T816
Test name
Test status
Simulation time 216865354 ps
CPU time 0.9 seconds
Started Jun 27 06:36:09 PM PDT 24
Finished Jun 27 06:36:14 PM PDT 24
Peak memory 206288 kb
Host smart-cb2ad93f-4d17-475b-ae63-f4cac288126a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2113480650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.2113480650
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.989838922
Short name T692
Test name
Test status
Simulation time 171059130 ps
CPU time 0.74 seconds
Started Jun 27 06:36:07 PM PDT 24
Finished Jun 27 06:36:11 PM PDT 24
Peak memory 206280 kb
Host smart-42e1208e-8fbf-4bdc-9dfd-462cb141c832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98983
8922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.989838922
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.2006365793
Short name T1388
Test name
Test status
Simulation time 205831983 ps
CPU time 0.89 seconds
Started Jun 27 06:36:09 PM PDT 24
Finished Jun 27 06:36:14 PM PDT 24
Peak memory 206276 kb
Host smart-e74c02cd-d653-4d89-95ba-b7fd0c1e83bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20063
65793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.2006365793
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.1464724264
Short name T320
Test name
Test status
Simulation time 191187346 ps
CPU time 0.86 seconds
Started Jun 27 06:36:05 PM PDT 24
Finished Jun 27 06:36:08 PM PDT 24
Peak memory 206276 kb
Host smart-20352cb8-5161-49b3-a422-38f45f11b994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14647
24264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.1464724264
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.641976668
Short name T445
Test name
Test status
Simulation time 161016742 ps
CPU time 0.78 seconds
Started Jun 27 06:36:08 PM PDT 24
Finished Jun 27 06:36:12 PM PDT 24
Peak memory 206268 kb
Host smart-90fe9e55-33a6-418d-9de6-87393819be3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64197
6668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.641976668
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.4290304675
Short name T2064
Test name
Test status
Simulation time 152608674 ps
CPU time 0.81 seconds
Started Jun 27 06:36:06 PM PDT 24
Finished Jun 27 06:36:09 PM PDT 24
Peak memory 206268 kb
Host smart-a55bc9d4-3b27-4e16-9b71-fcec15b0d458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42903
04675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.4290304675
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.1838933510
Short name T2385
Test name
Test status
Simulation time 201783755 ps
CPU time 0.9 seconds
Started Jun 27 06:36:03 PM PDT 24
Finished Jun 27 06:36:06 PM PDT 24
Peak memory 206296 kb
Host smart-45ef2eec-3e0f-4ada-a4a9-b1a9bbb76697
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1838933510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.1838933510
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.179728563
Short name T650
Test name
Test status
Simulation time 167382483 ps
CPU time 0.8 seconds
Started Jun 27 06:36:12 PM PDT 24
Finished Jun 27 06:36:16 PM PDT 24
Peak memory 206256 kb
Host smart-fd84da22-60e5-41a7-8d5a-7361b421cccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17972
8563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.179728563
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.652088362
Short name T1181
Test name
Test status
Simulation time 192972050 ps
CPU time 0.92 seconds
Started Jun 27 06:36:16 PM PDT 24
Finished Jun 27 06:36:18 PM PDT 24
Peak memory 206264 kb
Host smart-91524122-a70b-4514-876f-bf76ad067948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65208
8362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.652088362
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.1873072273
Short name T1710
Test name
Test status
Simulation time 188077285 ps
CPU time 0.79 seconds
Started Jun 27 06:36:10 PM PDT 24
Finished Jun 27 06:36:14 PM PDT 24
Peak memory 206312 kb
Host smart-37e31189-d425-475a-972c-dfcd70203353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18730
72273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.1873072273
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.750405113
Short name T1042
Test name
Test status
Simulation time 188416836 ps
CPU time 0.89 seconds
Started Jun 27 06:36:09 PM PDT 24
Finished Jun 27 06:36:14 PM PDT 24
Peak memory 206288 kb
Host smart-c7ee1228-d4a6-45ee-a3a0-d02dd05a507d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75040
5113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.750405113
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.3875634009
Short name T2218
Test name
Test status
Simulation time 168809832 ps
CPU time 0.78 seconds
Started Jun 27 06:36:41 PM PDT 24
Finished Jun 27 06:36:48 PM PDT 24
Peak memory 205304 kb
Host smart-8c20df8e-d751-4555-9787-da78cf7fedcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38756
34009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.3875634009
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.631629916
Short name T1262
Test name
Test status
Simulation time 148678404 ps
CPU time 0.82 seconds
Started Jun 27 06:36:38 PM PDT 24
Finished Jun 27 06:36:45 PM PDT 24
Peak memory 206256 kb
Host smart-1481fb41-dd07-4059-9f76-198e78bcdfe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63162
9916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.631629916
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.790921312
Short name T1980
Test name
Test status
Simulation time 152114392 ps
CPU time 0.78 seconds
Started Jun 27 06:36:33 PM PDT 24
Finished Jun 27 06:36:36 PM PDT 24
Peak memory 206440 kb
Host smart-804fe3e4-d34a-44ff-aaab-9194950ac2b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79092
1312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.790921312
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.3569062895
Short name T84
Test name
Test status
Simulation time 175235757 ps
CPU time 0.83 seconds
Started Jun 27 06:36:39 PM PDT 24
Finished Jun 27 06:36:45 PM PDT 24
Peak memory 206316 kb
Host smart-6197cdbb-8bbb-4b08-99ea-469f00f11151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35690
62895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.3569062895
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.329831794
Short name T738
Test name
Test status
Simulation time 3864461840 ps
CPU time 28.58 seconds
Started Jun 27 06:36:37 PM PDT 24
Finished Jun 27 06:37:11 PM PDT 24
Peak memory 206312 kb
Host smart-b7a63b4a-8eaa-4e67-b394-a2074bbb24ff
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=329831794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.329831794
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.1220726253
Short name T358
Test name
Test status
Simulation time 156679991 ps
CPU time 0.76 seconds
Started Jun 27 06:36:38 PM PDT 24
Finished Jun 27 06:36:44 PM PDT 24
Peak memory 206280 kb
Host smart-0dc8507f-7668-4448-bad1-fbf167291fda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12207
26253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.1220726253
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.3007027156
Short name T2495
Test name
Test status
Simulation time 182282513 ps
CPU time 0.84 seconds
Started Jun 27 06:36:41 PM PDT 24
Finished Jun 27 06:36:48 PM PDT 24
Peak memory 206252 kb
Host smart-6f97a384-39c0-4827-a2b3-2e626754c926
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30070
27156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.3007027156
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.3256613945
Short name T1504
Test name
Test status
Simulation time 5001078395 ps
CPU time 33.48 seconds
Started Jun 27 06:36:34 PM PDT 24
Finished Jun 27 06:37:09 PM PDT 24
Peak memory 206400 kb
Host smart-fdca0df6-ecc5-443d-b15e-eb88eb26ec42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32566
13945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.3256613945
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.343471751
Short name T2286
Test name
Test status
Simulation time 56473843 ps
CPU time 0.78 seconds
Started Jun 27 06:36:36 PM PDT 24
Finished Jun 27 06:36:42 PM PDT 24
Peak memory 206192 kb
Host smart-f0ff8c02-eef4-4aa9-981c-f7b960e5548e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=343471751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.343471751
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.3353787501
Short name T1701
Test name
Test status
Simulation time 4132293630 ps
CPU time 4.56 seconds
Started Jun 27 06:36:35 PM PDT 24
Finished Jun 27 06:36:42 PM PDT 24
Peak memory 206440 kb
Host smart-3fe9bf38-0a05-4fb1-9da7-89c57811a241
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3353787501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.3353787501
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.976659637
Short name T1393
Test name
Test status
Simulation time 13457574714 ps
CPU time 13.52 seconds
Started Jun 27 06:36:36 PM PDT 24
Finished Jun 27 06:36:54 PM PDT 24
Peak memory 206476 kb
Host smart-52fa9541-b82c-4e2e-a03b-1ba9cec014ae
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=976659637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.976659637
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.1170317076
Short name T229
Test name
Test status
Simulation time 23393988664 ps
CPU time 28.71 seconds
Started Jun 27 06:36:41 PM PDT 24
Finished Jun 27 06:37:16 PM PDT 24
Peak memory 206452 kb
Host smart-83b43158-65e6-4f37-aa1d-b25e5ce8f988
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1170317076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.1170317076
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.13231198
Short name T481
Test name
Test status
Simulation time 154323216 ps
CPU time 0.82 seconds
Started Jun 27 06:36:36 PM PDT 24
Finished Jun 27 06:36:40 PM PDT 24
Peak memory 206288 kb
Host smart-3dd14edb-f2df-4fdc-90d3-5d1330d9dd35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13231
198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.13231198
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.4025321409
Short name T1867
Test name
Test status
Simulation time 155970965 ps
CPU time 0.81 seconds
Started Jun 27 06:36:36 PM PDT 24
Finished Jun 27 06:36:42 PM PDT 24
Peak memory 206212 kb
Host smart-f978905c-eff1-4ce8-913c-5f5d256a527a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40253
21409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.4025321409
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.3288009183
Short name T1517
Test name
Test status
Simulation time 252278923 ps
CPU time 1.02 seconds
Started Jun 27 06:36:36 PM PDT 24
Finished Jun 27 06:36:41 PM PDT 24
Peak memory 206236 kb
Host smart-88c067d8-dca8-4204-87cd-c2bcd1673a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32880
09183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.3288009183
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.2019449198
Short name T1728
Test name
Test status
Simulation time 322219758 ps
CPU time 1.13 seconds
Started Jun 27 06:36:37 PM PDT 24
Finished Jun 27 06:36:42 PM PDT 24
Peak memory 206292 kb
Host smart-17b90d9a-9992-4b56-a2eb-8e53efd1d3a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20194
49198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.2019449198
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.548881026
Short name T1111
Test name
Test status
Simulation time 19320305065 ps
CPU time 31.09 seconds
Started Jun 27 06:36:37 PM PDT 24
Finished Jun 27 06:37:12 PM PDT 24
Peak memory 206476 kb
Host smart-71ec9639-4ff2-42de-8968-e838fd73c345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54888
1026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.548881026
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.109157797
Short name T2263
Test name
Test status
Simulation time 456950266 ps
CPU time 1.5 seconds
Started Jun 27 06:36:38 PM PDT 24
Finished Jun 27 06:36:46 PM PDT 24
Peak memory 206292 kb
Host smart-47a714c4-ff90-40a5-b3e8-9938c5cb15e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10915
7797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.109157797
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.2895813460
Short name T215
Test name
Test status
Simulation time 140946477 ps
CPU time 0.77 seconds
Started Jun 27 06:36:42 PM PDT 24
Finished Jun 27 06:36:49 PM PDT 24
Peak memory 206268 kb
Host smart-e17cc082-9099-4900-8380-6a68847760ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28958
13460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.2895813460
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.2956247746
Short name T2398
Test name
Test status
Simulation time 34506096 ps
CPU time 0.64 seconds
Started Jun 27 06:36:41 PM PDT 24
Finished Jun 27 06:36:48 PM PDT 24
Peak memory 206264 kb
Host smart-73d2fb17-bd94-4d8f-a4df-40b253f26e4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29562
47746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.2956247746
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.2369725622
Short name T2063
Test name
Test status
Simulation time 1000796217 ps
CPU time 2.78 seconds
Started Jun 27 06:36:35 PM PDT 24
Finished Jun 27 06:36:41 PM PDT 24
Peak memory 206432 kb
Host smart-dbf121b5-7626-4f67-b3d2-b0def48d0d99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23697
25622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.2369725622
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.2917511529
Short name T2195
Test name
Test status
Simulation time 418192049 ps
CPU time 2.53 seconds
Started Jun 27 06:36:33 PM PDT 24
Finished Jun 27 06:36:38 PM PDT 24
Peak memory 206340 kb
Host smart-ab8e55d3-be8e-4b7c-8a71-cb1732302ef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29175
11529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.2917511529
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.3982131775
Short name T1310
Test name
Test status
Simulation time 175842746 ps
CPU time 0.83 seconds
Started Jun 27 06:36:35 PM PDT 24
Finished Jun 27 06:36:38 PM PDT 24
Peak memory 206288 kb
Host smart-a802a0d4-6eba-48ed-af18-c425dcee1803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39821
31775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.3982131775
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.2749402833
Short name T2367
Test name
Test status
Simulation time 148532195 ps
CPU time 0.77 seconds
Started Jun 27 06:36:34 PM PDT 24
Finished Jun 27 06:36:37 PM PDT 24
Peak memory 206288 kb
Host smart-ad5685e0-0bbc-4e82-8082-0b7deaf16f48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27494
02833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.2749402833
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.609946473
Short name T1163
Test name
Test status
Simulation time 171098845 ps
CPU time 0.85 seconds
Started Jun 27 06:36:36 PM PDT 24
Finished Jun 27 06:36:42 PM PDT 24
Peak memory 206268 kb
Host smart-68b4a354-aafc-43bf-a0b6-0b5dc1f5a7ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60994
6473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.609946473
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.172618703
Short name T2197
Test name
Test status
Simulation time 275151159 ps
CPU time 0.94 seconds
Started Jun 27 06:36:33 PM PDT 24
Finished Jun 27 06:36:36 PM PDT 24
Peak memory 206248 kb
Host smart-1dde7343-0c72-4192-9491-8cdaa353fdbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17261
8703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.172618703
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.1959864881
Short name T2395
Test name
Test status
Simulation time 23306873528 ps
CPU time 23.39 seconds
Started Jun 27 06:36:37 PM PDT 24
Finished Jun 27 06:37:05 PM PDT 24
Peak memory 206332 kb
Host smart-9286b569-dc3d-4e76-ad85-bc56bec09418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19598
64881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.1959864881
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.1611334045
Short name T714
Test name
Test status
Simulation time 3359838279 ps
CPU time 3.59 seconds
Started Jun 27 06:36:37 PM PDT 24
Finished Jun 27 06:36:46 PM PDT 24
Peak memory 206348 kb
Host smart-f961dc2a-16eb-4ec4-bb44-5aa1e336ba52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16113
34045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.1611334045
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.2666787622
Short name T145
Test name
Test status
Simulation time 13420539895 ps
CPU time 99.28 seconds
Started Jun 27 06:36:38 PM PDT 24
Finished Jun 27 06:38:23 PM PDT 24
Peak memory 206384 kb
Host smart-59d1bef9-b73d-478b-bf67-d689cb13c3e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26667
87622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.2666787622
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.4242222284
Short name T642
Test name
Test status
Simulation time 3793468699 ps
CPU time 103.72 seconds
Started Jun 27 06:36:38 PM PDT 24
Finished Jun 27 06:38:28 PM PDT 24
Peak memory 206440 kb
Host smart-fceda519-c698-4acd-ae32-dffa5739534a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4242222284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.4242222284
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.2347389334
Short name T2481
Test name
Test status
Simulation time 237823521 ps
CPU time 0.92 seconds
Started Jun 27 06:36:37 PM PDT 24
Finished Jun 27 06:36:42 PM PDT 24
Peak memory 206288 kb
Host smart-7466d341-71ce-46a1-b8d0-c934229b7cf7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2347389334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.2347389334
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.3864151827
Short name T2247
Test name
Test status
Simulation time 185463232 ps
CPU time 0.85 seconds
Started Jun 27 06:36:35 PM PDT 24
Finished Jun 27 06:36:40 PM PDT 24
Peak memory 206280 kb
Host smart-b2ffbd68-994c-4612-820c-f9aff27d2446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38641
51827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.3864151827
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.2827932505
Short name T1953
Test name
Test status
Simulation time 5527303319 ps
CPU time 55.5 seconds
Started Jun 27 06:36:34 PM PDT 24
Finished Jun 27 06:37:33 PM PDT 24
Peak memory 206400 kb
Host smart-55ed9965-19d9-49da-a630-e5b3b8af68a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28279
32505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.2827932505
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.864826696
Short name T500
Test name
Test status
Simulation time 5400408460 ps
CPU time 36.77 seconds
Started Jun 27 06:36:39 PM PDT 24
Finished Jun 27 06:37:22 PM PDT 24
Peak memory 206400 kb
Host smart-486b1c3b-fc30-49d8-be5c-ff594ceeec1d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=864826696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.864826696
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.74995417
Short name T2523
Test name
Test status
Simulation time 167192854 ps
CPU time 0.81 seconds
Started Jun 27 06:36:37 PM PDT 24
Finished Jun 27 06:36:43 PM PDT 24
Peak memory 206256 kb
Host smart-8bb31daf-7465-4164-9c9d-306db318979c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=74995417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.74995417
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.4164233533
Short name T1455
Test name
Test status
Simulation time 142077879 ps
CPU time 0.79 seconds
Started Jun 27 06:36:32 PM PDT 24
Finished Jun 27 06:36:34 PM PDT 24
Peak memory 206276 kb
Host smart-287f8f37-2a6a-4526-b4ca-32503b8ea153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41642
33533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.4164233533
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.2506376513
Short name T390
Test name
Test status
Simulation time 241687492 ps
CPU time 0.89 seconds
Started Jun 27 06:36:33 PM PDT 24
Finished Jun 27 06:36:36 PM PDT 24
Peak memory 206284 kb
Host smart-bfb42226-df6f-4c22-8ad4-06476528b06c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25063
76513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.2506376513
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.3191065715
Short name T1791
Test name
Test status
Simulation time 195932725 ps
CPU time 0.86 seconds
Started Jun 27 06:36:36 PM PDT 24
Finished Jun 27 06:36:40 PM PDT 24
Peak memory 206240 kb
Host smart-bedb88a1-c0d0-44bc-8231-c1b55b9c92c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31910
65715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.3191065715
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.4272417417
Short name T557
Test name
Test status
Simulation time 168116656 ps
CPU time 0.82 seconds
Started Jun 27 06:36:38 PM PDT 24
Finished Jun 27 06:36:45 PM PDT 24
Peak memory 206304 kb
Host smart-7ed308d6-9e77-46e4-820a-c4f9fe3096d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42724
17417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.4272417417
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.3946550211
Short name T1451
Test name
Test status
Simulation time 175775621 ps
CPU time 0.79 seconds
Started Jun 27 06:36:37 PM PDT 24
Finished Jun 27 06:36:43 PM PDT 24
Peak memory 206292 kb
Host smart-c0cea33c-283b-4cf3-8985-2272103f1af1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39465
50211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.3946550211
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.1422256621
Short name T2560
Test name
Test status
Simulation time 208112110 ps
CPU time 0.88 seconds
Started Jun 27 06:36:40 PM PDT 24
Finished Jun 27 06:36:47 PM PDT 24
Peak memory 206272 kb
Host smart-f507cf2a-6bc0-4bfc-a343-7572d1929955
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1422256621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.1422256621
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.297490084
Short name T404
Test name
Test status
Simulation time 136877985 ps
CPU time 0.78 seconds
Started Jun 27 06:36:35 PM PDT 24
Finished Jun 27 06:36:39 PM PDT 24
Peak memory 206216 kb
Host smart-1f1297f9-6689-495c-908c-e3282f0d73bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29749
0084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.297490084
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.1822815584
Short name T922
Test name
Test status
Simulation time 42122701 ps
CPU time 0.66 seconds
Started Jun 27 06:36:36 PM PDT 24
Finished Jun 27 06:36:40 PM PDT 24
Peak memory 206280 kb
Host smart-7b913484-75a6-45eb-8681-265a1a30963d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18228
15584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.1822815584
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.2321600397
Short name T752
Test name
Test status
Simulation time 156933417 ps
CPU time 0.8 seconds
Started Jun 27 06:36:33 PM PDT 24
Finished Jun 27 06:36:36 PM PDT 24
Peak memory 206268 kb
Host smart-0f0c00bd-893a-4910-8075-b1d7a13eab6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23216
00397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.2321600397
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.1914442328
Short name T1071
Test name
Test status
Simulation time 208474220 ps
CPU time 0.9 seconds
Started Jun 27 06:36:37 PM PDT 24
Finished Jun 27 06:36:43 PM PDT 24
Peak memory 206252 kb
Host smart-562af03d-1dc8-4e11-9554-6930f0a61aeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19144
42328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.1914442328
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.591357455
Short name T1417
Test name
Test status
Simulation time 160478074 ps
CPU time 0.76 seconds
Started Jun 27 06:36:42 PM PDT 24
Finished Jun 27 06:36:48 PM PDT 24
Peak memory 206288 kb
Host smart-9db5e2d9-8ae8-469e-b549-99d56bfa4e28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59135
7455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.591357455
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.4056859627
Short name T581
Test name
Test status
Simulation time 159399802 ps
CPU time 0.81 seconds
Started Jun 27 06:36:37 PM PDT 24
Finished Jun 27 06:36:43 PM PDT 24
Peak memory 206284 kb
Host smart-264cae6b-18f4-41ec-bbaf-083f3ad7511e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40568
59627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.4056859627
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.4201633399
Short name T2198
Test name
Test status
Simulation time 215682050 ps
CPU time 0.83 seconds
Started Jun 27 06:36:33 PM PDT 24
Finished Jun 27 06:36:36 PM PDT 24
Peak memory 206216 kb
Host smart-146262f9-e68f-4eb8-b452-9731025d9102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42016
33399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.4201633399
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.4017589301
Short name T1200
Test name
Test status
Simulation time 146871092 ps
CPU time 0.78 seconds
Started Jun 27 06:36:39 PM PDT 24
Finished Jun 27 06:36:46 PM PDT 24
Peak memory 206272 kb
Host smart-b98ef350-4f6c-4b17-808e-e951a7f878cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40175
89301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.4017589301
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.742836593
Short name T378
Test name
Test status
Simulation time 156187472 ps
CPU time 0.79 seconds
Started Jun 27 06:36:36 PM PDT 24
Finished Jun 27 06:36:40 PM PDT 24
Peak memory 206204 kb
Host smart-03ec062f-572d-4ce1-bbe5-2e82d39b4e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74283
6593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.742836593
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.3817788844
Short name T2614
Test name
Test status
Simulation time 235523801 ps
CPU time 0.99 seconds
Started Jun 27 06:36:38 PM PDT 24
Finished Jun 27 06:36:45 PM PDT 24
Peak memory 206252 kb
Host smart-231b8154-b055-4ecd-b3b2-4f9b0ac54986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38177
88844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.3817788844
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.865585726
Short name T2377
Test name
Test status
Simulation time 5779849546 ps
CPU time 165.3 seconds
Started Jun 27 06:36:36 PM PDT 24
Finished Jun 27 06:39:26 PM PDT 24
Peak memory 206236 kb
Host smart-16efe645-bb03-4fd6-8249-7ac8cf414e21
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=865585726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.865585726
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.766841556
Short name T1144
Test name
Test status
Simulation time 160925098 ps
CPU time 0.75 seconds
Started Jun 27 06:36:40 PM PDT 24
Finished Jun 27 06:36:46 PM PDT 24
Peak memory 206252 kb
Host smart-8c219009-20d9-42f0-bc85-3462df4daabd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76684
1556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.766841556
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.3214240854
Short name T1647
Test name
Test status
Simulation time 161463272 ps
CPU time 0.83 seconds
Started Jun 27 06:36:34 PM PDT 24
Finished Jun 27 06:36:37 PM PDT 24
Peak memory 206264 kb
Host smart-0c1ce3f8-c769-4368-ace5-4e2444dfcb08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32142
40854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.3214240854
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.2108184381
Short name T2230
Test name
Test status
Simulation time 5043325406 ps
CPU time 49.51 seconds
Started Jun 27 06:36:37 PM PDT 24
Finished Jun 27 06:37:30 PM PDT 24
Peak memory 206396 kb
Host smart-9ee5aba7-9885-49ae-b6cf-3b4a74b6a3df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21081
84381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.2108184381
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.2821944377
Short name T995
Test name
Test status
Simulation time 38460259 ps
CPU time 0.69 seconds
Started Jun 27 06:36:55 PM PDT 24
Finished Jun 27 06:37:00 PM PDT 24
Peak memory 206320 kb
Host smart-f2386ed5-2a7d-4b5b-823d-0117782a72b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2821944377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.2821944377
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.3428794222
Short name T14
Test name
Test status
Simulation time 3394654525 ps
CPU time 4.35 seconds
Started Jun 27 06:36:36 PM PDT 24
Finished Jun 27 06:36:45 PM PDT 24
Peak memory 206464 kb
Host smart-a4c7ccc6-7f01-4607-a67d-bb35f8f56338
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3428794222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.3428794222
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.492230048
Short name T1257
Test name
Test status
Simulation time 13375151587 ps
CPU time 11.99 seconds
Started Jun 27 06:36:37 PM PDT 24
Finished Jun 27 06:36:55 PM PDT 24
Peak memory 206352 kb
Host smart-268c9d9b-d5d0-4963-bfce-fabf4d401db2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=492230048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.492230048
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.2989040800
Short name T1933
Test name
Test status
Simulation time 23387006990 ps
CPU time 21.83 seconds
Started Jun 27 06:36:36 PM PDT 24
Finished Jun 27 06:37:02 PM PDT 24
Peak memory 206344 kb
Host smart-0a02b264-7e77-4cc7-8411-e1a2013cb75d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2989040800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.2989040800
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.3763714787
Short name T1817
Test name
Test status
Simulation time 181540709 ps
CPU time 0.82 seconds
Started Jun 27 06:36:38 PM PDT 24
Finished Jun 27 06:36:45 PM PDT 24
Peak memory 206280 kb
Host smart-572b207d-4c70-4255-9c4c-aaa8361b5fef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37637
14787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.3763714787
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.1930912226
Short name T499
Test name
Test status
Simulation time 170210929 ps
CPU time 0.78 seconds
Started Jun 27 06:36:37 PM PDT 24
Finished Jun 27 06:36:43 PM PDT 24
Peak memory 206276 kb
Host smart-6c168fa1-4e47-4aee-85b2-6dc5cf8d2894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19309
12226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.1930912226
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.2556812445
Short name T871
Test name
Test status
Simulation time 304006180 ps
CPU time 1.11 seconds
Started Jun 27 06:36:35 PM PDT 24
Finished Jun 27 06:36:40 PM PDT 24
Peak memory 206268 kb
Host smart-3079cfa9-57d2-4b98-b60c-d437429bc4a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25568
12445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.2556812445
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.2855323795
Short name T2388
Test name
Test status
Simulation time 1187577580 ps
CPU time 2.58 seconds
Started Jun 27 06:36:39 PM PDT 24
Finished Jun 27 06:36:47 PM PDT 24
Peak memory 206352 kb
Host smart-f735e4e7-d942-4520-be62-9c9aed7a9380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28553
23795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.2855323795
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.2733431588
Short name T187
Test name
Test status
Simulation time 18817352563 ps
CPU time 31.24 seconds
Started Jun 27 06:36:36 PM PDT 24
Finished Jun 27 06:37:11 PM PDT 24
Peak memory 206404 kb
Host smart-c9bef40d-727f-40f1-a385-1b4bf70d39aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27334
31588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.2733431588
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.1900266652
Short name T1431
Test name
Test status
Simulation time 390741368 ps
CPU time 1.16 seconds
Started Jun 27 06:36:35 PM PDT 24
Finished Jun 27 06:36:38 PM PDT 24
Peak memory 206300 kb
Host smart-80bff074-0ed6-452d-b33a-eab518c443ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19002
66652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.1900266652
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.1268717840
Short name T1193
Test name
Test status
Simulation time 153010057 ps
CPU time 0.8 seconds
Started Jun 27 06:36:41 PM PDT 24
Finished Jun 27 06:36:48 PM PDT 24
Peak memory 206444 kb
Host smart-b90f0ada-c684-4b64-83ea-97a7bdb0453d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12687
17840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.1268717840
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.3597199526
Short name T1342
Test name
Test status
Simulation time 40172087 ps
CPU time 0.68 seconds
Started Jun 27 06:36:38 PM PDT 24
Finished Jun 27 06:36:44 PM PDT 24
Peak memory 206176 kb
Host smart-6243988b-bec0-47aa-895d-f0e1bd659f3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35971
99526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.3597199526
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.2885801408
Short name T1129
Test name
Test status
Simulation time 879073603 ps
CPU time 2.14 seconds
Started Jun 27 06:36:40 PM PDT 24
Finished Jun 27 06:36:48 PM PDT 24
Peak memory 206568 kb
Host smart-0c951ee4-596f-46e9-83be-4879cc46309a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28858
01408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.2885801408
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.1652840045
Short name T1649
Test name
Test status
Simulation time 433098332 ps
CPU time 2.58 seconds
Started Jun 27 06:36:41 PM PDT 24
Finished Jun 27 06:36:50 PM PDT 24
Peak memory 206340 kb
Host smart-e0ad8da7-e2cc-4265-8c28-fc7ff9d7e337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16528
40045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.1652840045
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.884137867
Short name T437
Test name
Test status
Simulation time 135431481 ps
CPU time 0.75 seconds
Started Jun 27 06:36:37 PM PDT 24
Finished Jun 27 06:36:42 PM PDT 24
Peak memory 206292 kb
Host smart-ecc2126d-fe92-4ec9-a7a7-409b23fb6343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88413
7867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.884137867
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.1212751042
Short name T931
Test name
Test status
Simulation time 203883651 ps
CPU time 0.93 seconds
Started Jun 27 06:36:39 PM PDT 24
Finished Jun 27 06:36:46 PM PDT 24
Peak memory 206252 kb
Host smart-8b59b6ee-f43a-4d4b-ba05-df49f6ff181b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12127
51042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.1212751042
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.3414950424
Short name T2520
Test name
Test status
Simulation time 261002071 ps
CPU time 0.97 seconds
Started Jun 27 06:36:37 PM PDT 24
Finished Jun 27 06:36:44 PM PDT 24
Peak memory 206280 kb
Host smart-2501fbda-4ca4-44c8-ad5e-cab678b59989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34149
50424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.3414950424
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.1291566046
Short name T2081
Test name
Test status
Simulation time 23339193801 ps
CPU time 23.6 seconds
Started Jun 27 06:36:37 PM PDT 24
Finished Jun 27 06:37:05 PM PDT 24
Peak memory 206304 kb
Host smart-f78d5193-1df5-40df-b9bb-d77bbcadd249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12915
66046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.1291566046
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.3397141626
Short name T1757
Test name
Test status
Simulation time 3323060639 ps
CPU time 3.9 seconds
Started Jun 27 06:36:39 PM PDT 24
Finished Jun 27 06:36:49 PM PDT 24
Peak memory 206204 kb
Host smart-e6141c8b-def7-442c-8393-8c4143f8ce83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33971
41626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.3397141626
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.1233404848
Short name T2318
Test name
Test status
Simulation time 11071656267 ps
CPU time 289.57 seconds
Started Jun 27 06:36:41 PM PDT 24
Finished Jun 27 06:41:37 PM PDT 24
Peak memory 205752 kb
Host smart-8b8a74d8-0584-4c8c-81fe-311dcb525bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12334
04848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.1233404848
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.1724986573
Short name T1668
Test name
Test status
Simulation time 3179979976 ps
CPU time 85.56 seconds
Started Jun 27 06:36:39 PM PDT 24
Finished Jun 27 06:38:10 PM PDT 24
Peak memory 206312 kb
Host smart-4cc64651-49c3-421f-a81e-a59ee4a2e521
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1724986573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.1724986573
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.296369449
Short name T825
Test name
Test status
Simulation time 287135956 ps
CPU time 0.95 seconds
Started Jun 27 06:36:41 PM PDT 24
Finished Jun 27 06:36:48 PM PDT 24
Peak memory 206428 kb
Host smart-5970d0aa-68c9-4c70-971d-90847af2a928
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=296369449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.296369449
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.1127073235
Short name T992
Test name
Test status
Simulation time 184272913 ps
CPU time 0.83 seconds
Started Jun 27 06:36:41 PM PDT 24
Finished Jun 27 06:36:48 PM PDT 24
Peak memory 206276 kb
Host smart-fe7161c3-910b-4d2b-b78c-e11fa597d874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11270
73235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.1127073235
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.1160206881
Short name T1570
Test name
Test status
Simulation time 6168907458 ps
CPU time 56.7 seconds
Started Jun 27 06:36:41 PM PDT 24
Finished Jun 27 06:37:44 PM PDT 24
Peak memory 206424 kb
Host smart-51aa0682-3bcd-4d74-9c74-ad359555abbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11602
06881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.1160206881
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.856814727
Short name T2333
Test name
Test status
Simulation time 6664210684 ps
CPU time 191.56 seconds
Started Jun 27 06:36:40 PM PDT 24
Finished Jun 27 06:39:58 PM PDT 24
Peak memory 206544 kb
Host smart-acef6a4b-8f70-46b2-8294-31ea58cb1ed9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=856814727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.856814727
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.3746519623
Short name T2381
Test name
Test status
Simulation time 143966779 ps
CPU time 0.77 seconds
Started Jun 27 06:36:55 PM PDT 24
Finished Jun 27 06:37:01 PM PDT 24
Peak memory 206292 kb
Host smart-db5f046f-4af3-4795-bb96-194d930eeb22
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3746519623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.3746519623
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.2885351164
Short name T1377
Test name
Test status
Simulation time 186843230 ps
CPU time 0.89 seconds
Started Jun 27 06:36:55 PM PDT 24
Finished Jun 27 06:37:01 PM PDT 24
Peak memory 206436 kb
Host smart-7d3cd2de-da32-4c0e-8ddf-91e04910ad47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28853
51164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.2885351164
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.3485685758
Short name T2229
Test name
Test status
Simulation time 210644647 ps
CPU time 0.91 seconds
Started Jun 27 06:36:56 PM PDT 24
Finished Jun 27 06:37:03 PM PDT 24
Peak memory 206272 kb
Host smart-58b0e761-987e-4e2c-a995-e2d3100c5002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34856
85758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.3485685758
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.3936525504
Short name T1136
Test name
Test status
Simulation time 165962211 ps
CPU time 0.86 seconds
Started Jun 27 06:36:56 PM PDT 24
Finished Jun 27 06:37:03 PM PDT 24
Peak memory 206172 kb
Host smart-c146deeb-e7f1-4757-b6a4-e24e0170668b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39365
25504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.3936525504
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.1001507165
Short name T2326
Test name
Test status
Simulation time 170128268 ps
CPU time 0.81 seconds
Started Jun 27 06:36:52 PM PDT 24
Finished Jun 27 06:36:54 PM PDT 24
Peak memory 206272 kb
Host smart-fcfd3dc0-6ca5-4a73-b8ea-4be5bc3af4d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10015
07165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.1001507165
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.3609587966
Short name T2087
Test name
Test status
Simulation time 148325768 ps
CPU time 0.79 seconds
Started Jun 27 06:36:53 PM PDT 24
Finished Jun 27 06:36:56 PM PDT 24
Peak memory 206276 kb
Host smart-542d334e-1830-4149-b509-60119e18d97e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36095
87966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.3609587966
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.1111045018
Short name T2325
Test name
Test status
Simulation time 283033572 ps
CPU time 0.99 seconds
Started Jun 27 06:36:53 PM PDT 24
Finished Jun 27 06:36:57 PM PDT 24
Peak memory 206256 kb
Host smart-2819cfb8-715b-47df-bea7-b487d285700c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1111045018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.1111045018
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.3754874919
Short name T1003
Test name
Test status
Simulation time 175500470 ps
CPU time 0.79 seconds
Started Jun 27 06:36:52 PM PDT 24
Finished Jun 27 06:36:54 PM PDT 24
Peak memory 206244 kb
Host smart-de460805-2dec-45da-ba82-5fce5dc45c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37548
74919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.3754874919
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.3966717830
Short name T1850
Test name
Test status
Simulation time 53923788 ps
CPU time 0.67 seconds
Started Jun 27 06:36:59 PM PDT 24
Finished Jun 27 06:37:08 PM PDT 24
Peak memory 206264 kb
Host smart-6c4c02c7-6e47-4c40-b0b7-78d82654f508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39667
17830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.3966717830
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.3674892956
Short name T44
Test name
Test status
Simulation time 20564193392 ps
CPU time 44.53 seconds
Started Jun 27 06:37:01 PM PDT 24
Finished Jun 27 06:37:54 PM PDT 24
Peak memory 206464 kb
Host smart-a72d6efc-c478-4c6d-b596-9583656e1fcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36748
92956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.3674892956
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.3927959261
Short name T2182
Test name
Test status
Simulation time 149960889 ps
CPU time 0.78 seconds
Started Jun 27 06:36:53 PM PDT 24
Finished Jun 27 06:36:56 PM PDT 24
Peak memory 206272 kb
Host smart-b1f71c82-3fa5-496f-a36e-15f970192808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39279
59261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.3927959261
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.2401222320
Short name T1483
Test name
Test status
Simulation time 233683165 ps
CPU time 0.87 seconds
Started Jun 27 06:36:55 PM PDT 24
Finished Jun 27 06:37:01 PM PDT 24
Peak memory 206304 kb
Host smart-20db621c-9d4c-4465-a3da-7f7bf966d7f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24012
22320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.2401222320
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.1478851209
Short name T1959
Test name
Test status
Simulation time 284894470 ps
CPU time 0.94 seconds
Started Jun 27 06:36:54 PM PDT 24
Finished Jun 27 06:36:58 PM PDT 24
Peak memory 206304 kb
Host smart-6cb6a2fc-e53a-4424-a2e8-78a01566a26d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14788
51209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.1478851209
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.3077520913
Short name T1327
Test name
Test status
Simulation time 184006679 ps
CPU time 0.81 seconds
Started Jun 27 06:36:57 PM PDT 24
Finished Jun 27 06:37:05 PM PDT 24
Peak memory 206276 kb
Host smart-e2baf559-0b8e-4ce7-8404-fbe93b9d680e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30775
20913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.3077520913
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.357251343
Short name T1286
Test name
Test status
Simulation time 160350417 ps
CPU time 0.77 seconds
Started Jun 27 06:36:55 PM PDT 24
Finished Jun 27 06:37:00 PM PDT 24
Peak memory 206256 kb
Host smart-9991c091-92e2-47d0-ba25-2407830f2dcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35725
1343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.357251343
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.321803408
Short name T794
Test name
Test status
Simulation time 166726775 ps
CPU time 0.78 seconds
Started Jun 27 06:36:57 PM PDT 24
Finished Jun 27 06:37:04 PM PDT 24
Peak memory 206268 kb
Host smart-3d089b77-abc9-4eba-a2c4-de1024db96d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32180
3408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.321803408
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.3603084287
Short name T97
Test name
Test status
Simulation time 156386142 ps
CPU time 0.79 seconds
Started Jun 27 06:36:54 PM PDT 24
Finished Jun 27 06:36:59 PM PDT 24
Peak memory 206456 kb
Host smart-7c7aeb75-a5df-470d-a2d8-66f9398be1dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36030
84287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.3603084287
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.3877570649
Short name T2012
Test name
Test status
Simulation time 203253208 ps
CPU time 0.87 seconds
Started Jun 27 06:36:54 PM PDT 24
Finished Jun 27 06:36:59 PM PDT 24
Peak memory 206292 kb
Host smart-534c4473-cd03-4ad8-8a68-229318f6cc1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38775
70649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.3877570649
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.3728303046
Short name T1577
Test name
Test status
Simulation time 5461666830 ps
CPU time 39.57 seconds
Started Jun 27 06:37:02 PM PDT 24
Finished Jun 27 06:37:51 PM PDT 24
Peak memory 206396 kb
Host smart-47c4753f-1d13-4efe-a422-c39fdc7b477b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3728303046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.3728303046
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.618334542
Short name T881
Test name
Test status
Simulation time 191897890 ps
CPU time 0.83 seconds
Started Jun 27 06:36:52 PM PDT 24
Finished Jun 27 06:36:54 PM PDT 24
Peak memory 206272 kb
Host smart-2e1653ed-1e35-44c3-b783-aa9291828b44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61833
4542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.618334542
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.1567903689
Short name T371
Test name
Test status
Simulation time 179153540 ps
CPU time 0.81 seconds
Started Jun 27 06:36:55 PM PDT 24
Finished Jun 27 06:37:00 PM PDT 24
Peak memory 206272 kb
Host smart-ff7a87fb-62c5-43b2-b108-ef9056d424ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15679
03689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.1567903689
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.2969050285
Short name T2221
Test name
Test status
Simulation time 5057131624 ps
CPU time 139.59 seconds
Started Jun 27 06:36:55 PM PDT 24
Finished Jun 27 06:39:19 PM PDT 24
Peak memory 206412 kb
Host smart-8cabd600-652a-46a0-8b18-2771dfbb55c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29690
50285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.2969050285
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.1223250881
Short name T1045
Test name
Test status
Simulation time 93900464 ps
CPU time 0.71 seconds
Started Jun 27 06:36:54 PM PDT 24
Finished Jun 27 06:36:57 PM PDT 24
Peak memory 206352 kb
Host smart-6ff7a0f8-0fbe-4dbb-a4c0-cfb9d74194bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1223250881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.1223250881
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.560297804
Short name T2415
Test name
Test status
Simulation time 4275333315 ps
CPU time 4.66 seconds
Started Jun 27 06:36:56 PM PDT 24
Finished Jun 27 06:37:06 PM PDT 24
Peak memory 206360 kb
Host smart-c1cc11b4-a23a-4f58-88aa-bd77bd3850c1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=560297804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.560297804
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.3285886494
Short name T917
Test name
Test status
Simulation time 13328366199 ps
CPU time 15.3 seconds
Started Jun 27 06:36:53 PM PDT 24
Finished Jun 27 06:37:10 PM PDT 24
Peak memory 206472 kb
Host smart-e42c1940-845c-40ad-9e71-4f1ab90ec460
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3285886494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.3285886494
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.3716497415
Short name T433
Test name
Test status
Simulation time 23430065151 ps
CPU time 23.02 seconds
Started Jun 27 06:36:58 PM PDT 24
Finished Jun 27 06:37:29 PM PDT 24
Peak memory 206024 kb
Host smart-a3190106-4bc6-4346-b121-8fa9a26e5d0b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3716497415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.3716497415
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.1257646112
Short name T1778
Test name
Test status
Simulation time 181294500 ps
CPU time 0.78 seconds
Started Jun 27 06:36:58 PM PDT 24
Finished Jun 27 06:37:06 PM PDT 24
Peak memory 206056 kb
Host smart-37501065-88ac-4c43-8898-b7a19bc0fc13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12576
46112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.1257646112
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.2229292606
Short name T1528
Test name
Test status
Simulation time 152487999 ps
CPU time 0.76 seconds
Started Jun 27 06:36:59 PM PDT 24
Finished Jun 27 06:37:09 PM PDT 24
Peak memory 206280 kb
Host smart-81654bab-5aab-40d2-bd05-0ad8a99175f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22292
92606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.2229292606
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.619070273
Short name T175
Test name
Test status
Simulation time 539449562 ps
CPU time 1.58 seconds
Started Jun 27 06:36:55 PM PDT 24
Finished Jun 27 06:37:00 PM PDT 24
Peak memory 206316 kb
Host smart-c1980c4f-424c-4d5f-b128-0369adb90553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61907
0273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.619070273
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.2060491319
Short name T1963
Test name
Test status
Simulation time 953438399 ps
CPU time 2.28 seconds
Started Jun 27 06:36:57 PM PDT 24
Finished Jun 27 06:37:07 PM PDT 24
Peak memory 206448 kb
Host smart-ee82c6d2-80dc-434a-b975-2bea6271505c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20604
91319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.2060491319
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.508274853
Short name T2396
Test name
Test status
Simulation time 9855455609 ps
CPU time 16.97 seconds
Started Jun 27 06:36:57 PM PDT 24
Finished Jun 27 06:37:21 PM PDT 24
Peak memory 206456 kb
Host smart-235e62fb-4c39-4e78-b52f-93cea4e464d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50827
4853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.508274853
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.1221534163
Short name T2456
Test name
Test status
Simulation time 348231173 ps
CPU time 1.16 seconds
Started Jun 27 06:36:54 PM PDT 24
Finished Jun 27 06:36:59 PM PDT 24
Peak memory 206268 kb
Host smart-2963ca89-b94e-4512-ba0b-2265f2db08cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12215
34163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.1221534163
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.2257996266
Short name T974
Test name
Test status
Simulation time 165928028 ps
CPU time 0.78 seconds
Started Jun 27 06:36:56 PM PDT 24
Finished Jun 27 06:37:04 PM PDT 24
Peak memory 206272 kb
Host smart-fb7b41df-954c-4b39-b051-ac4774a964ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22579
96266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.2257996266
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.280720825
Short name T1683
Test name
Test status
Simulation time 62003548 ps
CPU time 0.66 seconds
Started Jun 27 06:37:39 PM PDT 24
Finished Jun 27 06:37:40 PM PDT 24
Peak memory 206252 kb
Host smart-6b07be0a-928b-4f96-a33f-c7c83fbe0002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28072
0825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.280720825
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.1291176398
Short name T1651
Test name
Test status
Simulation time 714122014 ps
CPU time 1.81 seconds
Started Jun 27 06:36:57 PM PDT 24
Finished Jun 27 06:37:06 PM PDT 24
Peak memory 206436 kb
Host smart-300ecf47-cd17-4fe8-b0fa-a81e7fdefe3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12911
76398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.1291176398
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.1023747372
Short name T1730
Test name
Test status
Simulation time 345533306 ps
CPU time 2.09 seconds
Started Jun 27 06:36:58 PM PDT 24
Finished Jun 27 06:37:08 PM PDT 24
Peak memory 206296 kb
Host smart-7b61038c-d111-478b-ac6c-baba0b869640
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10237
47372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.1023747372
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.1171782092
Short name T1439
Test name
Test status
Simulation time 231155478 ps
CPU time 0.88 seconds
Started Jun 27 06:36:59 PM PDT 24
Finished Jun 27 06:37:09 PM PDT 24
Peak memory 206272 kb
Host smart-43b4e2c5-dd79-45b3-ab05-e44dd7306934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11717
82092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.1171782092
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.2569392909
Short name T971
Test name
Test status
Simulation time 153141752 ps
CPU time 0.74 seconds
Started Jun 27 06:36:58 PM PDT 24
Finished Jun 27 06:37:07 PM PDT 24
Peak memory 205672 kb
Host smart-e8566894-eed4-41dc-afb9-b2b73a1b4a5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25693
92909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.2569392909
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.2688903003
Short name T1419
Test name
Test status
Simulation time 157261216 ps
CPU time 0.82 seconds
Started Jun 27 06:36:58 PM PDT 24
Finished Jun 27 06:37:07 PM PDT 24
Peak memory 206280 kb
Host smart-79f11373-0188-4a33-8e7e-2f4699f3464b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26889
03003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.2688903003
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.162868557
Short name T560
Test name
Test status
Simulation time 217103722 ps
CPU time 0.91 seconds
Started Jun 27 06:36:56 PM PDT 24
Finished Jun 27 06:37:03 PM PDT 24
Peak memory 206264 kb
Host smart-336ee620-3762-4aa5-8989-122d3f722dbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16286
8557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.162868557
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.3335926544
Short name T1776
Test name
Test status
Simulation time 23309205000 ps
CPU time 21.79 seconds
Started Jun 27 06:36:58 PM PDT 24
Finished Jun 27 06:37:27 PM PDT 24
Peak memory 206324 kb
Host smart-1815226c-e064-4969-b468-8987650b437d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33359
26544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.3335926544
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.3759939540
Short name T2300
Test name
Test status
Simulation time 3339399290 ps
CPU time 3.87 seconds
Started Jun 27 06:36:59 PM PDT 24
Finished Jun 27 06:37:11 PM PDT 24
Peak memory 206340 kb
Host smart-1b8aab1b-5ebf-49a2-b2cf-155904a827d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37599
39540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.3759939540
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.2990622434
Short name T729
Test name
Test status
Simulation time 12340835364 ps
CPU time 117.39 seconds
Started Jun 27 06:36:59 PM PDT 24
Finished Jun 27 06:39:05 PM PDT 24
Peak memory 206476 kb
Host smart-351f77ec-8e09-4ba3-977a-e4671e18d594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29906
22434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.2990622434
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.433830895
Short name T1900
Test name
Test status
Simulation time 5882222923 ps
CPU time 55.19 seconds
Started Jun 27 06:36:59 PM PDT 24
Finished Jun 27 06:38:02 PM PDT 24
Peak memory 206488 kb
Host smart-f767f44b-7195-4d15-a06a-65744e4972c1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=433830895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.433830895
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.2547227617
Short name T1587
Test name
Test status
Simulation time 262868459 ps
CPU time 0.88 seconds
Started Jun 27 06:36:56 PM PDT 24
Finished Jun 27 06:37:03 PM PDT 24
Peak memory 206228 kb
Host smart-f73f1487-2476-45e9-8a36-babb926a43ae
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2547227617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.2547227617
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.583657028
Short name T1279
Test name
Test status
Simulation time 207585861 ps
CPU time 0.84 seconds
Started Jun 27 06:37:00 PM PDT 24
Finished Jun 27 06:37:10 PM PDT 24
Peak memory 206284 kb
Host smart-38a4f7e5-6345-48c3-9599-e8aca7e9c068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58365
7028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.583657028
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.6574775
Short name T2346
Test name
Test status
Simulation time 4061743255 ps
CPU time 111.05 seconds
Started Jun 27 06:37:00 PM PDT 24
Finished Jun 27 06:39:00 PM PDT 24
Peak memory 206420 kb
Host smart-8d5d8cee-291d-4002-90ce-909d95f0c424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65747
75 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.6574775
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.793345732
Short name T1044
Test name
Test status
Simulation time 4546226621 ps
CPU time 123.23 seconds
Started Jun 27 06:36:59 PM PDT 24
Finished Jun 27 06:39:11 PM PDT 24
Peak memory 206436 kb
Host smart-0c8e6ac5-096f-46bb-a2f3-3145e07fc3fd
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=793345732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.793345732
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.2016165413
Short name T1891
Test name
Test status
Simulation time 163054481 ps
CPU time 0.81 seconds
Started Jun 27 06:37:03 PM PDT 24
Finished Jun 27 06:37:13 PM PDT 24
Peak memory 206280 kb
Host smart-6653c4fa-6b08-4398-bda2-8a7ca5545166
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2016165413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.2016165413
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.1980121036
Short name T447
Test name
Test status
Simulation time 167679713 ps
CPU time 0.81 seconds
Started Jun 27 06:36:58 PM PDT 24
Finished Jun 27 06:37:07 PM PDT 24
Peak memory 206284 kb
Host smart-01de59e1-26c4-4b1e-90fb-f56c637e4c27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19801
21036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.1980121036
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.634517682
Short name T850
Test name
Test status
Simulation time 162988098 ps
CPU time 0.77 seconds
Started Jun 27 06:37:04 PM PDT 24
Finished Jun 27 06:37:14 PM PDT 24
Peak memory 206304 kb
Host smart-2ad6556b-0e22-4715-9004-1ace1fc78995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63451
7682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.634517682
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.2016671887
Short name T2353
Test name
Test status
Simulation time 197087976 ps
CPU time 0.83 seconds
Started Jun 27 06:36:59 PM PDT 24
Finished Jun 27 06:37:07 PM PDT 24
Peak memory 206264 kb
Host smart-5d4d9a84-cd7c-44af-8c4e-2dd18ae78e6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20166
71887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.2016671887
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.478366306
Short name T346
Test name
Test status
Simulation time 191061701 ps
CPU time 0.8 seconds
Started Jun 27 06:37:03 PM PDT 24
Finished Jun 27 06:37:13 PM PDT 24
Peak memory 206196 kb
Host smart-635431a2-388a-48c5-83b9-f20d55580c53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47836
6306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.478366306
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.2468701061
Short name T2524
Test name
Test status
Simulation time 147101772 ps
CPU time 0.74 seconds
Started Jun 27 06:36:59 PM PDT 24
Finished Jun 27 06:37:08 PM PDT 24
Peak memory 206260 kb
Host smart-8e1dea88-0e88-4dcc-a827-a70e934d8e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24687
01061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.2468701061
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.2887881045
Short name T862
Test name
Test status
Simulation time 211093883 ps
CPU time 0.89 seconds
Started Jun 27 06:36:59 PM PDT 24
Finished Jun 27 06:37:07 PM PDT 24
Peak memory 206280 kb
Host smart-d8d589ba-5ed6-42c0-a0fd-0aac6a3b169f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2887881045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.2887881045
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.1155622503
Short name T2098
Test name
Test status
Simulation time 192471597 ps
CPU time 0.81 seconds
Started Jun 27 06:37:04 PM PDT 24
Finished Jun 27 06:37:14 PM PDT 24
Peak memory 206288 kb
Host smart-9981f695-9b30-4dd3-a96c-c0935e259381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11556
22503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.1155622503
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.3938615359
Short name T1909
Test name
Test status
Simulation time 34549084 ps
CPU time 0.65 seconds
Started Jun 27 06:37:02 PM PDT 24
Finished Jun 27 06:37:12 PM PDT 24
Peak memory 206256 kb
Host smart-a8cf47c1-7466-4277-82b7-93e35130db2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39386
15359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.3938615359
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.1093680619
Short name T1658
Test name
Test status
Simulation time 17275301058 ps
CPU time 40.53 seconds
Started Jun 27 06:37:05 PM PDT 24
Finished Jun 27 06:37:54 PM PDT 24
Peak memory 206536 kb
Host smart-8cf4e5f7-1ef8-4acc-8232-2100c8899388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10936
80619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.1093680619
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.2370890561
Short name T2513
Test name
Test status
Simulation time 191896673 ps
CPU time 0.83 seconds
Started Jun 27 06:36:59 PM PDT 24
Finished Jun 27 06:37:07 PM PDT 24
Peak memory 206256 kb
Host smart-256d6ca0-b32d-4805-a931-54e2aa60216b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23708
90561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.2370890561
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.1785034715
Short name T2592
Test name
Test status
Simulation time 240612621 ps
CPU time 0.89 seconds
Started Jun 27 06:37:02 PM PDT 24
Finished Jun 27 06:37:12 PM PDT 24
Peak memory 206288 kb
Host smart-631d9855-e744-4d7e-bd75-89c8cb19a5b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17850
34715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.1785034715
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.1358157475
Short name T2176
Test name
Test status
Simulation time 206969311 ps
CPU time 0.82 seconds
Started Jun 27 06:37:03 PM PDT 24
Finished Jun 27 06:37:13 PM PDT 24
Peak memory 206212 kb
Host smart-9c547e96-a46d-4dff-83a5-352818a37fd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13581
57475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.1358157475
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.67694212
Short name T653
Test name
Test status
Simulation time 247713549 ps
CPU time 0.92 seconds
Started Jun 27 06:37:04 PM PDT 24
Finished Jun 27 06:37:14 PM PDT 24
Peak memory 206288 kb
Host smart-fd5b4a13-b58a-438b-8ac4-0b10e4691124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67694
212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.67694212
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.3440977634
Short name T1559
Test name
Test status
Simulation time 196241749 ps
CPU time 0.83 seconds
Started Jun 27 06:36:57 PM PDT 24
Finished Jun 27 06:37:05 PM PDT 24
Peak memory 206276 kb
Host smart-947591ab-d581-48b3-b752-af7bca44c1f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34409
77634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.3440977634
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.1812505338
Short name T1882
Test name
Test status
Simulation time 180637390 ps
CPU time 0.82 seconds
Started Jun 27 06:36:57 PM PDT 24
Finished Jun 27 06:37:04 PM PDT 24
Peak memory 206280 kb
Host smart-f7e89961-9970-4bfa-9d29-6c66957a5b4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18125
05338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.1812505338
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.1574132701
Short name T386
Test name
Test status
Simulation time 150538283 ps
CPU time 0.78 seconds
Started Jun 27 06:37:01 PM PDT 24
Finished Jun 27 06:37:10 PM PDT 24
Peak memory 206292 kb
Host smart-d42395df-8a85-4bba-8385-a73e09a1bb51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15741
32701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.1574132701
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.1061569248
Short name T965
Test name
Test status
Simulation time 225264896 ps
CPU time 0.95 seconds
Started Jun 27 06:37:04 PM PDT 24
Finished Jun 27 06:37:14 PM PDT 24
Peak memory 206304 kb
Host smart-9781fe3c-7ac0-4062-9791-ed9768db3f5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10615
69248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.1061569248
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.1076077525
Short name T1470
Test name
Test status
Simulation time 5121468142 ps
CPU time 135.62 seconds
Started Jun 27 06:37:00 PM PDT 24
Finished Jun 27 06:39:25 PM PDT 24
Peak memory 206436 kb
Host smart-f80ff353-054d-4117-85f7-8ba356eed21c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1076077525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.1076077525
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.2604584773
Short name T932
Test name
Test status
Simulation time 189728857 ps
CPU time 0.83 seconds
Started Jun 27 06:36:56 PM PDT 24
Finished Jun 27 06:37:04 PM PDT 24
Peak memory 206300 kb
Host smart-361ddc00-748c-49b2-82cc-f7cbbfbb2cb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26045
84773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.2604584773
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.91435013
Short name T1605
Test name
Test status
Simulation time 154806627 ps
CPU time 0.81 seconds
Started Jun 27 06:36:53 PM PDT 24
Finished Jun 27 06:36:56 PM PDT 24
Peak memory 206268 kb
Host smart-ed8bc8d7-8160-461e-9603-547edec8c778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91435
013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.91435013
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.4242403150
Short name T2401
Test name
Test status
Simulation time 3123775936 ps
CPU time 28.9 seconds
Started Jun 27 06:36:52 PM PDT 24
Finished Jun 27 06:37:23 PM PDT 24
Peak memory 206396 kb
Host smart-a5278eda-ed1b-4443-8663-071b39bfacd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42424
03150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.4242403150
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.1642789538
Short name T2474
Test name
Test status
Simulation time 3716099110 ps
CPU time 4.65 seconds
Started Jun 27 06:36:54 PM PDT 24
Finished Jun 27 06:37:03 PM PDT 24
Peak memory 206436 kb
Host smart-3972a3a3-cc55-49b4-b4bb-0bdc4e31599d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1642789538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.1642789538
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.175430222
Short name T1479
Test name
Test status
Simulation time 13353763070 ps
CPU time 14.53 seconds
Started Jun 27 06:36:56 PM PDT 24
Finished Jun 27 06:37:18 PM PDT 24
Peak memory 206480 kb
Host smart-f9468b43-51f1-4c3f-bcf8-733603736c54
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=175430222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.175430222
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.1971393925
Short name T1515
Test name
Test status
Simulation time 23361056273 ps
CPU time 22.36 seconds
Started Jun 27 06:36:59 PM PDT 24
Finished Jun 27 06:37:29 PM PDT 24
Peak memory 206336 kb
Host smart-bbe5902c-ccff-4960-b0c5-a7e997b85deb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1971393925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.1971393925
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.1124450183
Short name T2550
Test name
Test status
Simulation time 156906723 ps
CPU time 0.82 seconds
Started Jun 27 06:36:56 PM PDT 24
Finished Jun 27 06:37:03 PM PDT 24
Peak memory 206176 kb
Host smart-4a5bee6d-73ff-42ed-b8a8-1656a1920e7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11244
50183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.1124450183
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.471833605
Short name T2428
Test name
Test status
Simulation time 150191871 ps
CPU time 0.73 seconds
Started Jun 27 06:37:01 PM PDT 24
Finished Jun 27 06:37:10 PM PDT 24
Peak memory 206304 kb
Host smart-e46107da-9677-4774-9b39-4712b882f340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47183
3605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.471833605
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.2874018456
Short name T956
Test name
Test status
Simulation time 375745486 ps
CPU time 1.26 seconds
Started Jun 27 06:36:54 PM PDT 24
Finished Jun 27 06:36:58 PM PDT 24
Peak memory 206264 kb
Host smart-db91e6e0-1866-41d0-85e7-ddf61f21af25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28740
18456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.2874018456
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.3049392032
Short name T924
Test name
Test status
Simulation time 326125033 ps
CPU time 1.06 seconds
Started Jun 27 06:36:56 PM PDT 24
Finished Jun 27 06:37:03 PM PDT 24
Peak memory 206288 kb
Host smart-fbd1a8e2-e804-4ab8-a704-f09f696b1af7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30493
92032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.3049392032
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.2938133622
Short name T524
Test name
Test status
Simulation time 21584796937 ps
CPU time 38.38 seconds
Started Jun 27 06:36:57 PM PDT 24
Finished Jun 27 06:37:41 PM PDT 24
Peak memory 206468 kb
Host smart-de50f3e4-af60-4b5d-9eed-9b6a93175595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29381
33622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.2938133622
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.2919882189
Short name T1787
Test name
Test status
Simulation time 356617651 ps
CPU time 1.09 seconds
Started Jun 27 06:36:57 PM PDT 24
Finished Jun 27 06:37:04 PM PDT 24
Peak memory 206252 kb
Host smart-3bc7532b-d83a-4c2d-bdd0-be1b3baff084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29198
82189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.2919882189
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.1733025127
Short name T2490
Test name
Test status
Simulation time 154340550 ps
CPU time 0.77 seconds
Started Jun 27 06:36:57 PM PDT 24
Finished Jun 27 06:37:04 PM PDT 24
Peak memory 206252 kb
Host smart-bf9a634d-5fcc-490a-8be5-8c154e56ec23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17330
25127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.1733025127
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.410456087
Short name T1964
Test name
Test status
Simulation time 64505931 ps
CPU time 0.7 seconds
Started Jun 27 06:37:02 PM PDT 24
Finished Jun 27 06:37:12 PM PDT 24
Peak memory 206312 kb
Host smart-46d9ef60-8e8f-4ade-95d2-dcfce265c8ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41045
6087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.410456087
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.1206060715
Short name T1589
Test name
Test status
Simulation time 751168947 ps
CPU time 1.73 seconds
Started Jun 27 06:36:53 PM PDT 24
Finished Jun 27 06:36:58 PM PDT 24
Peak memory 206348 kb
Host smart-c4da0f27-fa62-4d9c-8377-e47cddffbf36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12060
60715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.1206060715
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.2683316729
Short name T81
Test name
Test status
Simulation time 178613349 ps
CPU time 1.79 seconds
Started Jun 27 06:36:59 PM PDT 24
Finished Jun 27 06:37:08 PM PDT 24
Peak memory 206348 kb
Host smart-d6e05553-f7a9-4995-9eb3-1a220c9b0907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26833
16729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.2683316729
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.2135324119
Short name T108
Test name
Test status
Simulation time 233684448 ps
CPU time 0.85 seconds
Started Jun 27 06:36:59 PM PDT 24
Finished Jun 27 06:37:08 PM PDT 24
Peak memory 206284 kb
Host smart-d134a605-b22f-4041-aed0-7ee4cb697804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21353
24119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.2135324119
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.4189469316
Short name T2370
Test name
Test status
Simulation time 146233955 ps
CPU time 0.74 seconds
Started Jun 27 06:36:54 PM PDT 24
Finished Jun 27 06:36:59 PM PDT 24
Peak memory 206288 kb
Host smart-b94e7320-bbe7-40e2-9901-6ad5bd5da40c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41894
69316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.4189469316
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.2652864734
Short name T332
Test name
Test status
Simulation time 195331840 ps
CPU time 0.87 seconds
Started Jun 27 06:37:00 PM PDT 24
Finished Jun 27 06:37:10 PM PDT 24
Peak memory 206272 kb
Host smart-21db761b-617d-4851-bb97-a7a96b6dcb8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26528
64734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.2652864734
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.3612285813
Short name T1411
Test name
Test status
Simulation time 254381473 ps
CPU time 0.92 seconds
Started Jun 27 06:37:11 PM PDT 24
Finished Jun 27 06:37:18 PM PDT 24
Peak memory 206280 kb
Host smart-5cc79883-2a88-4f25-ad3e-9db043f25b1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36122
85813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.3612285813
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.1617468094
Short name T2376
Test name
Test status
Simulation time 23318173471 ps
CPU time 23.47 seconds
Started Jun 27 06:37:00 PM PDT 24
Finished Jun 27 06:37:32 PM PDT 24
Peak memory 206316 kb
Host smart-0a5cde1b-e130-4b6b-ae77-002508aa191c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16174
68094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.1617468094
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.1938954080
Short name T2342
Test name
Test status
Simulation time 3352035211 ps
CPU time 3.78 seconds
Started Jun 27 06:36:57 PM PDT 24
Finished Jun 27 06:37:08 PM PDT 24
Peak memory 206364 kb
Host smart-ebd8ae6c-34b4-4d78-9f80-dc7b2479511f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19389
54080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.1938954080
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.3854843260
Short name T1510
Test name
Test status
Simulation time 10086652931 ps
CPU time 270.38 seconds
Started Jun 27 06:36:56 PM PDT 24
Finished Jun 27 06:41:33 PM PDT 24
Peak memory 206336 kb
Host smart-0e86444e-2176-46cf-bf3d-b2534b213b1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38548
43260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.3854843260
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.2757599052
Short name T2083
Test name
Test status
Simulation time 5773476924 ps
CPU time 158.96 seconds
Started Jun 27 06:37:00 PM PDT 24
Finished Jun 27 06:39:47 PM PDT 24
Peak memory 206440 kb
Host smart-d4b39fdc-aa33-4c7d-88c3-828bba0a07ce
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2757599052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.2757599052
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.3133047230
Short name T449
Test name
Test status
Simulation time 240781809 ps
CPU time 0.88 seconds
Started Jun 27 06:36:59 PM PDT 24
Finished Jun 27 06:37:09 PM PDT 24
Peak memory 206276 kb
Host smart-8e9223c7-774a-408e-8adb-fb996137f1ca
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3133047230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.3133047230
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.3131605046
Short name T1873
Test name
Test status
Simulation time 190758602 ps
CPU time 0.86 seconds
Started Jun 27 06:36:56 PM PDT 24
Finished Jun 27 06:37:04 PM PDT 24
Peak memory 206132 kb
Host smart-8ebbf1fb-5998-4e7c-84de-3ab95241729d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31316
05046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.3131605046
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.1215618484
Short name T1085
Test name
Test status
Simulation time 7123875758 ps
CPU time 64.93 seconds
Started Jun 27 06:37:01 PM PDT 24
Finished Jun 27 06:38:15 PM PDT 24
Peak memory 206484 kb
Host smart-a3155153-7f11-448b-a7d6-c481890888e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12156
18484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.1215618484
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.3857235290
Short name T1795
Test name
Test status
Simulation time 3310797461 ps
CPU time 90.67 seconds
Started Jun 27 06:37:00 PM PDT 24
Finished Jun 27 06:38:39 PM PDT 24
Peak memory 206308 kb
Host smart-550f17ac-5c91-4360-8955-5c6711486d20
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3857235290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.3857235290
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.2139583404
Short name T253
Test name
Test status
Simulation time 164860607 ps
CPU time 0.79 seconds
Started Jun 27 06:37:02 PM PDT 24
Finished Jun 27 06:37:12 PM PDT 24
Peak memory 206296 kb
Host smart-e66ca979-db4c-423c-b004-bd77efdd31d9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2139583404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.2139583404
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.2190826505
Short name T2005
Test name
Test status
Simulation time 189273252 ps
CPU time 0.85 seconds
Started Jun 27 06:37:00 PM PDT 24
Finished Jun 27 06:37:10 PM PDT 24
Peak memory 206136 kb
Host smart-551dc5b7-8b9a-40df-bc47-b7701636aa55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21908
26505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.2190826505
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.2109487242
Short name T2618
Test name
Test status
Simulation time 144190595 ps
CPU time 0.74 seconds
Started Jun 27 06:36:59 PM PDT 24
Finished Jun 27 06:37:07 PM PDT 24
Peak memory 206296 kb
Host smart-813f1ea4-7e4d-4d70-b178-74c9a31cd8e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21094
87242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.2109487242
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.3911481840
Short name T2324
Test name
Test status
Simulation time 218153516 ps
CPU time 0.86 seconds
Started Jun 27 06:36:52 PM PDT 24
Finished Jun 27 06:36:55 PM PDT 24
Peak memory 206280 kb
Host smart-fc5b66e1-0a2d-4580-a302-bb02dd105213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39114
81840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.3911481840
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.1984894973
Short name T2015
Test name
Test status
Simulation time 173472646 ps
CPU time 0.77 seconds
Started Jun 27 06:36:55 PM PDT 24
Finished Jun 27 06:37:00 PM PDT 24
Peak memory 206276 kb
Host smart-7475d368-9209-4618-a815-fb9c1097bf72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19848
94973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.1984894973
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.1800957291
Short name T2488
Test name
Test status
Simulation time 155515572 ps
CPU time 0.78 seconds
Started Jun 27 06:37:02 PM PDT 24
Finished Jun 27 06:37:12 PM PDT 24
Peak memory 206260 kb
Host smart-7b9deb9b-4275-41e2-be9c-088a08b57189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18009
57291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.1800957291
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.3662107265
Short name T1292
Test name
Test status
Simulation time 239318377 ps
CPU time 0.94 seconds
Started Jun 27 06:36:54 PM PDT 24
Finished Jun 27 06:36:58 PM PDT 24
Peak memory 206308 kb
Host smart-a37dbb12-31fb-4e7b-995a-9629f7c4d6f2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3662107265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.3662107265
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.2823929046
Short name T1284
Test name
Test status
Simulation time 161100338 ps
CPU time 0.74 seconds
Started Jun 27 06:36:58 PM PDT 24
Finished Jun 27 06:37:07 PM PDT 24
Peak memory 206272 kb
Host smart-c30daa25-9ebd-46fc-8f38-05c0a6d64151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28239
29046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.2823929046
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.1610558067
Short name T968
Test name
Test status
Simulation time 79571801 ps
CPU time 0.69 seconds
Started Jun 27 06:36:58 PM PDT 24
Finished Jun 27 06:37:07 PM PDT 24
Peak memory 205680 kb
Host smart-dec452b8-4470-4f4c-b8ff-b1b4fa844791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16105
58067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.1610558067
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.3581365072
Short name T708
Test name
Test status
Simulation time 12534691636 ps
CPU time 25.99 seconds
Started Jun 27 06:36:58 PM PDT 24
Finished Jun 27 06:37:32 PM PDT 24
Peak memory 206256 kb
Host smart-94d043f9-a265-4268-a05e-2abe14e36c10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35813
65072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.3581365072
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.1246702997
Short name T1324
Test name
Test status
Simulation time 184120100 ps
CPU time 0.83 seconds
Started Jun 27 06:36:54 PM PDT 24
Finished Jun 27 06:36:59 PM PDT 24
Peak memory 206268 kb
Host smart-efad2bbe-ca40-4792-b6bd-cea9aac13ab8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12467
02997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.1246702997
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.819453272
Short name T1082
Test name
Test status
Simulation time 192829381 ps
CPU time 0.83 seconds
Started Jun 27 06:36:52 PM PDT 24
Finished Jun 27 06:36:54 PM PDT 24
Peak memory 206280 kb
Host smart-a3c49410-2bf8-4a7e-beda-7dded68bc0d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81945
3272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.819453272
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.1556555200
Short name T2521
Test name
Test status
Simulation time 159311885 ps
CPU time 0.78 seconds
Started Jun 27 06:36:56 PM PDT 24
Finished Jun 27 06:37:03 PM PDT 24
Peak memory 206288 kb
Host smart-1726f864-e56e-425f-af29-010f66515914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15565
55200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.1556555200
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.3837230163
Short name T577
Test name
Test status
Simulation time 176812463 ps
CPU time 0.84 seconds
Started Jun 27 06:36:52 PM PDT 24
Finished Jun 27 06:36:55 PM PDT 24
Peak memory 206248 kb
Host smart-69fb2b95-7ad2-4df4-b72e-fee1bdf9f0e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38372
30163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.3837230163
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.886775604
Short name T1512
Test name
Test status
Simulation time 145414497 ps
CPU time 0.74 seconds
Started Jun 27 06:36:55 PM PDT 24
Finished Jun 27 06:37:01 PM PDT 24
Peak memory 206284 kb
Host smart-529f269f-49b9-4f75-bfa9-ccfbbd59ff6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88677
5604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.886775604
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.304836674
Short name T522
Test name
Test status
Simulation time 155298655 ps
CPU time 0.78 seconds
Started Jun 27 06:36:53 PM PDT 24
Finished Jun 27 06:36:56 PM PDT 24
Peak memory 206248 kb
Host smart-996e990c-e42a-4e67-be80-9286da5a1bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30483
6674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.304836674
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.454629025
Short name T2507
Test name
Test status
Simulation time 148855813 ps
CPU time 0.78 seconds
Started Jun 27 06:36:55 PM PDT 24
Finished Jun 27 06:37:00 PM PDT 24
Peak memory 206288 kb
Host smart-9c0a8257-0629-489c-8872-9ffadf688a03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45462
9025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.454629025
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.1047380761
Short name T2455
Test name
Test status
Simulation time 273911486 ps
CPU time 0.95 seconds
Started Jun 27 06:36:56 PM PDT 24
Finished Jun 27 06:37:02 PM PDT 24
Peak memory 206280 kb
Host smart-151d31a9-b817-47d2-ba0d-26a014c646ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10473
80761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.1047380761
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.1614787618
Short name T1421
Test name
Test status
Simulation time 5604994246 ps
CPU time 160.08 seconds
Started Jun 27 06:36:54 PM PDT 24
Finished Jun 27 06:39:37 PM PDT 24
Peak memory 206456 kb
Host smart-c21c8f08-2187-4770-980a-2563d9dd7685
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1614787618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.1614787618
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.3704596818
Short name T339
Test name
Test status
Simulation time 192169872 ps
CPU time 0.84 seconds
Started Jun 27 06:37:00 PM PDT 24
Finished Jun 27 06:37:10 PM PDT 24
Peak memory 206284 kb
Host smart-ab11b31c-f621-401a-a9bb-ff5759ab52e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37045
96818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.3704596818
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.229359635
Short name T1438
Test name
Test status
Simulation time 191265948 ps
CPU time 0.81 seconds
Started Jun 27 06:36:55 PM PDT 24
Finished Jun 27 06:37:01 PM PDT 24
Peak memory 206276 kb
Host smart-d147f47d-a895-4945-ab10-909f48d658d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22935
9635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.229359635
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.2202077587
Short name T1145
Test name
Test status
Simulation time 6630395350 ps
CPU time 62.45 seconds
Started Jun 27 06:36:57 PM PDT 24
Finished Jun 27 06:38:06 PM PDT 24
Peak memory 206448 kb
Host smart-1bf5047a-4ff6-4ab9-8692-b123aecad6b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22020
77587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.2202077587
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.3808104888
Short name T868
Test name
Test status
Simulation time 42740626 ps
CPU time 0.65 seconds
Started Jun 27 06:37:20 PM PDT 24
Finished Jun 27 06:37:28 PM PDT 24
Peak memory 206304 kb
Host smart-2309817b-1ba7-4996-a53a-f3d20ea12600
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3808104888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.3808104888
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.2151130547
Short name T368
Test name
Test status
Simulation time 3810148321 ps
CPU time 4.32 seconds
Started Jun 27 06:36:56 PM PDT 24
Finished Jun 27 06:37:05 PM PDT 24
Peak memory 206360 kb
Host smart-9394313f-1f6b-4433-aef6-8b4571774869
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2151130547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.2151130547
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.3316902047
Short name T1536
Test name
Test status
Simulation time 13327176517 ps
CPU time 15.25 seconds
Started Jun 27 06:37:02 PM PDT 24
Finished Jun 27 06:37:26 PM PDT 24
Peak memory 206396 kb
Host smart-8d30b278-368e-4533-9008-0f3030cd2bc6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3316902047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.3316902047
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.3744057695
Short name T2234
Test name
Test status
Simulation time 23392936541 ps
CPU time 23.55 seconds
Started Jun 27 06:37:01 PM PDT 24
Finished Jun 27 06:37:34 PM PDT 24
Peak memory 206368 kb
Host smart-c5de1222-b8a7-42ed-9c46-4a95e8aeffca
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3744057695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.3744057695
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.4139188496
Short name T1168
Test name
Test status
Simulation time 165723378 ps
CPU time 0.81 seconds
Started Jun 27 06:36:59 PM PDT 24
Finished Jun 27 06:37:09 PM PDT 24
Peak memory 206280 kb
Host smart-35a914be-5a4a-4784-a60b-17e38c3df518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41391
88496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.4139188496
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.3783832712
Short name T887
Test name
Test status
Simulation time 177926382 ps
CPU time 0.81 seconds
Started Jun 27 06:36:58 PM PDT 24
Finished Jun 27 06:37:06 PM PDT 24
Peak memory 206300 kb
Host smart-7237b3fe-f52b-46a0-a220-3485e9f28950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37838
32712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.3783832712
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.173429557
Short name T2183
Test name
Test status
Simulation time 519456656 ps
CPU time 1.51 seconds
Started Jun 27 06:36:56 PM PDT 24
Finished Jun 27 06:37:03 PM PDT 24
Peak memory 206356 kb
Host smart-c88e1858-25f7-4582-8da9-01411ada3567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17342
9557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.173429557
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.2742312945
Short name T163
Test name
Test status
Simulation time 1086888914 ps
CPU time 2.16 seconds
Started Jun 27 06:37:00 PM PDT 24
Finished Jun 27 06:37:11 PM PDT 24
Peak memory 206364 kb
Host smart-3488a24b-f4d8-49e0-8464-739397e3493e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27423
12945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.2742312945
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.4291638677
Short name T178
Test name
Test status
Simulation time 18751596560 ps
CPU time 31.98 seconds
Started Jun 27 06:36:53 PM PDT 24
Finished Jun 27 06:37:28 PM PDT 24
Peak memory 206400 kb
Host smart-3c5c2a93-4730-4ebe-8ea4-c4a7d2638c46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42916
38677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.4291638677
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.2749849330
Short name T875
Test name
Test status
Simulation time 341056408 ps
CPU time 1.08 seconds
Started Jun 27 06:36:59 PM PDT 24
Finished Jun 27 06:37:08 PM PDT 24
Peak memory 206260 kb
Host smart-df0c2c8e-81b3-4d01-a086-e0ae66e1a1f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27498
49330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.2749849330
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.139350911
Short name T815
Test name
Test status
Simulation time 141685786 ps
CPU time 0.75 seconds
Started Jun 27 06:37:00 PM PDT 24
Finished Jun 27 06:37:10 PM PDT 24
Peak memory 206276 kb
Host smart-38df226d-83db-4692-bcb7-da9365819119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13935
0911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.139350911
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.3528768342
Short name T487
Test name
Test status
Simulation time 38787558 ps
CPU time 0.63 seconds
Started Jun 27 06:37:00 PM PDT 24
Finished Jun 27 06:37:09 PM PDT 24
Peak memory 206284 kb
Host smart-3f9a74a1-973c-4efa-8c2f-1bf38df5d160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35287
68342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.3528768342
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.3556181002
Short name T2465
Test name
Test status
Simulation time 825918538 ps
CPU time 1.96 seconds
Started Jun 27 06:37:00 PM PDT 24
Finished Jun 27 06:37:11 PM PDT 24
Peak memory 206420 kb
Host smart-e6bd100b-e291-4bfe-9792-235be7f8d074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35561
81002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.3556181002
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.523446794
Short name T1311
Test name
Test status
Simulation time 262721690 ps
CPU time 1.64 seconds
Started Jun 27 06:37:02 PM PDT 24
Finished Jun 27 06:37:13 PM PDT 24
Peak memory 206360 kb
Host smart-8adbb38a-8efe-4fb5-b4f0-c59912a4a449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52344
6794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.523446794
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.4119771638
Short name T1481
Test name
Test status
Simulation time 182482726 ps
CPU time 0.84 seconds
Started Jun 27 06:36:59 PM PDT 24
Finished Jun 27 06:37:09 PM PDT 24
Peak memory 206292 kb
Host smart-7c9bbe01-4f1a-4ae0-8e4a-6961d8ed4f23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41197
71638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.4119771638
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.2069983516
Short name T1603
Test name
Test status
Simulation time 143903163 ps
CPU time 0.72 seconds
Started Jun 27 06:37:00 PM PDT 24
Finished Jun 27 06:37:09 PM PDT 24
Peak memory 206284 kb
Host smart-2c694a5c-a161-4da6-aee6-e7ea09106018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20699
83516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.2069983516
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.1223640326
Short name T672
Test name
Test status
Simulation time 236583204 ps
CPU time 0.89 seconds
Started Jun 27 06:37:03 PM PDT 24
Finished Jun 27 06:37:13 PM PDT 24
Peak memory 206276 kb
Host smart-81c0c67f-a756-46fc-9e7f-e49b38b488a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12236
40326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.1223640326
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.4227186653
Short name T2464
Test name
Test status
Simulation time 253082357 ps
CPU time 0.91 seconds
Started Jun 27 06:37:02 PM PDT 24
Finished Jun 27 06:37:12 PM PDT 24
Peak memory 206300 kb
Host smart-3aeb1a64-cc29-47a1-aa6b-e4c3bb107fcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42271
86653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.4227186653
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.650400431
Short name T576
Test name
Test status
Simulation time 23317631977 ps
CPU time 22.09 seconds
Started Jun 27 06:37:03 PM PDT 24
Finished Jun 27 06:37:34 PM PDT 24
Peak memory 206320 kb
Host smart-7ea6a96b-0bff-4f1e-afdc-1f1dbbc89098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65040
0431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.650400431
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.3195711945
Short name T1848
Test name
Test status
Simulation time 3301146310 ps
CPU time 3.7 seconds
Started Jun 27 06:36:55 PM PDT 24
Finished Jun 27 06:37:03 PM PDT 24
Peak memory 206312 kb
Host smart-bf3e270d-753d-4e51-9b20-fd3132210d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31957
11945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.3195711945
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.2770506821
Short name T1670
Test name
Test status
Simulation time 6475370939 ps
CPU time 60.45 seconds
Started Jun 27 06:37:03 PM PDT 24
Finished Jun 27 06:38:13 PM PDT 24
Peak memory 206480 kb
Host smart-210cfdae-346c-4844-9078-f6dfda5ec09d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27705
06821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.2770506821
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.1881398023
Short name T2
Test name
Test status
Simulation time 4408095697 ps
CPU time 117.12 seconds
Started Jun 27 06:37:01 PM PDT 24
Finished Jun 27 06:39:07 PM PDT 24
Peak memory 206444 kb
Host smart-bf491201-f2ee-4846-aab4-afe013ba163c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1881398023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.1881398023
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.2652257605
Short name T687
Test name
Test status
Simulation time 251005513 ps
CPU time 0.97 seconds
Started Jun 27 06:37:03 PM PDT 24
Finished Jun 27 06:37:13 PM PDT 24
Peak memory 206292 kb
Host smart-f2a92258-4b75-4b8a-aaa9-6d41eeba8a67
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2652257605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.2652257605
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.1936544194
Short name T1320
Test name
Test status
Simulation time 263445722 ps
CPU time 0.98 seconds
Started Jun 27 06:37:03 PM PDT 24
Finished Jun 27 06:37:13 PM PDT 24
Peak memory 206264 kb
Host smart-08ab33e4-78b4-4a0b-90c2-7893092997ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19365
44194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.1936544194
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.1284139137
Short name T2320
Test name
Test status
Simulation time 3336301315 ps
CPU time 29.33 seconds
Started Jun 27 06:37:04 PM PDT 24
Finished Jun 27 06:37:42 PM PDT 24
Peak memory 206508 kb
Host smart-81df2c3e-87fb-4774-a4ec-cdf5178d1946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12841
39137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.1284139137
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.514545419
Short name T880
Test name
Test status
Simulation time 3864489610 ps
CPU time 27.83 seconds
Started Jun 27 06:37:08 PM PDT 24
Finished Jun 27 06:37:43 PM PDT 24
Peak memory 206500 kb
Host smart-098f6064-af44-4438-8069-573d1bce72e3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=514545419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.514545419
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.2073079701
Short name T326
Test name
Test status
Simulation time 175174987 ps
CPU time 0.8 seconds
Started Jun 27 06:37:03 PM PDT 24
Finished Jun 27 06:37:12 PM PDT 24
Peak memory 206292 kb
Host smart-dd37c951-6140-4cd0-9fc1-d182f76eb08b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2073079701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.2073079701
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.1244145887
Short name T1798
Test name
Test status
Simulation time 140661536 ps
CPU time 0.73 seconds
Started Jun 27 06:37:03 PM PDT 24
Finished Jun 27 06:37:12 PM PDT 24
Peak memory 206276 kb
Host smart-e7f9bb23-a2a9-4330-9c97-3812a90a5510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12441
45887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.1244145887
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.3695949616
Short name T120
Test name
Test status
Simulation time 190021783 ps
CPU time 0.91 seconds
Started Jun 27 06:37:08 PM PDT 24
Finished Jun 27 06:37:16 PM PDT 24
Peak memory 206280 kb
Host smart-dd300037-9489-4a85-b4ac-610ba12f3395
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36959
49616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.3695949616
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.177204239
Short name T856
Test name
Test status
Simulation time 148100717 ps
CPU time 0.76 seconds
Started Jun 27 06:37:16 PM PDT 24
Finished Jun 27 06:37:22 PM PDT 24
Peak memory 206120 kb
Host smart-be7f4d09-a2e6-4a2f-82ce-c337f33747cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17720
4239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.177204239
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.2117352882
Short name T362
Test name
Test status
Simulation time 169772741 ps
CPU time 0.84 seconds
Started Jun 27 06:37:19 PM PDT 24
Finished Jun 27 06:37:26 PM PDT 24
Peak memory 206304 kb
Host smart-044f3e4a-938a-43b8-a135-e625eef412bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21173
52882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.2117352882
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.2321358399
Short name T2373
Test name
Test status
Simulation time 161471425 ps
CPU time 0.79 seconds
Started Jun 27 06:37:06 PM PDT 24
Finished Jun 27 06:37:15 PM PDT 24
Peak memory 206280 kb
Host smart-e097cd55-fd47-4471-9d3b-9949e5e3a196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23213
58399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.2321358399
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.1632852053
Short name T2047
Test name
Test status
Simulation time 193978245 ps
CPU time 0.87 seconds
Started Jun 27 06:37:07 PM PDT 24
Finished Jun 27 06:37:15 PM PDT 24
Peak memory 206248 kb
Host smart-92cf139b-8494-4301-b967-7750c7347d35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16328
52053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.1632852053
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.909210371
Short name T680
Test name
Test status
Simulation time 225214573 ps
CPU time 0.88 seconds
Started Jun 27 06:37:21 PM PDT 24
Finished Jun 27 06:37:29 PM PDT 24
Peak memory 206244 kb
Host smart-de8cc6e1-eb75-4573-9fe3-15d1caee4cf2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=909210371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.909210371
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.729028350
Short name T969
Test name
Test status
Simulation time 154880575 ps
CPU time 0.76 seconds
Started Jun 27 06:37:08 PM PDT 24
Finished Jun 27 06:37:16 PM PDT 24
Peak memory 206272 kb
Host smart-fbea3c6d-233d-4529-8b40-13a369970d12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72902
8350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.729028350
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.634278575
Short name T1531
Test name
Test status
Simulation time 62242227 ps
CPU time 0.66 seconds
Started Jun 27 06:37:07 PM PDT 24
Finished Jun 27 06:37:15 PM PDT 24
Peak memory 206276 kb
Host smart-879a1cca-2ec7-4ac3-b10d-e01893cad328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63427
8575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.634278575
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.98027433
Short name T1802
Test name
Test status
Simulation time 20509643218 ps
CPU time 43.68 seconds
Started Jun 27 06:37:21 PM PDT 24
Finished Jun 27 06:38:12 PM PDT 24
Peak memory 206392 kb
Host smart-08201646-a333-47c4-806b-bb309e3368dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98027
433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.98027433
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.1908822832
Short name T1418
Test name
Test status
Simulation time 180118228 ps
CPU time 0.77 seconds
Started Jun 27 06:37:20 PM PDT 24
Finished Jun 27 06:37:27 PM PDT 24
Peak memory 206300 kb
Host smart-ea3b776f-48a5-4b9c-9172-c1827d5b73a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19088
22832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.1908822832
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.1707625818
Short name T2410
Test name
Test status
Simulation time 234483940 ps
CPU time 0.92 seconds
Started Jun 27 06:37:22 PM PDT 24
Finished Jun 27 06:37:30 PM PDT 24
Peak memory 206280 kb
Host smart-be2e6cc4-3c10-487e-b975-aa5eceb27d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17076
25818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.1707625818
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.3858838346
Short name T1919
Test name
Test status
Simulation time 243421679 ps
CPU time 0.86 seconds
Started Jun 27 06:37:16 PM PDT 24
Finished Jun 27 06:37:22 PM PDT 24
Peak memory 206304 kb
Host smart-aa4270db-3976-41e9-9f39-30eafdf563b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38588
38346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.3858838346
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.2566613972
Short name T1043
Test name
Test status
Simulation time 210844198 ps
CPU time 0.83 seconds
Started Jun 27 06:37:21 PM PDT 24
Finished Jun 27 06:37:29 PM PDT 24
Peak memory 206276 kb
Host smart-1169635c-5484-43d0-9bfd-4b10766d7b94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25666
13972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.2566613972
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.3484475324
Short name T1332
Test name
Test status
Simulation time 136647276 ps
CPU time 0.72 seconds
Started Jun 27 06:37:22 PM PDT 24
Finished Jun 27 06:37:30 PM PDT 24
Peak memory 206220 kb
Host smart-1d8ee971-b511-410d-8cf9-21e39a711219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34844
75324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.3484475324
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.2936035919
Short name T1236
Test name
Test status
Simulation time 157717868 ps
CPU time 0.77 seconds
Started Jun 27 06:37:22 PM PDT 24
Finished Jun 27 06:37:30 PM PDT 24
Peak memory 206220 kb
Host smart-bc231c0d-2a7a-448a-8d27-1bdb5442288a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29360
35919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.2936035919
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.3949365094
Short name T546
Test name
Test status
Simulation time 148457243 ps
CPU time 0.76 seconds
Started Jun 27 06:37:05 PM PDT 24
Finished Jun 27 06:37:15 PM PDT 24
Peak memory 206264 kb
Host smart-054f1ff6-8710-42e6-8549-64313b7ec31f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39493
65094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.3949365094
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.1054407620
Short name T824
Test name
Test status
Simulation time 177398798 ps
CPU time 0.84 seconds
Started Jun 27 06:37:21 PM PDT 24
Finished Jun 27 06:37:29 PM PDT 24
Peak memory 206032 kb
Host smart-4f7e8a62-916b-4c52-9192-29ffbb0d02eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10544
07620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.1054407620
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.1870062342
Short name T602
Test name
Test status
Simulation time 3453691992 ps
CPU time 31.84 seconds
Started Jun 27 06:37:16 PM PDT 24
Finished Jun 27 06:37:52 PM PDT 24
Peak memory 206408 kb
Host smart-b8c26bc8-fd31-4d7d-9b19-03779bd56f29
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1870062342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.1870062342
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.3025866134
Short name T1106
Test name
Test status
Simulation time 254502725 ps
CPU time 0.85 seconds
Started Jun 27 06:37:21 PM PDT 24
Finished Jun 27 06:37:29 PM PDT 24
Peak memory 206228 kb
Host smart-be1f8ebe-806f-4cbf-bc24-9e7ec9ea304a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30258
66134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.3025866134
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.545481868
Short name T1425
Test name
Test status
Simulation time 221815606 ps
CPU time 0.83 seconds
Started Jun 27 06:37:08 PM PDT 24
Finished Jun 27 06:37:16 PM PDT 24
Peak memory 206272 kb
Host smart-96dcab4d-f685-4765-8ffc-06e500012cfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54548
1868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.545481868
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.1615580360
Short name T1007
Test name
Test status
Simulation time 3945776297 ps
CPU time 105.49 seconds
Started Jun 27 06:37:16 PM PDT 24
Finished Jun 27 06:39:06 PM PDT 24
Peak memory 206420 kb
Host smart-908fe080-cfe8-45d8-845c-1a002c9b28c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16155
80360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.1615580360
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.2050939282
Short name T190
Test name
Test status
Simulation time 39282108 ps
CPU time 0.7 seconds
Started Jun 27 06:37:07 PM PDT 24
Finished Jun 27 06:37:15 PM PDT 24
Peak memory 206372 kb
Host smart-e181ddf4-52b6-4347-854d-838c8d92d786
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2050939282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.2050939282
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.1731255376
Short name T1488
Test name
Test status
Simulation time 3777399939 ps
CPU time 4.49 seconds
Started Jun 27 06:37:18 PM PDT 24
Finished Jun 27 06:37:28 PM PDT 24
Peak memory 206344 kb
Host smart-ac98f4e0-c115-48c8-b279-088d4d98c69c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1731255376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.1731255376
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.1455940094
Short name T1375
Test name
Test status
Simulation time 13371187913 ps
CPU time 13.67 seconds
Started Jun 27 06:37:15 PM PDT 24
Finished Jun 27 06:37:34 PM PDT 24
Peak memory 206500 kb
Host smart-31ead4e0-d190-408a-aa04-1261e0477555
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1455940094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.1455940094
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.1458524463
Short name T564
Test name
Test status
Simulation time 23336214314 ps
CPU time 26.49 seconds
Started Jun 27 06:37:09 PM PDT 24
Finished Jun 27 06:37:42 PM PDT 24
Peak memory 206340 kb
Host smart-3ab3da7b-e61d-4a1c-ad37-46f7edd90d96
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1458524463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.1458524463
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.3427284988
Short name T923
Test name
Test status
Simulation time 219661050 ps
CPU time 0.84 seconds
Started Jun 27 06:37:10 PM PDT 24
Finished Jun 27 06:37:18 PM PDT 24
Peak memory 206276 kb
Host smart-36effca7-30da-43de-84f0-a392fa661b6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34272
84988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.3427284988
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.1791316236
Short name T2487
Test name
Test status
Simulation time 142524805 ps
CPU time 0.74 seconds
Started Jun 27 06:37:16 PM PDT 24
Finished Jun 27 06:37:22 PM PDT 24
Peak memory 206280 kb
Host smart-50b94cd3-3f29-40ad-8adc-c9895c256134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17913
16236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.1791316236
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.3515158529
Short name T2186
Test name
Test status
Simulation time 364162497 ps
CPU time 1.13 seconds
Started Jun 27 06:37:16 PM PDT 24
Finished Jun 27 06:37:22 PM PDT 24
Peak memory 206100 kb
Host smart-c4be1dc9-acf1-472b-87db-615632f06cd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35151
58529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.3515158529
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.1964474314
Short name T2214
Test name
Test status
Simulation time 381511027 ps
CPU time 1.18 seconds
Started Jun 27 06:37:15 PM PDT 24
Finished Jun 27 06:37:21 PM PDT 24
Peak memory 206292 kb
Host smart-c14bf489-392d-4775-ad3c-3dd6ad42b0ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19644
74314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.1964474314
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.2983920555
Short name T1766
Test name
Test status
Simulation time 21493906113 ps
CPU time 38.27 seconds
Started Jun 27 06:37:08 PM PDT 24
Finished Jun 27 06:37:53 PM PDT 24
Peak memory 206436 kb
Host smart-a5c51824-fc6f-4a09-b911-d97335f63677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29839
20555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.2983920555
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.4109792672
Short name T2317
Test name
Test status
Simulation time 475252705 ps
CPU time 1.36 seconds
Started Jun 27 06:37:15 PM PDT 24
Finished Jun 27 06:37:21 PM PDT 24
Peak memory 206280 kb
Host smart-e1efc320-2235-48dd-a1c5-aab4f12bde72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41097
92672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.4109792672
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.581096803
Short name T1790
Test name
Test status
Simulation time 135885281 ps
CPU time 0.71 seconds
Started Jun 27 06:37:21 PM PDT 24
Finished Jun 27 06:37:29 PM PDT 24
Peak memory 206284 kb
Host smart-cde32c23-5498-498f-a46b-b4af76b5010b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58109
6803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.581096803
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.1632225988
Short name T2249
Test name
Test status
Simulation time 53291542 ps
CPU time 0.64 seconds
Started Jun 27 06:37:21 PM PDT 24
Finished Jun 27 06:37:29 PM PDT 24
Peak memory 206276 kb
Host smart-c05c5a91-20eb-4be2-8bbd-275c10f28cee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16322
25988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.1632225988
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.1862839466
Short name T1473
Test name
Test status
Simulation time 915433346 ps
CPU time 2.3 seconds
Started Jun 27 06:37:21 PM PDT 24
Finished Jun 27 06:37:30 PM PDT 24
Peak memory 206320 kb
Host smart-49b07961-03f0-41b3-acd7-736f61eff824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18628
39466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.1862839466
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.224607476
Short name T2095
Test name
Test status
Simulation time 277400728 ps
CPU time 2.03 seconds
Started Jun 27 06:37:16 PM PDT 24
Finished Jun 27 06:37:23 PM PDT 24
Peak memory 206340 kb
Host smart-9cdc29a2-aee4-4b9b-b56b-c77f4491970f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22460
7476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.224607476
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.3177698206
Short name T2246
Test name
Test status
Simulation time 233681451 ps
CPU time 0.87 seconds
Started Jun 27 06:37:21 PM PDT 24
Finished Jun 27 06:37:29 PM PDT 24
Peak memory 206248 kb
Host smart-c4b78fff-c67b-48cc-b2ca-77302e9bba66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31776
98206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.3177698206
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.2446483024
Short name T1053
Test name
Test status
Simulation time 186629866 ps
CPU time 0.78 seconds
Started Jun 27 06:37:21 PM PDT 24
Finished Jun 27 06:37:29 PM PDT 24
Peak memory 206236 kb
Host smart-9b91ca70-540f-4008-b1bd-eb12b0aa1acc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24464
83024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.2446483024
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.243378990
Short name T2547
Test name
Test status
Simulation time 240079491 ps
CPU time 0.92 seconds
Started Jun 27 06:37:16 PM PDT 24
Finished Jun 27 06:37:22 PM PDT 24
Peak memory 206268 kb
Host smart-214142e5-4666-4645-8e93-f5535274ae4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24337
8990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.243378990
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.3494672764
Short name T1359
Test name
Test status
Simulation time 205449627 ps
CPU time 0.81 seconds
Started Jun 27 06:37:18 PM PDT 24
Finished Jun 27 06:37:24 PM PDT 24
Peak memory 206300 kb
Host smart-de78c7c7-b1fe-4eeb-844d-4863119e3f80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34946
72764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.3494672764
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.157044571
Short name T387
Test name
Test status
Simulation time 23300537798 ps
CPU time 23.86 seconds
Started Jun 27 06:37:20 PM PDT 24
Finished Jun 27 06:37:52 PM PDT 24
Peak memory 206284 kb
Host smart-d619befd-4ad6-41ec-91a1-7dc4f8e8c292
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15704
4571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.157044571
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.2093275907
Short name T1693
Test name
Test status
Simulation time 3324164049 ps
CPU time 4.36 seconds
Started Jun 27 06:37:09 PM PDT 24
Finished Jun 27 06:37:20 PM PDT 24
Peak memory 206332 kb
Host smart-8b4a4577-a68e-4a92-acfc-2fec0de21d65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20932
75907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.2093275907
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.3851722303
Short name T1036
Test name
Test status
Simulation time 6238841298 ps
CPU time 57.07 seconds
Started Jun 27 06:37:19 PM PDT 24
Finished Jun 27 06:38:23 PM PDT 24
Peak memory 206520 kb
Host smart-6408adcd-38c4-4488-9b3e-bde66d544306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38517
22303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.3851722303
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.592581682
Short name T1416
Test name
Test status
Simulation time 5656996768 ps
CPU time 51.99 seconds
Started Jun 27 06:37:22 PM PDT 24
Finished Jun 27 06:38:23 PM PDT 24
Peak memory 206444 kb
Host smart-1542d816-d82e-4c91-9680-3c89bf93ca7b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=592581682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.592581682
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.1671949710
Short name T2162
Test name
Test status
Simulation time 252995096 ps
CPU time 0.93 seconds
Started Jun 27 06:37:18 PM PDT 24
Finished Jun 27 06:37:25 PM PDT 24
Peak memory 206284 kb
Host smart-9c2100ab-4fa4-45a0-a81d-8538cde14fbd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1671949710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.1671949710
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.2027058498
Short name T647
Test name
Test status
Simulation time 185444031 ps
CPU time 0.85 seconds
Started Jun 27 06:37:16 PM PDT 24
Finished Jun 27 06:37:22 PM PDT 24
Peak memory 206284 kb
Host smart-e7fe85a6-fb2a-4383-b458-67882c6d9480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20270
58498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.2027058498
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.2617838944
Short name T473
Test name
Test status
Simulation time 3946256314 ps
CPU time 36.02 seconds
Started Jun 27 06:37:21 PM PDT 24
Finished Jun 27 06:38:04 PM PDT 24
Peak memory 206224 kb
Host smart-62ba29ce-a023-41e9-b9c4-e6439f677b9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26178
38944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.2617838944
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.2628567861
Short name T646
Test name
Test status
Simulation time 4867647230 ps
CPU time 33.2 seconds
Started Jun 27 06:37:22 PM PDT 24
Finished Jun 27 06:38:04 PM PDT 24
Peak memory 206436 kb
Host smart-187357ed-0339-4418-89d0-7179be96b8ff
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2628567861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.2628567861
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.1923142418
Short name T609
Test name
Test status
Simulation time 169028962 ps
CPU time 0.78 seconds
Started Jun 27 06:37:16 PM PDT 24
Finished Jun 27 06:37:21 PM PDT 24
Peak memory 206300 kb
Host smart-e4104abd-b470-413f-973c-7bcc05c6159e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1923142418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.1923142418
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.1454636643
Short name T1141
Test name
Test status
Simulation time 181980817 ps
CPU time 0.76 seconds
Started Jun 27 06:37:17 PM PDT 24
Finished Jun 27 06:37:23 PM PDT 24
Peak memory 206284 kb
Host smart-fffd1567-235f-44bc-ba62-80adae873607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14546
36643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.1454636643
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.3637739188
Short name T125
Test name
Test status
Simulation time 166056037 ps
CPU time 0.82 seconds
Started Jun 27 06:37:16 PM PDT 24
Finished Jun 27 06:37:21 PM PDT 24
Peak memory 206260 kb
Host smart-4afaba60-f737-4bba-a31c-09b689600611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36377
39188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.3637739188
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.333277758
Short name T347
Test name
Test status
Simulation time 210654426 ps
CPU time 0.88 seconds
Started Jun 27 06:37:16 PM PDT 24
Finished Jun 27 06:37:22 PM PDT 24
Peak memory 206272 kb
Host smart-4c892701-d5cd-4104-9e39-364e6724cce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33327
7758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.333277758
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.3640158188
Short name T23
Test name
Test status
Simulation time 158133793 ps
CPU time 0.76 seconds
Started Jun 27 06:37:11 PM PDT 24
Finished Jun 27 06:37:18 PM PDT 24
Peak memory 206240 kb
Host smart-f79f0abb-f67d-4bea-9429-9529dca62f46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36401
58188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.3640158188
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.3215683657
Short name T1695
Test name
Test status
Simulation time 159525643 ps
CPU time 0.8 seconds
Started Jun 27 06:37:09 PM PDT 24
Finished Jun 27 06:37:17 PM PDT 24
Peak memory 206296 kb
Host smart-5757a3b5-cccc-4898-9800-0a82023dff3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32156
83657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.3215683657
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.2907934382
Short name T162
Test name
Test status
Simulation time 158915479 ps
CPU time 0.75 seconds
Started Jun 27 06:37:19 PM PDT 24
Finished Jun 27 06:37:26 PM PDT 24
Peak memory 206308 kb
Host smart-32b303e9-7444-401a-8705-ef7a10279963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29079
34382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.2907934382
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.255892892
Short name T1822
Test name
Test status
Simulation time 243368725 ps
CPU time 0.91 seconds
Started Jun 27 06:37:22 PM PDT 24
Finished Jun 27 06:37:30 PM PDT 24
Peak memory 206296 kb
Host smart-a99b32a6-8003-46e8-9252-f3fb85ec1deb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=255892892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.255892892
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.3565974288
Short name T1709
Test name
Test status
Simulation time 147223366 ps
CPU time 0.75 seconds
Started Jun 27 06:37:21 PM PDT 24
Finished Jun 27 06:37:29 PM PDT 24
Peak memory 206164 kb
Host smart-dd791c60-e2df-4825-af94-65bec24a1998
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35659
74288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.3565974288
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.558141493
Short name T2200
Test name
Test status
Simulation time 66359615 ps
CPU time 0.67 seconds
Started Jun 27 06:37:21 PM PDT 24
Finished Jun 27 06:37:29 PM PDT 24
Peak memory 206216 kb
Host smart-5ea2e71d-62f6-45b8-965d-ffa70d43887a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55814
1493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.558141493
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.1878152470
Short name T2419
Test name
Test status
Simulation time 14795540550 ps
CPU time 30.71 seconds
Started Jun 27 06:37:19 PM PDT 24
Finished Jun 27 06:37:56 PM PDT 24
Peak memory 206476 kb
Host smart-00874792-e03a-40b7-89e4-298303ca5fef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18781
52470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.1878152470
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.3429490411
Short name T488
Test name
Test status
Simulation time 147655981 ps
CPU time 0.79 seconds
Started Jun 27 06:37:10 PM PDT 24
Finished Jun 27 06:37:17 PM PDT 24
Peak memory 206276 kb
Host smart-e8897a81-5c43-4796-b615-e4e5623235a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34294
90411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.3429490411
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.3617006673
Short name T800
Test name
Test status
Simulation time 229094282 ps
CPU time 0.92 seconds
Started Jun 27 06:37:15 PM PDT 24
Finished Jun 27 06:37:21 PM PDT 24
Peak memory 206268 kb
Host smart-55eede7b-72bd-4376-b03e-f9c53a02b3c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36170
06673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.3617006673
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.1052824782
Short name T1906
Test name
Test status
Simulation time 179296401 ps
CPU time 0.78 seconds
Started Jun 27 06:37:16 PM PDT 24
Finished Jun 27 06:37:22 PM PDT 24
Peak memory 206304 kb
Host smart-bf59e29b-2856-4cc4-9c4f-7c2b476e2396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10528
24782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.1052824782
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.2804291538
Short name T1015
Test name
Test status
Simulation time 198745822 ps
CPU time 0.92 seconds
Started Jun 27 06:37:16 PM PDT 24
Finished Jun 27 06:37:23 PM PDT 24
Peak memory 206260 kb
Host smart-bd1bc376-9068-40cf-b8ef-56ff4eb3caec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28042
91538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.2804291538
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.65281054
Short name T1319
Test name
Test status
Simulation time 184464463 ps
CPU time 0.76 seconds
Started Jun 27 06:37:22 PM PDT 24
Finished Jun 27 06:37:32 PM PDT 24
Peak memory 206268 kb
Host smart-0a27e3f7-c8a1-4097-a9da-ed358629c5ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65281
054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.65281054
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.2306314212
Short name T1217
Test name
Test status
Simulation time 177524455 ps
CPU time 0.81 seconds
Started Jun 27 06:37:18 PM PDT 24
Finished Jun 27 06:37:24 PM PDT 24
Peak memory 206256 kb
Host smart-0018f8da-1692-41c2-abef-2867f526c66f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23063
14212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.2306314212
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.813997696
Short name T1991
Test name
Test status
Simulation time 191467786 ps
CPU time 0.77 seconds
Started Jun 27 06:37:09 PM PDT 24
Finished Jun 27 06:37:17 PM PDT 24
Peak memory 206276 kb
Host smart-4749efa8-56b0-4c75-9e88-092c82281e58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81399
7696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.813997696
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.683366393
Short name T414
Test name
Test status
Simulation time 185747012 ps
CPU time 0.86 seconds
Started Jun 27 06:37:11 PM PDT 24
Finished Jun 27 06:37:18 PM PDT 24
Peak memory 206188 kb
Host smart-7dc3d459-20ef-4d24-9450-a03bea3e7b24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68336
6393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.683366393
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.245823212
Short name T507
Test name
Test status
Simulation time 5926061022 ps
CPU time 160.33 seconds
Started Jun 27 06:37:17 PM PDT 24
Finished Jun 27 06:40:02 PM PDT 24
Peak memory 206440 kb
Host smart-c5c8cf17-f506-47e0-8101-98a7df82614a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=245823212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.245823212
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.2235834953
Short name T442
Test name
Test status
Simulation time 188080054 ps
CPU time 0.79 seconds
Started Jun 27 06:37:08 PM PDT 24
Finished Jun 27 06:37:16 PM PDT 24
Peak memory 206260 kb
Host smart-1f17cc4e-f3fb-413a-b7ec-9607337267f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22358
34953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.2235834953
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.3192827379
Short name T2313
Test name
Test status
Simulation time 161889254 ps
CPU time 0.78 seconds
Started Jun 27 06:37:11 PM PDT 24
Finished Jun 27 06:37:18 PM PDT 24
Peak memory 206172 kb
Host smart-d9fcbbea-2b2e-4e70-aeb2-dbb1dcfc8524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31928
27379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.3192827379
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.3162190799
Short name T756
Test name
Test status
Simulation time 4558472975 ps
CPU time 39.26 seconds
Started Jun 27 06:37:21 PM PDT 24
Finished Jun 27 06:38:08 PM PDT 24
Peak memory 206488 kb
Host smart-72d9dc3c-b231-4bdb-bee4-236a551ccc7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31621
90799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.3162190799
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.1321444488
Short name T1140
Test name
Test status
Simulation time 50792599 ps
CPU time 0.71 seconds
Started Jun 27 06:37:24 PM PDT 24
Finished Jun 27 06:37:32 PM PDT 24
Peak memory 206356 kb
Host smart-0734c4bd-692c-495c-b5ea-750496762b43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1321444488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.1321444488
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.4233265889
Short name T2108
Test name
Test status
Simulation time 3848231929 ps
CPU time 4.51 seconds
Started Jun 27 06:37:08 PM PDT 24
Finished Jun 27 06:37:20 PM PDT 24
Peak memory 206436 kb
Host smart-21731ce9-6417-44f1-8964-141bc627ce55
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4233265889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.4233265889
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.612049039
Short name T1703
Test name
Test status
Simulation time 13366004101 ps
CPU time 12.67 seconds
Started Jun 27 06:37:22 PM PDT 24
Finished Jun 27 06:37:42 PM PDT 24
Peak memory 206336 kb
Host smart-99bac87b-ee41-48cc-a81d-1d498b903afb
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=612049039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.612049039
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.3766488508
Short name T1551
Test name
Test status
Simulation time 23394607163 ps
CPU time 20.63 seconds
Started Jun 27 06:37:17 PM PDT 24
Finished Jun 27 06:37:43 PM PDT 24
Peak memory 206424 kb
Host smart-2f1d7e68-06e4-47de-96d4-6fb7795c95df
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3766488508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.3766488508
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.4289363640
Short name T1089
Test name
Test status
Simulation time 182886813 ps
CPU time 0.8 seconds
Started Jun 27 06:37:19 PM PDT 24
Finished Jun 27 06:37:25 PM PDT 24
Peak memory 206284 kb
Host smart-d127ddaa-83a4-4a4f-bd4e-61eada33f7e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42893
63640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.4289363640
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.1609391948
Short name T809
Test name
Test status
Simulation time 161475794 ps
CPU time 0.76 seconds
Started Jun 27 06:37:18 PM PDT 24
Finished Jun 27 06:37:24 PM PDT 24
Peak memory 206276 kb
Host smart-55d3c151-6040-4151-a160-addab3e2b021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16093
91948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.1609391948
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.1588559437
Short name T183
Test name
Test status
Simulation time 360721072 ps
CPU time 1.16 seconds
Started Jun 27 06:37:18 PM PDT 24
Finished Jun 27 06:37:25 PM PDT 24
Peak memory 206280 kb
Host smart-952eed29-7ebd-4646-8658-d84c0f92f48f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15885
59437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.1588559437
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.1985851534
Short name T2356
Test name
Test status
Simulation time 1453208206 ps
CPU time 3.08 seconds
Started Jun 27 06:37:18 PM PDT 24
Finished Jun 27 06:37:27 PM PDT 24
Peak memory 206440 kb
Host smart-47f55b67-b599-43b5-9437-039c8258d9b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19858
51534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.1985851534
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.1669613533
Short name T570
Test name
Test status
Simulation time 357765363 ps
CPU time 1.18 seconds
Started Jun 27 06:37:23 PM PDT 24
Finished Jun 27 06:37:32 PM PDT 24
Peak memory 206312 kb
Host smart-2a5702c3-7f45-404e-a065-6815d38045d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16696
13533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.1669613533
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.170507290
Short name T1774
Test name
Test status
Simulation time 147297371 ps
CPU time 0.75 seconds
Started Jun 27 06:37:19 PM PDT 24
Finished Jun 27 06:37:25 PM PDT 24
Peak memory 206284 kb
Host smart-7b418369-914b-4be7-a93c-221b97864f2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17050
7290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.170507290
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.48580096
Short name T832
Test name
Test status
Simulation time 41403162 ps
CPU time 0.64 seconds
Started Jun 27 06:37:19 PM PDT 24
Finished Jun 27 06:37:26 PM PDT 24
Peak memory 206296 kb
Host smart-b71c4133-891d-4cbb-8019-c416856fb0d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48580
096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.48580096
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.477899944
Short name T890
Test name
Test status
Simulation time 919480508 ps
CPU time 2.02 seconds
Started Jun 27 06:37:08 PM PDT 24
Finished Jun 27 06:37:17 PM PDT 24
Peak memory 206424 kb
Host smart-7aed3d3f-6d5b-4f6a-8feb-2ff43783f94c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47789
9944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.477899944
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.1266646519
Short name T671
Test name
Test status
Simulation time 157654065 ps
CPU time 1.18 seconds
Started Jun 27 06:37:12 PM PDT 24
Finished Jun 27 06:37:19 PM PDT 24
Peak memory 206396 kb
Host smart-ee60f25a-bdd8-4997-8cab-1900347c186a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12666
46519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.1266646519
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.2188070178
Short name T525
Test name
Test status
Simulation time 224074912 ps
CPU time 0.85 seconds
Started Jun 27 06:37:10 PM PDT 24
Finished Jun 27 06:37:17 PM PDT 24
Peak memory 206288 kb
Host smart-dd371256-34b4-4b49-85f6-f09377373ca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21880
70178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.2188070178
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.2574103103
Short name T2366
Test name
Test status
Simulation time 148793888 ps
CPU time 0.78 seconds
Started Jun 27 06:37:20 PM PDT 24
Finished Jun 27 06:37:27 PM PDT 24
Peak memory 206296 kb
Host smart-f3b8e2eb-4c17-4a4f-a779-3c66db2fe8f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25741
03103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.2574103103
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.3703163620
Short name T562
Test name
Test status
Simulation time 208040971 ps
CPU time 0.9 seconds
Started Jun 27 06:37:13 PM PDT 24
Finished Jun 27 06:37:19 PM PDT 24
Peak memory 206288 kb
Host smart-c24ad90c-6b7b-452f-ad26-923b8761ad63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37031
63620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.3703163620
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.2098336251
Short name T2038
Test name
Test status
Simulation time 218149338 ps
CPU time 0.83 seconds
Started Jun 27 06:37:10 PM PDT 24
Finished Jun 27 06:37:17 PM PDT 24
Peak memory 206272 kb
Host smart-0707a0f7-1265-4418-91ff-0d617cf83b18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20983
36251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.2098336251
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.2752281557
Short name T628
Test name
Test status
Simulation time 23315052834 ps
CPU time 21.6 seconds
Started Jun 27 06:37:18 PM PDT 24
Finished Jun 27 06:37:44 PM PDT 24
Peak memory 206324 kb
Host smart-abb45eb0-3075-47fd-ad9c-ea713252f36c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27522
81557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.2752281557
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.1094169144
Short name T1746
Test name
Test status
Simulation time 3360715765 ps
CPU time 3.92 seconds
Started Jun 27 06:37:19 PM PDT 24
Finished Jun 27 06:37:30 PM PDT 24
Peak memory 206348 kb
Host smart-2df7ea80-f1f1-4fa6-aa62-daefc19fbacb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10941
69144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.1094169144
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.3702676839
Short name T1855
Test name
Test status
Simulation time 7260168246 ps
CPU time 53.47 seconds
Started Jun 27 06:37:13 PM PDT 24
Finished Jun 27 06:38:12 PM PDT 24
Peak memory 206636 kb
Host smart-953e734e-9fd1-45a0-aa13-2eeaffd7425c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37026
76839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.3702676839
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.2929717793
Short name T2128
Test name
Test status
Simulation time 5020171719 ps
CPU time 36.15 seconds
Started Jun 27 06:37:13 PM PDT 24
Finished Jun 27 06:37:54 PM PDT 24
Peak memory 206400 kb
Host smart-872cfb8c-e260-42bb-8ba5-993b289d7f90
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2929717793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.2929717793
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.57683774
Short name T2100
Test name
Test status
Simulation time 272737497 ps
CPU time 0.94 seconds
Started Jun 27 06:37:14 PM PDT 24
Finished Jun 27 06:37:20 PM PDT 24
Peak memory 206412 kb
Host smart-9077355f-57d8-4944-ae4e-67813260bced
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=57683774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.57683774
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.1116919131
Short name T1779
Test name
Test status
Simulation time 188603316 ps
CPU time 0.82 seconds
Started Jun 27 06:37:13 PM PDT 24
Finished Jun 27 06:37:19 PM PDT 24
Peak memory 206276 kb
Host smart-f99d59d4-9c87-4a62-a3db-7d0d1c5e4546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11169
19131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.1116919131
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.552728259
Short name T144
Test name
Test status
Simulation time 4587169415 ps
CPU time 126.99 seconds
Started Jun 27 06:37:12 PM PDT 24
Finished Jun 27 06:39:24 PM PDT 24
Peak memory 206412 kb
Host smart-4c85e1af-25c4-4abb-ae7c-dfe6d0ee8ae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55272
8259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.552728259
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.1536131759
Short name T1924
Test name
Test status
Simulation time 5932338730 ps
CPU time 159.62 seconds
Started Jun 27 06:37:11 PM PDT 24
Finished Jun 27 06:39:56 PM PDT 24
Peak memory 206436 kb
Host smart-5242b540-03b6-481d-af6d-55db9d27e555
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1536131759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.1536131759
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.1724744726
Short name T1170
Test name
Test status
Simulation time 156833239 ps
CPU time 0.8 seconds
Started Jun 27 06:37:14 PM PDT 24
Finished Jun 27 06:37:20 PM PDT 24
Peak memory 206316 kb
Host smart-ebf7fe2e-4a01-4328-871a-f705754f0d71
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1724744726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.1724744726
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.3539321901
Short name T1898
Test name
Test status
Simulation time 145648735 ps
CPU time 0.77 seconds
Started Jun 27 06:37:20 PM PDT 24
Finished Jun 27 06:37:27 PM PDT 24
Peak memory 206292 kb
Host smart-d3e1457e-e49c-4d4f-a338-f1e21be0cca2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35393
21901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.3539321901
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.1480093574
Short name T135
Test name
Test status
Simulation time 189821001 ps
CPU time 0.88 seconds
Started Jun 27 06:37:20 PM PDT 24
Finished Jun 27 06:37:27 PM PDT 24
Peak memory 206292 kb
Host smart-bd9ff47d-f612-4e89-b6c4-942c933eee40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14800
93574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.1480093574
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.1161933803
Short name T2092
Test name
Test status
Simulation time 156711643 ps
CPU time 0.83 seconds
Started Jun 27 06:37:14 PM PDT 24
Finished Jun 27 06:37:20 PM PDT 24
Peak memory 206440 kb
Host smart-85fc13f4-137e-4737-a3ba-22eb090b914d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11619
33803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.1161933803
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.3626548307
Short name T1596
Test name
Test status
Simulation time 173302817 ps
CPU time 0.78 seconds
Started Jun 27 06:37:20 PM PDT 24
Finished Jun 27 06:37:27 PM PDT 24
Peak memory 206292 kb
Host smart-9a85a27f-3c8b-47ec-9793-66736a4f39fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36265
48307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.3626548307
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.3445663931
Short name T1061
Test name
Test status
Simulation time 172961281 ps
CPU time 0.79 seconds
Started Jun 27 06:37:28 PM PDT 24
Finished Jun 27 06:37:36 PM PDT 24
Peak memory 206276 kb
Host smart-3ee6bf6a-61ec-48c1-a2d0-5c9cdd72ecb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34456
63931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.3445663931
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.774272718
Short name T1573
Test name
Test status
Simulation time 154944797 ps
CPU time 0.81 seconds
Started Jun 27 06:37:27 PM PDT 24
Finished Jun 27 06:37:35 PM PDT 24
Peak memory 206260 kb
Host smart-4164b415-f487-4249-b878-ba17e31246d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77427
2718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.774272718
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.1132284861
Short name T1114
Test name
Test status
Simulation time 223554747 ps
CPU time 0.94 seconds
Started Jun 27 06:37:25 PM PDT 24
Finished Jun 27 06:37:34 PM PDT 24
Peak memory 206412 kb
Host smart-7cb64347-ce0b-464a-89e6-3dd2f11160fb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1132284861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.1132284861
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.1929942529
Short name T879
Test name
Test status
Simulation time 146121935 ps
CPU time 0.74 seconds
Started Jun 27 06:37:26 PM PDT 24
Finished Jun 27 06:37:34 PM PDT 24
Peak memory 206272 kb
Host smart-dc612bcf-c5b7-4551-92e3-6dead4593eec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19299
42529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.1929942529
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.3015954357
Short name T2294
Test name
Test status
Simulation time 74137803 ps
CPU time 0.69 seconds
Started Jun 27 06:37:26 PM PDT 24
Finished Jun 27 06:37:34 PM PDT 24
Peak memory 206268 kb
Host smart-4a569de4-8274-4d4e-a4cf-ada41edaed6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30159
54357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.3015954357
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.2899441858
Short name T2103
Test name
Test status
Simulation time 15234914110 ps
CPU time 34.47 seconds
Started Jun 27 06:37:25 PM PDT 24
Finished Jun 27 06:38:07 PM PDT 24
Peak memory 206496 kb
Host smart-bc7079c0-0e1f-4df6-95c3-aae17f51caf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28994
41858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.2899441858
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.2840301892
Short name T2608
Test name
Test status
Simulation time 158916513 ps
CPU time 0.78 seconds
Started Jun 27 06:37:28 PM PDT 24
Finished Jun 27 06:37:36 PM PDT 24
Peak memory 206164 kb
Host smart-216e1944-7c18-4e27-b2c1-c9d990ab49f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28403
01892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.2840301892
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.107006040
Short name T1401
Test name
Test status
Simulation time 232800718 ps
CPU time 0.9 seconds
Started Jun 27 06:37:26 PM PDT 24
Finished Jun 27 06:37:34 PM PDT 24
Peak memory 206300 kb
Host smart-91ad0e94-8f5a-4689-a265-bc0908acb962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10700
6040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.107006040
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.1778696281
Short name T1288
Test name
Test status
Simulation time 215065494 ps
CPU time 0.89 seconds
Started Jun 27 06:37:24 PM PDT 24
Finished Jun 27 06:37:32 PM PDT 24
Peak memory 206460 kb
Host smart-7d056e47-d049-4ad8-bdb9-253a4946465e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17786
96281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.1778696281
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.2457641015
Short name T458
Test name
Test status
Simulation time 172699649 ps
CPU time 0.8 seconds
Started Jun 27 06:37:26 PM PDT 24
Finished Jun 27 06:37:34 PM PDT 24
Peak memory 206280 kb
Host smart-f2b5efa5-ff99-4c5d-b242-8225a5a75e10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24576
41015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.2457641015
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.1259593427
Short name T1534
Test name
Test status
Simulation time 132465467 ps
CPU time 0.78 seconds
Started Jun 27 06:37:26 PM PDT 24
Finished Jun 27 06:37:34 PM PDT 24
Peak memory 206272 kb
Host smart-b010eadb-0f84-4615-bcb4-9b4ff40330e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12595
93427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.1259593427
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.3947495064
Short name T2192
Test name
Test status
Simulation time 149915839 ps
CPU time 0.77 seconds
Started Jun 27 06:37:25 PM PDT 24
Finished Jun 27 06:37:33 PM PDT 24
Peak memory 206244 kb
Host smart-b9f9c0e6-c242-45f3-8b79-3def303ea7e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39474
95064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.3947495064
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.410661839
Short name T1826
Test name
Test status
Simulation time 149977994 ps
CPU time 0.78 seconds
Started Jun 27 06:37:25 PM PDT 24
Finished Jun 27 06:37:33 PM PDT 24
Peak memory 206288 kb
Host smart-8a924338-6a52-4a5a-9c1d-8aa31a402721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41066
1839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.410661839
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.1257341811
Short name T463
Test name
Test status
Simulation time 216923817 ps
CPU time 0.96 seconds
Started Jun 27 06:37:25 PM PDT 24
Finished Jun 27 06:37:34 PM PDT 24
Peak memory 206288 kb
Host smart-c5e6ca5b-5f47-4977-89ce-8bbfcee59169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12573
41811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.1257341811
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.3561519960
Short name T791
Test name
Test status
Simulation time 5741356260 ps
CPU time 52.8 seconds
Started Jun 27 06:37:28 PM PDT 24
Finished Jun 27 06:38:28 PM PDT 24
Peak memory 206436 kb
Host smart-528f01ef-cc57-4695-b177-5b67a97e48ad
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3561519960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.3561519960
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.1825288381
Short name T614
Test name
Test status
Simulation time 164034228 ps
CPU time 0.77 seconds
Started Jun 27 06:37:27 PM PDT 24
Finished Jun 27 06:37:36 PM PDT 24
Peak memory 206288 kb
Host smart-34762b28-a1d8-4b28-b35c-cfede27099a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18252
88381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.1825288381
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.2001215536
Short name T343
Test name
Test status
Simulation time 158852919 ps
CPU time 0.82 seconds
Started Jun 27 06:37:24 PM PDT 24
Finished Jun 27 06:37:32 PM PDT 24
Peak memory 206260 kb
Host smart-4d622cf9-4550-4ae7-84e0-eae067c2b314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20012
15536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.2001215536
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.3745244586
Short name T662
Test name
Test status
Simulation time 5340397540 ps
CPU time 144.56 seconds
Started Jun 27 06:37:26 PM PDT 24
Finished Jun 27 06:39:58 PM PDT 24
Peak memory 206420 kb
Host smart-b5aec3db-1963-4ce2-86e6-f44201a92af3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37452
44586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.3745244586
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.741484045
Short name T536
Test name
Test status
Simulation time 36346381 ps
CPU time 0.66 seconds
Started Jun 27 06:37:43 PM PDT 24
Finished Jun 27 06:37:46 PM PDT 24
Peak memory 206352 kb
Host smart-9662116c-4c16-4aca-94eb-c43591c8c0ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=741484045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.741484045
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.965829755
Short name T2139
Test name
Test status
Simulation time 3474320250 ps
CPU time 3.89 seconds
Started Jun 27 06:37:22 PM PDT 24
Finished Jun 27 06:37:33 PM PDT 24
Peak memory 206360 kb
Host smart-e6b0f010-2a31-46e6-8df8-d8f824713f44
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=965829755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.965829755
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.2201098528
Short name T2341
Test name
Test status
Simulation time 13407763694 ps
CPU time 14.5 seconds
Started Jun 27 06:37:26 PM PDT 24
Finished Jun 27 06:37:49 PM PDT 24
Peak memory 206408 kb
Host smart-64c101e1-8b89-4f80-a849-460e95362e37
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2201098528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.2201098528
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.1619238917
Short name T1978
Test name
Test status
Simulation time 23386376169 ps
CPU time 23.27 seconds
Started Jun 27 06:37:26 PM PDT 24
Finished Jun 27 06:37:57 PM PDT 24
Peak memory 206488 kb
Host smart-3169f8bd-47c6-421d-93bb-c7f2e68d5c08
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1619238917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.1619238917
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.3971520791
Short name T462
Test name
Test status
Simulation time 156656991 ps
CPU time 0.78 seconds
Started Jun 27 06:37:25 PM PDT 24
Finished Jun 27 06:37:33 PM PDT 24
Peak memory 206268 kb
Host smart-4534d560-446b-4168-9d31-bf517a2a1937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39715
20791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.3971520791
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.3356391520
Short name T2552
Test name
Test status
Simulation time 147515574 ps
CPU time 0.75 seconds
Started Jun 27 06:37:26 PM PDT 24
Finished Jun 27 06:37:34 PM PDT 24
Peak memory 206268 kb
Host smart-b663b393-21c3-44f6-a233-972f8d0b3b14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33563
91520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.3356391520
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.850297618
Short name T1450
Test name
Test status
Simulation time 208570067 ps
CPU time 0.84 seconds
Started Jun 27 06:37:25 PM PDT 24
Finished Jun 27 06:37:33 PM PDT 24
Peak memory 206268 kb
Host smart-60390366-f2d6-451c-aac1-8e8cbce95f7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85029
7618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.850297618
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.3874931067
Short name T1478
Test name
Test status
Simulation time 771392232 ps
CPU time 1.75 seconds
Started Jun 27 06:37:28 PM PDT 24
Finished Jun 27 06:37:37 PM PDT 24
Peak memory 206368 kb
Host smart-9c80d615-0c37-4399-a457-0696054e5957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38749
31067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.3874931067
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.2787507608
Short name T1815
Test name
Test status
Simulation time 8640350426 ps
CPU time 16.87 seconds
Started Jun 27 06:37:24 PM PDT 24
Finished Jun 27 06:37:48 PM PDT 24
Peak memory 206432 kb
Host smart-2bfd8dda-d3c6-4b4d-b25b-9b9327f944aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27875
07608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.2787507608
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.3355034706
Short name T1370
Test name
Test status
Simulation time 325744792 ps
CPU time 1.29 seconds
Started Jun 27 06:37:29 PM PDT 24
Finished Jun 27 06:37:37 PM PDT 24
Peak memory 206292 kb
Host smart-dfc45b54-4c4a-48dd-8895-515958955f4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33550
34706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.3355034706
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.2055869394
Short name T591
Test name
Test status
Simulation time 198621409 ps
CPU time 0.82 seconds
Started Jun 27 06:37:28 PM PDT 24
Finished Jun 27 06:37:36 PM PDT 24
Peak memory 206228 kb
Host smart-272d9f78-a933-4fdf-8313-e9f3dc95934e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20558
69394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.2055869394
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.721783823
Short name T2122
Test name
Test status
Simulation time 37446069 ps
CPU time 0.67 seconds
Started Jun 27 06:37:25 PM PDT 24
Finished Jun 27 06:37:33 PM PDT 24
Peak memory 206276 kb
Host smart-33e07f92-b740-4e72-8c7a-859d8960657d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72178
3823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.721783823
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.2536333817
Short name T1903
Test name
Test status
Simulation time 1036189691 ps
CPU time 2.91 seconds
Started Jun 27 06:37:27 PM PDT 24
Finished Jun 27 06:37:38 PM PDT 24
Peak memory 206476 kb
Host smart-8409c123-5538-471c-b930-c68c6bb19570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25363
33817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.2536333817
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.3063547868
Short name T1712
Test name
Test status
Simulation time 198177160 ps
CPU time 2.28 seconds
Started Jun 27 06:37:24 PM PDT 24
Finished Jun 27 06:37:34 PM PDT 24
Peak memory 206360 kb
Host smart-ff4cb1a2-147d-4072-b338-b8527661e5d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30635
47868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.3063547868
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.1050731644
Short name T2308
Test name
Test status
Simulation time 182199258 ps
CPU time 0.79 seconds
Started Jun 27 06:37:24 PM PDT 24
Finished Jun 27 06:37:33 PM PDT 24
Peak memory 206284 kb
Host smart-8fe123c0-e9be-44e7-baf9-3ea2dabb144a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10507
31644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.1050731644
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.453727812
Short name T1526
Test name
Test status
Simulation time 137247926 ps
CPU time 0.78 seconds
Started Jun 27 06:37:28 PM PDT 24
Finished Jun 27 06:37:36 PM PDT 24
Peak memory 206248 kb
Host smart-f40953f1-acde-46f8-8c8a-a8bedaa9dbc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45372
7812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.453727812
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.3715230816
Short name T321
Test name
Test status
Simulation time 186059276 ps
CPU time 0.82 seconds
Started Jun 27 06:37:35 PM PDT 24
Finished Jun 27 06:37:38 PM PDT 24
Peak memory 206288 kb
Host smart-8ecb8df1-43d8-42bd-9eed-18f69cb22183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37152
30816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.3715230816
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_invalid_sync.650754638
Short name T1031
Test name
Test status
Simulation time 9228076338 ps
CPU time 68.25 seconds
Started Jun 27 06:37:27 PM PDT 24
Finished Jun 27 06:38:42 PM PDT 24
Peak memory 206476 kb
Host smart-dbef3dde-31b5-4429-ab00-5c4fb8accf37
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=650754638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.650754638
Directory /workspace/18.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.1698842520
Short name T598
Test name
Test status
Simulation time 228143640 ps
CPU time 0.92 seconds
Started Jun 27 06:37:25 PM PDT 24
Finished Jun 27 06:37:34 PM PDT 24
Peak memory 206272 kb
Host smart-d7a8133d-1392-4de8-a63f-4ea436002ed3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16988
42520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.1698842520
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.1807224297
Short name T2082
Test name
Test status
Simulation time 23326712592 ps
CPU time 21.1 seconds
Started Jun 27 06:37:27 PM PDT 24
Finished Jun 27 06:37:56 PM PDT 24
Peak memory 206348 kb
Host smart-ec3c0fd2-1916-45b9-9643-4e8356125c31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18072
24297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.1807224297
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.1736230233
Short name T512
Test name
Test status
Simulation time 3323051382 ps
CPU time 3.92 seconds
Started Jun 27 06:37:27 PM PDT 24
Finished Jun 27 06:37:38 PM PDT 24
Peak memory 206340 kb
Host smart-1de2ea2a-a091-4c6a-b62f-bdd1ebb7c626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17362
30233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.1736230233
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.1428533574
Short name T1654
Test name
Test status
Simulation time 8947819066 ps
CPU time 80.87 seconds
Started Jun 27 06:37:28 PM PDT 24
Finished Jun 27 06:38:56 PM PDT 24
Peak memory 206492 kb
Host smart-24654183-a2d9-465c-89a4-eb76b6b8afc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14285
33574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.1428533574
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.469184577
Short name T861
Test name
Test status
Simulation time 7694610733 ps
CPU time 213.56 seconds
Started Jun 27 06:37:28 PM PDT 24
Finished Jun 27 06:41:09 PM PDT 24
Peak memory 206468 kb
Host smart-cefe2e08-c4f6-4dfb-ba13-4f0a9f7e5255
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=469184577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.469184577
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.1248479438
Short name T2621
Test name
Test status
Simulation time 251589856 ps
CPU time 1.01 seconds
Started Jun 27 06:37:28 PM PDT 24
Finished Jun 27 06:37:36 PM PDT 24
Peak memory 206256 kb
Host smart-add8cccb-52b6-41a3-8398-80c2af78e68c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1248479438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.1248479438
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.3418148979
Short name T1640
Test name
Test status
Simulation time 190724959 ps
CPU time 0.89 seconds
Started Jun 27 06:37:45 PM PDT 24
Finished Jun 27 06:37:50 PM PDT 24
Peak memory 206276 kb
Host smart-2003223a-55f6-4c2f-99f4-47a0c68bc38d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34181
48979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.3418148979
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.1214768274
Short name T2033
Test name
Test status
Simulation time 5643720666 ps
CPU time 50.98 seconds
Started Jun 27 06:37:44 PM PDT 24
Finished Jun 27 06:38:38 PM PDT 24
Peak memory 206464 kb
Host smart-fad0e2f5-3c46-498f-b4c7-086fa3038eac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12147
68274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.1214768274
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.1929272248
Short name T1927
Test name
Test status
Simulation time 5595030295 ps
CPU time 54.7 seconds
Started Jun 27 06:37:47 PM PDT 24
Finished Jun 27 06:38:47 PM PDT 24
Peak memory 206468 kb
Host smart-8c2d0df6-962b-4407-90fa-7f6d19461db3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1929272248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.1929272248
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.3514981951
Short name T1188
Test name
Test status
Simulation time 172015548 ps
CPU time 0.81 seconds
Started Jun 27 06:37:43 PM PDT 24
Finished Jun 27 06:37:46 PM PDT 24
Peak memory 206296 kb
Host smart-0e1fb1d6-abb3-421f-806d-acea0cc04bf8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3514981951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.3514981951
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.3044197624
Short name T1744
Test name
Test status
Simulation time 146734969 ps
CPU time 0.76 seconds
Started Jun 27 06:37:46 PM PDT 24
Finished Jun 27 06:37:52 PM PDT 24
Peak memory 206276 kb
Host smart-f1b3ccc0-029d-4a7e-bb78-6b5755018e30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30441
97624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.3044197624
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.386244471
Short name T797
Test name
Test status
Simulation time 173988401 ps
CPU time 0.83 seconds
Started Jun 27 06:37:44 PM PDT 24
Finished Jun 27 06:37:47 PM PDT 24
Peak memory 206252 kb
Host smart-c93f069e-5cb9-4e3a-a3cd-56e06e197f48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38624
4471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.386244471
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.1406903801
Short name T1119
Test name
Test status
Simulation time 174166351 ps
CPU time 0.79 seconds
Started Jun 27 06:37:46 PM PDT 24
Finished Jun 27 06:37:52 PM PDT 24
Peak memory 206300 kb
Host smart-7e44ebfe-fa62-45b4-883d-102403445287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14069
03801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.1406903801
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.2630395116
Short name T2322
Test name
Test status
Simulation time 212240354 ps
CPU time 0.86 seconds
Started Jun 27 06:37:44 PM PDT 24
Finished Jun 27 06:37:48 PM PDT 24
Peak memory 206276 kb
Host smart-ff63ece7-c7a9-4bb2-8fdb-129c9d86db3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26303
95116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.2630395116
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.453380276
Short name T749
Test name
Test status
Simulation time 152646398 ps
CPU time 0.77 seconds
Started Jun 27 06:37:47 PM PDT 24
Finished Jun 27 06:37:53 PM PDT 24
Peak memory 206272 kb
Host smart-586c1acb-a12f-4da1-9970-656e3db91f0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45338
0276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.453380276
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.1049042307
Short name T1497
Test name
Test status
Simulation time 208997576 ps
CPU time 0.9 seconds
Started Jun 27 06:37:45 PM PDT 24
Finished Jun 27 06:37:49 PM PDT 24
Peak memory 206280 kb
Host smart-f7b4784f-8145-4207-8a60-1bc1b2c449e5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1049042307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.1049042307
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.337605642
Short name T441
Test name
Test status
Simulation time 147508155 ps
CPU time 0.79 seconds
Started Jun 27 06:37:43 PM PDT 24
Finished Jun 27 06:37:46 PM PDT 24
Peak memory 206260 kb
Host smart-c45a057a-ef59-4363-a6e0-af128889c606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33760
5642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.337605642
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.860832601
Short name T2565
Test name
Test status
Simulation time 56162254 ps
CPU time 0.7 seconds
Started Jun 27 06:37:44 PM PDT 24
Finished Jun 27 06:37:48 PM PDT 24
Peak memory 206432 kb
Host smart-b59b0664-90d7-4aae-809f-b85e8859f0ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86083
2601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.860832601
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.2617019203
Short name T1641
Test name
Test status
Simulation time 17597643474 ps
CPU time 40.13 seconds
Started Jun 27 06:37:46 PM PDT 24
Finished Jun 27 06:38:31 PM PDT 24
Peak memory 206452 kb
Host smart-04eeb994-d488-415b-9840-715cab27a66d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26170
19203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.2617019203
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.4232700912
Short name T847
Test name
Test status
Simulation time 220701806 ps
CPU time 0.88 seconds
Started Jun 27 06:37:44 PM PDT 24
Finished Jun 27 06:37:47 PM PDT 24
Peak memory 206264 kb
Host smart-64c5c1fc-ec29-4859-9708-5b9226918efb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42327
00912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.4232700912
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.2576076304
Short name T1767
Test name
Test status
Simulation time 268645447 ps
CPU time 0.89 seconds
Started Jun 27 06:37:47 PM PDT 24
Finished Jun 27 06:37:53 PM PDT 24
Peak memory 206288 kb
Host smart-32510a3a-e302-4a66-89cf-0314cf7975ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25760
76304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.2576076304
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.3403428651
Short name T1063
Test name
Test status
Simulation time 226139228 ps
CPU time 0.86 seconds
Started Jun 27 06:37:46 PM PDT 24
Finished Jun 27 06:37:51 PM PDT 24
Peak memory 206296 kb
Host smart-ab46515e-4df9-4c4c-882e-f38dd06387ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34034
28651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.3403428651
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.1017878254
Short name T1051
Test name
Test status
Simulation time 217914820 ps
CPU time 0.85 seconds
Started Jun 27 06:37:51 PM PDT 24
Finished Jun 27 06:37:57 PM PDT 24
Peak memory 206280 kb
Host smart-a93e30e5-dc4a-4494-8d3a-48e2864e8348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10178
78254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.1017878254
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.818298760
Short name T2625
Test name
Test status
Simulation time 168536596 ps
CPU time 0.89 seconds
Started Jun 27 06:37:48 PM PDT 24
Finished Jun 27 06:37:55 PM PDT 24
Peak memory 206284 kb
Host smart-6c739de5-85c6-4b8f-9b93-11920baec18a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81829
8760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.818298760
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.3874518793
Short name T928
Test name
Test status
Simulation time 163651453 ps
CPU time 0.78 seconds
Started Jun 27 06:37:43 PM PDT 24
Finished Jun 27 06:37:46 PM PDT 24
Peak memory 206276 kb
Host smart-f1f49c6e-8a70-486c-b471-542b84d7bb4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38745
18793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.3874518793
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.1530665486
Short name T1340
Test name
Test status
Simulation time 160439448 ps
CPU time 0.82 seconds
Started Jun 27 06:37:45 PM PDT 24
Finished Jun 27 06:37:51 PM PDT 24
Peak memory 206284 kb
Host smart-acfa26ba-9334-454a-9ced-ebbfb3f28a5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15306
65486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.1530665486
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.4278833390
Short name T1932
Test name
Test status
Simulation time 257725212 ps
CPU time 0.97 seconds
Started Jun 27 06:37:45 PM PDT 24
Finished Jun 27 06:37:50 PM PDT 24
Peak memory 206288 kb
Host smart-5df3861d-cba6-4d39-9d90-5e9669a37dd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42788
33390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.4278833390
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.381454654
Short name T1260
Test name
Test status
Simulation time 3852129703 ps
CPU time 35.11 seconds
Started Jun 27 06:37:46 PM PDT 24
Finished Jun 27 06:38:25 PM PDT 24
Peak memory 206488 kb
Host smart-9a8f9321-6dea-42a2-bc6d-57f42e0164c8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=381454654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.381454654
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.2313375441
Short name T400
Test name
Test status
Simulation time 161843800 ps
CPU time 0.83 seconds
Started Jun 27 06:37:47 PM PDT 24
Finished Jun 27 06:37:53 PM PDT 24
Peak memory 206300 kb
Host smart-9d62e06b-82d7-4857-b13f-764156e428e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23133
75441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.2313375441
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.960624364
Short name T1303
Test name
Test status
Simulation time 256910118 ps
CPU time 0.86 seconds
Started Jun 27 06:37:43 PM PDT 24
Finished Jun 27 06:37:46 PM PDT 24
Peak memory 206276 kb
Host smart-62c8da63-e612-40e2-9388-8daffa508ca4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96062
4364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.960624364
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.3460442714
Short name T2440
Test name
Test status
Simulation time 4233080270 ps
CPU time 30.49 seconds
Started Jun 27 06:37:47 PM PDT 24
Finished Jun 27 06:38:23 PM PDT 24
Peak memory 206468 kb
Host smart-8823687f-99ea-42dd-b29c-6048cb26896f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34604
42714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.3460442714
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.1814483916
Short name T1827
Test name
Test status
Simulation time 44266329 ps
CPU time 0.69 seconds
Started Jun 27 06:37:44 PM PDT 24
Finished Jun 27 06:37:47 PM PDT 24
Peak memory 206356 kb
Host smart-7d9d96d9-5e35-411f-af98-6df1c30b08b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1814483916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.1814483916
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.1120781584
Short name T15
Test name
Test status
Simulation time 3939364839 ps
CPU time 4.48 seconds
Started Jun 27 06:37:47 PM PDT 24
Finished Jun 27 06:37:57 PM PDT 24
Peak memory 206440 kb
Host smart-a7a10b78-cca3-4047-8b1f-3f4568f3ae89
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1120781584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.1120781584
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.3592037615
Short name T2271
Test name
Test status
Simulation time 13354865000 ps
CPU time 15.3 seconds
Started Jun 27 06:37:46 PM PDT 24
Finished Jun 27 06:38:06 PM PDT 24
Peak memory 206356 kb
Host smart-aa9e3498-e801-40e3-8233-5e1dfe71942a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3592037615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.3592037615
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.1986574705
Short name T12
Test name
Test status
Simulation time 23379465240 ps
CPU time 23.35 seconds
Started Jun 27 06:37:48 PM PDT 24
Finished Jun 27 06:38:17 PM PDT 24
Peak memory 206456 kb
Host smart-5e5c8a3c-4ef1-46f0-ae4e-6d4b21019b8d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1986574705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.1986574705
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.1651755361
Short name T1336
Test name
Test status
Simulation time 161190942 ps
CPU time 0.78 seconds
Started Jun 27 06:37:46 PM PDT 24
Finished Jun 27 06:37:52 PM PDT 24
Peak memory 206292 kb
Host smart-d0c5be90-4872-484c-b773-4d11595936c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16517
55361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.1651755361
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.2702258927
Short name T2368
Test name
Test status
Simulation time 163747861 ps
CPU time 0.76 seconds
Started Jun 27 06:37:45 PM PDT 24
Finished Jun 27 06:37:51 PM PDT 24
Peak memory 206276 kb
Host smart-1dde925b-f4c2-404a-b422-83b059f2e13a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27022
58927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.2702258927
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.801674029
Short name T626
Test name
Test status
Simulation time 200424445 ps
CPU time 0.88 seconds
Started Jun 27 06:37:46 PM PDT 24
Finished Jun 27 06:37:51 PM PDT 24
Peak memory 206292 kb
Host smart-f12f50a3-0cb2-4a29-81c1-0637bae3b0a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80167
4029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.801674029
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_device_address.1408197639
Short name T2340
Test name
Test status
Simulation time 6505519195 ps
CPU time 14.29 seconds
Started Jun 27 06:37:47 PM PDT 24
Finished Jun 27 06:38:06 PM PDT 24
Peak memory 206168 kb
Host smart-fd8ad6be-3a97-4e31-844b-079976aaa8a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14081
97639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.1408197639
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.2920300061
Short name T2138
Test name
Test status
Simulation time 333839575 ps
CPU time 1.12 seconds
Started Jun 27 06:37:47 PM PDT 24
Finished Jun 27 06:37:53 PM PDT 24
Peak memory 206012 kb
Host smart-13d3b5d2-f72d-42cb-9a8c-45849ba4d0a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29203
00061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.2920300061
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.481687811
Short name T2255
Test name
Test status
Simulation time 146474933 ps
CPU time 0.78 seconds
Started Jun 27 06:37:48 PM PDT 24
Finished Jun 27 06:37:55 PM PDT 24
Peak memory 206244 kb
Host smart-95cbebbd-5ccc-49a2-ad0f-96b04825333c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48168
7811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.481687811
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.4103244830
Short name T2562
Test name
Test status
Simulation time 55941644 ps
CPU time 0.68 seconds
Started Jun 27 06:37:48 PM PDT 24
Finished Jun 27 06:37:54 PM PDT 24
Peak memory 206216 kb
Host smart-af3cbe73-4987-4c9d-98e1-678ad588a9bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41032
44830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.4103244830
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.1731889049
Short name T1673
Test name
Test status
Simulation time 898574714 ps
CPU time 1.96 seconds
Started Jun 27 06:37:46 PM PDT 24
Finished Jun 27 06:37:53 PM PDT 24
Peak memory 206344 kb
Host smart-69018063-b15c-4303-b4d0-7fea9232f334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17318
89049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.1731889049
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.889950972
Short name T2287
Test name
Test status
Simulation time 355635967 ps
CPU time 2.45 seconds
Started Jun 27 06:37:46 PM PDT 24
Finished Jun 27 06:37:55 PM PDT 24
Peak memory 206292 kb
Host smart-fb20585a-3db2-4c34-a4b5-f7c3f85b6b89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88995
0972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.889950972
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.1336317769
Short name T2066
Test name
Test status
Simulation time 205596150 ps
CPU time 0.79 seconds
Started Jun 27 06:37:45 PM PDT 24
Finished Jun 27 06:37:49 PM PDT 24
Peak memory 206264 kb
Host smart-8a9bd461-dbc6-4d14-87c4-40a318376093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13363
17769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.1336317769
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.1699371416
Short name T2113
Test name
Test status
Simulation time 150870579 ps
CPU time 0.75 seconds
Started Jun 27 06:37:48 PM PDT 24
Finished Jun 27 06:37:54 PM PDT 24
Peak memory 206224 kb
Host smart-9a2a5e57-31b3-4cd3-b88c-a2a92c3c0d8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16993
71416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.1699371416
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.65105704
Short name T897
Test name
Test status
Simulation time 206402760 ps
CPU time 0.91 seconds
Started Jun 27 06:37:48 PM PDT 24
Finished Jun 27 06:37:55 PM PDT 24
Peak memory 206260 kb
Host smart-d8505d7a-98bc-41fd-829f-5e1b6214744a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65105
704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.65105704
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.3082394037
Short name T1435
Test name
Test status
Simulation time 191120264 ps
CPU time 0.81 seconds
Started Jun 27 06:37:47 PM PDT 24
Finished Jun 27 06:37:53 PM PDT 24
Peak memory 206280 kb
Host smart-7ccd217b-d3e1-4ff3-933b-c57613c94395
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30823
94037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.3082394037
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.898143549
Short name T919
Test name
Test status
Simulation time 23331831101 ps
CPU time 22.49 seconds
Started Jun 27 06:37:47 PM PDT 24
Finished Jun 27 06:38:15 PM PDT 24
Peak memory 206336 kb
Host smart-d7a912a2-0648-41a9-9c63-5bb87591f3e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89814
3549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.898143549
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.362046985
Short name T532
Test name
Test status
Simulation time 3336570147 ps
CPU time 3.6 seconds
Started Jun 27 06:37:50 PM PDT 24
Finished Jun 27 06:37:59 PM PDT 24
Peak memory 206236 kb
Host smart-6973c6f6-6a3e-4e68-8450-0d89a8a505f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36204
6985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.362046985
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.2302570539
Short name T1748
Test name
Test status
Simulation time 12910583122 ps
CPU time 353.65 seconds
Started Jun 27 06:37:48 PM PDT 24
Finished Jun 27 06:43:47 PM PDT 24
Peak memory 206512 kb
Host smart-7dcf1c16-0e10-4a1b-a120-d1d3975a3e53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23025
70539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.2302570539
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.3854504890
Short name T2053
Test name
Test status
Simulation time 7998516259 ps
CPU time 215.9 seconds
Started Jun 27 06:37:46 PM PDT 24
Finished Jun 27 06:41:26 PM PDT 24
Peak memory 206412 kb
Host smart-c82e1ab2-b4de-4556-a424-43e737bec6f6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3854504890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.3854504890
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.3283792715
Short name T318
Test name
Test status
Simulation time 245587109 ps
CPU time 0.88 seconds
Started Jun 27 06:37:44 PM PDT 24
Finished Jun 27 06:37:48 PM PDT 24
Peak memory 206296 kb
Host smart-b40e9d80-05db-431e-9c20-9db5371ec865
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3283792715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.3283792715
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.4115721499
Short name T717
Test name
Test status
Simulation time 215785097 ps
CPU time 0.98 seconds
Started Jun 27 06:37:48 PM PDT 24
Finished Jun 27 06:37:54 PM PDT 24
Peak memory 206272 kb
Host smart-4bd0bb2d-cc46-4c6f-b743-194ceec0a1a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41157
21499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.4115721499
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.3652345656
Short name T1190
Test name
Test status
Simulation time 5198248036 ps
CPU time 146.03 seconds
Started Jun 27 06:37:47 PM PDT 24
Finished Jun 27 06:40:19 PM PDT 24
Peak memory 206448 kb
Host smart-5eff4f71-b4c7-4a3e-9998-bb56e14811f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36523
45656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.3652345656
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.3886341922
Short name T2129
Test name
Test status
Simulation time 4828613330 ps
CPU time 33.53 seconds
Started Jun 27 06:37:45 PM PDT 24
Finished Jun 27 06:38:24 PM PDT 24
Peak memory 206412 kb
Host smart-3977e15f-2099-4a54-af69-61d1107de0e4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3886341922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.3886341922
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.3566818551
Short name T2468
Test name
Test status
Simulation time 158254140 ps
CPU time 0.78 seconds
Started Jun 27 06:37:47 PM PDT 24
Finished Jun 27 06:37:53 PM PDT 24
Peak memory 206304 kb
Host smart-58168c14-8bf5-436b-bd0c-29e8d86884d7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3566818551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.3566818551
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.2904189436
Short name T852
Test name
Test status
Simulation time 148705326 ps
CPU time 0.77 seconds
Started Jun 27 06:37:48 PM PDT 24
Finished Jun 27 06:37:55 PM PDT 24
Peak memory 206284 kb
Host smart-a671a639-1893-461b-b93b-a7a19f1a0427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29041
89436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.2904189436
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.2725970965
Short name T2453
Test name
Test status
Simulation time 199599672 ps
CPU time 0.84 seconds
Started Jun 27 06:37:46 PM PDT 24
Finished Jun 27 06:37:52 PM PDT 24
Peak memory 206272 kb
Host smart-9e23f7cd-2668-45d8-96fb-7e4f11c617f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27259
70965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.2725970965
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.677427918
Short name T498
Test name
Test status
Simulation time 257094034 ps
CPU time 0.97 seconds
Started Jun 27 06:37:47 PM PDT 24
Finished Jun 27 06:37:53 PM PDT 24
Peak memory 206280 kb
Host smart-b3b0c5d1-0015-4db2-bc2f-624c6aa1df74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67742
7918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.677427918
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.3374656605
Short name T2624
Test name
Test status
Simulation time 160945043 ps
CPU time 0.8 seconds
Started Jun 27 06:37:45 PM PDT 24
Finished Jun 27 06:37:49 PM PDT 24
Peak memory 206280 kb
Host smart-70f0a7a5-5f22-43cf-a3e9-8de7e244adca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33746
56605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.3374656605
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.3247367470
Short name T1456
Test name
Test status
Simulation time 212416789 ps
CPU time 0.87 seconds
Started Jun 27 06:37:45 PM PDT 24
Finished Jun 27 06:37:51 PM PDT 24
Peak memory 206248 kb
Host smart-92d1a42d-8560-489b-bac0-b4e65f4d5cd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32473
67470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.3247367470
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.3911299967
Short name T2407
Test name
Test status
Simulation time 161171861 ps
CPU time 0.77 seconds
Started Jun 27 06:37:49 PM PDT 24
Finished Jun 27 06:37:55 PM PDT 24
Peak memory 206280 kb
Host smart-bd2e864b-224f-4229-ba9d-5a3bb896ee24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39112
99967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.3911299967
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.1504119309
Short name T1004
Test name
Test status
Simulation time 223957322 ps
CPU time 0.99 seconds
Started Jun 27 06:37:48 PM PDT 24
Finished Jun 27 06:37:55 PM PDT 24
Peak memory 206272 kb
Host smart-281046a3-00a5-4b6e-a7da-10be5b3397f7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1504119309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.1504119309
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.1138582092
Short name T962
Test name
Test status
Simulation time 141815340 ps
CPU time 0.76 seconds
Started Jun 27 06:37:47 PM PDT 24
Finished Jun 27 06:37:53 PM PDT 24
Peak memory 206272 kb
Host smart-037ede97-23ce-47d7-9020-2495e06f799e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11385
82092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.1138582092
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.4059721354
Short name T2422
Test name
Test status
Simulation time 122508382 ps
CPU time 0.74 seconds
Started Jun 27 06:37:50 PM PDT 24
Finished Jun 27 06:37:56 PM PDT 24
Peak memory 206168 kb
Host smart-c8213659-2b63-4786-9c27-11a7b85229f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40597
21354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.4059721354
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.1967569521
Short name T256
Test name
Test status
Simulation time 21154845496 ps
CPU time 46.14 seconds
Started Jun 27 06:37:48 PM PDT 24
Finished Jun 27 06:38:40 PM PDT 24
Peak memory 206440 kb
Host smart-4a3de8b6-d77b-4960-8a1e-cbc1f3d2394d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19675
69521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.1967569521
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.613446071
Short name T768
Test name
Test status
Simulation time 159018855 ps
CPU time 0.83 seconds
Started Jun 27 06:37:50 PM PDT 24
Finished Jun 27 06:37:56 PM PDT 24
Peak memory 206156 kb
Host smart-e258ef87-2433-49de-b099-d26a3816d983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61344
6071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.613446071
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.3367763130
Short name T587
Test name
Test status
Simulation time 224454568 ps
CPU time 0.85 seconds
Started Jun 27 06:37:46 PM PDT 24
Finished Jun 27 06:37:52 PM PDT 24
Peak memory 206236 kb
Host smart-a132cff7-ca55-4cfa-abac-c179f34555db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33677
63130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.3367763130
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.2199955694
Short name T1290
Test name
Test status
Simulation time 204568662 ps
CPU time 0.93 seconds
Started Jun 27 06:37:48 PM PDT 24
Finished Jun 27 06:37:54 PM PDT 24
Peak memory 206324 kb
Host smart-d952a266-2e87-4257-b885-5fc7443d6456
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21999
55694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.2199955694
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.1282105910
Short name T1124
Test name
Test status
Simulation time 176642066 ps
CPU time 0.82 seconds
Started Jun 27 06:37:47 PM PDT 24
Finished Jun 27 06:37:53 PM PDT 24
Peak memory 206228 kb
Host smart-5e1af2cd-09ed-497e-b449-3c3c66ca510f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12821
05910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.1282105910
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.2494748951
Short name T1477
Test name
Test status
Simulation time 141251567 ps
CPU time 0.76 seconds
Started Jun 27 06:37:49 PM PDT 24
Finished Jun 27 06:37:55 PM PDT 24
Peak memory 206300 kb
Host smart-4e66094f-69d2-4996-a469-e13b0e46183a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24947
48951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.2494748951
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.3327695191
Short name T2314
Test name
Test status
Simulation time 169244134 ps
CPU time 0.8 seconds
Started Jun 27 06:37:49 PM PDT 24
Finished Jun 27 06:37:55 PM PDT 24
Peak memory 206280 kb
Host smart-1fbe7492-8957-4529-919d-505e792d3c5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33276
95191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.3327695191
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.993825122
Short name T2446
Test name
Test status
Simulation time 154050063 ps
CPU time 0.77 seconds
Started Jun 27 06:37:49 PM PDT 24
Finished Jun 27 06:37:55 PM PDT 24
Peak memory 206296 kb
Host smart-ae5771f8-fbc3-4572-8e17-3bbfb330a51b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99382
5122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.993825122
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.4029641351
Short name T988
Test name
Test status
Simulation time 274807415 ps
CPU time 0.94 seconds
Started Jun 27 06:37:47 PM PDT 24
Finished Jun 27 06:37:53 PM PDT 24
Peak memory 206284 kb
Host smart-f36b4705-cf00-468b-937d-1a40a3cc4fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40296
41351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.4029641351
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.1670769891
Short name T1519
Test name
Test status
Simulation time 7272156441 ps
CPU time 63.72 seconds
Started Jun 27 06:37:49 PM PDT 24
Finished Jun 27 06:38:58 PM PDT 24
Peak memory 206488 kb
Host smart-c8ccbedf-e5cd-4535-ad51-6a8b82dbccca
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1670769891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.1670769891
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.1153813015
Short name T141
Test name
Test status
Simulation time 190913479 ps
CPU time 0.94 seconds
Started Jun 27 06:37:48 PM PDT 24
Finished Jun 27 06:37:55 PM PDT 24
Peak memory 206276 kb
Host smart-800f3c09-e065-42b9-9310-2cf820fb0dee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11538
13015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.1153813015
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.1798570938
Short name T1660
Test name
Test status
Simulation time 155697382 ps
CPU time 0.76 seconds
Started Jun 27 06:37:45 PM PDT 24
Finished Jun 27 06:37:49 PM PDT 24
Peak memory 206276 kb
Host smart-3cacbfc5-5ca7-4145-adfb-59207ee6eb14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17985
70938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.1798570938
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.1503088232
Short name T580
Test name
Test status
Simulation time 5747205315 ps
CPU time 42.33 seconds
Started Jun 27 06:37:46 PM PDT 24
Finished Jun 27 06:38:33 PM PDT 24
Peak memory 206336 kb
Host smart-cffcea45-24ea-4fb9-822d-5feef61d3bb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15030
88232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.1503088232
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.1292034167
Short name T1912
Test name
Test status
Simulation time 34974604 ps
CPU time 0.65 seconds
Started Jun 27 06:34:41 PM PDT 24
Finished Jun 27 06:34:50 PM PDT 24
Peak memory 206352 kb
Host smart-6f5a667e-6528-4849-8e78-d733ec151383
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1292034167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.1292034167
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.3319230723
Short name T1322
Test name
Test status
Simulation time 3895441845 ps
CPU time 5.51 seconds
Started Jun 27 06:34:43 PM PDT 24
Finished Jun 27 06:34:58 PM PDT 24
Peak memory 206364 kb
Host smart-74cac9fd-b587-4249-a322-b65fe28388a3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3319230723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.3319230723
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.3766507951
Short name T2498
Test name
Test status
Simulation time 13433470690 ps
CPU time 12.64 seconds
Started Jun 27 06:34:41 PM PDT 24
Finished Jun 27 06:35:03 PM PDT 24
Peak memory 206428 kb
Host smart-f12d6b53-03af-4c11-a06a-bf3777ba6e6a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3766507951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.3766507951
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.501360335
Short name T2331
Test name
Test status
Simulation time 23418446561 ps
CPU time 22.63 seconds
Started Jun 27 06:34:40 PM PDT 24
Finished Jun 27 06:35:10 PM PDT 24
Peak memory 206576 kb
Host smart-8c57cf3e-cba5-454e-b25b-553e294aa0f9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=501360335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.501360335
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.1290268049
Short name T2156
Test name
Test status
Simulation time 188235727 ps
CPU time 0.88 seconds
Started Jun 27 06:34:40 PM PDT 24
Finished Jun 27 06:34:45 PM PDT 24
Peak memory 206280 kb
Host smart-f98e6ad2-77f6-43e1-89e5-d2ed97896756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12902
68049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.1290268049
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.1113726111
Short name T66
Test name
Test status
Simulation time 136473218 ps
CPU time 0.72 seconds
Started Jun 27 06:34:42 PM PDT 24
Finished Jun 27 06:34:52 PM PDT 24
Peak memory 206276 kb
Host smart-ff304b88-898c-4be3-ba6e-a121a6d8ca2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11137
26111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.1113726111
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.3416790415
Short name T409
Test name
Test status
Simulation time 187712641 ps
CPU time 0.78 seconds
Started Jun 27 06:34:45 PM PDT 24
Finished Jun 27 06:34:57 PM PDT 24
Peak memory 205980 kb
Host smart-cc42cf71-60e4-43a8-a6eb-e71240b121c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34167
90415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.3416790415
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.1984519492
Short name T835
Test name
Test status
Simulation time 257402356 ps
CPU time 0.99 seconds
Started Jun 27 06:34:41 PM PDT 24
Finished Jun 27 06:34:51 PM PDT 24
Peak memory 206248 kb
Host smart-3ad5b72f-7fe8-4049-812b-2783385a4c90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19845
19492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.1984519492
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.747973220
Short name T1582
Test name
Test status
Simulation time 670018503 ps
CPU time 1.66 seconds
Started Jun 27 06:34:43 PM PDT 24
Finished Jun 27 06:34:54 PM PDT 24
Peak memory 206372 kb
Host smart-f6df3477-c18f-4b0e-b5da-c07dcac612d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74797
3220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.747973220
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.2284633948
Short name T177
Test name
Test status
Simulation time 17351938059 ps
CPU time 32.97 seconds
Started Jun 27 06:34:39 PM PDT 24
Finished Jun 27 06:35:16 PM PDT 24
Peak memory 206388 kb
Host smart-c0e87d76-d62f-46be-974c-7d9cc34c40b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22846
33948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.2284633948
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.1262324545
Short name T700
Test name
Test status
Simulation time 341986754 ps
CPU time 1.16 seconds
Started Jun 27 06:34:41 PM PDT 24
Finished Jun 27 06:34:51 PM PDT 24
Peak memory 206260 kb
Host smart-d0489439-2b9c-4c07-9dc3-254732b88270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12623
24545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.1262324545
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.2665265453
Short name T740
Test name
Test status
Simulation time 145379592 ps
CPU time 0.73 seconds
Started Jun 27 06:34:41 PM PDT 24
Finished Jun 27 06:34:50 PM PDT 24
Peak memory 206272 kb
Host smart-8626bc24-4949-4ffc-80a5-6491ab2eb433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26652
65453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.2665265453
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.2269005673
Short name T600
Test name
Test status
Simulation time 69984321 ps
CPU time 0.67 seconds
Started Jun 27 06:34:41 PM PDT 24
Finished Jun 27 06:34:50 PM PDT 24
Peak memory 206284 kb
Host smart-1519d2cc-5000-4ce8-a2b2-a6f14750a5d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22690
05673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.2269005673
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.1597471411
Short name T1012
Test name
Test status
Simulation time 982049903 ps
CPU time 2.15 seconds
Started Jun 27 06:34:44 PM PDT 24
Finished Jun 27 06:34:56 PM PDT 24
Peak memory 206452 kb
Host smart-63fb14a5-1918-4bf0-9a28-6d456c84cf6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15974
71411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.1597471411
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.118083976
Short name T1275
Test name
Test status
Simulation time 253297777 ps
CPU time 1.74 seconds
Started Jun 27 06:34:43 PM PDT 24
Finished Jun 27 06:34:54 PM PDT 24
Peak memory 206448 kb
Host smart-f77272fb-26ee-49dd-9b0c-2c0ddf5d29aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11808
3976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.118083976
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.1701019726
Short name T2288
Test name
Test status
Simulation time 163075131 ps
CPU time 0.81 seconds
Started Jun 27 06:34:41 PM PDT 24
Finished Jun 27 06:34:48 PM PDT 24
Peak memory 206272 kb
Host smart-b8a72db1-c082-4c36-a4ab-75b5dac46a74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17010
19726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.1701019726
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.521525861
Short name T704
Test name
Test status
Simulation time 151567169 ps
CPU time 0.75 seconds
Started Jun 27 06:34:42 PM PDT 24
Finished Jun 27 06:34:51 PM PDT 24
Peak memory 206236 kb
Host smart-829e895f-ed79-4467-a14e-e72d6f675ec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52152
5861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.521525861
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.4286430478
Short name T1621
Test name
Test status
Simulation time 179940943 ps
CPU time 0.84 seconds
Started Jun 27 06:34:44 PM PDT 24
Finished Jun 27 06:34:54 PM PDT 24
Peak memory 206264 kb
Host smart-1e00bad8-8a8e-4457-981b-499ade7e99ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42864
30478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.4286430478
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.2955950993
Short name T424
Test name
Test status
Simulation time 166726012 ps
CPU time 0.84 seconds
Started Jun 27 06:34:41 PM PDT 24
Finished Jun 27 06:34:51 PM PDT 24
Peak memory 206224 kb
Host smart-f401c08c-69d2-4e71-ab75-6dd6d0134434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29559
50993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.2955950993
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.284553542
Short name T1718
Test name
Test status
Simulation time 23329939895 ps
CPU time 22.62 seconds
Started Jun 27 06:34:44 PM PDT 24
Finished Jun 27 06:35:17 PM PDT 24
Peak memory 206232 kb
Host smart-07687f67-ca91-47cc-abb0-d3236ef12818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28455
3542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.284553542
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.3821480436
Short name T2548
Test name
Test status
Simulation time 3343369306 ps
CPU time 3.76 seconds
Started Jun 27 06:34:43 PM PDT 24
Finished Jun 27 06:34:56 PM PDT 24
Peak memory 206296 kb
Host smart-f2c683ba-2961-4bea-a807-23abb5c3957c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38214
80436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.3821480436
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.1887411328
Short name T1884
Test name
Test status
Simulation time 10449388975 ps
CPU time 287.47 seconds
Started Jun 27 06:34:43 PM PDT 24
Finished Jun 27 06:39:40 PM PDT 24
Peak memory 206444 kb
Host smart-a5bb4997-3231-452d-9dde-31c489a22862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18874
11328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.1887411328
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.4062718161
Short name T1535
Test name
Test status
Simulation time 4826786571 ps
CPU time 42.75 seconds
Started Jun 27 06:34:43 PM PDT 24
Finished Jun 27 06:35:35 PM PDT 24
Peak memory 206464 kb
Host smart-8b71e940-4091-4792-8815-2589a33812ba
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4062718161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.4062718161
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.4110629642
Short name T2136
Test name
Test status
Simulation time 248614556 ps
CPU time 0.87 seconds
Started Jun 27 06:34:44 PM PDT 24
Finished Jun 27 06:34:56 PM PDT 24
Peak memory 206256 kb
Host smart-2b3bd2fc-ab76-49f6-a054-75d77c8e19e6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4110629642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.4110629642
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.1059756408
Short name T1866
Test name
Test status
Simulation time 235752414 ps
CPU time 0.92 seconds
Started Jun 27 06:34:44 PM PDT 24
Finished Jun 27 06:34:55 PM PDT 24
Peak memory 206304 kb
Host smart-273b1c44-9734-45ba-ae54-99163e23ee63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10597
56408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.1059756408
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.688824587
Short name T1940
Test name
Test status
Simulation time 5042998098 ps
CPU time 34.1 seconds
Started Jun 27 06:34:45 PM PDT 24
Finished Jun 27 06:35:30 PM PDT 24
Peak memory 206460 kb
Host smart-4632856b-c9db-477f-ab91-a171345b46db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68882
4587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.688824587
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.1580173286
Short name T1068
Test name
Test status
Simulation time 4943457877 ps
CPU time 33.82 seconds
Started Jun 27 06:34:44 PM PDT 24
Finished Jun 27 06:35:28 PM PDT 24
Peak memory 206420 kb
Host smart-0c93abc1-394e-4af6-85f4-485b5f1ca35e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1580173286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.1580173286
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.1699558100
Short name T2593
Test name
Test status
Simulation time 169156920 ps
CPU time 0.8 seconds
Started Jun 27 06:34:45 PM PDT 24
Finished Jun 27 06:34:56 PM PDT 24
Peak memory 206264 kb
Host smart-394ee159-0d3f-4a37-a330-80b76645ad54
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1699558100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.1699558100
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.2024336874
Short name T582
Test name
Test status
Simulation time 147847628 ps
CPU time 0.76 seconds
Started Jun 27 06:34:42 PM PDT 24
Finished Jun 27 06:34:52 PM PDT 24
Peak memory 206284 kb
Host smart-d473b1a0-942e-40f1-a53d-1c4a184ebe16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20243
36874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.2024336874
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.1025601997
Short name T2556
Test name
Test status
Simulation time 300071957 ps
CPU time 0.88 seconds
Started Jun 27 06:34:44 PM PDT 24
Finished Jun 27 06:34:55 PM PDT 24
Peak memory 206300 kb
Host smart-42f80629-7de2-407c-8073-f7c158b4d035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10256
01997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.1025601997
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.2306775862
Short name T1880
Test name
Test status
Simulation time 213492802 ps
CPU time 0.82 seconds
Started Jun 27 06:34:44 PM PDT 24
Finished Jun 27 06:34:54 PM PDT 24
Peak memory 206272 kb
Host smart-e9857995-75d3-4e59-8755-0994953aeaf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23067
75862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.2306775862
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.841014155
Short name T2191
Test name
Test status
Simulation time 173417050 ps
CPU time 0.78 seconds
Started Jun 27 06:34:44 PM PDT 24
Finished Jun 27 06:34:55 PM PDT 24
Peak memory 206272 kb
Host smart-5dba0f23-20a6-411a-a0c8-6fedca648b62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84101
4155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.841014155
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.1679603591
Short name T657
Test name
Test status
Simulation time 163966462 ps
CPU time 0.81 seconds
Started Jun 27 06:34:44 PM PDT 24
Finished Jun 27 06:34:55 PM PDT 24
Peak memory 206300 kb
Host smart-3b30fc66-cf51-4fd6-9729-d53fd7b82142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16796
03591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.1679603591
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.2230173814
Short name T2089
Test name
Test status
Simulation time 153767210 ps
CPU time 0.77 seconds
Started Jun 27 06:34:47 PM PDT 24
Finished Jun 27 06:34:59 PM PDT 24
Peak memory 206308 kb
Host smart-ae04e7ad-368e-4d9d-9ada-f9cbc3ee913e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22301
73814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.2230173814
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.1278668343
Short name T1819
Test name
Test status
Simulation time 230559057 ps
CPU time 0.91 seconds
Started Jun 27 06:34:47 PM PDT 24
Finished Jun 27 06:34:58 PM PDT 24
Peak memory 206312 kb
Host smart-a48171f4-9be1-45e8-a57e-f9abeed08254
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1278668343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.1278668343
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.1275015471
Short name T203
Test name
Test status
Simulation time 195492066 ps
CPU time 0.88 seconds
Started Jun 27 06:34:45 PM PDT 24
Finished Jun 27 06:34:56 PM PDT 24
Peak memory 206304 kb
Host smart-f3db635a-86ae-4728-99b7-962b086bf63b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12750
15471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.1275015471
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.1028702356
Short name T2244
Test name
Test status
Simulation time 166825601 ps
CPU time 0.8 seconds
Started Jun 27 06:34:47 PM PDT 24
Finished Jun 27 06:34:59 PM PDT 24
Peak memory 206288 kb
Host smart-c2baf2b5-0acd-4f2d-9246-9318a7eea7cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10287
02356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.1028702356
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.2737697394
Short name T1161
Test name
Test status
Simulation time 41467666 ps
CPU time 0.66 seconds
Started Jun 27 06:34:47 PM PDT 24
Finished Jun 27 06:34:59 PM PDT 24
Peak memory 206284 kb
Host smart-33ad943b-7b8a-40e5-b001-7e2e77569fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27376
97394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.2737697394
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.2899937698
Short name T1285
Test name
Test status
Simulation time 16516921551 ps
CPU time 34.5 seconds
Started Jun 27 06:34:56 PM PDT 24
Finished Jun 27 06:35:41 PM PDT 24
Peak memory 206512 kb
Host smart-225c918c-8ca3-4db2-8561-434b3d63c2e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28999
37698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.2899937698
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.543510324
Short name T381
Test name
Test status
Simulation time 203824859 ps
CPU time 0.87 seconds
Started Jun 27 06:34:42 PM PDT 24
Finished Jun 27 06:34:51 PM PDT 24
Peak memory 206264 kb
Host smart-3b5486fc-29e0-4a4f-8a0c-91437e9691af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54351
0324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.543510324
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.2897326279
Short name T776
Test name
Test status
Simulation time 203174303 ps
CPU time 0.86 seconds
Started Jun 27 06:34:44 PM PDT 24
Finished Jun 27 06:34:55 PM PDT 24
Peak memory 206312 kb
Host smart-6ee1bbfa-7c2c-4b2f-9aa4-0eac8924b577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28973
26279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.2897326279
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.3944105672
Short name T848
Test name
Test status
Simulation time 4794198070 ps
CPU time 127.63 seconds
Started Jun 27 06:34:57 PM PDT 24
Finished Jun 27 06:37:15 PM PDT 24
Peak memory 206420 kb
Host smart-dda394dc-56d7-47e9-bf11-bda85c43099b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3944105672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.3944105672
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.1717881373
Short name T715
Test name
Test status
Simulation time 7978670488 ps
CPU time 213.03 seconds
Started Jun 27 06:34:57 PM PDT 24
Finished Jun 27 06:38:40 PM PDT 24
Peak memory 206404 kb
Host smart-5de0a787-91c0-4987-b761-d2ae9a107fb5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1717881373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.1717881373
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.624214708
Short name T2339
Test name
Test status
Simulation time 12026254362 ps
CPU time 240.77 seconds
Started Jun 27 06:34:42 PM PDT 24
Finished Jun 27 06:38:51 PM PDT 24
Peak memory 205592 kb
Host smart-3af3ec4d-996b-46e0-ba17-c0cebd6fcfa2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=624214708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.624214708
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.1468973814
Short name T1852
Test name
Test status
Simulation time 198508921 ps
CPU time 0.9 seconds
Started Jun 27 06:34:43 PM PDT 24
Finished Jun 27 06:34:54 PM PDT 24
Peak memory 206320 kb
Host smart-9dd4a164-8fb3-4958-b489-8b8edb9a991e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14689
73814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.1468973814
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.1282028188
Short name T1610
Test name
Test status
Simulation time 191305711 ps
CPU time 0.93 seconds
Started Jun 27 06:34:57 PM PDT 24
Finished Jun 27 06:35:08 PM PDT 24
Peak memory 206272 kb
Host smart-cb3c4bbd-baef-4c8d-98d2-ab5da4f91ff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12820
28188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.1282028188
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.4270646376
Short name T2109
Test name
Test status
Simulation time 201051988 ps
CPU time 0.8 seconds
Started Jun 27 06:34:57 PM PDT 24
Finished Jun 27 06:35:08 PM PDT 24
Peak memory 206276 kb
Host smart-ef2fb6ce-9308-4431-933e-2d62fb22739a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42706
46376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.4270646376
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.452971622
Short name T76
Test name
Test status
Simulation time 178777785 ps
CPU time 0.8 seconds
Started Jun 27 06:34:57 PM PDT 24
Finished Jun 27 06:35:08 PM PDT 24
Peak memory 206276 kb
Host smart-96af68fe-70f9-4e29-bc47-9a9a5fdc89f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45297
1622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.452971622
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.1213755593
Short name T197
Test name
Test status
Simulation time 818017035 ps
CPU time 1.64 seconds
Started Jun 27 06:34:41 PM PDT 24
Finished Jun 27 06:34:51 PM PDT 24
Peak memory 224052 kb
Host smart-f20ca432-273c-45db-b1c6-8d32eb8ec7d8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1213755593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.1213755593
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.3301226276
Short name T56
Test name
Test status
Simulation time 402131994 ps
CPU time 1.22 seconds
Started Jun 27 06:34:42 PM PDT 24
Finished Jun 27 06:34:52 PM PDT 24
Peak memory 206268 kb
Host smart-a71e5311-b6d2-4e7b-9415-abc8639e5a6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33012
26276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.3301226276
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.2505658829
Short name T711
Test name
Test status
Simulation time 155087526 ps
CPU time 0.74 seconds
Started Jun 27 06:34:57 PM PDT 24
Finished Jun 27 06:35:08 PM PDT 24
Peak memory 206272 kb
Host smart-82213582-d7a4-4ee5-81f7-fc6d42842c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25056
58829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.2505658829
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.116096614
Short name T2522
Test name
Test status
Simulation time 155790517 ps
CPU time 0.89 seconds
Started Jun 27 06:34:57 PM PDT 24
Finished Jun 27 06:35:08 PM PDT 24
Peak memory 206288 kb
Host smart-e93ed254-ea59-478b-8f82-aa894220204f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11609
6614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.116096614
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.3771429942
Short name T617
Test name
Test status
Simulation time 229028288 ps
CPU time 0.91 seconds
Started Jun 27 06:34:42 PM PDT 24
Finished Jun 27 06:34:51 PM PDT 24
Peak memory 205504 kb
Host smart-4e85eb24-3758-407f-95d8-37ac8af1a79f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37714
29942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.3771429942
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.1937449653
Short name T1459
Test name
Test status
Simulation time 3498179422 ps
CPU time 92.25 seconds
Started Jun 27 06:34:57 PM PDT 24
Finished Jun 27 06:36:39 PM PDT 24
Peak memory 206412 kb
Host smart-f989c843-7551-411c-89ac-76110f62b1bb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1937449653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.1937449653
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.1216267584
Short name T588
Test name
Test status
Simulation time 165478839 ps
CPU time 0.8 seconds
Started Jun 27 06:34:42 PM PDT 24
Finished Jun 27 06:34:51 PM PDT 24
Peak memory 206284 kb
Host smart-1372fda3-f27d-4464-bda3-82a1495eae4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12162
67584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.1216267584
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.985178185
Short name T2193
Test name
Test status
Simulation time 245649750 ps
CPU time 0.88 seconds
Started Jun 27 06:34:45 PM PDT 24
Finished Jun 27 06:34:57 PM PDT 24
Peak memory 206288 kb
Host smart-bcf113cd-8a00-4b65-b7a4-46525c405d1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98517
8185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.985178185
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.316231120
Short name T446
Test name
Test status
Simulation time 4477347779 ps
CPU time 43.05 seconds
Started Jun 27 06:34:40 PM PDT 24
Finished Jun 27 06:35:27 PM PDT 24
Peak memory 206388 kb
Host smart-67b9aa99-a055-42f7-a6e8-0d621902519d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31623
1120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.316231120
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.1204601441
Short name T744
Test name
Test status
Simulation time 34533226 ps
CPU time 0.64 seconds
Started Jun 27 06:38:07 PM PDT 24
Finished Jun 27 06:38:12 PM PDT 24
Peak memory 206364 kb
Host smart-b4ceffc5-fdea-4499-828b-c4cd9f3697fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1204601441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.1204601441
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.3550110393
Short name T643
Test name
Test status
Simulation time 4266364628 ps
CPU time 4.56 seconds
Started Jun 27 06:38:05 PM PDT 24
Finished Jun 27 06:38:12 PM PDT 24
Peak memory 206256 kb
Host smart-2b0fa098-0e11-409a-9677-687631ea4b63
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3550110393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.3550110393
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.714401259
Short name T1289
Test name
Test status
Simulation time 13345193951 ps
CPU time 14.04 seconds
Started Jun 27 06:37:59 PM PDT 24
Finished Jun 27 06:38:14 PM PDT 24
Peak memory 206312 kb
Host smart-41a86bd9-0fd7-47f0-a94c-834345d171a4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=714401259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.714401259
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.1096249142
Short name T457
Test name
Test status
Simulation time 23395294777 ps
CPU time 21.08 seconds
Started Jun 27 06:38:05 PM PDT 24
Finished Jun 27 06:38:30 PM PDT 24
Peak memory 206416 kb
Host smart-ae94fdc3-f3ff-4950-a7f4-f353bca1ad2e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1096249142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.1096249142
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.1590110343
Short name T352
Test name
Test status
Simulation time 170830909 ps
CPU time 0.8 seconds
Started Jun 27 06:38:01 PM PDT 24
Finished Jun 27 06:38:03 PM PDT 24
Peak memory 206300 kb
Host smart-54a15cba-f300-49dd-a8d2-706998703ff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15901
10343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.1590110343
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.1743604737
Short name T62
Test name
Test status
Simulation time 181052236 ps
CPU time 0.84 seconds
Started Jun 27 06:38:00 PM PDT 24
Finished Jun 27 06:38:02 PM PDT 24
Peak memory 206284 kb
Host smart-7ca5569f-2dd9-44d3-b467-bdaa646db96d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17436
04737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.1743604737
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.2471420813
Short name T2622
Test name
Test status
Simulation time 285909549 ps
CPU time 1.05 seconds
Started Jun 27 06:38:03 PM PDT 24
Finished Jun 27 06:38:07 PM PDT 24
Peak memory 206260 kb
Host smart-53df76a8-c77a-48bf-8254-fb9bfbd38523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24714
20813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.2471420813
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.279825000
Short name T1965
Test name
Test status
Simulation time 788587129 ps
CPU time 1.99 seconds
Started Jun 27 06:38:02 PM PDT 24
Finished Jun 27 06:38:05 PM PDT 24
Peak memory 206428 kb
Host smart-38b5ccf5-0092-4232-95b7-85613c6ed7da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27982
5000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.279825000
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.572182849
Short name T2471
Test name
Test status
Simulation time 7878794145 ps
CPU time 13.22 seconds
Started Jun 27 06:38:05 PM PDT 24
Finished Jun 27 06:38:22 PM PDT 24
Peak memory 206452 kb
Host smart-5f4f03de-604b-406d-a778-e9c8717d6a8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57218
2849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.572182849
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.2999098414
Short name T1682
Test name
Test status
Simulation time 363051675 ps
CPU time 1.27 seconds
Started Jun 27 06:38:02 PM PDT 24
Finished Jun 27 06:38:05 PM PDT 24
Peak memory 206268 kb
Host smart-5399b174-ee4f-4ba0-8ffd-8d3272c0113c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29990
98414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.2999098414
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.229873198
Short name T48
Test name
Test status
Simulation time 140526888 ps
CPU time 0.76 seconds
Started Jun 27 06:38:00 PM PDT 24
Finished Jun 27 06:38:02 PM PDT 24
Peak memory 206280 kb
Host smart-d295d0ea-8662-4fd6-bcd1-5d09a2d4163b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22987
3198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.229873198
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.1715283825
Short name T1563
Test name
Test status
Simulation time 57867725 ps
CPU time 0.69 seconds
Started Jun 27 06:38:07 PM PDT 24
Finished Jun 27 06:38:12 PM PDT 24
Peak memory 205736 kb
Host smart-ae17cd62-2ae4-430a-94c9-5dbac389461e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17152
83825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.1715283825
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.1360189880
Short name T419
Test name
Test status
Simulation time 858512854 ps
CPU time 2.2 seconds
Started Jun 27 06:37:59 PM PDT 24
Finished Jun 27 06:38:03 PM PDT 24
Peak memory 206376 kb
Host smart-11076c7d-d1fd-4f55-908b-f98ac2e27d46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13601
89880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.1360189880
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.2129404329
Short name T1501
Test name
Test status
Simulation time 245914945 ps
CPU time 1.61 seconds
Started Jun 27 06:37:57 PM PDT 24
Finished Jun 27 06:38:00 PM PDT 24
Peak memory 206452 kb
Host smart-6cab9b79-b051-4183-a312-1908c72954ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21294
04329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.2129404329
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.1752165747
Short name T1928
Test name
Test status
Simulation time 229259476 ps
CPU time 0.92 seconds
Started Jun 27 06:38:08 PM PDT 24
Finished Jun 27 06:38:14 PM PDT 24
Peak memory 206296 kb
Host smart-049f4d70-d76f-4b36-87bf-65fc445db585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17521
65747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.1752165747
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.1495105653
Short name T1172
Test name
Test status
Simulation time 145989703 ps
CPU time 0.75 seconds
Started Jun 27 06:38:03 PM PDT 24
Finished Jun 27 06:38:05 PM PDT 24
Peak memory 206288 kb
Host smart-c9741f66-8270-412a-abfe-e01be2186293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14951
05653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.1495105653
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.2062531911
Short name T2436
Test name
Test status
Simulation time 244243940 ps
CPU time 0.9 seconds
Started Jun 27 06:38:05 PM PDT 24
Finished Jun 27 06:38:09 PM PDT 24
Peak memory 206272 kb
Host smart-e48293cb-e9bb-490f-b188-2999fb267a5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20625
31911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.2062531911
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_invalid_sync.2104774769
Short name T2124
Test name
Test status
Simulation time 5299587933 ps
CPU time 143.28 seconds
Started Jun 27 06:38:09 PM PDT 24
Finished Jun 27 06:40:38 PM PDT 24
Peak memory 206468 kb
Host smart-f74fe98c-0686-41c1-8cbc-ebd0d3aa0a3b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2104774769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_invalid_sync.2104774769
Directory /workspace/20.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.1341665972
Short name T2173
Test name
Test status
Simulation time 217110371 ps
CPU time 0.87 seconds
Started Jun 27 06:38:00 PM PDT 24
Finished Jun 27 06:38:03 PM PDT 24
Peak memory 206272 kb
Host smart-9066d552-2b05-477b-8666-0bb78efc1724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13416
65972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.1341665972
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.3596124016
Short name T994
Test name
Test status
Simulation time 23347664153 ps
CPU time 25.59 seconds
Started Jun 27 06:37:58 PM PDT 24
Finished Jun 27 06:38:25 PM PDT 24
Peak memory 206344 kb
Host smart-f850de65-def1-4241-a4cb-224c72af476a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35961
24016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.3596124016
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.3151008344
Short name T2226
Test name
Test status
Simulation time 3363040882 ps
CPU time 3.68 seconds
Started Jun 27 06:38:01 PM PDT 24
Finished Jun 27 06:38:06 PM PDT 24
Peak memory 206332 kb
Host smart-99504c33-3636-494d-8580-f85e881e65c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31510
08344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.3151008344
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.441112786
Short name T1841
Test name
Test status
Simulation time 9928993866 ps
CPU time 93.87 seconds
Started Jun 27 06:38:00 PM PDT 24
Finished Jun 27 06:39:35 PM PDT 24
Peak memory 206492 kb
Host smart-0d62c235-6a4e-4637-b75c-f7e3df7e0986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44111
2786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.441112786
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.4229217944
Short name T1716
Test name
Test status
Simulation time 5639998680 ps
CPU time 55.51 seconds
Started Jun 27 06:37:58 PM PDT 24
Finished Jun 27 06:38:55 PM PDT 24
Peak memory 206496 kb
Host smart-58821dcc-7f46-4353-890f-afae7900ce1d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4229217944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.4229217944
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.2516810351
Short name T373
Test name
Test status
Simulation time 263526201 ps
CPU time 0.88 seconds
Started Jun 27 06:38:05 PM PDT 24
Finished Jun 27 06:38:09 PM PDT 24
Peak memory 206260 kb
Host smart-2e097dc6-f61a-45a8-b8c2-3c1a2d0fb0e9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2516810351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.2516810351
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.1379824647
Short name T1442
Test name
Test status
Simulation time 186845548 ps
CPU time 0.93 seconds
Started Jun 27 06:38:00 PM PDT 24
Finished Jun 27 06:38:02 PM PDT 24
Peak memory 206300 kb
Host smart-472d6242-7416-4986-aeac-cf6060edc86c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13798
24647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.1379824647
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.3103339333
Short name T2583
Test name
Test status
Simulation time 6301107330 ps
CPU time 60.96 seconds
Started Jun 27 06:38:02 PM PDT 24
Finished Jun 27 06:39:04 PM PDT 24
Peak memory 206396 kb
Host smart-93fe5775-e6f0-4fb7-ae5b-cb8519dc9350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31033
39333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.3103339333
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.2419738249
Short name T1467
Test name
Test status
Simulation time 3635350509 ps
CPU time 28.4 seconds
Started Jun 27 06:38:00 PM PDT 24
Finished Jun 27 06:38:30 PM PDT 24
Peak memory 206556 kb
Host smart-aa8250dd-c3f0-44db-935f-04f0b50f8c07
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2419738249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.2419738249
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.3556901724
Short name T412
Test name
Test status
Simulation time 183223411 ps
CPU time 0.82 seconds
Started Jun 27 06:38:05 PM PDT 24
Finished Jun 27 06:38:10 PM PDT 24
Peak memory 206292 kb
Host smart-2069bc34-6510-4a45-b4ff-20bcab08a267
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3556901724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.3556901724
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.3134438856
Short name T1686
Test name
Test status
Simulation time 164822237 ps
CPU time 0.84 seconds
Started Jun 27 06:38:00 PM PDT 24
Finished Jun 27 06:38:03 PM PDT 24
Peak memory 206300 kb
Host smart-11633f02-2dad-4b3e-a4b0-700a37340f9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31344
38856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.3134438856
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.4180229927
Short name T1581
Test name
Test status
Simulation time 174951313 ps
CPU time 0.82 seconds
Started Jun 27 06:38:06 PM PDT 24
Finished Jun 27 06:38:11 PM PDT 24
Peak memory 206268 kb
Host smart-7f624f24-f3c7-4b1e-9f6f-fdfb48e99f7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41802
29927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.4180229927
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.2415531257
Short name T1737
Test name
Test status
Simulation time 190481179 ps
CPU time 0.84 seconds
Started Jun 27 06:37:59 PM PDT 24
Finished Jun 27 06:38:02 PM PDT 24
Peak memory 206240 kb
Host smart-fc2d260d-c98c-4814-bbfb-e20009c81a2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24155
31257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.2415531257
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.4175538785
Short name T1231
Test name
Test status
Simulation time 162257498 ps
CPU time 0.82 seconds
Started Jun 27 06:38:07 PM PDT 24
Finished Jun 27 06:38:13 PM PDT 24
Peak memory 206196 kb
Host smart-2505df4b-0dd7-466a-8e86-845553be15ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41755
38785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.4175538785
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.1961570567
Short name T829
Test name
Test status
Simulation time 192468823 ps
CPU time 0.81 seconds
Started Jun 27 06:38:02 PM PDT 24
Finished Jun 27 06:38:04 PM PDT 24
Peak memory 206260 kb
Host smart-e9d4dfd2-aeaf-4de6-bd66-242f7e21dc62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19615
70567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.1961570567
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.2327443517
Short name T849
Test name
Test status
Simulation time 194225009 ps
CPU time 0.92 seconds
Started Jun 27 06:38:05 PM PDT 24
Finished Jun 27 06:38:08 PM PDT 24
Peak memory 206192 kb
Host smart-c61e03c7-c1ed-4210-9cb8-ae650d8158c7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2327443517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.2327443517
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.2217668861
Short name T1833
Test name
Test status
Simulation time 141115120 ps
CPU time 0.75 seconds
Started Jun 27 06:37:58 PM PDT 24
Finished Jun 27 06:37:59 PM PDT 24
Peak memory 206224 kb
Host smart-8db8dce0-198d-4366-be53-e564baec06f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22176
68861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.2217668861
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.961865114
Short name T1960
Test name
Test status
Simulation time 57010099 ps
CPU time 0.68 seconds
Started Jun 27 06:38:02 PM PDT 24
Finished Jun 27 06:38:04 PM PDT 24
Peak memory 206264 kb
Host smart-7d57a33c-9fdb-44e3-baf2-bac8535fddbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96186
5114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.961865114
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.3473993981
Short name T254
Test name
Test status
Simulation time 8358942308 ps
CPU time 17.51 seconds
Started Jun 27 06:38:03 PM PDT 24
Finished Jun 27 06:38:22 PM PDT 24
Peak memory 206448 kb
Host smart-646d5834-d3f7-499d-8918-3c2db1d79b35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34739
93981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.3473993981
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.1802683492
Short name T2613
Test name
Test status
Simulation time 204239041 ps
CPU time 0.84 seconds
Started Jun 27 06:38:04 PM PDT 24
Finished Jun 27 06:38:07 PM PDT 24
Peak memory 206168 kb
Host smart-94543010-379b-4645-9e72-96b4e8b2cb4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18026
83492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.1802683492
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.1464707460
Short name T1070
Test name
Test status
Simulation time 262241162 ps
CPU time 0.91 seconds
Started Jun 27 06:37:59 PM PDT 24
Finished Jun 27 06:38:02 PM PDT 24
Peak memory 206284 kb
Host smart-7ffc6b05-08e4-44b0-b223-85006b097260
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14647
07460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.1464707460
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.392153372
Short name T1595
Test name
Test status
Simulation time 191565380 ps
CPU time 0.79 seconds
Started Jun 27 06:38:08 PM PDT 24
Finished Jun 27 06:38:14 PM PDT 24
Peak memory 206300 kb
Host smart-b5d8cd49-0f12-40af-8941-5786184f654b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39215
3372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.392153372
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.3278539546
Short name T1461
Test name
Test status
Simulation time 203193919 ps
CPU time 0.89 seconds
Started Jun 27 06:38:00 PM PDT 24
Finished Jun 27 06:38:02 PM PDT 24
Peak memory 206236 kb
Host smart-e87525c8-8421-4efc-9930-9f6ae1f5a45a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32785
39546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.3278539546
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.3330663494
Short name T1765
Test name
Test status
Simulation time 210717958 ps
CPU time 0.8 seconds
Started Jun 27 06:38:03 PM PDT 24
Finished Jun 27 06:38:06 PM PDT 24
Peak memory 206268 kb
Host smart-e6bf7732-ee86-4496-b25d-75bdee663459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33306
63494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.3330663494
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.2762711419
Short name T502
Test name
Test status
Simulation time 158870005 ps
CPU time 0.75 seconds
Started Jun 27 06:38:05 PM PDT 24
Finished Jun 27 06:38:10 PM PDT 24
Peak memory 206272 kb
Host smart-cdfb3431-c26c-42ca-8581-c11f1cffdd17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27627
11419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.2762711419
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.2226203597
Short name T1060
Test name
Test status
Simulation time 153069377 ps
CPU time 0.76 seconds
Started Jun 27 06:38:05 PM PDT 24
Finished Jun 27 06:38:08 PM PDT 24
Peak memory 206272 kb
Host smart-24b0db00-3523-4b1b-86cc-b2b50fc1e9ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22262
03597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.2226203597
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.570538841
Short name T782
Test name
Test status
Simulation time 246926689 ps
CPU time 0.99 seconds
Started Jun 27 06:38:04 PM PDT 24
Finished Jun 27 06:38:08 PM PDT 24
Peak memory 206276 kb
Host smart-5e9e282c-717b-4493-9ebc-88de04639e92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57053
8841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.570538841
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.1949507496
Short name T1572
Test name
Test status
Simulation time 4403563900 ps
CPU time 120.32 seconds
Started Jun 27 06:38:05 PM PDT 24
Finished Jun 27 06:40:08 PM PDT 24
Peak memory 206440 kb
Host smart-a2e1eb31-d88f-4c7a-9735-86d4ecc222f4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1949507496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.1949507496
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.1605531158
Short name T930
Test name
Test status
Simulation time 160346832 ps
CPU time 0.8 seconds
Started Jun 27 06:38:07 PM PDT 24
Finished Jun 27 06:38:13 PM PDT 24
Peak memory 205724 kb
Host smart-c5cd6dae-aed3-4da2-b39b-80995f880a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16055
31158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.1605531158
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.3207458939
Short name T1121
Test name
Test status
Simulation time 183438211 ps
CPU time 0.82 seconds
Started Jun 27 06:38:05 PM PDT 24
Finished Jun 27 06:38:10 PM PDT 24
Peak memory 206256 kb
Host smart-1947f892-5625-42eb-bc79-f6ad9b79f702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32074
58939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.3207458939
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.114789958
Short name T2510
Test name
Test status
Simulation time 5763095780 ps
CPU time 40.06 seconds
Started Jun 27 06:38:01 PM PDT 24
Finished Jun 27 06:38:43 PM PDT 24
Peak memory 206576 kb
Host smart-63540608-c09c-4fe1-a3c2-654d6feb2737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11478
9958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.114789958
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.3684354770
Short name T964
Test name
Test status
Simulation time 89770510 ps
CPU time 0.84 seconds
Started Jun 27 06:38:05 PM PDT 24
Finished Jun 27 06:38:09 PM PDT 24
Peak memory 206340 kb
Host smart-6914d3fb-f936-4614-83c3-f0a7361c6248
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3684354770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.3684354770
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.2678194239
Short name T2445
Test name
Test status
Simulation time 3693166691 ps
CPU time 4.88 seconds
Started Jun 27 06:38:00 PM PDT 24
Finished Jun 27 06:38:06 PM PDT 24
Peak memory 206432 kb
Host smart-4f4d375c-da0a-46dc-ba5c-e9c5d8c7a260
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2678194239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.2678194239
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.3211365057
Short name T7
Test name
Test status
Simulation time 13473385216 ps
CPU time 14.28 seconds
Started Jun 27 06:38:01 PM PDT 24
Finished Jun 27 06:38:17 PM PDT 24
Peak memory 206368 kb
Host smart-ae79eb2f-4b6c-4b9b-a6ab-e363285af43a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3211365057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.3211365057
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.249499979
Short name T823
Test name
Test status
Simulation time 23394584565 ps
CPU time 21.88 seconds
Started Jun 27 06:38:04 PM PDT 24
Finished Jun 27 06:38:28 PM PDT 24
Peak memory 206328 kb
Host smart-da7ff9b8-19f8-4e9f-a434-a0b09a24ac4d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=249499979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.249499979
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.867175778
Short name T1155
Test name
Test status
Simulation time 166028054 ps
CPU time 0.83 seconds
Started Jun 27 06:38:07 PM PDT 24
Finished Jun 27 06:38:12 PM PDT 24
Peak memory 206288 kb
Host smart-7de8eb12-78cc-4c75-a3be-6658b68b76bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86717
5778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.867175778
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.3320071973
Short name T1775
Test name
Test status
Simulation time 209754882 ps
CPU time 0.88 seconds
Started Jun 27 06:38:06 PM PDT 24
Finished Jun 27 06:38:10 PM PDT 24
Peak memory 206452 kb
Host smart-ee20e5bc-14b0-4846-a835-16ca862c3d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33200
71973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.3320071973
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.2705046643
Short name T181
Test name
Test status
Simulation time 192320705 ps
CPU time 0.87 seconds
Started Jun 27 06:38:07 PM PDT 24
Finished Jun 27 06:38:12 PM PDT 24
Peak memory 206264 kb
Host smart-f47de193-0cd4-4fe7-b3a9-33db41b06202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27050
46643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.2705046643
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.2363477460
Short name T172
Test name
Test status
Simulation time 650428302 ps
CPU time 1.64 seconds
Started Jun 27 06:38:03 PM PDT 24
Finished Jun 27 06:38:07 PM PDT 24
Peak memory 206364 kb
Host smart-34a47660-74e4-4047-8da8-1074095d6860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23634
77460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.2363477460
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.618603604
Short name T1453
Test name
Test status
Simulation time 6454966773 ps
CPU time 11.34 seconds
Started Jun 27 06:38:06 PM PDT 24
Finished Jun 27 06:38:21 PM PDT 24
Peak memory 206596 kb
Host smart-2586ef28-e657-4d75-ad2f-f032a3f666c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61860
3604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.618603604
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.1880580574
Short name T1987
Test name
Test status
Simulation time 387906738 ps
CPU time 1.25 seconds
Started Jun 27 06:38:05 PM PDT 24
Finished Jun 27 06:38:09 PM PDT 24
Peak memory 206280 kb
Host smart-34bacbe3-846c-4185-9b83-6239310332d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18805
80574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.1880580574
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.21848119
Short name T2023
Test name
Test status
Simulation time 143912851 ps
CPU time 0.77 seconds
Started Jun 27 06:38:06 PM PDT 24
Finished Jun 27 06:38:11 PM PDT 24
Peak memory 206460 kb
Host smart-b303657b-845d-4d89-9f17-79e0c283b530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21848
119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.21848119
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.3430338462
Short name T1574
Test name
Test status
Simulation time 112950702 ps
CPU time 0.73 seconds
Started Jun 27 06:38:07 PM PDT 24
Finished Jun 27 06:38:13 PM PDT 24
Peak memory 206268 kb
Host smart-c4e4c5bb-8149-41d7-9b0f-99ade96ba213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34303
38462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.3430338462
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.4078622537
Short name T2604
Test name
Test status
Simulation time 854542972 ps
CPU time 2.11 seconds
Started Jun 27 06:38:09 PM PDT 24
Finished Jun 27 06:38:16 PM PDT 24
Peak memory 206372 kb
Host smart-c757bd81-876d-49e5-b12f-3fc8a9c0fdee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40786
22537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.4078622537
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.324626027
Short name T860
Test name
Test status
Simulation time 211349882 ps
CPU time 2.08 seconds
Started Jun 27 06:38:06 PM PDT 24
Finished Jun 27 06:38:13 PM PDT 24
Peak memory 206384 kb
Host smart-99bb7848-8a80-493c-90ac-9542f07c8d92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32462
6027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.324626027
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.3201650524
Short name T455
Test name
Test status
Simulation time 156541606 ps
CPU time 0.77 seconds
Started Jun 27 06:38:05 PM PDT 24
Finished Jun 27 06:38:09 PM PDT 24
Peak memory 206296 kb
Host smart-07c240c8-ef7e-4d4d-b1a8-ea8e07d31f68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32016
50524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.3201650524
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.4172729509
Short name T1328
Test name
Test status
Simulation time 186510658 ps
CPU time 0.81 seconds
Started Jun 27 06:38:03 PM PDT 24
Finished Jun 27 06:38:05 PM PDT 24
Peak memory 206284 kb
Host smart-928c3d83-4c47-41d7-81b2-b1840eff02c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41727
29509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.4172729509
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.2489857081
Short name T530
Test name
Test status
Simulation time 249912109 ps
CPU time 0.86 seconds
Started Jun 27 06:38:06 PM PDT 24
Finished Jun 27 06:38:10 PM PDT 24
Peak memory 206316 kb
Host smart-3b6d83cd-4f43-4fc1-89a3-204184445663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24898
57081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.2489857081
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.3209098463
Short name T1020
Test name
Test status
Simulation time 218365923 ps
CPU time 0.92 seconds
Started Jun 27 06:38:02 PM PDT 24
Finished Jun 27 06:38:04 PM PDT 24
Peak memory 206268 kb
Host smart-59fed2b6-ffb8-4609-8d4a-4d4c47a17edb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32090
98463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.3209098463
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.3185400513
Short name T359
Test name
Test status
Simulation time 23340734411 ps
CPU time 22.61 seconds
Started Jun 27 06:38:06 PM PDT 24
Finished Jun 27 06:38:32 PM PDT 24
Peak memory 206332 kb
Host smart-eb210d27-7226-42c9-8368-535c3b8b889a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31854
00513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.3185400513
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.788274858
Short name T1831
Test name
Test status
Simulation time 3274379272 ps
CPU time 3.69 seconds
Started Jun 27 06:38:07 PM PDT 24
Finished Jun 27 06:38:15 PM PDT 24
Peak memory 206368 kb
Host smart-27c3f690-1831-4d3c-b0ab-4bc4241d10a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78827
4858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.788274858
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.68605045
Short name T2470
Test name
Test status
Simulation time 8491770907 ps
CPU time 78.53 seconds
Started Jun 27 06:38:09 PM PDT 24
Finished Jun 27 06:39:34 PM PDT 24
Peak memory 206468 kb
Host smart-3f89f82c-af8b-4358-ad11-c16c6ed6f115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68605
045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.68605045
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.2466766964
Short name T913
Test name
Test status
Simulation time 3333148589 ps
CPU time 22.26 seconds
Started Jun 27 06:38:05 PM PDT 24
Finished Jun 27 06:38:31 PM PDT 24
Peak memory 206508 kb
Host smart-5532f602-6b41-49b7-abec-5bb0d028b6fe
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2466766964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.2466766964
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.923613191
Short name T2076
Test name
Test status
Simulation time 263723513 ps
CPU time 0.97 seconds
Started Jun 27 06:38:06 PM PDT 24
Finished Jun 27 06:38:10 PM PDT 24
Peak memory 206296 kb
Host smart-832af4ea-7580-421f-aeb6-cdaffdfab258
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=923613191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.923613191
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.3322891290
Short name T1869
Test name
Test status
Simulation time 193079442 ps
CPU time 0.89 seconds
Started Jun 27 06:38:08 PM PDT 24
Finished Jun 27 06:38:15 PM PDT 24
Peak memory 206256 kb
Host smart-8e4475ac-f2d4-4f04-86af-e044d900252d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33228
91290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.3322891290
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.1663964379
Short name T1807
Test name
Test status
Simulation time 5567540059 ps
CPU time 52.39 seconds
Started Jun 27 06:38:06 PM PDT 24
Finished Jun 27 06:39:02 PM PDT 24
Peak memory 206424 kb
Host smart-12fd0b94-2adc-4291-8fad-7cfffa7fd9d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16639
64379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.1663964379
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.2337033722
Short name T813
Test name
Test status
Simulation time 4607840814 ps
CPU time 129.28 seconds
Started Jun 27 06:38:02 PM PDT 24
Finished Jun 27 06:40:13 PM PDT 24
Peak memory 206372 kb
Host smart-22ca5884-a8cf-42ce-8541-dd3044430349
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2337033722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.2337033722
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.2747940035
Short name T912
Test name
Test status
Simulation time 203837433 ps
CPU time 0.83 seconds
Started Jun 27 06:38:08 PM PDT 24
Finished Jun 27 06:38:15 PM PDT 24
Peak memory 206272 kb
Host smart-4e28cb04-118d-4fba-bf5d-e9a440cdf315
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2747940035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.2747940035
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.383435246
Short name T826
Test name
Test status
Simulation time 175380243 ps
CPU time 0.81 seconds
Started Jun 27 06:38:10 PM PDT 24
Finished Jun 27 06:38:17 PM PDT 24
Peak memory 206280 kb
Host smart-26d873e9-7578-4bbd-92c4-b10211e997d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38343
5246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.383435246
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.1057584889
Short name T1875
Test name
Test status
Simulation time 176811795 ps
CPU time 0.77 seconds
Started Jun 27 06:38:08 PM PDT 24
Finished Jun 27 06:38:14 PM PDT 24
Peak memory 206256 kb
Host smart-4756ceaf-da37-40be-bcbb-042543f9e158
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10575
84889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.1057584889
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.3582366789
Short name T727
Test name
Test status
Simulation time 183067341 ps
CPU time 0.84 seconds
Started Jun 27 06:38:10 PM PDT 24
Finished Jun 27 06:38:17 PM PDT 24
Peak memory 206272 kb
Host smart-65e2a18b-db05-4009-8393-3da78aed06f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35823
66789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.3582366789
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.2193201541
Short name T1844
Test name
Test status
Simulation time 170452994 ps
CPU time 0.78 seconds
Started Jun 27 06:38:12 PM PDT 24
Finished Jun 27 06:38:18 PM PDT 24
Peak memory 206264 kb
Host smart-ea4b02f1-d198-4f8d-a824-83d8bf2fc765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21932
01541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.2193201541
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.2897452698
Short name T2416
Test name
Test status
Simulation time 192949098 ps
CPU time 0.9 seconds
Started Jun 27 06:38:09 PM PDT 24
Finished Jun 27 06:38:16 PM PDT 24
Peak memory 206256 kb
Host smart-962e6551-4a07-4181-815a-041c139ee6b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28974
52698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.2897452698
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.1143613959
Short name T1537
Test name
Test status
Simulation time 155659464 ps
CPU time 0.87 seconds
Started Jun 27 06:38:10 PM PDT 24
Finished Jun 27 06:38:16 PM PDT 24
Peak memory 206276 kb
Host smart-3ecbeced-98a5-46d7-8401-a555fa360028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11436
13959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.1143613959
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.3152351067
Short name T748
Test name
Test status
Simulation time 222797719 ps
CPU time 0.9 seconds
Started Jun 27 06:38:08 PM PDT 24
Finished Jun 27 06:38:14 PM PDT 24
Peak memory 206272 kb
Host smart-71c3431f-90bd-4d89-9a2c-d3cec3cc3696
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3152351067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.3152351067
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.651172051
Short name T627
Test name
Test status
Simulation time 170285808 ps
CPU time 0.79 seconds
Started Jun 27 06:38:07 PM PDT 24
Finished Jun 27 06:38:13 PM PDT 24
Peak memory 206264 kb
Host smart-4e37b32a-e9de-4507-a716-7fc0f21545ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65117
2051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.651172051
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.809713113
Short name T2546
Test name
Test status
Simulation time 39867328 ps
CPU time 0.68 seconds
Started Jun 27 06:38:10 PM PDT 24
Finished Jun 27 06:38:17 PM PDT 24
Peak memory 206264 kb
Host smart-3af3c8f7-5e06-4ebe-800b-85e9b802b1ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80971
3113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.809713113
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.672308203
Short name T702
Test name
Test status
Simulation time 20337637157 ps
CPU time 43.16 seconds
Started Jun 27 06:38:05 PM PDT 24
Finished Jun 27 06:38:52 PM PDT 24
Peak memory 206508 kb
Host smart-e9d6396d-6a12-4d24-90c6-64d79396355b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67230
8203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.672308203
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.196036169
Short name T1665
Test name
Test status
Simulation time 190239982 ps
CPU time 0.85 seconds
Started Jun 27 06:38:03 PM PDT 24
Finished Jun 27 06:38:05 PM PDT 24
Peak memory 206284 kb
Host smart-22e29ed7-8b0d-4a3e-9f09-1831f528c7a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19603
6169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.196036169
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.2673572713
Short name T1950
Test name
Test status
Simulation time 202234492 ps
CPU time 0.9 seconds
Started Jun 27 06:38:10 PM PDT 24
Finished Jun 27 06:38:17 PM PDT 24
Peak memory 206272 kb
Host smart-d71ceeb9-17d8-4c6f-9438-efb6b63b752e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26735
72713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.2673572713
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.693133379
Short name T892
Test name
Test status
Simulation time 190522424 ps
CPU time 0.91 seconds
Started Jun 27 06:38:12 PM PDT 24
Finished Jun 27 06:38:18 PM PDT 24
Peak memory 206280 kb
Host smart-03e6e028-1d31-43e2-9bf2-505d75262eb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69313
3379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.693133379
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.723283460
Short name T2609
Test name
Test status
Simulation time 195951377 ps
CPU time 0.81 seconds
Started Jun 27 06:38:10 PM PDT 24
Finished Jun 27 06:38:17 PM PDT 24
Peak memory 206260 kb
Host smart-e4e2c09e-4128-415b-ac74-028b5c3190b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72328
3460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.723283460
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.3165022668
Short name T2028
Test name
Test status
Simulation time 180046529 ps
CPU time 0.79 seconds
Started Jun 27 06:38:09 PM PDT 24
Finished Jun 27 06:38:16 PM PDT 24
Peak memory 206280 kb
Host smart-38005a46-fa1e-4e4b-8f34-e65bba1cac14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31650
22668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.3165022668
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.1244315759
Short name T1612
Test name
Test status
Simulation time 199944551 ps
CPU time 0.8 seconds
Started Jun 27 06:38:09 PM PDT 24
Finished Jun 27 06:38:16 PM PDT 24
Peak memory 206276 kb
Host smart-836c45b8-4767-4541-a7cc-8199225d3926
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12443
15759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.1244315759
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.2704115096
Short name T2061
Test name
Test status
Simulation time 193757249 ps
CPU time 0.87 seconds
Started Jun 27 06:38:09 PM PDT 24
Finished Jun 27 06:38:16 PM PDT 24
Peak memory 206296 kb
Host smart-8a4eaa0b-79b1-4ce3-bb05-bc10f18862e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27041
15096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.2704115096
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.4053783916
Short name T579
Test name
Test status
Simulation time 5324087159 ps
CPU time 38.23 seconds
Started Jun 27 06:38:10 PM PDT 24
Finished Jun 27 06:38:53 PM PDT 24
Peak memory 206420 kb
Host smart-da783153-eef4-4571-8657-c9e925b4a931
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4053783916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.4053783916
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.1898416435
Short name T422
Test name
Test status
Simulation time 167125718 ps
CPU time 0.77 seconds
Started Jun 27 06:38:09 PM PDT 24
Finished Jun 27 06:38:16 PM PDT 24
Peak memory 206284 kb
Host smart-ad53b3a6-8226-49b0-8b00-c775ed78c992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18984
16435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.1898416435
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.1720624703
Short name T2607
Test name
Test status
Simulation time 159121324 ps
CPU time 0.77 seconds
Started Jun 27 06:38:09 PM PDT 24
Finished Jun 27 06:38:16 PM PDT 24
Peak memory 206280 kb
Host smart-c79de8d4-44a8-4858-81e6-38b2200fda69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17206
24703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.1720624703
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.3227265487
Short name T2458
Test name
Test status
Simulation time 4474098888 ps
CPU time 113.44 seconds
Started Jun 27 06:38:09 PM PDT 24
Finished Jun 27 06:40:08 PM PDT 24
Peak memory 206424 kb
Host smart-00f4d95d-f9d3-4a0b-9c8b-77c0ea4bb7f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32272
65487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.3227265487
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.2811522896
Short name T678
Test name
Test status
Simulation time 36653287 ps
CPU time 0.68 seconds
Started Jun 27 06:38:28 PM PDT 24
Finished Jun 27 06:38:33 PM PDT 24
Peak memory 206320 kb
Host smart-1423de3d-be1e-415c-8daf-7ce64fa15708
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2811522896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.2811522896
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.2834559880
Short name T595
Test name
Test status
Simulation time 3886524505 ps
CPU time 4.44 seconds
Started Jun 27 06:38:08 PM PDT 24
Finished Jun 27 06:38:17 PM PDT 24
Peak memory 206448 kb
Host smart-f19e8cd1-cf91-449d-800e-7a4060ace3fd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2834559880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.2834559880
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.483893524
Short name T2448
Test name
Test status
Simulation time 13422513511 ps
CPU time 13.29 seconds
Started Jun 27 06:38:06 PM PDT 24
Finished Jun 27 06:38:23 PM PDT 24
Peak memory 206420 kb
Host smart-b8e1f687-0bac-4c3d-b59b-ab7659623f1e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=483893524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.483893524
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.2139384687
Short name T11
Test name
Test status
Simulation time 23344934024 ps
CPU time 21.06 seconds
Started Jun 27 06:38:08 PM PDT 24
Finished Jun 27 06:38:35 PM PDT 24
Peak memory 206484 kb
Host smart-2a6de69f-f041-4e3e-bf17-c44a1d062b74
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2139384687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.2139384687
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.1871653638
Short name T735
Test name
Test status
Simulation time 155725770 ps
CPU time 0.8 seconds
Started Jun 27 06:38:08 PM PDT 24
Finished Jun 27 06:38:15 PM PDT 24
Peak memory 206276 kb
Host smart-a8fff7ce-aceb-4369-8670-d196646b8399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18716
53638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.1871653638
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.1957067835
Short name T2085
Test name
Test status
Simulation time 187058687 ps
CPU time 0.78 seconds
Started Jun 27 06:38:05 PM PDT 24
Finished Jun 27 06:38:09 PM PDT 24
Peak memory 206280 kb
Host smart-e44752a5-fa48-41c6-bc0b-a8a65de2b9e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19570
67835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.1957067835
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.1701531223
Short name T2079
Test name
Test status
Simulation time 545625987 ps
CPU time 1.5 seconds
Started Jun 27 06:38:05 PM PDT 24
Finished Jun 27 06:38:09 PM PDT 24
Peak memory 206276 kb
Host smart-e9ec8578-4241-4464-bc6b-4370957b27f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17015
31223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.1701531223
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.2681263479
Short name T1033
Test name
Test status
Simulation time 851730348 ps
CPU time 2.01 seconds
Started Jun 27 06:38:07 PM PDT 24
Finished Jun 27 06:38:13 PM PDT 24
Peak memory 206420 kb
Host smart-12b1b6c2-3853-4fd2-89be-1fe3dec827d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26812
63479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.2681263479
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.3619745369
Short name T1485
Test name
Test status
Simulation time 6496459502 ps
CPU time 11.99 seconds
Started Jun 27 06:38:06 PM PDT 24
Finished Jun 27 06:38:22 PM PDT 24
Peak memory 206440 kb
Host smart-883ba266-c80c-4799-91db-ad4c0d98c6c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36197
45369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.3619745369
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.3857732772
Short name T90
Test name
Test status
Simulation time 427435503 ps
CPU time 1.36 seconds
Started Jun 27 06:38:06 PM PDT 24
Finished Jun 27 06:38:12 PM PDT 24
Peak memory 206456 kb
Host smart-f92dd8f4-791a-4cc0-b654-2f804ddcf2a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38577
32772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.3857732772
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.3719667339
Short name T770
Test name
Test status
Simulation time 159036797 ps
CPU time 0.8 seconds
Started Jun 27 06:38:07 PM PDT 24
Finished Jun 27 06:38:13 PM PDT 24
Peak memory 206260 kb
Host smart-d1214a8f-3638-416d-a1e3-cadcb421163a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37196
67339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.3719667339
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.1224973067
Short name T1167
Test name
Test status
Simulation time 47282061 ps
CPU time 0.66 seconds
Started Jun 27 06:38:00 PM PDT 24
Finished Jun 27 06:38:03 PM PDT 24
Peak memory 206276 kb
Host smart-c76d0793-4687-4299-ab18-9e8ed4c865f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12249
73067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.1224973067
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.395716714
Short name T1490
Test name
Test status
Simulation time 1145134931 ps
CPU time 2.27 seconds
Started Jun 27 06:38:08 PM PDT 24
Finished Jun 27 06:38:17 PM PDT 24
Peak memory 206448 kb
Host smart-4f3d1070-1b94-434b-afb7-e26c25eec0af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39571
6714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.395716714
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.2250408558
Short name T2413
Test name
Test status
Simulation time 394044163 ps
CPU time 2.33 seconds
Started Jun 27 06:37:58 PM PDT 24
Finished Jun 27 06:38:01 PM PDT 24
Peak memory 206308 kb
Host smart-07543b7d-fb8c-41fa-815c-224031cb5227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22504
08558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.2250408558
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.1932251631
Short name T1489
Test name
Test status
Simulation time 260370992 ps
CPU time 0.92 seconds
Started Jun 27 06:38:27 PM PDT 24
Finished Jun 27 06:38:33 PM PDT 24
Peak memory 206272 kb
Host smart-f43ec0c4-da2f-47ba-8b8e-4f2999b3dc4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19322
51631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.1932251631
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.3031354909
Short name T2576
Test name
Test status
Simulation time 144355459 ps
CPU time 0.86 seconds
Started Jun 27 06:38:28 PM PDT 24
Finished Jun 27 06:38:34 PM PDT 24
Peak memory 206272 kb
Host smart-d200603d-c0ef-4d7b-8d2c-d57b2132c6e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30313
54909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.3031354909
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.2964327253
Short name T998
Test name
Test status
Simulation time 181950021 ps
CPU time 0.87 seconds
Started Jun 27 06:38:22 PM PDT 24
Finished Jun 27 06:38:25 PM PDT 24
Peak memory 206288 kb
Host smart-514ebc82-ff3b-4a2d-83ab-766478f7a312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29643
27253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.2964327253
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.2786737733
Short name T970
Test name
Test status
Simulation time 161689956 ps
CPU time 0.79 seconds
Started Jun 27 06:38:24 PM PDT 24
Finished Jun 27 06:38:29 PM PDT 24
Peak memory 206280 kb
Host smart-7f3d51e5-c8f5-46d9-8233-20c25308ca2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27867
37733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.2786737733
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.1822247158
Short name T1204
Test name
Test status
Simulation time 23306204548 ps
CPU time 23.68 seconds
Started Jun 27 06:38:24 PM PDT 24
Finished Jun 27 06:38:52 PM PDT 24
Peak memory 206324 kb
Host smart-a4b7002c-7897-4d57-9dcf-bd4ca41173b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18222
47158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.1822247158
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.1937715292
Short name T730
Test name
Test status
Simulation time 3326903041 ps
CPU time 4.34 seconds
Started Jun 27 06:38:22 PM PDT 24
Finished Jun 27 06:38:30 PM PDT 24
Peak memory 206332 kb
Host smart-372d9dcb-7321-44cf-87dc-873598a82007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19377
15292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.1937715292
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.1975071962
Short name T2480
Test name
Test status
Simulation time 6544094434 ps
CPU time 174.25 seconds
Started Jun 27 06:38:25 PM PDT 24
Finished Jun 27 06:41:25 PM PDT 24
Peak memory 206524 kb
Host smart-31009307-a8c4-45dc-a9f3-6a26377d5e0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19750
71962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.1975071962
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.127203414
Short name T5
Test name
Test status
Simulation time 4581276700 ps
CPU time 43.19 seconds
Started Jun 27 06:38:24 PM PDT 24
Finished Jun 27 06:39:12 PM PDT 24
Peak memory 206480 kb
Host smart-3b872012-ba13-4733-8b95-bf721ae923f3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=127203414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.127203414
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.2727954056
Short name T743
Test name
Test status
Simulation time 249809601 ps
CPU time 1.03 seconds
Started Jun 27 06:38:21 PM PDT 24
Finished Jun 27 06:38:24 PM PDT 24
Peak memory 206316 kb
Host smart-2214f631-cd4f-4efa-b8ab-e2dd7e5a9a13
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2727954056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.2727954056
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.3355162440
Short name T1084
Test name
Test status
Simulation time 201793593 ps
CPU time 0.92 seconds
Started Jun 27 06:38:24 PM PDT 24
Finished Jun 27 06:38:28 PM PDT 24
Peak memory 206252 kb
Host smart-045cf5e5-dee4-4d57-8a41-43e2e120de76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33551
62440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.3355162440
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.1054802260
Short name T1399
Test name
Test status
Simulation time 3742196608 ps
CPU time 99.65 seconds
Started Jun 27 06:38:27 PM PDT 24
Finished Jun 27 06:40:11 PM PDT 24
Peak memory 206408 kb
Host smart-95def4a6-8026-4ec6-8d58-2cddf9d48734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10548
02260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.1054802260
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.3190194037
Short name T814
Test name
Test status
Simulation time 6057190446 ps
CPU time 43.35 seconds
Started Jun 27 06:38:25 PM PDT 24
Finished Jun 27 06:39:14 PM PDT 24
Peak memory 206440 kb
Host smart-32ee99ec-08af-41cb-808b-8c13ce41e49d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3190194037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.3190194037
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.2119071987
Short name T1946
Test name
Test status
Simulation time 156556545 ps
CPU time 0.85 seconds
Started Jun 27 06:38:24 PM PDT 24
Finished Jun 27 06:38:29 PM PDT 24
Peak memory 206412 kb
Host smart-736c21ec-3224-4375-99b8-b964960942d3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2119071987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.2119071987
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.3787248667
Short name T2616
Test name
Test status
Simulation time 146405681 ps
CPU time 0.77 seconds
Started Jun 27 06:38:24 PM PDT 24
Finished Jun 27 06:38:28 PM PDT 24
Peak memory 206272 kb
Host smart-2094a5ff-f2b7-4dac-84e6-ac74e086ad82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37872
48667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.3787248667
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.3787716347
Short name T1427
Test name
Test status
Simulation time 178340731 ps
CPU time 0.79 seconds
Started Jun 27 06:38:28 PM PDT 24
Finished Jun 27 06:38:34 PM PDT 24
Peak memory 206276 kb
Host smart-b6148097-29eb-4204-a0bc-d5960b20b464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37877
16347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.3787716347
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.3955347248
Short name T840
Test name
Test status
Simulation time 206432223 ps
CPU time 0.79 seconds
Started Jun 27 06:38:21 PM PDT 24
Finished Jun 27 06:38:24 PM PDT 24
Peak memory 206176 kb
Host smart-fc0ea9bc-3594-44a3-9dda-c4a935c38a4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39553
47248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.3955347248
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.1182696806
Short name T2298
Test name
Test status
Simulation time 170533792 ps
CPU time 0.74 seconds
Started Jun 27 06:38:23 PM PDT 24
Finished Jun 27 06:38:28 PM PDT 24
Peak memory 206268 kb
Host smart-6daf425d-114c-432e-aa31-a814f8b5a4c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11826
96806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.1182696806
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.1693061764
Short name T685
Test name
Test status
Simulation time 285517792 ps
CPU time 1.06 seconds
Started Jun 27 06:38:21 PM PDT 24
Finished Jun 27 06:38:25 PM PDT 24
Peak memory 206296 kb
Host smart-e1e79855-c95d-46d9-b300-e98a7c6618e0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1693061764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.1693061764
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.2020511947
Short name T2171
Test name
Test status
Simulation time 181416563 ps
CPU time 0.81 seconds
Started Jun 27 06:38:22 PM PDT 24
Finished Jun 27 06:38:25 PM PDT 24
Peak memory 206236 kb
Host smart-3a296be0-bfae-40c5-95d0-9d0ebfe3e9f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20205
11947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.2020511947
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.647859319
Short name T1440
Test name
Test status
Simulation time 33089273 ps
CPU time 0.64 seconds
Started Jun 27 06:38:22 PM PDT 24
Finished Jun 27 06:38:25 PM PDT 24
Peak memory 206280 kb
Host smart-c0ad566d-5793-4db7-9767-f696b47fef22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64785
9319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.647859319
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.3260025904
Short name T1832
Test name
Test status
Simulation time 12285624614 ps
CPU time 26.76 seconds
Started Jun 27 06:38:21 PM PDT 24
Finished Jun 27 06:38:50 PM PDT 24
Peak memory 206456 kb
Host smart-91563b5c-82e9-460d-8afc-c436ab0fe53e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32600
25904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.3260025904
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.159543923
Short name T354
Test name
Test status
Simulation time 143208884 ps
CPU time 0.8 seconds
Started Jun 27 06:38:22 PM PDT 24
Finished Jun 27 06:38:26 PM PDT 24
Peak memory 206280 kb
Host smart-d94250c5-8ca8-481e-9b68-42d3ebe40623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15954
3923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.159543923
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.770624888
Short name T716
Test name
Test status
Simulation time 227340967 ps
CPU time 0.92 seconds
Started Jun 27 06:38:25 PM PDT 24
Finished Jun 27 06:38:32 PM PDT 24
Peak memory 206312 kb
Host smart-42ae0cee-410b-45f3-b73d-3f1d9d3be18d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77062
4888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.770624888
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.883901536
Short name T1182
Test name
Test status
Simulation time 223797598 ps
CPU time 0.94 seconds
Started Jun 27 06:38:24 PM PDT 24
Finished Jun 27 06:38:30 PM PDT 24
Peak memory 206456 kb
Host smart-5dfeb02a-9d41-4f89-a23a-6d4e03e2851a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88390
1536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.883901536
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.3124365730
Short name T2345
Test name
Test status
Simulation time 181129999 ps
CPU time 0.83 seconds
Started Jun 27 06:38:25 PM PDT 24
Finished Jun 27 06:38:32 PM PDT 24
Peak memory 206280 kb
Host smart-06767737-f749-491a-b628-7553c2a8008a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31243
65730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.3124365730
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.2644846510
Short name T1302
Test name
Test status
Simulation time 136850341 ps
CPU time 0.74 seconds
Started Jun 27 06:38:21 PM PDT 24
Finished Jun 27 06:38:24 PM PDT 24
Peak memory 206264 kb
Host smart-4e8346f7-5f4c-4188-a131-d04d4be0c574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26448
46510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.2644846510
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.1652231464
Short name T623
Test name
Test status
Simulation time 169029085 ps
CPU time 0.78 seconds
Started Jun 27 06:38:23 PM PDT 24
Finished Jun 27 06:38:27 PM PDT 24
Peak memory 206276 kb
Host smart-36f55498-9503-4173-96c1-194d0ad7f4a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16522
31464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.1652231464
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.1765448785
Short name T2184
Test name
Test status
Simulation time 158914354 ps
CPU time 0.83 seconds
Started Jun 27 06:38:23 PM PDT 24
Finished Jun 27 06:38:28 PM PDT 24
Peak memory 206288 kb
Host smart-1d49a897-38b3-4af8-a7fb-71d880a62d39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17654
48785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.1765448785
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.2001940502
Short name T539
Test name
Test status
Simulation time 249490605 ps
CPU time 0.94 seconds
Started Jun 27 06:38:25 PM PDT 24
Finished Jun 27 06:38:31 PM PDT 24
Peak memory 206292 kb
Host smart-732cf052-d402-48fc-b6d7-1255f4489592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20019
40502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.2001940502
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.2164609877
Short name T583
Test name
Test status
Simulation time 150262133 ps
CPU time 0.75 seconds
Started Jun 27 06:38:25 PM PDT 24
Finished Jun 27 06:38:30 PM PDT 24
Peak memory 206276 kb
Host smart-9fe5ba5d-f6c6-4748-ba33-a0dba169fab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21646
09877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.2164609877
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.2904208841
Short name T459
Test name
Test status
Simulation time 198101419 ps
CPU time 0.81 seconds
Started Jun 27 06:38:27 PM PDT 24
Finished Jun 27 06:38:33 PM PDT 24
Peak memory 206272 kb
Host smart-a292f654-c2e8-4d86-9a3e-b8e68a951bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29042
08841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.2904208841
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.354349083
Short name T596
Test name
Test status
Simulation time 3211064665 ps
CPU time 22.26 seconds
Started Jun 27 06:38:26 PM PDT 24
Finished Jun 27 06:38:53 PM PDT 24
Peak memory 206388 kb
Host smart-fe6430e9-2149-4f8b-a0ac-16e3cce18379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35434
9083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.354349083
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.575232555
Short name T2493
Test name
Test status
Simulation time 50623919 ps
CPU time 0.69 seconds
Started Jun 27 06:38:28 PM PDT 24
Finished Jun 27 06:38:34 PM PDT 24
Peak memory 206360 kb
Host smart-985d94c0-733b-465c-900b-86d48b485d6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=575232555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.575232555
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.1626500075
Short name T2048
Test name
Test status
Simulation time 3672896613 ps
CPU time 4.42 seconds
Started Jun 27 06:38:28 PM PDT 24
Finished Jun 27 06:38:37 PM PDT 24
Peak memory 206320 kb
Host smart-cc7f1c43-781a-4031-89f5-b2973ba8b991
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1626500075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.1626500075
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.1387632882
Short name T1547
Test name
Test status
Simulation time 13356559097 ps
CPU time 11.9 seconds
Started Jun 27 06:38:33 PM PDT 24
Finished Jun 27 06:38:48 PM PDT 24
Peak memory 206164 kb
Host smart-48b7a0f4-0878-4d6b-8eb7-cbdf34ac0875
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1387632882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.1387632882
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.1041013339
Short name T1492
Test name
Test status
Simulation time 23323884537 ps
CPU time 24.92 seconds
Started Jun 27 06:38:33 PM PDT 24
Finished Jun 27 06:39:02 PM PDT 24
Peak memory 206348 kb
Host smart-348327d1-6b0d-4123-986d-7759e0c18a63
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1041013339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.1041013339
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.1343971424
Short name T450
Test name
Test status
Simulation time 185177767 ps
CPU time 0.82 seconds
Started Jun 27 06:38:27 PM PDT 24
Finished Jun 27 06:38:33 PM PDT 24
Peak memory 206240 kb
Host smart-d3865030-5742-421d-aaca-40dd796bd032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13439
71424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.1343971424
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.424114244
Short name T533
Test name
Test status
Simulation time 189910464 ps
CPU time 0.8 seconds
Started Jun 27 06:38:33 PM PDT 24
Finished Jun 27 06:38:38 PM PDT 24
Peak memory 206308 kb
Host smart-a5146b4f-362d-4b6b-8261-e58338648d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42411
4244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.424114244
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.2901445518
Short name T927
Test name
Test status
Simulation time 388213306 ps
CPU time 1.18 seconds
Started Jun 27 06:38:33 PM PDT 24
Finished Jun 27 06:38:38 PM PDT 24
Peak memory 206280 kb
Host smart-ddfabf91-f6ea-479a-bdc3-478dabc5dd4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29014
45518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.2901445518
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.1625860421
Short name T1491
Test name
Test status
Simulation time 697075512 ps
CPU time 1.63 seconds
Started Jun 27 06:38:32 PM PDT 24
Finished Jun 27 06:38:37 PM PDT 24
Peak memory 206372 kb
Host smart-958de206-0f6e-4c79-880b-8321428fc3c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16258
60421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.1625860421
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.3128975825
Short name T1192
Test name
Test status
Simulation time 15285115136 ps
CPU time 29.14 seconds
Started Jun 27 06:38:31 PM PDT 24
Finished Jun 27 06:39:04 PM PDT 24
Peak memory 206464 kb
Host smart-38285a4f-8c47-4602-996f-3a8cb58d8034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31289
75825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.3128975825
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.2591327876
Short name T2477
Test name
Test status
Simulation time 410710283 ps
CPU time 1.18 seconds
Started Jun 27 06:38:33 PM PDT 24
Finished Jun 27 06:38:38 PM PDT 24
Peak memory 206280 kb
Host smart-02288ccd-53c4-4078-ae54-2defdb7baef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25913
27876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.2591327876
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.2144612803
Short name T688
Test name
Test status
Simulation time 161729570 ps
CPU time 0.81 seconds
Started Jun 27 06:38:31 PM PDT 24
Finished Jun 27 06:38:36 PM PDT 24
Peak memory 206272 kb
Host smart-6db43eb9-134f-48f8-8ccc-02d23884349f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21446
12803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.2144612803
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.4263717304
Short name T527
Test name
Test status
Simulation time 92649107 ps
CPU time 0.71 seconds
Started Jun 27 06:38:33 PM PDT 24
Finished Jun 27 06:38:38 PM PDT 24
Peak memory 206292 kb
Host smart-9ded6904-90e0-44d8-8e6c-bc903270f9fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42637
17304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.4263717304
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.272715518
Short name T2475
Test name
Test status
Simulation time 873977628 ps
CPU time 1.98 seconds
Started Jun 27 06:38:32 PM PDT 24
Finished Jun 27 06:38:37 PM PDT 24
Peak memory 206436 kb
Host smart-34e9e32f-f5b5-419a-a645-b28f88c0216e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27271
5518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.272715518
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.3446775143
Short name T1372
Test name
Test status
Simulation time 205260872 ps
CPU time 1.72 seconds
Started Jun 27 06:38:33 PM PDT 24
Finished Jun 27 06:38:39 PM PDT 24
Peak memory 206172 kb
Host smart-7b2509ae-5f53-459a-90e3-241207b3fdef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34467
75143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.3446775143
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.1400949884
Short name T1123
Test name
Test status
Simulation time 257046827 ps
CPU time 0.87 seconds
Started Jun 27 06:38:32 PM PDT 24
Finished Jun 27 06:38:37 PM PDT 24
Peak memory 206296 kb
Host smart-de83ac9d-661e-42d3-b2a1-be3e37855dec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14009
49884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.1400949884
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.1787075571
Short name T667
Test name
Test status
Simulation time 165517180 ps
CPU time 0.8 seconds
Started Jun 27 06:38:33 PM PDT 24
Finished Jun 27 06:38:38 PM PDT 24
Peak memory 206304 kb
Host smart-1fcb5dec-6ef3-41b4-8da5-af130c941990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17870
75571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.1787075571
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.743351127
Short name T407
Test name
Test status
Simulation time 221376057 ps
CPU time 0.97 seconds
Started Jun 27 06:38:33 PM PDT 24
Finished Jun 27 06:38:38 PM PDT 24
Peak memory 206172 kb
Host smart-7e415102-1948-4860-9a98-b58159bd3f91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74335
1127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.743351127
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_invalid_sync.4110062456
Short name T2080
Test name
Test status
Simulation time 6694811389 ps
CPU time 179.35 seconds
Started Jun 27 06:38:32 PM PDT 24
Finished Jun 27 06:41:35 PM PDT 24
Peak memory 206440 kb
Host smart-d9f11454-9f55-494e-96ae-4e42868a1975
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4110062456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.4110062456
Directory /workspace/23.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.3240760958
Short name T2531
Test name
Test status
Simulation time 200352494 ps
CPU time 0.85 seconds
Started Jun 27 06:38:32 PM PDT 24
Finished Jun 27 06:38:37 PM PDT 24
Peak memory 206252 kb
Host smart-7c380ab9-15ee-437a-9477-4703549a24a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32407
60958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.3240760958
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.2080675969
Short name T364
Test name
Test status
Simulation time 23330146802 ps
CPU time 20.54 seconds
Started Jun 27 06:38:32 PM PDT 24
Finished Jun 27 06:38:56 PM PDT 24
Peak memory 206316 kb
Host smart-0d4cb6dd-42f2-4c29-8b41-89e9d11f9fa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20806
75969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.2080675969
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.516213836
Short name T1997
Test name
Test status
Simulation time 3273575643 ps
CPU time 3.82 seconds
Started Jun 27 06:38:35 PM PDT 24
Finished Jun 27 06:38:42 PM PDT 24
Peak memory 206340 kb
Host smart-c3d389af-0974-480f-9889-9d750afa47db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51621
3836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.516213836
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.1623279098
Short name T822
Test name
Test status
Simulation time 10008426688 ps
CPU time 258.02 seconds
Started Jun 27 06:38:31 PM PDT 24
Finished Jun 27 06:42:53 PM PDT 24
Peak memory 206464 kb
Host smart-2fa296d4-6bf4-4c42-a7cc-3df6bac7a208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16232
79098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.1623279098
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.647203424
Short name T1981
Test name
Test status
Simulation time 4696974756 ps
CPU time 45.35 seconds
Started Jun 27 06:38:26 PM PDT 24
Finished Jun 27 06:39:17 PM PDT 24
Peak memory 206448 kb
Host smart-fa132920-b80f-4289-8e14-a9d4dad95b5d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=647203424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.647203424
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.3372479134
Short name T1221
Test name
Test status
Simulation time 235647304 ps
CPU time 0.95 seconds
Started Jun 27 06:38:35 PM PDT 24
Finished Jun 27 06:38:39 PM PDT 24
Peak memory 206168 kb
Host smart-3908869e-2df4-4c62-8083-8d4f30f56d23
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3372479134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.3372479134
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.1141037666
Short name T388
Test name
Test status
Simulation time 198593521 ps
CPU time 0.87 seconds
Started Jun 27 06:38:35 PM PDT 24
Finished Jun 27 06:38:39 PM PDT 24
Peak memory 206224 kb
Host smart-42fe5b3b-5557-4df4-8c4c-f60f3e01a622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11410
37666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.1141037666
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.3173401442
Short name T146
Test name
Test status
Simulation time 3588871883 ps
CPU time 31.93 seconds
Started Jun 27 06:38:33 PM PDT 24
Finished Jun 27 06:39:09 PM PDT 24
Peak memory 206496 kb
Host smart-5270978e-d4d7-41bf-b275-700b41fa98e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31734
01442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.3173401442
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.1477176665
Short name T1680
Test name
Test status
Simulation time 5826563648 ps
CPU time 158.32 seconds
Started Jun 27 06:38:35 PM PDT 24
Finished Jun 27 06:41:16 PM PDT 24
Peak memory 206384 kb
Host smart-5a4b7613-192e-4c8b-bce1-74d5e83ebfe8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1477176665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.1477176665
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.3085097240
Short name T1233
Test name
Test status
Simulation time 148777441 ps
CPU time 0.78 seconds
Started Jun 27 06:38:35 PM PDT 24
Finished Jun 27 06:38:39 PM PDT 24
Peak memory 206240 kb
Host smart-c5ae592e-d3fd-4d3a-9b3c-17e9121870ac
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3085097240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.3085097240
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.1757583068
Short name T1590
Test name
Test status
Simulation time 147669288 ps
CPU time 0.78 seconds
Started Jun 27 06:38:34 PM PDT 24
Finished Jun 27 06:38:39 PM PDT 24
Peak memory 206280 kb
Host smart-623d9549-b5c6-4320-b70f-a5168985c19e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17575
83068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.1757583068
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.1737977272
Short name T915
Test name
Test status
Simulation time 183235786 ps
CPU time 0.84 seconds
Started Jun 27 06:38:33 PM PDT 24
Finished Jun 27 06:38:37 PM PDT 24
Peak memory 206292 kb
Host smart-99f3c3d6-fa6f-4456-8a5b-65d89d751655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17379
77272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.1737977272
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.3501618785
Short name T675
Test name
Test status
Simulation time 157062773 ps
CPU time 0.77 seconds
Started Jun 27 06:38:33 PM PDT 24
Finished Jun 27 06:38:37 PM PDT 24
Peak memory 206276 kb
Host smart-606552de-c730-47e7-ba5d-d376f2499220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35016
18785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.3501618785
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.247966121
Short name T2170
Test name
Test status
Simulation time 178920641 ps
CPU time 0.8 seconds
Started Jun 27 06:38:24 PM PDT 24
Finished Jun 27 06:38:29 PM PDT 24
Peak memory 206276 kb
Host smart-ea66e479-8b01-4a5e-9b22-ab6f52dc26d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24796
6121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.247966121
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.1678145734
Short name T1317
Test name
Test status
Simulation time 151091005 ps
CPU time 0.8 seconds
Started Jun 27 06:38:20 PM PDT 24
Finished Jun 27 06:38:22 PM PDT 24
Peak memory 206272 kb
Host smart-d0bca1c1-a4bb-486a-8cb0-6319056b4e9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16781
45734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.1678145734
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.119404418
Short name T1579
Test name
Test status
Simulation time 197516910 ps
CPU time 0.86 seconds
Started Jun 27 06:38:21 PM PDT 24
Finished Jun 27 06:38:25 PM PDT 24
Peak memory 206296 kb
Host smart-53970e42-016b-4837-9d70-8e6fc75d18b0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=119404418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.119404418
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.2110591243
Short name T649
Test name
Test status
Simulation time 145172030 ps
CPU time 0.79 seconds
Started Jun 27 06:38:21 PM PDT 24
Finished Jun 27 06:38:24 PM PDT 24
Peak memory 206276 kb
Host smart-154dc2ba-bc10-4eeb-bc8e-291255fda4e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21105
91243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.2110591243
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.3424981215
Short name T1678
Test name
Test status
Simulation time 32517971 ps
CPU time 0.66 seconds
Started Jun 27 06:38:24 PM PDT 24
Finished Jun 27 06:38:28 PM PDT 24
Peak memory 206264 kb
Host smart-9343806d-3873-49c5-9795-0efd0ef11aff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34249
81215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.3424981215
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.2093494617
Short name T1858
Test name
Test status
Simulation time 20890177231 ps
CPU time 46.17 seconds
Started Jun 27 06:38:21 PM PDT 24
Finished Jun 27 06:39:09 PM PDT 24
Peak memory 206520 kb
Host smart-2b7ac133-2faa-46dc-b640-b2632172046b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20934
94617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.2093494617
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.753853465
Short name T548
Test name
Test status
Simulation time 263785775 ps
CPU time 0.89 seconds
Started Jun 27 06:38:26 PM PDT 24
Finished Jun 27 06:38:32 PM PDT 24
Peak memory 206268 kb
Host smart-d7fd6c96-a79b-459d-a045-88a8d0102c53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75385
3465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.753853465
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.3538696186
Short name T1380
Test name
Test status
Simulation time 213142851 ps
CPU time 0.9 seconds
Started Jun 27 06:38:25 PM PDT 24
Finished Jun 27 06:38:31 PM PDT 24
Peak memory 206272 kb
Host smart-5cf3fca3-0440-43bd-8538-8d07f6d3fa11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35386
96186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.3538696186
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.3831686371
Short name T942
Test name
Test status
Simulation time 189366412 ps
CPU time 0.83 seconds
Started Jun 27 06:38:22 PM PDT 24
Finished Jun 27 06:38:26 PM PDT 24
Peak memory 206324 kb
Host smart-07b9e09e-127a-493a-b418-5c488289a594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38316
86371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.3831686371
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.2570619749
Short name T2016
Test name
Test status
Simulation time 154177383 ps
CPU time 0.78 seconds
Started Jun 27 06:38:27 PM PDT 24
Finished Jun 27 06:38:33 PM PDT 24
Peak memory 206260 kb
Host smart-17aec16c-5ddf-4eab-8101-5aec4a124d66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25706
19749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.2570619749
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.1018920208
Short name T1265
Test name
Test status
Simulation time 186254260 ps
CPU time 0.83 seconds
Started Jun 27 06:38:25 PM PDT 24
Finished Jun 27 06:38:30 PM PDT 24
Peak memory 206436 kb
Host smart-b9044b8a-da4f-4c08-b84a-7473fd946dbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10189
20208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.1018920208
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.904719078
Short name T877
Test name
Test status
Simulation time 148353179 ps
CPU time 0.75 seconds
Started Jun 27 06:38:23 PM PDT 24
Finished Jun 27 06:38:27 PM PDT 24
Peak memory 206272 kb
Host smart-3b2a9ba3-5000-4dc4-a52d-f78be695cccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90471
9078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.904719078
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.2971930646
Short name T1711
Test name
Test status
Simulation time 157694264 ps
CPU time 0.79 seconds
Started Jun 27 06:38:25 PM PDT 24
Finished Jun 27 06:38:31 PM PDT 24
Peak memory 206288 kb
Host smart-0953cf36-80cf-4efd-aec8-e5ba0af86e36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29719
30646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.2971930646
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.1766414329
Short name T1634
Test name
Test status
Simulation time 217876231 ps
CPU time 0.9 seconds
Started Jun 27 06:38:28 PM PDT 24
Finished Jun 27 06:38:34 PM PDT 24
Peak memory 206292 kb
Host smart-21d4da6c-c3c3-42f3-8b66-6b6d80326eb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17664
14329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.1766414329
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.2749052548
Short name T1879
Test name
Test status
Simulation time 5283652584 ps
CPU time 51.01 seconds
Started Jun 27 06:38:29 PM PDT 24
Finished Jun 27 06:39:25 PM PDT 24
Peak memory 206428 kb
Host smart-4eb202f8-757b-4c29-b396-dd2bcd7912c8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2749052548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.2749052548
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.1716731178
Short name T2104
Test name
Test status
Simulation time 202402223 ps
CPU time 0.83 seconds
Started Jun 27 06:38:28 PM PDT 24
Finished Jun 27 06:38:34 PM PDT 24
Peak memory 206276 kb
Host smart-0f5f83fc-52b7-4bad-800d-7f88b5759247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17167
31178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.1716731178
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.887313889
Short name T2595
Test name
Test status
Simulation time 197696730 ps
CPU time 0.83 seconds
Started Jun 27 06:38:30 PM PDT 24
Finished Jun 27 06:38:35 PM PDT 24
Peak memory 206280 kb
Host smart-07120bbb-5385-4522-9a6c-3139a2471661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88731
3889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.887313889
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.2936210872
Short name T891
Test name
Test status
Simulation time 5816025287 ps
CPU time 49.98 seconds
Started Jun 27 06:38:33 PM PDT 24
Finished Jun 27 06:39:26 PM PDT 24
Peak memory 206252 kb
Host smart-771b5d10-7756-4284-843d-8187d7c3ed93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29362
10872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.2936210872
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.443632231
Short name T1674
Test name
Test status
Simulation time 62453836 ps
CPU time 0.75 seconds
Started Jun 27 06:38:51 PM PDT 24
Finished Jun 27 06:38:55 PM PDT 24
Peak memory 206348 kb
Host smart-4ec5d6bc-001e-4c12-a5a4-f02f1e5adb14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=443632231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.443632231
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.705449091
Short name T2241
Test name
Test status
Simulation time 4162553415 ps
CPU time 5.03 seconds
Started Jun 27 06:38:30 PM PDT 24
Finished Jun 27 06:38:39 PM PDT 24
Peak memory 206444 kb
Host smart-806ea5c5-fca6-4e41-8af5-98cbdb54849f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=705449091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.705449091
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.4032113585
Short name T1333
Test name
Test status
Simulation time 13336984081 ps
CPU time 12.63 seconds
Started Jun 27 06:38:33 PM PDT 24
Finished Jun 27 06:38:49 PM PDT 24
Peak memory 206424 kb
Host smart-c8307a37-fac3-4753-9ef2-fab8ff0ca08f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4032113585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.4032113585
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.2796888810
Short name T1482
Test name
Test status
Simulation time 23425174786 ps
CPU time 24.01 seconds
Started Jun 27 06:38:33 PM PDT 24
Finished Jun 27 06:39:01 PM PDT 24
Peak memory 206496 kb
Host smart-b2a5c67c-bc36-4443-8db9-a2caafbdca25
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2796888810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.2796888810
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.2242345232
Short name T413
Test name
Test status
Simulation time 163650017 ps
CPU time 0.79 seconds
Started Jun 27 06:38:35 PM PDT 24
Finished Jun 27 06:38:39 PM PDT 24
Peak memory 206284 kb
Host smart-7a30759a-03f7-4dad-935b-99808ac4ca83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22423
45232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.2242345232
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.3197482565
Short name T1724
Test name
Test status
Simulation time 157267585 ps
CPU time 0.76 seconds
Started Jun 27 06:38:33 PM PDT 24
Finished Jun 27 06:38:37 PM PDT 24
Peak memory 206276 kb
Host smart-03208bbe-437c-480c-9535-6e90855869a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31974
82565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.3197482565
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.1198666520
Short name T2274
Test name
Test status
Simulation time 321225832 ps
CPU time 1.14 seconds
Started Jun 27 06:38:32 PM PDT 24
Finished Jun 27 06:38:37 PM PDT 24
Peak memory 206276 kb
Host smart-a19d5b6a-2d6e-40e9-83cb-7bf3b45494b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11986
66520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.1198666520
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.3651315507
Short name T2289
Test name
Test status
Simulation time 479133417 ps
CPU time 1.28 seconds
Started Jun 27 06:38:23 PM PDT 24
Finished Jun 27 06:38:27 PM PDT 24
Peak memory 206292 kb
Host smart-0868f943-4ca8-472d-90e7-a95775bf0b6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36513
15507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.3651315507
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.2253298020
Short name T94
Test name
Test status
Simulation time 21593261765 ps
CPU time 37.74 seconds
Started Jun 27 06:38:32 PM PDT 24
Finished Jun 27 06:39:14 PM PDT 24
Peak memory 206428 kb
Host smart-df3e4c82-5107-4284-8fe1-8b2853e4c902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22532
98020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.2253298020
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.4196244777
Short name T95
Test name
Test status
Simulation time 456513141 ps
CPU time 1.27 seconds
Started Jun 27 06:38:33 PM PDT 24
Finished Jun 27 06:38:38 PM PDT 24
Peak memory 206308 kb
Host smart-5e93e2b4-c6af-4632-ad56-4b0c6a73f3ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41962
44777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.4196244777
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.2704817925
Short name T1888
Test name
Test status
Simulation time 173241326 ps
CPU time 0.76 seconds
Started Jun 27 06:38:23 PM PDT 24
Finished Jun 27 06:38:28 PM PDT 24
Peak memory 206268 kb
Host smart-19a162fe-a235-4947-b50a-9deb397a54c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27048
17925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.2704817925
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.4158271489
Short name T691
Test name
Test status
Simulation time 40410182 ps
CPU time 0.68 seconds
Started Jun 27 06:38:33 PM PDT 24
Finished Jun 27 06:38:38 PM PDT 24
Peak memory 206268 kb
Host smart-25e5a06c-e6c1-4c87-bb8e-e0a24f59c2fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41582
71489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.4158271489
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.1331910904
Short name T2589
Test name
Test status
Simulation time 949009887 ps
CPU time 2.27 seconds
Started Jun 27 06:38:31 PM PDT 24
Finished Jun 27 06:38:37 PM PDT 24
Peak memory 206408 kb
Host smart-687e11ec-b6a4-49de-830b-8a2eaa698baa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13319
10904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.1331910904
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.2020128184
Short name T1283
Test name
Test status
Simulation time 238584796 ps
CPU time 2.13 seconds
Started Jun 27 06:38:33 PM PDT 24
Finished Jun 27 06:38:39 PM PDT 24
Peak memory 206308 kb
Host smart-44a6d6fc-59c8-4d92-8b1e-51c41c73fe34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20201
28184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.2020128184
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.1250231999
Short name T1901
Test name
Test status
Simulation time 182202403 ps
CPU time 0.85 seconds
Started Jun 27 06:38:24 PM PDT 24
Finished Jun 27 06:38:29 PM PDT 24
Peak memory 206288 kb
Host smart-adfd828c-24d7-4ce8-8e61-03729ab652c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12502
31999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.1250231999
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.2885817653
Short name T110
Test name
Test status
Simulation time 164666441 ps
CPU time 0.82 seconds
Started Jun 27 06:38:27 PM PDT 24
Finished Jun 27 06:38:33 PM PDT 24
Peak memory 206244 kb
Host smart-6ba9259e-35ce-4339-9cac-4f864192a7df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28858
17653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.2885817653
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.3337175607
Short name T1801
Test name
Test status
Simulation time 153234281 ps
CPU time 0.81 seconds
Started Jun 27 06:38:35 PM PDT 24
Finished Jun 27 06:38:39 PM PDT 24
Peak memory 206188 kb
Host smart-6f0bc997-2d14-4746-851f-dee69843b921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33371
75607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.3337175607
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_invalid_sync.2643871974
Short name T1692
Test name
Test status
Simulation time 6430410370 ps
CPU time 179.94 seconds
Started Jun 27 06:38:33 PM PDT 24
Finished Jun 27 06:41:37 PM PDT 24
Peak memory 206360 kb
Host smart-741b46a5-4daf-4e35-ae9e-76685f031d6d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2643871974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.2643871974
Directory /workspace/24.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.2849816077
Short name T1441
Test name
Test status
Simulation time 229479464 ps
CPU time 0.88 seconds
Started Jun 27 06:38:35 PM PDT 24
Finished Jun 27 06:38:39 PM PDT 24
Peak memory 206272 kb
Host smart-5a53c4f3-360e-415d-a907-c71ff1ba5315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28498
16077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.2849816077
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.3248160666
Short name T2412
Test name
Test status
Simulation time 23293485476 ps
CPU time 20.52 seconds
Started Jun 27 06:38:32 PM PDT 24
Finished Jun 27 06:38:57 PM PDT 24
Peak memory 206316 kb
Host smart-f3bca974-bdd5-441c-8337-2dd433bae825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32481
60666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.3248160666
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.3862664588
Short name T844
Test name
Test status
Simulation time 3290184706 ps
CPU time 4.33 seconds
Started Jun 27 06:38:35 PM PDT 24
Finished Jun 27 06:38:42 PM PDT 24
Peak memory 206332 kb
Host smart-9f680e61-b466-4a45-ac45-db3d4c353edb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38626
64588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.3862664588
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.2075096330
Short name T247
Test name
Test status
Simulation time 10604348735 ps
CPU time 296.9 seconds
Started Jun 27 06:38:35 PM PDT 24
Finished Jun 27 06:43:35 PM PDT 24
Peak memory 206492 kb
Host smart-d1561371-b221-444d-8fc1-6ba4060878bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20750
96330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.2075096330
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.2157227032
Short name T1391
Test name
Test status
Simulation time 5310508876 ps
CPU time 48.24 seconds
Started Jun 27 06:38:35 PM PDT 24
Finished Jun 27 06:39:27 PM PDT 24
Peak memory 206356 kb
Host smart-2e766c98-fd80-4a83-9055-d8bfb027aaff
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2157227032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.2157227032
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.301515070
Short name T335
Test name
Test status
Simulation time 255165080 ps
CPU time 1.01 seconds
Started Jun 27 06:38:35 PM PDT 24
Finished Jun 27 06:38:39 PM PDT 24
Peak memory 206240 kb
Host smart-52c05e51-23f0-4573-81c2-1a8b2de95454
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=301515070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.301515070
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.242778118
Short name T1591
Test name
Test status
Simulation time 190010582 ps
CPU time 0.91 seconds
Started Jun 27 06:38:28 PM PDT 24
Finished Jun 27 06:38:34 PM PDT 24
Peak memory 206264 kb
Host smart-a591407d-eed0-45ee-b48c-71999413ec1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24277
8118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.242778118
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.197625767
Short name T1269
Test name
Test status
Simulation time 3985894579 ps
CPU time 28.39 seconds
Started Jun 27 06:38:35 PM PDT 24
Finished Jun 27 06:39:07 PM PDT 24
Peak memory 206312 kb
Host smart-036512da-6438-4fec-9365-21e3b711e5df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19762
5767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.197625767
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.2166999572
Short name T1178
Test name
Test status
Simulation time 5371891936 ps
CPU time 39.62 seconds
Started Jun 27 06:38:31 PM PDT 24
Finished Jun 27 06:39:15 PM PDT 24
Peak memory 206404 kb
Host smart-9e574ebd-a416-4bb9-bf89-d83fb1cb4672
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2166999572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.2166999572
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.3707322907
Short name T2132
Test name
Test status
Simulation time 156459640 ps
CPU time 0.79 seconds
Started Jun 27 06:38:35 PM PDT 24
Finished Jun 27 06:38:39 PM PDT 24
Peak memory 206240 kb
Host smart-1d2dde2d-d6c5-4dc4-ab98-d3fde0f1a6b5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3707322907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.3707322907
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.4213463335
Short name T731
Test name
Test status
Simulation time 161534186 ps
CPU time 0.81 seconds
Started Jun 27 06:38:33 PM PDT 24
Finished Jun 27 06:38:38 PM PDT 24
Peak memory 206212 kb
Host smart-0b69c1ee-c18b-411e-9a7b-2b80c813221f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42134
63335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.4213463335
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.678071901
Short name T2123
Test name
Test status
Simulation time 241160333 ps
CPU time 0.84 seconds
Started Jun 27 06:38:22 PM PDT 24
Finished Jun 27 06:38:26 PM PDT 24
Peak memory 206272 kb
Host smart-284d9dcd-4c50-4bb6-894a-c14b8c40f82a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67807
1901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.678071901
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.1577828616
Short name T2454
Test name
Test status
Simulation time 231971197 ps
CPU time 0.86 seconds
Started Jun 27 06:38:24 PM PDT 24
Finished Jun 27 06:38:29 PM PDT 24
Peak memory 206280 kb
Host smart-5bca9431-dbf7-480c-9618-c4b14c42a7ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15778
28616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.1577828616
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.4128882895
Short name T2272
Test name
Test status
Simulation time 166057785 ps
CPU time 0.79 seconds
Started Jun 27 06:38:33 PM PDT 24
Finished Jun 27 06:38:38 PM PDT 24
Peak memory 206244 kb
Host smart-1443ae5a-395d-4d7e-bc8d-67a34dfd5c91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41288
82895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.4128882895
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.2706231488
Short name T344
Test name
Test status
Simulation time 199280021 ps
CPU time 0.83 seconds
Started Jun 27 06:38:23 PM PDT 24
Finished Jun 27 06:38:28 PM PDT 24
Peak memory 206272 kb
Host smart-ac886dc2-1ac5-4c54-8fd7-cbc72e815e80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27062
31488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.2706231488
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.782429888
Short name T943
Test name
Test status
Simulation time 149182453 ps
CPU time 0.8 seconds
Started Jun 27 06:38:21 PM PDT 24
Finished Jun 27 06:38:24 PM PDT 24
Peak memory 206276 kb
Host smart-68a5db08-98f1-41e4-98fc-11ca1e7ae52d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78242
9888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.782429888
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.858761204
Short name T497
Test name
Test status
Simulation time 170738840 ps
CPU time 0.86 seconds
Started Jun 27 06:38:24 PM PDT 24
Finished Jun 27 06:38:28 PM PDT 24
Peak memory 206248 kb
Host smart-b3e5a721-e802-45f4-9bf3-06d25616c018
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=858761204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.858761204
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.2233226281
Short name T2402
Test name
Test status
Simulation time 175623884 ps
CPU time 0.78 seconds
Started Jun 27 06:38:53 PM PDT 24
Finished Jun 27 06:38:58 PM PDT 24
Peak memory 206268 kb
Host smart-2c8d020a-6108-44f2-a4e6-b1c088effeec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22332
26281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.2233226281
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.465727270
Short name T2348
Test name
Test status
Simulation time 58490005 ps
CPU time 0.74 seconds
Started Jun 27 06:38:55 PM PDT 24
Finished Jun 27 06:39:02 PM PDT 24
Peak memory 206276 kb
Host smart-68f42fd3-3b07-4a8c-acd7-51ada2aff973
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46572
7270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.465727270
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.1909239093
Short name T719
Test name
Test status
Simulation time 21518132884 ps
CPU time 53.6 seconds
Started Jun 27 06:38:56 PM PDT 24
Finished Jun 27 06:39:56 PM PDT 24
Peak memory 206424 kb
Host smart-f5cd0859-0f64-4c81-9030-26dd903e37c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19092
39093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.1909239093
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.2223842131
Short name T1225
Test name
Test status
Simulation time 178268423 ps
CPU time 0.83 seconds
Started Jun 27 06:38:50 PM PDT 24
Finished Jun 27 06:38:52 PM PDT 24
Peak memory 206276 kb
Host smart-a8bec9bd-28d8-4df9-aa97-0b7fd6c896c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22238
42131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.2223842131
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.950249065
Short name T1555
Test name
Test status
Simulation time 240941685 ps
CPU time 0.88 seconds
Started Jun 27 06:38:50 PM PDT 24
Finished Jun 27 06:38:52 PM PDT 24
Peak memory 206288 kb
Host smart-74a945ce-ecaa-4707-bbb1-20d085ce640f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95024
9065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.950249065
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.893591238
Short name T771
Test name
Test status
Simulation time 230033288 ps
CPU time 0.95 seconds
Started Jun 27 06:38:53 PM PDT 24
Finished Jun 27 06:38:57 PM PDT 24
Peak memory 206256 kb
Host smart-cb034bd5-142e-4e65-b94d-de087c92dba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89359
1238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.893591238
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.3354807684
Short name T1151
Test name
Test status
Simulation time 161748126 ps
CPU time 0.8 seconds
Started Jun 27 06:38:52 PM PDT 24
Finished Jun 27 06:38:56 PM PDT 24
Peak memory 206272 kb
Host smart-cb782420-54c1-4bfc-9685-47a3d04789db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33548
07684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.3354807684
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.3032625988
Short name T1350
Test name
Test status
Simulation time 143985633 ps
CPU time 0.82 seconds
Started Jun 27 06:38:49 PM PDT 24
Finished Jun 27 06:38:51 PM PDT 24
Peak memory 206268 kb
Host smart-9ab85aa3-f454-4ff0-b075-addf1c3d2925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30326
25988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.3032625988
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.3089331022
Short name T2371
Test name
Test status
Simulation time 155761074 ps
CPU time 0.75 seconds
Started Jun 27 06:38:50 PM PDT 24
Finished Jun 27 06:38:53 PM PDT 24
Peak memory 206276 kb
Host smart-fecc9da5-c047-4299-98a1-f400c7e1adc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30893
31022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.3089331022
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.3727769625
Short name T1138
Test name
Test status
Simulation time 206971617 ps
CPU time 0.84 seconds
Started Jun 27 06:38:55 PM PDT 24
Finished Jun 27 06:39:01 PM PDT 24
Peak memory 206312 kb
Host smart-ea283ce7-737e-440e-87b0-2a811884249a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37277
69625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.3727769625
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.3144864413
Short name T1376
Test name
Test status
Simulation time 258380984 ps
CPU time 0.91 seconds
Started Jun 27 06:38:50 PM PDT 24
Finished Jun 27 06:38:53 PM PDT 24
Peak memory 206296 kb
Host smart-a0ee1476-6701-4e00-90f4-d7939487da1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31448
64413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.3144864413
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.3510830240
Short name T2102
Test name
Test status
Simulation time 232935384 ps
CPU time 1 seconds
Started Jun 27 06:38:55 PM PDT 24
Finished Jun 27 06:39:02 PM PDT 24
Peak memory 206284 kb
Host smart-b7a5d02e-fefd-4768-85c5-6a8387d156c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35108
30240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.3510830240
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.1406697141
Short name T1820
Test name
Test status
Simulation time 153720936 ps
CPU time 0.75 seconds
Started Jun 27 06:38:49 PM PDT 24
Finished Jun 27 06:38:51 PM PDT 24
Peak memory 206304 kb
Host smart-3add10fd-52c1-4d83-a06f-0b1f2d7ba267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14066
97141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.1406697141
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.3122824616
Short name T377
Test name
Test status
Simulation time 3403928592 ps
CPU time 90.53 seconds
Started Jun 27 06:38:53 PM PDT 24
Finished Jun 27 06:40:27 PM PDT 24
Peak memory 206600 kb
Host smart-3e755172-a840-4a25-83c6-ebe95f2ed240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31228
24616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.3122824616
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.3342867710
Short name T535
Test name
Test status
Simulation time 44843231 ps
CPU time 0.76 seconds
Started Jun 27 06:38:50 PM PDT 24
Finished Jun 27 06:38:53 PM PDT 24
Peak memory 206352 kb
Host smart-0053e5b2-fb70-406c-a6d8-113fc53440b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3342867710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.3342867710
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.312135658
Short name T2032
Test name
Test status
Simulation time 3913501993 ps
CPU time 4.83 seconds
Started Jun 27 06:38:52 PM PDT 24
Finished Jun 27 06:39:00 PM PDT 24
Peak memory 206360 kb
Host smart-703ea80d-1177-4a53-a0e2-1f5b8fd02043
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=312135658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.312135658
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.1710542676
Short name T1408
Test name
Test status
Simulation time 13400065301 ps
CPU time 12.29 seconds
Started Jun 27 06:38:55 PM PDT 24
Finished Jun 27 06:39:13 PM PDT 24
Peak memory 206156 kb
Host smart-25774c43-c19b-4ef3-871d-ce9c3c765ad5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1710542676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.1710542676
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.4107520033
Short name T911
Test name
Test status
Simulation time 23456546797 ps
CPU time 25.4 seconds
Started Jun 27 06:38:54 PM PDT 24
Finished Jun 27 06:39:25 PM PDT 24
Peak memory 206500 kb
Host smart-20d1af06-a0ee-4070-a2d3-377e144e8ff7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4107520033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.4107520033
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.1497413680
Short name T1839
Test name
Test status
Simulation time 166102374 ps
CPU time 0.9 seconds
Started Jun 27 06:38:54 PM PDT 24
Finished Jun 27 06:38:59 PM PDT 24
Peak memory 206300 kb
Host smart-0f78f51a-cc8a-42e8-8956-ada8d13b830c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14974
13680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.1497413680
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.3897437428
Short name T761
Test name
Test status
Simulation time 168868151 ps
CPU time 0.83 seconds
Started Jun 27 06:38:50 PM PDT 24
Finished Jun 27 06:38:52 PM PDT 24
Peak memory 206272 kb
Host smart-5d716364-b975-4dce-90a5-764a5e0335d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38974
37428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.3897437428
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.692241892
Short name T1763
Test name
Test status
Simulation time 616690771 ps
CPU time 1.84 seconds
Started Jun 27 06:38:55 PM PDT 24
Finished Jun 27 06:39:03 PM PDT 24
Peak memory 206368 kb
Host smart-8fa00859-0139-4b32-a684-c090b1b2ac83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69224
1892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.692241892
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.1688242501
Short name T2508
Test name
Test status
Simulation time 694574978 ps
CPU time 1.7 seconds
Started Jun 27 06:38:50 PM PDT 24
Finished Jun 27 06:38:53 PM PDT 24
Peak memory 206336 kb
Host smart-7bc12217-e31d-4632-8b72-a7868720013b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16882
42501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.1688242501
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.541716438
Short name T166
Test name
Test status
Simulation time 16351421545 ps
CPU time 30.75 seconds
Started Jun 27 06:38:52 PM PDT 24
Finished Jun 27 06:39:26 PM PDT 24
Peak memory 206472 kb
Host smart-ae5e7960-bba2-4479-83b0-d39a4af6347d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54171
6438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.541716438
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.2244434550
Short name T1185
Test name
Test status
Simulation time 485799304 ps
CPU time 1.28 seconds
Started Jun 27 06:38:51 PM PDT 24
Finished Jun 27 06:38:54 PM PDT 24
Peak memory 206276 kb
Host smart-130352f7-3bbc-4ed7-8e7d-a00986c9f629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22444
34550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.2244434550
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_enable.2482996255
Short name T1549
Test name
Test status
Simulation time 82621316 ps
CPU time 0.7 seconds
Started Jun 27 06:38:58 PM PDT 24
Finished Jun 27 06:39:04 PM PDT 24
Peak memory 206288 kb
Host smart-bc25389d-b523-439c-86db-785ee7a62818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24829
96255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.2482996255
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.4131556633
Short name T2043
Test name
Test status
Simulation time 820250427 ps
CPU time 2.12 seconds
Started Jun 27 06:38:54 PM PDT 24
Finished Jun 27 06:39:00 PM PDT 24
Peak memory 206440 kb
Host smart-1016cc83-1f33-48cc-8443-3fa15a7cd537
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41315
56633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.4131556633
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.558628081
Short name T1287
Test name
Test status
Simulation time 357319586 ps
CPU time 2.57 seconds
Started Jun 27 06:38:52 PM PDT 24
Finished Jun 27 06:38:58 PM PDT 24
Peak memory 206504 kb
Host smart-180be523-ffcf-470e-9017-96c2c98d8455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55862
8081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.558628081
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.4000807042
Short name T1276
Test name
Test status
Simulation time 155516401 ps
CPU time 0.87 seconds
Started Jun 27 06:38:53 PM PDT 24
Finished Jun 27 06:38:59 PM PDT 24
Peak memory 206252 kb
Host smart-ab30b797-d216-4496-9540-17a8ea5f3073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40008
07042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.4000807042
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.1045848735
Short name T1653
Test name
Test status
Simulation time 159671656 ps
CPU time 0.81 seconds
Started Jun 27 06:38:53 PM PDT 24
Finished Jun 27 06:38:57 PM PDT 24
Peak memory 206264 kb
Host smart-11986b96-5c76-4e8b-8a56-5aa9fd3f9e3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10458
48735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.1045848735
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.2852695792
Short name T2615
Test name
Test status
Simulation time 243014341 ps
CPU time 0.89 seconds
Started Jun 27 06:38:51 PM PDT 24
Finished Jun 27 06:38:53 PM PDT 24
Peak memory 206288 kb
Host smart-bab8d12c-bee8-4dfa-a89b-a9d08f362da7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28526
95792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.2852695792
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.3638743213
Short name T1187
Test name
Test status
Simulation time 197512934 ps
CPU time 0.83 seconds
Started Jun 27 06:38:50 PM PDT 24
Finished Jun 27 06:38:52 PM PDT 24
Peak memory 206276 kb
Host smart-ecab296a-e099-4e14-80b4-4ae509847704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36387
43213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.3638743213
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.683310692
Short name T2337
Test name
Test status
Simulation time 23347512163 ps
CPU time 21.71 seconds
Started Jun 27 06:38:53 PM PDT 24
Finished Jun 27 06:39:20 PM PDT 24
Peak memory 206520 kb
Host smart-9a34714b-343c-48f7-b63c-f21289c0f033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68331
0692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.683310692
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.3610232596
Short name T2202
Test name
Test status
Simulation time 3318660246 ps
CPU time 3.78 seconds
Started Jun 27 06:38:52 PM PDT 24
Finished Jun 27 06:38:59 PM PDT 24
Peak memory 206336 kb
Host smart-4453e303-6ade-449a-bf58-bcfdb530ba11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36102
32596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.3610232596
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.3331362154
Short name T1524
Test name
Test status
Simulation time 8830982074 ps
CPU time 81.06 seconds
Started Jun 27 06:38:54 PM PDT 24
Finished Jun 27 06:40:20 PM PDT 24
Peak memory 206488 kb
Host smart-6866b37f-4150-4c18-a18f-6a021b2f9a4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33313
62154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.3331362154
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.238923511
Short name T1134
Test name
Test status
Simulation time 4784480372 ps
CPU time 122.04 seconds
Started Jun 27 06:38:55 PM PDT 24
Finished Jun 27 06:41:03 PM PDT 24
Peak memory 206440 kb
Host smart-a98f1e5c-02e5-4b8e-96c2-32afb2492826
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=238923511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.238923511
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.1964423950
Short name T1039
Test name
Test status
Simulation time 240287770 ps
CPU time 1.02 seconds
Started Jun 27 06:38:55 PM PDT 24
Finished Jun 27 06:39:01 PM PDT 24
Peak memory 206292 kb
Host smart-8b4e4599-884f-4643-84f6-fd11e0deb215
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1964423950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.1964423950
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.582063970
Short name T1058
Test name
Test status
Simulation time 220716269 ps
CPU time 0.95 seconds
Started Jun 27 06:38:55 PM PDT 24
Finished Jun 27 06:39:02 PM PDT 24
Peak memory 206080 kb
Host smart-48cb1681-f756-4b36-8122-0d0ab338cad6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58206
3970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.582063970
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.789470184
Short name T1894
Test name
Test status
Simulation time 4680594426 ps
CPU time 124.2 seconds
Started Jun 27 06:38:51 PM PDT 24
Finished Jun 27 06:40:58 PM PDT 24
Peak memory 206432 kb
Host smart-edce6970-4d8f-4f94-bc62-0bb6e195e857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78947
0184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.789470184
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.3215642802
Short name T665
Test name
Test status
Simulation time 3778986382 ps
CPU time 26.51 seconds
Started Jun 27 06:38:54 PM PDT 24
Finished Jun 27 06:39:26 PM PDT 24
Peak memory 206516 kb
Host smart-94f36382-d188-4414-9c44-131e7c0b7578
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3215642802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.3215642802
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.2920925474
Short name T1249
Test name
Test status
Simulation time 179900521 ps
CPU time 0.85 seconds
Started Jun 27 06:38:55 PM PDT 24
Finished Jun 27 06:39:01 PM PDT 24
Peak memory 206232 kb
Host smart-3d00ada9-0e93-4406-925e-b2d8f1e18ad1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2920925474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.2920925474
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.3874323892
Short name T986
Test name
Test status
Simulation time 185278730 ps
CPU time 0.88 seconds
Started Jun 27 06:38:53 PM PDT 24
Finished Jun 27 06:38:57 PM PDT 24
Peak memory 206260 kb
Host smart-5d3957db-92a7-40f2-99bf-b6108fa6d85e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38743
23892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.3874323892
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.807262041
Short name T1638
Test name
Test status
Simulation time 217459205 ps
CPU time 0.88 seconds
Started Jun 27 06:38:53 PM PDT 24
Finished Jun 27 06:38:58 PM PDT 24
Peak memory 206208 kb
Host smart-ee14270c-6a63-4402-8dd6-8528d57f9bf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80726
2041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.807262041
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.1611423963
Short name T366
Test name
Test status
Simulation time 171090059 ps
CPU time 0.77 seconds
Started Jun 27 06:38:53 PM PDT 24
Finished Jun 27 06:38:59 PM PDT 24
Peak memory 206252 kb
Host smart-f312c76d-9d96-4555-be85-4786f176d634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16114
23963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.1611423963
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.2340442400
Short name T1889
Test name
Test status
Simulation time 157238475 ps
CPU time 0.81 seconds
Started Jun 27 06:38:55 PM PDT 24
Finished Jun 27 06:39:01 PM PDT 24
Peak memory 206240 kb
Host smart-d8873ab7-4faf-4ae7-9656-491f701ef907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23404
42400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.2340442400
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.3107543406
Short name T828
Test name
Test status
Simulation time 194885984 ps
CPU time 0.83 seconds
Started Jun 27 06:38:49 PM PDT 24
Finished Jun 27 06:38:51 PM PDT 24
Peak memory 206292 kb
Host smart-e4926ec4-2d99-40cc-adda-a48dd3a9ff96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31075
43406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.3107543406
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.4123201613
Short name T180
Test name
Test status
Simulation time 214780567 ps
CPU time 0.86 seconds
Started Jun 27 06:38:56 PM PDT 24
Finished Jun 27 06:39:03 PM PDT 24
Peak memory 206256 kb
Host smart-c86aff5c-4194-4ee1-90d8-115127df3694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41232
01613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.4123201613
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.3834123118
Short name T1499
Test name
Test status
Simulation time 224425884 ps
CPU time 0.89 seconds
Started Jun 27 06:38:55 PM PDT 24
Finished Jun 27 06:39:01 PM PDT 24
Peak memory 206296 kb
Host smart-e63ab21d-4800-4247-ae0f-8ac3639a2d9a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3834123118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.3834123118
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.1142364885
Short name T2009
Test name
Test status
Simulation time 143599365 ps
CPU time 0.76 seconds
Started Jun 27 06:38:54 PM PDT 24
Finished Jun 27 06:39:00 PM PDT 24
Peak memory 206280 kb
Host smart-a722008d-9255-44dd-b3c2-eb06e983f941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11423
64885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.1142364885
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.2698754828
Short name T2209
Test name
Test status
Simulation time 35255340 ps
CPU time 0.72 seconds
Started Jun 27 06:38:54 PM PDT 24
Finished Jun 27 06:38:59 PM PDT 24
Peak memory 206216 kb
Host smart-98ae56e4-5082-4a8d-9213-7b4bae4db5e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26987
54828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.2698754828
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.97897524
Short name T1758
Test name
Test status
Simulation time 12400670927 ps
CPU time 26.12 seconds
Started Jun 27 06:38:51 PM PDT 24
Finished Jun 27 06:39:19 PM PDT 24
Peak memory 206520 kb
Host smart-a8d14b37-f5b0-4888-817d-d3d553da9ab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97897
524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.97897524
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.2955283723
Short name T250
Test name
Test status
Simulation time 146949082 ps
CPU time 0.83 seconds
Started Jun 27 06:38:54 PM PDT 24
Finished Jun 27 06:39:00 PM PDT 24
Peak memory 206296 kb
Host smart-2aa7d526-8319-4c55-aab6-73159f2689e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29552
83723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.2955283723
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.474241388
Short name T1931
Test name
Test status
Simulation time 221161134 ps
CPU time 0.86 seconds
Started Jun 27 06:38:54 PM PDT 24
Finished Jun 27 06:39:00 PM PDT 24
Peak memory 206216 kb
Host smart-81c7eb0e-55fe-4e92-aa23-0997d3240de9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47424
1388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.474241388
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.3175007378
Short name T1784
Test name
Test status
Simulation time 190571207 ps
CPU time 0.85 seconds
Started Jun 27 06:38:55 PM PDT 24
Finished Jun 27 06:39:02 PM PDT 24
Peak memory 206120 kb
Host smart-14a74503-ba9b-4a6a-bc38-bddf49b64f5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31750
07378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.3175007378
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.2943760636
Short name T787
Test name
Test status
Simulation time 178065322 ps
CPU time 0.89 seconds
Started Jun 27 06:38:55 PM PDT 24
Finished Jun 27 06:39:02 PM PDT 24
Peak memory 206104 kb
Host smart-11ae7d01-a069-43fd-b0e6-1760d529d174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29437
60636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.2943760636
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.1982453036
Short name T2207
Test name
Test status
Simulation time 150226213 ps
CPU time 0.75 seconds
Started Jun 27 06:38:53 PM PDT 24
Finished Jun 27 06:38:56 PM PDT 24
Peak memory 206208 kb
Host smart-6eb99001-69da-47ea-94ed-e5fab320dc2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19824
53036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.1982453036
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.141788173
Short name T2543
Test name
Test status
Simulation time 148103276 ps
CPU time 0.76 seconds
Started Jun 27 06:38:53 PM PDT 24
Finished Jun 27 06:38:59 PM PDT 24
Peak memory 206232 kb
Host smart-d424b39f-5cbd-493c-8da6-c973b4cd41b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14178
8173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.141788173
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.1016045843
Short name T572
Test name
Test status
Simulation time 152109902 ps
CPU time 0.79 seconds
Started Jun 27 06:38:56 PM PDT 24
Finished Jun 27 06:39:03 PM PDT 24
Peak memory 206316 kb
Host smart-fd2ba4bb-ba3a-4e4a-824c-b917a19fc10d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10160
45843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.1016045843
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.2698584814
Short name T1304
Test name
Test status
Simulation time 241515481 ps
CPU time 0.98 seconds
Started Jun 27 06:38:55 PM PDT 24
Finished Jun 27 06:39:02 PM PDT 24
Peak memory 206284 kb
Host smart-c71b0c33-8407-4cd6-9892-a163c35af49b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26985
84814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.2698584814
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.231779754
Short name T543
Test name
Test status
Simulation time 3729249177 ps
CPU time 27.18 seconds
Started Jun 27 06:38:53 PM PDT 24
Finished Jun 27 06:39:24 PM PDT 24
Peak memory 206408 kb
Host smart-e867997b-3593-4f32-9957-1b29b0679d84
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=231779754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.231779754
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.1009379439
Short name T2530
Test name
Test status
Simulation time 179857125 ps
CPU time 0.87 seconds
Started Jun 27 06:38:53 PM PDT 24
Finished Jun 27 06:38:57 PM PDT 24
Peak memory 206440 kb
Host smart-588f25d7-5b5b-45ec-a412-acbf935f5519
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10093
79439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.1009379439
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.1842108051
Short name T1434
Test name
Test status
Simulation time 161271482 ps
CPU time 0.8 seconds
Started Jun 27 06:38:54 PM PDT 24
Finished Jun 27 06:39:01 PM PDT 24
Peak memory 206296 kb
Host smart-e0c99a6b-1afe-4afb-8bd7-f4dcb80386c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18421
08051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.1842108051
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.86607800
Short name T1323
Test name
Test status
Simulation time 5924332682 ps
CPU time 53.61 seconds
Started Jun 27 06:38:54 PM PDT 24
Finished Jun 27 06:39:52 PM PDT 24
Peak memory 206348 kb
Host smart-eb2433a9-7dce-4a4a-9053-0dead49439df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86607
800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.86607800
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.990319226
Short name T403
Test name
Test status
Simulation time 60123826 ps
CPU time 0.8 seconds
Started Jun 27 06:39:12 PM PDT 24
Finished Jun 27 06:39:20 PM PDT 24
Peak memory 206300 kb
Host smart-d8eafbce-c443-413c-b313-eb27e6eb6218
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=990319226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.990319226
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.1403657702
Short name T1734
Test name
Test status
Simulation time 4382267463 ps
CPU time 5.44 seconds
Started Jun 27 06:38:56 PM PDT 24
Finished Jun 27 06:39:07 PM PDT 24
Peak memory 206432 kb
Host smart-6c0c11ec-96eb-4de6-ba20-0e57235ea878
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1403657702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.1403657702
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.2896153872
Short name T519
Test name
Test status
Simulation time 13417573586 ps
CPU time 11.59 seconds
Started Jun 27 06:38:57 PM PDT 24
Finished Jun 27 06:39:14 PM PDT 24
Peak memory 206408 kb
Host smart-87b57cdf-7a26-462f-aa34-8996aa691b6a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2896153872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.2896153872
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.1773764956
Short name T2432
Test name
Test status
Simulation time 23473885137 ps
CPU time 24.1 seconds
Started Jun 27 06:38:52 PM PDT 24
Finished Jun 27 06:39:19 PM PDT 24
Peak memory 206392 kb
Host smart-b6d43f5e-9845-4af4-abe7-8303e65e2960
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1773764956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.1773764956
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.3209589979
Short name T1824
Test name
Test status
Simulation time 225511790 ps
CPU time 0.95 seconds
Started Jun 27 06:38:56 PM PDT 24
Finished Jun 27 06:39:03 PM PDT 24
Peak memory 206304 kb
Host smart-37dd3164-c41b-44cb-926a-8d27f7205d71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32095
89979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.3209589979
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.3231861358
Short name T854
Test name
Test status
Simulation time 182391227 ps
CPU time 0.79 seconds
Started Jun 27 06:38:56 PM PDT 24
Finished Jun 27 06:39:03 PM PDT 24
Peak memory 206300 kb
Host smart-e77177f9-512e-47b3-a88b-f6d3600bcbbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32318
61358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.3231861358
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.139785932
Short name T920
Test name
Test status
Simulation time 465585295 ps
CPU time 1.4 seconds
Started Jun 27 06:38:54 PM PDT 24
Finished Jun 27 06:39:01 PM PDT 24
Peak memory 206260 kb
Host smart-b15a09bb-9c46-4a4c-9f02-15236275b23c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13978
5932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.139785932
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.3089385795
Short name T2569
Test name
Test status
Simulation time 1010286961 ps
CPU time 2.2 seconds
Started Jun 27 06:38:55 PM PDT 24
Finished Jun 27 06:39:02 PM PDT 24
Peak memory 206360 kb
Host smart-d660c548-5da4-42fc-8c9f-7b03ee5dd49e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30893
85795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.3089385795
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.3650464942
Short name T1013
Test name
Test status
Simulation time 21417439756 ps
CPU time 39.28 seconds
Started Jun 27 06:38:53 PM PDT 24
Finished Jun 27 06:39:37 PM PDT 24
Peak memory 206400 kb
Host smart-b6ddb9ca-e3a9-44cd-9f8a-1bc41bed7f5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36504
64942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.3650464942
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.4145889938
Short name T96
Test name
Test status
Simulation time 427692157 ps
CPU time 1.28 seconds
Started Jun 27 06:38:56 PM PDT 24
Finished Jun 27 06:39:03 PM PDT 24
Peak memory 206280 kb
Host smart-e1ac3ebe-1882-47e0-91b5-d57dfae32bfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41458
89938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.4145889938
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.4088194696
Short name T1834
Test name
Test status
Simulation time 158836472 ps
CPU time 0.75 seconds
Started Jun 27 06:38:56 PM PDT 24
Finished Jun 27 06:39:02 PM PDT 24
Peak memory 206192 kb
Host smart-fd0b57ca-c4e7-42ff-9fe5-f036b9603b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40881
94696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.4088194696
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.2077476490
Short name T1338
Test name
Test status
Simulation time 78030572 ps
CPU time 0.71 seconds
Started Jun 27 06:38:55 PM PDT 24
Finished Jun 27 06:39:01 PM PDT 24
Peak memory 206232 kb
Host smart-a72adae6-7ef6-4bfb-9a69-babd873101f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20774
76490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.2077476490
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.2280886175
Short name T1056
Test name
Test status
Simulation time 900009101 ps
CPU time 2.09 seconds
Started Jun 27 06:38:56 PM PDT 24
Finished Jun 27 06:39:04 PM PDT 24
Peak memory 206352 kb
Host smart-76ea7646-cb74-4c9a-855d-41a12736ff52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22808
86175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.2280886175
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.425671065
Short name T1487
Test name
Test status
Simulation time 325971192 ps
CPU time 2.02 seconds
Started Jun 27 06:38:56 PM PDT 24
Finished Jun 27 06:39:04 PM PDT 24
Peak memory 206348 kb
Host smart-61f95013-ab52-4ad6-97d5-7524ead4a67e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42567
1065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.425671065
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.2488482388
Short name T1277
Test name
Test status
Simulation time 221327650 ps
CPU time 0.88 seconds
Started Jun 27 06:38:57 PM PDT 24
Finished Jun 27 06:39:04 PM PDT 24
Peak memory 206280 kb
Host smart-780b0cbf-2210-4251-a05f-41d001a3ebdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24884
82388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.2488482388
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.1018321888
Short name T639
Test name
Test status
Simulation time 148321955 ps
CPU time 0.81 seconds
Started Jun 27 06:38:55 PM PDT 24
Finished Jun 27 06:39:01 PM PDT 24
Peak memory 206240 kb
Host smart-50886168-0765-4698-9355-fd2e321d29b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10183
21888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.1018321888
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.3443537080
Short name T805
Test name
Test status
Simulation time 183972074 ps
CPU time 0.82 seconds
Started Jun 27 06:38:55 PM PDT 24
Finished Jun 27 06:39:02 PM PDT 24
Peak memory 206316 kb
Host smart-8bf3f3ba-cf8a-43d0-99f7-77625a181951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34435
37080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.3443537080
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_invalid_sync.3781306142
Short name T2264
Test name
Test status
Simulation time 8010313775 ps
CPU time 79.23 seconds
Started Jun 27 06:38:54 PM PDT 24
Finished Jun 27 06:40:18 PM PDT 24
Peak memory 206436 kb
Host smart-714c3b76-0bfc-4325-ac82-b1e7ac64f3fe
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3781306142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.3781306142
Directory /workspace/26.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.1220123761
Short name T1368
Test name
Test status
Simulation time 183511091 ps
CPU time 0.84 seconds
Started Jun 27 06:38:56 PM PDT 24
Finished Jun 27 06:39:03 PM PDT 24
Peak memory 206264 kb
Host smart-97bb50e5-c2c6-4aa4-b98a-6539f4731c9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12201
23761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.1220123761
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.2050046446
Short name T453
Test name
Test status
Simulation time 23300057925 ps
CPU time 23.02 seconds
Started Jun 27 06:38:54 PM PDT 24
Finished Jun 27 06:39:23 PM PDT 24
Peak memory 206320 kb
Host smart-1e3e712b-c35f-43d3-8f08-b4af8b0a1070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20500
46446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.2050046446
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.505109577
Short name T2212
Test name
Test status
Simulation time 3346207271 ps
CPU time 3.87 seconds
Started Jun 27 06:39:14 PM PDT 24
Finished Jun 27 06:39:28 PM PDT 24
Peak memory 206264 kb
Host smart-98bccd13-607a-433b-bf94-1052592063ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50510
9577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.505109577
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.4214512893
Short name T1646
Test name
Test status
Simulation time 5754401604 ps
CPU time 39.99 seconds
Started Jun 27 06:39:10 PM PDT 24
Finished Jun 27 06:39:53 PM PDT 24
Peak memory 206488 kb
Host smart-48e286fb-b5ca-4926-a198-3bcecee6f463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42145
12893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.4214512893
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.1539963356
Short name T637
Test name
Test status
Simulation time 4671276547 ps
CPU time 31.68 seconds
Started Jun 27 06:39:12 PM PDT 24
Finished Jun 27 06:39:51 PM PDT 24
Peak memory 206460 kb
Host smart-465ffd07-a31e-4b80-bfc6-693584c4d8b1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1539963356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.1539963356
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.2070859860
Short name T2114
Test name
Test status
Simulation time 231845470 ps
CPU time 0.94 seconds
Started Jun 27 06:39:09 PM PDT 24
Finished Jun 27 06:39:12 PM PDT 24
Peak memory 206300 kb
Host smart-4adc62d0-16a7-4227-b974-0ea8b6866e23
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2070859860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.2070859860
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.168058514
Short name T789
Test name
Test status
Simulation time 200224831 ps
CPU time 0.89 seconds
Started Jun 27 06:39:15 PM PDT 24
Finished Jun 27 06:39:28 PM PDT 24
Peak memory 206280 kb
Host smart-d605a306-a4b1-4303-a69b-a8bcaefa6278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16805
8514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.168058514
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.1920379110
Short name T1525
Test name
Test status
Simulation time 4539034689 ps
CPU time 123.95 seconds
Started Jun 27 06:39:10 PM PDT 24
Finished Jun 27 06:41:17 PM PDT 24
Peak memory 206440 kb
Host smart-f3710741-5a1a-41fb-984d-cd459f0e2457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19203
79110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.1920379110
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.4066205323
Short name T2266
Test name
Test status
Simulation time 4093900907 ps
CPU time 37.78 seconds
Started Jun 27 06:39:09 PM PDT 24
Finished Jun 27 06:39:49 PM PDT 24
Peak memory 206480 kb
Host smart-0200a5f5-08b2-4b0f-92d9-fdc3b157a823
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4066205323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.4066205323
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.291778723
Short name T317
Test name
Test status
Simulation time 211391309 ps
CPU time 0.85 seconds
Started Jun 27 06:39:15 PM PDT 24
Finished Jun 27 06:39:27 PM PDT 24
Peak memory 206288 kb
Host smart-b1f76706-43ec-4d57-9eb0-e7e0c0e00765
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=291778723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.291778723
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.1741737224
Short name T2319
Test name
Test status
Simulation time 171876338 ps
CPU time 0.78 seconds
Started Jun 27 06:39:12 PM PDT 24
Finished Jun 27 06:39:21 PM PDT 24
Peak memory 206284 kb
Host smart-c1b90172-e9a0-472e-adbe-0ad0d272df2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17417
37224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.1741737224
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.4220450446
Short name T140
Test name
Test status
Simulation time 197637101 ps
CPU time 0.86 seconds
Started Jun 27 06:39:12 PM PDT 24
Finished Jun 27 06:39:19 PM PDT 24
Peak memory 206460 kb
Host smart-bce6f71b-3d3d-4730-b1ba-e35048c4121b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42204
50446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.4220450446
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.3663063773
Short name T2391
Test name
Test status
Simulation time 163694324 ps
CPU time 0.81 seconds
Started Jun 27 06:39:14 PM PDT 24
Finished Jun 27 06:39:25 PM PDT 24
Peak memory 206240 kb
Host smart-ab6e88ce-1a45-4076-900e-54d3cc83f3ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36630
63773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.3663063773
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.161223130
Short name T2351
Test name
Test status
Simulation time 229301208 ps
CPU time 0.87 seconds
Started Jun 27 06:39:18 PM PDT 24
Finished Jun 27 06:39:32 PM PDT 24
Peak memory 206260 kb
Host smart-3fa401c6-9bf9-47db-8efb-bcd47524a308
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16122
3130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.161223130
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.674089742
Short name T415
Test name
Test status
Simulation time 166569712 ps
CPU time 0.78 seconds
Started Jun 27 06:39:11 PM PDT 24
Finished Jun 27 06:39:16 PM PDT 24
Peak memory 206252 kb
Host smart-a1b57dae-9066-485f-960a-914948faaaa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67408
9742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.674089742
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.2105761017
Short name T2427
Test name
Test status
Simulation time 213280604 ps
CPU time 0.8 seconds
Started Jun 27 06:39:10 PM PDT 24
Finished Jun 27 06:39:14 PM PDT 24
Peak memory 206280 kb
Host smart-685ea0b1-7223-4641-bb8a-8f671e3e9823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21057
61017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.2105761017
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.2499633520
Short name T1853
Test name
Test status
Simulation time 236063529 ps
CPU time 0.94 seconds
Started Jun 27 06:39:14 PM PDT 24
Finished Jun 27 06:39:25 PM PDT 24
Peak memory 206244 kb
Host smart-fa9c30fb-c23c-42e9-be87-931cc126c06a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2499633520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.2499633520
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.910637715
Short name T2542
Test name
Test status
Simulation time 204549516 ps
CPU time 0.81 seconds
Started Jun 27 06:39:14 PM PDT 24
Finished Jun 27 06:39:26 PM PDT 24
Peak memory 206284 kb
Host smart-7e269c0e-d23e-491c-9343-597e12dc4183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91063
7715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.910637715
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.1173029454
Short name T27
Test name
Test status
Simulation time 40716319 ps
CPU time 0.67 seconds
Started Jun 27 06:39:10 PM PDT 24
Finished Jun 27 06:39:15 PM PDT 24
Peak memory 206272 kb
Host smart-a7d6abc2-3d08-4841-ab3c-92562dc00bf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11730
29454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.1173029454
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.3547373373
Short name T755
Test name
Test status
Simulation time 21203355251 ps
CPU time 50.23 seconds
Started Jun 27 06:39:09 PM PDT 24
Finished Jun 27 06:40:01 PM PDT 24
Peak memory 206448 kb
Host smart-7f4ff42a-992b-453c-b503-df436980e04d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35473
73373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.3547373373
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.3886407733
Short name T589
Test name
Test status
Simulation time 196493231 ps
CPU time 0.84 seconds
Started Jun 27 06:39:12 PM PDT 24
Finished Jun 27 06:39:21 PM PDT 24
Peak memory 206248 kb
Host smart-b2154cde-e378-45b7-97f8-4096ebbca0ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38864
07733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.3886407733
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.2065825600
Short name T2334
Test name
Test status
Simulation time 191710442 ps
CPU time 0.89 seconds
Started Jun 27 06:39:12 PM PDT 24
Finished Jun 27 06:39:19 PM PDT 24
Peak memory 206304 kb
Host smart-60fa7895-cb36-4bfe-a50d-e5743867d1ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20658
25600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.2065825600
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.4256980326
Short name T1446
Test name
Test status
Simulation time 256130278 ps
CPU time 0.89 seconds
Started Jun 27 06:39:15 PM PDT 24
Finished Jun 27 06:39:28 PM PDT 24
Peak memory 206088 kb
Host smart-a3485ebe-77e6-4e44-833e-1b2c8f4bd818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42569
80326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.4256980326
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.1018719987
Short name T934
Test name
Test status
Simulation time 191516866 ps
CPU time 0.86 seconds
Started Jun 27 06:39:11 PM PDT 24
Finished Jun 27 06:39:16 PM PDT 24
Peak memory 206252 kb
Host smart-45a63b8d-748c-4ab5-a37b-764bf0cd733b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10187
19987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.1018719987
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.3776454777
Short name T593
Test name
Test status
Simulation time 145348043 ps
CPU time 0.74 seconds
Started Jun 27 06:39:13 PM PDT 24
Finished Jun 27 06:39:22 PM PDT 24
Peak memory 206272 kb
Host smart-34b94161-04cb-4070-9504-6bba85582614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37764
54777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.3776454777
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.3191359922
Short name T819
Test name
Test status
Simulation time 151811849 ps
CPU time 0.77 seconds
Started Jun 27 06:39:12 PM PDT 24
Finished Jun 27 06:39:20 PM PDT 24
Peak memory 206248 kb
Host smart-e60e9823-8e4b-4857-be95-47eda24a0b92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31913
59922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.3191359922
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.2081465053
Short name T360
Test name
Test status
Simulation time 179364751 ps
CPU time 0.86 seconds
Started Jun 27 06:39:15 PM PDT 24
Finished Jun 27 06:39:28 PM PDT 24
Peak memory 206296 kb
Host smart-0a0b0293-4211-4831-844e-b9c8f81c2028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20814
65053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.2081465053
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.970911287
Short name T2035
Test name
Test status
Simulation time 213810705 ps
CPU time 0.9 seconds
Started Jun 27 06:39:10 PM PDT 24
Finished Jun 27 06:39:15 PM PDT 24
Peak memory 206316 kb
Host smart-396c1b16-14a8-49ce-8fa6-54a37d3906ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97091
1287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.970911287
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.2714761296
Short name T1223
Test name
Test status
Simulation time 5775711097 ps
CPU time 160.95 seconds
Started Jun 27 06:39:13 PM PDT 24
Finished Jun 27 06:42:02 PM PDT 24
Peak memory 206472 kb
Host smart-041f24ed-ed54-406a-8200-13cd70045bbe
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2714761296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.2714761296
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.1106220119
Short name T621
Test name
Test status
Simulation time 228589454 ps
CPU time 0.83 seconds
Started Jun 27 06:39:09 PM PDT 24
Finished Jun 27 06:39:11 PM PDT 24
Peak memory 206272 kb
Host smart-87dd57d1-edd5-4465-a696-1396f07a815e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11062
20119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.1106220119
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.3011846900
Short name T1973
Test name
Test status
Simulation time 164410687 ps
CPU time 0.79 seconds
Started Jun 27 06:39:09 PM PDT 24
Finished Jun 27 06:39:12 PM PDT 24
Peak memory 206236 kb
Host smart-9da582dd-e880-4b7a-917a-0bcde0d99cf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30118
46900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.3011846900
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.1278645568
Short name T1005
Test name
Test status
Simulation time 6412989636 ps
CPU time 47.39 seconds
Started Jun 27 06:39:13 PM PDT 24
Finished Jun 27 06:40:10 PM PDT 24
Peak memory 206480 kb
Host smart-80f5ba59-af46-4a28-a469-40a5ce2b2052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12786
45568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.1278645568
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.4239967540
Short name T2257
Test name
Test status
Simulation time 40085158 ps
CPU time 0.65 seconds
Started Jun 27 06:39:15 PM PDT 24
Finished Jun 27 06:39:28 PM PDT 24
Peak memory 206364 kb
Host smart-cd94056a-1776-4f62-ac94-48ec3fb5f191
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4239967540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.4239967540
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.1183818546
Short name T1343
Test name
Test status
Simulation time 3657500860 ps
CPU time 4.4 seconds
Started Jun 27 06:39:11 PM PDT 24
Finished Jun 27 06:39:22 PM PDT 24
Peak memory 206496 kb
Host smart-cf5ed2c5-3af5-4cde-8863-747400943c72
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1183818546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.1183818546
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.2988321525
Short name T2400
Test name
Test status
Simulation time 23307693610 ps
CPU time 22.13 seconds
Started Jun 27 06:39:14 PM PDT 24
Finished Jun 27 06:39:46 PM PDT 24
Peak memory 206476 kb
Host smart-e88d69f6-f2f6-4683-badb-2d5c992cf2a6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2988321525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.2988321525
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.3852328574
Short name T328
Test name
Test status
Simulation time 165834590 ps
CPU time 0.82 seconds
Started Jun 27 06:39:10 PM PDT 24
Finished Jun 27 06:39:15 PM PDT 24
Peak memory 206276 kb
Host smart-c6caa684-3e55-4f24-9e73-cb2379d553e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38523
28574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.3852328574
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.305890110
Short name T63
Test name
Test status
Simulation time 173095918 ps
CPU time 0.79 seconds
Started Jun 27 06:39:11 PM PDT 24
Finished Jun 27 06:39:16 PM PDT 24
Peak memory 206252 kb
Host smart-ffacd084-8a99-49c8-b049-f2d1744d6a63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30589
0110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.305890110
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.2058285066
Short name T477
Test name
Test status
Simulation time 372159736 ps
CPU time 1.15 seconds
Started Jun 27 06:39:12 PM PDT 24
Finished Jun 27 06:39:19 PM PDT 24
Peak memory 206296 kb
Host smart-7c628018-ced9-4878-90f1-9581053b4a5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20582
85066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.2058285066
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.2113747823
Short name T2090
Test name
Test status
Simulation time 1501699355 ps
CPU time 3.19 seconds
Started Jun 27 06:39:14 PM PDT 24
Finished Jun 27 06:39:28 PM PDT 24
Peak memory 206348 kb
Host smart-d6315c0a-b851-4b30-bcb1-327135afe474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21137
47823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.2113747823
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.964958203
Short name T2532
Test name
Test status
Simulation time 10831477417 ps
CPU time 19.11 seconds
Started Jun 27 06:39:17 PM PDT 24
Finished Jun 27 06:39:48 PM PDT 24
Peak memory 206440 kb
Host smart-f2acdecc-92dc-4195-bced-ed0479ebe90c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96495
8203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.964958203
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.3225984445
Short name T1266
Test name
Test status
Simulation time 509610772 ps
CPU time 1.45 seconds
Started Jun 27 06:39:14 PM PDT 24
Finished Jun 27 06:39:27 PM PDT 24
Peak memory 206276 kb
Host smart-c9e6e5a2-9c26-45c5-8c10-8f9abac0de29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32259
84445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.3225984445
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.4077581120
Short name T1309
Test name
Test status
Simulation time 149295325 ps
CPU time 0.77 seconds
Started Jun 27 06:39:09 PM PDT 24
Finished Jun 27 06:39:12 PM PDT 24
Peak memory 206244 kb
Host smart-0a4c0755-fbc3-4714-ba73-11d24e12eb6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40775
81120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.4077581120
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.2187549869
Short name T529
Test name
Test status
Simulation time 38284012 ps
CPU time 0.63 seconds
Started Jun 27 06:39:15 PM PDT 24
Finished Jun 27 06:39:26 PM PDT 24
Peak memory 206288 kb
Host smart-c8d8d892-bcea-42f3-a359-cda2b92c4b8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21875
49869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.2187549869
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.3745610020
Short name T1212
Test name
Test status
Simulation time 764940241 ps
CPU time 1.97 seconds
Started Jun 27 06:39:10 PM PDT 24
Finished Jun 27 06:39:14 PM PDT 24
Peak memory 206444 kb
Host smart-0a1aa507-1e5d-474a-97d0-467ee9f4a41e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37456
10020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.3745610020
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.2620612510
Short name T1725
Test name
Test status
Simulation time 376367366 ps
CPU time 2.15 seconds
Started Jun 27 06:39:10 PM PDT 24
Finished Jun 27 06:39:14 PM PDT 24
Peak memory 206420 kb
Host smart-b47d09ab-1acc-4228-930a-109880d583ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26206
12510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.2620612510
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.1616897322
Short name T2074
Test name
Test status
Simulation time 232828243 ps
CPU time 0.98 seconds
Started Jun 27 06:39:11 PM PDT 24
Finished Jun 27 06:39:18 PM PDT 24
Peak memory 206284 kb
Host smart-67fcc2a5-350f-491a-8750-3667f00ebb3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16168
97322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.1616897322
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.1791712765
Short name T1639
Test name
Test status
Simulation time 165081973 ps
CPU time 0.79 seconds
Started Jun 27 06:39:12 PM PDT 24
Finished Jun 27 06:39:21 PM PDT 24
Peak memory 206272 kb
Host smart-7983ad36-b483-4269-901b-f8dc59565f4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17917
12765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.1791712765
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.2327782762
Short name T1110
Test name
Test status
Simulation time 148352764 ps
CPU time 0.85 seconds
Started Jun 27 06:39:11 PM PDT 24
Finished Jun 27 06:39:18 PM PDT 24
Peak memory 206436 kb
Host smart-76280b55-b106-4ddb-b2d0-228b41507392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23277
82762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.2327782762
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.278614955
Short name T1127
Test name
Test status
Simulation time 5669956431 ps
CPU time 152.55 seconds
Started Jun 27 06:39:11 PM PDT 24
Finished Jun 27 06:41:50 PM PDT 24
Peak memory 206632 kb
Host smart-ed14853d-075a-4771-8fcc-a3de1447412f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=278614955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.278614955
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.273948528
Short name T1248
Test name
Test status
Simulation time 184232167 ps
CPU time 0.84 seconds
Started Jun 27 06:39:14 PM PDT 24
Finished Jun 27 06:39:25 PM PDT 24
Peak memory 206276 kb
Host smart-938747fc-8893-4cbd-944e-c286e3640c9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27394
8528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.273948528
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.2240733364
Short name T2372
Test name
Test status
Simulation time 23401608210 ps
CPU time 28.23 seconds
Started Jun 27 06:39:10 PM PDT 24
Finished Jun 27 06:39:42 PM PDT 24
Peak memory 206336 kb
Host smart-1bbea2d2-c1a3-416d-92c8-31ad204c111d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22407
33364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.2240733364
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.1490334172
Short name T1983
Test name
Test status
Simulation time 3312538482 ps
CPU time 3.94 seconds
Started Jun 27 06:39:10 PM PDT 24
Finished Jun 27 06:39:17 PM PDT 24
Peak memory 206304 kb
Host smart-abb5956a-ef34-4e6e-8cc5-1f57cfe42237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14903
34172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.1490334172
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.4173684886
Short name T889
Test name
Test status
Simulation time 7918802381 ps
CPU time 52.57 seconds
Started Jun 27 06:39:13 PM PDT 24
Finished Jun 27 06:40:15 PM PDT 24
Peak memory 206436 kb
Host smart-cd020e1f-355c-4d06-85e9-94702ff5b91c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41736
84886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.4173684886
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.2792121722
Short name T1166
Test name
Test status
Simulation time 7577182641 ps
CPU time 52.27 seconds
Started Jun 27 06:39:12 PM PDT 24
Finished Jun 27 06:40:10 PM PDT 24
Peak memory 206572 kb
Host smart-1d324cde-f25f-433d-82b0-268d7fde4c1b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2792121722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.2792121722
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.2809829343
Short name T2564
Test name
Test status
Simulation time 258677092 ps
CPU time 0.93 seconds
Started Jun 27 06:39:14 PM PDT 24
Finished Jun 27 06:39:25 PM PDT 24
Peak memory 206292 kb
Host smart-f59a3bce-0528-4e18-9a8b-a8847b4bd85b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2809829343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.2809829343
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.1630778489
Short name T1128
Test name
Test status
Simulation time 190939717 ps
CPU time 0.9 seconds
Started Jun 27 06:39:12 PM PDT 24
Finished Jun 27 06:39:21 PM PDT 24
Peak memory 206272 kb
Host smart-816fec1a-380f-47b6-849b-b97033ca5ef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16307
78489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.1630778489
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.4271605572
Short name T1930
Test name
Test status
Simulation time 3674339465 ps
CPU time 96.24 seconds
Started Jun 27 06:39:16 PM PDT 24
Finished Jun 27 06:41:05 PM PDT 24
Peak memory 206436 kb
Host smart-fed6176c-efdb-40a1-9cc7-0e619cc2bb5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42716
05572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.4271605572
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.1871974593
Short name T698
Test name
Test status
Simulation time 6414089276 ps
CPU time 63.36 seconds
Started Jun 27 06:39:09 PM PDT 24
Finished Jun 27 06:40:15 PM PDT 24
Peak memory 206508 kb
Host smart-e572f843-d316-4edc-87c0-7fc05c574da7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1871974593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.1871974593
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.3631641816
Short name T465
Test name
Test status
Simulation time 160811807 ps
CPU time 0.77 seconds
Started Jun 27 06:39:14 PM PDT 24
Finished Jun 27 06:39:25 PM PDT 24
Peak memory 206296 kb
Host smart-e834a12c-3223-4868-9747-f7c3179fcb90
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3631641816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.3631641816
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.3949495522
Short name T506
Test name
Test status
Simulation time 197474522 ps
CPU time 0.79 seconds
Started Jun 27 06:39:15 PM PDT 24
Finished Jun 27 06:39:28 PM PDT 24
Peak memory 206116 kb
Host smart-d48edf09-0b78-4b27-8023-17a98ffbbf8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39494
95522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.3949495522
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.3628420047
Short name T2437
Test name
Test status
Simulation time 270002980 ps
CPU time 0.93 seconds
Started Jun 27 06:39:11 PM PDT 24
Finished Jun 27 06:39:16 PM PDT 24
Peak memory 206436 kb
Host smart-d668b22d-4a3b-4e75-94ae-da31fdceeef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36284
20047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.3628420047
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.2544574460
Short name T2235
Test name
Test status
Simulation time 256203646 ps
CPU time 0.9 seconds
Started Jun 27 06:39:16 PM PDT 24
Finished Jun 27 06:39:30 PM PDT 24
Peak memory 206296 kb
Host smart-07056e5a-47d6-4e2d-a5d6-10b9d76d905b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25445
74460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.2544574460
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.2028505438
Short name T903
Test name
Test status
Simulation time 150862805 ps
CPU time 0.76 seconds
Started Jun 27 06:39:14 PM PDT 24
Finished Jun 27 06:39:25 PM PDT 24
Peak memory 206272 kb
Host smart-2f3eaea8-628a-4238-91ed-ea2446aaf63e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20285
05438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.2028505438
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.2916938483
Short name T17
Test name
Test status
Simulation time 153948762 ps
CPU time 0.77 seconds
Started Jun 27 06:39:13 PM PDT 24
Finished Jun 27 06:39:22 PM PDT 24
Peak memory 206272 kb
Host smart-7254ecdd-9ec8-460b-8229-a851aed0f9ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29169
38483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.2916938483
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.4046242751
Short name T2442
Test name
Test status
Simulation time 155885850 ps
CPU time 0.77 seconds
Started Jun 27 06:39:17 PM PDT 24
Finished Jun 27 06:39:31 PM PDT 24
Peak memory 206256 kb
Host smart-4163d1eb-a938-4281-8fbf-62ef5b86dbbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40462
42751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.4046242751
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.3003707633
Short name T491
Test name
Test status
Simulation time 205030926 ps
CPU time 0.93 seconds
Started Jun 27 06:39:15 PM PDT 24
Finished Jun 27 06:39:28 PM PDT 24
Peak memory 206300 kb
Host smart-5b71a7ee-06f8-413c-a7bc-733d1ea07b7a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3003707633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.3003707633
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.1565116020
Short name T1557
Test name
Test status
Simulation time 172059341 ps
CPU time 0.81 seconds
Started Jun 27 06:39:16 PM PDT 24
Finished Jun 27 06:39:29 PM PDT 24
Peak memory 206276 kb
Host smart-f25cc8e0-73c7-49b0-9ebf-9d07ec20206d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15651
16020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.1565116020
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.441409840
Short name T2159
Test name
Test status
Simulation time 41377835 ps
CPU time 0.66 seconds
Started Jun 27 06:39:17 PM PDT 24
Finished Jun 27 06:39:31 PM PDT 24
Peak memory 206248 kb
Host smart-ad0b1218-ecdc-4155-8016-c78f33139a6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44140
9840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.441409840
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.2694139433
Short name T257
Test name
Test status
Simulation time 11392383710 ps
CPU time 22.91 seconds
Started Jun 27 06:39:16 PM PDT 24
Finished Jun 27 06:39:52 PM PDT 24
Peak memory 206424 kb
Host smart-acd9435a-90dc-4ca7-b2b0-6644327bfd4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26941
39433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.2694139433
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.3498076532
Short name T1177
Test name
Test status
Simulation time 195627759 ps
CPU time 0.86 seconds
Started Jun 27 06:39:16 PM PDT 24
Finished Jun 27 06:39:29 PM PDT 24
Peak memory 206252 kb
Host smart-65f8a5fa-7d7b-4268-b8f7-68481e7ba05d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34980
76532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.3498076532
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.3003079227
Short name T1715
Test name
Test status
Simulation time 204944494 ps
CPU time 0.84 seconds
Started Jun 27 06:39:16 PM PDT 24
Finished Jun 27 06:39:30 PM PDT 24
Peak memory 206284 kb
Host smart-fd356459-a8b6-4bc9-96e1-e808df2c3f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30030
79227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.3003079227
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.194487432
Short name T607
Test name
Test status
Simulation time 189521600 ps
CPU time 0.81 seconds
Started Jun 27 06:39:14 PM PDT 24
Finished Jun 27 06:39:25 PM PDT 24
Peak memory 206300 kb
Host smart-c5bc1750-289b-4d1c-aa32-c8dc5f810fbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19448
7432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.194487432
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.2119475446
Short name T720
Test name
Test status
Simulation time 186987923 ps
CPU time 0.8 seconds
Started Jun 27 06:39:14 PM PDT 24
Finished Jun 27 06:39:25 PM PDT 24
Peak memory 206224 kb
Host smart-67825b7c-5cc7-4653-817f-c4f5a282228c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21194
75446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.2119475446
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.3245003083
Short name T1923
Test name
Test status
Simulation time 134742168 ps
CPU time 0.78 seconds
Started Jun 27 06:39:15 PM PDT 24
Finished Jun 27 06:39:26 PM PDT 24
Peak memory 206256 kb
Host smart-3821dc4f-f55f-491c-9dd8-03bcc700ca84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32450
03083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.3245003083
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.747080207
Short name T2423
Test name
Test status
Simulation time 162438879 ps
CPU time 0.78 seconds
Started Jun 27 06:39:19 PM PDT 24
Finished Jun 27 06:39:33 PM PDT 24
Peak memory 206260 kb
Host smart-9c90ee93-cc64-45b7-a638-83740619ed8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74708
0207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.747080207
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.95964626
Short name T98
Test name
Test status
Simulation time 151882882 ps
CPU time 0.72 seconds
Started Jun 27 06:39:15 PM PDT 24
Finished Jun 27 06:39:27 PM PDT 24
Peak memory 206284 kb
Host smart-aab5ceb2-351b-40c6-b601-d806aa5c9a7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95964
626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.95964626
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.2034187549
Short name T2185
Test name
Test status
Simulation time 282894995 ps
CPU time 1 seconds
Started Jun 27 06:39:19 PM PDT 24
Finished Jun 27 06:39:33 PM PDT 24
Peak memory 206276 kb
Host smart-32aca2bd-347b-4bac-a44f-3f9202c56811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20341
87549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.2034187549
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.518060175
Short name T1254
Test name
Test status
Simulation time 4002306788 ps
CPU time 104.56 seconds
Started Jun 27 06:39:17 PM PDT 24
Finished Jun 27 06:41:15 PM PDT 24
Peak memory 206472 kb
Host smart-adb0384c-0762-4a58-8e1e-4fdb03f768fb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=518060175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.518060175
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.2552424288
Short name T1246
Test name
Test status
Simulation time 147221168 ps
CPU time 0.75 seconds
Started Jun 27 06:39:16 PM PDT 24
Finished Jun 27 06:39:29 PM PDT 24
Peak memory 206288 kb
Host smart-d3f2df0c-ae1b-4fe2-bb2a-a9a8057856be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25524
24288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.2552424288
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.720146296
Short name T520
Test name
Test status
Simulation time 156150502 ps
CPU time 0.77 seconds
Started Jun 27 06:39:19 PM PDT 24
Finished Jun 27 06:39:33 PM PDT 24
Peak memory 206272 kb
Host smart-35ae6c70-3a20-4011-a6df-ad776d467849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72014
6296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.720146296
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.2328264365
Short name T1369
Test name
Test status
Simulation time 3692182298 ps
CPU time 99.31 seconds
Started Jun 27 06:39:16 PM PDT 24
Finished Jun 27 06:41:08 PM PDT 24
Peak memory 206428 kb
Host smart-1d8200c2-a04c-46db-8553-c0c67c7ff83a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23282
64365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.2328264365
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.1526380113
Short name T2219
Test name
Test status
Simulation time 51533966 ps
CPU time 0.67 seconds
Started Jun 27 06:39:20 PM PDT 24
Finished Jun 27 06:39:35 PM PDT 24
Peak memory 206352 kb
Host smart-637c3b06-886b-45ab-91e5-ed918bbe3efe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1526380113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.1526380113
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.1737531598
Short name T2590
Test name
Test status
Simulation time 4322527591 ps
CPU time 5.01 seconds
Started Jun 27 06:39:16 PM PDT 24
Finished Jun 27 06:39:33 PM PDT 24
Peak memory 206512 kb
Host smart-5f81cefa-3c6e-4c68-b892-6e769d2b4c12
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1737531598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.1737531598
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.2777088706
Short name T2573
Test name
Test status
Simulation time 13470505623 ps
CPU time 12.77 seconds
Started Jun 27 06:39:12 PM PDT 24
Finished Jun 27 06:39:33 PM PDT 24
Peak memory 206464 kb
Host smart-f24a0e5c-be2e-4b76-8ff0-ef5db526f9b7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2777088706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.2777088706
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.92068162
Short name T834
Test name
Test status
Simulation time 23397157189 ps
CPU time 22.51 seconds
Started Jun 27 06:39:21 PM PDT 24
Finished Jun 27 06:39:57 PM PDT 24
Peak memory 206332 kb
Host smart-7312caf9-e80e-447f-bb52-f8dc72b35588
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=92068162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.92068162
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.3289142864
Short name T1016
Test name
Test status
Simulation time 183394122 ps
CPU time 0.82 seconds
Started Jun 27 06:39:14 PM PDT 24
Finished Jun 27 06:39:25 PM PDT 24
Peak memory 206164 kb
Host smart-31e13bda-ed24-4861-8b71-286c77a694b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32891
42864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.3289142864
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.1739370845
Short name T2001
Test name
Test status
Simulation time 147486684 ps
CPU time 0.74 seconds
Started Jun 27 06:39:15 PM PDT 24
Finished Jun 27 06:39:28 PM PDT 24
Peak memory 206280 kb
Host smart-f8a73217-c5ab-4b5b-858c-119fcff8421a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17393
70845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.1739370845
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.3085240192
Short name T1029
Test name
Test status
Simulation time 346786191 ps
CPU time 1.13 seconds
Started Jun 27 06:39:20 PM PDT 24
Finished Jun 27 06:39:35 PM PDT 24
Peak memory 206268 kb
Host smart-7d4a9639-d471-48f3-8725-0cdbe532eae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30852
40192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.3085240192
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.4209052537
Short name T104
Test name
Test status
Simulation time 1480234592 ps
CPU time 3.01 seconds
Started Jun 27 06:39:16 PM PDT 24
Finished Jun 27 06:39:32 PM PDT 24
Peak memory 206440 kb
Host smart-ba768210-ea5a-4ee6-8c8d-deac40a299a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42090
52537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.4209052537
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.4291696864
Short name T615
Test name
Test status
Simulation time 6596587623 ps
CPU time 11.76 seconds
Started Jun 27 06:39:21 PM PDT 24
Finished Jun 27 06:39:47 PM PDT 24
Peak memory 206464 kb
Host smart-0d4cc8e4-a982-48c4-b0ef-836c07565923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42916
96864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.4291696864
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.3395247486
Short name T1794
Test name
Test status
Simulation time 364885352 ps
CPU time 1.12 seconds
Started Jun 27 06:39:15 PM PDT 24
Finished Jun 27 06:39:28 PM PDT 24
Peak memory 206276 kb
Host smart-0c366dfb-6072-43c5-bb53-f2eaed794c7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33952
47486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.3395247486
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.4121881347
Short name T1241
Test name
Test status
Simulation time 146469416 ps
CPU time 0.78 seconds
Started Jun 27 06:39:15 PM PDT 24
Finished Jun 27 06:39:29 PM PDT 24
Peak memory 206268 kb
Host smart-07777e05-6858-4088-8729-34206daac6a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41218
81347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.4121881347
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.3234854396
Short name T2107
Test name
Test status
Simulation time 44926031 ps
CPU time 0.62 seconds
Started Jun 27 06:39:20 PM PDT 24
Finished Jun 27 06:39:34 PM PDT 24
Peak memory 206280 kb
Host smart-cdef5a88-ae6b-4fb4-9063-639b88976fa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32348
54396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.3234854396
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.2940716262
Short name T2052
Test name
Test status
Simulation time 861623540 ps
CPU time 1.96 seconds
Started Jun 27 06:39:17 PM PDT 24
Finished Jun 27 06:39:32 PM PDT 24
Peak memory 206424 kb
Host smart-c2fb7ced-2f0f-48e9-b8a2-344d80629585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29407
16262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.2940716262
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.887537758
Short name T1550
Test name
Test status
Simulation time 235673546 ps
CPU time 1.32 seconds
Started Jun 27 06:39:17 PM PDT 24
Finished Jun 27 06:39:32 PM PDT 24
Peak memory 206340 kb
Host smart-0e33cfe7-c0e1-4c45-b3cd-e89ff234d4e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88753
7758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.887537758
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.2576420780
Short name T1251
Test name
Test status
Simulation time 200071394 ps
CPU time 0.81 seconds
Started Jun 27 06:39:19 PM PDT 24
Finished Jun 27 06:39:33 PM PDT 24
Peak memory 206288 kb
Host smart-f5fd463c-39d8-481b-a6bf-0b848274e9a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25764
20780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.2576420780
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.219775373
Short name T1851
Test name
Test status
Simulation time 196461380 ps
CPU time 0.78 seconds
Started Jun 27 06:39:18 PM PDT 24
Finished Jun 27 06:39:31 PM PDT 24
Peak memory 206268 kb
Host smart-6ed61188-a8c2-4835-914c-a4cf4e7d1b50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21977
5373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.219775373
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.170681641
Short name T921
Test name
Test status
Simulation time 169247187 ps
CPU time 0.81 seconds
Started Jun 27 06:39:11 PM PDT 24
Finished Jun 27 06:39:18 PM PDT 24
Peak memory 206452 kb
Host smart-abf96612-f92a-4bb3-a102-dcef94074074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17068
1641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.170681641
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_invalid_sync.1211632255
Short name T2006
Test name
Test status
Simulation time 6017545811 ps
CPU time 54.23 seconds
Started Jun 27 06:39:18 PM PDT 24
Finished Jun 27 06:40:26 PM PDT 24
Peak memory 206412 kb
Host smart-8ef05111-411b-437c-81a4-533eece580e9
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1211632255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.1211632255
Directory /workspace/28.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.2027423356
Short name T1179
Test name
Test status
Simulation time 202087640 ps
CPU time 0.81 seconds
Started Jun 27 06:39:18 PM PDT 24
Finished Jun 27 06:39:32 PM PDT 24
Peak memory 206268 kb
Host smart-3f300f3a-84e9-452b-aca8-67edbaa6ee2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20274
23356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.2027423356
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.70403406
Short name T1086
Test name
Test status
Simulation time 23340381694 ps
CPU time 24.22 seconds
Started Jun 27 06:39:22 PM PDT 24
Finished Jun 27 06:39:59 PM PDT 24
Peak memory 206332 kb
Host smart-5cced91d-a5a1-4a03-8bff-2a4b06c79872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70403
406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.70403406
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.1931951927
Short name T597
Test name
Test status
Simulation time 3358264729 ps
CPU time 3.55 seconds
Started Jun 27 06:39:17 PM PDT 24
Finished Jun 27 06:39:34 PM PDT 24
Peak memory 206332 kb
Host smart-d0959618-b110-426a-aab5-7ca0819a249a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19319
51927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.1931951927
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.839689867
Short name T1001
Test name
Test status
Simulation time 6737519698 ps
CPU time 187.44 seconds
Started Jun 27 06:39:23 PM PDT 24
Finished Jun 27 06:42:44 PM PDT 24
Peak memory 206520 kb
Host smart-9c37757e-4482-4a8c-b0d2-b72d1ac9beca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83968
9867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.839689867
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.3481960565
Short name T1066
Test name
Test status
Simulation time 4319968645 ps
CPU time 118.52 seconds
Started Jun 27 06:39:19 PM PDT 24
Finished Jun 27 06:41:31 PM PDT 24
Peak memory 206436 kb
Host smart-3341a028-bab4-46ab-9b7b-9cfa1b225203
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3481960565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.3481960565
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.574159392
Short name T725
Test name
Test status
Simulation time 292631351 ps
CPU time 0.96 seconds
Started Jun 27 06:39:17 PM PDT 24
Finished Jun 27 06:39:31 PM PDT 24
Peak memory 206260 kb
Host smart-119835b0-9f28-4880-844a-15561a657733
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=574159392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.574159392
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.2649049802
Short name T2073
Test name
Test status
Simulation time 239300700 ps
CPU time 0.88 seconds
Started Jun 27 06:39:22 PM PDT 24
Finished Jun 27 06:39:37 PM PDT 24
Peak memory 206276 kb
Host smart-10f62fc6-7428-4491-b223-8f7e6652351d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26490
49802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.2649049802
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.3799016420
Short name T2029
Test name
Test status
Simulation time 2948340800 ps
CPU time 25.12 seconds
Started Jun 27 06:39:22 PM PDT 24
Finished Jun 27 06:40:01 PM PDT 24
Peak memory 206424 kb
Host smart-af296dea-8ffd-4d57-a71b-1be4c5ced1bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37990
16420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.3799016420
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.3525083142
Short name T1173
Test name
Test status
Simulation time 7860691071 ps
CPU time 216.26 seconds
Started Jun 27 06:39:17 PM PDT 24
Finished Jun 27 06:43:07 PM PDT 24
Peak memory 206412 kb
Host smart-feecbf85-6439-4cbd-9929-6563e4bdf716
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3525083142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.3525083142
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.2946365623
Short name T1719
Test name
Test status
Simulation time 186283259 ps
CPU time 0.76 seconds
Started Jun 27 06:39:22 PM PDT 24
Finished Jun 27 06:39:37 PM PDT 24
Peak memory 206292 kb
Host smart-7c8a07d3-6865-428e-80f9-75970553017f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2946365623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.2946365623
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.698817337
Short name T1705
Test name
Test status
Simulation time 152130807 ps
CPU time 0.78 seconds
Started Jun 27 06:39:14 PM PDT 24
Finished Jun 27 06:39:25 PM PDT 24
Peak memory 206288 kb
Host smart-8a6ae17d-a67e-4692-b274-f80882e5f8ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69881
7337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.698817337
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.2092464097
Short name T112
Test name
Test status
Simulation time 217330468 ps
CPU time 0.87 seconds
Started Jun 27 06:39:12 PM PDT 24
Finished Jun 27 06:39:22 PM PDT 24
Peak memory 206260 kb
Host smart-23b89f04-b005-4ea1-ae76-4c314e6b54cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20924
64097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.2092464097
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.2716073907
Short name T2180
Test name
Test status
Simulation time 151666884 ps
CPU time 0.83 seconds
Started Jun 27 06:39:12 PM PDT 24
Finished Jun 27 06:39:22 PM PDT 24
Peak memory 206272 kb
Host smart-a87a7f5e-8144-4129-95fa-da718b7cb0bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27160
73907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.2716073907
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.927011802
Short name T469
Test name
Test status
Simulation time 173350687 ps
CPU time 0.87 seconds
Started Jun 27 06:39:15 PM PDT 24
Finished Jun 27 06:39:29 PM PDT 24
Peak memory 206248 kb
Host smart-31f905b8-17ad-41fc-973e-9b94e26df923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92701
1802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.927011802
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.2562729216
Short name T1782
Test name
Test status
Simulation time 169576229 ps
CPU time 0.77 seconds
Started Jun 27 06:39:15 PM PDT 24
Finished Jun 27 06:39:28 PM PDT 24
Peak memory 206284 kb
Host smart-ebc6f3cd-bde9-4d22-a77b-4fe3fc1988e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25627
29216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.2562729216
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.1939367848
Short name T1626
Test name
Test status
Simulation time 167098650 ps
CPU time 0.75 seconds
Started Jun 27 06:39:17 PM PDT 24
Finished Jun 27 06:39:31 PM PDT 24
Peak memory 206256 kb
Host smart-b7cac28f-20a3-4a15-b317-901263e779c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19393
67848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.1939367848
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.1340829979
Short name T888
Test name
Test status
Simulation time 233634057 ps
CPU time 0.9 seconds
Started Jun 27 06:39:16 PM PDT 24
Finished Jun 27 06:39:30 PM PDT 24
Peak memory 206300 kb
Host smart-e99b05dd-58a1-4d36-bf1d-ef4c18770953
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1340829979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.1340829979
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.3997950247
Short name T1861
Test name
Test status
Simulation time 164081230 ps
CPU time 0.74 seconds
Started Jun 27 06:39:17 PM PDT 24
Finished Jun 27 06:39:30 PM PDT 24
Peak memory 206276 kb
Host smart-f76e3e1d-6972-4262-b035-3f6ce9f249e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39979
50247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.3997950247
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.3626876324
Short name T1038
Test name
Test status
Simulation time 42911095 ps
CPU time 0.65 seconds
Started Jun 27 06:39:18 PM PDT 24
Finished Jun 27 06:39:32 PM PDT 24
Peak memory 206256 kb
Host smart-f697ce64-8c56-48b4-af30-6dc200d06b27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36268
76324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.3626876324
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.1045066462
Short name T259
Test name
Test status
Simulation time 5811752735 ps
CPU time 12.69 seconds
Started Jun 27 06:39:14 PM PDT 24
Finished Jun 27 06:39:37 PM PDT 24
Peak memory 206436 kb
Host smart-b8cf404a-55d6-431f-be66-a354bfb8e1e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10450
66462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.1045066462
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.4047081051
Short name T709
Test name
Test status
Simulation time 161042981 ps
CPU time 0.76 seconds
Started Jun 27 06:39:11 PM PDT 24
Finished Jun 27 06:39:15 PM PDT 24
Peak memory 206272 kb
Host smart-2cd14d17-63d9-4908-af44-de76176b2cdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40470
81051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.4047081051
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.999369425
Short name T2027
Test name
Test status
Simulation time 217644370 ps
CPU time 0.86 seconds
Started Jun 27 06:39:15 PM PDT 24
Finished Jun 27 06:39:28 PM PDT 24
Peak memory 206268 kb
Host smart-ac2130c7-8ce6-4f3f-ace0-940edbe70ee2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99936
9425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.999369425
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.1569453179
Short name T1918
Test name
Test status
Simulation time 204718956 ps
CPU time 0.87 seconds
Started Jun 27 06:39:16 PM PDT 24
Finished Jun 27 06:39:30 PM PDT 24
Peak memory 206300 kb
Host smart-f1f0087c-121b-4a89-9f07-6c6cecb1a7d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15694
53179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.1569453179
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.3075761538
Short name T319
Test name
Test status
Simulation time 170910083 ps
CPU time 0.83 seconds
Started Jun 27 06:39:15 PM PDT 24
Finished Jun 27 06:39:28 PM PDT 24
Peak memory 206256 kb
Host smart-151a0cee-b4d4-459b-acaa-8bde3972f48e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30757
61538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.3075761538
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.4031220456
Short name T1387
Test name
Test status
Simulation time 188640362 ps
CPU time 0.74 seconds
Started Jun 27 06:39:16 PM PDT 24
Finished Jun 27 06:39:29 PM PDT 24
Peak memory 206268 kb
Host smart-b633e925-87ed-4cae-bcbb-ede2e6da5e5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40312
20456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.4031220456
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.757461382
Short name T552
Test name
Test status
Simulation time 149224915 ps
CPU time 0.71 seconds
Started Jun 27 06:39:15 PM PDT 24
Finished Jun 27 06:39:28 PM PDT 24
Peak memory 206268 kb
Host smart-12a77f8f-2ab9-4282-a18a-79c495438f3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75746
1382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.757461382
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.3398944049
Short name T1430
Test name
Test status
Simulation time 161801948 ps
CPU time 0.74 seconds
Started Jun 27 06:39:16 PM PDT 24
Finished Jun 27 06:39:30 PM PDT 24
Peak memory 206292 kb
Host smart-7cc2f6bf-4833-44f9-bcd5-eecfd36b45e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33989
44049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.3398944049
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.719122317
Short name T2121
Test name
Test status
Simulation time 259591135 ps
CPU time 0.87 seconds
Started Jun 27 06:39:14 PM PDT 24
Finished Jun 27 06:39:26 PM PDT 24
Peak memory 206284 kb
Host smart-86c5c4ed-71f9-4247-aa01-8b5d359ae05d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71912
2317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.719122317
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.1893000057
Short name T1970
Test name
Test status
Simulation time 5839545428 ps
CPU time 51.94 seconds
Started Jun 27 06:39:17 PM PDT 24
Finished Jun 27 06:40:22 PM PDT 24
Peak memory 206504 kb
Host smart-3932c34f-c655-4496-9979-c90c7a5fba2a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1893000057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.1893000057
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.2516455336
Short name T2024
Test name
Test status
Simulation time 172584839 ps
CPU time 0.81 seconds
Started Jun 27 06:39:19 PM PDT 24
Finished Jun 27 06:39:33 PM PDT 24
Peak memory 206276 kb
Host smart-d8db38de-1211-4a61-8db6-34e9f121cf6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25164
55336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.2516455336
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.688998371
Short name T513
Test name
Test status
Simulation time 158802033 ps
CPU time 0.75 seconds
Started Jun 27 06:39:09 PM PDT 24
Finished Jun 27 06:39:12 PM PDT 24
Peak memory 206272 kb
Host smart-f2f7579b-72a5-43f1-875b-4fc65aaecb92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68899
8371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.688998371
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.2294242309
Short name T2119
Test name
Test status
Simulation time 6973291527 ps
CPU time 49.93 seconds
Started Jun 27 06:39:16 PM PDT 24
Finished Jun 27 06:40:18 PM PDT 24
Peak memory 206492 kb
Host smart-2e8f967f-a774-441a-9f27-e9675d755709
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22942
42309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.2294242309
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.1748140774
Short name T349
Test name
Test status
Simulation time 35611927 ps
CPU time 0.71 seconds
Started Jun 27 06:39:30 PM PDT 24
Finished Jun 27 06:39:42 PM PDT 24
Peak memory 206348 kb
Host smart-b71a54b1-9690-4ea4-810e-4e18d2986e8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1748140774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.1748140774
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.2993173564
Short name T1364
Test name
Test status
Simulation time 4182999700 ps
CPU time 4.72 seconds
Started Jun 27 06:39:21 PM PDT 24
Finished Jun 27 06:39:40 PM PDT 24
Peak memory 206484 kb
Host smart-3d1c7db0-a26a-4e19-96db-53d9ad7cc860
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2993173564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.2993173564
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.600858286
Short name T2409
Test name
Test status
Simulation time 13400983143 ps
CPU time 13.52 seconds
Started Jun 27 06:39:15 PM PDT 24
Finished Jun 27 06:39:40 PM PDT 24
Peak memory 206348 kb
Host smart-cb387e1f-0e6d-403d-babc-d1f1747cbca3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=600858286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.600858286
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.205879763
Short name T2503
Test name
Test status
Simulation time 23410322004 ps
CPU time 21.13 seconds
Started Jun 27 06:39:15 PM PDT 24
Finished Jun 27 06:39:49 PM PDT 24
Peak memory 206416 kb
Host smart-32bf11a6-305e-4857-8bc4-5a27a53762fc
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=205879763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.205879763
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.702357975
Short name T1720
Test name
Test status
Simulation time 150523740 ps
CPU time 0.76 seconds
Started Jun 27 06:39:20 PM PDT 24
Finished Jun 27 06:39:35 PM PDT 24
Peak memory 206268 kb
Host smart-d91a4f9d-ef75-45e2-af95-8bff5f240af1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70235
7975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.702357975
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.1789799499
Short name T439
Test name
Test status
Simulation time 150923116 ps
CPU time 0.77 seconds
Started Jun 27 06:39:15 PM PDT 24
Finished Jun 27 06:39:27 PM PDT 24
Peak memory 206272 kb
Host smart-764d0b57-6f31-4654-ad16-20cff9e0bf0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17897
99499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.1789799499
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.280569286
Short name T1373
Test name
Test status
Simulation time 414225965 ps
CPU time 1.42 seconds
Started Jun 27 06:39:18 PM PDT 24
Finished Jun 27 06:39:33 PM PDT 24
Peak memory 206260 kb
Host smart-57b6766c-c7a2-4e2f-99e2-b7927e38e9ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28056
9286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.280569286
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.616180772
Short name T1657
Test name
Test status
Simulation time 1204954295 ps
CPU time 2.49 seconds
Started Jun 27 06:39:20 PM PDT 24
Finished Jun 27 06:39:36 PM PDT 24
Peak memory 206360 kb
Host smart-97e422f3-1f96-4b93-9712-c639a716465b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61618
0772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.616180772
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.2891485558
Short name T434
Test name
Test status
Simulation time 7342935188 ps
CPU time 15.3 seconds
Started Jun 27 06:39:11 PM PDT 24
Finished Jun 27 06:39:33 PM PDT 24
Peak memory 206404 kb
Host smart-37dbad0b-f68e-446e-bf04-c81eac81463e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28914
85558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.2891485558
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.226093728
Short name T2232
Test name
Test status
Simulation time 354484622 ps
CPU time 1.12 seconds
Started Jun 27 06:39:19 PM PDT 24
Finished Jun 27 06:39:33 PM PDT 24
Peak memory 206296 kb
Host smart-25a0413e-330a-4d53-9861-ed5ce6e2298d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22609
3728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.226093728
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.551981005
Short name T836
Test name
Test status
Simulation time 151123445 ps
CPU time 0.74 seconds
Started Jun 27 06:39:17 PM PDT 24
Finished Jun 27 06:39:31 PM PDT 24
Peak memory 206260 kb
Host smart-3f0e89b9-5857-4f95-9344-6fed75148c09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55198
1005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.551981005
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.3638113948
Short name T2383
Test name
Test status
Simulation time 53181542 ps
CPU time 0.71 seconds
Started Jun 27 06:39:11 PM PDT 24
Finished Jun 27 06:39:16 PM PDT 24
Peak memory 206284 kb
Host smart-fa69e277-2408-4c1e-9fb4-4785af3f86d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36381
13948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.3638113948
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.1952139790
Short name T827
Test name
Test status
Simulation time 921869873 ps
CPU time 2.05 seconds
Started Jun 27 06:39:20 PM PDT 24
Finished Jun 27 06:39:36 PM PDT 24
Peak memory 206380 kb
Host smart-8b192b54-dd96-4ac1-8cc5-551f09976f43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19521
39790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.1952139790
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.4168144086
Short name T2049
Test name
Test status
Simulation time 363389433 ps
CPU time 2.17 seconds
Started Jun 27 06:39:17 PM PDT 24
Finished Jun 27 06:39:32 PM PDT 24
Peak memory 206420 kb
Host smart-1f3ea769-e721-47ae-9526-8fdbd1d5ad50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41681
44086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.4168144086
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.816496211
Short name T19
Test name
Test status
Simulation time 178935269 ps
CPU time 0.8 seconds
Started Jun 27 06:39:19 PM PDT 24
Finished Jun 27 06:39:34 PM PDT 24
Peak memory 206288 kb
Host smart-cdd88081-1db3-427d-8ce6-152b76e9cd50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81649
6211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.816496211
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.1744928549
Short name T1112
Test name
Test status
Simulation time 213344237 ps
CPU time 0.77 seconds
Started Jun 27 06:39:18 PM PDT 24
Finished Jun 27 06:39:32 PM PDT 24
Peak memory 206288 kb
Host smart-95fdb687-09b6-463e-8285-7ccfb9d8a630
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17449
28549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.1744928549
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.4209736814
Short name T929
Test name
Test status
Simulation time 202837916 ps
CPU time 0.82 seconds
Started Jun 27 06:39:20 PM PDT 24
Finished Jun 27 06:39:34 PM PDT 24
Peak memory 206288 kb
Host smart-f98e928c-78e5-4a16-9b85-072e9c5edea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42097
36814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.4209736814
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.234619640
Short name T781
Test name
Test status
Simulation time 244033402 ps
CPU time 0.92 seconds
Started Jun 27 06:39:17 PM PDT 24
Finished Jun 27 06:39:31 PM PDT 24
Peak memory 206272 kb
Host smart-c2135e43-820f-41e7-ba56-5c675e8a23c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23461
9640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.234619640
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.1150463062
Short name T1642
Test name
Test status
Simulation time 23280075912 ps
CPU time 21.13 seconds
Started Jun 27 06:39:22 PM PDT 24
Finished Jun 27 06:39:57 PM PDT 24
Peak memory 206336 kb
Host smart-5ec01841-4b4a-44c6-b416-36d3a9ea054b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11504
63062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.1150463062
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.4293226445
Short name T966
Test name
Test status
Simulation time 3339963227 ps
CPU time 3.46 seconds
Started Jun 27 06:39:20 PM PDT 24
Finished Jun 27 06:39:37 PM PDT 24
Peak memory 206336 kb
Host smart-0be3563d-d56a-497b-8046-201ad6823852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42932
26445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.4293226445
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.2321609914
Short name T1224
Test name
Test status
Simulation time 9066943885 ps
CPU time 78.5 seconds
Started Jun 27 06:39:20 PM PDT 24
Finished Jun 27 06:40:52 PM PDT 24
Peak memory 206484 kb
Host smart-91564a71-2a8d-42ac-8602-73ad89f222e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23216
09914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.2321609914
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.4159539177
Short name T1065
Test name
Test status
Simulation time 3724685947 ps
CPU time 31.83 seconds
Started Jun 27 06:39:19 PM PDT 24
Finished Jun 27 06:40:04 PM PDT 24
Peak memory 206432 kb
Host smart-e111317b-8b04-4b20-9d36-5d82189f3ddf
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4159539177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.4159539177
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.1398168362
Short name T899
Test name
Test status
Simulation time 241393402 ps
CPU time 0.89 seconds
Started Jun 27 06:39:23 PM PDT 24
Finished Jun 27 06:39:37 PM PDT 24
Peak memory 206276 kb
Host smart-5a59959f-eddf-48a3-a4a3-bed4311e6dce
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1398168362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.1398168362
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.1110627087
Short name T1897
Test name
Test status
Simulation time 212833368 ps
CPU time 0.88 seconds
Started Jun 27 06:39:22 PM PDT 24
Finished Jun 27 06:39:36 PM PDT 24
Peak memory 206276 kb
Host smart-f20d3768-b824-4af6-a205-c5c5ed34a995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11106
27087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.1110627087
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.726124009
Short name T1529
Test name
Test status
Simulation time 5879809564 ps
CPU time 159.92 seconds
Started Jun 27 06:39:15 PM PDT 24
Finished Jun 27 06:42:08 PM PDT 24
Peak memory 206400 kb
Host smart-f0f9156d-cf9b-4fe5-834b-d389aaf82fc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72612
4009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.726124009
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.2702104169
Short name T2541
Test name
Test status
Simulation time 4475641405 ps
CPU time 123.02 seconds
Started Jun 27 06:39:15 PM PDT 24
Finished Jun 27 06:41:28 PM PDT 24
Peak memory 206400 kb
Host smart-f65b9e7d-3ce4-45d5-9d6d-f12c997b1995
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2702104169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.2702104169
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.3164368856
Short name T1234
Test name
Test status
Simulation time 156427995 ps
CPU time 0.82 seconds
Started Jun 27 06:39:14 PM PDT 24
Finished Jun 27 06:39:25 PM PDT 24
Peak memory 206300 kb
Host smart-55515b35-64b4-4866-ad0a-e3e1f4acaba4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3164368856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.3164368856
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.3492744006
Short name T1494
Test name
Test status
Simulation time 148269465 ps
CPU time 0.78 seconds
Started Jun 27 06:39:15 PM PDT 24
Finished Jun 27 06:39:26 PM PDT 24
Peak memory 206276 kb
Host smart-8a354cf5-7853-40ec-8b3f-37593eef45b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34927
44006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.3492744006
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.1531612391
Short name T132
Test name
Test status
Simulation time 186232786 ps
CPU time 0.89 seconds
Started Jun 27 06:39:13 PM PDT 24
Finished Jun 27 06:39:25 PM PDT 24
Peak memory 206284 kb
Host smart-dcf78039-2f00-4235-b9a6-355928923445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15316
12391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.1531612391
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.1054978383
Short name T518
Test name
Test status
Simulation time 218539216 ps
CPU time 0.9 seconds
Started Jun 27 06:39:14 PM PDT 24
Finished Jun 27 06:39:25 PM PDT 24
Peak memory 206252 kb
Host smart-bd6afd9c-b919-4f0e-8e92-1a1596d24ce6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10549
78383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.1054978383
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.169747080
Short name T1975
Test name
Test status
Simulation time 162276171 ps
CPU time 0.74 seconds
Started Jun 27 06:39:15 PM PDT 24
Finished Jun 27 06:39:26 PM PDT 24
Peak memory 206272 kb
Host smart-dcbe9132-2935-4b9e-9e56-aa2b2564d20e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16974
7080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.169747080
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.491680465
Short name T1860
Test name
Test status
Simulation time 194257984 ps
CPU time 0.83 seconds
Started Jun 27 06:39:10 PM PDT 24
Finished Jun 27 06:39:14 PM PDT 24
Peak memory 206276 kb
Host smart-87eaa620-71a7-41c8-a6dc-96c9b2e7f3cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49168
0465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.491680465
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.2075337907
Short name T793
Test name
Test status
Simulation time 146833086 ps
CPU time 0.8 seconds
Started Jun 27 06:39:15 PM PDT 24
Finished Jun 27 06:39:28 PM PDT 24
Peak memory 206284 kb
Host smart-b61244ea-8e05-4a3c-811d-b30071751c53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20753
37907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.2075337907
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.3301013332
Short name T2397
Test name
Test status
Simulation time 282155781 ps
CPU time 0.95 seconds
Started Jun 27 06:39:18 PM PDT 24
Finished Jun 27 06:39:33 PM PDT 24
Peak memory 206280 kb
Host smart-4a9d2c8e-77fd-43c7-9925-220699096a11
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3301013332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.3301013332
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.1563818202
Short name T432
Test name
Test status
Simulation time 179924455 ps
CPU time 0.79 seconds
Started Jun 27 06:39:18 PM PDT 24
Finished Jun 27 06:39:33 PM PDT 24
Peak memory 206260 kb
Host smart-9fb0fd0f-261e-4b3f-869e-74518fb2599a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15638
18202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.1563818202
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.2366305301
Short name T1586
Test name
Test status
Simulation time 47381120 ps
CPU time 0.7 seconds
Started Jun 27 06:39:15 PM PDT 24
Finished Jun 27 06:39:27 PM PDT 24
Peak memory 206276 kb
Host smart-1919697a-530b-41fe-9e3e-9cca8152c136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23663
05301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.2366305301
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.4088299139
Short name T2375
Test name
Test status
Simulation time 9161481988 ps
CPU time 21.29 seconds
Started Jun 27 06:39:16 PM PDT 24
Finished Jun 27 06:39:50 PM PDT 24
Peak memory 206528 kb
Host smart-90d9c396-ed2e-4d6e-9243-788e87d39886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40882
99139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.4088299139
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.3850082612
Short name T2030
Test name
Test status
Simulation time 185410876 ps
CPU time 0.9 seconds
Started Jun 27 06:39:15 PM PDT 24
Finished Jun 27 06:39:28 PM PDT 24
Peak memory 206272 kb
Host smart-0eae318d-32e3-48a8-be1e-868e028ce55e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38500
82612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.3850082612
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.1067998169
Short name T2584
Test name
Test status
Simulation time 193415125 ps
CPU time 0.84 seconds
Started Jun 27 06:39:16 PM PDT 24
Finished Jun 27 06:39:29 PM PDT 24
Peak memory 206292 kb
Host smart-f5c74527-8365-43dc-a304-40add3ec5cda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10679
98169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.1067998169
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.2856726128
Short name T1773
Test name
Test status
Simulation time 203620757 ps
CPU time 0.83 seconds
Started Jun 27 06:39:16 PM PDT 24
Finished Jun 27 06:39:29 PM PDT 24
Peak memory 206296 kb
Host smart-9043a00d-9624-4e60-9278-eef97e674ea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28567
26128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.2856726128
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.2410084457
Short name T554
Test name
Test status
Simulation time 198858023 ps
CPU time 0.86 seconds
Started Jun 27 06:39:16 PM PDT 24
Finished Jun 27 06:39:30 PM PDT 24
Peak memory 206240 kb
Host smart-d5c90758-f812-4407-9425-4dccb6059dc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24100
84457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.2410084457
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.1246812373
Short name T1681
Test name
Test status
Simulation time 171247110 ps
CPU time 0.82 seconds
Started Jun 27 06:39:17 PM PDT 24
Finished Jun 27 06:39:30 PM PDT 24
Peak memory 206288 kb
Host smart-0fba5843-30f6-4f08-85a1-da38ecb3ec60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12468
12373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.1246812373
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.2679727674
Short name T2452
Test name
Test status
Simulation time 158147548 ps
CPU time 0.8 seconds
Started Jun 27 06:39:18 PM PDT 24
Finished Jun 27 06:39:33 PM PDT 24
Peak memory 206272 kb
Host smart-265110b6-e716-4f21-8ecc-8d9e8cf97119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26797
27674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.2679727674
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.2864494161
Short name T713
Test name
Test status
Simulation time 148027911 ps
CPU time 0.77 seconds
Started Jun 27 06:39:16 PM PDT 24
Finished Jun 27 06:39:29 PM PDT 24
Peak memory 206300 kb
Host smart-3545de5e-a96b-4692-989a-93901b961319
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28644
94161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.2864494161
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.1411953749
Short name T2285
Test name
Test status
Simulation time 194061011 ps
CPU time 0.85 seconds
Started Jun 27 06:39:20 PM PDT 24
Finished Jun 27 06:39:34 PM PDT 24
Peak memory 206016 kb
Host smart-19813508-e6d1-4fc8-871b-cda206841985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14119
53749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.1411953749
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.3479487472
Short name T395
Test name
Test status
Simulation time 4015344976 ps
CPU time 104.08 seconds
Started Jun 27 06:39:19 PM PDT 24
Finished Jun 27 06:41:17 PM PDT 24
Peak memory 206456 kb
Host smart-ac1a4240-1707-4927-939d-1209cb4d0b09
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3479487472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.3479487472
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.515568670
Short name T2101
Test name
Test status
Simulation time 178874754 ps
CPU time 0.8 seconds
Started Jun 27 06:39:21 PM PDT 24
Finished Jun 27 06:39:36 PM PDT 24
Peak memory 206268 kb
Host smart-3c5771b8-68e3-41ea-8823-7715c72b6117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51556
8670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.515568670
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.1909316266
Short name T830
Test name
Test status
Simulation time 172151178 ps
CPU time 0.8 seconds
Started Jun 27 06:39:16 PM PDT 24
Finished Jun 27 06:39:29 PM PDT 24
Peak memory 206280 kb
Host smart-ad02bf2a-7cc7-4266-b5d8-c84e354332f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19093
16266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.1909316266
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.3919842209
Short name T1613
Test name
Test status
Simulation time 4225519410 ps
CPU time 110.06 seconds
Started Jun 27 06:39:16 PM PDT 24
Finished Jun 27 06:41:19 PM PDT 24
Peak memory 206456 kb
Host smart-fc883e11-063a-4326-b857-2e03ddd5c67a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39198
42209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.3919842209
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.3255421464
Short name T1911
Test name
Test status
Simulation time 33427783 ps
CPU time 0.67 seconds
Started Jun 27 06:34:56 PM PDT 24
Finished Jun 27 06:35:07 PM PDT 24
Peak memory 206336 kb
Host smart-5b0d4403-2a28-4c8f-97b2-a6cc0da96b68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3255421464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.3255421464
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.2488583413
Short name T1792
Test name
Test status
Simulation time 3535704017 ps
CPU time 4.04 seconds
Started Jun 27 06:34:41 PM PDT 24
Finished Jun 27 06:34:52 PM PDT 24
Peak memory 206336 kb
Host smart-33b853ba-d94a-4eb6-9f40-96f50fed2f29
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2488583413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.2488583413
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.3729992142
Short name T803
Test name
Test status
Simulation time 23366649472 ps
CPU time 20.7 seconds
Started Jun 27 06:34:44 PM PDT 24
Finished Jun 27 06:35:15 PM PDT 24
Peak memory 206476 kb
Host smart-d570cb71-e617-40dd-9d0a-59c699fc0bc9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3729992142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.3729992142
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.1811145688
Short name T1385
Test name
Test status
Simulation time 179344610 ps
CPU time 0.83 seconds
Started Jun 27 06:34:41 PM PDT 24
Finished Jun 27 06:34:50 PM PDT 24
Peak memory 206252 kb
Host smart-d36a01a1-d0bd-4edd-9d32-d9dfd384106e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18111
45688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.1811145688
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.3344789503
Short name T58
Test name
Test status
Simulation time 158709889 ps
CPU time 0.82 seconds
Started Jun 27 06:34:41 PM PDT 24
Finished Jun 27 06:34:50 PM PDT 24
Peak memory 206272 kb
Host smart-2b0a39f2-5e49-4e03-8f29-fdad08428546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33447
89503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.3344789503
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.1827677103
Short name T1814
Test name
Test status
Simulation time 165019666 ps
CPU time 0.75 seconds
Started Jun 27 06:34:39 PM PDT 24
Finished Jun 27 06:34:44 PM PDT 24
Peak memory 206256 kb
Host smart-dec9da6d-6883-412a-9d10-5299c987888e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18276
77103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.1827677103
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.3201895253
Short name T2554
Test name
Test status
Simulation time 549133418 ps
CPU time 1.63 seconds
Started Jun 27 06:34:43 PM PDT 24
Finished Jun 27 06:34:53 PM PDT 24
Peak memory 206352 kb
Host smart-43638174-bcd5-48ba-acff-1780223d9e80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32018
95253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.3201895253
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_device_address.592977013
Short name T870
Test name
Test status
Simulation time 18434599031 ps
CPU time 34.49 seconds
Started Jun 27 06:34:43 PM PDT 24
Finished Jun 27 06:35:28 PM PDT 24
Peak memory 206444 kb
Host smart-5724b8a1-a234-4e62-b423-b6b98a8e420b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59297
7013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.592977013
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.184983681
Short name T399
Test name
Test status
Simulation time 501363671 ps
CPU time 1.37 seconds
Started Jun 27 06:34:44 PM PDT 24
Finished Jun 27 06:34:56 PM PDT 24
Peak memory 206192 kb
Host smart-1d0a2b55-87b9-44f1-8ec4-736725af6964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18498
3681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.184983681
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.2329472402
Short name T2444
Test name
Test status
Simulation time 148041357 ps
CPU time 0.76 seconds
Started Jun 27 06:34:41 PM PDT 24
Finished Jun 27 06:34:49 PM PDT 24
Peak memory 206216 kb
Host smart-e5684932-95c0-44fa-8b82-33f6f1c31383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23294
72402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.2329472402
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.3552780805
Short name T1405
Test name
Test status
Simulation time 39509001 ps
CPU time 0.64 seconds
Started Jun 27 06:34:43 PM PDT 24
Finished Jun 27 06:34:53 PM PDT 24
Peak memory 206308 kb
Host smart-391eb7e7-0f1c-4545-b99e-ace0a37c7d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35527
80805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.3552780805
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.509352766
Short name T18
Test name
Test status
Simulation time 884226772 ps
CPU time 2.03 seconds
Started Jun 27 06:34:40 PM PDT 24
Finished Jun 27 06:34:49 PM PDT 24
Peak memory 206304 kb
Host smart-273f81b3-cffe-439a-9c83-2932f0dcd1f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50935
2766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.509352766
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.523656688
Short name T963
Test name
Test status
Simulation time 186633377 ps
CPU time 1.8 seconds
Started Jun 27 06:34:43 PM PDT 24
Finished Jun 27 06:34:55 PM PDT 24
Peak memory 206392 kb
Host smart-0b4e5879-4e9c-42b2-b3ab-dc1ca0eb4a59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52365
6688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.523656688
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.2526987221
Short name T1754
Test name
Test status
Simulation time 236023457 ps
CPU time 0.9 seconds
Started Jun 27 06:34:45 PM PDT 24
Finished Jun 27 06:34:56 PM PDT 24
Peak memory 206304 kb
Host smart-74664452-6baf-4885-9bd7-b084d2acfa50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25269
87221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.2526987221
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.3345958120
Short name T460
Test name
Test status
Simulation time 143577544 ps
CPU time 0.75 seconds
Started Jun 27 06:34:44 PM PDT 24
Finished Jun 27 06:34:54 PM PDT 24
Peak memory 206316 kb
Host smart-d16b00f2-ebc7-4509-9141-2a022ac17727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33459
58120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.3345958120
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.3300410829
Short name T1096
Test name
Test status
Simulation time 308904671 ps
CPU time 1 seconds
Started Jun 27 06:34:45 PM PDT 24
Finished Jun 27 06:34:56 PM PDT 24
Peak memory 206304 kb
Host smart-f84e05e2-bc0d-4b73-8f9b-118fd365dd85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33004
10829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.3300410829
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.4047277711
Short name T353
Test name
Test status
Simulation time 188735875 ps
CPU time 0.77 seconds
Started Jun 27 06:34:45 PM PDT 24
Finished Jun 27 06:34:56 PM PDT 24
Peak memory 206264 kb
Host smart-eddf8bd9-9093-4243-8866-cfee9375f011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40472
77711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.4047277711
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.1675694868
Short name T2321
Test name
Test status
Simulation time 23283589291 ps
CPU time 20.92 seconds
Started Jun 27 06:34:43 PM PDT 24
Finished Jun 27 06:35:14 PM PDT 24
Peak memory 206320 kb
Host smart-07fe0335-571a-43f0-873c-fa8a9fb102a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16756
94868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.1675694868
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.3299308040
Short name T1198
Test name
Test status
Simulation time 3346877495 ps
CPU time 3.51 seconds
Started Jun 27 06:34:44 PM PDT 24
Finished Jun 27 06:34:57 PM PDT 24
Peak memory 206316 kb
Host smart-bb669868-7a40-4d72-b49b-41239754a7b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32993
08040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.3299308040
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.1299478953
Short name T1617
Test name
Test status
Simulation time 11273980341 ps
CPU time 72.57 seconds
Started Jun 27 06:34:48 PM PDT 24
Finished Jun 27 06:36:11 PM PDT 24
Peak memory 206500 kb
Host smart-11b6b674-071f-48bb-9129-78a40bd6105d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12994
78953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.1299478953
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.219788703
Short name T2142
Test name
Test status
Simulation time 5602617097 ps
CPU time 39.98 seconds
Started Jun 27 06:34:45 PM PDT 24
Finished Jun 27 06:35:35 PM PDT 24
Peak memory 206464 kb
Host smart-c7022492-ffc1-40f1-a87b-2ba49675053b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=219788703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.219788703
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.1507976047
Short name T2099
Test name
Test status
Simulation time 233332297 ps
CPU time 0.88 seconds
Started Jun 27 06:34:47 PM PDT 24
Finished Jun 27 06:34:58 PM PDT 24
Peak memory 206308 kb
Host smart-366152d9-2dcb-473a-b7dc-748b4f4142d4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1507976047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.1507976047
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.3258025356
Short name T1740
Test name
Test status
Simulation time 221080734 ps
CPU time 0.89 seconds
Started Jun 27 06:34:47 PM PDT 24
Finished Jun 27 06:34:58 PM PDT 24
Peak memory 206292 kb
Host smart-cc9a0002-aad7-4df8-80cd-34711ae2bd51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32580
25356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.3258025356
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.3989045701
Short name T1614
Test name
Test status
Simulation time 3741793067 ps
CPU time 33.5 seconds
Started Jun 27 06:34:43 PM PDT 24
Finished Jun 27 06:35:27 PM PDT 24
Peak memory 206532 kb
Host smart-6b5f3d46-7482-4d56-8ffb-d77913dcb7e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39890
45701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.3989045701
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.2784011832
Short name T944
Test name
Test status
Simulation time 7496733080 ps
CPU time 191.96 seconds
Started Jun 27 06:34:45 PM PDT 24
Finished Jun 27 06:38:07 PM PDT 24
Peak memory 206456 kb
Host smart-72988e03-50b1-4bf4-a1e7-5253318828de
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2784011832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.2784011832
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.3027903673
Short name T1142
Test name
Test status
Simulation time 150679396 ps
CPU time 0.8 seconds
Started Jun 27 06:34:51 PM PDT 24
Finished Jun 27 06:35:03 PM PDT 24
Peak memory 206288 kb
Host smart-09b04d5e-2aa9-463f-a281-abf0c89db1c6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3027903673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.3027903673
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.2802288159
Short name T22
Test name
Test status
Simulation time 173368705 ps
CPU time 0.87 seconds
Started Jun 27 06:34:53 PM PDT 24
Finished Jun 27 06:35:04 PM PDT 24
Peak memory 206276 kb
Host smart-2db13e1f-5536-4a82-a979-fb4d01f6b382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28022
88159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.2802288159
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.935667035
Short name T1264
Test name
Test status
Simulation time 227518731 ps
CPU time 0.91 seconds
Started Jun 27 06:34:53 PM PDT 24
Finished Jun 27 06:35:05 PM PDT 24
Peak memory 206288 kb
Host smart-6a1c26d4-e324-44e0-9ea3-ae5d36283d88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93566
7035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.935667035
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.263634282
Short name T1836
Test name
Test status
Simulation time 196108331 ps
CPU time 0.82 seconds
Started Jun 27 06:34:53 PM PDT 24
Finished Jun 27 06:35:05 PM PDT 24
Peak memory 206288 kb
Host smart-ecf01e84-5d5d-43d0-86fe-b3e3b7c77628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26363
4282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.263634282
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.2777679406
Short name T2528
Test name
Test status
Simulation time 168546585 ps
CPU time 0.76 seconds
Started Jun 27 06:34:54 PM PDT 24
Finished Jun 27 06:35:05 PM PDT 24
Peak memory 206268 kb
Host smart-6607a5b6-4f3d-4920-99b7-d81f6c5d384a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27776
79406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.2777679406
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.3516838447
Short name T452
Test name
Test status
Simulation time 240497475 ps
CPU time 0.87 seconds
Started Jun 27 06:34:50 PM PDT 24
Finished Jun 27 06:35:02 PM PDT 24
Peak memory 206268 kb
Host smart-9274e343-b1c9-4fc8-9b71-c42f1dc9b850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35168
38447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.3516838447
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.1990700467
Short name T2369
Test name
Test status
Simulation time 204141138 ps
CPU time 0.86 seconds
Started Jun 27 06:34:52 PM PDT 24
Finished Jun 27 06:35:03 PM PDT 24
Peak memory 206276 kb
Host smart-c98c428c-a895-46fe-a864-db53b7efbff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19907
00467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.1990700467
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.3231212760
Short name T666
Test name
Test status
Simulation time 257901187 ps
CPU time 1 seconds
Started Jun 27 06:35:04 PM PDT 24
Finished Jun 27 06:35:12 PM PDT 24
Peak memory 206132 kb
Host smart-6b09c690-a3a2-4558-9a1e-e6f347397ab6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3231212760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.3231212760
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.402641756
Short name T2014
Test name
Test status
Simulation time 230943312 ps
CPU time 0.88 seconds
Started Jun 27 06:35:04 PM PDT 24
Finished Jun 27 06:35:12 PM PDT 24
Peak memory 206104 kb
Host smart-a78ed4c0-3f9d-457c-97dc-295448d880e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40264
1756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.402641756
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.1283216760
Short name T1722
Test name
Test status
Simulation time 158962632 ps
CPU time 0.76 seconds
Started Jun 27 06:34:53 PM PDT 24
Finished Jun 27 06:35:05 PM PDT 24
Peak memory 206252 kb
Host smart-8e6df857-0716-4f72-9d4e-933d4da2edc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12832
16760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.1283216760
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.1544463225
Short name T728
Test name
Test status
Simulation time 35705092 ps
CPU time 0.64 seconds
Started Jun 27 06:35:04 PM PDT 24
Finished Jun 27 06:35:12 PM PDT 24
Peak memory 206268 kb
Host smart-58b43a64-69df-41e0-b9cd-59ce384bf682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15444
63225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.1544463225
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.994757395
Short name T1862
Test name
Test status
Simulation time 22922265596 ps
CPU time 47.24 seconds
Started Jun 27 06:35:03 PM PDT 24
Finished Jun 27 06:35:57 PM PDT 24
Peak memory 206396 kb
Host smart-9fc7063a-a0cd-4d3f-978b-6c37a25a3782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99475
7395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.994757395
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.895706650
Short name T2268
Test name
Test status
Simulation time 194259921 ps
CPU time 0.86 seconds
Started Jun 27 06:34:52 PM PDT 24
Finished Jun 27 06:35:03 PM PDT 24
Peak memory 206436 kb
Host smart-67d6993c-824b-4d1e-97b3-17fb2309b1f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89570
6650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.895706650
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.2930481316
Short name T938
Test name
Test status
Simulation time 240465043 ps
CPU time 0.96 seconds
Started Jun 27 06:34:55 PM PDT 24
Finished Jun 27 06:35:06 PM PDT 24
Peak memory 206292 kb
Host smart-1b755132-d054-43e0-b65d-b767a55a7391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29304
81316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.2930481316
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.1528170645
Short name T780
Test name
Test status
Simulation time 9745288361 ps
CPU time 87.95 seconds
Started Jun 27 06:34:52 PM PDT 24
Finished Jun 27 06:36:31 PM PDT 24
Peak memory 206464 kb
Host smart-273dcbc9-7416-4664-ada2-46e79d48c58e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1528170645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.1528170645
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.3689434495
Short name T169
Test name
Test status
Simulation time 10280105011 ps
CPU time 48 seconds
Started Jun 27 06:34:54 PM PDT 24
Finished Jun 27 06:35:52 PM PDT 24
Peak memory 206380 kb
Host smart-45b5f73c-430e-4d22-9afe-46f0181d4765
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3689434495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.3689434495
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.3735292484
Short name T41
Test name
Test status
Simulation time 11644716716 ps
CPU time 78.74 seconds
Started Jun 27 06:34:54 PM PDT 24
Finished Jun 27 06:36:23 PM PDT 24
Peak memory 206416 kb
Host smart-f7c32d81-4d7e-44c6-82b3-65cb109d8af7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3735292484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.3735292484
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.1747608443
Short name T2572
Test name
Test status
Simulation time 281118502 ps
CPU time 0.9 seconds
Started Jun 27 06:35:03 PM PDT 24
Finished Jun 27 06:35:11 PM PDT 24
Peak memory 206296 kb
Host smart-cacd287b-6852-4d16-b6be-094cfb3b0d53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17476
08443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.1747608443
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.3723961412
Short name T2134
Test name
Test status
Simulation time 164096069 ps
CPU time 0.81 seconds
Started Jun 27 06:35:04 PM PDT 24
Finished Jun 27 06:35:12 PM PDT 24
Peak memory 206252 kb
Host smart-effabd00-9a81-486f-9747-5dc9a5ca3d67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37239
61412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.3723961412
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.2031095688
Short name T1471
Test name
Test status
Simulation time 166292699 ps
CPU time 0.81 seconds
Started Jun 27 06:35:02 PM PDT 24
Finished Jun 27 06:35:10 PM PDT 24
Peak memory 206224 kb
Host smart-6c149698-8bdf-48e3-afe5-c2e865af516e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20310
95688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.2031095688
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.1258715119
Short name T78
Test name
Test status
Simulation time 174417648 ps
CPU time 0.76 seconds
Started Jun 27 06:35:02 PM PDT 24
Finished Jun 27 06:35:10 PM PDT 24
Peak memory 206276 kb
Host smart-29d4ea0d-634f-430f-a039-bff164c66031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12587
15119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.1258715119
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.146668963
Short name T210
Test name
Test status
Simulation time 532702156 ps
CPU time 1.28 seconds
Started Jun 27 06:35:03 PM PDT 24
Finished Jun 27 06:35:11 PM PDT 24
Peak memory 225096 kb
Host smart-f9da7d1a-625c-4f1f-997b-03ceb0078b19
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=146668963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.146668963
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.268662735
Short name T2434
Test name
Test status
Simulation time 496009012 ps
CPU time 1.46 seconds
Started Jun 27 06:34:57 PM PDT 24
Finished Jun 27 06:35:09 PM PDT 24
Peak memory 206272 kb
Host smart-d2703134-b1c8-4be3-a473-03eb7e27b970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26866
2735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.268662735
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.3160809511
Short name T361
Test name
Test status
Simulation time 157360355 ps
CPU time 0.8 seconds
Started Jun 27 06:34:53 PM PDT 24
Finished Jun 27 06:35:05 PM PDT 24
Peak memory 206252 kb
Host smart-37782682-5899-4fc2-8c1e-fca0a9685f64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31608
09511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.3160809511
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.597950227
Short name T733
Test name
Test status
Simulation time 149878678 ps
CPU time 0.78 seconds
Started Jun 27 06:34:53 PM PDT 24
Finished Jun 27 06:35:04 PM PDT 24
Peak memory 206292 kb
Host smart-8558b2ca-6052-44f7-941e-7615c8e02e9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59795
0227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.597950227
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.4040762563
Short name T1095
Test name
Test status
Simulation time 208939736 ps
CPU time 0.93 seconds
Started Jun 27 06:35:04 PM PDT 24
Finished Jun 27 06:35:12 PM PDT 24
Peak memory 206280 kb
Host smart-b6645079-056c-4653-a61d-df52a4696ad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40407
62563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.4040762563
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.244027092
Short name T2013
Test name
Test status
Simulation time 6503318545 ps
CPU time 177.07 seconds
Started Jun 27 06:34:51 PM PDT 24
Finished Jun 27 06:37:59 PM PDT 24
Peak memory 206476 kb
Host smart-65ad8bd0-03f3-49d6-89ff-7a9f98245a44
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=244027092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.244027092
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.3408828376
Short name T2364
Test name
Test status
Simulation time 173201067 ps
CPU time 0.81 seconds
Started Jun 27 06:34:52 PM PDT 24
Finished Jun 27 06:35:03 PM PDT 24
Peak memory 206260 kb
Host smart-ffc388a9-3d25-4909-971a-99e3e227adc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34088
28376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.3408828376
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.3208256475
Short name T312
Test name
Test status
Simulation time 178942324 ps
CPU time 0.84 seconds
Started Jun 27 06:35:04 PM PDT 24
Finished Jun 27 06:35:12 PM PDT 24
Peak memory 206220 kb
Host smart-2ac53942-d9b6-4520-a5ac-bef0bffe431a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32082
56475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.3208256475
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.2274557369
Short name T2157
Test name
Test status
Simulation time 7516526647 ps
CPU time 67.85 seconds
Started Jun 27 06:34:58 PM PDT 24
Finished Jun 27 06:36:15 PM PDT 24
Peak memory 206316 kb
Host smart-919688ed-e0e8-40bf-bd2e-ddf9276f95f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22745
57369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.2274557369
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.1843270070
Short name T168
Test name
Test status
Simulation time 15589624672 ps
CPU time 132.02 seconds
Started Jun 27 06:35:03 PM PDT 24
Finished Jun 27 06:37:23 PM PDT 24
Peak memory 206400 kb
Host smart-15d5ebba-edb5-411c-b17b-6534072d547f
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1843270070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.1843270070
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.2455568050
Short name T1989
Test name
Test status
Simulation time 107534793 ps
CPU time 0.71 seconds
Started Jun 27 06:39:38 PM PDT 24
Finished Jun 27 06:39:49 PM PDT 24
Peak memory 206372 kb
Host smart-67cf5eb1-4c5c-44b6-83ed-e2c59aede62c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2455568050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.2455568050
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.4235643381
Short name T1075
Test name
Test status
Simulation time 4051149090 ps
CPU time 4.38 seconds
Started Jun 27 06:39:25 PM PDT 24
Finished Jun 27 06:39:43 PM PDT 24
Peak memory 206500 kb
Host smart-8b296b8a-dd73-4409-b682-1fbfa34fbe87
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4235643381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.4235643381
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.1706078460
Short name T2208
Test name
Test status
Simulation time 13408324901 ps
CPU time 13.44 seconds
Started Jun 27 06:39:28 PM PDT 24
Finished Jun 27 06:39:54 PM PDT 24
Peak memory 206304 kb
Host smart-7cf3cc38-b80f-471b-a041-9057f745bcb2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1706078460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.1706078460
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.2800725876
Short name T783
Test name
Test status
Simulation time 23448530758 ps
CPU time 23.9 seconds
Started Jun 27 06:39:25 PM PDT 24
Finished Jun 27 06:40:02 PM PDT 24
Peak memory 206400 kb
Host smart-a9adacbf-ad96-4c41-a716-a84792187a4f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2800725876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.2800725876
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.2907632182
Short name T2060
Test name
Test status
Simulation time 207488529 ps
CPU time 0.81 seconds
Started Jun 27 06:39:30 PM PDT 24
Finished Jun 27 06:39:43 PM PDT 24
Peak memory 206228 kb
Host smart-d737c6fc-42cb-4b59-96f6-1b3ee6ef0ad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29076
32182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.2907632182
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.3094811116
Short name T1896
Test name
Test status
Simulation time 192984537 ps
CPU time 0.83 seconds
Started Jun 27 06:39:28 PM PDT 24
Finished Jun 27 06:39:41 PM PDT 24
Peak memory 206288 kb
Host smart-fadc2d2a-8ba0-466c-b99c-8c5fefe4e5b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30948
11116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.3094811116
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.433091968
Short name T2026
Test name
Test status
Simulation time 417381946 ps
CPU time 1.36 seconds
Started Jun 27 06:39:28 PM PDT 24
Finished Jun 27 06:39:41 PM PDT 24
Peak memory 206288 kb
Host smart-8646a508-6817-4e9e-8f35-828d9c1c15a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43309
1968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.433091968
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.1556327148
Short name T2473
Test name
Test status
Simulation time 924915811 ps
CPU time 2.16 seconds
Started Jun 27 06:39:26 PM PDT 24
Finished Jun 27 06:39:41 PM PDT 24
Peak memory 206576 kb
Host smart-9ceefbd0-f1aa-4599-95df-69c5cceebec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15563
27148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.1556327148
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.693919779
Short name T93
Test name
Test status
Simulation time 17568409477 ps
CPU time 33.49 seconds
Started Jun 27 06:39:31 PM PDT 24
Finished Jun 27 06:40:15 PM PDT 24
Peak memory 206420 kb
Host smart-3f071751-9c97-4e40-8a24-20d8fcc252b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69391
9779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.693919779
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.3414875318
Short name T950
Test name
Test status
Simulation time 428578984 ps
CPU time 1.27 seconds
Started Jun 27 06:39:28 PM PDT 24
Finished Jun 27 06:39:41 PM PDT 24
Peak memory 206220 kb
Host smart-ea3ea166-729b-47ec-83cb-3925b7fb88d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34148
75318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.3414875318
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.3100017026
Short name T1245
Test name
Test status
Simulation time 132141712 ps
CPU time 0.73 seconds
Started Jun 27 06:39:33 PM PDT 24
Finished Jun 27 06:39:45 PM PDT 24
Peak memory 206244 kb
Host smart-70092fed-01cf-41e9-9661-1b1165aa9523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31000
17026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.3100017026
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.563602220
Short name T2312
Test name
Test status
Simulation time 48337569 ps
CPU time 0.65 seconds
Started Jun 27 06:39:25 PM PDT 24
Finished Jun 27 06:39:38 PM PDT 24
Peak memory 206284 kb
Host smart-57697cf9-6f96-4e0f-8a86-0a0038755b52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56360
2220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.563602220
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.4214524254
Short name T1191
Test name
Test status
Simulation time 1019192793 ps
CPU time 2.53 seconds
Started Jun 27 06:39:26 PM PDT 24
Finished Jun 27 06:39:41 PM PDT 24
Peak memory 206388 kb
Host smart-150638a8-41de-4268-a8db-c64ebd038d3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42145
24254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.4214524254
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.1486320217
Short name T189
Test name
Test status
Simulation time 164438623 ps
CPU time 1.41 seconds
Started Jun 27 06:39:26 PM PDT 24
Finished Jun 27 06:39:41 PM PDT 24
Peak memory 206412 kb
Host smart-1215ea4d-2f0a-48eb-a989-3c14e16e1b0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14863
20217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.1486320217
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.10502491
Short name T1988
Test name
Test status
Simulation time 194958162 ps
CPU time 0.86 seconds
Started Jun 27 06:39:33 PM PDT 24
Finished Jun 27 06:39:44 PM PDT 24
Peak memory 206288 kb
Host smart-a44b6842-12bf-4e34-9432-640c8937e9f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10502
491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.10502491
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.1121949799
Short name T991
Test name
Test status
Simulation time 145741345 ps
CPU time 0.76 seconds
Started Jun 27 06:39:25 PM PDT 24
Finished Jun 27 06:39:38 PM PDT 24
Peak memory 206284 kb
Host smart-9658dcde-aa9c-4a22-bfe3-fffe539701f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11219
49799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.1121949799
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.791447884
Short name T1685
Test name
Test status
Simulation time 216913424 ps
CPU time 0.97 seconds
Started Jun 27 06:39:27 PM PDT 24
Finished Jun 27 06:39:40 PM PDT 24
Peak memory 206232 kb
Host smart-426cd70f-f229-4db5-8c61-7104b37bb0fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79144
7884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.791447884
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.374959746
Short name T2040
Test name
Test status
Simulation time 205057590 ps
CPU time 0.85 seconds
Started Jun 27 06:39:28 PM PDT 24
Finished Jun 27 06:39:41 PM PDT 24
Peak memory 206220 kb
Host smart-9c2ae78d-d094-4596-b5e2-44aae304ef6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37495
9746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.374959746
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.646684489
Short name T2500
Test name
Test status
Simulation time 23307607252 ps
CPU time 23.98 seconds
Started Jun 27 06:39:24 PM PDT 24
Finished Jun 27 06:40:01 PM PDT 24
Peak memory 206344 kb
Host smart-686e6307-b7e1-404c-8fda-7885d60d9e83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64668
4489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.646684489
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.407013850
Short name T739
Test name
Test status
Simulation time 3285007576 ps
CPU time 3.76 seconds
Started Jun 27 06:39:40 PM PDT 24
Finished Jun 27 06:39:55 PM PDT 24
Peak memory 206236 kb
Host smart-87f7e4d9-fdbf-41b3-86db-7a81146122c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40701
3850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.407013850
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.1227702499
Short name T1101
Test name
Test status
Simulation time 8026756967 ps
CPU time 54.18 seconds
Started Jun 27 06:39:25 PM PDT 24
Finished Jun 27 06:40:33 PM PDT 24
Peak memory 206492 kb
Host smart-61c1c795-35c0-4860-a185-e2112996fdf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12277
02499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.1227702499
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.847155271
Short name T764
Test name
Test status
Simulation time 5665828306 ps
CPU time 151.18 seconds
Started Jun 27 06:39:30 PM PDT 24
Finished Jun 27 06:42:13 PM PDT 24
Peak memory 206440 kb
Host smart-c40371e5-ff56-4111-a72a-aef9738c6850
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=847155271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.847155271
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.2934025707
Short name T2469
Test name
Test status
Simulation time 280263006 ps
CPU time 0.91 seconds
Started Jun 27 06:39:33 PM PDT 24
Finished Jun 27 06:39:45 PM PDT 24
Peak memory 206268 kb
Host smart-d25e528d-e9cc-4b00-9bfc-6bf20e01ed74
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2934025707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.2934025707
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.563856107
Short name T372
Test name
Test status
Simulation time 204006402 ps
CPU time 0.94 seconds
Started Jun 27 06:39:30 PM PDT 24
Finished Jun 27 06:39:43 PM PDT 24
Peak memory 206240 kb
Host smart-830e797c-135d-4744-b44a-3ce4c9f1e283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56385
6107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.563856107
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.3708806804
Short name T718
Test name
Test status
Simulation time 4691147674 ps
CPU time 32.44 seconds
Started Jun 27 06:39:33 PM PDT 24
Finished Jun 27 06:40:16 PM PDT 24
Peak memory 206488 kb
Host smart-0eddad5d-9c8c-47d2-b2f6-a8c0b968bf55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37088
06804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.3708806804
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.3616961577
Short name T2217
Test name
Test status
Simulation time 2998154082 ps
CPU time 79 seconds
Started Jun 27 06:39:30 PM PDT 24
Finished Jun 27 06:41:00 PM PDT 24
Peak memory 206440 kb
Host smart-dc520b31-47c4-431a-ac51-82f9272587f4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3616961577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.3616961577
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.2137486327
Short name T1967
Test name
Test status
Simulation time 161751426 ps
CPU time 0.85 seconds
Started Jun 27 06:39:24 PM PDT 24
Finished Jun 27 06:39:39 PM PDT 24
Peak memory 206296 kb
Host smart-9a72befb-53b4-43d6-b891-07c9cca2955d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2137486327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.2137486327
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.3874326569
Short name T839
Test name
Test status
Simulation time 162550201 ps
CPU time 0.8 seconds
Started Jun 27 06:39:40 PM PDT 24
Finished Jun 27 06:39:52 PM PDT 24
Peak memory 206176 kb
Host smart-fa2626de-d035-4028-bcfe-79734d0b19c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38743
26569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.3874326569
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.3568284851
Short name T2518
Test name
Test status
Simulation time 208472060 ps
CPU time 0.86 seconds
Started Jun 27 06:39:33 PM PDT 24
Finished Jun 27 06:39:44 PM PDT 24
Peak memory 206252 kb
Host smart-f0a94b72-b53d-46b6-980d-de050c410209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35682
84851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.3568284851
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.3587332903
Short name T1631
Test name
Test status
Simulation time 189683186 ps
CPU time 0.87 seconds
Started Jun 27 06:39:30 PM PDT 24
Finished Jun 27 06:39:43 PM PDT 24
Peak memory 206304 kb
Host smart-24007aa1-928d-4fbc-a7d1-a9880f98e345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35873
32903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.3587332903
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.1761378785
Short name T786
Test name
Test status
Simulation time 184166336 ps
CPU time 0.83 seconds
Started Jun 27 06:39:28 PM PDT 24
Finished Jun 27 06:39:41 PM PDT 24
Peak memory 206260 kb
Host smart-a2112802-7a8a-4dca-ab1d-59aed20c39ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17613
78785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.1761378785
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.3625070698
Short name T468
Test name
Test status
Simulation time 185773548 ps
CPU time 0.76 seconds
Started Jun 27 06:39:24 PM PDT 24
Finished Jun 27 06:39:38 PM PDT 24
Peak memory 206284 kb
Host smart-043041b2-47f4-4372-8970-48d68569874b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36250
70698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.3625070698
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.1651856583
Short name T1825
Test name
Test status
Simulation time 164067679 ps
CPU time 0.78 seconds
Started Jun 27 06:39:30 PM PDT 24
Finished Jun 27 06:39:42 PM PDT 24
Peak memory 206144 kb
Host smart-4e7d47de-59bb-4cbd-8a52-2ca68bd98c89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16518
56583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.1651856583
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.463105211
Short name T1047
Test name
Test status
Simulation time 243201498 ps
CPU time 0.97 seconds
Started Jun 27 06:39:33 PM PDT 24
Finished Jun 27 06:39:45 PM PDT 24
Peak memory 206268 kb
Host smart-447ff628-66ad-4809-9cd6-1bf641046760
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=463105211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.463105211
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.1719612434
Short name T1268
Test name
Test status
Simulation time 141399894 ps
CPU time 0.78 seconds
Started Jun 27 06:39:31 PM PDT 24
Finished Jun 27 06:39:43 PM PDT 24
Peak memory 206288 kb
Host smart-e1ab85c6-1463-4979-96b2-271c9af63754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17196
12434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.1719612434
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.62454869
Short name T1361
Test name
Test status
Simulation time 35255817 ps
CPU time 0.65 seconds
Started Jun 27 06:39:31 PM PDT 24
Finished Jun 27 06:39:43 PM PDT 24
Peak memory 206284 kb
Host smart-df90c1de-dd57-499f-b762-e6ecb76fc572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62454
869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.62454869
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.3084604487
Short name T884
Test name
Test status
Simulation time 8989388128 ps
CPU time 19.83 seconds
Started Jun 27 06:39:26 PM PDT 24
Finished Jun 27 06:39:58 PM PDT 24
Peak memory 206424 kb
Host smart-da7626ee-aad5-43d2-b056-54f99f11ac95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30846
04487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.3084604487
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.2437246183
Short name T1293
Test name
Test status
Simulation time 181513597 ps
CPU time 0.83 seconds
Started Jun 27 06:39:29 PM PDT 24
Finished Jun 27 06:39:41 PM PDT 24
Peak memory 206256 kb
Host smart-7d2a41c4-060c-448e-9462-72f3a7f37611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24372
46183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.2437246183
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.153062749
Short name T405
Test name
Test status
Simulation time 223312684 ps
CPU time 0.92 seconds
Started Jun 27 06:39:31 PM PDT 24
Finished Jun 27 06:39:43 PM PDT 24
Peak memory 206280 kb
Host smart-98cdc018-760a-4d5a-ac83-de888997efe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15306
2749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.153062749
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.1093778597
Short name T1845
Test name
Test status
Simulation time 218882440 ps
CPU time 0.85 seconds
Started Jun 27 06:39:28 PM PDT 24
Finished Jun 27 06:39:41 PM PDT 24
Peak memory 206296 kb
Host smart-f4d4eb92-0df1-4c1f-8f9c-f518eb2c2ba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10937
78597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.1093778597
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.1019078624
Short name T1334
Test name
Test status
Simulation time 178271976 ps
CPU time 0.83 seconds
Started Jun 27 06:39:28 PM PDT 24
Finished Jun 27 06:39:41 PM PDT 24
Peak memory 206276 kb
Host smart-38298a63-3834-4b9e-9643-662699c15a5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10190
78624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.1019078624
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.3398041102
Short name T490
Test name
Test status
Simulation time 158515537 ps
CPU time 0.77 seconds
Started Jun 27 06:39:31 PM PDT 24
Finished Jun 27 06:39:43 PM PDT 24
Peak memory 206148 kb
Host smart-605d3c6c-1c70-47df-a3a3-3935bee3ed66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33980
41102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.3398041102
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.771462472
Short name T1993
Test name
Test status
Simulation time 164149910 ps
CPU time 0.78 seconds
Started Jun 27 06:39:31 PM PDT 24
Finished Jun 27 06:39:43 PM PDT 24
Peak memory 206288 kb
Host smart-713ed239-bce5-4871-90e6-f2fcd1f53185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77146
2472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.771462472
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.348142868
Short name T327
Test name
Test status
Simulation time 158068004 ps
CPU time 0.78 seconds
Started Jun 27 06:39:32 PM PDT 24
Finished Jun 27 06:39:43 PM PDT 24
Peak memory 206160 kb
Host smart-54e00a74-25d6-47b7-aca8-43839452349a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34814
2868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.348142868
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.2200107085
Short name T2382
Test name
Test status
Simulation time 222261016 ps
CPU time 0.96 seconds
Started Jun 27 06:39:30 PM PDT 24
Finished Jun 27 06:39:42 PM PDT 24
Peak memory 206288 kb
Host smart-5d8b31a0-5ab9-4966-b4da-692466d97f7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22001
07085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.2200107085
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.1295476615
Short name T1886
Test name
Test status
Simulation time 5229545158 ps
CPU time 144.11 seconds
Started Jun 27 06:39:25 PM PDT 24
Finished Jun 27 06:42:02 PM PDT 24
Peak memory 206436 kb
Host smart-107eaecd-3d02-412a-bb2a-d5fca7e907ed
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1295476615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.1295476615
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.2669867604
Short name T374
Test name
Test status
Simulation time 237849757 ps
CPU time 0.84 seconds
Started Jun 27 06:39:31 PM PDT 24
Finished Jun 27 06:39:43 PM PDT 24
Peak memory 206276 kb
Host smart-bcff8895-4d70-4502-9fb0-f64a6c3f1156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26698
67604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.2669867604
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.1112880465
Short name T2533
Test name
Test status
Simulation time 249587821 ps
CPU time 0.89 seconds
Started Jun 27 06:39:40 PM PDT 24
Finished Jun 27 06:39:52 PM PDT 24
Peak memory 206172 kb
Host smart-d20005c4-c69a-4ec5-96b6-2f63fe4c40b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11128
80465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.1112880465
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.362261796
Short name T2359
Test name
Test status
Simulation time 5552670078 ps
CPU time 39.31 seconds
Started Jun 27 06:39:30 PM PDT 24
Finished Jun 27 06:40:21 PM PDT 24
Peak memory 205988 kb
Host smart-47c8ab5d-d320-4ab7-b0f3-f7ad410c4517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36226
1796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.362261796
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.2369580272
Short name T2581
Test name
Test status
Simulation time 33713370 ps
CPU time 0.64 seconds
Started Jun 27 06:39:42 PM PDT 24
Finished Jun 27 06:39:53 PM PDT 24
Peak memory 206364 kb
Host smart-f0763960-a707-405e-ad63-9027d1cc6613
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2369580272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.2369580272
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.2796486977
Short name T2602
Test name
Test status
Simulation time 4096208737 ps
CPU time 4.89 seconds
Started Jun 27 06:39:37 PM PDT 24
Finished Jun 27 06:39:51 PM PDT 24
Peak memory 206312 kb
Host smart-789993a3-6532-45ac-999b-594344e1adc8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2796486977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.2796486977
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.712349621
Short name T2086
Test name
Test status
Simulation time 13385497212 ps
CPU time 12.74 seconds
Started Jun 27 06:39:40 PM PDT 24
Finished Jun 27 06:40:04 PM PDT 24
Peak memory 206296 kb
Host smart-f4b1d27a-d722-4a16-9582-3e1cc16e3239
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=712349621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.712349621
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.408076329
Short name T1228
Test name
Test status
Simulation time 23399929273 ps
CPU time 27.7 seconds
Started Jun 27 06:39:37 PM PDT 24
Finished Jun 27 06:40:15 PM PDT 24
Peak memory 206372 kb
Host smart-00b7eff6-e171-4474-bc06-822b6ec7d1d2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=408076329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.408076329
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.385441889
Short name T885
Test name
Test status
Simulation time 153444868 ps
CPU time 0.78 seconds
Started Jun 27 06:39:37 PM PDT 24
Finished Jun 27 06:39:49 PM PDT 24
Peak memory 206228 kb
Host smart-34369ce3-1003-494e-8f31-248789afb6f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38544
1889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.385441889
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.1975064244
Short name T2097
Test name
Test status
Simulation time 156672135 ps
CPU time 0.81 seconds
Started Jun 27 06:39:40 PM PDT 24
Finished Jun 27 06:39:52 PM PDT 24
Peak memory 206104 kb
Host smart-f78dae56-fc35-4bbe-9612-d23f5917c520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19750
64244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.1975064244
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.3943220566
Short name T1828
Test name
Test status
Simulation time 277853192 ps
CPU time 1.03 seconds
Started Jun 27 06:39:37 PM PDT 24
Finished Jun 27 06:39:49 PM PDT 24
Peak memory 206228 kb
Host smart-0b39603b-d5de-47dc-998f-068cf2c30592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39432
20566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.3943220566
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.2178882356
Short name T1132
Test name
Test status
Simulation time 474834830 ps
CPU time 1.24 seconds
Started Jun 27 06:39:36 PM PDT 24
Finished Jun 27 06:39:47 PM PDT 24
Peak memory 206244 kb
Host smart-854f3db6-72aa-4f07-a28e-294c3a35796a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21788
82356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.2178882356
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.1453018464
Short name T766
Test name
Test status
Simulation time 11072897134 ps
CPU time 20.23 seconds
Started Jun 27 06:39:35 PM PDT 24
Finished Jun 27 06:40:06 PM PDT 24
Peak memory 206516 kb
Host smart-6a78a30a-55e8-49af-a26d-1ddccd7f9e7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14530
18464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.1453018464
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.3828511704
Short name T2213
Test name
Test status
Simulation time 335933436 ps
CPU time 1.1 seconds
Started Jun 27 06:39:34 PM PDT 24
Finished Jun 27 06:39:45 PM PDT 24
Peak memory 206288 kb
Host smart-2d79202e-d373-467b-b783-819ec43a041c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38285
11704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.3828511704
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.246640348
Short name T2250
Test name
Test status
Simulation time 147316252 ps
CPU time 0.78 seconds
Started Jun 27 06:39:35 PM PDT 24
Finished Jun 27 06:39:46 PM PDT 24
Peak memory 206288 kb
Host smart-21cfc755-c6db-4532-8b9e-80099896b0bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24664
0348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.246640348
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.3739466035
Short name T790
Test name
Test status
Simulation time 33807806 ps
CPU time 0.65 seconds
Started Jun 27 06:39:34 PM PDT 24
Finished Jun 27 06:39:45 PM PDT 24
Peak memory 206292 kb
Host smart-34d2f4f4-a181-47a0-9a49-f92178f77c5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37394
66035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.3739466035
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.2026185778
Short name T1895
Test name
Test status
Simulation time 780770747 ps
CPU time 1.75 seconds
Started Jun 27 06:39:38 PM PDT 24
Finished Jun 27 06:39:50 PM PDT 24
Peak memory 206396 kb
Host smart-6dfab2bf-4747-412f-9d66-faa43877ce35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20261
85778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.2026185778
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.2884457930
Short name T1823
Test name
Test status
Simulation time 267033768 ps
CPU time 1.96 seconds
Started Jun 27 06:39:34 PM PDT 24
Finished Jun 27 06:39:46 PM PDT 24
Peak memory 206380 kb
Host smart-0db1ed62-cc0b-4000-a7f7-3d895faa0f31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28844
57930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.2884457930
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.3756960965
Short name T1837
Test name
Test status
Simulation time 173166402 ps
CPU time 0.79 seconds
Started Jun 27 06:39:31 PM PDT 24
Finished Jun 27 06:39:43 PM PDT 24
Peak memory 206288 kb
Host smart-a2f73354-aad9-472a-9aee-6d408aa8af7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37569
60965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.3756960965
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.3138901507
Short name T1749
Test name
Test status
Simulation time 136933514 ps
CPU time 0.72 seconds
Started Jun 27 06:39:30 PM PDT 24
Finished Jun 27 06:39:42 PM PDT 24
Peak memory 206296 kb
Host smart-e3b3d9ff-3904-4134-a198-a8bfe1a974fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31389
01507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.3138901507
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.4067857094
Short name T778
Test name
Test status
Simulation time 229036655 ps
CPU time 0.88 seconds
Started Jun 27 06:39:30 PM PDT 24
Finished Jun 27 06:39:42 PM PDT 24
Peak memory 206296 kb
Host smart-121e667e-88e7-45bf-8ecf-897ea8f501d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40678
57094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.4067857094
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_invalid_sync.279895117
Short name T767
Test name
Test status
Simulation time 7232198390 ps
CPU time 51.81 seconds
Started Jun 27 06:39:25 PM PDT 24
Finished Jun 27 06:40:29 PM PDT 24
Peak memory 206404 kb
Host smart-e910c319-7fdf-4a6d-b6db-7536801c64aa
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=279895117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.279895117
Directory /workspace/31.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.1733008367
Short name T1742
Test name
Test status
Simulation time 183778448 ps
CPU time 0.83 seconds
Started Jun 27 06:39:32 PM PDT 24
Finished Jun 27 06:39:44 PM PDT 24
Peak memory 206272 kb
Host smart-8fe04ccd-e9ca-408d-ba25-7e4aade0ce71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17330
08367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.1733008367
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.4171846982
Short name T759
Test name
Test status
Simulation time 23328575763 ps
CPU time 22.36 seconds
Started Jun 27 06:39:30 PM PDT 24
Finished Jun 27 06:40:04 PM PDT 24
Peak memory 206340 kb
Host smart-fc41b967-85c2-48a5-aeff-b3d28d6b0741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41718
46982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.4171846982
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.3404181899
Short name T324
Test name
Test status
Simulation time 3360110445 ps
CPU time 4.37 seconds
Started Jun 27 06:39:30 PM PDT 24
Finished Jun 27 06:39:46 PM PDT 24
Peak memory 206140 kb
Host smart-6279a8f5-b88a-4a59-a262-4509330613d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34041
81899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.3404181899
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.3962583174
Short name T542
Test name
Test status
Simulation time 9177367888 ps
CPU time 59.56 seconds
Started Jun 27 06:39:30 PM PDT 24
Finished Jun 27 06:40:41 PM PDT 24
Peak memory 206496 kb
Host smart-85d5fb55-6c8d-4992-8a29-0769d17f73fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39625
83174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.3962583174
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.2397071172
Short name T1009
Test name
Test status
Simulation time 4102227273 ps
CPU time 112.99 seconds
Started Jun 27 06:39:40 PM PDT 24
Finished Jun 27 06:41:44 PM PDT 24
Peak memory 206368 kb
Host smart-dcbc7a94-0ee3-4135-827e-af5a635ef099
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2397071172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.2397071172
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.2177559024
Short name T1726
Test name
Test status
Simulation time 256287852 ps
CPU time 0.91 seconds
Started Jun 27 06:39:30 PM PDT 24
Finished Jun 27 06:39:42 PM PDT 24
Peak memory 206300 kb
Host smart-6be5bd28-2423-4c3f-92d9-6dbef5547f3e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2177559024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.2177559024
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.4164309539
Short name T2516
Test name
Test status
Simulation time 205314921 ps
CPU time 0.89 seconds
Started Jun 27 06:39:30 PM PDT 24
Finished Jun 27 06:39:43 PM PDT 24
Peak memory 206048 kb
Host smart-54e006ec-8546-424a-9e84-470db9050cfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41643
09539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.4164309539
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.2941238383
Short name T2160
Test name
Test status
Simulation time 5714720195 ps
CPU time 149.33 seconds
Started Jun 27 06:39:40 PM PDT 24
Finished Jun 27 06:42:20 PM PDT 24
Peak memory 206276 kb
Host smart-0d2f0f45-b035-4ef1-8a2d-ff3d161d9602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29412
38383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.2941238383
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.2739896779
Short name T2199
Test name
Test status
Simulation time 4686060397 ps
CPU time 32.13 seconds
Started Jun 27 06:39:38 PM PDT 24
Finished Jun 27 06:40:21 PM PDT 24
Peak memory 206508 kb
Host smart-bc83b3b8-d6ae-4e8c-9bb9-fc3fc3417f36
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2739896779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.2739896779
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.4112925745
Short name T1429
Test name
Test status
Simulation time 155874140 ps
CPU time 0.79 seconds
Started Jun 27 06:39:36 PM PDT 24
Finished Jun 27 06:39:47 PM PDT 24
Peak memory 206248 kb
Host smart-6b46648f-b38b-4b66-bc24-f0198b60bc5d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4112925745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.4112925745
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.604472856
Short name T676
Test name
Test status
Simulation time 187318732 ps
CPU time 0.8 seconds
Started Jun 27 06:39:40 PM PDT 24
Finished Jun 27 06:39:52 PM PDT 24
Peak memory 206180 kb
Host smart-a025058f-28ce-4652-9ec5-e96ac23fcc46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60447
2856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.604472856
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.1484632354
Short name T130
Test name
Test status
Simulation time 238972669 ps
CPU time 0.95 seconds
Started Jun 27 06:39:37 PM PDT 24
Finished Jun 27 06:39:49 PM PDT 24
Peak memory 206232 kb
Host smart-0bc2a632-365e-4604-8532-f11335217e26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14846
32354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.1484632354
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.3064726283
Short name T1619
Test name
Test status
Simulation time 142505221 ps
CPU time 0.74 seconds
Started Jun 27 06:39:36 PM PDT 24
Finished Jun 27 06:39:47 PM PDT 24
Peak memory 206244 kb
Host smart-6b1bfae1-b0ea-44fb-a051-ada62496dc7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30647
26283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.3064726283
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.3030039701
Short name T1356
Test name
Test status
Simulation time 166320836 ps
CPU time 0.75 seconds
Started Jun 27 06:39:40 PM PDT 24
Finished Jun 27 06:39:52 PM PDT 24
Peak memory 206176 kb
Host smart-b6f00daa-b969-4e21-81d2-e91aff033cc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30300
39701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.3030039701
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.596791988
Short name T2070
Test name
Test status
Simulation time 188577914 ps
CPU time 0.78 seconds
Started Jun 27 06:39:38 PM PDT 24
Finished Jun 27 06:39:49 PM PDT 24
Peak memory 206288 kb
Host smart-74972b23-2f3a-4b42-86a7-90d75c2cd085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59679
1988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.596791988
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.1360848066
Short name T495
Test name
Test status
Simulation time 151526942 ps
CPU time 0.72 seconds
Started Jun 27 06:39:38 PM PDT 24
Finished Jun 27 06:39:49 PM PDT 24
Peak memory 206292 kb
Host smart-8f5a3faf-9ce4-4ada-9a29-be13bb880bfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13608
48066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.1360848066
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.1499418727
Short name T1240
Test name
Test status
Simulation time 187246449 ps
CPU time 0.84 seconds
Started Jun 27 06:39:38 PM PDT 24
Finished Jun 27 06:39:50 PM PDT 24
Peak memory 206308 kb
Host smart-adbc9b8b-7873-4476-8cfc-1399dff35021
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1499418727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.1499418727
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.512896466
Short name T843
Test name
Test status
Simulation time 149644068 ps
CPU time 0.75 seconds
Started Jun 27 06:39:39 PM PDT 24
Finished Jun 27 06:39:50 PM PDT 24
Peak memory 206292 kb
Host smart-9b02d820-88e1-4e0e-b0e1-16895fb35cdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51289
6466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.512896466
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.2554971693
Short name T1242
Test name
Test status
Simulation time 34070910 ps
CPU time 0.67 seconds
Started Jun 27 06:39:35 PM PDT 24
Finished Jun 27 06:39:46 PM PDT 24
Peak memory 206280 kb
Host smart-c253ccb1-cc23-406e-bded-8d85350b91c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25549
71693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.2554971693
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.1794777029
Short name T258
Test name
Test status
Simulation time 18961159480 ps
CPU time 38.84 seconds
Started Jun 27 06:39:35 PM PDT 24
Finished Jun 27 06:40:24 PM PDT 24
Peak memory 214656 kb
Host smart-5b7bf4ed-ddd4-41b7-9ae5-b2c8d84c5e5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17947
77029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.1794777029
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.1133060654
Short name T1100
Test name
Test status
Simulation time 201011120 ps
CPU time 0.87 seconds
Started Jun 27 06:39:39 PM PDT 24
Finished Jun 27 06:39:51 PM PDT 24
Peak memory 206288 kb
Host smart-b82de80d-8c0c-4797-b92f-893c4ca24442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11330
60654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.1133060654
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.127537755
Short name T345
Test name
Test status
Simulation time 210026738 ps
CPU time 0.82 seconds
Started Jun 27 06:39:38 PM PDT 24
Finished Jun 27 06:39:49 PM PDT 24
Peak memory 206300 kb
Host smart-0a6e9286-8c44-42ab-9852-ccac8d427486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12753
7755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.127537755
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.139011819
Short name T1495
Test name
Test status
Simulation time 245608822 ps
CPU time 0.86 seconds
Started Jun 27 06:39:39 PM PDT 24
Finished Jun 27 06:39:51 PM PDT 24
Peak memory 206308 kb
Host smart-7f75c19f-a72e-4b81-a6a6-2dc6448d950d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13901
1819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.139011819
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.3044726654
Short name T1584
Test name
Test status
Simulation time 168788268 ps
CPU time 0.83 seconds
Started Jun 27 06:39:25 PM PDT 24
Finished Jun 27 06:39:38 PM PDT 24
Peak memory 206268 kb
Host smart-b262382c-c703-42e8-b660-a8e15032d55a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30447
26654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.3044726654
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.2254953129
Short name T1341
Test name
Test status
Simulation time 182953480 ps
CPU time 0.8 seconds
Started Jun 27 06:39:43 PM PDT 24
Finished Jun 27 06:39:54 PM PDT 24
Peak memory 206236 kb
Host smart-f98bde73-7df5-42eb-a644-c0dbd75b99f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22549
53129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.2254953129
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.1505261962
Short name T436
Test name
Test status
Simulation time 142734726 ps
CPU time 0.75 seconds
Started Jun 27 06:39:46 PM PDT 24
Finished Jun 27 06:39:57 PM PDT 24
Peak memory 206260 kb
Host smart-f466e483-e529-4062-9b4f-79fc192030cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15052
61962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.1505261962
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.4113033567
Short name T1843
Test name
Test status
Simulation time 234040452 ps
CPU time 0.83 seconds
Started Jun 27 06:39:44 PM PDT 24
Finished Jun 27 06:39:55 PM PDT 24
Peak memory 206272 kb
Host smart-ef0dc523-2e6d-4d3b-8c0d-af77cdae32fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41130
33567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.4113033567
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.3363329300
Short name T456
Test name
Test status
Simulation time 269360913 ps
CPU time 0.97 seconds
Started Jun 27 06:39:42 PM PDT 24
Finished Jun 27 06:39:54 PM PDT 24
Peak memory 206300 kb
Host smart-0c5edaa9-5e0c-4287-985e-58f84702fc1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33633
29300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.3363329300
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.1777146207
Short name T1752
Test name
Test status
Simulation time 4705323908 ps
CPU time 128.34 seconds
Started Jun 27 06:39:41 PM PDT 24
Finished Jun 27 06:42:00 PM PDT 24
Peak memory 206428 kb
Host smart-a3969a29-33e2-40bc-aa8e-7fe385afa1bd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1777146207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.1777146207
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.1248133391
Short name T2304
Test name
Test status
Simulation time 169626705 ps
CPU time 0.8 seconds
Started Jun 27 06:39:43 PM PDT 24
Finished Jun 27 06:39:55 PM PDT 24
Peak memory 206276 kb
Host smart-d616877c-086d-4b26-bc44-e9fe3f917c72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12481
33391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.1248133391
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.1892779173
Short name T2626
Test name
Test status
Simulation time 183318495 ps
CPU time 0.79 seconds
Started Jun 27 06:39:46 PM PDT 24
Finished Jun 27 06:39:57 PM PDT 24
Peak memory 206436 kb
Host smart-79166e73-58e5-4922-be80-b4a35e336eaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18927
79173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.1892779173
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.2322869458
Short name T2515
Test name
Test status
Simulation time 5844430149 ps
CPU time 148.77 seconds
Started Jun 27 06:39:43 PM PDT 24
Finished Jun 27 06:42:23 PM PDT 24
Peak memory 206412 kb
Host smart-53344464-345d-4d0a-86c3-f6ac2a218fc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23228
69458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.2322869458
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.146051636
Short name T772
Test name
Test status
Simulation time 37771300 ps
CPU time 0.64 seconds
Started Jun 27 06:39:47 PM PDT 24
Finished Jun 27 06:39:58 PM PDT 24
Peak memory 206352 kb
Host smart-2b261841-101b-4179-991b-bff237823c64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=146051636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.146051636
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.3683270574
Short name T1797
Test name
Test status
Simulation time 3777416377 ps
CPU time 5.39 seconds
Started Jun 27 06:39:43 PM PDT 24
Finished Jun 27 06:39:59 PM PDT 24
Peak memory 206340 kb
Host smart-a18711d4-d4a3-4e53-86da-5a56935c9649
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3683270574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.3683270574
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.2446553925
Short name T1810
Test name
Test status
Simulation time 13335228691 ps
CPU time 12.81 seconds
Started Jun 27 06:39:42 PM PDT 24
Finished Jun 27 06:40:05 PM PDT 24
Peak memory 206324 kb
Host smart-627ec2b7-8730-4786-868d-a3d0ad9e2bc4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2446553925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.2446553925
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.2001466415
Short name T1576
Test name
Test status
Simulation time 23320736286 ps
CPU time 25.81 seconds
Started Jun 27 06:39:43 PM PDT 24
Finished Jun 27 06:40:20 PM PDT 24
Peak memory 206320 kb
Host smart-71146e11-78fd-4c00-8792-f156b1daf925
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2001466415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.2001466415
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.3247511419
Short name T1067
Test name
Test status
Simulation time 151807842 ps
CPU time 0.79 seconds
Started Jun 27 06:39:41 PM PDT 24
Finished Jun 27 06:39:52 PM PDT 24
Peak memory 206272 kb
Host smart-33bfc431-6e6a-4122-9faa-6b294bb6433f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32475
11419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.3247511419
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.2299268416
Short name T2578
Test name
Test status
Simulation time 168621223 ps
CPU time 0.74 seconds
Started Jun 27 06:39:41 PM PDT 24
Finished Jun 27 06:39:52 PM PDT 24
Peak memory 206272 kb
Host smart-496d9a77-68f2-4f79-9856-7cedf27631a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22992
68416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.2299268416
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.3653448439
Short name T2071
Test name
Test status
Simulation time 500228647 ps
CPU time 1.42 seconds
Started Jun 27 06:39:43 PM PDT 24
Finished Jun 27 06:39:54 PM PDT 24
Peak memory 206376 kb
Host smart-d868a457-4d51-420d-9a7b-cf63b7406b73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36534
48439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.3653448439
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.1954969668
Short name T2275
Test name
Test status
Simulation time 827898163 ps
CPU time 1.89 seconds
Started Jun 27 06:39:45 PM PDT 24
Finished Jun 27 06:39:57 PM PDT 24
Peak memory 206248 kb
Host smart-526682c1-8b86-4d9b-93e8-b742d32b33f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19549
69668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.1954969668
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.2971013389
Short name T1915
Test name
Test status
Simulation time 9459086709 ps
CPU time 17.97 seconds
Started Jun 27 06:39:43 PM PDT 24
Finished Jun 27 06:40:12 PM PDT 24
Peak memory 206420 kb
Host smart-6a6c64fa-6ac4-42b6-8cd8-b12f70fcf4f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29710
13389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.2971013389
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.974865410
Short name T2062
Test name
Test status
Simulation time 466925255 ps
CPU time 1.26 seconds
Started Jun 27 06:39:41 PM PDT 24
Finished Jun 27 06:39:53 PM PDT 24
Peak memory 206276 kb
Host smart-5bfea753-3f58-49d9-938a-bc1d6e021be8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97486
5410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.974865410
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.4117223536
Short name T2245
Test name
Test status
Simulation time 160413961 ps
CPU time 0.76 seconds
Started Jun 27 06:39:41 PM PDT 24
Finished Jun 27 06:39:53 PM PDT 24
Peak memory 206268 kb
Host smart-b76a2e31-2cb7-4fad-925d-195009eac06c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41172
23536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.4117223536
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.417217685
Short name T894
Test name
Test status
Simulation time 35779324 ps
CPU time 0.65 seconds
Started Jun 27 06:39:44 PM PDT 24
Finished Jun 27 06:39:55 PM PDT 24
Peak memory 206216 kb
Host smart-177301d9-829a-4059-b0fb-316d8b8829a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41721
7685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.417217685
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.3907458814
Short name T2568
Test name
Test status
Simulation time 901108836 ps
CPU time 2.2 seconds
Started Jun 27 06:39:44 PM PDT 24
Finished Jun 27 06:39:57 PM PDT 24
Peak memory 206384 kb
Host smart-2f176fed-c592-49e4-8490-38dea132b590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39074
58814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.3907458814
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.3623127971
Short name T2044
Test name
Test status
Simulation time 209560528 ps
CPU time 1.75 seconds
Started Jun 27 06:39:44 PM PDT 24
Finished Jun 27 06:39:56 PM PDT 24
Peak memory 206420 kb
Host smart-4c4e5257-9d71-4577-9947-fbd4046c70d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36231
27971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.3623127971
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.1352433729
Short name T820
Test name
Test status
Simulation time 185751452 ps
CPU time 0.79 seconds
Started Jun 27 06:39:42 PM PDT 24
Finished Jun 27 06:39:53 PM PDT 24
Peak memory 206264 kb
Host smart-199ac836-52ed-41bc-b497-1f7c5aec9a69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13524
33729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.1352433729
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.3813484542
Short name T1691
Test name
Test status
Simulation time 152278826 ps
CPU time 0.79 seconds
Started Jun 27 06:39:48 PM PDT 24
Finished Jun 27 06:39:58 PM PDT 24
Peak memory 206264 kb
Host smart-7ab64626-81ef-4b58-b290-c9c316c8ff7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38134
84542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.3813484542
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.1858344461
Short name T926
Test name
Test status
Simulation time 221185293 ps
CPU time 0.9 seconds
Started Jun 27 06:39:41 PM PDT 24
Finished Jun 27 06:39:53 PM PDT 24
Peak memory 206292 kb
Host smart-68720b21-e806-4540-a218-80845da1b86e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18583
44461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.1858344461
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.1715096572
Short name T2460
Test name
Test status
Simulation time 264436554 ps
CPU time 0.87 seconds
Started Jun 27 06:39:46 PM PDT 24
Finished Jun 27 06:39:57 PM PDT 24
Peak memory 206268 kb
Host smart-0fb54300-7328-4f47-9e5c-b9254a3785c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17150
96572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.1715096572
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.2135086291
Short name T389
Test name
Test status
Simulation time 23305247892 ps
CPU time 25.71 seconds
Started Jun 27 06:39:44 PM PDT 24
Finished Jun 27 06:40:20 PM PDT 24
Peak memory 206336 kb
Host smart-ee8244d4-0d7a-4aca-a551-518900d0221d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21350
86291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.2135086291
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.3176433637
Short name T2479
Test name
Test status
Simulation time 3291262236 ps
CPU time 3.68 seconds
Started Jun 27 06:39:44 PM PDT 24
Finished Jun 27 06:39:58 PM PDT 24
Peak memory 206328 kb
Host smart-beb10601-f10b-456e-94a5-0c8aafecd118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31764
33637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.3176433637
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.3430919842
Short name T978
Test name
Test status
Simulation time 10199797680 ps
CPU time 92.61 seconds
Started Jun 27 06:39:43 PM PDT 24
Finished Jun 27 06:41:27 PM PDT 24
Peak memory 206488 kb
Host smart-0de10d1f-8856-4ea2-ad2c-76549758c8c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34309
19842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.3430919842
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.3617429309
Short name T613
Test name
Test status
Simulation time 6567032292 ps
CPU time 47.89 seconds
Started Jun 27 06:39:46 PM PDT 24
Finished Jun 27 06:40:44 PM PDT 24
Peak memory 206488 kb
Host smart-bca675a2-f848-4631-bc40-7929003e6ddd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3617429309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.3617429309
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.3614885847
Short name T592
Test name
Test status
Simulation time 252494683 ps
CPU time 0.93 seconds
Started Jun 27 06:39:40 PM PDT 24
Finished Jun 27 06:39:53 PM PDT 24
Peak memory 206292 kb
Host smart-1f37ba8a-bfc0-47e0-8cca-d155d36506af
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3614885847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.3614885847
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.1061336402
Short name T2505
Test name
Test status
Simulation time 261954316 ps
CPU time 0.93 seconds
Started Jun 27 06:39:45 PM PDT 24
Finished Jun 27 06:39:56 PM PDT 24
Peak memory 206308 kb
Host smart-f78219e4-8e6a-468c-b44e-e2f1cfe90008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10613
36402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.1061336402
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.3501397151
Short name T2233
Test name
Test status
Simulation time 4720112785 ps
CPU time 132.57 seconds
Started Jun 27 06:39:42 PM PDT 24
Finished Jun 27 06:42:05 PM PDT 24
Peak memory 205884 kb
Host smart-1f940c2b-29e1-4ef4-8e23-3bd2a0b1b2f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35013
97151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.3501397151
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.2940587166
Short name T1219
Test name
Test status
Simulation time 4626712540 ps
CPU time 40.3 seconds
Started Jun 27 06:39:45 PM PDT 24
Finished Jun 27 06:40:36 PM PDT 24
Peak memory 206448 kb
Host smart-e7ea9283-f943-4fab-905c-1469cae78da9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2940587166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.2940587166
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.54957113
Short name T476
Test name
Test status
Simulation time 174168834 ps
CPU time 0.81 seconds
Started Jun 27 06:39:43 PM PDT 24
Finished Jun 27 06:39:55 PM PDT 24
Peak memory 206276 kb
Host smart-875cc2c5-418e-4015-8757-74c730e547de
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=54957113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.54957113
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.1283586729
Short name T1966
Test name
Test status
Simulation time 149602799 ps
CPU time 0.74 seconds
Started Jun 27 06:39:43 PM PDT 24
Finished Jun 27 06:39:54 PM PDT 24
Peak memory 206284 kb
Host smart-6b4c7ad7-6ceb-4d7a-9a1a-d9006bd03da6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12835
86729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.1283586729
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.783552380
Short name T138
Test name
Test status
Simulation time 180519414 ps
CPU time 0.81 seconds
Started Jun 27 06:39:45 PM PDT 24
Finished Jun 27 06:39:56 PM PDT 24
Peak memory 206148 kb
Host smart-9f4b9b9a-2a2b-4833-9ab5-cada7e015cc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78355
2380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.783552380
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.3622957748
Short name T645
Test name
Test status
Simulation time 183360870 ps
CPU time 0.86 seconds
Started Jun 27 06:39:45 PM PDT 24
Finished Jun 27 06:39:56 PM PDT 24
Peak memory 206304 kb
Host smart-e2d0d558-5f40-4e1e-9127-e6f6451ac757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36229
57748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.3622957748
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.1007520427
Short name T1102
Test name
Test status
Simulation time 161100021 ps
CPU time 0.77 seconds
Started Jun 27 06:39:44 PM PDT 24
Finished Jun 27 06:39:55 PM PDT 24
Peak memory 206280 kb
Host smart-b308a77b-f177-4bb6-8c4a-73256cb1730c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10075
20427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.1007520427
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.121601579
Short name T2421
Test name
Test status
Simulation time 196124006 ps
CPU time 0.81 seconds
Started Jun 27 06:39:47 PM PDT 24
Finished Jun 27 06:39:58 PM PDT 24
Peak memory 206272 kb
Host smart-3f7e6520-d401-46d4-82e1-e200962c4149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12160
1579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.121601579
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.1426596777
Short name T2189
Test name
Test status
Simulation time 169516317 ps
CPU time 0.81 seconds
Started Jun 27 06:39:44 PM PDT 24
Finished Jun 27 06:39:55 PM PDT 24
Peak memory 206276 kb
Host smart-9f2400ed-c6e3-422a-b55f-3658e3a27c7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14265
96777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.1426596777
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.2218007717
Short name T1458
Test name
Test status
Simulation time 235608318 ps
CPU time 1.1 seconds
Started Jun 27 06:39:47 PM PDT 24
Finished Jun 27 06:39:58 PM PDT 24
Peak memory 206256 kb
Host smart-61711229-857b-47e7-836a-9f98f67a221e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2218007717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.2218007717
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.867732759
Short name T869
Test name
Test status
Simulation time 166803515 ps
CPU time 0.78 seconds
Started Jun 27 06:39:43 PM PDT 24
Finished Jun 27 06:39:55 PM PDT 24
Peak memory 206280 kb
Host smart-86d20ac0-dfaa-49bb-bd12-2dcee8b06e30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86773
2759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.867732759
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.311141131
Short name T2591
Test name
Test status
Simulation time 30731614 ps
CPU time 0.62 seconds
Started Jun 27 06:39:44 PM PDT 24
Finished Jun 27 06:39:55 PM PDT 24
Peak memory 206248 kb
Host smart-6fba1f98-626f-4718-935c-23ccd6639fa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31114
1131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.311141131
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.1360682663
Short name T2252
Test name
Test status
Simulation time 15561718257 ps
CPU time 32.91 seconds
Started Jun 27 06:39:46 PM PDT 24
Finished Jun 27 06:40:29 PM PDT 24
Peak memory 206612 kb
Host smart-41a8ecf0-e5a8-4e9b-8538-2f1579c7299a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13606
82663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.1360682663
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.3221475456
Short name T1969
Test name
Test status
Simulation time 251730658 ps
CPU time 0.88 seconds
Started Jun 27 06:39:43 PM PDT 24
Finished Jun 27 06:39:54 PM PDT 24
Peak memory 206256 kb
Host smart-8c9ba210-d59d-425b-8f1d-e45a4278e0b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32214
75456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.3221475456
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.3987319964
Short name T1562
Test name
Test status
Simulation time 194574412 ps
CPU time 0.84 seconds
Started Jun 27 06:39:47 PM PDT 24
Finished Jun 27 06:39:58 PM PDT 24
Peak memory 206268 kb
Host smart-9ef28bf3-b652-4ed6-b745-76a28b57d3d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39873
19964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.3987319964
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.1191215395
Short name T2535
Test name
Test status
Simulation time 234532175 ps
CPU time 0.88 seconds
Started Jun 27 06:39:45 PM PDT 24
Finished Jun 27 06:39:56 PM PDT 24
Peak memory 206300 kb
Host smart-79115475-01d5-448f-add9-49366999645d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11912
15395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.1191215395
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.221960266
Short name T355
Test name
Test status
Simulation time 174904565 ps
CPU time 0.77 seconds
Started Jun 27 06:39:44 PM PDT 24
Finished Jun 27 06:39:55 PM PDT 24
Peak memory 206280 kb
Host smart-042d809a-50b7-44f8-bf0a-f1ceb00ebf99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22196
0266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.221960266
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.3303838419
Short name T1258
Test name
Test status
Simulation time 181777558 ps
CPU time 0.82 seconds
Started Jun 27 06:39:46 PM PDT 24
Finished Jun 27 06:39:57 PM PDT 24
Peak memory 206268 kb
Host smart-48aa5009-ac34-4ed5-aed8-a90e3302c641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33038
38419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.3303838419
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.2035144079
Short name T2225
Test name
Test status
Simulation time 150351087 ps
CPU time 0.78 seconds
Started Jun 27 06:39:46 PM PDT 24
Finished Jun 27 06:39:57 PM PDT 24
Peak memory 206268 kb
Host smart-bed7db5b-ed4f-437f-93bc-8980d23e105c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20351
44079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.2035144079
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.3188441990
Short name T811
Test name
Test status
Simulation time 193431216 ps
CPU time 0.81 seconds
Started Jun 27 06:39:45 PM PDT 24
Finished Jun 27 06:39:56 PM PDT 24
Peak memory 205780 kb
Host smart-c0639188-f046-44dc-b9d3-415e4db56b70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31884
41990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.3188441990
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.3947236291
Short name T753
Test name
Test status
Simulation time 239189610 ps
CPU time 0.88 seconds
Started Jun 27 06:39:44 PM PDT 24
Finished Jun 27 06:39:55 PM PDT 24
Peak memory 206224 kb
Host smart-4b9e3d62-2953-42d2-829d-b6a5832abceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39472
36291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.3947236291
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.2104109735
Short name T1885
Test name
Test status
Simulation time 5294366863 ps
CPU time 148.72 seconds
Started Jun 27 06:39:44 PM PDT 24
Finished Jun 27 06:42:23 PM PDT 24
Peak memory 206452 kb
Host smart-0b2ad734-205e-4e0d-adde-e45be7ea28fa
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2104109735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.2104109735
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.2153844664
Short name T893
Test name
Test status
Simulation time 229865519 ps
CPU time 0.88 seconds
Started Jun 27 06:39:45 PM PDT 24
Finished Jun 27 06:39:56 PM PDT 24
Peak memory 205592 kb
Host smart-7705a44d-ac04-4697-8550-4930aa867d90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21538
44664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.2153844664
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.1585769651
Short name T2549
Test name
Test status
Simulation time 153179841 ps
CPU time 0.76 seconds
Started Jun 27 06:39:43 PM PDT 24
Finished Jun 27 06:39:55 PM PDT 24
Peak memory 206272 kb
Host smart-d98da350-df7c-4ead-816a-5a02485e15f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15857
69651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.1585769651
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.3403056719
Short name T1400
Test name
Test status
Simulation time 5557480005 ps
CPU time 54.57 seconds
Started Jun 27 06:39:42 PM PDT 24
Finished Jun 27 06:40:47 PM PDT 24
Peak memory 205916 kb
Host smart-2eb64fbc-1766-4181-8c8a-b374b0a8daa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34030
56719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.3403056719
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.3632338058
Short name T1363
Test name
Test status
Simulation time 65955497 ps
CPU time 0.73 seconds
Started Jun 27 06:40:07 PM PDT 24
Finished Jun 27 06:40:11 PM PDT 24
Peak memory 206296 kb
Host smart-53b30205-00a2-4fc2-94af-2c161fbf4bed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3632338058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.3632338058
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.4279611827
Short name T544
Test name
Test status
Simulation time 4307759245 ps
CPU time 4.59 seconds
Started Jun 27 06:39:43 PM PDT 24
Finished Jun 27 06:39:59 PM PDT 24
Peak memory 206512 kb
Host smart-542a4e7f-0147-46ec-96f1-c0176bb496f9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4279611827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.4279611827
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.837924450
Short name T777
Test name
Test status
Simulation time 13349277070 ps
CPU time 12.34 seconds
Started Jun 27 06:39:45 PM PDT 24
Finished Jun 27 06:40:08 PM PDT 24
Peak memory 206444 kb
Host smart-036172cb-a04a-4bab-88ec-a6a4e2ec7ca3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=837924450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.837924450
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.2429844320
Short name T227
Test name
Test status
Simulation time 23350048933 ps
CPU time 21.75 seconds
Started Jun 27 06:39:48 PM PDT 24
Finished Jun 27 06:40:19 PM PDT 24
Peak memory 206436 kb
Host smart-9e77ad93-c4eb-46dd-b536-ae9d1c364a30
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2429844320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.2429844320
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.2187870367
Short name T1818
Test name
Test status
Simulation time 158687461 ps
CPU time 0.76 seconds
Started Jun 27 06:39:44 PM PDT 24
Finished Jun 27 06:39:55 PM PDT 24
Peak memory 206268 kb
Host smart-f149b6a2-9611-4376-be3d-e894568a8d22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21878
70367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.2187870367
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.558110249
Short name T1948
Test name
Test status
Simulation time 157613952 ps
CPU time 0.75 seconds
Started Jun 27 06:40:02 PM PDT 24
Finished Jun 27 06:40:06 PM PDT 24
Peak memory 206308 kb
Host smart-a6fbd38a-e5ff-410e-abc4-787238ac90cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55811
0249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.558110249
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.1609051216
Short name T1859
Test name
Test status
Simulation time 145149142 ps
CPU time 0.76 seconds
Started Jun 27 06:40:02 PM PDT 24
Finished Jun 27 06:40:06 PM PDT 24
Peak memory 206284 kb
Host smart-0edcd8dc-b375-43cf-befc-c881bd888768
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16090
51216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.1609051216
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.526883866
Short name T2172
Test name
Test status
Simulation time 1182015201 ps
CPU time 2.43 seconds
Started Jun 27 06:39:59 PM PDT 24
Finished Jun 27 06:40:05 PM PDT 24
Peak memory 206356 kb
Host smart-c12342fc-0701-4fbf-aea7-3239ba069dd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52688
3866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.526883866
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.2902602354
Short name T2020
Test name
Test status
Simulation time 18361569694 ps
CPU time 35.35 seconds
Started Jun 27 06:40:06 PM PDT 24
Finished Jun 27 06:40:46 PM PDT 24
Peak memory 206488 kb
Host smart-1c7784dd-e240-4fa1-a6c5-ebabafbe8fef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29026
02354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.2902602354
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.2438899102
Short name T633
Test name
Test status
Simulation time 500456880 ps
CPU time 1.44 seconds
Started Jun 27 06:40:05 PM PDT 24
Finished Jun 27 06:40:11 PM PDT 24
Peak memory 206272 kb
Host smart-d6ab16da-f04e-4560-aa53-b83b6d742183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24388
99102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.2438899102
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.544984746
Short name T40
Test name
Test status
Simulation time 147253887 ps
CPU time 0.81 seconds
Started Jun 27 06:40:07 PM PDT 24
Finished Jun 27 06:40:11 PM PDT 24
Peak memory 206280 kb
Host smart-796ce18c-e785-4ae3-afd8-3a66b38b80fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54498
4746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.544984746
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.2895947965
Short name T2222
Test name
Test status
Simulation time 38734605 ps
CPU time 0.7 seconds
Started Jun 27 06:40:02 PM PDT 24
Finished Jun 27 06:40:08 PM PDT 24
Peak memory 206424 kb
Host smart-4835bf56-cf12-4267-b981-5e41254d7ea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28959
47965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.2895947965
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.397706120
Short name T375
Test name
Test status
Simulation time 1004776060 ps
CPU time 2.53 seconds
Started Jun 27 06:40:02 PM PDT 24
Finished Jun 27 06:40:08 PM PDT 24
Peak memory 206412 kb
Host smart-b344ef5d-218d-4a1f-868e-e825a8c1a028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39770
6120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.397706120
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.2502311000
Short name T2078
Test name
Test status
Simulation time 203936815 ps
CPU time 1.46 seconds
Started Jun 27 06:39:59 PM PDT 24
Finished Jun 27 06:40:04 PM PDT 24
Peak memory 206416 kb
Host smart-3b7cbbc9-bc7e-4a18-b6d2-dff098a990a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25023
11000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.2502311000
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.3532703363
Short name T1571
Test name
Test status
Simulation time 248286334 ps
CPU time 0.98 seconds
Started Jun 27 06:40:04 PM PDT 24
Finished Jun 27 06:40:10 PM PDT 24
Peak memory 206292 kb
Host smart-7cc08f07-e893-4b92-9e8f-201b7715dc83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35327
03363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.3532703363
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.1188732817
Short name T874
Test name
Test status
Simulation time 154062920 ps
CPU time 0.76 seconds
Started Jun 27 06:40:01 PM PDT 24
Finished Jun 27 06:40:05 PM PDT 24
Peak memory 206292 kb
Host smart-3cb43a5e-e2c4-42d7-b001-2b26fbedd6c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11887
32817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.1188732817
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.4189785973
Short name T1759
Test name
Test status
Simulation time 196663853 ps
CPU time 0.88 seconds
Started Jun 27 06:40:02 PM PDT 24
Finished Jun 27 06:40:06 PM PDT 24
Peak memory 206296 kb
Host smart-641829c3-5d9e-427e-800e-78e05671aa8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41897
85973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.4189785973
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_invalid_sync.3500899159
Short name T73
Test name
Test status
Simulation time 5251929249 ps
CPU time 138.8 seconds
Started Jun 27 06:40:09 PM PDT 24
Finished Jun 27 06:42:31 PM PDT 24
Peak memory 206488 kb
Host smart-40965265-f36c-4651-b62f-01272e7a68e9
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3500899159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.3500899159
Directory /workspace/33.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.264981007
Short name T1661
Test name
Test status
Simulation time 228319824 ps
CPU time 0.86 seconds
Started Jun 27 06:40:02 PM PDT 24
Finished Jun 27 06:40:06 PM PDT 24
Peak memory 206244 kb
Host smart-117de6db-20b7-4106-9fc5-910a69042cbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26498
1007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.264981007
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.3031574214
Short name T1687
Test name
Test status
Simulation time 23368136182 ps
CPU time 22.9 seconds
Started Jun 27 06:40:02 PM PDT 24
Finished Jun 27 06:40:28 PM PDT 24
Peak memory 206112 kb
Host smart-be339654-8b3c-4f24-8bd8-7feef2a0be39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30315
74214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.3031574214
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.2536703548
Short name T1788
Test name
Test status
Simulation time 3346360113 ps
CPU time 4.45 seconds
Started Jun 27 06:40:05 PM PDT 24
Finished Jun 27 06:40:14 PM PDT 24
Peak memory 206332 kb
Host smart-a46da40a-0a58-457c-9458-f1de186b9980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25367
03548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.2536703548
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.1387842167
Short name T2598
Test name
Test status
Simulation time 9468381276 ps
CPU time 92.79 seconds
Started Jun 27 06:39:59 PM PDT 24
Finished Jun 27 06:41:35 PM PDT 24
Peak memory 206480 kb
Host smart-851c6d64-3267-4d7a-b7f1-4d98a7a4bb62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13878
42167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.1387842167
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.2573614812
Short name T1316
Test name
Test status
Simulation time 3878121962 ps
CPU time 35.19 seconds
Started Jun 27 06:40:04 PM PDT 24
Finished Jun 27 06:40:44 PM PDT 24
Peak memory 206404 kb
Host smart-7446f304-2a6f-4303-bacd-b0ad187619e0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2573614812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.2573614812
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.1382614786
Short name T948
Test name
Test status
Simulation time 254932459 ps
CPU time 0.86 seconds
Started Jun 27 06:40:02 PM PDT 24
Finished Jun 27 06:40:06 PM PDT 24
Peak memory 206304 kb
Host smart-d96f426e-3efb-4bc3-8f0c-32f0b66ff753
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1382614786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.1382614786
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.1811227939
Short name T1545
Test name
Test status
Simulation time 211373774 ps
CPU time 0.89 seconds
Started Jun 27 06:40:00 PM PDT 24
Finished Jun 27 06:40:04 PM PDT 24
Peak memory 206280 kb
Host smart-d160f74b-9ee7-4746-b4c5-aa441e544dba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18112
27939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.1811227939
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.606691617
Short name T1432
Test name
Test status
Simulation time 5923354474 ps
CPU time 153.93 seconds
Started Jun 27 06:40:09 PM PDT 24
Finished Jun 27 06:42:46 PM PDT 24
Peak memory 206464 kb
Host smart-c372de7a-3220-4c5f-96de-7643b068f6b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60669
1617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.606691617
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.885229025
Short name T2292
Test name
Test status
Simulation time 4983416435 ps
CPU time 45.87 seconds
Started Jun 27 06:40:03 PM PDT 24
Finished Jun 27 06:40:53 PM PDT 24
Peak memory 206408 kb
Host smart-a5c307d5-9914-4384-81fb-a2da1da68c14
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=885229025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.885229025
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.1106992606
Short name T2112
Test name
Test status
Simulation time 165102170 ps
CPU time 0.76 seconds
Started Jun 27 06:40:06 PM PDT 24
Finished Jun 27 06:40:10 PM PDT 24
Peak memory 206292 kb
Host smart-4f53a4de-cce0-4421-9ed3-f7c24a59f965
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1106992606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.1106992606
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.610284562
Short name T1986
Test name
Test status
Simulation time 166935169 ps
CPU time 0.78 seconds
Started Jun 27 06:40:04 PM PDT 24
Finished Jun 27 06:40:10 PM PDT 24
Peak memory 206284 kb
Host smart-3d4b5084-e978-4e6c-ae2b-00b95ea20fbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61028
4562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.610284562
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.2173517960
Short name T123
Test name
Test status
Simulation time 225111181 ps
CPU time 0.88 seconds
Started Jun 27 06:40:09 PM PDT 24
Finished Jun 27 06:40:13 PM PDT 24
Peak memory 206304 kb
Host smart-118193da-7746-45d1-9893-5b5f12b0b3ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21735
17960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.2173517960
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.1487554874
Short name T1059
Test name
Test status
Simulation time 230911256 ps
CPU time 0.8 seconds
Started Jun 27 06:40:09 PM PDT 24
Finished Jun 27 06:40:13 PM PDT 24
Peak memory 206312 kb
Host smart-73ba7e43-772e-4c93-9234-ec971ad5cfad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14875
54874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.1487554874
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.390122549
Short name T363
Test name
Test status
Simulation time 162043159 ps
CPU time 0.81 seconds
Started Jun 27 06:40:05 PM PDT 24
Finished Jun 27 06:40:10 PM PDT 24
Peak memory 206456 kb
Host smart-32f24ab4-ce8d-44e9-8f61-4eb8ac0c4fcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39012
2549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.390122549
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.1342080757
Short name T1750
Test name
Test status
Simulation time 205560370 ps
CPU time 0.86 seconds
Started Jun 27 06:40:02 PM PDT 24
Finished Jun 27 06:40:08 PM PDT 24
Peak memory 206244 kb
Host smart-46e78113-3e6d-4cfb-bc32-4a169015d25f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13420
80757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.1342080757
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.3417146486
Short name T1390
Test name
Test status
Simulation time 166289545 ps
CPU time 0.83 seconds
Started Jun 27 06:40:03 PM PDT 24
Finished Jun 27 06:40:08 PM PDT 24
Peak memory 206280 kb
Host smart-bd2931fb-68c8-4fbb-bf41-75bdc85c6930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34171
46486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.3417146486
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.2885313393
Short name T2489
Test name
Test status
Simulation time 248871270 ps
CPU time 0.96 seconds
Started Jun 27 06:40:03 PM PDT 24
Finished Jun 27 06:40:08 PM PDT 24
Peak memory 206212 kb
Host smart-e3ff3f40-8652-4e12-ad24-5e445c36eb5b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2885313393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.2885313393
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.3576117069
Short name T975
Test name
Test status
Simulation time 150298726 ps
CPU time 0.76 seconds
Started Jun 27 06:40:05 PM PDT 24
Finished Jun 27 06:40:10 PM PDT 24
Peak memory 206460 kb
Host smart-f70ca981-ef76-42aa-bace-89ef8aa439c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35761
17069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.3576117069
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.2001742632
Short name T726
Test name
Test status
Simulation time 56104663 ps
CPU time 0.69 seconds
Started Jun 27 06:40:02 PM PDT 24
Finished Jun 27 06:40:07 PM PDT 24
Peak memory 206264 kb
Host smart-3a8d6a31-5b2d-4703-a653-d4eef3e65102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20017
42632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.2001742632
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.3503353476
Short name T255
Test name
Test status
Simulation time 17518356101 ps
CPU time 34.53 seconds
Started Jun 27 06:40:05 PM PDT 24
Finished Jun 27 06:40:44 PM PDT 24
Peak memory 206524 kb
Host smart-f383f3a7-aee8-4427-b702-e40c44a1571e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35033
53476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.3503353476
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.996428583
Short name T910
Test name
Test status
Simulation time 168996192 ps
CPU time 0.88 seconds
Started Jun 27 06:40:05 PM PDT 24
Finished Jun 27 06:40:10 PM PDT 24
Peak memory 206448 kb
Host smart-e5575dce-ee30-4cff-b77a-76f6575284ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99642
8583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.996428583
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.4160116863
Short name T990
Test name
Test status
Simulation time 198772473 ps
CPU time 0.92 seconds
Started Jun 27 06:40:03 PM PDT 24
Finished Jun 27 06:40:08 PM PDT 24
Peak memory 206264 kb
Host smart-73b214f0-067e-4a62-9126-abd0315722fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41601
16863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.4160116863
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.452554080
Short name T2216
Test name
Test status
Simulation time 218328618 ps
CPU time 0.92 seconds
Started Jun 27 06:40:07 PM PDT 24
Finished Jun 27 06:40:12 PM PDT 24
Peak memory 206296 kb
Host smart-afc567ce-e780-4250-ba9a-2347c1baf826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45255
4080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.452554080
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.1439822494
Short name T2347
Test name
Test status
Simulation time 193384706 ps
CPU time 0.82 seconds
Started Jun 27 06:39:59 PM PDT 24
Finished Jun 27 06:40:03 PM PDT 24
Peak memory 206264 kb
Host smart-d345d8f0-b9c8-4e3c-baf6-aca87c3eda90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14398
22494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.1439822494
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.168018034
Short name T2517
Test name
Test status
Simulation time 159377775 ps
CPU time 0.8 seconds
Started Jun 27 06:40:00 PM PDT 24
Finished Jun 27 06:40:04 PM PDT 24
Peak memory 206276 kb
Host smart-71a17874-5949-4897-86bc-479e6063a808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16801
8034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.168018034
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.3519188654
Short name T2417
Test name
Test status
Simulation time 157592871 ps
CPU time 0.82 seconds
Started Jun 27 06:40:04 PM PDT 24
Finished Jun 27 06:40:09 PM PDT 24
Peak memory 206432 kb
Host smart-c4a4316e-541c-4c20-b539-d2a8fc16ebd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35191
88654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.3519188654
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.3428156144
Short name T2387
Test name
Test status
Simulation time 155324712 ps
CPU time 0.76 seconds
Started Jun 27 06:40:09 PM PDT 24
Finished Jun 27 06:40:13 PM PDT 24
Peak memory 206312 kb
Host smart-2460eaae-d13e-454a-a642-c778c7742600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34281
56144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.3428156144
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.2730180032
Short name T323
Test name
Test status
Simulation time 308376925 ps
CPU time 0.98 seconds
Started Jun 27 06:40:01 PM PDT 24
Finished Jun 27 06:40:05 PM PDT 24
Peak memory 206272 kb
Host smart-af48b946-0a93-4ada-a4ea-0434697b0c49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27301
80032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.2730180032
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.1360270259
Short name T1272
Test name
Test status
Simulation time 3405807890 ps
CPU time 32.4 seconds
Started Jun 27 06:40:04 PM PDT 24
Finished Jun 27 06:40:41 PM PDT 24
Peak memory 206424 kb
Host smart-bc461bf7-0d47-433b-a9dc-5b815d3a61ba
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1360270259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.1360270259
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.2374487732
Short name T2499
Test name
Test status
Simulation time 168737370 ps
CPU time 0.87 seconds
Started Jun 27 06:40:02 PM PDT 24
Finished Jun 27 06:40:06 PM PDT 24
Peak memory 206040 kb
Host smart-b766f56d-df8a-40d6-ab73-801047b15ba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23744
87732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.2374487732
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.1439095840
Short name T2617
Test name
Test status
Simulation time 159404038 ps
CPU time 0.8 seconds
Started Jun 27 06:40:01 PM PDT 24
Finished Jun 27 06:40:05 PM PDT 24
Peak memory 206220 kb
Host smart-616b85e3-3751-4403-8965-43112d98a876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14390
95840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.1439095840
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.614328867
Short name T2492
Test name
Test status
Simulation time 4327526532 ps
CPU time 30.92 seconds
Started Jun 27 06:40:01 PM PDT 24
Finished Jun 27 06:40:35 PM PDT 24
Peak memory 206432 kb
Host smart-3cdce8aa-830a-4ae7-affd-67f13c6ec525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61432
8867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.614328867
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.3685270062
Short name T1951
Test name
Test status
Simulation time 55616074 ps
CPU time 0.69 seconds
Started Jun 27 06:40:34 PM PDT 24
Finished Jun 27 06:40:47 PM PDT 24
Peak memory 206356 kb
Host smart-2189f20e-2bb1-4fd8-90c5-bcaf73250a50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3685270062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.3685270062
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.909594684
Short name T9
Test name
Test status
Simulation time 4298079486 ps
CPU time 4.96 seconds
Started Jun 27 06:40:00 PM PDT 24
Finished Jun 27 06:40:08 PM PDT 24
Peak memory 206508 kb
Host smart-a4d73a85-4e17-404b-8bc1-717c00b7394f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=909594684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.909594684
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.431828152
Short name T2501
Test name
Test status
Simulation time 13338000247 ps
CPU time 13.53 seconds
Started Jun 27 06:40:01 PM PDT 24
Finished Jun 27 06:40:18 PM PDT 24
Peak memory 206340 kb
Host smart-d88a4998-fe2f-4ce1-95cd-a6beb69774db
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=431828152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.431828152
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.858009910
Short name T652
Test name
Test status
Simulation time 23481922067 ps
CPU time 23.98 seconds
Started Jun 27 06:40:01 PM PDT 24
Finished Jun 27 06:40:28 PM PDT 24
Peak memory 206432 kb
Host smart-5f775baf-292e-4105-b7b7-5bd9d0e73afb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=858009910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.858009910
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.1934505945
Short name T517
Test name
Test status
Simulation time 151673372 ps
CPU time 0.79 seconds
Started Jun 27 06:40:03 PM PDT 24
Finished Jun 27 06:40:09 PM PDT 24
Peak memory 206252 kb
Host smart-224fdf39-2747-48b0-88ba-1e441f236a46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19345
05945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.1934505945
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.4264907887
Short name T1667
Test name
Test status
Simulation time 184888061 ps
CPU time 0.87 seconds
Started Jun 27 06:40:03 PM PDT 24
Finished Jun 27 06:40:08 PM PDT 24
Peak memory 206216 kb
Host smart-c12a1e8c-f608-4c3b-a826-8837e78fcde5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42649
07887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.4264907887
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.145315030
Short name T176
Test name
Test status
Simulation time 404896924 ps
CPU time 1.37 seconds
Started Jun 27 06:40:03 PM PDT 24
Finished Jun 27 06:40:09 PM PDT 24
Peak memory 206244 kb
Host smart-cf3bd11b-a298-4d4f-989e-b63221d6eaf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14531
5030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.145315030
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.3116105567
Short name T1135
Test name
Test status
Simulation time 576699864 ps
CPU time 1.61 seconds
Started Jun 27 06:40:04 PM PDT 24
Finished Jun 27 06:40:11 PM PDT 24
Peak memory 206284 kb
Host smart-c2b92b0b-0f1e-477a-bcb9-b24cfe96ab36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31161
05567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.3116105567
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.1790308463
Short name T918
Test name
Test status
Simulation time 13667545416 ps
CPU time 25.83 seconds
Started Jun 27 06:40:03 PM PDT 24
Finished Jun 27 06:40:33 PM PDT 24
Peak memory 206416 kb
Host smart-6aaaa435-5b68-4b90-a075-78b7432b8616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17903
08463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.1790308463
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.3024570601
Short name T1961
Test name
Test status
Simulation time 391665618 ps
CPU time 1.26 seconds
Started Jun 27 06:40:01 PM PDT 24
Finished Jun 27 06:40:06 PM PDT 24
Peak memory 206252 kb
Host smart-2e985217-d7b4-41e2-a33c-701c27a68466
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30245
70601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.3024570601
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.2523438770
Short name T957
Test name
Test status
Simulation time 153293314 ps
CPU time 0.76 seconds
Started Jun 27 06:40:01 PM PDT 24
Finished Jun 27 06:40:04 PM PDT 24
Peak memory 206216 kb
Host smart-7cf9a55b-855c-4fc8-ab57-87dd569c1030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25234
38770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.2523438770
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.875523843
Short name T234
Test name
Test status
Simulation time 58124453 ps
CPU time 0.69 seconds
Started Jun 27 06:40:02 PM PDT 24
Finished Jun 27 06:40:07 PM PDT 24
Peak memory 206280 kb
Host smart-92788c99-0a37-400e-a8b1-d19b4b1619f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87552
3843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.875523843
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.315672768
Short name T29
Test name
Test status
Simulation time 815301420 ps
CPU time 1.83 seconds
Started Jun 27 06:40:01 PM PDT 24
Finished Jun 27 06:40:06 PM PDT 24
Peak memory 206372 kb
Host smart-750e625d-5fa0-486d-be58-dad9ce50f08d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31567
2768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.315672768
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.800376613
Short name T561
Test name
Test status
Simulation time 177297763 ps
CPU time 1.63 seconds
Started Jun 27 06:40:04 PM PDT 24
Finished Jun 27 06:40:10 PM PDT 24
Peak memory 206324 kb
Host smart-0dcc95ee-6c26-4438-9de4-f8a5dd98419c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80037
6613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.800376613
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.3816178711
Short name T2039
Test name
Test status
Simulation time 205879943 ps
CPU time 0.79 seconds
Started Jun 27 06:40:01 PM PDT 24
Finished Jun 27 06:40:06 PM PDT 24
Peak memory 206296 kb
Host smart-9c69b6c8-c32e-49dc-833c-a524cc75761d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38161
78711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.3816178711
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.2364034063
Short name T806
Test name
Test status
Simulation time 135957353 ps
CPU time 0.77 seconds
Started Jun 27 06:40:06 PM PDT 24
Finished Jun 27 06:40:11 PM PDT 24
Peak memory 206288 kb
Host smart-6545ba6a-3090-4bc7-aa5e-972a38dc1232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23640
34063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.2364034063
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.2275512842
Short name T651
Test name
Test status
Simulation time 214020519 ps
CPU time 0.9 seconds
Started Jun 27 06:40:04 PM PDT 24
Finished Jun 27 06:40:09 PM PDT 24
Peak memory 206264 kb
Host smart-bc7290e6-ab47-4298-b541-39689dd5ff90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22755
12842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.2275512842
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_invalid_sync.4078372287
Short name T221
Test name
Test status
Simulation time 6878552930 ps
CPU time 175.4 seconds
Started Jun 27 06:40:04 PM PDT 24
Finished Jun 27 06:43:04 PM PDT 24
Peak memory 206464 kb
Host smart-e1893c2a-bc74-4fb3-8e52-979f67c63c3b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4078372287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.4078372287
Directory /workspace/34.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.1380586756
Short name T563
Test name
Test status
Simulation time 226102242 ps
CPU time 0.83 seconds
Started Jun 27 06:40:08 PM PDT 24
Finished Jun 27 06:40:12 PM PDT 24
Peak memory 206300 kb
Host smart-d5c324ff-f871-40c8-ab4d-f29ab7b8da5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13805
86756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.1380586756
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.3637766173
Short name T1460
Test name
Test status
Simulation time 23325644395 ps
CPU time 22.61 seconds
Started Jun 27 06:40:03 PM PDT 24
Finished Jun 27 06:40:30 PM PDT 24
Peak memory 206284 kb
Host smart-0a233179-45e2-4a6c-b96b-0e317272e006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36377
66173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.3637766173
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.1605172564
Short name T1627
Test name
Test status
Simulation time 3344249069 ps
CPU time 4.1 seconds
Started Jun 27 06:40:07 PM PDT 24
Finished Jun 27 06:40:15 PM PDT 24
Peak memory 206340 kb
Host smart-865ff38c-75cf-49f2-9eea-f8a7ea3cd8a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16051
72564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.1605172564
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.3511844353
Short name T604
Test name
Test status
Simulation time 12452653509 ps
CPU time 338.7 seconds
Started Jun 27 06:40:05 PM PDT 24
Finished Jun 27 06:45:48 PM PDT 24
Peak memory 206488 kb
Host smart-9835d86a-219f-46ff-8711-201c20cbf674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35118
44353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.3511844353
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.3238379044
Short name T431
Test name
Test status
Simulation time 5004210732 ps
CPU time 134.23 seconds
Started Jun 27 06:40:03 PM PDT 24
Finished Jun 27 06:42:21 PM PDT 24
Peak memory 206444 kb
Host smart-d6876a98-5baa-4f45-97d1-ed9c59872460
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3238379044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.3238379044
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.1398598082
Short name T2273
Test name
Test status
Simulation time 257415093 ps
CPU time 0.9 seconds
Started Jun 27 06:40:01 PM PDT 24
Finished Jun 27 06:40:05 PM PDT 24
Peak memory 206300 kb
Host smart-e8a75c77-2beb-4d4b-86e0-aecf7c178d0b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1398598082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.1398598082
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.2323388950
Short name T751
Test name
Test status
Simulation time 233205373 ps
CPU time 0.87 seconds
Started Jun 27 06:40:09 PM PDT 24
Finished Jun 27 06:40:13 PM PDT 24
Peak memory 206300 kb
Host smart-8ca53d9c-54fd-4a87-bc20-94c4b81e4dfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23233
88950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.2323388950
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.1760636741
Short name T611
Test name
Test status
Simulation time 4683009418 ps
CPU time 128.07 seconds
Started Jun 27 06:39:59 PM PDT 24
Finished Jun 27 06:42:10 PM PDT 24
Peak memory 206444 kb
Host smart-09dadb28-c8d3-4ace-ae5d-7c3515c8c372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17606
36741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.1760636741
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.872291017
Short name T1945
Test name
Test status
Simulation time 5411821473 ps
CPU time 49.58 seconds
Started Jun 27 06:40:05 PM PDT 24
Finished Jun 27 06:40:59 PM PDT 24
Peak memory 206488 kb
Host smart-b51eaf95-9565-4e51-8536-bcd15e6ca137
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=872291017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.872291017
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.685850044
Short name T2450
Test name
Test status
Simulation time 147073921 ps
CPU time 0.77 seconds
Started Jun 27 06:40:08 PM PDT 24
Finished Jun 27 06:40:12 PM PDT 24
Peak memory 206316 kb
Host smart-d52729c6-1598-4db1-b0de-c30f76cc457a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=685850044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.685850044
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.3677962143
Short name T1348
Test name
Test status
Simulation time 173166647 ps
CPU time 0.77 seconds
Started Jun 27 06:40:02 PM PDT 24
Finished Jun 27 06:40:08 PM PDT 24
Peak memory 206228 kb
Host smart-312406b2-8694-4993-a0bc-3859f38ea354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36779
62143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.3677962143
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.4284494766
Short name T2476
Test name
Test status
Simulation time 199571868 ps
CPU time 0.85 seconds
Started Jun 27 06:40:06 PM PDT 24
Finished Jun 27 06:40:10 PM PDT 24
Peak memory 206276 kb
Host smart-e96af439-871b-44e0-853f-3102586dc3d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42844
94766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.4284494766
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.389579511
Short name T24
Test name
Test status
Simulation time 202392529 ps
CPU time 0.9 seconds
Started Jun 27 06:40:09 PM PDT 24
Finished Jun 27 06:40:13 PM PDT 24
Peak memory 206312 kb
Host smart-7a9da866-47c7-4ea8-8371-4a9e4e327dfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38957
9511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.389579511
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.1724867036
Short name T340
Test name
Test status
Simulation time 193942021 ps
CPU time 0.78 seconds
Started Jun 27 06:40:03 PM PDT 24
Finished Jun 27 06:40:08 PM PDT 24
Peak memory 206228 kb
Host smart-a3d94bc7-cc5b-4606-9cb3-6ed2d8e92f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17248
67036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.1724867036
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.2135088052
Short name T2386
Test name
Test status
Simulation time 208717280 ps
CPU time 0.82 seconds
Started Jun 27 06:40:09 PM PDT 24
Finished Jun 27 06:40:13 PM PDT 24
Peak memory 206300 kb
Host smart-74f02aca-e443-4ce8-872d-dcf90a0ae2c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21350
88052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.2135088052
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.2847420847
Short name T1087
Test name
Test status
Simulation time 157665561 ps
CPU time 0.82 seconds
Started Jun 27 06:40:10 PM PDT 24
Finished Jun 27 06:40:13 PM PDT 24
Peak memory 206296 kb
Host smart-6ab320e0-e5f0-4860-82a5-4477eab2b000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28474
20847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.2847420847
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.1556703065
Short name T1444
Test name
Test status
Simulation time 211919831 ps
CPU time 0.88 seconds
Started Jun 27 06:40:34 PM PDT 24
Finished Jun 27 06:40:46 PM PDT 24
Peak memory 206280 kb
Host smart-52b8d4e7-ef50-4436-870a-b963cdf19240
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1556703065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.1556703065
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.3806364474
Short name T38
Test name
Test status
Simulation time 156365512 ps
CPU time 0.81 seconds
Started Jun 27 06:40:44 PM PDT 24
Finished Jun 27 06:41:20 PM PDT 24
Peak memory 206252 kb
Host smart-1cab80af-571a-4757-88a4-1e3950fa4e3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38063
64474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.3806364474
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.2519349915
Short name T2558
Test name
Test status
Simulation time 46338962 ps
CPU time 0.66 seconds
Started Jun 27 06:40:33 PM PDT 24
Finished Jun 27 06:40:45 PM PDT 24
Peak memory 206252 kb
Host smart-339c2a5e-565d-42b5-8279-325f39abc710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25193
49915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.2519349915
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.839549814
Short name T1214
Test name
Test status
Simulation time 7915769389 ps
CPU time 17.16 seconds
Started Jun 27 06:40:35 PM PDT 24
Finished Jun 27 06:41:07 PM PDT 24
Peak memory 206296 kb
Host smart-1be9138a-e66f-46d1-9f8d-a9b8a4d3dc09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83954
9814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.839549814
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.2948591598
Short name T1462
Test name
Test status
Simulation time 183293679 ps
CPU time 0.84 seconds
Started Jun 27 06:40:36 PM PDT 24
Finished Jun 27 06:40:53 PM PDT 24
Peak memory 206276 kb
Host smart-8967a56d-e841-40a0-867a-034f5fca2591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29485
91598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.2948591598
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.2485648175
Short name T1480
Test name
Test status
Simulation time 207913216 ps
CPU time 0.91 seconds
Started Jun 27 06:40:35 PM PDT 24
Finished Jun 27 06:40:51 PM PDT 24
Peak memory 206288 kb
Host smart-054c5edb-4884-45b1-89f3-ee7e3ed1e257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24856
48175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.2485648175
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.2633281299
Short name T1913
Test name
Test status
Simulation time 192046028 ps
CPU time 0.8 seconds
Started Jun 27 06:40:36 PM PDT 24
Finished Jun 27 06:40:53 PM PDT 24
Peak memory 206296 kb
Host smart-8e8cb173-0d53-444f-9a82-7ea0e0c02b30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26332
81299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.2633281299
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.2885196016
Short name T1252
Test name
Test status
Simulation time 146190750 ps
CPU time 0.82 seconds
Started Jun 27 06:40:35 PM PDT 24
Finished Jun 27 06:40:51 PM PDT 24
Peak memory 206272 kb
Host smart-2f435232-9c82-4383-b196-956d22a2df1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28851
96016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.2885196016
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.1691761286
Short name T74
Test name
Test status
Simulation time 143157169 ps
CPU time 0.77 seconds
Started Jun 27 06:40:33 PM PDT 24
Finished Jun 27 06:40:44 PM PDT 24
Peak memory 205952 kb
Host smart-de6ee309-5c53-4691-9f60-3281f5370204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16917
61286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.1691761286
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.1679277057
Short name T2022
Test name
Test status
Simulation time 157491904 ps
CPU time 0.77 seconds
Started Jun 27 06:40:33 PM PDT 24
Finished Jun 27 06:40:46 PM PDT 24
Peak memory 206220 kb
Host smart-5b4c946e-4515-4c86-825b-34bb6abcda84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16792
77057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.1679277057
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.27143343
Short name T1727
Test name
Test status
Simulation time 144144566 ps
CPU time 0.75 seconds
Started Jun 27 06:40:35 PM PDT 24
Finished Jun 27 06:40:51 PM PDT 24
Peak memory 206280 kb
Host smart-ceee0ce9-4b34-43d4-af59-900406eb68a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27143
343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.27143343
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.188039867
Short name T684
Test name
Test status
Simulation time 253688600 ps
CPU time 0.95 seconds
Started Jun 27 06:40:33 PM PDT 24
Finished Jun 27 06:40:44 PM PDT 24
Peak memory 206228 kb
Host smart-b4832f62-db2a-4a6e-baf9-f582b41e6c21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18803
9867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.188039867
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.331008461
Short name T1698
Test name
Test status
Simulation time 3875923589 ps
CPU time 26.72 seconds
Started Jun 27 06:40:34 PM PDT 24
Finished Jun 27 06:41:13 PM PDT 24
Peak memory 206408 kb
Host smart-e3a6e486-1826-4a7f-bf5e-b9f4c45d8f9e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=331008461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.331008461
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.3901262452
Short name T2612
Test name
Test status
Simulation time 187740840 ps
CPU time 0.81 seconds
Started Jun 27 06:40:33 PM PDT 24
Finished Jun 27 06:40:44 PM PDT 24
Peak memory 206276 kb
Host smart-20093a49-d462-4355-a05f-182473e05a7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39012
62452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.3901262452
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.3805630946
Short name T648
Test name
Test status
Simulation time 174055137 ps
CPU time 0.78 seconds
Started Jun 27 06:40:35 PM PDT 24
Finished Jun 27 06:40:51 PM PDT 24
Peak memory 206256 kb
Host smart-28dc8164-31a9-4bfa-b957-d3c5891b0883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38056
30946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.3805630946
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.1474081830
Short name T1398
Test name
Test status
Simulation time 6788577276 ps
CPU time 185.6 seconds
Started Jun 27 06:40:35 PM PDT 24
Finished Jun 27 06:43:56 PM PDT 24
Peak memory 206412 kb
Host smart-7b8ad108-27c6-474f-b7bc-03cec8454a9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14740
81830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.1474081830
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.3112121916
Short name T634
Test name
Test status
Simulation time 52848370 ps
CPU time 0.67 seconds
Started Jun 27 06:40:44 PM PDT 24
Finished Jun 27 06:41:20 PM PDT 24
Peak memory 206360 kb
Host smart-d2e93841-5f3c-46aa-aba6-d0bcc5a5f85b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3112121916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.3112121916
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.2492098261
Short name T1048
Test name
Test status
Simulation time 3879108244 ps
CPU time 4.24 seconds
Started Jun 27 06:40:44 PM PDT 24
Finished Jun 27 06:41:23 PM PDT 24
Peak memory 206440 kb
Host smart-e0c54383-9583-4286-bcd1-d8a6f511ede1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2492098261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.2492098261
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.3755486442
Short name T1080
Test name
Test status
Simulation time 13366600613 ps
CPU time 12.87 seconds
Started Jun 27 06:40:36 PM PDT 24
Finished Jun 27 06:41:05 PM PDT 24
Peak memory 206284 kb
Host smart-1ad17e2e-ca68-4b6e-a8d3-fdff03c0b25a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3755486442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.3755486442
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.1724023327
Short name T1382
Test name
Test status
Simulation time 23326089970 ps
CPU time 21.59 seconds
Started Jun 27 06:40:34 PM PDT 24
Finished Jun 27 06:41:08 PM PDT 24
Peak memory 206476 kb
Host smart-ac593fa1-79a4-4c8f-857c-718c040c5545
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1724023327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.1724023327
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.58012439
Short name T933
Test name
Test status
Simulation time 169275299 ps
CPU time 0.81 seconds
Started Jun 27 06:40:31 PM PDT 24
Finished Jun 27 06:40:41 PM PDT 24
Peak memory 206448 kb
Host smart-4d59c2c4-ca0d-4923-a254-b4479de2cc00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58012
439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.58012439
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.2306785791
Short name T2360
Test name
Test status
Simulation time 139943346 ps
CPU time 0.72 seconds
Started Jun 27 06:40:35 PM PDT 24
Finished Jun 27 06:40:51 PM PDT 24
Peak memory 206220 kb
Host smart-6cdefe06-98d0-4e40-96ce-0c8f8383bcce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23067
85791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.2306785791
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.3815761563
Short name T1768
Test name
Test status
Simulation time 779682264 ps
CPU time 1.78 seconds
Started Jun 27 06:40:33 PM PDT 24
Finished Jun 27 06:40:45 PM PDT 24
Peak memory 206408 kb
Host smart-35763e0d-7adb-471f-8074-d3c4bdff4eef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38157
61563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.3815761563
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.1557027897
Short name T1783
Test name
Test status
Simulation time 15101651183 ps
CPU time 29.97 seconds
Started Jun 27 06:40:33 PM PDT 24
Finished Jun 27 06:41:13 PM PDT 24
Peak memory 206492 kb
Host smart-de13f057-bf81-4ad0-8f9a-bf0763a034ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15570
27897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.1557027897
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.199873465
Short name T1971
Test name
Test status
Simulation time 445936158 ps
CPU time 1.32 seconds
Started Jun 27 06:40:36 PM PDT 24
Finished Jun 27 06:40:53 PM PDT 24
Peak memory 206244 kb
Host smart-e70a125e-148b-426b-96c4-0554c668ecfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19987
3465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.199873465
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.2967620367
Short name T1379
Test name
Test status
Simulation time 148567315 ps
CPU time 0.77 seconds
Started Jun 27 06:40:33 PM PDT 24
Finished Jun 27 06:40:44 PM PDT 24
Peak memory 206204 kb
Host smart-cfa6a7d1-2938-4382-a8eb-88d3b4ab2f6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29676
20367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.2967620367
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.3916411195
Short name T1937
Test name
Test status
Simulation time 32715530 ps
CPU time 0.63 seconds
Started Jun 27 06:40:38 PM PDT 24
Finished Jun 27 06:40:58 PM PDT 24
Peak memory 206280 kb
Host smart-dcae3f85-45cf-4de1-9623-98251f5e32a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39164
11195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.3916411195
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.269556400
Short name T1700
Test name
Test status
Simulation time 853831522 ps
CPU time 2 seconds
Started Jun 27 06:40:31 PM PDT 24
Finished Jun 27 06:40:43 PM PDT 24
Peak memory 206396 kb
Host smart-a7c08563-28a8-4600-8356-9a3ae2da93ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26955
6400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.269556400
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.1979425433
Short name T821
Test name
Test status
Simulation time 347554650 ps
CPU time 2.06 seconds
Started Jun 27 06:40:34 PM PDT 24
Finished Jun 27 06:40:47 PM PDT 24
Peak memory 206388 kb
Host smart-9dfd6fc0-df1c-43a6-817e-63167867d797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19794
25433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.1979425433
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.2069824951
Short name T2306
Test name
Test status
Simulation time 205391148 ps
CPU time 0.89 seconds
Started Jun 27 06:40:32 PM PDT 24
Finished Jun 27 06:40:44 PM PDT 24
Peak memory 206296 kb
Host smart-34883121-1d58-42a5-9a7b-2046b564c515
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20698
24951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.2069824951
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.229668734
Short name T610
Test name
Test status
Simulation time 144534726 ps
CPU time 0.74 seconds
Started Jun 27 06:40:34 PM PDT 24
Finished Jun 27 06:40:46 PM PDT 24
Peak memory 206220 kb
Host smart-e65d0a4b-8cb6-4e07-824a-b4551a379d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22966
8734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.229668734
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.2000738643
Short name T2327
Test name
Test status
Simulation time 184662386 ps
CPU time 0.9 seconds
Started Jun 27 06:40:36 PM PDT 24
Finished Jun 27 06:40:53 PM PDT 24
Peak memory 206292 kb
Host smart-7509f31e-00cd-4062-bc7c-6b2ba01915ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20007
38643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.2000738643
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_invalid_sync.1360933829
Short name T855
Test name
Test status
Simulation time 6990540946 ps
CPU time 45.48 seconds
Started Jun 27 06:40:39 PM PDT 24
Finished Jun 27 06:41:46 PM PDT 24
Peak memory 206424 kb
Host smart-7662e49d-32b2-4db4-ab01-7889a55a21f0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1360933829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.1360933829
Directory /workspace/35.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.3587780579
Short name T1226
Test name
Test status
Simulation time 235224286 ps
CPU time 0.87 seconds
Started Jun 27 06:40:34 PM PDT 24
Finished Jun 27 06:40:46 PM PDT 24
Peak memory 206268 kb
Host smart-df3ceca0-45cf-433e-8dfa-4de12e6b892b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35877
80579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.3587780579
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.207524002
Short name T444
Test name
Test status
Simulation time 23293598008 ps
CPU time 22.34 seconds
Started Jun 27 06:40:38 PM PDT 24
Finished Jun 27 06:41:20 PM PDT 24
Peak memory 206360 kb
Host smart-dd8ac9d7-360c-453d-8406-50d02fcbbff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20752
4002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.207524002
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.1267405053
Short name T1939
Test name
Test status
Simulation time 3280935986 ps
CPU time 3.56 seconds
Started Jun 27 06:40:31 PM PDT 24
Finished Jun 27 06:40:44 PM PDT 24
Peak memory 206336 kb
Host smart-fe9d9f63-35d2-4e6d-824e-52f1473a49eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12674
05053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.1267405053
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.1070145083
Short name T1175
Test name
Test status
Simulation time 14172256075 ps
CPU time 97.06 seconds
Started Jun 27 06:40:33 PM PDT 24
Finished Jun 27 06:42:22 PM PDT 24
Peak memory 206504 kb
Host smart-cbd3036a-7985-439a-bb2e-27bd00fb3e1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10701
45083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.1070145083
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.2627421772
Short name T1688
Test name
Test status
Simulation time 4691897885 ps
CPU time 36.05 seconds
Started Jun 27 06:40:34 PM PDT 24
Finished Jun 27 06:41:22 PM PDT 24
Peak memory 206420 kb
Host smart-1845e55a-af0e-4e4a-b15b-c34cf0e89c68
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2627421772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.2627421772
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.2181634293
Short name T1760
Test name
Test status
Simulation time 234700699 ps
CPU time 0.86 seconds
Started Jun 27 06:40:39 PM PDT 24
Finished Jun 27 06:41:05 PM PDT 24
Peak memory 206284 kb
Host smart-4f2941ae-21e6-41e0-b5ad-42338728f0b9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2181634293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.2181634293
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.4160806106
Short name T1662
Test name
Test status
Simulation time 195705051 ps
CPU time 0.84 seconds
Started Jun 27 06:40:32 PM PDT 24
Finished Jun 27 06:40:43 PM PDT 24
Peak memory 206276 kb
Host smart-314b67fe-75ce-4c79-b6b3-9b91ceb750c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41608
06106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.4160806106
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.1863682095
Short name T1560
Test name
Test status
Simulation time 3701859663 ps
CPU time 34.75 seconds
Started Jun 27 06:40:32 PM PDT 24
Finished Jun 27 06:41:16 PM PDT 24
Peak memory 206408 kb
Host smart-9da87c95-1166-4eb1-aa40-9c608ab6cfea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18636
82095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.1863682095
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.154677671
Short name T1201
Test name
Test status
Simulation time 7539093974 ps
CPU time 70.21 seconds
Started Jun 27 06:40:33 PM PDT 24
Finished Jun 27 06:41:54 PM PDT 24
Peak memory 206372 kb
Host smart-b2e8b964-b28b-49d2-a810-25ae8940dc27
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=154677671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.154677671
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.3909257209
Short name T448
Test name
Test status
Simulation time 162255605 ps
CPU time 0.78 seconds
Started Jun 27 06:40:35 PM PDT 24
Finished Jun 27 06:40:51 PM PDT 24
Peak memory 206296 kb
Host smart-ea7ad2a0-c676-461b-859c-7dabe85ba83c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3909257209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.3909257209
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.2681990631
Short name T1153
Test name
Test status
Simulation time 146923665 ps
CPU time 0.74 seconds
Started Jun 27 06:40:38 PM PDT 24
Finished Jun 27 06:40:59 PM PDT 24
Peak memory 206272 kb
Host smart-881dade7-4ae3-40ea-894e-d726cab55faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26819
90631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.2681990631
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.279386960
Short name T122
Test name
Test status
Simulation time 216758166 ps
CPU time 0.91 seconds
Started Jun 27 06:40:33 PM PDT 24
Finished Jun 27 06:40:44 PM PDT 24
Peak memory 206432 kb
Host smart-e8d73a4d-6f9a-4297-9f62-548cff7702af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27938
6960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.279386960
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.3378702724
Short name T1902
Test name
Test status
Simulation time 183212037 ps
CPU time 0.85 seconds
Started Jun 27 06:40:34 PM PDT 24
Finished Jun 27 06:40:49 PM PDT 24
Peak memory 206284 kb
Host smart-8cf5a532-71cf-40d0-9e95-aa3e388fb1b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33787
02724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.3378702724
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.2478422837
Short name T1506
Test name
Test status
Simulation time 166345376 ps
CPU time 0.83 seconds
Started Jun 27 06:40:35 PM PDT 24
Finished Jun 27 06:40:49 PM PDT 24
Peak memory 206260 kb
Host smart-7a3b2242-ae51-4e22-9c3f-47801a93405c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24784
22837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.2478422837
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.2016203015
Short name T558
Test name
Test status
Simulation time 156541121 ps
CPU time 0.77 seconds
Started Jun 27 06:40:33 PM PDT 24
Finished Jun 27 06:40:46 PM PDT 24
Peak memory 206272 kb
Host smart-43117584-2a5b-4852-a8d1-76972f05e8b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20162
03015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.2016203015
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.538848132
Short name T1307
Test name
Test status
Simulation time 178336842 ps
CPU time 0.82 seconds
Started Jun 27 06:40:30 PM PDT 24
Finished Jun 27 06:40:41 PM PDT 24
Peak memory 206260 kb
Host smart-8d1ca846-d7e0-4967-a77d-0f2268d11c75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53884
8132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.538848132
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.1810753987
Short name T1074
Test name
Test status
Simulation time 239337210 ps
CPU time 0.96 seconds
Started Jun 27 06:40:35 PM PDT 24
Finished Jun 27 06:40:49 PM PDT 24
Peak memory 206276 kb
Host smart-026055b7-89e3-4970-81e6-36836a2c5861
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1810753987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.1810753987
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.3258692466
Short name T2619
Test name
Test status
Simulation time 168496387 ps
CPU time 0.79 seconds
Started Jun 27 06:40:32 PM PDT 24
Finished Jun 27 06:40:42 PM PDT 24
Peak memory 206276 kb
Host smart-f74943b2-7604-42f5-b416-222a1bb410d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32586
92466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.3258692466
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.2311433317
Short name T37
Test name
Test status
Simulation time 72308998 ps
CPU time 0.68 seconds
Started Jun 27 06:40:38 PM PDT 24
Finished Jun 27 06:40:58 PM PDT 24
Peak memory 206268 kb
Host smart-59a322d3-8a35-44cc-bc07-5be3af6ab870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23114
33317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.2311433317
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.4108397701
Short name T279
Test name
Test status
Simulation time 16919727973 ps
CPU time 35 seconds
Started Jun 27 06:40:37 PM PDT 24
Finished Jun 27 06:41:30 PM PDT 24
Peak memory 206444 kb
Host smart-baf1a7a5-58d8-4b04-8365-d34ef5d6f0a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41083
97701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.4108397701
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.1386412162
Short name T2502
Test name
Test status
Simulation time 212651790 ps
CPU time 0.91 seconds
Started Jun 27 06:40:32 PM PDT 24
Finished Jun 27 06:40:43 PM PDT 24
Peak memory 206280 kb
Host smart-7885edd0-4db9-4617-b802-804f28098740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13864
12162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.1386412162
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.3929191336
Short name T807
Test name
Test status
Simulation time 228491533 ps
CPU time 0.89 seconds
Started Jun 27 06:40:33 PM PDT 24
Finished Jun 27 06:40:44 PM PDT 24
Peak memory 206008 kb
Host smart-10dcaca3-86d3-4c92-89f5-0a1a2381f864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39291
91336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.3929191336
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.844761093
Short name T537
Test name
Test status
Simulation time 224504011 ps
CPU time 0.88 seconds
Started Jun 27 06:40:36 PM PDT 24
Finished Jun 27 06:40:53 PM PDT 24
Peak memory 206296 kb
Host smart-ab93318c-f67b-4ce4-bd87-881fdc46f0f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84476
1093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.844761093
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.1756548386
Short name T383
Test name
Test status
Simulation time 159358524 ps
CPU time 0.76 seconds
Started Jun 27 06:40:33 PM PDT 24
Finished Jun 27 06:40:44 PM PDT 24
Peak memory 206284 kb
Host smart-01111bcc-7cf3-4466-9886-1267133bccd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17565
48386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.1756548386
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.3298972557
Short name T682
Test name
Test status
Simulation time 151363313 ps
CPU time 0.75 seconds
Started Jun 27 06:40:43 PM PDT 24
Finished Jun 27 06:41:20 PM PDT 24
Peak memory 206280 kb
Host smart-d217197e-1066-48a0-9c54-eb0fe52e0af4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32989
72557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.3298972557
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.2954172111
Short name T2605
Test name
Test status
Simulation time 143193994 ps
CPU time 0.76 seconds
Started Jun 27 06:40:35 PM PDT 24
Finished Jun 27 06:40:49 PM PDT 24
Peak memory 206276 kb
Host smart-c3650642-8987-447a-98cd-2512dc5ebcab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29541
72111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.2954172111
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.3637943537
Short name T1972
Test name
Test status
Simulation time 176043651 ps
CPU time 0.82 seconds
Started Jun 27 06:40:30 PM PDT 24
Finished Jun 27 06:40:40 PM PDT 24
Peak memory 206264 kb
Host smart-332d29a3-5353-4430-8417-18e21a8d9529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36379
43537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.3637943537
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.649130795
Short name T1585
Test name
Test status
Simulation time 250900057 ps
CPU time 0.92 seconds
Started Jun 27 06:40:35 PM PDT 24
Finished Jun 27 06:40:49 PM PDT 24
Peak memory 206292 kb
Host smart-ac00296c-4843-49d8-a657-33810c96f227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64913
0795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.649130795
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.3703012804
Short name T804
Test name
Test status
Simulation time 4124551324 ps
CPU time 37.29 seconds
Started Jun 27 06:40:40 PM PDT 24
Finished Jun 27 06:41:41 PM PDT 24
Peak memory 206512 kb
Host smart-5172f6b0-cd91-4064-8da8-bc093d4c37f0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3703012804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.3703012804
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.1535031474
Short name T1920
Test name
Test status
Simulation time 163577707 ps
CPU time 0.78 seconds
Started Jun 27 06:40:37 PM PDT 24
Finished Jun 27 06:40:56 PM PDT 24
Peak memory 206208 kb
Host smart-e529eead-7928-4498-9a81-0ffae3a14344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15350
31474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.1535031474
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.1836523770
Short name T1544
Test name
Test status
Simulation time 176761024 ps
CPU time 0.81 seconds
Started Jun 27 06:40:36 PM PDT 24
Finished Jun 27 06:40:51 PM PDT 24
Peak memory 206280 kb
Host smart-2e305bf1-9880-4f4c-b114-94685c246288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18365
23770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.1836523770
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.3426163575
Short name T2147
Test name
Test status
Simulation time 3361799756 ps
CPU time 90.89 seconds
Started Jun 27 06:40:36 PM PDT 24
Finished Jun 27 06:42:21 PM PDT 24
Peak memory 206100 kb
Host smart-3bd47550-dc0a-49ba-86f8-65841b439055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34261
63575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.3426163575
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.1199316792
Short name T1476
Test name
Test status
Simulation time 58399878 ps
CPU time 0.69 seconds
Started Jun 27 06:40:37 PM PDT 24
Finished Jun 27 06:40:56 PM PDT 24
Peak memory 206272 kb
Host smart-2fc1eb75-e302-4b8c-a65b-9b86ad17517b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1199316792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.1199316792
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.2981145045
Short name T1938
Test name
Test status
Simulation time 4035845209 ps
CPU time 4.63 seconds
Started Jun 27 06:40:40 PM PDT 24
Finished Jun 27 06:41:09 PM PDT 24
Peak memory 206356 kb
Host smart-2fa274f0-bee3-40c2-8c11-b1c9a8863ff0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2981145045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.2981145045
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.28488745
Short name T1838
Test name
Test status
Simulation time 13445515835 ps
CPU time 12.25 seconds
Started Jun 27 06:40:37 PM PDT 24
Finished Jun 27 06:41:05 PM PDT 24
Peak memory 206248 kb
Host smart-d922401d-c638-4db5-ba2b-d799cc36555f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=28488745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.28488745
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.235271916
Short name T2447
Test name
Test status
Simulation time 23452300342 ps
CPU time 24.4 seconds
Started Jun 27 06:40:40 PM PDT 24
Finished Jun 27 06:41:29 PM PDT 24
Peak memory 206404 kb
Host smart-60e73462-b162-4008-99e7-bdfa767d6ecb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=235271916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.235271916
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.2897598056
Short name T348
Test name
Test status
Simulation time 175744804 ps
CPU time 0.85 seconds
Started Jun 27 06:40:36 PM PDT 24
Finished Jun 27 06:40:53 PM PDT 24
Peak memory 206224 kb
Host smart-bb16489f-a439-4c28-bfe8-5d0449c9f732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28975
98056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.2897598056
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.3324986597
Short name T705
Test name
Test status
Simulation time 191662108 ps
CPU time 0.78 seconds
Started Jun 27 06:40:37 PM PDT 24
Finished Jun 27 06:40:53 PM PDT 24
Peak memory 206284 kb
Host smart-d03de5dc-1fd5-4401-aec2-35a733f6b2de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33249
86597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.3324986597
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.2258185244
Short name T2007
Test name
Test status
Simulation time 240066413 ps
CPU time 1 seconds
Started Jun 27 06:40:39 PM PDT 24
Finished Jun 27 06:41:02 PM PDT 24
Peak memory 206300 kb
Host smart-d943ed9c-4260-4358-8bfb-4eef5e2284bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22581
85244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.2258185244
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.1928186962
Short name T1282
Test name
Test status
Simulation time 293604178 ps
CPU time 0.93 seconds
Started Jun 27 06:40:37 PM PDT 24
Finished Jun 27 06:40:56 PM PDT 24
Peak memory 206300 kb
Host smart-6f06cb80-e9a4-4be7-b6a0-4d4bf090b882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19281
86962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.1928186962
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.1262080941
Short name T906
Test name
Test status
Simulation time 9080218707 ps
CPU time 16.62 seconds
Started Jun 27 06:40:39 PM PDT 24
Finished Jun 27 06:41:17 PM PDT 24
Peak memory 206488 kb
Host smart-240399f2-e104-4315-95e2-192195c237a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12620
80941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.1262080941
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.341752294
Short name T1381
Test name
Test status
Simulation time 492157838 ps
CPU time 1.41 seconds
Started Jun 27 06:40:38 PM PDT 24
Finished Jun 27 06:41:01 PM PDT 24
Peak memory 206304 kb
Host smart-e73965be-0599-40cb-98e2-93c4d47eb090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34175
2294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.341752294
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.432959108
Short name T1291
Test name
Test status
Simulation time 149716729 ps
CPU time 0.75 seconds
Started Jun 27 06:40:34 PM PDT 24
Finished Jun 27 06:40:47 PM PDT 24
Peak memory 206200 kb
Host smart-ddb12d25-67c2-4dc7-b78a-01e903d8f234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43295
9108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.432959108
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.3856880175
Short name T987
Test name
Test status
Simulation time 39001739 ps
CPU time 0.64 seconds
Started Jun 27 06:40:34 PM PDT 24
Finished Jun 27 06:40:47 PM PDT 24
Peak memory 206216 kb
Host smart-2f7deeb4-2943-408f-9fd2-9f517dd54319
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38568
80175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.3856880175
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.3729864073
Short name T1761
Test name
Test status
Simulation time 785326179 ps
CPU time 1.9 seconds
Started Jun 27 06:40:39 PM PDT 24
Finished Jun 27 06:41:02 PM PDT 24
Peak memory 206436 kb
Host smart-0410910d-3208-4bb6-bdfa-1a12dddf7f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37298
64073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.3729864073
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.3027304905
Short name T993
Test name
Test status
Simulation time 167975131 ps
CPU time 1.7 seconds
Started Jun 27 06:40:39 PM PDT 24
Finished Jun 27 06:41:02 PM PDT 24
Peak memory 206368 kb
Host smart-7c84f5ef-d269-4c4c-b9ec-a5970a4e561a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30273
04905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.3027304905
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.1255405259
Short name T2545
Test name
Test status
Simulation time 257699146 ps
CPU time 0.88 seconds
Started Jun 27 06:40:37 PM PDT 24
Finished Jun 27 06:40:56 PM PDT 24
Peak memory 206292 kb
Host smart-120cb5e7-2d9e-4a25-8976-cdffa909bba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12554
05259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.1255405259
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.1928809800
Short name T741
Test name
Test status
Simulation time 152820870 ps
CPU time 0.77 seconds
Started Jun 27 06:40:33 PM PDT 24
Finished Jun 27 06:40:44 PM PDT 24
Peak memory 206268 kb
Host smart-ef137bbc-a506-487e-9f97-a50f19f40576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19288
09800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.1928809800
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.2635981481
Short name T2585
Test name
Test status
Simulation time 230816553 ps
CPU time 0.9 seconds
Started Jun 27 06:40:38 PM PDT 24
Finished Jun 27 06:40:59 PM PDT 24
Peak memory 206296 kb
Host smart-84398369-8c25-4d60-a7c3-6a9e8be5a611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26359
81481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.2635981481
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_invalid_sync.1358558209
Short name T1402
Test name
Test status
Simulation time 7076551389 ps
CPU time 192.54 seconds
Started Jun 27 06:40:34 PM PDT 24
Finished Jun 27 06:44:00 PM PDT 24
Peak memory 206464 kb
Host smart-2f7359a8-96e1-4e95-b330-4d9910a64a05
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1358558209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.1358558209
Directory /workspace/36.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.3017714166
Short name T1255
Test name
Test status
Simulation time 184149599 ps
CPU time 0.81 seconds
Started Jun 27 06:40:33 PM PDT 24
Finished Jun 27 06:40:44 PM PDT 24
Peak memory 206276 kb
Host smart-deba8172-9fcf-4944-a822-68d22ae501ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30177
14166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.3017714166
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.3287092036
Short name T1403
Test name
Test status
Simulation time 23266228541 ps
CPU time 21.68 seconds
Started Jun 27 06:40:34 PM PDT 24
Finished Jun 27 06:41:08 PM PDT 24
Peak memory 206340 kb
Host smart-931cb518-71d6-4462-b9c5-ac642e981a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32870
92036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.3287092036
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.3842870739
Short name T2187
Test name
Test status
Simulation time 3344015027 ps
CPU time 3.66 seconds
Started Jun 27 06:40:37 PM PDT 24
Finished Jun 27 06:40:59 PM PDT 24
Peak memory 206324 kb
Host smart-902c8840-1757-4d77-a198-af334f06301f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38428
70739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.3842870739
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.1839306771
Short name T2057
Test name
Test status
Simulation time 9789314311 ps
CPU time 272.07 seconds
Started Jun 27 06:40:41 PM PDT 24
Finished Jun 27 06:45:40 PM PDT 24
Peak memory 206444 kb
Host smart-cff269c8-de6d-4344-96bb-3d4f4c3e9f82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18393
06771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.1839306771
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.3533196761
Short name T605
Test name
Test status
Simulation time 4295826034 ps
CPU time 114.11 seconds
Started Jun 27 06:40:41 PM PDT 24
Finished Jun 27 06:43:05 PM PDT 24
Peak memory 206436 kb
Host smart-90646ad3-68b9-4776-8645-704fd08813cc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3533196761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.3533196761
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.3725399292
Short name T812
Test name
Test status
Simulation time 249209789 ps
CPU time 0.9 seconds
Started Jun 27 06:40:40 PM PDT 24
Finished Jun 27 06:41:05 PM PDT 24
Peak memory 206276 kb
Host smart-cc7ea587-500c-419b-ac40-64f64ab7a9ad
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3725399292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.3725399292
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.3518588942
Short name T1629
Test name
Test status
Simulation time 200446101 ps
CPU time 0.86 seconds
Started Jun 27 06:40:40 PM PDT 24
Finished Jun 27 06:41:05 PM PDT 24
Peak memory 206260 kb
Host smart-19955a39-c8bc-40b0-a8b7-1e8a7ac520e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35185
88942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.3518588942
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.4058566900
Short name T1974
Test name
Test status
Simulation time 6245342752 ps
CPU time 55.87 seconds
Started Jun 27 06:40:41 PM PDT 24
Finished Jun 27 06:42:04 PM PDT 24
Peak memory 206396 kb
Host smart-d66344f2-ba16-42fb-9168-b07a0f368cc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40585
66900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.4058566900
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.473555520
Short name T724
Test name
Test status
Simulation time 3557425937 ps
CPU time 32.9 seconds
Started Jun 27 06:40:36 PM PDT 24
Finished Jun 27 06:41:25 PM PDT 24
Peak memory 206436 kb
Host smart-c037013b-6d66-486f-b820-854e0395a39f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=473555520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.473555520
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.1475755497
Short name T2059
Test name
Test status
Simulation time 158008975 ps
CPU time 0.74 seconds
Started Jun 27 06:40:36 PM PDT 24
Finished Jun 27 06:40:53 PM PDT 24
Peak memory 206284 kb
Host smart-1ba69960-697a-4321-853f-f58708ef8349
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1475755497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.1475755497
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.3071563814
Short name T1599
Test name
Test status
Simulation time 155072255 ps
CPU time 0.74 seconds
Started Jun 27 06:40:41 PM PDT 24
Finished Jun 27 06:41:12 PM PDT 24
Peak memory 206252 kb
Host smart-781fac66-81b1-425d-902a-281b888a6d2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30715
63814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.3071563814
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.3719162291
Short name T1675
Test name
Test status
Simulation time 210553393 ps
CPU time 0.85 seconds
Started Jun 27 06:40:40 PM PDT 24
Finished Jun 27 06:41:08 PM PDT 24
Peak memory 206260 kb
Host smart-d0392238-974a-490f-8bb1-0be7f1e68265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37191
62291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.3719162291
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.1537832422
Short name T1076
Test name
Test status
Simulation time 199766568 ps
CPU time 0.8 seconds
Started Jun 27 06:40:42 PM PDT 24
Finished Jun 27 06:41:15 PM PDT 24
Peak memory 206288 kb
Host smart-7d246bdf-f730-46cd-91b2-590ab64204fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15378
32422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.1537832422
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.2031794405
Short name T528
Test name
Test status
Simulation time 173355715 ps
CPU time 0.77 seconds
Started Jun 27 06:40:42 PM PDT 24
Finished Jun 27 06:41:15 PM PDT 24
Peak memory 206276 kb
Host smart-bca27c9f-1a7b-4956-8f67-212eadb8ce6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20317
94405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.2031794405
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.3847534063
Short name T1770
Test name
Test status
Simulation time 238586998 ps
CPU time 0.89 seconds
Started Jun 27 06:40:41 PM PDT 24
Finished Jun 27 06:41:12 PM PDT 24
Peak memory 206236 kb
Host smart-8522c0ed-7d5e-4934-8a4c-737ba4c33dfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38475
34063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.3847534063
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.4207261083
Short name T152
Test name
Test status
Simulation time 177230714 ps
CPU time 0.75 seconds
Started Jun 27 06:40:36 PM PDT 24
Finished Jun 27 06:40:53 PM PDT 24
Peak memory 206268 kb
Host smart-13739c87-6b30-4ab7-af4c-eb1bf3361e8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42072
61083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.4207261083
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.447407602
Short name T80
Test name
Test status
Simulation time 277390872 ps
CPU time 0.94 seconds
Started Jun 27 06:40:41 PM PDT 24
Finished Jun 27 06:41:12 PM PDT 24
Peak memory 206296 kb
Host smart-e3603b61-4fd0-4e38-bf85-11e77b94cb4b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=447407602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.447407602
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.176371176
Short name T864
Test name
Test status
Simulation time 185174189 ps
CPU time 0.77 seconds
Started Jun 27 06:40:37 PM PDT 24
Finished Jun 27 06:40:56 PM PDT 24
Peak memory 206260 kb
Host smart-d62c796b-9132-4703-ac74-970d36a96dfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17637
1176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.176371176
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.3313488580
Short name T1854
Test name
Test status
Simulation time 129031775 ps
CPU time 0.72 seconds
Started Jun 27 06:40:36 PM PDT 24
Finished Jun 27 06:40:53 PM PDT 24
Peak memory 206260 kb
Host smart-6d033802-2fe5-4675-977c-2cf10e54f322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33134
88580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.3313488580
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.3041788394
Short name T249
Test name
Test status
Simulation time 8540561892 ps
CPU time 19.18 seconds
Started Jun 27 06:40:36 PM PDT 24
Finished Jun 27 06:41:11 PM PDT 24
Peak memory 206504 kb
Host smart-64b5aad2-db9e-46a0-b3c1-65934fcd013c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30417
88394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.3041788394
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.3547018816
Short name T1561
Test name
Test status
Simulation time 141666448 ps
CPU time 0.78 seconds
Started Jun 27 06:40:34 PM PDT 24
Finished Jun 27 06:40:47 PM PDT 24
Peak memory 206268 kb
Host smart-41b129bd-86d6-4386-a020-60869b07b223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35470
18816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.3547018816
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.1622078734
Short name T2536
Test name
Test status
Simulation time 259873484 ps
CPU time 0.93 seconds
Started Jun 27 06:40:39 PM PDT 24
Finished Jun 27 06:41:02 PM PDT 24
Peak memory 206304 kb
Host smart-53efe5db-4f0c-4f9e-81ed-bc08dd03877c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16220
78734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.1622078734
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.2185269492
Short name T2277
Test name
Test status
Simulation time 163145179 ps
CPU time 0.75 seconds
Started Jun 27 06:40:37 PM PDT 24
Finished Jun 27 06:40:56 PM PDT 24
Peak memory 206244 kb
Host smart-3386fff2-fa40-4900-b7cd-a52742d6803d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21852
69492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.2185269492
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.3144320568
Short name T1633
Test name
Test status
Simulation time 256305075 ps
CPU time 0.87 seconds
Started Jun 27 06:40:40 PM PDT 24
Finished Jun 27 06:41:05 PM PDT 24
Peak memory 206292 kb
Host smart-05e31654-af9f-4797-ae4f-d18d2fe22186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31443
20568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.3144320568
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.3614228663
Short name T2154
Test name
Test status
Simulation time 188269845 ps
CPU time 0.82 seconds
Started Jun 27 06:40:35 PM PDT 24
Finished Jun 27 06:40:49 PM PDT 24
Peak memory 206208 kb
Host smart-727ca7f9-4abb-4524-9bef-86f23840910f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36142
28663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.3614228663
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.4142347110
Short name T620
Test name
Test status
Simulation time 144732503 ps
CPU time 0.75 seconds
Started Jun 27 06:40:37 PM PDT 24
Finished Jun 27 06:40:56 PM PDT 24
Peak memory 206272 kb
Host smart-ab75663f-ae4e-473c-8868-ead7bcacdd63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41423
47110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.4142347110
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.1282489667
Short name T1511
Test name
Test status
Simulation time 176728446 ps
CPU time 0.86 seconds
Started Jun 27 06:40:39 PM PDT 24
Finished Jun 27 06:41:01 PM PDT 24
Peak memory 206304 kb
Host smart-90d0d160-0f58-4215-b7f2-0f2a1bd74b40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12824
89667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.1282489667
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.4233839623
Short name T1789
Test name
Test status
Simulation time 244753368 ps
CPU time 0.89 seconds
Started Jun 27 06:40:40 PM PDT 24
Finished Jun 27 06:41:05 PM PDT 24
Peak memory 206288 kb
Host smart-236a5b2e-6bef-467d-9ecc-81b0009c2d8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42338
39623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.4233839623
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.263996416
Short name T2362
Test name
Test status
Simulation time 5247138600 ps
CPU time 37.31 seconds
Started Jun 27 06:40:40 PM PDT 24
Finished Jun 27 06:41:41 PM PDT 24
Peak memory 206488 kb
Host smart-23c313b4-3b55-44be-87ea-3e6f5ecc97ec
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=263996416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.263996416
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.4283681397
Short name T2261
Test name
Test status
Simulation time 203133100 ps
CPU time 0.85 seconds
Started Jun 27 06:40:37 PM PDT 24
Finished Jun 27 06:40:53 PM PDT 24
Peak memory 206064 kb
Host smart-59750153-d5cc-4a9c-ad6c-394128e7f4f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42836
81397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.4283681397
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.59878349
Short name T1046
Test name
Test status
Simulation time 181552314 ps
CPU time 0.83 seconds
Started Jun 27 06:40:44 PM PDT 24
Finished Jun 27 06:41:20 PM PDT 24
Peak memory 206252 kb
Host smart-7d68947b-3f64-4428-8cfc-5db6d9763e11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59878
349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.59878349
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.996967505
Short name T902
Test name
Test status
Simulation time 5642331318 ps
CPU time 47.47 seconds
Started Jun 27 06:40:39 PM PDT 24
Finished Jun 27 06:41:51 PM PDT 24
Peak memory 206452 kb
Host smart-c1004754-a864-45ba-a311-76602598187a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99696
7505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.996967505
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.4089571947
Short name T1977
Test name
Test status
Simulation time 37797253 ps
CPU time 0.65 seconds
Started Jun 27 06:40:50 PM PDT 24
Finished Jun 27 06:41:34 PM PDT 24
Peak memory 206356 kb
Host smart-7401d4b5-77ae-4f86-a0be-92495988f5eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4089571947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.4089571947
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.1171138276
Short name T1186
Test name
Test status
Simulation time 4132067894 ps
CPU time 4.99 seconds
Started Jun 27 06:40:44 PM PDT 24
Finished Jun 27 06:41:24 PM PDT 24
Peak memory 206364 kb
Host smart-42b1e4a9-53b7-4e0e-a25c-ff8f6b02398b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1171138276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.1171138276
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.2970821096
Short name T1607
Test name
Test status
Simulation time 13346352875 ps
CPU time 11.58 seconds
Started Jun 27 06:40:51 PM PDT 24
Finished Jun 27 06:41:50 PM PDT 24
Peak memory 206384 kb
Host smart-892de484-b1fe-40a6-981f-317fb66e9e5d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2970821096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.2970821096
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.2001288166
Short name T1707
Test name
Test status
Simulation time 23357148391 ps
CPU time 22.5 seconds
Started Jun 27 06:40:46 PM PDT 24
Finished Jun 27 06:41:50 PM PDT 24
Peak memory 206356 kb
Host smart-59b8e6c0-4969-4e92-ab03-d348b21d333e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2001288166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.2001288166
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.3513749667
Short name T1384
Test name
Test status
Simulation time 153015758 ps
CPU time 0.78 seconds
Started Jun 27 06:40:43 PM PDT 24
Finished Jun 27 06:41:20 PM PDT 24
Peak memory 206272 kb
Host smart-88efff39-eec7-4329-9b55-b8c7e2bc2964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35137
49667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.3513749667
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.1195196566
Short name T64
Test name
Test status
Simulation time 170967043 ps
CPU time 0.78 seconds
Started Jun 27 06:40:45 PM PDT 24
Finished Jun 27 06:41:25 PM PDT 24
Peak memory 206272 kb
Host smart-b86ece1e-c044-4aa4-a7b9-2b40f2986b99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11951
96566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.1195196566
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.3852138854
Short name T1929
Test name
Test status
Simulation time 310738146 ps
CPU time 1.1 seconds
Started Jun 27 06:40:51 PM PDT 24
Finished Jun 27 06:41:39 PM PDT 24
Peak memory 206272 kb
Host smart-6f5b91a3-8c75-4e00-8002-3392485886c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38521
38854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.3852138854
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.1933114724
Short name T164
Test name
Test status
Simulation time 1215817808 ps
CPU time 2.61 seconds
Started Jun 27 06:40:41 PM PDT 24
Finished Jun 27 06:41:14 PM PDT 24
Peak memory 206588 kb
Host smart-4d1d189f-db4e-449b-b1f9-d41a637d058d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19331
14724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.1933114724
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.3917175259
Short name T2041
Test name
Test status
Simulation time 20918186820 ps
CPU time 35.99 seconds
Started Jun 27 06:40:43 PM PDT 24
Finished Jun 27 06:41:51 PM PDT 24
Peak memory 206216 kb
Host smart-bbe3784b-4167-42d8-b0b8-d19f72339b41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39171
75259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.3917175259
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.3437429263
Short name T1050
Test name
Test status
Simulation time 445756064 ps
CPU time 1.25 seconds
Started Jun 27 06:40:44 PM PDT 24
Finished Jun 27 06:41:20 PM PDT 24
Peak memory 206256 kb
Host smart-db716ddb-0d72-457e-85f5-1160990a2254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34374
29263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.3437429263
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.3460060529
Short name T2144
Test name
Test status
Simulation time 175301315 ps
CPU time 0.78 seconds
Started Jun 27 06:40:45 PM PDT 24
Finished Jun 27 06:41:25 PM PDT 24
Peak memory 206432 kb
Host smart-b3265b43-3f59-4bdd-baca-f12407eae322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34600
60529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.3460060529
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.1910935012
Short name T624
Test name
Test status
Simulation time 47343388 ps
CPU time 0.68 seconds
Started Jun 27 06:40:46 PM PDT 24
Finished Jun 27 06:41:29 PM PDT 24
Peak memory 206296 kb
Host smart-b998ad32-df21-40fc-8843-ad2af068b342
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19109
35012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.1910935012
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.3133031555
Short name T2601
Test name
Test status
Simulation time 937743423 ps
CPU time 2.08 seconds
Started Jun 27 06:40:45 PM PDT 24
Finished Jun 27 06:41:26 PM PDT 24
Peak memory 206364 kb
Host smart-70b1dbba-adaf-437d-b998-9aab498bfe33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31330
31555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.3133031555
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.3379216014
Short name T2223
Test name
Test status
Simulation time 268306565 ps
CPU time 1.92 seconds
Started Jun 27 06:40:46 PM PDT 24
Finished Jun 27 06:41:26 PM PDT 24
Peak memory 206420 kb
Host smart-998a7c15-7439-4593-bca2-4b569c9761b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33792
16014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.3379216014
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.1460015501
Short name T428
Test name
Test status
Simulation time 177813471 ps
CPU time 0.87 seconds
Started Jun 27 06:40:51 PM PDT 24
Finished Jun 27 06:41:39 PM PDT 24
Peak memory 206288 kb
Host smart-779efcb3-bad4-44e0-b90f-60fb99c25eeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14600
15501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.1460015501
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.1269826644
Short name T1755
Test name
Test status
Simulation time 149682983 ps
CPU time 0.77 seconds
Started Jun 27 06:40:45 PM PDT 24
Finished Jun 27 06:41:24 PM PDT 24
Peak memory 206228 kb
Host smart-96ed27a0-f1e1-4c55-b213-340dcfdf596d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12698
26644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.1269826644
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.1215181835
Short name T703
Test name
Test status
Simulation time 226380690 ps
CPU time 0.86 seconds
Started Jun 27 06:40:46 PM PDT 24
Finished Jun 27 06:41:25 PM PDT 24
Peak memory 206284 kb
Host smart-c7fe41ba-d05f-43ba-97fc-8f8659b1398b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12151
81835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.1215181835
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.3696879367
Short name T351
Test name
Test status
Simulation time 182060976 ps
CPU time 0.84 seconds
Started Jun 27 06:40:50 PM PDT 24
Finished Jun 27 06:41:38 PM PDT 24
Peak memory 206288 kb
Host smart-b9ae7db2-9692-40ee-b000-bc4691cb6aca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36968
79367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.3696879367
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.2129900130
Short name T411
Test name
Test status
Simulation time 23334434433 ps
CPU time 29.41 seconds
Started Jun 27 06:40:49 PM PDT 24
Finished Jun 27 06:42:03 PM PDT 24
Peak memory 206232 kb
Host smart-78a0274e-e35f-4003-b759-1449f6c036f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21299
00130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.2129900130
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.3355589672
Short name T28
Test name
Test status
Simulation time 3308593486 ps
CPU time 3.96 seconds
Started Jun 27 06:40:43 PM PDT 24
Finished Jun 27 06:41:19 PM PDT 24
Peak memory 206160 kb
Host smart-2aaade6f-67c6-4743-b3bd-f945b8b7e9c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33555
89672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.3355589672
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.668143181
Short name T2278
Test name
Test status
Simulation time 9449271417 ps
CPU time 266.28 seconds
Started Jun 27 06:40:46 PM PDT 24
Finished Jun 27 06:45:54 PM PDT 24
Peak memory 206504 kb
Host smart-2c0e0fee-bb6f-4403-ba11-3c315dc7eda7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66814
3181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.668143181
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.141976950
Short name T435
Test name
Test status
Simulation time 5511515346 ps
CPU time 36.25 seconds
Started Jun 27 06:40:41 PM PDT 24
Finished Jun 27 06:41:44 PM PDT 24
Peak memory 206520 kb
Host smart-e819ba7e-1f43-4597-a204-b22effcca3da
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=141976950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.141976950
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.59616336
Short name T779
Test name
Test status
Simulation time 263596825 ps
CPU time 0.88 seconds
Started Jun 27 06:40:46 PM PDT 24
Finished Jun 27 06:41:25 PM PDT 24
Peak memory 206308 kb
Host smart-d1fa041f-bc79-4178-81e9-1dc51f90bf75
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=59616336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.59616336
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.647351980
Short name T1628
Test name
Test status
Simulation time 252172958 ps
CPU time 0.96 seconds
Started Jun 27 06:40:41 PM PDT 24
Finished Jun 27 06:41:09 PM PDT 24
Peak memory 206288 kb
Host smart-53d74fcd-7227-4ea2-93a8-c4fabb30c134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64735
1980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.647351980
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.4167093319
Short name T1899
Test name
Test status
Simulation time 5672495786 ps
CPU time 40.42 seconds
Started Jun 27 06:40:42 PM PDT 24
Finished Jun 27 06:41:55 PM PDT 24
Peak memory 206508 kb
Host smart-292fda2f-0232-4754-a8cf-6d553823ace0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41670
93319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.4167093319
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.87256424
Short name T1194
Test name
Test status
Simulation time 3270497483 ps
CPU time 29.95 seconds
Started Jun 27 06:40:43 PM PDT 24
Finished Jun 27 06:41:45 PM PDT 24
Peak memory 206428 kb
Host smart-b2c3c94f-7e6b-477a-acc9-e01ffbc70f6a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=87256424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.87256424
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.2280866723
Short name T629
Test name
Test status
Simulation time 164072785 ps
CPU time 0.78 seconds
Started Jun 27 06:40:50 PM PDT 24
Finished Jun 27 06:41:38 PM PDT 24
Peak memory 206292 kb
Host smart-1460f225-aad8-415f-9180-b8d17f087a38
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2280866723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.2280866723
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.2507572285
Short name T475
Test name
Test status
Simulation time 177994623 ps
CPU time 0.79 seconds
Started Jun 27 06:40:42 PM PDT 24
Finished Jun 27 06:41:15 PM PDT 24
Peak memory 206272 kb
Host smart-994e52e2-522b-438f-872d-a63984f184c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25075
72285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.2507572285
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.2635154071
Short name T1846
Test name
Test status
Simulation time 169581904 ps
CPU time 0.79 seconds
Started Jun 27 06:40:43 PM PDT 24
Finished Jun 27 06:41:20 PM PDT 24
Peak memory 206268 kb
Host smart-f2213ae4-5fc4-4216-93a8-2c0c51c82b43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26351
54071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.2635154071
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.712073838
Short name T2611
Test name
Test status
Simulation time 194632925 ps
CPU time 0.84 seconds
Started Jun 27 06:40:51 PM PDT 24
Finished Jun 27 06:41:39 PM PDT 24
Peak memory 206172 kb
Host smart-7d4fd87a-33fa-4dd2-a56b-76c027d6829e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71207
3838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.712073838
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.3279685321
Short name T2031
Test name
Test status
Simulation time 167182613 ps
CPU time 0.76 seconds
Started Jun 27 06:40:50 PM PDT 24
Finished Jun 27 06:41:38 PM PDT 24
Peak memory 206272 kb
Host smart-e1c0612b-a326-4075-844d-b33fb47df8bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32796
85321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.3279685321
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.814647570
Short name T1041
Test name
Test status
Simulation time 211356998 ps
CPU time 0.8 seconds
Started Jun 27 06:40:43 PM PDT 24
Finished Jun 27 06:41:20 PM PDT 24
Peak memory 206280 kb
Host smart-742ec9a2-311c-448d-8feb-ad11787684b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81464
7570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.814647570
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.2519737835
Short name T471
Test name
Test status
Simulation time 236134230 ps
CPU time 0.9 seconds
Started Jun 27 06:40:45 PM PDT 24
Finished Jun 27 06:41:25 PM PDT 24
Peak memory 206284 kb
Host smart-88654b88-ae1a-48a2-87bc-3587a263b724
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2519737835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.2519737835
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.3705834660
Short name T2588
Test name
Test status
Simulation time 141918396 ps
CPU time 0.74 seconds
Started Jun 27 06:40:50 PM PDT 24
Finished Jun 27 06:41:38 PM PDT 24
Peak memory 206288 kb
Host smart-2493d1b8-6899-4895-b003-e87ca1ffb2f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37058
34660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.3705834660
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.1603264951
Short name T2485
Test name
Test status
Simulation time 8484193124 ps
CPU time 20.09 seconds
Started Jun 27 06:40:49 PM PDT 24
Finished Jun 27 06:41:54 PM PDT 24
Peak memory 206516 kb
Host smart-e8d91f0d-2e79-4abd-9f47-5aa09ce24169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16032
64951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.1603264951
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.4239297576
Short name T2150
Test name
Test status
Simulation time 148755705 ps
CPU time 0.79 seconds
Started Jun 27 06:40:46 PM PDT 24
Finished Jun 27 06:41:25 PM PDT 24
Peak memory 206236 kb
Host smart-ad9e7f7a-78d6-4b34-b44c-eab2dd75296b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42392
97576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.4239297576
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.966372088
Short name T1922
Test name
Test status
Simulation time 297103622 ps
CPU time 1.02 seconds
Started Jun 27 06:40:50 PM PDT 24
Finished Jun 27 06:41:39 PM PDT 24
Peak memory 206280 kb
Host smart-a1c6e56a-1b4d-467f-b010-b895e90527c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96637
2088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.966372088
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.3453344235
Short name T1404
Test name
Test status
Simulation time 221390640 ps
CPU time 0.86 seconds
Started Jun 27 06:40:46 PM PDT 24
Finished Jun 27 06:41:28 PM PDT 24
Peak memory 206292 kb
Host smart-6575530d-2b29-4e45-a085-2edf6ab0227e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34533
44235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.3453344235
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.650019127
Short name T316
Test name
Test status
Simulation time 193719741 ps
CPU time 0.86 seconds
Started Jun 27 06:40:51 PM PDT 24
Finished Jun 27 06:41:39 PM PDT 24
Peak memory 206188 kb
Host smart-3a55ac89-6902-4940-a846-897493663239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65001
9127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.650019127
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.1236273930
Short name T2599
Test name
Test status
Simulation time 201960864 ps
CPU time 0.85 seconds
Started Jun 27 06:40:46 PM PDT 24
Finished Jun 27 06:41:28 PM PDT 24
Peak memory 206268 kb
Host smart-dc8a6621-4b65-4b1e-ac08-49b944be9409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12362
73930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.1236273930
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.1609256110
Short name T2084
Test name
Test status
Simulation time 146629642 ps
CPU time 0.76 seconds
Started Jun 27 06:40:42 PM PDT 24
Finished Jun 27 06:41:15 PM PDT 24
Peak memory 206276 kb
Host smart-47b3ebff-1b61-44a9-9999-de883a7b851f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16092
56110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.1609256110
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.2707976248
Short name T2557
Test name
Test status
Simulation time 164058421 ps
CPU time 0.77 seconds
Started Jun 27 06:40:51 PM PDT 24
Finished Jun 27 06:41:39 PM PDT 24
Peak memory 206304 kb
Host smart-c94ca6b2-e8ad-4075-a8e5-0a31dd7b06c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27079
76248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.2707976248
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.1271914201
Short name T706
Test name
Test status
Simulation time 225379565 ps
CPU time 0.91 seconds
Started Jun 27 06:40:46 PM PDT 24
Finished Jun 27 06:41:29 PM PDT 24
Peak memory 206280 kb
Host smart-a18f376c-ac07-4730-b70b-372d8117bcba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12719
14201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.1271914201
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.3152417634
Short name T1273
Test name
Test status
Simulation time 6010561961 ps
CPU time 164.04 seconds
Started Jun 27 06:40:44 PM PDT 24
Finished Jun 27 06:44:03 PM PDT 24
Peak memory 206464 kb
Host smart-aa0d6065-de6e-49a8-9efb-49454a378594
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3152417634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.3152417634
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.1635166869
Short name T1943
Test name
Test status
Simulation time 172516720 ps
CPU time 0.79 seconds
Started Jun 27 06:40:49 PM PDT 24
Finished Jun 27 06:41:34 PM PDT 24
Peak memory 206292 kb
Host smart-5acffc55-4bc8-446c-a425-642ad8f600a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16351
66869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.1635166869
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.3737377919
Short name T2449
Test name
Test status
Simulation time 187650859 ps
CPU time 0.85 seconds
Started Jun 27 06:40:46 PM PDT 24
Finished Jun 27 06:41:25 PM PDT 24
Peak memory 206288 kb
Host smart-2d9c12d0-e267-485f-99cd-fabed4c5a9f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37373
77919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.3737377919
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.2906774102
Short name T1021
Test name
Test status
Simulation time 4299793011 ps
CPU time 121.35 seconds
Started Jun 27 06:40:50 PM PDT 24
Finished Jun 27 06:43:39 PM PDT 24
Peak memory 206428 kb
Host smart-94b6d0f1-35f0-4db5-bd02-521a7d80418a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29067
74102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.2906774102
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.946508004
Short name T1567
Test name
Test status
Simulation time 44716654 ps
CPU time 0.67 seconds
Started Jun 27 06:40:46 PM PDT 24
Finished Jun 27 06:41:29 PM PDT 24
Peak memory 206316 kb
Host smart-fdbdd7c6-8ba1-4794-a641-85d8155545fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=946508004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.946508004
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.2147734413
Short name T1541
Test name
Test status
Simulation time 3669297144 ps
CPU time 4.38 seconds
Started Jun 27 06:40:45 PM PDT 24
Finished Jun 27 06:41:28 PM PDT 24
Peak memory 206320 kb
Host smart-19e14102-67a1-4b24-a049-3fb577121d89
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2147734413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.2147734413
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.2956051986
Short name T1600
Test name
Test status
Simulation time 13366995083 ps
CPU time 11.85 seconds
Started Jun 27 06:40:51 PM PDT 24
Finished Jun 27 06:41:50 PM PDT 24
Peak memory 206352 kb
Host smart-4faf3a92-c228-4ffa-b276-54375f802989
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2956051986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.2956051986
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.2491720656
Short name T1609
Test name
Test status
Simulation time 23466826106 ps
CPU time 22.76 seconds
Started Jun 27 06:40:48 PM PDT 24
Finished Jun 27 06:41:56 PM PDT 24
Peak memory 206492 kb
Host smart-069d05ac-27c0-408f-b0c7-54fec70f3fc7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2491720656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.2491720656
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.1798685072
Short name T1622
Test name
Test status
Simulation time 148352218 ps
CPU time 0.78 seconds
Started Jun 27 06:40:49 PM PDT 24
Finished Jun 27 06:41:34 PM PDT 24
Peak memory 206272 kb
Host smart-d7037b1b-0878-481a-84e7-f7f99ba69901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17986
85072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.1798685072
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.1088572901
Short name T1437
Test name
Test status
Simulation time 157894022 ps
CPU time 0.78 seconds
Started Jun 27 06:40:50 PM PDT 24
Finished Jun 27 06:41:39 PM PDT 24
Peak memory 206272 kb
Host smart-7c77d249-1268-40e6-9abb-296af7204bd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10885
72901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.1088572901
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.4274933241
Short name T1812
Test name
Test status
Simulation time 384473948 ps
CPU time 1.21 seconds
Started Jun 27 06:40:55 PM PDT 24
Finished Jun 27 06:41:50 PM PDT 24
Peak memory 206248 kb
Host smart-0e183b0a-1910-4f95-807c-4a2d2876330a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42749
33241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.4274933241
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.3470524599
Short name T2133
Test name
Test status
Simulation time 777317115 ps
CPU time 1.89 seconds
Started Jun 27 06:40:49 PM PDT 24
Finished Jun 27 06:41:35 PM PDT 24
Peak memory 206352 kb
Host smart-2a1daf70-337f-43fb-a905-4dfb26f66aea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34705
24599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.3470524599
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.2347800275
Short name T182
Test name
Test status
Simulation time 12389642018 ps
CPU time 23.14 seconds
Started Jun 27 06:40:50 PM PDT 24
Finished Jun 27 06:42:01 PM PDT 24
Peak memory 206436 kb
Host smart-e32ba93e-d0ce-477e-9860-91847bd2c23f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23478
00275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.2347800275
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.2171961088
Short name T1877
Test name
Test status
Simulation time 398273515 ps
CPU time 1.23 seconds
Started Jun 27 06:40:50 PM PDT 24
Finished Jun 27 06:41:39 PM PDT 24
Peak memory 206272 kb
Host smart-2dcbf318-771d-4552-9fd3-e2280885df68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21719
61088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.2171961088
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.2385220843
Short name T2248
Test name
Test status
Simulation time 146448919 ps
CPU time 0.8 seconds
Started Jun 27 06:40:55 PM PDT 24
Finished Jun 27 06:41:50 PM PDT 24
Peak memory 206240 kb
Host smart-20957c34-96fd-400e-bfff-f6721ddb1a6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23852
20843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.2385220843
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.942105707
Short name T1856
Test name
Test status
Simulation time 86137034 ps
CPU time 0.7 seconds
Started Jun 27 06:40:55 PM PDT 24
Finished Jun 27 06:41:50 PM PDT 24
Peak memory 206280 kb
Host smart-9d5dd8bc-4430-4eb2-81e7-7ca3831221ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94210
5707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.942105707
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.3446179900
Short name T2354
Test name
Test status
Simulation time 861438016 ps
CPU time 1.99 seconds
Started Jun 27 06:40:52 PM PDT 24
Finished Jun 27 06:41:45 PM PDT 24
Peak memory 206380 kb
Host smart-43d5f02e-4a20-47c4-89d2-2ea961df6ccf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34461
79900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.3446179900
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.3866840669
Short name T1793
Test name
Test status
Simulation time 174392114 ps
CPU time 1.88 seconds
Started Jun 27 06:40:55 PM PDT 24
Finished Jun 27 06:41:51 PM PDT 24
Peak memory 206424 kb
Host smart-356f331e-ee86-45ea-8ec1-80070434aa63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38668
40669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.3866840669
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.2019488992
Short name T1216
Test name
Test status
Simulation time 193115470 ps
CPU time 0.81 seconds
Started Jun 27 06:40:50 PM PDT 24
Finished Jun 27 06:41:38 PM PDT 24
Peak memory 206288 kb
Host smart-23877101-1608-4681-96ee-343b441a960c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20194
88992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.2019488992
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.2270324106
Short name T418
Test name
Test status
Simulation time 178796750 ps
CPU time 0.76 seconds
Started Jun 27 06:40:53 PM PDT 24
Finished Jun 27 06:41:44 PM PDT 24
Peak memory 206248 kb
Host smart-df41a857-f129-43e2-8e31-c36def01979d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22703
24106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.2270324106
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.2976858855
Short name T1008
Test name
Test status
Simulation time 229774040 ps
CPU time 0.92 seconds
Started Jun 27 06:40:55 PM PDT 24
Finished Jun 27 06:41:50 PM PDT 24
Peak memory 206288 kb
Host smart-1f11e426-6a44-4ce1-a05c-0d80299c3e76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29768
58855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.2976858855
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.4009407793
Short name T1147
Test name
Test status
Simulation time 237021111 ps
CPU time 0.88 seconds
Started Jun 27 06:40:52 PM PDT 24
Finished Jun 27 06:41:44 PM PDT 24
Peak memory 206236 kb
Host smart-73ac3591-30df-48d9-8a58-a4b630c13798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40094
07793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.4009407793
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.40863851
Short name T801
Test name
Test status
Simulation time 23321163987 ps
CPU time 21.95 seconds
Started Jun 27 06:40:55 PM PDT 24
Finished Jun 27 06:42:11 PM PDT 24
Peak memory 206336 kb
Host smart-40279513-dd3f-43c5-9cd9-2fa1b83663f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40863
851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.40863851
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.2599588344
Short name T1351
Test name
Test status
Simulation time 3270709750 ps
CPU time 3.88 seconds
Started Jun 27 06:40:55 PM PDT 24
Finished Jun 27 06:41:48 PM PDT 24
Peak memory 206348 kb
Host smart-fd9d787b-ee3f-4e7b-95e7-45e146ef7f48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25995
88344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.2599588344
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.1259602120
Short name T91
Test name
Test status
Simulation time 6661546157 ps
CPU time 184.71 seconds
Started Jun 27 06:40:52 PM PDT 24
Finished Jun 27 06:44:48 PM PDT 24
Peak memory 206520 kb
Host smart-2d72622f-0365-4d8f-8595-475da91da9f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12596
02120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.1259602120
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.3647493292
Short name T1325
Test name
Test status
Simulation time 3756340861 ps
CPU time 35.76 seconds
Started Jun 27 06:40:55 PM PDT 24
Finished Jun 27 06:42:24 PM PDT 24
Peak memory 206444 kb
Host smart-14435b64-ad79-423c-a26e-a1e9187e1fa7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3647493292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.3647493292
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.2720882003
Short name T1484
Test name
Test status
Simulation time 235449513 ps
CPU time 0.95 seconds
Started Jun 27 06:40:55 PM PDT 24
Finished Jun 27 06:41:50 PM PDT 24
Peak memory 206276 kb
Host smart-cc40cc60-ae1e-47c4-9905-401911e1e29b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2720882003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.2720882003
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.1835546314
Short name T1247
Test name
Test status
Simulation time 189126517 ps
CPU time 0.86 seconds
Started Jun 27 06:40:51 PM PDT 24
Finished Jun 27 06:41:39 PM PDT 24
Peak memory 206200 kb
Host smart-2f311ac4-9950-48dd-af99-b9c6437a7718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18355
46314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.1835546314
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.3774374279
Short name T1659
Test name
Test status
Simulation time 5025717475 ps
CPU time 138.65 seconds
Started Jun 27 06:40:54 PM PDT 24
Finished Jun 27 06:44:03 PM PDT 24
Peak memory 206436 kb
Host smart-5e79cc93-736e-428e-b078-12792cd4bc65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37743
74279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.3774374279
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.358442747
Short name T1378
Test name
Test status
Simulation time 5267288186 ps
CPU time 44.62 seconds
Started Jun 27 06:40:54 PM PDT 24
Finished Jun 27 06:42:29 PM PDT 24
Peak memory 206420 kb
Host smart-9d361a28-9040-4fa5-9381-8ee8db271e97
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=358442747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.358442747
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.4183417510
Short name T1532
Test name
Test status
Simulation time 166368841 ps
CPU time 0.8 seconds
Started Jun 27 06:40:51 PM PDT 24
Finished Jun 27 06:41:39 PM PDT 24
Peak memory 206232 kb
Host smart-e5c7804c-9fe9-411d-aa36-8e41f9ae3b86
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4183417510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.4183417510
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.2411554832
Short name T309
Test name
Test status
Simulation time 168395911 ps
CPU time 0.75 seconds
Started Jun 27 06:40:54 PM PDT 24
Finished Jun 27 06:41:45 PM PDT 24
Peak memory 206232 kb
Host smart-3a5cb197-b77f-4311-9d24-d94775962431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24115
54832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.2411554832
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.3586007957
Short name T1189
Test name
Test status
Simulation time 169081950 ps
CPU time 0.83 seconds
Started Jun 27 06:40:55 PM PDT 24
Finished Jun 27 06:41:50 PM PDT 24
Peak memory 206264 kb
Host smart-33e8ff62-708c-4914-bfc1-50a130d34bc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35860
07957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.3586007957
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.964634112
Short name T1645
Test name
Test status
Simulation time 201813995 ps
CPU time 0.84 seconds
Started Jun 27 06:40:54 PM PDT 24
Finished Jun 27 06:41:45 PM PDT 24
Peak memory 206256 kb
Host smart-6f45c86e-cb56-4f31-8488-22ab38e61bdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96463
4112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.964634112
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.2531888594
Short name T2231
Test name
Test status
Simulation time 180546812 ps
CPU time 0.8 seconds
Started Jun 27 06:40:54 PM PDT 24
Finished Jun 27 06:41:45 PM PDT 24
Peak memory 206204 kb
Host smart-ead1e702-1260-4504-bd74-ecfae01c7b47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25318
88594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.2531888594
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.1470755061
Short name T1002
Test name
Test status
Simulation time 154076944 ps
CPU time 0.76 seconds
Started Jun 27 06:40:55 PM PDT 24
Finished Jun 27 06:41:49 PM PDT 24
Peak memory 206264 kb
Host smart-9f9ede8d-d675-459e-9126-ac4bfff761db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14707
55061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.1470755061
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.214556435
Short name T165
Test name
Test status
Simulation time 156957281 ps
CPU time 0.76 seconds
Started Jun 27 06:40:59 PM PDT 24
Finished Jun 27 06:41:55 PM PDT 24
Peak memory 206196 kb
Host smart-6b199c87-5c9a-4882-bedd-33f524c0c6bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21455
6435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.214556435
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.511331646
Short name T1347
Test name
Test status
Simulation time 209365015 ps
CPU time 0.87 seconds
Started Jun 27 06:40:53 PM PDT 24
Finished Jun 27 06:41:45 PM PDT 24
Peak memory 206292 kb
Host smart-595148d1-cd88-42d4-8ac9-6a279bc60ff7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=511331646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.511331646
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.166146607
Short name T39
Test name
Test status
Simulation time 140608738 ps
CPU time 0.73 seconds
Started Jun 27 06:40:53 PM PDT 24
Finished Jun 27 06:41:45 PM PDT 24
Peak memory 206276 kb
Host smart-2babd840-4eb2-44f1-bfd0-add433fa4ec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16614
6607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.166146607
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.3399065705
Short name T947
Test name
Test status
Simulation time 39690349 ps
CPU time 0.64 seconds
Started Jun 27 06:40:57 PM PDT 24
Finished Jun 27 06:41:50 PM PDT 24
Peak memory 206248 kb
Host smart-b17bb71a-ae91-4afb-905a-ef096d9cac45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33990
65705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.3399065705
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.816385761
Short name T2426
Test name
Test status
Simulation time 19216509802 ps
CPU time 41.45 seconds
Started Jun 27 06:40:56 PM PDT 24
Finished Jun 27 06:42:31 PM PDT 24
Peak memory 206428 kb
Host smart-6f65ba18-bbd1-457b-a03f-1650df809e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81638
5761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.816385761
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.1250076050
Short name T313
Test name
Test status
Simulation time 204601029 ps
CPU time 0.86 seconds
Started Jun 27 06:40:44 PM PDT 24
Finished Jun 27 06:41:20 PM PDT 24
Peak memory 206276 kb
Host smart-356bb815-3ff4-4be6-ae15-afe5372e0fcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12500
76050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.1250076050
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.2560853651
Short name T722
Test name
Test status
Simulation time 215551974 ps
CPU time 0.84 seconds
Started Jun 27 06:40:47 PM PDT 24
Finished Jun 27 06:41:29 PM PDT 24
Peak memory 206280 kb
Host smart-eab0c5ad-72d9-4e0b-bab0-cc4604c6d44d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25608
53651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.2560853651
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.2233226870
Short name T1615
Test name
Test status
Simulation time 244321296 ps
CPU time 0.89 seconds
Started Jun 27 06:41:01 PM PDT 24
Finished Jun 27 06:42:01 PM PDT 24
Peak memory 206196 kb
Host smart-d5ffe2e6-d627-4b01-b234-7e04879baf1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22332
26870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.2233226870
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.1358429168
Short name T1769
Test name
Test status
Simulation time 163012428 ps
CPU time 0.78 seconds
Started Jun 27 06:40:58 PM PDT 24
Finished Jun 27 06:41:55 PM PDT 24
Peak memory 206176 kb
Host smart-7ee742ac-e981-4830-9f62-48a3570c5d46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13584
29168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.1358429168
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.2293124683
Short name T2330
Test name
Test status
Simulation time 147809034 ps
CPU time 0.75 seconds
Started Jun 27 06:40:58 PM PDT 24
Finished Jun 27 06:41:55 PM PDT 24
Peak memory 206172 kb
Host smart-36a6f095-4860-4dd2-8057-cc7959c31a20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22931
24683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.2293124683
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.3190781440
Short name T608
Test name
Test status
Simulation time 145540747 ps
CPU time 0.72 seconds
Started Jun 27 06:41:00 PM PDT 24
Finished Jun 27 06:41:56 PM PDT 24
Peak memory 206172 kb
Host smart-cc48d8e9-773f-483d-8608-37ecf76e098c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31907
81440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.3190781440
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.2719084831
Short name T2283
Test name
Test status
Simulation time 157497204 ps
CPU time 0.75 seconds
Started Jun 27 06:40:56 PM PDT 24
Finished Jun 27 06:41:50 PM PDT 24
Peak memory 206240 kb
Host smart-028e183e-c252-4b86-b01c-340c129af3c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27190
84831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.2719084831
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.504425329
Short name T999
Test name
Test status
Simulation time 213324664 ps
CPU time 0.87 seconds
Started Jun 27 06:40:58 PM PDT 24
Finished Jun 27 06:41:55 PM PDT 24
Peak memory 206188 kb
Host smart-494a679b-f692-439a-99fe-2afe33c9a58c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50442
5329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.504425329
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.44997407
Short name T478
Test name
Test status
Simulation time 3863591666 ps
CPU time 34.96 seconds
Started Jun 27 06:41:02 PM PDT 24
Finished Jun 27 06:42:35 PM PDT 24
Peak memory 206496 kb
Host smart-951ca166-80ac-43bd-b9d6-302feaf7ea0d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=44997407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.44997407
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.4212239877
Short name T342
Test name
Test status
Simulation time 161142882 ps
CPU time 0.79 seconds
Started Jun 27 06:41:02 PM PDT 24
Finished Jun 27 06:42:01 PM PDT 24
Peak memory 205924 kb
Host smart-7517b549-da9a-4f52-8aaa-7a0b0aa76cf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42122
39877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.4212239877
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.1452975001
Short name T1620
Test name
Test status
Simulation time 146620045 ps
CPU time 0.75 seconds
Started Jun 27 06:41:02 PM PDT 24
Finished Jun 27 06:42:01 PM PDT 24
Peak memory 206288 kb
Host smart-fe3de089-27bb-4194-b62f-246f21e0e870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14529
75001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.1452975001
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.2521051639
Short name T1538
Test name
Test status
Simulation time 6881786465 ps
CPU time 59.81 seconds
Started Jun 27 06:41:02 PM PDT 24
Finished Jun 27 06:43:00 PM PDT 24
Peak memory 206484 kb
Host smart-a65823be-0829-4596-9b11-1532a8779b33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25210
51639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.2521051639
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.960638479
Short name T370
Test name
Test status
Simulation time 37085936 ps
CPU time 0.64 seconds
Started Jun 27 06:40:50 PM PDT 24
Finished Jun 27 06:41:38 PM PDT 24
Peak memory 206348 kb
Host smart-2a1f1844-9218-4306-b2b2-1ac1a0c33158
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=960638479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.960638479
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.2885289780
Short name T2178
Test name
Test status
Simulation time 4109413431 ps
CPU time 5.35 seconds
Started Jun 27 06:40:46 PM PDT 24
Finished Jun 27 06:41:33 PM PDT 24
Peak memory 206380 kb
Host smart-499088b0-ea41-4e85-93e9-cd4f186573bf
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2885289780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.2885289780
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.2761307332
Short name T1733
Test name
Test status
Simulation time 13413365344 ps
CPU time 13.95 seconds
Started Jun 27 06:40:56 PM PDT 24
Finished Jun 27 06:42:03 PM PDT 24
Peak memory 206336 kb
Host smart-e67aff87-a922-47e2-9ac2-fd5c4dfe6221
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2761307332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.2761307332
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.4050230276
Short name T538
Test name
Test status
Simulation time 23348207042 ps
CPU time 29 seconds
Started Jun 27 06:40:47 PM PDT 24
Finished Jun 27 06:41:57 PM PDT 24
Peak memory 206332 kb
Host smart-7c4d7c3f-8357-4665-ba23-c559ff44542e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4050230276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.4050230276
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.3506452987
Short name T2037
Test name
Test status
Simulation time 150922049 ps
CPU time 0.75 seconds
Started Jun 27 06:40:50 PM PDT 24
Finished Jun 27 06:41:38 PM PDT 24
Peak memory 206272 kb
Host smart-0f7274f3-c81c-4de6-af3b-da42fb270b13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35064
52987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.3506452987
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.3031240307
Short name T1183
Test name
Test status
Simulation time 160406445 ps
CPU time 0.76 seconds
Started Jun 27 06:40:55 PM PDT 24
Finished Jun 27 06:41:50 PM PDT 24
Peak memory 206224 kb
Host smart-6ba208b7-56b6-4d50-b3d6-9852cbf737ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30312
40307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.3031240307
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.2027661329
Short name T173
Test name
Test status
Simulation time 230526147 ps
CPU time 0.95 seconds
Started Jun 27 06:40:49 PM PDT 24
Finished Jun 27 06:41:34 PM PDT 24
Peak memory 206236 kb
Host smart-f041fa08-2b60-47d3-a576-b67ca1185dfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20276
61329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.2027661329
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.3765782702
Short name T1952
Test name
Test status
Simulation time 1112933258 ps
CPU time 2.34 seconds
Started Jun 27 06:40:55 PM PDT 24
Finished Jun 27 06:41:51 PM PDT 24
Peak memory 206416 kb
Host smart-a48f945f-4d91-4aa4-aad3-ef37143bffbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37657
82702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.3765782702
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.2831354327
Short name T1422
Test name
Test status
Simulation time 10658762278 ps
CPU time 18.24 seconds
Started Jun 27 06:40:55 PM PDT 24
Finished Jun 27 06:42:07 PM PDT 24
Peak memory 206512 kb
Host smart-d35a698b-3fc1-480e-9d98-60740f3093fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28313
54327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.2831354327
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.1001312750
Short name T677
Test name
Test status
Simulation time 482223783 ps
CPU time 1.36 seconds
Started Jun 27 06:40:56 PM PDT 24
Finished Jun 27 06:41:51 PM PDT 24
Peak memory 206280 kb
Host smart-e10cbf42-3e4e-42fd-9c36-a934dff2af23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10013
12750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.1001312750
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.1084244355
Short name T2051
Test name
Test status
Simulation time 144482611 ps
CPU time 0.75 seconds
Started Jun 27 06:40:55 PM PDT 24
Finished Jun 27 06:41:50 PM PDT 24
Peak memory 206044 kb
Host smart-6794b4a4-ff4e-47c9-854c-640335b128c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10842
44355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.1084244355
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.4224638328
Short name T601
Test name
Test status
Simulation time 45168643 ps
CPU time 0.66 seconds
Started Jun 27 06:40:53 PM PDT 24
Finished Jun 27 06:41:44 PM PDT 24
Peak memory 206248 kb
Host smart-bcc96f0d-ae7e-4f93-9067-b832bab8eeca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42246
38328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.4224638328
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.3063614539
Short name T594
Test name
Test status
Simulation time 798463611 ps
CPU time 2.04 seconds
Started Jun 27 06:40:56 PM PDT 24
Finished Jun 27 06:41:51 PM PDT 24
Peak memory 206348 kb
Host smart-09a30694-51f8-4e94-8920-4508a4775c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30636
14539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.3063614539
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.42889449
Short name T2389
Test name
Test status
Simulation time 185855626 ps
CPU time 2.09 seconds
Started Jun 27 06:40:55 PM PDT 24
Finished Jun 27 06:41:51 PM PDT 24
Peak memory 206336 kb
Host smart-88800ddf-4846-491d-accf-c9e7ff806d39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42889
449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.42889449
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.2235279374
Short name T212
Test name
Test status
Simulation time 198125254 ps
CPU time 0.84 seconds
Started Jun 27 06:40:46 PM PDT 24
Finished Jun 27 06:41:28 PM PDT 24
Peak memory 206272 kb
Host smart-5adf407c-9d57-40f3-8bce-d668ca4644fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22352
79374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.2235279374
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.1468384408
Short name T1908
Test name
Test status
Simulation time 147034948 ps
CPU time 0.77 seconds
Started Jun 27 06:40:44 PM PDT 24
Finished Jun 27 06:41:20 PM PDT 24
Peak memory 206260 kb
Host smart-c0c40033-3e91-41d5-8573-934f8539af3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14683
84408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.1468384408
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.2553283488
Short name T379
Test name
Test status
Simulation time 179620378 ps
CPU time 0.81 seconds
Started Jun 27 06:40:52 PM PDT 24
Finished Jun 27 06:41:44 PM PDT 24
Peak memory 206248 kb
Host smart-46a47a00-8bcc-4a81-860c-dc19abc2f53d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25532
83488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.2553283488
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.904876639
Short name T2478
Test name
Test status
Simulation time 242026711 ps
CPU time 0.92 seconds
Started Jun 27 06:40:54 PM PDT 24
Finished Jun 27 06:41:45 PM PDT 24
Peak memory 206272 kb
Host smart-8b16f82d-cb45-4fae-80b6-e73cba9b6e62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90487
6639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.904876639
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.1662142849
Short name T2310
Test name
Test status
Simulation time 23327572096 ps
CPU time 27.28 seconds
Started Jun 27 06:40:56 PM PDT 24
Finished Jun 27 06:42:17 PM PDT 24
Peak memory 206336 kb
Host smart-644a411e-bff5-461f-b4c5-49ca7e8573a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16621
42849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.1662142849
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.295982534
Short name T1394
Test name
Test status
Simulation time 3335099784 ps
CPU time 3.84 seconds
Started Jun 27 06:40:51 PM PDT 24
Finished Jun 27 06:41:42 PM PDT 24
Peak memory 206320 kb
Host smart-f462a042-bdbf-408e-9123-316dddca34f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29598
2534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.295982534
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.1079905926
Short name T905
Test name
Test status
Simulation time 8862848121 ps
CPU time 79.31 seconds
Started Jun 27 06:40:54 PM PDT 24
Finished Jun 27 06:43:04 PM PDT 24
Peak memory 206500 kb
Host smart-87cf09fe-20fd-4154-b45e-3bbc90603a91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10799
05926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.1079905926
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.872145314
Short name T1857
Test name
Test status
Simulation time 8185738390 ps
CPU time 79.62 seconds
Started Jun 27 06:40:52 PM PDT 24
Finished Jun 27 06:42:58 PM PDT 24
Peak memory 206440 kb
Host smart-b110c905-60d5-4ec8-9f05-7d2246c206f1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=872145314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.872145314
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.4131211342
Short name T365
Test name
Test status
Simulation time 270047847 ps
CPU time 0.91 seconds
Started Jun 27 06:40:55 PM PDT 24
Finished Jun 27 06:41:50 PM PDT 24
Peak memory 206292 kb
Host smart-ca7550c2-4eda-4b2c-96e3-2665e6b1f6e6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4131211342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.4131211342
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.860829229
Short name T2145
Test name
Test status
Simulation time 195701513 ps
CPU time 0.9 seconds
Started Jun 27 06:40:54 PM PDT 24
Finished Jun 27 06:41:45 PM PDT 24
Peak memory 206204 kb
Host smart-d916f185-682b-4182-ad8c-737d5f420864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86082
9229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.860829229
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.1634700086
Short name T2072
Test name
Test status
Simulation time 5913548770 ps
CPU time 45.33 seconds
Started Jun 27 06:40:51 PM PDT 24
Finished Jun 27 06:42:23 PM PDT 24
Peak memory 206452 kb
Host smart-54bb62af-8215-440b-8db6-114f0aa06d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16347
00086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.1634700086
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.674834373
Short name T818
Test name
Test status
Simulation time 6886777863 ps
CPU time 64.17 seconds
Started Jun 27 06:40:51 PM PDT 24
Finished Jun 27 06:42:42 PM PDT 24
Peak memory 206436 kb
Host smart-324c8285-8c1e-4fcb-bd6d-3138b5e7a449
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=674834373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.674834373
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.1730028958
Short name T796
Test name
Test status
Simulation time 192346401 ps
CPU time 0.81 seconds
Started Jun 27 06:40:50 PM PDT 24
Finished Jun 27 06:41:38 PM PDT 24
Peak memory 206280 kb
Host smart-35b2f96f-44b6-4b8f-acc0-e0413322fbaf
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1730028958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.1730028958
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.3399835581
Short name T1921
Test name
Test status
Simulation time 137540717 ps
CPU time 0.77 seconds
Started Jun 27 06:40:50 PM PDT 24
Finished Jun 27 06:41:38 PM PDT 24
Peak memory 206264 kb
Host smart-e0f03214-20fc-43a5-b6c5-7c7784b64870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33998
35581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.3399835581
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.3020714959
Short name T128
Test name
Test status
Simulation time 222748403 ps
CPU time 0.83 seconds
Started Jun 27 06:40:54 PM PDT 24
Finished Jun 27 06:41:45 PM PDT 24
Peak memory 206276 kb
Host smart-aad8b552-0557-49f1-891d-83e4052c63fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30207
14959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.3020714959
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.1422429760
Short name T1149
Test name
Test status
Simulation time 200873562 ps
CPU time 0.83 seconds
Started Jun 27 06:41:00 PM PDT 24
Finished Jun 27 06:42:00 PM PDT 24
Peak memory 206188 kb
Host smart-865fa942-6825-4d3f-a23b-1826b423bf21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14224
29760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.1422429760
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.1099181275
Short name T2316
Test name
Test status
Simulation time 234237108 ps
CPU time 0.84 seconds
Started Jun 27 06:40:54 PM PDT 24
Finished Jun 27 06:41:45 PM PDT 24
Peak memory 206276 kb
Host smart-cae3f2e1-feca-4bb4-9975-9b22ed1d9335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10991
81275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.1099181275
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.1783569915
Short name T2472
Test name
Test status
Simulation time 148080336 ps
CPU time 0.75 seconds
Started Jun 27 06:40:55 PM PDT 24
Finished Jun 27 06:41:49 PM PDT 24
Peak memory 206264 kb
Host smart-3db33d4a-4223-4cd7-8efc-53be1430d647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17835
69915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.1783569915
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.1260035481
Short name T1409
Test name
Test status
Simulation time 164129222 ps
CPU time 0.76 seconds
Started Jun 27 06:40:53 PM PDT 24
Finished Jun 27 06:41:45 PM PDT 24
Peak memory 206276 kb
Host smart-9550dbaa-a483-4be7-a830-6f112df8d78a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12600
35481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.1260035481
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.4273441458
Short name T1104
Test name
Test status
Simulation time 203450311 ps
CPU time 0.86 seconds
Started Jun 27 06:40:53 PM PDT 24
Finished Jun 27 06:41:44 PM PDT 24
Peak memory 206292 kb
Host smart-33ae8bc0-e1d5-4100-8a84-8baab7a09e05
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4273441458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.4273441458
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.1887624680
Short name T1022
Test name
Test status
Simulation time 146419413 ps
CPU time 0.72 seconds
Started Jun 27 06:40:56 PM PDT 24
Finished Jun 27 06:41:50 PM PDT 24
Peak memory 206252 kb
Host smart-c60a1fab-99fc-46f1-b7f3-d6b0987f8b0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18876
24680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.1887624680
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.3618675853
Short name T1353
Test name
Test status
Simulation time 31343347 ps
CPU time 0.67 seconds
Started Jun 27 06:40:53 PM PDT 24
Finished Jun 27 06:41:44 PM PDT 24
Peak memory 206268 kb
Host smart-df7143d7-80d9-4bfe-8f73-21374ef5de22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36186
75853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.3618675853
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.236312659
Short name T945
Test name
Test status
Simulation time 18759497664 ps
CPU time 41.35 seconds
Started Jun 27 06:40:57 PM PDT 24
Finished Jun 27 06:42:31 PM PDT 24
Peak memory 214628 kb
Host smart-29ebac6b-92f9-4a2f-8067-da8857d65388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23631
2659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.236312659
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.233359109
Short name T394
Test name
Test status
Simulation time 203587139 ps
CPU time 0.83 seconds
Started Jun 27 06:40:45 PM PDT 24
Finished Jun 27 06:41:24 PM PDT 24
Peak memory 206248 kb
Host smart-c3ba1a6a-032a-424a-9ac1-5dd63fd895bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23335
9109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.233359109
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.2745469562
Short name T622
Test name
Test status
Simulation time 229980321 ps
CPU time 0.9 seconds
Started Jun 27 06:40:58 PM PDT 24
Finished Jun 27 06:41:55 PM PDT 24
Peak memory 206184 kb
Host smart-d2296af5-85ff-4291-9f68-b87b0f520ab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27454
69562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.2745469562
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.2236907552
Short name T707
Test name
Test status
Simulation time 261796089 ps
CPU time 0.85 seconds
Started Jun 27 06:40:56 PM PDT 24
Finished Jun 27 06:41:50 PM PDT 24
Peak memory 206276 kb
Host smart-1bf07e77-2fe7-496d-af29-aa64630a6d83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22369
07552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.2236907552
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.2481772542
Short name T1165
Test name
Test status
Simulation time 190491129 ps
CPU time 0.8 seconds
Started Jun 27 06:40:55 PM PDT 24
Finished Jun 27 06:41:50 PM PDT 24
Peak memory 206256 kb
Host smart-4ad20416-ddef-491a-b252-bee9bf7dbf6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24817
72542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.2481772542
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.4036479797
Short name T2329
Test name
Test status
Simulation time 171278252 ps
CPU time 0.78 seconds
Started Jun 27 06:40:56 PM PDT 24
Finished Jun 27 06:41:50 PM PDT 24
Peak memory 206248 kb
Host smart-7b9e0f22-b40d-486e-be8e-1f1a1a468660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40364
79797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.4036479797
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.771316561
Short name T333
Test name
Test status
Simulation time 154131413 ps
CPU time 0.79 seconds
Started Jun 27 06:40:45 PM PDT 24
Finished Jun 27 06:41:25 PM PDT 24
Peak memory 206436 kb
Host smart-999d67e0-1174-47d8-90a6-88f1abfebd47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77131
6561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.771316561
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.3460682713
Short name T336
Test name
Test status
Simulation time 150299251 ps
CPU time 0.78 seconds
Started Jun 27 06:41:02 PM PDT 24
Finished Jun 27 06:42:01 PM PDT 24
Peak memory 205924 kb
Host smart-458f99de-5f67-4883-b8ca-0eb0ba28a30a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34606
82713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.3460682713
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.1182347039
Short name T658
Test name
Test status
Simulation time 254066480 ps
CPU time 0.89 seconds
Started Jun 27 06:41:02 PM PDT 24
Finished Jun 27 06:42:01 PM PDT 24
Peak memory 206304 kb
Host smart-bda7096a-b89a-443d-9075-fe4c89ffdaaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11823
47039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.1182347039
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.624904539
Short name T842
Test name
Test status
Simulation time 4736092144 ps
CPU time 130.44 seconds
Started Jun 27 06:40:44 PM PDT 24
Finished Jun 27 06:43:29 PM PDT 24
Peak memory 206432 kb
Host smart-1bd8df68-813b-4b0c-a655-77aa240b55dc
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=624904539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.624904539
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.639112482
Short name T2075
Test name
Test status
Simulation time 169807203 ps
CPU time 0.78 seconds
Started Jun 27 06:41:02 PM PDT 24
Finished Jun 27 06:42:01 PM PDT 24
Peak memory 206288 kb
Host smart-4b78e50c-4804-4693-9378-495775437a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63911
2482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.639112482
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.3616690245
Short name T102
Test name
Test status
Simulation time 152822383 ps
CPU time 0.81 seconds
Started Jun 27 06:40:44 PM PDT 24
Finished Jun 27 06:41:20 PM PDT 24
Peak memory 206228 kb
Host smart-470cdc8c-35ae-4f44-89f4-76fbd731ff18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36166
90245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.3616690245
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.4234698653
Short name T1018
Test name
Test status
Simulation time 7521759446 ps
CPU time 67.53 seconds
Started Jun 27 06:41:02 PM PDT 24
Finished Jun 27 06:43:07 PM PDT 24
Peak memory 206388 kb
Host smart-f5018831-3009-49d6-80b2-c61c8b1a0c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42346
98653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.4234698653
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.3506146884
Short name T757
Test name
Test status
Simulation time 55614784 ps
CPU time 0.69 seconds
Started Jun 27 06:35:09 PM PDT 24
Finished Jun 27 06:35:15 PM PDT 24
Peak memory 206356 kb
Host smart-e9ad8981-12ee-449d-8b1c-9f19e1f5db91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3506146884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.3506146884
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.2750281891
Short name T509
Test name
Test status
Simulation time 3698449682 ps
CPU time 4.45 seconds
Started Jun 27 06:34:51 PM PDT 24
Finished Jun 27 06:35:06 PM PDT 24
Peak memory 206348 kb
Host smart-72efa5cc-e8de-43f3-a200-fd724b91fcbf
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2750281891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.2750281891
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.3858096242
Short name T2570
Test name
Test status
Simulation time 13317469290 ps
CPU time 12.79 seconds
Started Jun 27 06:34:57 PM PDT 24
Finished Jun 27 06:35:20 PM PDT 24
Peak memory 206256 kb
Host smart-6b49af85-3127-4760-8de9-bb2d050b7784
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3858096242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.3858096242
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.2627150236
Short name T1113
Test name
Test status
Simulation time 23369195918 ps
CPU time 25.69 seconds
Started Jun 27 06:34:53 PM PDT 24
Finished Jun 27 06:35:29 PM PDT 24
Peak memory 206344 kb
Host smart-d0ba0ff4-37ee-4ba3-aeb0-bade147ea269
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2627150236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.2627150236
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.2673805910
Short name T745
Test name
Test status
Simulation time 166023929 ps
CPU time 0.8 seconds
Started Jun 27 06:34:59 PM PDT 24
Finished Jun 27 06:35:08 PM PDT 24
Peak memory 206272 kb
Host smart-3a1f3727-22b9-48e8-bdf5-34f4518409a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26738
05910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.2673805910
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.3206970889
Short name T52
Test name
Test status
Simulation time 155715644 ps
CPU time 0.78 seconds
Started Jun 27 06:34:53 PM PDT 24
Finished Jun 27 06:35:05 PM PDT 24
Peak memory 206288 kb
Host smart-5aaea2a4-00d7-42b6-ad70-544194a65191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32069
70889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.3206970889
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.618802538
Short name T86
Test name
Test status
Simulation time 163429285 ps
CPU time 0.81 seconds
Started Jun 27 06:34:51 PM PDT 24
Finished Jun 27 06:35:03 PM PDT 24
Peak memory 206264 kb
Host smart-6a139317-cbb8-40b9-9880-57671112d684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61880
2538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.618802538
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.1140923577
Short name T1103
Test name
Test status
Simulation time 152618224 ps
CPU time 0.77 seconds
Started Jun 27 06:34:53 PM PDT 24
Finished Jun 27 06:35:04 PM PDT 24
Peak memory 206276 kb
Host smart-1340dc26-c321-49f3-be25-ad7e5a0454e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11409
23577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.1140923577
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.956883210
Short name T1876
Test name
Test status
Simulation time 354353062 ps
CPU time 1.21 seconds
Started Jun 27 06:34:51 PM PDT 24
Finished Jun 27 06:35:03 PM PDT 24
Peak memory 206280 kb
Host smart-d342638b-45cc-4f84-8625-39b8a27fe80e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95688
3210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.956883210
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.3778072320
Short name T568
Test name
Test status
Simulation time 297549197 ps
CPU time 0.91 seconds
Started Jun 27 06:35:03 PM PDT 24
Finished Jun 27 06:35:10 PM PDT 24
Peak memory 206288 kb
Host smart-74060054-0597-4429-b2d6-98b84f2417ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37780
72320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.3778072320
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.3336442505
Short name T2155
Test name
Test status
Simulation time 19329450587 ps
CPU time 35.35 seconds
Started Jun 27 06:34:52 PM PDT 24
Finished Jun 27 06:35:38 PM PDT 24
Peak memory 206408 kb
Host smart-b2003f09-f316-41df-a113-ac6761e0bf8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33364
42505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.3336442505
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.1381351981
Short name T732
Test name
Test status
Simulation time 330401536 ps
CPU time 1.12 seconds
Started Jun 27 06:34:52 PM PDT 24
Finished Jun 27 06:35:04 PM PDT 24
Peak memory 206296 kb
Host smart-1b12cadb-4cc5-42ec-b170-2671f6b135fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13813
51981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.1381351981
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.340513282
Short name T2461
Test name
Test status
Simulation time 194706246 ps
CPU time 0.8 seconds
Started Jun 27 06:34:54 PM PDT 24
Finished Jun 27 06:35:05 PM PDT 24
Peak memory 206268 kb
Host smart-beb2922a-5de4-4c7d-8184-28e087abf849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34051
3282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.340513282
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.1850393047
Short name T1428
Test name
Test status
Simulation time 39344196 ps
CPU time 0.66 seconds
Started Jun 27 06:34:55 PM PDT 24
Finished Jun 27 06:35:06 PM PDT 24
Peak memory 206276 kb
Host smart-f6156550-7a47-4ee5-b2ba-a53ba9fae38e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18503
93047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.1850393047
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.2879896792
Short name T1771
Test name
Test status
Simulation time 935812402 ps
CPU time 2.22 seconds
Started Jun 27 06:34:53 PM PDT 24
Finished Jun 27 06:35:06 PM PDT 24
Peak memory 206436 kb
Host smart-b97aed03-4ff2-4282-b455-d2800d0be1ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28798
96792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.2879896792
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.1842468867
Short name T1702
Test name
Test status
Simulation time 156899554 ps
CPU time 1.26 seconds
Started Jun 27 06:35:03 PM PDT 24
Finished Jun 27 06:35:11 PM PDT 24
Peak memory 206364 kb
Host smart-d685fe34-a916-470d-9293-f80cda424cec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18424
68867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.1842468867
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.3670573034
Short name T556
Test name
Test status
Simulation time 221198167 ps
CPU time 0.84 seconds
Started Jun 27 06:35:03 PM PDT 24
Finished Jun 27 06:35:11 PM PDT 24
Peak memory 206288 kb
Host smart-6495fe2a-4488-4e34-ab5e-1a30369bf42e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36705
73034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.3670573034
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.3514029675
Short name T2603
Test name
Test status
Simulation time 139940211 ps
CPU time 0.75 seconds
Started Jun 27 06:34:53 PM PDT 24
Finished Jun 27 06:35:04 PM PDT 24
Peak memory 206288 kb
Host smart-bc4562be-bf3c-4aa0-a46f-2538c05948c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35140
29675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.3514029675
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.3912158226
Short name T1578
Test name
Test status
Simulation time 223477873 ps
CPU time 0.9 seconds
Started Jun 27 06:35:04 PM PDT 24
Finished Jun 27 06:35:12 PM PDT 24
Peak memory 206236 kb
Host smart-5fd3e757-493b-406a-8233-d8fde8796154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39121
58226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.3912158226
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_invalid_sync.571816686
Short name T2106
Test name
Test status
Simulation time 5345950464 ps
CPU time 47.45 seconds
Started Jun 27 06:34:56 PM PDT 24
Finished Jun 27 06:35:53 PM PDT 24
Peak memory 206488 kb
Host smart-9b10a4f4-da35-4ed4-8342-77f34da34bcf
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=571816686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_invalid_sync.571816686
Directory /workspace/4.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.1668316455
Short name T2206
Test name
Test status
Simulation time 182091767 ps
CPU time 0.86 seconds
Started Jun 27 06:34:54 PM PDT 24
Finished Jun 27 06:35:05 PM PDT 24
Peak memory 206280 kb
Host smart-a55ed344-7855-42ea-bcdf-d9dedf10b565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16683
16455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.1668316455
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.3746870430
Short name T1222
Test name
Test status
Simulation time 23319793564 ps
CPU time 24.58 seconds
Started Jun 27 06:34:57 PM PDT 24
Finished Jun 27 06:35:32 PM PDT 24
Peak memory 206344 kb
Host smart-25aa9257-6f66-447d-8fb9-0956b1ab4ca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37468
70430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.3746870430
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.1115954351
Short name T1349
Test name
Test status
Simulation time 3350714435 ps
CPU time 3.7 seconds
Started Jun 27 06:34:52 PM PDT 24
Finished Jun 27 06:35:06 PM PDT 24
Peak memory 206340 kb
Host smart-e52ef56a-4d55-4f80-923b-1ad611771216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11159
54351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.1115954351
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.913753557
Short name T423
Test name
Test status
Simulation time 8590514822 ps
CPU time 66.29 seconds
Started Jun 27 06:34:53 PM PDT 24
Finished Jun 27 06:36:10 PM PDT 24
Peak memory 206472 kb
Host smart-20c10936-0f57-43bd-ad9e-c17f67836c1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91375
3557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.913753557
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.2614731483
Short name T2482
Test name
Test status
Simulation time 5503912399 ps
CPU time 35.98 seconds
Started Jun 27 06:35:03 PM PDT 24
Finished Jun 27 06:35:46 PM PDT 24
Peak memory 206384 kb
Host smart-19093fd6-ab9c-4d68-9067-c29e50fc64a2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2614731483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.2614731483
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.4176313877
Short name T2582
Test name
Test status
Simulation time 243056080 ps
CPU time 0.92 seconds
Started Jun 27 06:34:54 PM PDT 24
Finished Jun 27 06:35:05 PM PDT 24
Peak memory 206300 kb
Host smart-790d70fe-ee3b-43c1-9e64-b7c1b6855ba7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4176313877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.4176313877
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.3798134708
Short name T2259
Test name
Test status
Simulation time 249680885 ps
CPU time 0.91 seconds
Started Jun 27 06:35:04 PM PDT 24
Finished Jun 27 06:35:12 PM PDT 24
Peak memory 206276 kb
Host smart-d09cdadc-d93c-4c7b-ba41-527e94a344e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37981
34708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.3798134708
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.3994642204
Short name T1706
Test name
Test status
Simulation time 4813228805 ps
CPU time 125.76 seconds
Started Jun 27 06:34:52 PM PDT 24
Finished Jun 27 06:37:09 PM PDT 24
Peak memory 206440 kb
Host smart-ef229082-ef3d-487c-b943-ba414553c740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39946
42204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.3994642204
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.2958482583
Short name T427
Test name
Test status
Simulation time 5027806046 ps
CPU time 35.47 seconds
Started Jun 27 06:34:58 PM PDT 24
Finished Jun 27 06:35:43 PM PDT 24
Peak memory 206500 kb
Host smart-7459b1e8-d6f2-417e-9c25-a146909580b2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2958482583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.2958482583
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.2358089462
Short name T689
Test name
Test status
Simulation time 154473394 ps
CPU time 0.77 seconds
Started Jun 27 06:34:52 PM PDT 24
Finished Jun 27 06:35:04 PM PDT 24
Peak memory 206248 kb
Host smart-7427fe3d-edd9-4cde-b754-8b888089f4d1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2358089462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.2358089462
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.3234416875
Short name T760
Test name
Test status
Simulation time 146537755 ps
CPU time 0.78 seconds
Started Jun 27 06:34:56 PM PDT 24
Finished Jun 27 06:35:06 PM PDT 24
Peak memory 206276 kb
Host smart-87ffa896-94a3-4b51-b4ef-2d6bb7e64af6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32344
16875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.3234416875
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.217174677
Short name T113
Test name
Test status
Simulation time 231475661 ps
CPU time 0.88 seconds
Started Jun 27 06:34:55 PM PDT 24
Finished Jun 27 06:35:06 PM PDT 24
Peak memory 206288 kb
Host smart-2e400b7c-fbe9-4512-90cc-142a7605aa69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21717
4677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.217174677
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.2252343531
Short name T1597
Test name
Test status
Simulation time 201906740 ps
CPU time 0.87 seconds
Started Jun 27 06:34:57 PM PDT 24
Finished Jun 27 06:35:08 PM PDT 24
Peak memory 206296 kb
Host smart-058f7d01-20d1-4225-8823-3c81b6c671ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22523
43531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.2252343531
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.3373809375
Short name T1000
Test name
Test status
Simulation time 174885609 ps
CPU time 0.77 seconds
Started Jun 27 06:34:55 PM PDT 24
Finished Jun 27 06:35:05 PM PDT 24
Peak memory 206272 kb
Host smart-5933ee6d-a7de-40db-929b-ec46229e9c7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33738
09375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.3373809375
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.1299289069
Short name T618
Test name
Test status
Simulation time 187947657 ps
CPU time 0.85 seconds
Started Jun 27 06:34:56 PM PDT 24
Finished Jun 27 06:35:07 PM PDT 24
Peak memory 206272 kb
Host smart-8e202912-c2b5-4f14-b683-a55fcf02a063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12992
89069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.1299289069
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.2916987303
Short name T1227
Test name
Test status
Simulation time 208615659 ps
CPU time 0.86 seconds
Started Jun 27 06:34:52 PM PDT 24
Finished Jun 27 06:35:03 PM PDT 24
Peak memory 206248 kb
Host smart-aed3a125-57c2-426d-908d-b50bd73bc86b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29169
87303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.2916987303
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.2231271098
Short name T1630
Test name
Test status
Simulation time 225717847 ps
CPU time 0.99 seconds
Started Jun 27 06:34:55 PM PDT 24
Finished Jun 27 06:35:06 PM PDT 24
Peak memory 206292 kb
Host smart-acf387d8-ef8b-44b8-acb2-dfadc552816d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2231271098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.2231271098
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.3310410117
Short name T1721
Test name
Test status
Simulation time 203101822 ps
CPU time 0.94 seconds
Started Jun 27 06:35:11 PM PDT 24
Finished Jun 27 06:35:17 PM PDT 24
Peak memory 206280 kb
Host smart-3054dab2-d605-4f6f-950c-ab20a71812b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33104
10117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.3310410117
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.1947836722
Short name T2135
Test name
Test status
Simulation time 142286779 ps
CPU time 0.76 seconds
Started Jun 27 06:35:11 PM PDT 24
Finished Jun 27 06:35:16 PM PDT 24
Peak memory 206268 kb
Host smart-11176758-b64a-45d6-8ccf-a9f4f95b6cd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19478
36722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.1947836722
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.1527275026
Short name T2429
Test name
Test status
Simulation time 46913308 ps
CPU time 0.63 seconds
Started Jun 27 06:35:12 PM PDT 24
Finished Jun 27 06:35:18 PM PDT 24
Peak memory 206252 kb
Host smart-22a1e043-a047-4078-8dd5-194285b8f6eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15272
75026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.1527275026
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.2300436144
Short name T2137
Test name
Test status
Simulation time 5878775484 ps
CPU time 14.09 seconds
Started Jun 27 06:35:09 PM PDT 24
Finished Jun 27 06:35:28 PM PDT 24
Peak memory 206452 kb
Host smart-f3d40944-b2ab-45d9-b32e-a1e1ad29d243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23004
36144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.2300436144
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.4179717435
Short name T2203
Test name
Test status
Simulation time 179194031 ps
CPU time 0.83 seconds
Started Jun 27 06:35:10 PM PDT 24
Finished Jun 27 06:35:16 PM PDT 24
Peak memory 206164 kb
Host smart-d7284990-bd0f-4ee0-a98c-18312b1547e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41797
17435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.4179717435
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.581621114
Short name T1352
Test name
Test status
Simulation time 232366532 ps
CPU time 0.87 seconds
Started Jun 27 06:35:12 PM PDT 24
Finished Jun 27 06:35:18 PM PDT 24
Peak memory 206296 kb
Host smart-5a6f8b6c-0488-4c29-9791-6fbc02f2ae97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58162
1114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.581621114
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.2973095665
Short name T438
Test name
Test status
Simulation time 14045473973 ps
CPU time 120.77 seconds
Started Jun 27 06:35:15 PM PDT 24
Finished Jun 27 06:37:21 PM PDT 24
Peak memory 206420 kb
Host smart-5e230fad-e209-4a5e-ad23-c88e6c097ea3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2973095665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.2973095665
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.3104754177
Short name T42
Test name
Test status
Simulation time 13707785023 ps
CPU time 123 seconds
Started Jun 27 06:35:08 PM PDT 24
Finished Jun 27 06:37:17 PM PDT 24
Peak memory 206476 kb
Host smart-3e96e94c-da16-4ecc-bf89-00aa704f8951
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3104754177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.3104754177
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.1723532458
Short name T1052
Test name
Test status
Simulation time 11993422098 ps
CPU time 224.85 seconds
Started Jun 27 06:35:10 PM PDT 24
Finished Jun 27 06:39:00 PM PDT 24
Peak memory 206408 kb
Host smart-dbc50eb8-efe1-456d-be7f-55c7f963c812
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1723532458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.1723532458
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.4169025327
Short name T578
Test name
Test status
Simulation time 247112574 ps
CPU time 0.93 seconds
Started Jun 27 06:35:08 PM PDT 24
Finished Jun 27 06:35:15 PM PDT 24
Peak memory 206268 kb
Host smart-193cd480-d766-4702-90bf-74cffcac7f84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41690
25327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.4169025327
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.926599099
Short name T1689
Test name
Test status
Simulation time 180247921 ps
CPU time 0.83 seconds
Started Jun 27 06:35:10 PM PDT 24
Finished Jun 27 06:35:16 PM PDT 24
Peak memory 206272 kb
Host smart-df3b419d-5f02-4df2-970c-f5653d6dcf79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92659
9099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.926599099
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.506020499
Short name T2158
Test name
Test status
Simulation time 143942475 ps
CPU time 0.74 seconds
Started Jun 27 06:35:09 PM PDT 24
Finished Jun 27 06:35:16 PM PDT 24
Peak memory 206284 kb
Host smart-fa2944e3-cba5-4ca3-b03a-a7c8ccfd1e99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50602
0499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.506020499
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.3036655874
Short name T77
Test name
Test status
Simulation time 152989574 ps
CPU time 0.77 seconds
Started Jun 27 06:35:10 PM PDT 24
Finished Jun 27 06:35:16 PM PDT 24
Peak memory 206272 kb
Host smart-ff328709-7355-4c02-a06f-6789c2fe03b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30366
55874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.3036655874
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.4122395245
Short name T2240
Test name
Test status
Simulation time 456897009 ps
CPU time 1.39 seconds
Started Jun 27 06:35:13 PM PDT 24
Finished Jun 27 06:35:20 PM PDT 24
Peak memory 206264 kb
Host smart-861df1fb-d385-4bcf-bf47-fc41f54cddf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41223
95245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.4122395245
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.840910321
Short name T1962
Test name
Test status
Simulation time 187098732 ps
CPU time 0.78 seconds
Started Jun 27 06:35:11 PM PDT 24
Finished Jun 27 06:35:17 PM PDT 24
Peak memory 206276 kb
Host smart-2ba12dcf-4e5d-4603-ad34-00677ac61981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84091
0321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.840910321
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.3680592024
Short name T769
Test name
Test status
Simulation time 159984411 ps
CPU time 0.8 seconds
Started Jun 27 06:35:12 PM PDT 24
Finished Jun 27 06:35:18 PM PDT 24
Peak memory 206436 kb
Host smart-c85103f7-20df-4b23-a2fc-ee81cf3eb9de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36805
92024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.3680592024
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.2049278044
Short name T2509
Test name
Test status
Simulation time 209694144 ps
CPU time 0.93 seconds
Started Jun 27 06:35:15 PM PDT 24
Finished Jun 27 06:35:21 PM PDT 24
Peak memory 206264 kb
Host smart-ca1eb448-f3cd-492e-bd71-90977106cd8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20492
78044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.2049278044
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.3823478037
Short name T1808
Test name
Test status
Simulation time 4689273105 ps
CPU time 34.72 seconds
Started Jun 27 06:35:12 PM PDT 24
Finished Jun 27 06:35:52 PM PDT 24
Peak memory 206412 kb
Host smart-1f65e2a6-1731-4843-b908-0a664ecc3646
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3823478037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.3823478037
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.1140535769
Short name T1081
Test name
Test status
Simulation time 179119586 ps
CPU time 0.83 seconds
Started Jun 27 06:35:09 PM PDT 24
Finished Jun 27 06:35:15 PM PDT 24
Peak memory 206260 kb
Host smart-760c818d-2967-4188-9614-4016a8be18e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11405
35769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.1140535769
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.3814737458
Short name T322
Test name
Test status
Simulation time 154048113 ps
CPU time 0.81 seconds
Started Jun 27 06:35:14 PM PDT 24
Finished Jun 27 06:35:21 PM PDT 24
Peak memory 206272 kb
Host smart-4457f290-5ba9-4969-89d4-4f724a21757e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38147
37458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.3814737458
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.1498688027
Short name T1024
Test name
Test status
Simulation time 3405829995 ps
CPU time 25.72 seconds
Started Jun 27 06:35:10 PM PDT 24
Finished Jun 27 06:35:41 PM PDT 24
Peak memory 206312 kb
Host smart-168d8516-985d-495c-8985-25b2d37e9a54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14986
88027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.1498688027
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.73678302
Short name T154
Test name
Test status
Simulation time 10894300026 ps
CPU time 51.27 seconds
Started Jun 27 06:35:10 PM PDT 24
Finished Jun 27 06:36:06 PM PDT 24
Peak memory 206492 kb
Host smart-e0330d79-92a9-4c71-95f3-b1abafad025f
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=73678302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.73678302
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.1445756143
Short name T1125
Test name
Test status
Simulation time 56047244 ps
CPU time 0.67 seconds
Started Jun 27 06:41:11 PM PDT 24
Finished Jun 27 06:42:10 PM PDT 24
Peak memory 206364 kb
Host smart-d28c5fcb-23f9-4674-a498-b877c8382851
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1445756143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.1445756143
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.2107432660
Short name T2527
Test name
Test status
Simulation time 3666816102 ps
CPU time 4.78 seconds
Started Jun 27 06:40:51 PM PDT 24
Finished Jun 27 06:41:43 PM PDT 24
Peak memory 206284 kb
Host smart-ae434f46-1048-4434-b3b0-cdd3731cc699
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2107432660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.2107432660
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.4112354119
Short name T1397
Test name
Test status
Simulation time 13354719290 ps
CPU time 12.99 seconds
Started Jun 27 06:40:55 PM PDT 24
Finished Jun 27 06:42:02 PM PDT 24
Peak memory 206468 kb
Host smart-89926c07-6492-4962-9db0-5cba42165275
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4112354119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.4112354119
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.752957054
Short name T1738
Test name
Test status
Simulation time 23375704614 ps
CPU time 27.17 seconds
Started Jun 27 06:40:46 PM PDT 24
Finished Jun 27 06:41:55 PM PDT 24
Peak memory 206540 kb
Host smart-e3cf958e-d369-4d8f-b90f-30cb881e90af
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=752957054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.752957054
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.1624689978
Short name T1184
Test name
Test status
Simulation time 173994121 ps
CPU time 0.82 seconds
Started Jun 27 06:40:56 PM PDT 24
Finished Jun 27 06:41:50 PM PDT 24
Peak memory 206284 kb
Host smart-afba8d85-a9a7-443f-894f-d213c5b09605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16246
89978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.1624689978
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.3755752460
Short name T1010
Test name
Test status
Simulation time 168250431 ps
CPU time 0.81 seconds
Started Jun 27 06:40:43 PM PDT 24
Finished Jun 27 06:41:15 PM PDT 24
Peak memory 206252 kb
Host smart-b3d33457-f5b8-4402-8c85-093a5f24b52f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37557
52460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.3755752460
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.1608805967
Short name T492
Test name
Test status
Simulation time 264859599 ps
CPU time 1 seconds
Started Jun 27 06:40:53 PM PDT 24
Finished Jun 27 06:41:44 PM PDT 24
Peak memory 206236 kb
Host smart-862d4303-e1a2-4670-9dc2-1344327d8183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16088
05967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.1608805967
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.3347385690
Short name T2496
Test name
Test status
Simulation time 1546833395 ps
CPU time 3.06 seconds
Started Jun 27 06:40:52 PM PDT 24
Finished Jun 27 06:41:41 PM PDT 24
Peak memory 206396 kb
Host smart-32259d83-e5e6-4420-bd0e-19597e63ad8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33473
85690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.3347385690
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.2187529978
Short name T92
Test name
Test status
Simulation time 21651333129 ps
CPU time 40.25 seconds
Started Jun 27 06:40:50 PM PDT 24
Finished Jun 27 06:42:18 PM PDT 24
Peak memory 206372 kb
Host smart-d8b4dabd-a489-40d6-a174-1a1cd08ca6f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21875
29978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.2187529978
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.3468764532
Short name T402
Test name
Test status
Simulation time 456924291 ps
CPU time 1.3 seconds
Started Jun 27 06:40:55 PM PDT 24
Finished Jun 27 06:41:50 PM PDT 24
Peak memory 206216 kb
Host smart-05ce432f-ca2d-4f94-a606-e7cab161b58e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34687
64532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.3468764532
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.3000086379
Short name T846
Test name
Test status
Simulation time 140068769 ps
CPU time 0.73 seconds
Started Jun 27 06:40:56 PM PDT 24
Finished Jun 27 06:41:50 PM PDT 24
Peak memory 206280 kb
Host smart-89397d28-b4a9-4560-85fb-4e23515dffd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30000
86379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.3000086379
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.1074451630
Short name T1131
Test name
Test status
Simulation time 39993322 ps
CPU time 0.66 seconds
Started Jun 27 06:40:55 PM PDT 24
Finished Jun 27 06:41:50 PM PDT 24
Peak memory 206252 kb
Host smart-3ff2d5c1-769e-447c-838f-d7c2d736b49e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10744
51630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.1074451630
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.130680018
Short name T1072
Test name
Test status
Simulation time 964729425 ps
CPU time 2.1 seconds
Started Jun 27 06:41:11 PM PDT 24
Finished Jun 27 06:42:11 PM PDT 24
Peak memory 206412 kb
Host smart-ec5cb9ef-a72a-446a-a056-141b74564cc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13068
0018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.130680018
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.1513909625
Short name T1751
Test name
Test status
Simulation time 226093854 ps
CPU time 1.32 seconds
Started Jun 27 06:41:12 PM PDT 24
Finished Jun 27 06:42:11 PM PDT 24
Peak memory 206372 kb
Host smart-62d928bc-27a1-4c58-a448-87a80ff6f00b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15139
09625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.1513909625
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.1679285879
Short name T1305
Test name
Test status
Simulation time 184793443 ps
CPU time 0.84 seconds
Started Jun 27 06:41:13 PM PDT 24
Finished Jun 27 06:42:11 PM PDT 24
Peak memory 205888 kb
Host smart-8eaf8f17-8fcc-4434-9a5c-58de22a31dbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16792
85879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.1679285879
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.2564111419
Short name T1542
Test name
Test status
Simulation time 138567670 ps
CPU time 0.75 seconds
Started Jun 27 06:41:12 PM PDT 24
Finished Jun 27 06:42:11 PM PDT 24
Peak memory 206292 kb
Host smart-586768c8-c6c3-49a4-8ff9-62e8d2b02d3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25641
11419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.2564111419
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.1760245854
Short name T331
Test name
Test status
Simulation time 157437821 ps
CPU time 0.77 seconds
Started Jun 27 06:41:14 PM PDT 24
Finished Jun 27 06:42:11 PM PDT 24
Peak memory 206252 kb
Host smart-80cdafcf-c4ae-42fb-b163-c1b090b4f048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17602
45854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.1760245854
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.2602911690
Short name T1337
Test name
Test status
Simulation time 157053298 ps
CPU time 0.76 seconds
Started Jun 27 06:41:15 PM PDT 24
Finished Jun 27 06:42:14 PM PDT 24
Peak memory 206252 kb
Host smart-571698fd-c7b6-4423-bdcb-b7e8deb90c6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26029
11690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.2602911690
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.3198385609
Short name T1055
Test name
Test status
Simulation time 23294517455 ps
CPU time 28.19 seconds
Started Jun 27 06:41:15 PM PDT 24
Finished Jun 27 06:42:41 PM PDT 24
Peak memory 206316 kb
Host smart-3de59d5a-c958-4dbb-b363-abd91562b175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31983
85609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.3198385609
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.1578025007
Short name T1298
Test name
Test status
Simulation time 3314114219 ps
CPU time 3.54 seconds
Started Jun 27 06:41:14 PM PDT 24
Finished Jun 27 06:42:17 PM PDT 24
Peak memory 206316 kb
Host smart-74155332-515d-4a0c-92f3-c8d34a46c809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15780
25007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.1578025007
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.2807272148
Short name T996
Test name
Test status
Simulation time 6700636534 ps
CPU time 58.04 seconds
Started Jun 27 06:41:12 PM PDT 24
Finished Jun 27 06:43:08 PM PDT 24
Peak memory 206468 kb
Host smart-057fdea1-5957-4dfe-9360-4ad96fdca51e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28072
72148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.2807272148
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.1910485357
Short name T1331
Test name
Test status
Simulation time 3628423713 ps
CPU time 97.36 seconds
Started Jun 27 06:41:12 PM PDT 24
Finished Jun 27 06:43:47 PM PDT 24
Peak memory 206436 kb
Host smart-99a10d5c-b636-4895-b574-5ee3b1fc8436
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1910485357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.1910485357
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.559915644
Short name T2551
Test name
Test status
Simulation time 238872221 ps
CPU time 0.88 seconds
Started Jun 27 06:41:10 PM PDT 24
Finished Jun 27 06:42:07 PM PDT 24
Peak memory 206228 kb
Host smart-df1e7721-b0d2-49ca-978e-2a8a15263baa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=559915644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.559915644
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.3286162737
Short name T1207
Test name
Test status
Simulation time 196007905 ps
CPU time 0.84 seconds
Started Jun 27 06:41:16 PM PDT 24
Finished Jun 27 06:42:15 PM PDT 24
Peak memory 206284 kb
Host smart-3e5a6d12-e156-4279-a3c9-4d712dcaf972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32861
62737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.3286162737
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.1207321532
Short name T1406
Test name
Test status
Simulation time 5723376020 ps
CPU time 47.86 seconds
Started Jun 27 06:41:17 PM PDT 24
Finished Jun 27 06:43:02 PM PDT 24
Peak memory 206456 kb
Host smart-f7c017fc-23b2-4328-b36d-29b7f338f045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12073
21532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.1207321532
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.589651135
Short name T1583
Test name
Test status
Simulation time 4756573942 ps
CPU time 32.53 seconds
Started Jun 27 06:41:17 PM PDT 24
Finished Jun 27 06:42:46 PM PDT 24
Peak memory 206484 kb
Host smart-d88048ae-f766-4b6e-a679-874eb8e67796
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=589651135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.589651135
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.2777091811
Short name T1916
Test name
Test status
Simulation time 174938745 ps
CPU time 0.81 seconds
Started Jun 27 06:41:10 PM PDT 24
Finished Jun 27 06:42:07 PM PDT 24
Peak memory 206300 kb
Host smart-d04e349a-9e04-42c5-96b1-7742c3a55ace
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2777091811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.2777091811
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.1984886212
Short name T695
Test name
Test status
Simulation time 156291068 ps
CPU time 0.8 seconds
Started Jun 27 06:41:13 PM PDT 24
Finished Jun 27 06:42:11 PM PDT 24
Peak memory 205880 kb
Host smart-f1381b08-1c9f-461b-8de6-0fff71abdca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19848
86212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.1984886212
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.951206737
Short name T137
Test name
Test status
Simulation time 214538147 ps
CPU time 0.88 seconds
Started Jun 27 06:41:16 PM PDT 24
Finished Jun 27 06:42:15 PM PDT 24
Peak memory 206248 kb
Host smart-4b43ef7a-9eea-4d35-98a3-4bf04f84a16b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95120
6737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.951206737
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.2968215926
Short name T1699
Test name
Test status
Simulation time 151532143 ps
CPU time 0.76 seconds
Started Jun 27 06:41:15 PM PDT 24
Finished Jun 27 06:42:15 PM PDT 24
Peak memory 206304 kb
Host smart-d7d1e161-c9fa-4fa2-ad7a-224081ce254e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29682
15926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.2968215926
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.2931408424
Short name T2163
Test name
Test status
Simulation time 151690107 ps
CPU time 0.73 seconds
Started Jun 27 06:41:13 PM PDT 24
Finished Jun 27 06:42:11 PM PDT 24
Peak memory 206224 kb
Host smart-97c5ca27-1d61-47e0-b803-516e9ca1ba62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29314
08424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.2931408424
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.1836896509
Short name T2251
Test name
Test status
Simulation time 164580070 ps
CPU time 0.8 seconds
Started Jun 27 06:41:12 PM PDT 24
Finished Jun 27 06:42:11 PM PDT 24
Peak memory 206284 kb
Host smart-1d75fce3-9069-4702-ba6f-426d3aaae135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18368
96509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.1836896509
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.3862262311
Short name T857
Test name
Test status
Simulation time 160273909 ps
CPU time 0.74 seconds
Started Jun 27 06:41:16 PM PDT 24
Finished Jun 27 06:42:15 PM PDT 24
Peak memory 206292 kb
Host smart-20702b5f-057b-47b4-a9be-d60935968cf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38622
62311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.3862262311
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.720406456
Short name T616
Test name
Test status
Simulation time 245243291 ps
CPU time 0.88 seconds
Started Jun 27 06:41:14 PM PDT 24
Finished Jun 27 06:42:14 PM PDT 24
Peak memory 206272 kb
Host smart-245c922b-5d9e-4c4b-b17a-30f79db97a09
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=720406456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.720406456
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.2639931945
Short name T567
Test name
Test status
Simulation time 140873592 ps
CPU time 0.74 seconds
Started Jun 27 06:41:13 PM PDT 24
Finished Jun 27 06:42:11 PM PDT 24
Peak memory 206260 kb
Host smart-a49219c8-23de-4940-9956-569de81c7c3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26399
31945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.2639931945
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.884444766
Short name T1546
Test name
Test status
Simulation time 61279349 ps
CPU time 0.68 seconds
Started Jun 27 06:41:14 PM PDT 24
Finished Jun 27 06:42:13 PM PDT 24
Peak memory 206156 kb
Host smart-3cd9d929-ffdf-4ba1-9b28-a09d136c0656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88444
4766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.884444766
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.2123197293
Short name T2055
Test name
Test status
Simulation time 22698880874 ps
CPU time 46.67 seconds
Started Jun 27 06:41:13 PM PDT 24
Finished Jun 27 06:42:57 PM PDT 24
Peak memory 206392 kb
Host smart-414d4c2f-a869-4f18-908e-0f6ce267f140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21231
97293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.2123197293
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.3153284187
Short name T1261
Test name
Test status
Simulation time 198024343 ps
CPU time 0.85 seconds
Started Jun 27 06:41:14 PM PDT 24
Finished Jun 27 06:42:14 PM PDT 24
Peak memory 206172 kb
Host smart-d9b96bab-d16d-4fef-8fd1-35a8a5fc5b31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31532
84187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.3153284187
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.441933231
Short name T1498
Test name
Test status
Simulation time 239947235 ps
CPU time 0.92 seconds
Started Jun 27 06:41:11 PM PDT 24
Finished Jun 27 06:42:10 PM PDT 24
Peak memory 206292 kb
Host smart-80ba2bf5-77a2-4c2a-8f2e-7189bb1743a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44193
3231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.441933231
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.2837353511
Short name T430
Test name
Test status
Simulation time 244151700 ps
CPU time 0.85 seconds
Started Jun 27 06:41:16 PM PDT 24
Finished Jun 27 06:42:15 PM PDT 24
Peak memory 206300 kb
Host smart-9f4db977-ffbb-4d07-8a00-25707e885bbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28373
53511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.2837353511
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.1665939434
Short name T1301
Test name
Test status
Simulation time 196450187 ps
CPU time 0.89 seconds
Started Jun 27 06:41:09 PM PDT 24
Finished Jun 27 06:42:07 PM PDT 24
Peak memory 206280 kb
Host smart-56c53fe6-071b-4373-b6d2-c42b91b0d7c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16659
39434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.1665939434
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.1255483864
Short name T508
Test name
Test status
Simulation time 161303909 ps
CPU time 0.73 seconds
Started Jun 27 06:41:11 PM PDT 24
Finished Jun 27 06:42:10 PM PDT 24
Peak memory 206268 kb
Host smart-724638a1-933d-4c07-8428-e1ca49231426
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12554
83864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.1255483864
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.2344582414
Short name T1995
Test name
Test status
Simulation time 169657114 ps
CPU time 0.74 seconds
Started Jun 27 06:41:17 PM PDT 24
Finished Jun 27 06:42:15 PM PDT 24
Peak memory 206276 kb
Host smart-cbdbf195-65b9-4fcb-bef7-1abd24a613b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23445
82414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.2344582414
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.4020699514
Short name T2394
Test name
Test status
Simulation time 140127713 ps
CPU time 0.78 seconds
Started Jun 27 06:41:17 PM PDT 24
Finished Jun 27 06:42:15 PM PDT 24
Peak memory 206216 kb
Host smart-cf14e965-0107-4b8d-87ed-6d446e81efa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40206
99514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.4020699514
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.1903876049
Short name T763
Test name
Test status
Simulation time 201238687 ps
CPU time 0.9 seconds
Started Jun 27 06:41:13 PM PDT 24
Finished Jun 27 06:42:11 PM PDT 24
Peak memory 206272 kb
Host smart-7a7edc54-5136-4466-a2e2-3772ce30837e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19038
76049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.1903876049
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.1156184845
Short name T955
Test name
Test status
Simulation time 5302172043 ps
CPU time 41.02 seconds
Started Jun 27 06:41:16 PM PDT 24
Finished Jun 27 06:42:55 PM PDT 24
Peak memory 206416 kb
Host smart-7b617cd3-4b17-4672-9840-ead290c4c066
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1156184845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.1156184845
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.4288684022
Short name T397
Test name
Test status
Simulation time 204259160 ps
CPU time 0.83 seconds
Started Jun 27 06:41:14 PM PDT 24
Finished Jun 27 06:42:14 PM PDT 24
Peak memory 206168 kb
Host smart-3e343363-9546-4734-b32b-73b06fc9e220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42886
84022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.4288684022
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.2524275749
Short name T2236
Test name
Test status
Simulation time 195729327 ps
CPU time 0.79 seconds
Started Jun 27 06:41:14 PM PDT 24
Finished Jun 27 06:42:14 PM PDT 24
Peak memory 206280 kb
Host smart-b1764114-553b-4b23-b4a6-845b3d3fa18e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25242
75749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.2524275749
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.2879046339
Short name T1412
Test name
Test status
Simulation time 4434709707 ps
CPU time 40.79 seconds
Started Jun 27 06:41:13 PM PDT 24
Finished Jun 27 06:42:51 PM PDT 24
Peak memory 206468 kb
Host smart-41ac4a55-879c-4668-bb39-46f5412b01e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28790
46339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.2879046339
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.3722092754
Short name T1091
Test name
Test status
Simulation time 39365813 ps
CPU time 0.63 seconds
Started Jun 27 06:41:27 PM PDT 24
Finished Jun 27 06:42:21 PM PDT 24
Peak memory 206356 kb
Host smart-def10294-61d2-4092-8ff1-54c594405737
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3722092754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.3722092754
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.3267314464
Short name T1666
Test name
Test status
Simulation time 4253257642 ps
CPU time 4.9 seconds
Started Jun 27 06:41:12 PM PDT 24
Finished Jun 27 06:42:15 PM PDT 24
Peak memory 206368 kb
Host smart-70816c7c-c86d-4fb6-9336-e469149e89eb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3267314464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.3267314464
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.510917940
Short name T392
Test name
Test status
Simulation time 13376942107 ps
CPU time 11.86 seconds
Started Jun 27 06:41:14 PM PDT 24
Finished Jun 27 06:42:25 PM PDT 24
Peak memory 206340 kb
Host smart-de0f425a-bc8b-44ad-bdda-a1e563f1975e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=510917940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.510917940
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.3821952837
Short name T13
Test name
Test status
Simulation time 23438656460 ps
CPU time 23.28 seconds
Started Jun 27 06:41:16 PM PDT 24
Finished Jun 27 06:42:37 PM PDT 24
Peak memory 206420 kb
Host smart-6f67084a-1da6-4a88-9144-e7b3ff1fbe88
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3821952837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.3821952837
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.1575221697
Short name T219
Test name
Test status
Simulation time 150587392 ps
CPU time 0.78 seconds
Started Jun 27 06:41:16 PM PDT 24
Finished Jun 27 06:42:15 PM PDT 24
Peak memory 206284 kb
Host smart-d43d8155-255d-4404-b32d-71af899dfd04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15752
21697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.1575221697
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.1044142018
Short name T1152
Test name
Test status
Simulation time 146581267 ps
CPU time 0.79 seconds
Started Jun 27 06:41:11 PM PDT 24
Finished Jun 27 06:42:10 PM PDT 24
Peak memory 206432 kb
Host smart-3ecd4230-3dd5-4d38-9b3f-fc5b9ea73e11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10441
42018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.1044142018
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.1650644956
Short name T1079
Test name
Test status
Simulation time 492336854 ps
CPU time 1.5 seconds
Started Jun 27 06:41:12 PM PDT 24
Finished Jun 27 06:42:11 PM PDT 24
Peak memory 206276 kb
Host smart-3f8f9377-f937-4186-8dd3-282dea355b06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16506
44956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.1650644956
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.429394086
Short name T160
Test name
Test status
Simulation time 743356697 ps
CPU time 1.64 seconds
Started Jun 27 06:41:10 PM PDT 24
Finished Jun 27 06:42:08 PM PDT 24
Peak memory 206428 kb
Host smart-02364959-8387-48e6-a7b9-c5423c1b2aba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42939
4086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.429394086
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.685612183
Short name T217
Test name
Test status
Simulation time 9161334657 ps
CPU time 15.95 seconds
Started Jun 27 06:41:13 PM PDT 24
Finished Jun 27 06:42:26 PM PDT 24
Peak memory 206416 kb
Host smart-83a7e2c1-ea7c-4a74-a6d3-068f9d8584ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68561
2183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.685612183
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.1761328512
Short name T1202
Test name
Test status
Simulation time 407622556 ps
CPU time 1.36 seconds
Started Jun 27 06:41:09 PM PDT 24
Finished Jun 27 06:42:08 PM PDT 24
Peak memory 206268 kb
Host smart-7b1cfcc7-91c9-43df-a272-1be9f675779a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17613
28512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.1761328512
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.1983370188
Short name T638
Test name
Test status
Simulation time 142235180 ps
CPU time 0.75 seconds
Started Jun 27 06:41:17 PM PDT 24
Finished Jun 27 06:42:15 PM PDT 24
Peak memory 206188 kb
Host smart-42cd5a38-3d19-49eb-b5c0-cdad2cc6bd63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19833
70188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.1983370188
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.2922472208
Short name T555
Test name
Test status
Simulation time 55331817 ps
CPU time 0.7 seconds
Started Jun 27 06:41:09 PM PDT 24
Finished Jun 27 06:42:07 PM PDT 24
Peak memory 206284 kb
Host smart-c34b50b9-c3df-47e2-abdf-680fb3356ee5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29224
72208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.2922472208
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.2195697866
Short name T489
Test name
Test status
Simulation time 904426848 ps
CPU time 2.12 seconds
Started Jun 27 06:41:13 PM PDT 24
Finished Jun 27 06:42:12 PM PDT 24
Peak memory 206372 kb
Host smart-8f4ff3f6-f2c5-48f7-b4ad-5edf14af597b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21956
97866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.2195697866
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.1374281714
Short name T2332
Test name
Test status
Simulation time 308407759 ps
CPU time 1.58 seconds
Started Jun 27 06:41:13 PM PDT 24
Finished Jun 27 06:42:12 PM PDT 24
Peak memory 206440 kb
Host smart-beffc121-d7de-4ddb-b0d1-5d61f7c2e51c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13742
81714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.1374281714
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.1764000246
Short name T425
Test name
Test status
Simulation time 192467430 ps
CPU time 0.79 seconds
Started Jun 27 06:41:13 PM PDT 24
Finished Jun 27 06:42:11 PM PDT 24
Peak memory 206292 kb
Host smart-f1b5347c-6448-49d7-a97d-761f4ccb4d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17640
00246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.1764000246
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.2562589904
Short name T1829
Test name
Test status
Simulation time 141203595 ps
CPU time 0.73 seconds
Started Jun 27 06:41:13 PM PDT 24
Finished Jun 27 06:42:11 PM PDT 24
Peak memory 206292 kb
Host smart-d848c6d7-3456-480c-a24a-74b60abcc80f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25625
89904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.2562589904
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.2238533668
Short name T406
Test name
Test status
Simulation time 181768077 ps
CPU time 0.8 seconds
Started Jun 27 06:41:18 PM PDT 24
Finished Jun 27 06:42:15 PM PDT 24
Peak memory 206300 kb
Host smart-74f45172-3078-47d5-80e4-ec9ce6ba2759
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22385
33668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.2238533668
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_invalid_sync.4089546999
Short name T100
Test name
Test status
Simulation time 7692908446 ps
CPU time 197.55 seconds
Started Jun 27 06:41:16 PM PDT 24
Finished Jun 27 06:45:31 PM PDT 24
Peak memory 206500 kb
Host smart-c314b1b5-b324-4cb9-9c17-8f6ddf94dd9b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4089546999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.4089546999
Directory /workspace/41.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.133668706
Short name T32
Test name
Test status
Simulation time 190744732 ps
CPU time 0.84 seconds
Started Jun 27 06:41:18 PM PDT 24
Finished Jun 27 06:42:15 PM PDT 24
Peak memory 206272 kb
Host smart-533f62a7-d8d7-4de5-a332-2f003425537b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13366
8706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.133668706
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.1440232646
Short name T1611
Test name
Test status
Simulation time 23341421763 ps
CPU time 20.24 seconds
Started Jun 27 06:41:16 PM PDT 24
Finished Jun 27 06:42:34 PM PDT 24
Peak memory 206308 kb
Host smart-949d9560-8124-4de5-9c91-9048644bdccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14402
32646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.1440232646
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.638061920
Short name T2309
Test name
Test status
Simulation time 3331571380 ps
CPU time 4.05 seconds
Started Jun 27 06:41:18 PM PDT 24
Finished Jun 27 06:42:18 PM PDT 24
Peak memory 206348 kb
Host smart-0e5db89c-8b97-459c-bd6e-ccb1b60fc67c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63806
1920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.638061920
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.1972478429
Short name T1025
Test name
Test status
Simulation time 9122160539 ps
CPU time 82.18 seconds
Started Jun 27 06:41:22 PM PDT 24
Finished Jun 27 06:43:39 PM PDT 24
Peak memory 206436 kb
Host smart-6e3d3c00-cd9c-4fac-a45b-fb0750602e5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19724
78429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.1972478429
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.3937203893
Short name T863
Test name
Test status
Simulation time 4503726072 ps
CPU time 116.13 seconds
Started Jun 27 06:41:14 PM PDT 24
Finished Jun 27 06:44:09 PM PDT 24
Peak memory 206464 kb
Host smart-ea10b697-b3c4-4d09-912e-7d60d12fab9f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3937203893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.3937203893
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.3451227744
Short name T641
Test name
Test status
Simulation time 253093209 ps
CPU time 0.88 seconds
Started Jun 27 06:41:20 PM PDT 24
Finished Jun 27 06:42:18 PM PDT 24
Peak memory 206296 kb
Host smart-b16cadbe-692b-4cd7-85e5-35f4077bbb22
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3451227744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.3451227744
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.264475162
Short name T1078
Test name
Test status
Simulation time 189763910 ps
CPU time 0.84 seconds
Started Jun 27 06:41:20 PM PDT 24
Finished Jun 27 06:42:18 PM PDT 24
Peak memory 206284 kb
Host smart-45e3d8e0-7230-43a4-9d9e-6abdb0cb15fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26447
5162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.264475162
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.3422392104
Short name T466
Test name
Test status
Simulation time 4726718200 ps
CPU time 127.9 seconds
Started Jun 27 06:41:21 PM PDT 24
Finished Jun 27 06:44:25 PM PDT 24
Peak memory 206392 kb
Host smart-dded34f2-f1de-4843-a840-e205bdb923ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34223
92104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.3422392104
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.3850863954
Short name T1548
Test name
Test status
Simulation time 3264905514 ps
CPU time 90.06 seconds
Started Jun 27 06:41:20 PM PDT 24
Finished Jun 27 06:43:47 PM PDT 24
Peak memory 206232 kb
Host smart-ae874627-49d8-4de4-aed1-281e18e39296
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3850863954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.3850863954
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.2270935827
Short name T668
Test name
Test status
Simulation time 158315358 ps
CPU time 0.77 seconds
Started Jun 27 06:41:20 PM PDT 24
Finished Jun 27 06:42:18 PM PDT 24
Peak memory 206288 kb
Host smart-3f281c45-a2bf-4afe-a43d-b671ae4f8466
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2270935827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.2270935827
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.1910042992
Short name T1205
Test name
Test status
Simulation time 180022633 ps
CPU time 0.79 seconds
Started Jun 27 06:41:22 PM PDT 24
Finished Jun 27 06:42:18 PM PDT 24
Peak memory 206080 kb
Host smart-0a889325-f0fb-4954-b5e7-0bb8d2abfdba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19100
42992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.1910042992
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.843533490
Short name T115
Test name
Test status
Simulation time 209800854 ps
CPU time 0.82 seconds
Started Jun 27 06:41:22 PM PDT 24
Finished Jun 27 06:42:18 PM PDT 24
Peak memory 206052 kb
Host smart-06a635dd-69c2-491e-bb89-af9a20268ba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84353
3490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.843533490
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.2114252547
Short name T984
Test name
Test status
Simulation time 159295018 ps
CPU time 0.76 seconds
Started Jun 27 06:41:21 PM PDT 24
Finished Jun 27 06:42:18 PM PDT 24
Peak memory 206240 kb
Host smart-f89a0631-76af-4aec-a506-4d57d0d4ba62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21142
52547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.2114252547
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.632370375
Short name T1017
Test name
Test status
Simulation time 156068205 ps
CPU time 0.76 seconds
Started Jun 27 06:41:18 PM PDT 24
Finished Jun 27 06:42:15 PM PDT 24
Peak memory 206296 kb
Host smart-3904a793-957b-4faf-b239-8dba9968e748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63237
0375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.632370375
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.3427983983
Short name T2227
Test name
Test status
Simulation time 223729594 ps
CPU time 0.82 seconds
Started Jun 27 06:41:19 PM PDT 24
Finished Jun 27 06:42:17 PM PDT 24
Peak memory 206300 kb
Host smart-9251bef1-0ecf-4e1d-b48c-2ca3279bf813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34279
83983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.3427983983
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.2788451001
Short name T876
Test name
Test status
Simulation time 155761353 ps
CPU time 0.75 seconds
Started Jun 27 06:41:13 PM PDT 24
Finished Jun 27 06:42:11 PM PDT 24
Peak memory 206284 kb
Host smart-813e5409-861a-4eba-874b-76c1e190de73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27884
51001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.2788451001
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.1439352574
Short name T2606
Test name
Test status
Simulation time 225089041 ps
CPU time 0.87 seconds
Started Jun 27 06:41:19 PM PDT 24
Finished Jun 27 06:42:18 PM PDT 24
Peak memory 206316 kb
Host smart-be830f62-8f98-46c8-97a1-1c55b4216838
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1439352574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.1439352574
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.3440214461
Short name T2486
Test name
Test status
Simulation time 144685607 ps
CPU time 0.71 seconds
Started Jun 27 06:41:29 PM PDT 24
Finished Jun 27 06:42:24 PM PDT 24
Peak memory 206284 kb
Host smart-c51c064e-6db6-4a9e-8370-9dbf3549472e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34402
14461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.3440214461
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.3203730986
Short name T35
Test name
Test status
Simulation time 56450747 ps
CPU time 0.65 seconds
Started Jun 27 06:41:29 PM PDT 24
Finished Jun 27 06:42:24 PM PDT 24
Peak memory 206276 kb
Host smart-ecd99147-b334-485a-b067-1f5f4bd83fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32037
30986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.3203730986
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.3425409550
Short name T1213
Test name
Test status
Simulation time 13072190585 ps
CPU time 27.39 seconds
Started Jun 27 06:41:19 PM PDT 24
Finished Jun 27 06:42:44 PM PDT 24
Peak memory 206468 kb
Host smart-156fad1d-a086-4c0b-adea-9680717eecda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34254
09550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.3425409550
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.2882541891
Short name T1523
Test name
Test status
Simulation time 181120181 ps
CPU time 0.78 seconds
Started Jun 27 06:41:19 PM PDT 24
Finished Jun 27 06:42:17 PM PDT 24
Peak memory 206288 kb
Host smart-ace5c0c1-c74a-45ea-9acd-2292ad5d4d6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28825
41891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.2882541891
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.1728650961
Short name T882
Test name
Test status
Simulation time 201708317 ps
CPU time 0.82 seconds
Started Jun 27 06:41:23 PM PDT 24
Finished Jun 27 06:42:18 PM PDT 24
Peak memory 206296 kb
Host smart-9cdaaac3-edf0-48ad-a104-81760ec2f094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17286
50961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.1728650961
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.3605034398
Short name T1174
Test name
Test status
Simulation time 208741615 ps
CPU time 0.83 seconds
Started Jun 27 06:41:28 PM PDT 24
Finished Jun 27 06:42:24 PM PDT 24
Peak memory 206300 kb
Host smart-53f6375e-2b21-4cc1-a7f4-54b6cb1d9441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36050
34398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.3605034398
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.2275399162
Short name T1040
Test name
Test status
Simulation time 257433001 ps
CPU time 0.85 seconds
Started Jun 27 06:41:25 PM PDT 24
Finished Jun 27 06:42:21 PM PDT 24
Peak memory 206276 kb
Host smart-46b77e2d-894f-4d44-b199-858e869b7204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22753
99162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.2275399162
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.1118483825
Short name T1954
Test name
Test status
Simulation time 142901243 ps
CPU time 0.72 seconds
Started Jun 27 06:41:26 PM PDT 24
Finished Jun 27 06:42:21 PM PDT 24
Peak memory 206272 kb
Host smart-d508158b-3a17-4c72-8b00-d4748d872347
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11184
83825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.1118483825
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.4099255791
Short name T1448
Test name
Test status
Simulation time 152198137 ps
CPU time 0.84 seconds
Started Jun 27 06:41:15 PM PDT 24
Finished Jun 27 06:42:14 PM PDT 24
Peak memory 206276 kb
Host smart-d4a2cab1-9191-46bb-b51b-c3099fd484ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40992
55791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.4099255791
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.3383309825
Short name T1996
Test name
Test status
Simulation time 152730507 ps
CPU time 0.76 seconds
Started Jun 27 06:41:28 PM PDT 24
Finished Jun 27 06:42:24 PM PDT 24
Peak memory 206288 kb
Host smart-2d52504d-1c56-488e-accd-25619c52ac8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33833
09825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.3383309825
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.1683862149
Short name T1813
Test name
Test status
Simulation time 229371085 ps
CPU time 0.97 seconds
Started Jun 27 06:41:22 PM PDT 24
Finished Jun 27 06:42:18 PM PDT 24
Peak memory 206396 kb
Host smart-05ff7cf8-faec-4f7f-8125-89cca914b996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16838
62149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.1683862149
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.1410857975
Short name T2258
Test name
Test status
Simulation time 4529555264 ps
CPU time 123.68 seconds
Started Jun 27 06:41:22 PM PDT 24
Finished Jun 27 06:44:21 PM PDT 24
Peak memory 206600 kb
Host smart-4a981563-d182-4be4-9c88-52395b27447e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1410857975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.1410857975
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.1209562688
Short name T1840
Test name
Test status
Simulation time 171757932 ps
CPU time 0.78 seconds
Started Jun 27 06:41:25 PM PDT 24
Finished Jun 27 06:42:21 PM PDT 24
Peak memory 206276 kb
Host smart-1020873b-a8f0-4553-80a9-017edadef969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12095
62688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.1209562688
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.2921241414
Short name T817
Test name
Test status
Simulation time 148085431 ps
CPU time 0.73 seconds
Started Jun 27 06:41:28 PM PDT 24
Finished Jun 27 06:42:24 PM PDT 24
Peak memory 206272 kb
Host smart-cdca6adf-8f7e-4676-b3dd-d23ee48341f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29212
41414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.2921241414
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.1823107380
Short name T2152
Test name
Test status
Simulation time 7681755033 ps
CPU time 205.7 seconds
Started Jun 27 06:41:28 PM PDT 24
Finished Jun 27 06:45:49 PM PDT 24
Peak memory 206412 kb
Host smart-b2c14d25-e272-4deb-9a2b-7953462efea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18231
07380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.1823107380
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.1378334865
Short name T1601
Test name
Test status
Simulation time 110638697 ps
CPU time 0.71 seconds
Started Jun 27 06:41:31 PM PDT 24
Finished Jun 27 06:42:25 PM PDT 24
Peak memory 206320 kb
Host smart-b2b76a8d-0306-442c-81dc-1fdb75581024
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1378334865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.1378334865
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.3046706488
Short name T2262
Test name
Test status
Simulation time 4294082065 ps
CPU time 5.37 seconds
Started Jun 27 06:41:26 PM PDT 24
Finished Jun 27 06:42:26 PM PDT 24
Peak memory 206448 kb
Host smart-caf82e39-0cf1-4a06-8ea4-d8bf10798463
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3046706488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.3046706488
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.2761406906
Short name T2021
Test name
Test status
Simulation time 13374502440 ps
CPU time 15.94 seconds
Started Jun 27 06:41:27 PM PDT 24
Finished Jun 27 06:42:36 PM PDT 24
Peak memory 206344 kb
Host smart-607e3cbe-c26f-4b51-9570-8b0d5beb9284
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2761406906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.2761406906
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.2436398929
Short name T1872
Test name
Test status
Simulation time 23379414990 ps
CPU time 25.43 seconds
Started Jun 27 06:41:27 PM PDT 24
Finished Jun 27 06:42:46 PM PDT 24
Peak memory 206424 kb
Host smart-1c3b207d-94ad-4fea-8bde-bf17b52e2e4b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2436398929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.2436398929
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.2330437909
Short name T315
Test name
Test status
Simulation time 221352501 ps
CPU time 0.83 seconds
Started Jun 27 06:41:28 PM PDT 24
Finished Jun 27 06:42:23 PM PDT 24
Peak memory 206284 kb
Host smart-77f6a4b7-5d75-4588-9124-4f197184d029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23304
37909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.2330437909
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.3054056410
Short name T636
Test name
Test status
Simulation time 152786620 ps
CPU time 0.74 seconds
Started Jun 27 06:41:29 PM PDT 24
Finished Jun 27 06:42:24 PM PDT 24
Peak memory 206280 kb
Host smart-f441323c-c8e1-47bc-b0b2-0167f2238782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30540
56410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.3054056410
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.4152390090
Short name T1874
Test name
Test status
Simulation time 375060470 ps
CPU time 1.18 seconds
Started Jun 27 06:41:26 PM PDT 24
Finished Jun 27 06:42:21 PM PDT 24
Peak memory 206276 kb
Host smart-b1e58c88-d0d3-46f0-b449-aaf65a2b7ed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41523
90090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.4152390090
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.246804007
Short name T1105
Test name
Test status
Simulation time 1098603113 ps
CPU time 2.32 seconds
Started Jun 27 06:41:31 PM PDT 24
Finished Jun 27 06:42:26 PM PDT 24
Peak memory 206440 kb
Host smart-8e0e29c0-ec3f-40a0-a21a-67d07536b66f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24680
4007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.246804007
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.57302228
Short name T2224
Test name
Test status
Simulation time 15773948030 ps
CPU time 27.95 seconds
Started Jun 27 06:41:28 PM PDT 24
Finished Jun 27 06:42:51 PM PDT 24
Peak memory 206488 kb
Host smart-d1059675-06c4-4831-bc2a-c1f29e8c0f7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57302
228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.57302228
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.3055062318
Short name T1314
Test name
Test status
Simulation time 326520526 ps
CPU time 1.01 seconds
Started Jun 27 06:41:28 PM PDT 24
Finished Jun 27 06:42:24 PM PDT 24
Peak memory 206284 kb
Host smart-aa1ae7be-47d8-46f6-b63f-38a4d09c193b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30550
62318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.3055062318
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.476068271
Short name T1313
Test name
Test status
Simulation time 139259434 ps
CPU time 0.71 seconds
Started Jun 27 06:41:28 PM PDT 24
Finished Jun 27 06:42:24 PM PDT 24
Peak memory 206268 kb
Host smart-e4e60940-740e-4574-8407-8b61f9572024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47606
8271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.476068271
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.2377589952
Short name T1968
Test name
Test status
Simulation time 39761659 ps
CPU time 0.62 seconds
Started Jun 27 06:41:27 PM PDT 24
Finished Jun 27 06:42:21 PM PDT 24
Peak memory 206288 kb
Host smart-5961820e-5125-4963-9879-722831b4c9c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23775
89952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.2377589952
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.3063078492
Short name T2418
Test name
Test status
Simulation time 801508790 ps
CPU time 1.99 seconds
Started Jun 27 06:41:17 PM PDT 24
Finished Jun 27 06:42:16 PM PDT 24
Peak memory 206296 kb
Host smart-5ee26f7f-b77d-41e3-a22f-1e00f1fe6dbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30630
78492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.3063078492
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.756994467
Short name T2526
Test name
Test status
Simulation time 413742056 ps
CPU time 2.38 seconds
Started Jun 27 06:41:13 PM PDT 24
Finished Jun 27 06:42:12 PM PDT 24
Peak memory 206356 kb
Host smart-9849396f-9bfe-4294-9752-c5f87fcb9696
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75699
4467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.756994467
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.989408482
Short name T2115
Test name
Test status
Simulation time 168152239 ps
CPU time 0.82 seconds
Started Jun 27 06:41:19 PM PDT 24
Finished Jun 27 06:42:17 PM PDT 24
Peak memory 206312 kb
Host smart-e57ed9d6-257b-4fbc-be04-a3aba99202dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98940
8482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.989408482
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.378189192
Short name T2315
Test name
Test status
Simulation time 153394775 ps
CPU time 0.75 seconds
Started Jun 27 06:41:14 PM PDT 24
Finished Jun 27 06:42:14 PM PDT 24
Peak memory 206312 kb
Host smart-01969c12-a3d2-4785-9916-6fc834a387ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37818
9192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.378189192
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.3576922985
Short name T2344
Test name
Test status
Simulation time 257944548 ps
CPU time 0.92 seconds
Started Jun 27 06:41:16 PM PDT 24
Finished Jun 27 06:42:15 PM PDT 24
Peak memory 206288 kb
Host smart-60c44458-dc41-49d2-bff5-452c4cd04cad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35769
22985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.3576922985
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_invalid_sync.1914220173
Short name T2127
Test name
Test status
Simulation time 5386202698 ps
CPU time 145.74 seconds
Started Jun 27 06:41:14 PM PDT 24
Finished Jun 27 06:44:38 PM PDT 24
Peak memory 206484 kb
Host smart-6fc76fb4-8aa8-415a-8a79-9cea3d7b8e1b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1914220173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.1914220173
Directory /workspace/42.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.743505352
Short name T1433
Test name
Test status
Simulation time 237122486 ps
CPU time 0.89 seconds
Started Jun 27 06:41:16 PM PDT 24
Finished Jun 27 06:42:15 PM PDT 24
Peak memory 206272 kb
Host smart-1d329dc1-a9f8-4570-8776-e330d98181fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74350
5352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.743505352
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.2728215980
Short name T1516
Test name
Test status
Simulation time 23394175653 ps
CPU time 21.84 seconds
Started Jun 27 06:41:17 PM PDT 24
Finished Jun 27 06:42:36 PM PDT 24
Peak memory 206252 kb
Host smart-14d54af5-64b8-4b4d-be3d-c1d71b51b152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27282
15980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.2728215980
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.3354926835
Short name T2504
Test name
Test status
Simulation time 3279127044 ps
CPU time 4.28 seconds
Started Jun 27 06:41:20 PM PDT 24
Finished Jun 27 06:42:21 PM PDT 24
Peak memory 206340 kb
Host smart-e0d97422-3549-4eb1-a8e3-c76c4c0a27bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33549
26835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.3354926835
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.3240041147
Short name T1120
Test name
Test status
Simulation time 4215432398 ps
CPU time 36.33 seconds
Started Jun 27 06:41:15 PM PDT 24
Finished Jun 27 06:42:50 PM PDT 24
Peak memory 206468 kb
Host smart-a7419683-7200-46b1-8e4f-db0cfb57167a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32400
41147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.3240041147
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.2036340213
Short name T482
Test name
Test status
Simulation time 3221984642 ps
CPU time 83.95 seconds
Started Jun 27 06:41:24 PM PDT 24
Finished Jun 27 06:43:43 PM PDT 24
Peak memory 206444 kb
Host smart-08fa7879-013d-4436-a720-a3ea200c1004
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2036340213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.2036340213
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.2857065070
Short name T699
Test name
Test status
Simulation time 238537764 ps
CPU time 0.9 seconds
Started Jun 27 06:41:22 PM PDT 24
Finished Jun 27 06:42:18 PM PDT 24
Peak memory 206248 kb
Host smart-209d701b-e3ca-4aeb-8c0b-5f5b0b4f8439
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2857065070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.2857065070
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.3941075947
Short name T1159
Test name
Test status
Simulation time 198585503 ps
CPU time 0.9 seconds
Started Jun 27 06:41:21 PM PDT 24
Finished Jun 27 06:42:18 PM PDT 24
Peak memory 206460 kb
Host smart-c29410e4-a66f-475e-9117-741b2de8359a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39410
75947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.3941075947
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.539730632
Short name T1998
Test name
Test status
Simulation time 6497672402 ps
CPU time 177.87 seconds
Started Jun 27 06:41:20 PM PDT 24
Finished Jun 27 06:45:15 PM PDT 24
Peak memory 206432 kb
Host smart-ae526103-d5a7-4480-8da7-b789e24845da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53973
0632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.539730632
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.4126547862
Short name T1799
Test name
Test status
Simulation time 3947371141 ps
CPU time 27.38 seconds
Started Jun 27 06:41:20 PM PDT 24
Finished Jun 27 06:42:44 PM PDT 24
Peak memory 206500 kb
Host smart-5a2b6804-406c-4135-a05f-ff33641a8417
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4126547862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.4126547862
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.3107429859
Short name T2403
Test name
Test status
Simulation time 150685906 ps
CPU time 0.78 seconds
Started Jun 27 06:41:22 PM PDT 24
Finished Jun 27 06:42:18 PM PDT 24
Peak memory 206248 kb
Host smart-51c42ede-199b-423b-a515-53a98c2260c6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3107429859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.3107429859
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.3961333613
Short name T2580
Test name
Test status
Simulation time 165513663 ps
CPU time 0.77 seconds
Started Jun 27 06:41:20 PM PDT 24
Finished Jun 27 06:42:17 PM PDT 24
Peak memory 206072 kb
Host smart-8d441ab8-2fda-4fa1-8470-0752de7f87ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39613
33613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.3961333613
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.2115827578
Short name T129
Test name
Test status
Simulation time 174763551 ps
CPU time 0.77 seconds
Started Jun 27 06:41:23 PM PDT 24
Finished Jun 27 06:42:20 PM PDT 24
Peak memory 206284 kb
Host smart-1c668ae9-fe9e-44f5-981b-c1e5bf3c073e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21158
27578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.2115827578
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.3679172313
Short name T440
Test name
Test status
Simulation time 182687292 ps
CPU time 0.81 seconds
Started Jun 27 06:41:29 PM PDT 24
Finished Jun 27 06:42:24 PM PDT 24
Peak memory 206296 kb
Host smart-65b3a303-a703-409a-b489-deda9dbfea2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36791
72313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.3679172313
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.510176619
Short name T712
Test name
Test status
Simulation time 236593667 ps
CPU time 0.94 seconds
Started Jun 27 06:41:22 PM PDT 24
Finished Jun 27 06:42:18 PM PDT 24
Peak memory 206456 kb
Host smart-694968dd-3dff-45f5-8760-d3e2d4064344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51017
6619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.510176619
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.1196261851
Short name T410
Test name
Test status
Simulation time 188524302 ps
CPU time 0.76 seconds
Started Jun 27 06:41:24 PM PDT 24
Finished Jun 27 06:42:20 PM PDT 24
Peak memory 206284 kb
Host smart-991392f8-f1e2-4099-b8bb-780b89426870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11962
61851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.1196261851
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.3643108368
Short name T1109
Test name
Test status
Simulation time 153283921 ps
CPU time 0.83 seconds
Started Jun 27 06:41:26 PM PDT 24
Finished Jun 27 06:42:21 PM PDT 24
Peak memory 206276 kb
Host smart-abe2ddf6-446c-47ae-9fbc-e8b99a61b68d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36431
08368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.3643108368
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.4254307861
Short name T1753
Test name
Test status
Simulation time 239177851 ps
CPU time 0.86 seconds
Started Jun 27 06:41:24 PM PDT 24
Finished Jun 27 06:42:21 PM PDT 24
Peak memory 206300 kb
Host smart-ad2cec76-dd32-45f7-91a5-e9920399f325
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4254307861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.4254307861
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.2490272639
Short name T2181
Test name
Test status
Simulation time 138150547 ps
CPU time 0.79 seconds
Started Jun 27 06:41:22 PM PDT 24
Finished Jun 27 06:42:18 PM PDT 24
Peak memory 206456 kb
Host smart-8cdd3a78-2b4f-4892-be33-3a16b8a071e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24902
72639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.2490272639
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.4288791425
Short name T36
Test name
Test status
Simulation time 40485286 ps
CPU time 0.69 seconds
Started Jun 27 06:41:26 PM PDT 24
Finished Jun 27 06:42:21 PM PDT 24
Peak memory 206268 kb
Host smart-50317beb-fd8c-495f-8f7b-af46f66364e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42887
91425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.4288791425
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.3069509059
Short name T2399
Test name
Test status
Simulation time 15826595216 ps
CPU time 30.69 seconds
Started Jun 27 06:41:26 PM PDT 24
Finished Jun 27 06:42:51 PM PDT 24
Peak memory 206452 kb
Host smart-f8645087-78f9-4e34-a8e7-22225e1b0616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30695
09059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.3069509059
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.2345132793
Short name T1330
Test name
Test status
Simulation time 152207104 ps
CPU time 0.86 seconds
Started Jun 27 06:41:22 PM PDT 24
Finished Jun 27 06:42:18 PM PDT 24
Peak memory 206424 kb
Host smart-c7ac2a18-5e22-48d5-9c97-33ebe8cbb964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23451
32793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.2345132793
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.1096909243
Short name T213
Test name
Test status
Simulation time 214099668 ps
CPU time 0.82 seconds
Started Jun 27 06:41:25 PM PDT 24
Finished Jun 27 06:42:21 PM PDT 24
Peak memory 206288 kb
Host smart-dcce96f4-09e5-4c9e-bbfc-1c496eb758ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10969
09243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.1096909243
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.2031270557
Short name T566
Test name
Test status
Simulation time 183276786 ps
CPU time 0.81 seconds
Started Jun 27 06:41:28 PM PDT 24
Finished Jun 27 06:42:24 PM PDT 24
Peak memory 206296 kb
Host smart-a8e93fdb-5ad5-48f9-b938-9a6bd5aba7e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20312
70557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.2031270557
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.3838909170
Short name T1936
Test name
Test status
Simulation time 193902188 ps
CPU time 0.82 seconds
Started Jun 27 06:41:28 PM PDT 24
Finished Jun 27 06:42:24 PM PDT 24
Peak memory 206276 kb
Host smart-99ced233-a850-4b79-b770-5c12b312220d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38389
09170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.3838909170
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.1247091512
Short name T2291
Test name
Test status
Simulation time 225769270 ps
CPU time 0.86 seconds
Started Jun 27 06:41:27 PM PDT 24
Finished Jun 27 06:42:21 PM PDT 24
Peak memory 206272 kb
Host smart-2b0bf111-6b00-449c-8433-a8b2ad94ebe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12470
91512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.1247091512
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.3136119624
Short name T2164
Test name
Test status
Simulation time 213550353 ps
CPU time 0.79 seconds
Started Jun 27 06:41:28 PM PDT 24
Finished Jun 27 06:42:24 PM PDT 24
Peak memory 206268 kb
Host smart-1a35c081-4500-48a5-9bf1-07ba229a8660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31361
19624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.3136119624
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.337698244
Short name T979
Test name
Test status
Simulation time 208359325 ps
CPU time 0.84 seconds
Started Jun 27 06:41:33 PM PDT 24
Finished Jun 27 06:42:27 PM PDT 24
Peak memory 206284 kb
Host smart-92c1e9c1-768f-44bd-ac36-d4b5f202dadc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33769
8244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.337698244
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.3167396029
Short name T2111
Test name
Test status
Simulation time 210290201 ps
CPU time 0.91 seconds
Started Jun 27 06:41:32 PM PDT 24
Finished Jun 27 06:42:25 PM PDT 24
Peak memory 206284 kb
Host smart-89466d50-a6ed-407e-a529-36673b9f6ccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31673
96029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.3167396029
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.147147376
Short name T1616
Test name
Test status
Simulation time 6886673823 ps
CPU time 188.64 seconds
Started Jun 27 06:41:36 PM PDT 24
Finished Jun 27 06:45:36 PM PDT 24
Peak memory 206464 kb
Host smart-5a63966f-46a4-40f8-9751-8cea96c80bc8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=147147376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.147147376
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.2464372054
Short name T1847
Test name
Test status
Simulation time 166128187 ps
CPU time 0.77 seconds
Started Jun 27 06:41:35 PM PDT 24
Finished Jun 27 06:42:28 PM PDT 24
Peak memory 206268 kb
Host smart-8bdda712-b50d-4718-a50d-7932db9050f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24643
72054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.2464372054
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.3090136922
Short name T1956
Test name
Test status
Simulation time 175541558 ps
CPU time 0.8 seconds
Started Jun 27 06:41:36 PM PDT 24
Finished Jun 27 06:42:28 PM PDT 24
Peak memory 206144 kb
Host smart-6a4635ca-20b1-4994-9784-080f641d575a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30901
36922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.3090136922
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.2385492432
Short name T2538
Test name
Test status
Simulation time 7146321074 ps
CPU time 197.05 seconds
Started Jun 27 06:41:36 PM PDT 24
Finished Jun 27 06:45:44 PM PDT 24
Peak memory 206596 kb
Host smart-aa5d7b1b-3882-4dab-8001-68dd918bb981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23854
92432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.2385492432
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.4152883292
Short name T1270
Test name
Test status
Simulation time 39082653 ps
CPU time 0.66 seconds
Started Jun 27 06:41:51 PM PDT 24
Finished Jun 27 06:42:37 PM PDT 24
Peak memory 206356 kb
Host smart-32f3e4e5-628e-450b-b9a1-4c7ec3dca506
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4152883292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.4152883292
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.2734398315
Short name T503
Test name
Test status
Simulation time 3529925575 ps
CPU time 4.91 seconds
Started Jun 27 06:41:33 PM PDT 24
Finished Jun 27 06:42:31 PM PDT 24
Peak memory 206356 kb
Host smart-c6ff0a2d-f1e9-4fbe-afa3-00e613ae97b7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2734398315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.2734398315
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.3230407521
Short name T228
Test name
Test status
Simulation time 13378099383 ps
CPU time 12.12 seconds
Started Jun 27 06:41:34 PM PDT 24
Finished Jun 27 06:42:39 PM PDT 24
Peak memory 206492 kb
Host smart-7469dbf9-901e-431f-83c6-a650ceef25f7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3230407521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.3230407521
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.3787187733
Short name T1099
Test name
Test status
Simulation time 23421512294 ps
CPU time 22.51 seconds
Started Jun 27 06:41:35 PM PDT 24
Finished Jun 27 06:42:49 PM PDT 24
Peak memory 206340 kb
Host smart-aa8f9e51-361c-439e-ab8c-61ee2e31f517
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3787187733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.3787187733
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.197269279
Short name T385
Test name
Test status
Simulation time 167578531 ps
CPU time 0.8 seconds
Started Jun 27 06:41:36 PM PDT 24
Finished Jun 27 06:42:28 PM PDT 24
Peak memory 206264 kb
Host smart-d3f638b2-391f-43c7-a726-56f9ed83eef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19726
9279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.197269279
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.4101925932
Short name T1475
Test name
Test status
Simulation time 163311517 ps
CPU time 0.76 seconds
Started Jun 27 06:41:36 PM PDT 24
Finished Jun 27 06:42:28 PM PDT 24
Peak memory 206112 kb
Host smart-00589e18-eb19-4635-ad05-f79883cf629f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41019
25932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.4101925932
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.3310545369
Short name T1979
Test name
Test status
Simulation time 479048560 ps
CPU time 1.32 seconds
Started Jun 27 06:41:35 PM PDT 24
Finished Jun 27 06:42:28 PM PDT 24
Peak memory 206220 kb
Host smart-ffdb37ee-1a37-49ef-8705-45850e3a7b8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33105
45369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.3310545369
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.4036122321
Short name T2010
Test name
Test status
Simulation time 1593279539 ps
CPU time 3.63 seconds
Started Jun 27 06:41:38 PM PDT 24
Finished Jun 27 06:42:33 PM PDT 24
Peak memory 206428 kb
Host smart-0f9f94d5-c0f0-43e9-b908-b38d868cdca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40361
22321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.4036122321
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.3042225368
Short name T1881
Test name
Test status
Simulation time 19017555310 ps
CPU time 35.84 seconds
Started Jun 27 06:41:33 PM PDT 24
Finished Jun 27 06:43:02 PM PDT 24
Peak memory 206444 kb
Host smart-abc999ea-e9b6-41b8-ac61-fcb1007f210f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30422
25368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.3042225368
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.2855835150
Short name T1522
Test name
Test status
Simulation time 446315649 ps
CPU time 1.49 seconds
Started Jun 27 06:41:35 PM PDT 24
Finished Jun 27 06:42:28 PM PDT 24
Peak memory 206272 kb
Host smart-f75f6b92-b521-4f48-a5b2-8b6164b4f7c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28558
35150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.2855835150
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.1697626253
Short name T873
Test name
Test status
Simulation time 168042642 ps
CPU time 0.78 seconds
Started Jun 27 06:41:36 PM PDT 24
Finished Jun 27 06:42:28 PM PDT 24
Peak memory 206272 kb
Host smart-54dcb355-bc03-435d-858e-b6b5bac58d74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16976
26253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.1697626253
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.2321143723
Short name T900
Test name
Test status
Simulation time 99678717 ps
CPU time 0.67 seconds
Started Jun 27 06:41:30 PM PDT 24
Finished Jun 27 06:42:25 PM PDT 24
Peak memory 206276 kb
Host smart-0a5a9d8b-1ede-4365-a55e-f8657e1be44f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23211
43723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.2321143723
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.2822137833
Short name T630
Test name
Test status
Simulation time 767835541 ps
CPU time 1.91 seconds
Started Jun 27 06:41:33 PM PDT 24
Finished Jun 27 06:42:28 PM PDT 24
Peak memory 206428 kb
Host smart-27430635-3315-4278-a2c9-e25077185fb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28221
37833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.2822137833
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.1113125178
Short name T1474
Test name
Test status
Simulation time 294097383 ps
CPU time 2.08 seconds
Started Jun 27 06:41:32 PM PDT 24
Finished Jun 27 06:42:26 PM PDT 24
Peak memory 206372 kb
Host smart-13ae4729-9e65-481c-a1ae-dc03257927fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11131
25178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.1113125178
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.2948862579
Short name T2537
Test name
Test status
Simulation time 237393767 ps
CPU time 0.88 seconds
Started Jun 27 06:41:32 PM PDT 24
Finished Jun 27 06:42:25 PM PDT 24
Peak memory 206268 kb
Host smart-0a9ce530-9349-427d-9b88-74ed6030673d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29488
62579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.2948862579
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.2983500953
Short name T2451
Test name
Test status
Simulation time 146438503 ps
CPU time 0.78 seconds
Started Jun 27 06:41:36 PM PDT 24
Finished Jun 27 06:42:28 PM PDT 24
Peak memory 206276 kb
Host smart-92e1cc08-797d-4e56-bb55-7f88146b385a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29835
00953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.2983500953
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.4202930995
Short name T1656
Test name
Test status
Simulation time 170174274 ps
CPU time 0.8 seconds
Started Jun 27 06:41:32 PM PDT 24
Finished Jun 27 06:42:27 PM PDT 24
Peak memory 206280 kb
Host smart-2bda54fc-992b-4c79-9ca1-ea5e1c800873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42029
30995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.4202930995
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_invalid_sync.151472790
Short name T220
Test name
Test status
Simulation time 9253202821 ps
CPU time 65 seconds
Started Jun 27 06:41:32 PM PDT 24
Finished Jun 27 06:43:29 PM PDT 24
Peak memory 206416 kb
Host smart-4f5efc1d-68bd-4903-a87a-b795c3d361bb
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=151472790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.151472790
Directory /workspace/43.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.651945305
Short name T1436
Test name
Test status
Simulation time 243009784 ps
CPU time 0.86 seconds
Started Jun 27 06:41:32 PM PDT 24
Finished Jun 27 06:42:27 PM PDT 24
Peak memory 206264 kb
Host smart-b2e51f1b-61af-4c1d-a026-b8b8cfac6db0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65194
5305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.651945305
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.14371053
Short name T192
Test name
Test status
Simulation time 23279832562 ps
CPU time 27.57 seconds
Started Jun 27 06:41:35 PM PDT 24
Finished Jun 27 06:42:54 PM PDT 24
Peak memory 206288 kb
Host smart-10201d8b-6afb-400c-bf2c-24dd71744ba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14371
053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.14371053
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.1430117782
Short name T1552
Test name
Test status
Simulation time 3338881215 ps
CPU time 3.63 seconds
Started Jun 27 06:41:36 PM PDT 24
Finished Jun 27 06:42:31 PM PDT 24
Peak memory 206324 kb
Host smart-c5b9d299-8216-413e-b4ee-f0e869b08314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14301
17782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.1430117782
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.1982335044
Short name T1315
Test name
Test status
Simulation time 6285312334 ps
CPU time 169.64 seconds
Started Jun 27 06:41:37 PM PDT 24
Finished Jun 27 06:45:17 PM PDT 24
Peak memory 206496 kb
Host smart-545b47d5-0485-4058-83a2-1d9306975b6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19823
35044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.1982335044
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.2914303449
Short name T2000
Test name
Test status
Simulation time 3964378165 ps
CPU time 108.22 seconds
Started Jun 27 06:41:33 PM PDT 24
Finished Jun 27 06:44:14 PM PDT 24
Peak memory 206440 kb
Host smart-98ebadfe-ae58-42d3-b767-cd95b94b3810
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2914303449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.2914303449
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.4174046058
Short name T1736
Test name
Test status
Simulation time 242892800 ps
CPU time 0.88 seconds
Started Jun 27 06:41:36 PM PDT 24
Finished Jun 27 06:42:28 PM PDT 24
Peak memory 206296 kb
Host smart-2dd0495a-3860-49c4-b32a-af9fc6bd1afb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4174046058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.4174046058
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.1495478211
Short name T2105
Test name
Test status
Simulation time 195995986 ps
CPU time 0.84 seconds
Started Jun 27 06:41:33 PM PDT 24
Finished Jun 27 06:42:27 PM PDT 24
Peak memory 206272 kb
Host smart-c7fd2c42-fe1b-4889-8b27-73f82d1669cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14954
78211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.1495478211
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.823638693
Short name T1745
Test name
Test status
Simulation time 5979373678 ps
CPU time 157.86 seconds
Started Jun 27 06:41:35 PM PDT 24
Finished Jun 27 06:45:05 PM PDT 24
Peak memory 206468 kb
Host smart-1ef698dd-04ff-4819-b761-a36ab3c5c73c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82363
8693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.823638693
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.1782545864
Short name T1162
Test name
Test status
Simulation time 6736771661 ps
CPU time 63.93 seconds
Started Jun 27 06:41:34 PM PDT 24
Finished Jun 27 06:43:30 PM PDT 24
Peak memory 206492 kb
Host smart-83527d36-197b-4029-b7d8-8c28a7ccfc8e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1782545864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.1782545864
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.1837956379
Short name T2091
Test name
Test status
Simulation time 150583783 ps
CPU time 0.8 seconds
Started Jun 27 06:41:36 PM PDT 24
Finished Jun 27 06:42:28 PM PDT 24
Peak memory 206292 kb
Host smart-192fad15-381b-4951-a9ee-00d1f95fcb8c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1837956379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.1837956379
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.799776355
Short name T908
Test name
Test status
Simulation time 148974931 ps
CPU time 0.75 seconds
Started Jun 27 06:41:38 PM PDT 24
Finished Jun 27 06:42:30 PM PDT 24
Peak memory 206280 kb
Host smart-85b6fc16-80a3-4063-92e6-1b54000933d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79977
6355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.799776355
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.3147479233
Short name T2194
Test name
Test status
Simulation time 262492797 ps
CPU time 0.84 seconds
Started Jun 27 06:41:35 PM PDT 24
Finished Jun 27 06:42:27 PM PDT 24
Peak memory 206228 kb
Host smart-47a95f4e-3b47-4f7e-b6d6-6815c7f54d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31474
79233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.3147479233
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.2707748724
Short name T1230
Test name
Test status
Simulation time 151285578 ps
CPU time 0.81 seconds
Started Jun 27 06:41:33 PM PDT 24
Finished Jun 27 06:42:27 PM PDT 24
Peak memory 206288 kb
Host smart-af00b856-db1a-4e3d-8554-ce6c8077c771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27077
48724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.2707748724
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.2958895853
Short name T2406
Test name
Test status
Simulation time 192207644 ps
CPU time 0.84 seconds
Started Jun 27 06:41:36 PM PDT 24
Finished Jun 27 06:42:28 PM PDT 24
Peak memory 206260 kb
Host smart-4979baa0-cff7-469f-aafc-3fc2a8d53d76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29588
95853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.2958895853
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.3225303711
Short name T1365
Test name
Test status
Simulation time 146065063 ps
CPU time 0.75 seconds
Started Jun 27 06:41:36 PM PDT 24
Finished Jun 27 06:42:28 PM PDT 24
Peak memory 206272 kb
Host smart-5d2d2aac-69d9-4326-bb35-388cc47a1aae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32253
03711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.3225303711
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.1381522737
Short name T1806
Test name
Test status
Simulation time 189445140 ps
CPU time 0.78 seconds
Started Jun 27 06:41:35 PM PDT 24
Finished Jun 27 06:42:28 PM PDT 24
Peak memory 206284 kb
Host smart-6fc87324-862b-43e1-8489-2ab714554f67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13815
22737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.1381522737
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.3044564350
Short name T773
Test name
Test status
Simulation time 293036200 ps
CPU time 0.96 seconds
Started Jun 27 06:41:32 PM PDT 24
Finished Jun 27 06:42:25 PM PDT 24
Peak memory 206416 kb
Host smart-fd78f098-29dd-4513-bcc5-8021b16a7e0d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3044564350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.3044564350
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.2064658323
Short name T369
Test name
Test status
Simulation time 144209303 ps
CPU time 0.77 seconds
Started Jun 27 06:41:36 PM PDT 24
Finished Jun 27 06:42:28 PM PDT 24
Peak memory 206264 kb
Host smart-12cf9eb2-246b-4e37-af4c-4cded1e4c585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20646
58323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.2064658323
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.1070394731
Short name T1098
Test name
Test status
Simulation time 99680339 ps
CPU time 0.72 seconds
Started Jun 27 06:41:33 PM PDT 24
Finished Jun 27 06:42:27 PM PDT 24
Peak memory 206296 kb
Host smart-110bff41-103a-4928-8625-bdda0f5d8aaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10703
94731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.1070394731
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.812731687
Short name T1635
Test name
Test status
Simulation time 6519851973 ps
CPU time 15.15 seconds
Started Jun 27 06:41:48 PM PDT 24
Finished Jun 27 06:42:49 PM PDT 24
Peak memory 206496 kb
Host smart-471eae53-a58c-4e66-8f45-deb6f7d24dd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81273
1687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.812731687
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.948132421
Short name T625
Test name
Test status
Simulation time 148474345 ps
CPU time 0.79 seconds
Started Jun 27 06:41:50 PM PDT 24
Finished Jun 27 06:42:37 PM PDT 24
Peak memory 206284 kb
Host smart-ece40ea0-529c-4b14-9f02-2da32d8431bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94813
2421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.948132421
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.3844388139
Short name T2166
Test name
Test status
Simulation time 225817681 ps
CPU time 0.84 seconds
Started Jun 27 06:41:54 PM PDT 24
Finished Jun 27 06:42:39 PM PDT 24
Peak memory 206268 kb
Host smart-073f88be-434a-4a1a-86f6-485066a93693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38443
88139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.3844388139
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.2549000958
Short name T401
Test name
Test status
Simulation time 210247783 ps
CPU time 0.85 seconds
Started Jun 27 06:42:03 PM PDT 24
Finished Jun 27 06:42:46 PM PDT 24
Peak memory 206176 kb
Host smart-dd014d60-2dd5-47cc-862a-f94b7a24d61a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25490
00958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.2549000958
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.2193030155
Short name T1868
Test name
Test status
Simulation time 220831901 ps
CPU time 0.92 seconds
Started Jun 27 06:41:50 PM PDT 24
Finished Jun 27 06:42:38 PM PDT 24
Peak memory 206212 kb
Host smart-933e57a2-7757-4dcf-a443-b95c63b81b35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21930
30155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.2193030155
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.1190820695
Short name T75
Test name
Test status
Simulation time 143812792 ps
CPU time 0.72 seconds
Started Jun 27 06:42:03 PM PDT 24
Finished Jun 27 06:42:46 PM PDT 24
Peak memory 206152 kb
Host smart-80cd7020-ae20-46ae-a513-6cb11852f29a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11908
20695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.1190820695
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.3717043114
Short name T2126
Test name
Test status
Simulation time 148465914 ps
CPU time 0.79 seconds
Started Jun 27 06:41:50 PM PDT 24
Finished Jun 27 06:42:38 PM PDT 24
Peak memory 206272 kb
Host smart-92a3097c-03ba-46b7-b4e3-0c913dd01211
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37170
43114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.3717043114
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.3359911687
Short name T1156
Test name
Test status
Simulation time 162696909 ps
CPU time 0.8 seconds
Started Jun 27 06:41:49 PM PDT 24
Finished Jun 27 06:42:37 PM PDT 24
Peak memory 206172 kb
Host smart-75cca992-b48f-496a-97fb-10852e4c048a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33599
11687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.3359911687
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.568223463
Short name T584
Test name
Test status
Simulation time 214911242 ps
CPU time 0.91 seconds
Started Jun 27 06:41:49 PM PDT 24
Finished Jun 27 06:42:37 PM PDT 24
Peak memory 206224 kb
Host smart-f2277abd-ae18-439d-bff4-3d59f2c6def8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56822
3463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.568223463
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.1432790968
Short name T746
Test name
Test status
Simulation time 4201659233 ps
CPU time 37.68 seconds
Started Jun 27 06:41:51 PM PDT 24
Finished Jun 27 06:43:14 PM PDT 24
Peak memory 206484 kb
Host smart-b07faeec-8477-4052-86ee-d251060448e7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1432790968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.1432790968
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.2708320547
Short name T2165
Test name
Test status
Simulation time 166550016 ps
CPU time 0.77 seconds
Started Jun 27 06:41:52 PM PDT 24
Finished Jun 27 06:42:38 PM PDT 24
Peak memory 206108 kb
Host smart-7fcba486-9717-4a14-a378-3db993194d0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27083
20547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.2708320547
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.2050466578
Short name T2587
Test name
Test status
Simulation time 173095973 ps
CPU time 0.79 seconds
Started Jun 27 06:41:52 PM PDT 24
Finished Jun 27 06:42:38 PM PDT 24
Peak memory 206272 kb
Host smart-c36b4636-9aa6-4e34-a596-b58aca4e9097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20504
66578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.2050466578
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.1194234873
Short name T977
Test name
Test status
Simulation time 4048308927 ps
CPU time 35.39 seconds
Started Jun 27 06:41:52 PM PDT 24
Finished Jun 27 06:43:12 PM PDT 24
Peak memory 206420 kb
Host smart-3b4cb8b6-7911-4976-abfe-b77d3efa7dad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11942
34873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.1194234873
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.2383190876
Short name T1023
Test name
Test status
Simulation time 70790508 ps
CPU time 0.68 seconds
Started Jun 27 06:41:53 PM PDT 24
Finished Jun 27 06:42:38 PM PDT 24
Peak memory 206364 kb
Host smart-f09bb7b5-a708-4535-b5c0-62ca2baa047a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2383190876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.2383190876
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.629152920
Short name T573
Test name
Test status
Simulation time 3852230575 ps
CPU time 4.36 seconds
Started Jun 27 06:41:52 PM PDT 24
Finished Jun 27 06:42:41 PM PDT 24
Peak memory 206448 kb
Host smart-b12cf5b6-8636-4193-ae2a-4562341a0b4d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=629152920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.629152920
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.2342057403
Short name T1539
Test name
Test status
Simulation time 13354673724 ps
CPU time 12.46 seconds
Started Jun 27 06:41:53 PM PDT 24
Finished Jun 27 06:42:49 PM PDT 24
Peak memory 206336 kb
Host smart-fe26e702-df1d-4534-a0a4-9194d8fa3d81
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2342057403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.2342057403
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.4116767960
Short name T774
Test name
Test status
Simulation time 23359018727 ps
CPU time 22.56 seconds
Started Jun 27 06:41:48 PM PDT 24
Finished Jun 27 06:42:57 PM PDT 24
Peak memory 206440 kb
Host smart-54225651-484e-4de3-8aa0-37a9b6b91013
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4116767960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.4116767960
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.2192313939
Short name T2269
Test name
Test status
Simulation time 159157185 ps
CPU time 0.79 seconds
Started Jun 27 06:41:52 PM PDT 24
Finished Jun 27 06:42:38 PM PDT 24
Peak memory 206276 kb
Host smart-71cbef21-a4ea-4d67-b7d0-3369f5f78b22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21923
13939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.2192313939
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.340778449
Short name T907
Test name
Test status
Simulation time 149923869 ps
CPU time 0.78 seconds
Started Jun 27 06:41:50 PM PDT 24
Finished Jun 27 06:42:37 PM PDT 24
Peak memory 206284 kb
Host smart-a87afdb7-0544-46c5-be09-ae1ec60140f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34077
8449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.340778449
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.708164132
Short name T107
Test name
Test status
Simulation time 757540538 ps
CPU time 1.99 seconds
Started Jun 27 06:41:49 PM PDT 24
Finished Jun 27 06:42:38 PM PDT 24
Peak memory 206344 kb
Host smart-329330e4-2a07-45d4-ad54-510e799ca040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70816
4132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.708164132
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.1550776758
Short name T1396
Test name
Test status
Simulation time 1207764687 ps
CPU time 2.46 seconds
Started Jun 27 06:41:49 PM PDT 24
Finished Jun 27 06:42:39 PM PDT 24
Peak memory 206436 kb
Host smart-f34a3581-cd2b-4fc0-8537-9cdba8ca6771
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15507
76758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.1550776758
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.1393214531
Short name T1684
Test name
Test status
Simulation time 23061720578 ps
CPU time 41.53 seconds
Started Jun 27 06:41:49 PM PDT 24
Finished Jun 27 06:43:18 PM PDT 24
Peak memory 206476 kb
Host smart-9a208ad7-b7af-4334-ba2c-cbaf76268fef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13932
14531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.1393214531
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.3822283839
Short name T511
Test name
Test status
Simulation time 420717532 ps
CPU time 1.29 seconds
Started Jun 27 06:41:56 PM PDT 24
Finished Jun 27 06:42:41 PM PDT 24
Peak memory 206188 kb
Host smart-9746eda4-e12d-4da2-9f46-703bfe3f281e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38222
83839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.3822283839
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.4029519734
Short name T2559
Test name
Test status
Simulation time 135908035 ps
CPU time 0.81 seconds
Started Jun 27 06:41:52 PM PDT 24
Finished Jun 27 06:42:38 PM PDT 24
Peak memory 206272 kb
Host smart-f2732eaf-1928-4b16-ae05-09277cbf6bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40295
19734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.4029519734
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.4031751486
Short name T1215
Test name
Test status
Simulation time 50371560 ps
CPU time 0.65 seconds
Started Jun 27 06:41:46 PM PDT 24
Finished Jun 27 06:42:35 PM PDT 24
Peak memory 206280 kb
Host smart-94a411fe-2bed-46f4-b964-79f65e7b607d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40317
51486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.4031751486
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.182398850
Short name T2555
Test name
Test status
Simulation time 879270381 ps
CPU time 2.04 seconds
Started Jun 27 06:41:46 PM PDT 24
Finished Jun 27 06:42:36 PM PDT 24
Peak memory 206348 kb
Host smart-2167f911-4ca1-4798-968a-bda33608444b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18239
8850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.182398850
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.2623284002
Short name T914
Test name
Test status
Simulation time 233005179 ps
CPU time 1.48 seconds
Started Jun 27 06:41:51 PM PDT 24
Finished Jun 27 06:42:38 PM PDT 24
Peak memory 206360 kb
Host smart-95eb2121-f202-44f9-8075-2f87b553ef2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26232
84002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.2623284002
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.2998830875
Short name T952
Test name
Test status
Simulation time 214985068 ps
CPU time 0.91 seconds
Started Jun 27 06:41:53 PM PDT 24
Finished Jun 27 06:42:38 PM PDT 24
Peak memory 206300 kb
Host smart-f9489ff5-18c1-437c-a61b-3786a63b0bad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29988
30875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.2998830875
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.195576850
Short name T1463
Test name
Test status
Simulation time 141484061 ps
CPU time 0.72 seconds
Started Jun 27 06:41:47 PM PDT 24
Finished Jun 27 06:42:35 PM PDT 24
Peak memory 206292 kb
Host smart-a818dd43-156a-43ab-a36f-675d71dbb2e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19557
6850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.195576850
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.993548233
Short name T1280
Test name
Test status
Simulation time 161069455 ps
CPU time 0.79 seconds
Started Jun 27 06:42:02 PM PDT 24
Finished Jun 27 06:42:43 PM PDT 24
Peak memory 206156 kb
Host smart-5fb0cf42-cbef-429c-b6c6-5544aa23017a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99354
8233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.993548233
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_invalid_sync.1564444010
Short name T2153
Test name
Test status
Simulation time 9215852430 ps
CPU time 253.44 seconds
Started Jun 27 06:41:53 PM PDT 24
Finished Jun 27 06:46:50 PM PDT 24
Peak memory 206460 kb
Host smart-b655e8b3-c6c3-4b25-a616-ea918d3b4717
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1564444010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.1564444010
Directory /workspace/44.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.731344991
Short name T841
Test name
Test status
Simulation time 219139739 ps
CPU time 0.84 seconds
Started Jun 27 06:41:52 PM PDT 24
Finished Jun 27 06:42:38 PM PDT 24
Peak memory 206228 kb
Host smart-e1d01451-2001-43eb-85f3-bea444ad7a6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73134
4991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.731344991
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.3777305401
Short name T1677
Test name
Test status
Simulation time 23278969507 ps
CPU time 23.73 seconds
Started Jun 27 06:41:53 PM PDT 24
Finished Jun 27 06:43:01 PM PDT 24
Peak memory 206344 kb
Host smart-f8558dd6-a663-412a-a3ce-e6ab1a4ccd31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37773
05401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.3777305401
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.2472473380
Short name T545
Test name
Test status
Simulation time 3340203594 ps
CPU time 3.99 seconds
Started Jun 27 06:41:49 PM PDT 24
Finished Jun 27 06:42:40 PM PDT 24
Peak memory 206196 kb
Host smart-2130c7a6-f3be-4c34-924a-214f8a3ae7ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24724
73380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.2472473380
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.2525928677
Short name T1208
Test name
Test status
Simulation time 13346998772 ps
CPU time 116.49 seconds
Started Jun 27 06:42:02 PM PDT 24
Finished Jun 27 06:44:42 PM PDT 24
Peak memory 206352 kb
Host smart-7ecdbf87-0c23-4f3e-bde1-a49434250c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25259
28677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.2525928677
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.2414226082
Short name T1821
Test name
Test status
Simulation time 6586342865 ps
CPU time 181.16 seconds
Started Jun 27 06:41:53 PM PDT 24
Finished Jun 27 06:45:38 PM PDT 24
Peak memory 206428 kb
Host smart-8ce098ea-39ff-4234-b8a4-aae20cdeaf47
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2414226082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.2414226082
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.1048288474
Short name T1624
Test name
Test status
Simulation time 234787029 ps
CPU time 0.93 seconds
Started Jun 27 06:41:53 PM PDT 24
Finished Jun 27 06:42:38 PM PDT 24
Peak memory 206236 kb
Host smart-5d8ff963-b492-44a9-9495-168f18118b7c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1048288474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.1048288474
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.2758576391
Short name T656
Test name
Test status
Simulation time 220634173 ps
CPU time 0.92 seconds
Started Jun 27 06:41:53 PM PDT 24
Finished Jun 27 06:42:38 PM PDT 24
Peak memory 206260 kb
Host smart-db8c58a7-19ab-4325-86df-aa5efcc2f8bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27585
76391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.2758576391
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.733216966
Short name T2392
Test name
Test status
Simulation time 4737300692 ps
CPU time 41.89 seconds
Started Jun 27 06:41:52 PM PDT 24
Finished Jun 27 06:43:19 PM PDT 24
Peak memory 206356 kb
Host smart-b21a9752-3c5e-421c-a629-8879bb831210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73321
6966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.733216966
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.3577850742
Short name T1652
Test name
Test status
Simulation time 4604180552 ps
CPU time 42.72 seconds
Started Jun 27 06:41:53 PM PDT 24
Finished Jun 27 06:43:20 PM PDT 24
Peak memory 206444 kb
Host smart-46b0ba2c-dc48-440a-a33f-dfcc48e6c132
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3577850742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.3577850742
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.2585095933
Short name T252
Test name
Test status
Simulation time 153082059 ps
CPU time 0.76 seconds
Started Jun 27 06:41:50 PM PDT 24
Finished Jun 27 06:42:37 PM PDT 24
Peak memory 206292 kb
Host smart-d7611b6e-f061-4350-94fb-4bbed0aecefd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2585095933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.2585095933
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.1403313801
Short name T376
Test name
Test status
Simulation time 221531392 ps
CPU time 0.83 seconds
Started Jun 27 06:41:46 PM PDT 24
Finished Jun 27 06:42:35 PM PDT 24
Peak memory 206292 kb
Host smart-391fe751-0d15-4ea1-94cb-133d0ab4a15e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14033
13801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.1403313801
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.3561082925
Short name T118
Test name
Test status
Simulation time 228650024 ps
CPU time 0.86 seconds
Started Jun 27 06:41:54 PM PDT 24
Finished Jun 27 06:42:39 PM PDT 24
Peak memory 206244 kb
Host smart-c71150f4-9fd2-49bf-8f26-9120be640d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35610
82925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.3561082925
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.3071753855
Short name T2431
Test name
Test status
Simulation time 187125599 ps
CPU time 0.87 seconds
Started Jun 27 06:41:48 PM PDT 24
Finished Jun 27 06:42:34 PM PDT 24
Peak memory 206292 kb
Host smart-675a7b41-275f-4253-8327-41b096c205da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30717
53855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.3071753855
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.3781053861
Short name T2065
Test name
Test status
Simulation time 155122600 ps
CPU time 0.76 seconds
Started Jun 27 06:41:49 PM PDT 24
Finished Jun 27 06:42:37 PM PDT 24
Peak memory 206308 kb
Host smart-ed31611e-0963-4ce4-b145-ea29aa091071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37810
53861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.3781053861
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.804643587
Short name T2511
Test name
Test status
Simulation time 159293418 ps
CPU time 0.8 seconds
Started Jun 27 06:41:49 PM PDT 24
Finished Jun 27 06:42:37 PM PDT 24
Peak memory 206208 kb
Host smart-cd9b99a7-f2c3-4ff3-b072-d948f70616c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80464
3587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.804643587
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.2690515413
Short name T185
Test name
Test status
Simulation time 155027653 ps
CPU time 0.79 seconds
Started Jun 27 06:41:51 PM PDT 24
Finished Jun 27 06:42:38 PM PDT 24
Peak memory 206276 kb
Host smart-d09798dd-4bc6-404a-9f91-77995955af33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26905
15413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.2690515413
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.1304807686
Short name T2168
Test name
Test status
Simulation time 218011757 ps
CPU time 0.92 seconds
Started Jun 27 06:41:49 PM PDT 24
Finished Jun 27 06:42:37 PM PDT 24
Peak memory 206304 kb
Host smart-b819b55c-52d0-4fa8-b104-00ffb53e2e20
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1304807686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.1304807686
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.775248022
Short name T549
Test name
Test status
Simulation time 155345335 ps
CPU time 0.76 seconds
Started Jun 27 06:41:48 PM PDT 24
Finished Jun 27 06:42:33 PM PDT 24
Peak memory 206276 kb
Host smart-6446e193-c7d6-4d38-8b61-4f27cfc08fe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77524
8022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.775248022
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.3942281110
Short name T1796
Test name
Test status
Simulation time 42426662 ps
CPU time 0.65 seconds
Started Jun 27 06:41:53 PM PDT 24
Finished Jun 27 06:42:38 PM PDT 24
Peak memory 206276 kb
Host smart-fa94eb50-7ded-41cf-b424-9a59e97f0c14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39422
81110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.3942281110
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.2474665735
Short name T2141
Test name
Test status
Simulation time 21631128568 ps
CPU time 44.06 seconds
Started Jun 27 06:41:50 PM PDT 24
Finished Jun 27 06:43:20 PM PDT 24
Peak memory 206452 kb
Host smart-ee290c51-0fca-4bc0-81df-09a6ec2195af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24746
65735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.2474665735
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.3490726092
Short name T2430
Test name
Test status
Simulation time 192853170 ps
CPU time 0.82 seconds
Started Jun 27 06:41:52 PM PDT 24
Finished Jun 27 06:42:38 PM PDT 24
Peak memory 206244 kb
Host smart-be78a84d-b006-49d5-bdbb-dedce1e0d9e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34907
26092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.3490726092
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.1480966914
Short name T1243
Test name
Test status
Simulation time 225451923 ps
CPU time 0.88 seconds
Started Jun 27 06:41:51 PM PDT 24
Finished Jun 27 06:42:38 PM PDT 24
Peak memory 206096 kb
Host smart-f6d9e945-22fb-4c39-ab70-a41eb2e3bfc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14809
66914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.1480966914
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.1774418692
Short name T940
Test name
Test status
Simulation time 211996844 ps
CPU time 0.86 seconds
Started Jun 27 06:41:54 PM PDT 24
Finished Jun 27 06:42:38 PM PDT 24
Peak memory 206308 kb
Host smart-4878fdf2-8946-4340-a7ce-44b57450c0e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17744
18692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.1774418692
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.494817825
Short name T1992
Test name
Test status
Simulation time 180976884 ps
CPU time 0.81 seconds
Started Jun 27 06:41:50 PM PDT 24
Finished Jun 27 06:42:37 PM PDT 24
Peak memory 206276 kb
Host smart-de3fe543-9af4-4ff7-8310-ea12809365d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49481
7825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.494817825
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.493093412
Short name T983
Test name
Test status
Simulation time 175074488 ps
CPU time 0.8 seconds
Started Jun 27 06:41:48 PM PDT 24
Finished Jun 27 06:42:35 PM PDT 24
Peak memory 206276 kb
Host smart-6d28d2a4-8f51-40b4-b434-7ded2ee918f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49309
3412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.493093412
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.685053613
Short name T2254
Test name
Test status
Simulation time 209728549 ps
CPU time 0.86 seconds
Started Jun 27 06:41:53 PM PDT 24
Finished Jun 27 06:42:38 PM PDT 24
Peak memory 206256 kb
Host smart-c5724b01-e858-405a-b5f5-1ff629c01bea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68505
3613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.685053613
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.4171336908
Short name T515
Test name
Test status
Simulation time 154510494 ps
CPU time 0.76 seconds
Started Jun 27 06:41:49 PM PDT 24
Finished Jun 27 06:42:37 PM PDT 24
Peak memory 206304 kb
Host smart-3cf32dc6-d718-419e-a52c-f8a1eed2300c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41713
36908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.4171336908
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.1992957363
Short name T486
Test name
Test status
Simulation time 211578246 ps
CPU time 0.93 seconds
Started Jun 27 06:41:51 PM PDT 24
Finished Jun 27 06:42:38 PM PDT 24
Peak memory 206292 kb
Host smart-26f17f63-620a-4d68-9617-e51896073dcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19929
57363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.1992957363
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.303912416
Short name T1259
Test name
Test status
Simulation time 3951977190 ps
CPU time 35.73 seconds
Started Jun 27 06:41:52 PM PDT 24
Finished Jun 27 06:43:13 PM PDT 24
Peak memory 206464 kb
Host smart-65e6c1d7-1175-48c7-b081-e987c57583b4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=303912416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.303912416
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.169441632
Short name T2408
Test name
Test status
Simulation time 195409938 ps
CPU time 0.82 seconds
Started Jun 27 06:41:52 PM PDT 24
Finished Jun 27 06:42:38 PM PDT 24
Peak memory 206256 kb
Host smart-9addf85a-53f0-426c-b3b4-bf0d1feca8ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16944
1632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.169441632
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.168317312
Short name T443
Test name
Test status
Simulation time 145838383 ps
CPU time 0.77 seconds
Started Jun 27 06:41:49 PM PDT 24
Finished Jun 27 06:42:37 PM PDT 24
Peak memory 206300 kb
Host smart-396461ec-696d-4675-8af4-5c7dd23290be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16831
7312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.168317312
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.4022298204
Short name T1211
Test name
Test status
Simulation time 5766614937 ps
CPU time 160.6 seconds
Started Jun 27 06:41:50 PM PDT 24
Finished Jun 27 06:45:17 PM PDT 24
Peak memory 206348 kb
Host smart-a2f9ece4-cecd-43b7-9b74-0705ba9915c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40222
98204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.4022298204
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.3923812836
Short name T1295
Test name
Test status
Simulation time 95791798 ps
CPU time 0.72 seconds
Started Jun 27 06:42:03 PM PDT 24
Finished Jun 27 06:42:46 PM PDT 24
Peak memory 206364 kb
Host smart-c77b946b-a0c8-466f-b7fb-772396753ddc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3923812836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.3923812836
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.869322949
Short name T1565
Test name
Test status
Simulation time 3942092051 ps
CPU time 5.2 seconds
Started Jun 27 06:41:52 PM PDT 24
Finished Jun 27 06:42:42 PM PDT 24
Peak memory 206344 kb
Host smart-6ef263ae-ba1e-4179-a40e-a2ba1217b168
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=869322949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.869322949
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.3252641054
Short name T201
Test name
Test status
Simulation time 13382608110 ps
CPU time 11.84 seconds
Started Jun 27 06:42:01 PM PDT 24
Finished Jun 27 06:42:54 PM PDT 24
Peak memory 206220 kb
Host smart-6a5ea7d8-5d51-4906-9acc-3345b09f4d26
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3252641054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.3252641054
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.1052131434
Short name T2443
Test name
Test status
Simulation time 23399236820 ps
CPU time 25.32 seconds
Started Jun 27 06:42:01 PM PDT 24
Finished Jun 27 06:43:07 PM PDT 24
Peak memory 206296 kb
Host smart-80e0edef-600d-4f1a-ae69-f9cb287d484f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1052131434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.1052131434
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.1990117458
Short name T1696
Test name
Test status
Simulation time 185738533 ps
CPU time 0.83 seconds
Started Jun 27 06:41:56 PM PDT 24
Finished Jun 27 06:42:40 PM PDT 24
Peak memory 206280 kb
Host smart-e09ba467-8e54-4a19-883f-b23f87d29a97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19901
17458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.1990117458
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.1482891764
Short name T526
Test name
Test status
Simulation time 165893068 ps
CPU time 0.74 seconds
Started Jun 27 06:42:02 PM PDT 24
Finished Jun 27 06:42:45 PM PDT 24
Peak memory 206152 kb
Host smart-c7dd7acf-2ba8-43e8-b45f-33490409a2af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14828
91764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.1482891764
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.2188372041
Short name T2393
Test name
Test status
Simulation time 197229888 ps
CPU time 0.85 seconds
Started Jun 27 06:41:56 PM PDT 24
Finished Jun 27 06:42:40 PM PDT 24
Peak memory 206272 kb
Host smart-34efe34b-43b7-478e-a034-36524e554436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21883
72041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.2188372041
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.2912683745
Short name T1389
Test name
Test status
Simulation time 1038372678 ps
CPU time 2.58 seconds
Started Jun 27 06:41:56 PM PDT 24
Finished Jun 27 06:42:42 PM PDT 24
Peak memory 206352 kb
Host smart-5e8a0d4d-46ab-4835-a23c-94ba10020eeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29126
83745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.2912683745
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.2887098258
Short name T1947
Test name
Test status
Simulation time 16878984399 ps
CPU time 30.9 seconds
Started Jun 27 06:41:57 PM PDT 24
Finished Jun 27 06:43:10 PM PDT 24
Peak memory 206492 kb
Host smart-9393259a-020e-4b66-b14e-7c377654e972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28870
98258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.2887098258
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.1146795612
Short name T972
Test name
Test status
Simulation time 300580283 ps
CPU time 0.99 seconds
Started Jun 27 06:42:02 PM PDT 24
Finished Jun 27 06:42:43 PM PDT 24
Peak memory 206156 kb
Host smart-b5e2c2da-54d1-474e-866a-cfa88ddc05a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11467
95612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.1146795612
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.4110854803
Short name T2420
Test name
Test status
Simulation time 168497767 ps
CPU time 0.75 seconds
Started Jun 27 06:42:02 PM PDT 24
Finished Jun 27 06:42:43 PM PDT 24
Peak memory 206148 kb
Host smart-9cb9e06c-ef56-42be-9ecd-1b09e0357438
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41108
54803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.4110854803
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.2676227646
Short name T1568
Test name
Test status
Simulation time 55849751 ps
CPU time 0.68 seconds
Started Jun 27 06:41:50 PM PDT 24
Finished Jun 27 06:42:37 PM PDT 24
Peak memory 206280 kb
Host smart-377a78be-5876-4a5e-a699-a634ad48f780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26762
27646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.2676227646
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.2543438257
Short name T1395
Test name
Test status
Simulation time 939104655 ps
CPU time 2.23 seconds
Started Jun 27 06:41:53 PM PDT 24
Finished Jun 27 06:42:39 PM PDT 24
Peak memory 206436 kb
Host smart-9d6f1ecc-e6ae-42cb-81cb-cf0fc1dd481c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25434
38257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.2543438257
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.3191016998
Short name T2544
Test name
Test status
Simulation time 414540127 ps
CPU time 2.3 seconds
Started Jun 27 06:41:54 PM PDT 24
Finished Jun 27 06:42:41 PM PDT 24
Peak memory 206424 kb
Host smart-77650ace-79bc-42b7-8c10-5f83ca27c2d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31910
16998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.3191016998
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.2880562845
Short name T958
Test name
Test status
Simulation time 255589173 ps
CPU time 0.89 seconds
Started Jun 27 06:42:06 PM PDT 24
Finished Jun 27 06:42:48 PM PDT 24
Peak memory 206272 kb
Host smart-fbc31ede-39ae-474f-a6a5-09005cf3992d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28805
62845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.2880562845
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.2722744087
Short name T640
Test name
Test status
Simulation time 150860935 ps
CPU time 0.78 seconds
Started Jun 27 06:42:07 PM PDT 24
Finished Jun 27 06:42:48 PM PDT 24
Peak memory 206288 kb
Host smart-e0e6a8d2-0ee0-48c2-8eca-10e91cf62f5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27227
44087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.2722744087
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.3145848355
Short name T896
Test name
Test status
Simulation time 229248367 ps
CPU time 0.89 seconds
Started Jun 27 06:42:00 PM PDT 24
Finished Jun 27 06:42:43 PM PDT 24
Peak memory 206288 kb
Host smart-36ff0156-7979-4e5c-960b-5312cc52216a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31458
48355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.3145848355
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_invalid_sync.3796542262
Short name T2305
Test name
Test status
Simulation time 7610532544 ps
CPU time 210.34 seconds
Started Jun 27 06:41:59 PM PDT 24
Finished Jun 27 06:46:12 PM PDT 24
Peak memory 206460 kb
Host smart-45c738d6-d96d-4a73-b48e-2ab81644d7aa
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3796542262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.3796542262
Directory /workspace/45.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.3746571138
Short name T1118
Test name
Test status
Simulation time 203330113 ps
CPU time 0.88 seconds
Started Jun 27 06:42:03 PM PDT 24
Finished Jun 27 06:42:46 PM PDT 24
Peak memory 206252 kb
Host smart-35abbc52-2763-4524-9c18-04f5bb155ef8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37465
71138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.3746571138
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.2941822178
Short name T193
Test name
Test status
Simulation time 23357527935 ps
CPU time 22.06 seconds
Started Jun 27 06:42:00 PM PDT 24
Finished Jun 27 06:43:04 PM PDT 24
Peak memory 206336 kb
Host smart-8b6fc7ea-236f-4d24-a1c3-d940688f41b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29418
22178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.2941822178
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.444131425
Short name T1870
Test name
Test status
Simulation time 3334261523 ps
CPU time 3.69 seconds
Started Jun 27 06:42:00 PM PDT 24
Finished Jun 27 06:42:46 PM PDT 24
Peak memory 206344 kb
Host smart-5e631990-6727-4e09-b314-d41afb948daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44413
1425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.444131425
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.1018993985
Short name T1636
Test name
Test status
Simulation time 12380470349 ps
CPU time 334.41 seconds
Started Jun 27 06:42:00 PM PDT 24
Finished Jun 27 06:48:16 PM PDT 24
Peak memory 206504 kb
Host smart-54f24d5a-5d4f-464f-ac5a-6b005dd2acb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10189
93985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.1018993985
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.3101163562
Short name T1069
Test name
Test status
Simulation time 4858414334 ps
CPU time 126.64 seconds
Started Jun 27 06:42:08 PM PDT 24
Finished Jun 27 06:44:54 PM PDT 24
Peak memory 206436 kb
Host smart-94dba151-4104-4715-a955-db16ee96cddc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3101163562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.3101163562
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.4227642467
Short name T384
Test name
Test status
Simulation time 237601414 ps
CPU time 0.86 seconds
Started Jun 27 06:42:06 PM PDT 24
Finished Jun 27 06:42:48 PM PDT 24
Peak memory 206276 kb
Host smart-da39d644-ff81-4d68-b66f-e5058fc203c7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4227642467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.4227642467
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.3895433920
Short name T1805
Test name
Test status
Simulation time 190476577 ps
CPU time 0.81 seconds
Started Jun 27 06:42:04 PM PDT 24
Finished Jun 27 06:42:46 PM PDT 24
Peak memory 206228 kb
Host smart-c4565c46-6b9f-482a-94d5-b33b4e82f86e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38954
33920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.3895433920
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.727923053
Short name T762
Test name
Test status
Simulation time 6724025203 ps
CPU time 174.51 seconds
Started Jun 27 06:42:03 PM PDT 24
Finished Jun 27 06:45:40 PM PDT 24
Peak memory 206408 kb
Host smart-94840708-3b06-4652-adb5-aceb9d495eed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72792
3053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.727923053
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.710176930
Short name T1830
Test name
Test status
Simulation time 3131156234 ps
CPU time 25.53 seconds
Started Jun 27 06:42:06 PM PDT 24
Finished Jun 27 06:43:12 PM PDT 24
Peak memory 206436 kb
Host smart-23235c3a-cd30-4761-bf02-c6bb765a1966
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=710176930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.710176930
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.4240287223
Short name T734
Test name
Test status
Simulation time 178949063 ps
CPU time 0.79 seconds
Started Jun 27 06:42:00 PM PDT 24
Finished Jun 27 06:42:43 PM PDT 24
Peak memory 206248 kb
Host smart-27318580-e12d-4a7a-b8fc-ad253cc09fe6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4240287223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.4240287223
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.802744365
Short name T1914
Test name
Test status
Simulation time 144351940 ps
CPU time 0.76 seconds
Started Jun 27 06:42:05 PM PDT 24
Finished Jun 27 06:42:46 PM PDT 24
Peak memory 206196 kb
Host smart-da69c3ef-0f38-4dfa-9e41-09176407d355
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80274
4365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.802744365
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.4193365848
Short name T131
Test name
Test status
Simulation time 225590193 ps
CPU time 0.9 seconds
Started Jun 27 06:42:09 PM PDT 24
Finished Jun 27 06:42:48 PM PDT 24
Peak memory 206276 kb
Host smart-39d17c7c-1937-44b5-8a0c-f86b53991620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41933
65848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.4193365848
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.1384633326
Short name T2374
Test name
Test status
Simulation time 165099639 ps
CPU time 0.79 seconds
Started Jun 27 06:42:00 PM PDT 24
Finished Jun 27 06:42:43 PM PDT 24
Peak memory 206312 kb
Host smart-939a0698-3481-457a-b98e-f6db30c32d7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13846
33326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.1384633326
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.1966818837
Short name T1117
Test name
Test status
Simulation time 166022740 ps
CPU time 0.75 seconds
Started Jun 27 06:42:08 PM PDT 24
Finished Jun 27 06:42:48 PM PDT 24
Peak memory 206276 kb
Host smart-2569e9b4-9222-4530-8a44-19d672000501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19668
18837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.1966818837
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.2158102323
Short name T1445
Test name
Test status
Simulation time 256489478 ps
CPU time 0.84 seconds
Started Jun 27 06:42:04 PM PDT 24
Finished Jun 27 06:42:46 PM PDT 24
Peak memory 206284 kb
Host smart-d4af33cf-9e5b-4db4-9fe5-a2175c057ece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21581
02323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.2158102323
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.4030982223
Short name T1420
Test name
Test status
Simulation time 172460956 ps
CPU time 0.83 seconds
Started Jun 27 06:42:03 PM PDT 24
Finished Jun 27 06:42:46 PM PDT 24
Peak memory 206308 kb
Host smart-a72b470c-7ade-4490-8abb-797caa30d078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40309
82223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.4030982223
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.1923391232
Short name T2004
Test name
Test status
Simulation time 172913444 ps
CPU time 0.86 seconds
Started Jun 27 06:42:04 PM PDT 24
Finished Jun 27 06:42:46 PM PDT 24
Peak memory 206300 kb
Host smart-ec6f9786-233b-4984-bf8a-62b78b982583
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1923391232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.1923391232
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.560076909
Short name T480
Test name
Test status
Simulation time 174163364 ps
CPU time 0.76 seconds
Started Jun 27 06:42:07 PM PDT 24
Finished Jun 27 06:42:48 PM PDT 24
Peak memory 206280 kb
Host smart-cfaaa2eb-a440-440d-b4cd-a65802a1386c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56007
6909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.560076909
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.4211271386
Short name T1676
Test name
Test status
Simulation time 34192082 ps
CPU time 0.63 seconds
Started Jun 27 06:42:05 PM PDT 24
Finished Jun 27 06:42:46 PM PDT 24
Peak memory 206252 kb
Host smart-fafd1839-cf2f-44bb-8485-55571bdd8745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42112
71386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.4211271386
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.3037244349
Short name T278
Test name
Test status
Simulation time 12802400648 ps
CPU time 25.87 seconds
Started Jun 27 06:42:06 PM PDT 24
Finished Jun 27 06:43:13 PM PDT 24
Peak memory 206448 kb
Host smart-b42eaef4-c8b9-4e84-b689-194cfee76328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30372
44349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.3037244349
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.2017570816
Short name T82
Test name
Test status
Simulation time 188619650 ps
CPU time 0.84 seconds
Started Jun 27 06:42:05 PM PDT 24
Finished Jun 27 06:42:46 PM PDT 24
Peak memory 206256 kb
Host smart-ba374715-5aa5-499f-ad22-5834f98552ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20175
70816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.2017570816
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.340561649
Short name T2011
Test name
Test status
Simulation time 158632751 ps
CPU time 0.78 seconds
Started Jun 27 06:42:01 PM PDT 24
Finished Jun 27 06:42:43 PM PDT 24
Peak memory 206300 kb
Host smart-04f890bf-3afa-42c2-9d35-2acc01c108fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34056
1649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.340561649
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.3577164183
Short name T429
Test name
Test status
Simulation time 191183617 ps
CPU time 0.79 seconds
Started Jun 27 06:42:03 PM PDT 24
Finished Jun 27 06:42:46 PM PDT 24
Peak memory 206268 kb
Host smart-a89cd092-d4ef-4a46-87b2-b3e2eb62eef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35771
64183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.3577164183
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.914497409
Short name T1594
Test name
Test status
Simulation time 205230616 ps
CPU time 0.83 seconds
Started Jun 27 06:42:05 PM PDT 24
Finished Jun 27 06:42:46 PM PDT 24
Peak memory 206252 kb
Host smart-69ff985c-cf71-4de6-a485-391f5ce622a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91449
7409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.914497409
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.590556957
Short name T1502
Test name
Test status
Simulation time 197394592 ps
CPU time 0.78 seconds
Started Jun 27 06:42:06 PM PDT 24
Finished Jun 27 06:42:48 PM PDT 24
Peak memory 206272 kb
Host smart-825c3128-0ae4-4076-8e18-2fc7110afc59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59055
6957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.590556957
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.1583563064
Short name T547
Test name
Test status
Simulation time 150084562 ps
CPU time 0.7 seconds
Started Jun 27 06:42:02 PM PDT 24
Finished Jun 27 06:42:45 PM PDT 24
Peak memory 206276 kb
Host smart-7044c4b3-8a42-4847-83e0-8f88e6b75340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15835
63064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.1583563064
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.1556366114
Short name T2008
Test name
Test status
Simulation time 150344851 ps
CPU time 0.77 seconds
Started Jun 27 06:42:04 PM PDT 24
Finished Jun 27 06:42:46 PM PDT 24
Peak memory 206232 kb
Host smart-1cde0365-37fc-4b12-ae1a-6e14ab79bdc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15563
66114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.1556366114
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.2158097333
Short name T51
Test name
Test status
Simulation time 230237592 ps
CPU time 0.89 seconds
Started Jun 27 06:42:07 PM PDT 24
Finished Jun 27 06:42:48 PM PDT 24
Peak memory 206284 kb
Host smart-0ac80d2b-8194-4c64-97e6-b09140c0cf4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21580
97333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.2158097333
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.2505875794
Short name T2435
Test name
Test status
Simulation time 5289784145 ps
CPU time 143.95 seconds
Started Jun 27 06:42:05 PM PDT 24
Finished Jun 27 06:45:09 PM PDT 24
Peak memory 206452 kb
Host smart-595648b6-42d3-436d-850c-460ea28cf343
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2505875794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.2505875794
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.2217092856
Short name T1910
Test name
Test status
Simulation time 242296634 ps
CPU time 0.91 seconds
Started Jun 27 06:42:08 PM PDT 24
Finished Jun 27 06:42:48 PM PDT 24
Peak memory 206276 kb
Host smart-99c3c0cd-64f3-4632-9f07-4c540e5328dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22170
92856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.2217092856
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.1187147741
Short name T959
Test name
Test status
Simulation time 150470738 ps
CPU time 0.73 seconds
Started Jun 27 06:42:04 PM PDT 24
Finished Jun 27 06:42:46 PM PDT 24
Peak memory 206152 kb
Host smart-d9411833-4b87-4cc1-a0bb-33e226a1ef1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11871
47741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.1187147741
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.2947492277
Short name T334
Test name
Test status
Simulation time 4891946125 ps
CPU time 135.53 seconds
Started Jun 27 06:42:00 PM PDT 24
Finished Jun 27 06:44:57 PM PDT 24
Peak memory 206596 kb
Host smart-155fb0e2-b85c-48b4-ab19-72c47844f989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29474
92277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.2947492277
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.3719256922
Short name T784
Test name
Test status
Simulation time 42387374 ps
CPU time 0.66 seconds
Started Jun 27 06:42:19 PM PDT 24
Finished Jun 27 06:42:56 PM PDT 24
Peak memory 206352 kb
Host smart-8d53b337-4c8e-4d78-944e-2bafdb118856
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3719256922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.3719256922
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.1132710318
Short name T1747
Test name
Test status
Simulation time 3654470687 ps
CPU time 5.17 seconds
Started Jun 27 06:42:03 PM PDT 24
Finished Jun 27 06:42:50 PM PDT 24
Peak memory 206336 kb
Host smart-6568fd6e-1871-49bc-ab8e-5e04103eabdd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1132710318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.1132710318
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.3673085139
Short name T1592
Test name
Test status
Simulation time 13352314752 ps
CPU time 14.33 seconds
Started Jun 27 06:42:03 PM PDT 24
Finished Jun 27 06:43:00 PM PDT 24
Peak memory 206412 kb
Host smart-d2cf6ac0-8ee5-42e1-a989-314373e47700
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3673085139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.3673085139
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.2866568444
Short name T1618
Test name
Test status
Simulation time 23454770016 ps
CPU time 22.6 seconds
Started Jun 27 06:42:07 PM PDT 24
Finished Jun 27 06:43:10 PM PDT 24
Peak memory 206480 kb
Host smart-3e05a106-4a9d-4797-b3bc-fc48bb73e7cc
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2866568444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.2866568444
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.2028689319
Short name T1643
Test name
Test status
Simulation time 154389322 ps
CPU time 0.75 seconds
Started Jun 27 06:42:04 PM PDT 24
Finished Jun 27 06:42:46 PM PDT 24
Peak memory 206156 kb
Host smart-1ebd8b2f-38a2-49f3-aa29-b65e8f1ca1b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20286
89319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.2028689319
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.2964121047
Short name T2050
Test name
Test status
Simulation time 146979481 ps
CPU time 0.77 seconds
Started Jun 27 06:42:02 PM PDT 24
Finished Jun 27 06:42:45 PM PDT 24
Peak memory 206224 kb
Host smart-a6cf9ef7-9267-4da2-8786-86eef6287f3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29641
21047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.2964121047
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.3992067974
Short name T1094
Test name
Test status
Simulation time 277087897 ps
CPU time 1.11 seconds
Started Jun 27 06:42:21 PM PDT 24
Finished Jun 27 06:42:56 PM PDT 24
Peak memory 206272 kb
Host smart-00f25134-55f0-4ca4-a263-d17a1855fdc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39920
67974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.3992067974
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.2592746068
Short name T1366
Test name
Test status
Simulation time 882332425 ps
CPU time 1.9 seconds
Started Jun 27 06:42:18 PM PDT 24
Finished Jun 27 06:42:56 PM PDT 24
Peak memory 206420 kb
Host smart-20364b1d-978e-42f8-81ac-fbec587aa090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25927
46068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.2592746068
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.462318018
Short name T2211
Test name
Test status
Simulation time 21128712494 ps
CPU time 39.3 seconds
Started Jun 27 06:42:16 PM PDT 24
Finished Jun 27 06:43:31 PM PDT 24
Peak memory 206444 kb
Host smart-851b817b-fa4c-4778-b9d6-3cbd47eff730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46231
8018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.462318018
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.109329495
Short name T218
Test name
Test status
Simulation time 347869651 ps
CPU time 1.11 seconds
Started Jun 27 06:42:20 PM PDT 24
Finished Jun 27 06:42:56 PM PDT 24
Peak memory 206284 kb
Host smart-73aca738-a8f9-403c-938b-9863ca37ff75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10932
9495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.109329495
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.3735016272
Short name T833
Test name
Test status
Simulation time 140861173 ps
CPU time 0.74 seconds
Started Jun 27 06:42:21 PM PDT 24
Finished Jun 27 06:42:56 PM PDT 24
Peak memory 206264 kb
Host smart-7a933737-c54c-4e32-8d63-0ca6e725e56c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37350
16272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.3735016272
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.663067722
Short name T1533
Test name
Test status
Simulation time 46354867 ps
CPU time 0.63 seconds
Started Jun 27 06:42:21 PM PDT 24
Finished Jun 27 06:42:56 PM PDT 24
Peak memory 206276 kb
Host smart-3e561987-08a7-4bc3-b9c0-6dcc252da42f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66306
7722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.663067722
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.1341002939
Short name T2563
Test name
Test status
Simulation time 981654592 ps
CPU time 2.24 seconds
Started Jun 27 06:42:18 PM PDT 24
Finished Jun 27 06:42:56 PM PDT 24
Peak memory 206304 kb
Host smart-fb4227c9-fbe7-48d7-b252-e5685afbe3db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13410
02939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.1341002939
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.22792569
Short name T2594
Test name
Test status
Simulation time 332597164 ps
CPU time 2.28 seconds
Started Jun 27 06:42:20 PM PDT 24
Finished Jun 27 06:42:57 PM PDT 24
Peak memory 206352 kb
Host smart-e871e894-92b2-4d47-9165-a20554055eb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22792
569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.22792569
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.2287837952
Short name T1509
Test name
Test status
Simulation time 223945908 ps
CPU time 0.93 seconds
Started Jun 27 06:42:21 PM PDT 24
Finished Jun 27 06:42:56 PM PDT 24
Peak memory 206304 kb
Host smart-a47eb73d-b369-4a89-9ac8-51e7adc5f380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22878
37952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.2287837952
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.366949908
Short name T1346
Test name
Test status
Simulation time 150498694 ps
CPU time 0.78 seconds
Started Jun 27 06:42:16 PM PDT 24
Finished Jun 27 06:42:53 PM PDT 24
Peak memory 206276 kb
Host smart-d6e7cc12-c7d5-42cb-9bb5-5a44a4d278b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36694
9908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.366949908
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.3995512512
Short name T472
Test name
Test status
Simulation time 220529892 ps
CPU time 0.88 seconds
Started Jun 27 06:42:20 PM PDT 24
Finished Jun 27 06:42:56 PM PDT 24
Peak memory 206288 kb
Host smart-760a2056-5250-43d6-88b0-917921024672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39955
12512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.3995512512
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_invalid_sync.2759533816
Short name T2125
Test name
Test status
Simulation time 9181297203 ps
CPU time 259.96 seconds
Started Jun 27 06:42:18 PM PDT 24
Finished Jun 27 06:47:14 PM PDT 24
Peak memory 206600 kb
Host smart-60145439-cd3f-4501-8b39-1d50c1340b74
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2759533816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_invalid_sync.2759533816
Directory /workspace/46.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.3192169934
Short name T1663
Test name
Test status
Simulation time 177412886 ps
CPU time 0.81 seconds
Started Jun 27 06:42:16 PM PDT 24
Finished Jun 27 06:42:54 PM PDT 24
Peak memory 206248 kb
Host smart-0ab82cfe-f70a-4755-9a96-11fd29ce4cab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31921
69934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.3192169934
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.2265266998
Short name T1890
Test name
Test status
Simulation time 23317824656 ps
CPU time 24.36 seconds
Started Jun 27 06:42:21 PM PDT 24
Finished Jun 27 06:43:20 PM PDT 24
Peak memory 206328 kb
Host smart-e80b20f2-9fe3-4334-80dd-028f8212ca50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22652
66998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.2265266998
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.2594157780
Short name T540
Test name
Test status
Simulation time 3327201416 ps
CPU time 3.64 seconds
Started Jun 27 06:42:16 PM PDT 24
Finished Jun 27 06:42:56 PM PDT 24
Peak memory 206268 kb
Host smart-f2223bba-29b7-4452-a064-394da781e269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25941
57780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.2594157780
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.387551210
Short name T1410
Test name
Test status
Simulation time 7162009981 ps
CPU time 50.51 seconds
Started Jun 27 06:42:18 PM PDT 24
Finished Jun 27 06:43:45 PM PDT 24
Peak memory 206484 kb
Host smart-e6c14b4c-7b54-4401-9b06-70e33f2fda53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38755
1210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.387551210
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.1738476154
Short name T1232
Test name
Test status
Simulation time 5261754523 ps
CPU time 152.81 seconds
Started Jun 27 06:42:18 PM PDT 24
Finished Jun 27 06:45:27 PM PDT 24
Peak memory 206452 kb
Host smart-0085e691-db0f-4625-8bca-6eb015f26da5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1738476154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.1738476154
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.2101391827
Short name T2438
Test name
Test status
Simulation time 274521144 ps
CPU time 0.92 seconds
Started Jun 27 06:42:22 PM PDT 24
Finished Jun 27 06:42:56 PM PDT 24
Peak memory 206232 kb
Host smart-7483fda3-c137-42ca-ae98-75cfd2987117
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2101391827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.2101391827
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.1973604842
Short name T1297
Test name
Test status
Simulation time 191652824 ps
CPU time 0.86 seconds
Started Jun 27 06:42:21 PM PDT 24
Finished Jun 27 06:42:56 PM PDT 24
Peak memory 206276 kb
Host smart-40c4fc72-d680-4d0f-81ba-4b0f436ee4e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19736
04842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.1973604842
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.3511977965
Short name T2293
Test name
Test status
Simulation time 4798245315 ps
CPU time 43.03 seconds
Started Jun 27 06:42:22 PM PDT 24
Finished Jun 27 06:43:39 PM PDT 24
Peak memory 206328 kb
Host smart-b9c73d07-81bb-447c-9420-ace191d5159c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35119
77965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.3511977965
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.2560359462
Short name T1034
Test name
Test status
Simulation time 4719252900 ps
CPU time 131.16 seconds
Started Jun 27 06:42:20 PM PDT 24
Finished Jun 27 06:45:06 PM PDT 24
Peak memory 206452 kb
Host smart-bb2ece50-f7b8-4c71-969a-916dfc66b31a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2560359462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.2560359462
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.2347042475
Short name T426
Test name
Test status
Simulation time 156768760 ps
CPU time 0.8 seconds
Started Jun 27 06:42:20 PM PDT 24
Finished Jun 27 06:42:56 PM PDT 24
Peak memory 206276 kb
Host smart-e7853b8d-3874-4ebf-ae01-4e38ea3bf9bb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2347042475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.2347042475
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.2725560543
Short name T1088
Test name
Test status
Simulation time 162948118 ps
CPU time 0.77 seconds
Started Jun 27 06:42:20 PM PDT 24
Finished Jun 27 06:42:56 PM PDT 24
Peak memory 206288 kb
Host smart-714d7f2d-4b76-4088-b5af-f0d71c01a793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27255
60543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.2725560543
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.79255843
Short name T111
Test name
Test status
Simulation time 201048131 ps
CPU time 0.9 seconds
Started Jun 27 06:42:20 PM PDT 24
Finished Jun 27 06:42:56 PM PDT 24
Peak memory 206300 kb
Host smart-a21cb153-3632-464c-b5db-30a101fbf7d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79255
843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.79255843
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.2349582757
Short name T2357
Test name
Test status
Simulation time 198719976 ps
CPU time 0.86 seconds
Started Jun 27 06:42:21 PM PDT 24
Finished Jun 27 06:42:56 PM PDT 24
Peak memory 206144 kb
Host smart-8056a540-1a31-491c-b9a0-c704c122e95e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23495
82757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.2349582757
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.3815768429
Short name T1772
Test name
Test status
Simulation time 209800441 ps
CPU time 0.84 seconds
Started Jun 27 06:42:22 PM PDT 24
Finished Jun 27 06:42:56 PM PDT 24
Peak memory 206208 kb
Host smart-84034552-069d-4bbd-b8c5-c53013dee61e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38157
68429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.3815768429
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.3491916888
Short name T792
Test name
Test status
Simulation time 174050787 ps
CPU time 0.78 seconds
Started Jun 27 06:42:22 PM PDT 24
Finished Jun 27 06:42:56 PM PDT 24
Peak memory 206280 kb
Host smart-4c19f02f-dccb-4983-9105-a4ab0d31cc93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34919
16888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.3491916888
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.733389037
Short name T159
Test name
Test status
Simulation time 200520203 ps
CPU time 0.77 seconds
Started Jun 27 06:42:20 PM PDT 24
Finished Jun 27 06:42:56 PM PDT 24
Peak memory 206284 kb
Host smart-ebd30a07-62e7-49c3-ac83-748d7bc8b5f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73338
9037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.733389037
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.1605893959
Short name T2188
Test name
Test status
Simulation time 229996101 ps
CPU time 1.04 seconds
Started Jun 27 06:42:16 PM PDT 24
Finished Jun 27 06:42:54 PM PDT 24
Peak memory 206264 kb
Host smart-221c3f05-c6f1-45b4-9ff9-1a26d39fb608
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1605893959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.1605893959
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.4016939863
Short name T1982
Test name
Test status
Simulation time 176960265 ps
CPU time 0.83 seconds
Started Jun 27 06:42:22 PM PDT 24
Finished Jun 27 06:42:56 PM PDT 24
Peak memory 206136 kb
Host smart-49cd25a8-b235-454a-9168-8ef481281b26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40169
39863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.4016939863
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.3463588037
Short name T25
Test name
Test status
Simulation time 39466248 ps
CPU time 0.67 seconds
Started Jun 27 06:42:17 PM PDT 24
Finished Jun 27 06:42:54 PM PDT 24
Peak memory 206268 kb
Host smart-4bac8ada-f78a-4fea-adf2-73db26ac12f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34635
88037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.3463588037
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.52845160
Short name T89
Test name
Test status
Simulation time 22035406504 ps
CPU time 49.3 seconds
Started Jun 27 06:42:17 PM PDT 24
Finished Jun 27 06:43:43 PM PDT 24
Peak memory 206484 kb
Host smart-ae1bf126-6e5f-419e-b934-d20903b99b1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52845
160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.52845160
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.2982384738
Short name T1164
Test name
Test status
Simulation time 169407863 ps
CPU time 0.87 seconds
Started Jun 27 06:42:20 PM PDT 24
Finished Jun 27 06:42:56 PM PDT 24
Peak memory 206272 kb
Host smart-f9fd248e-19b2-4705-865f-b0d9807527a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29823
84738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.2982384738
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.4228189718
Short name T865
Test name
Test status
Simulation time 178725939 ps
CPU time 0.8 seconds
Started Jun 27 06:42:19 PM PDT 24
Finished Jun 27 06:42:56 PM PDT 24
Peak memory 206280 kb
Host smart-0d552c40-d167-4527-8fc5-70bf3a18b56f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42281
89718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.4228189718
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.2034380854
Short name T2380
Test name
Test status
Simulation time 216688618 ps
CPU time 0.84 seconds
Started Jun 27 06:42:21 PM PDT 24
Finished Jun 27 06:42:56 PM PDT 24
Peak memory 206300 kb
Host smart-f47ea7a5-4729-421f-99b5-b301c2238bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20343
80854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.2034380854
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.1575834975
Short name T802
Test name
Test status
Simulation time 207610092 ps
CPU time 0.81 seconds
Started Jun 27 06:42:21 PM PDT 24
Finished Jun 27 06:42:56 PM PDT 24
Peak memory 206092 kb
Host smart-67399799-56da-47ee-b279-73fc60e08d0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15758
34975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.1575834975
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.766867013
Short name T1800
Test name
Test status
Simulation time 182521326 ps
CPU time 0.82 seconds
Started Jun 27 06:42:18 PM PDT 24
Finished Jun 27 06:42:55 PM PDT 24
Peak memory 206276 kb
Host smart-0e9a060f-0e1f-487c-8e0c-914c569c6b48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76686
7013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.766867013
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.462342424
Short name T1011
Test name
Test status
Simulation time 156643505 ps
CPU time 0.77 seconds
Started Jun 27 06:42:22 PM PDT 24
Finished Jun 27 06:42:56 PM PDT 24
Peak memory 206280 kb
Host smart-00b962fb-1764-4b19-9e7c-2e32b39cf71b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46234
2424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.462342424
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.4010274474
Short name T951
Test name
Test status
Simulation time 163309160 ps
CPU time 0.76 seconds
Started Jun 27 06:42:18 PM PDT 24
Finished Jun 27 06:42:55 PM PDT 24
Peak memory 206208 kb
Host smart-7813f936-c7a4-429c-916b-38e697866c72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40102
74474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.4010274474
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.731292640
Short name T2534
Test name
Test status
Simulation time 266832847 ps
CPU time 1.04 seconds
Started Jun 27 06:42:15 PM PDT 24
Finished Jun 27 06:42:53 PM PDT 24
Peak memory 206296 kb
Host smart-6ea83d2a-ec9f-48f6-a23f-63aa8a51b880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73129
2640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.731292640
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.4184279237
Short name T1708
Test name
Test status
Simulation time 4817733519 ps
CPU time 45.07 seconds
Started Jun 27 06:42:18 PM PDT 24
Finished Jun 27 06:43:39 PM PDT 24
Peak memory 206436 kb
Host smart-96dfdd28-385d-4d8d-89c5-985b2746dd6c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4184279237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.4184279237
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.464175601
Short name T314
Test name
Test status
Simulation time 173343607 ps
CPU time 0.79 seconds
Started Jun 27 06:42:17 PM PDT 24
Finished Jun 27 06:42:54 PM PDT 24
Peak memory 206256 kb
Host smart-cef97f3b-99c7-46d0-8126-37d09ae0b33b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46417
5601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.464175601
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.2982492584
Short name T1220
Test name
Test status
Simulation time 197623311 ps
CPU time 0.81 seconds
Started Jun 27 06:42:22 PM PDT 24
Finished Jun 27 06:42:56 PM PDT 24
Peak memory 206280 kb
Host smart-2f9c639f-8ae1-487f-81b9-f14797e110cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29824
92584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.2982492584
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.807613331
Short name T330
Test name
Test status
Simulation time 6190442820 ps
CPU time 55.52 seconds
Started Jun 27 06:42:17 PM PDT 24
Finished Jun 27 06:43:49 PM PDT 24
Peak memory 206384 kb
Host smart-bf322894-4207-4f74-98df-44d59a9c6a10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80761
3331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.807613331
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.3435753227
Short name T2597
Test name
Test status
Simulation time 28471327 ps
CPU time 0.66 seconds
Started Jun 27 06:42:40 PM PDT 24
Finished Jun 27 06:43:07 PM PDT 24
Peak memory 206340 kb
Host smart-799fbe2a-9a79-4894-8505-555703244e04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3435753227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.3435753227
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.1965738829
Short name T2228
Test name
Test status
Simulation time 4030143279 ps
CPU time 4.76 seconds
Started Jun 27 06:42:17 PM PDT 24
Finished Jun 27 06:42:58 PM PDT 24
Peak memory 206556 kb
Host smart-1d229af4-7d54-4251-b7c1-cb9d47251de1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1965738829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.1965738829
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.955965058
Short name T2484
Test name
Test status
Simulation time 13462733447 ps
CPU time 12.28 seconds
Started Jun 27 06:42:18 PM PDT 24
Finished Jun 27 06:43:06 PM PDT 24
Peak memory 206364 kb
Host smart-a4afceee-0975-4d22-b735-8ff685ee164a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=955965058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.955965058
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.314624636
Short name T619
Test name
Test status
Simulation time 23411154754 ps
CPU time 23.7 seconds
Started Jun 27 06:42:36 PM PDT 24
Finished Jun 27 06:43:27 PM PDT 24
Peak memory 206312 kb
Host smart-cef7fd45-ede3-410e-becd-078389e5b35d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=314624636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.314624636
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.3699082199
Short name T1195
Test name
Test status
Simulation time 201738908 ps
CPU time 0.86 seconds
Started Jun 27 06:42:35 PM PDT 24
Finished Jun 27 06:43:04 PM PDT 24
Peak memory 206272 kb
Host smart-12844549-3231-4e5f-af1a-86d097b52b78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36990
82199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.3699082199
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.2849691449
Short name T1556
Test name
Test status
Simulation time 158499970 ps
CPU time 0.78 seconds
Started Jun 27 06:42:33 PM PDT 24
Finished Jun 27 06:43:03 PM PDT 24
Peak memory 206300 kb
Host smart-b0006ebf-a8cf-44d9-8de7-a8bbe7b42027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28496
91449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.2849691449
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.4172346260
Short name T1493
Test name
Test status
Simulation time 504964866 ps
CPU time 1.41 seconds
Started Jun 27 06:42:36 PM PDT 24
Finished Jun 27 06:43:04 PM PDT 24
Peak memory 206436 kb
Host smart-ba808ebd-6104-465a-ba1e-ee7ba5e738e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41723
46260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.4172346260
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.677220482
Short name T161
Test name
Test status
Simulation time 911696476 ps
CPU time 2.09 seconds
Started Jun 27 06:42:36 PM PDT 24
Finished Jun 27 06:43:07 PM PDT 24
Peak memory 206328 kb
Host smart-c4f5b120-7aa8-42cf-87ee-fd8a09ea888e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67722
0482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.677220482
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.4278639321
Short name T1032
Test name
Test status
Simulation time 10010964801 ps
CPU time 16.59 seconds
Started Jun 27 06:42:39 PM PDT 24
Finished Jun 27 06:43:23 PM PDT 24
Peak memory 206488 kb
Host smart-1234dcf1-f735-44ce-be15-237c27bc1daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42786
39321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.4278639321
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.911599239
Short name T2042
Test name
Test status
Simulation time 429072471 ps
CPU time 1.34 seconds
Started Jun 27 06:42:36 PM PDT 24
Finished Jun 27 06:43:06 PM PDT 24
Peak memory 206284 kb
Host smart-fcccfe4f-2fe7-4dd9-8f37-13a9272c84ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91159
9239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.911599239
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.206747277
Short name T1097
Test name
Test status
Simulation time 165150934 ps
CPU time 0.75 seconds
Started Jun 27 06:42:40 PM PDT 24
Finished Jun 27 06:43:08 PM PDT 24
Peak memory 206256 kb
Host smart-85a561a4-73d5-4218-8775-37e3016e2cbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20674
7277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.206747277
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.116721621
Short name T1115
Test name
Test status
Simulation time 57969908 ps
CPU time 0.65 seconds
Started Jun 27 06:42:40 PM PDT 24
Finished Jun 27 06:43:07 PM PDT 24
Peak memory 206292 kb
Host smart-f9cbc833-d192-4d9c-b0b4-17b099a56d79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11672
1621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.116721621
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.2286534240
Short name T1294
Test name
Test status
Simulation time 870962300 ps
CPU time 1.89 seconds
Started Jun 27 06:42:32 PM PDT 24
Finished Jun 27 06:43:03 PM PDT 24
Peak memory 206324 kb
Host smart-2c9226e1-7454-42a3-b2b4-132ed1efd80d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22865
34240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.2286534240
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.2934475623
Short name T1235
Test name
Test status
Simulation time 174275035 ps
CPU time 1.74 seconds
Started Jun 27 06:42:37 PM PDT 24
Finished Jun 27 06:43:06 PM PDT 24
Peak memory 206368 kb
Host smart-dfa1d8c8-2ebb-4e81-9eda-579e88898627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29344
75623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.2934475623
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.1969026931
Short name T391
Test name
Test status
Simulation time 245669110 ps
CPU time 0.91 seconds
Started Jun 27 06:42:36 PM PDT 24
Finished Jun 27 06:43:05 PM PDT 24
Peak memory 206280 kb
Host smart-f61967a6-ebda-413a-8bca-fc4defc9b90c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19690
26931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.1969026931
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.777515065
Short name T1671
Test name
Test status
Simulation time 146771179 ps
CPU time 0.77 seconds
Started Jun 27 06:42:39 PM PDT 24
Finished Jun 27 06:43:07 PM PDT 24
Peak memory 206268 kb
Host smart-7df12be6-f242-4e43-b74a-d1a4ff91fe10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77751
5065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.777515065
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.957124360
Short name T393
Test name
Test status
Simulation time 202375940 ps
CPU time 0.82 seconds
Started Jun 27 06:42:41 PM PDT 24
Finished Jun 27 06:43:08 PM PDT 24
Peak memory 206200 kb
Host smart-33810e96-e283-4748-8ea2-6ab06069abbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95712
4360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.957124360
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_invalid_sync.869128237
Short name T2586
Test name
Test status
Simulation time 6929386397 ps
CPU time 50.52 seconds
Started Jun 27 06:42:40 PM PDT 24
Finished Jun 27 06:43:57 PM PDT 24
Peak memory 206424 kb
Host smart-34c320b4-2314-4984-a990-7c0bdc3ebc80
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=869128237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.869128237
Directory /workspace/47.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.3564401528
Short name T2201
Test name
Test status
Simulation time 241131386 ps
CPU time 0.86 seconds
Started Jun 27 06:42:44 PM PDT 24
Finished Jun 27 06:43:09 PM PDT 24
Peak memory 206252 kb
Host smart-72fd3af4-ea05-411c-a81e-dbc773499424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35644
01528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.3564401528
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.2755839746
Short name T2571
Test name
Test status
Simulation time 23330726934 ps
CPU time 29.26 seconds
Started Jun 27 06:42:39 PM PDT 24
Finished Jun 27 06:43:36 PM PDT 24
Peak memory 206320 kb
Host smart-f3d7f90e-5237-431f-add7-9cd2975cd884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27558
39746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.2755839746
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.545094702
Short name T494
Test name
Test status
Simulation time 3297129941 ps
CPU time 3.82 seconds
Started Jun 27 06:42:38 PM PDT 24
Finished Jun 27 06:43:09 PM PDT 24
Peak memory 206344 kb
Host smart-683ead5d-0a5b-4b3a-90df-0dc853181b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54509
4702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.545094702
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.1246536797
Short name T1026
Test name
Test status
Simulation time 9597126665 ps
CPU time 87.73 seconds
Started Jun 27 06:42:39 PM PDT 24
Finished Jun 27 06:44:34 PM PDT 24
Peak memory 206508 kb
Host smart-6dcbd8a4-740a-44fb-8595-23a1d72a567a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12465
36797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.1246536797
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.1747285542
Short name T1148
Test name
Test status
Simulation time 4613092572 ps
CPU time 40.71 seconds
Started Jun 27 06:42:42 PM PDT 24
Finished Jun 27 06:43:48 PM PDT 24
Peak memory 206448 kb
Host smart-d3764420-70d8-4518-a450-8430ac29b6fc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1747285542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.1747285542
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.1614687938
Short name T216
Test name
Test status
Simulation time 245580753 ps
CPU time 0.89 seconds
Started Jun 27 06:42:41 PM PDT 24
Finished Jun 27 06:43:08 PM PDT 24
Peak memory 206300 kb
Host smart-5381a848-26de-4bfa-ba0a-07cc2f68f304
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1614687938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.1614687938
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.1117804717
Short name T997
Test name
Test status
Simulation time 220300890 ps
CPU time 0.84 seconds
Started Jun 27 06:42:38 PM PDT 24
Finished Jun 27 06:43:05 PM PDT 24
Peak memory 206292 kb
Host smart-402cab2b-b175-47e6-8f30-efc4953173f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11178
04717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.1117804717
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.2896020157
Short name T510
Test name
Test status
Simulation time 5624344775 ps
CPU time 153.13 seconds
Started Jun 27 06:42:40 PM PDT 24
Finished Jun 27 06:45:40 PM PDT 24
Peak memory 206436 kb
Host smart-8409720e-18ba-4e96-b7a1-e55937fc8417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28960
20157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.2896020157
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.2531131158
Short name T2068
Test name
Test status
Simulation time 5372746347 ps
CPU time 39.28 seconds
Started Jun 27 06:42:36 PM PDT 24
Finished Jun 27 06:43:44 PM PDT 24
Peak memory 206420 kb
Host smart-122be6bc-383d-4d76-923d-ba1311f6900c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2531131158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.2531131158
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.801821342
Short name T1209
Test name
Test status
Simulation time 146065891 ps
CPU time 0.78 seconds
Started Jun 27 06:42:33 PM PDT 24
Finished Jun 27 06:43:03 PM PDT 24
Peak memory 206296 kb
Host smart-658f2303-e554-467d-9139-a2045d334134
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=801821342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.801821342
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.2985039304
Short name T939
Test name
Test status
Simulation time 152544768 ps
CPU time 0.74 seconds
Started Jun 27 06:42:32 PM PDT 24
Finished Jun 27 06:43:02 PM PDT 24
Peak memory 206176 kb
Host smart-907035f4-b331-4364-bd5a-be8c1a529325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29850
39304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.2985039304
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.483069363
Short name T2349
Test name
Test status
Simulation time 204330926 ps
CPU time 0.94 seconds
Started Jun 27 06:42:36 PM PDT 24
Finished Jun 27 06:43:04 PM PDT 24
Peak memory 206256 kb
Host smart-462baaa6-2893-4c8f-9ce6-acb8577e54d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48306
9363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.483069363
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.1358383742
Short name T2243
Test name
Test status
Simulation time 188041593 ps
CPU time 0.87 seconds
Started Jun 27 06:42:42 PM PDT 24
Finished Jun 27 06:43:09 PM PDT 24
Peak memory 206296 kb
Host smart-e0958c5d-7f76-4d62-97bb-bbc206b39c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13583
83742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.1358383742
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.2417071935
Short name T1781
Test name
Test status
Simulation time 178646740 ps
CPU time 0.89 seconds
Started Jun 27 06:42:35 PM PDT 24
Finished Jun 27 06:43:04 PM PDT 24
Peak memory 206292 kb
Host smart-e4b170ab-497e-4aec-b5d4-2c0e6d4f2d83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24170
71935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.2417071935
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.3116935161
Short name T16
Test name
Test status
Simulation time 176533685 ps
CPU time 0.82 seconds
Started Jun 27 06:42:37 PM PDT 24
Finished Jun 27 06:43:05 PM PDT 24
Peak memory 206272 kb
Host smart-b99f3c7f-8cc1-4e45-9917-a89e2c5036ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31169
35161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.3116935161
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.3302719364
Short name T2056
Test name
Test status
Simulation time 159280896 ps
CPU time 0.77 seconds
Started Jun 27 06:42:40 PM PDT 24
Finished Jun 27 06:43:08 PM PDT 24
Peak memory 206252 kb
Host smart-f35b3d9e-a317-4450-ba63-23eefb19244c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33027
19364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.3302719364
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.2757590698
Short name T2579
Test name
Test status
Simulation time 241692071 ps
CPU time 0.98 seconds
Started Jun 27 06:42:38 PM PDT 24
Finished Jun 27 06:43:05 PM PDT 24
Peak memory 206304 kb
Host smart-6a25144b-5444-46ef-8466-8bdc7c5da718
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2757590698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.2757590698
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.1343402879
Short name T2462
Test name
Test status
Simulation time 176825127 ps
CPU time 0.77 seconds
Started Jun 27 06:42:42 PM PDT 24
Finished Jun 27 06:43:09 PM PDT 24
Peak memory 206284 kb
Host smart-3a4a8cb8-58ee-4385-ad07-64f35a7235fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13434
02879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.1343402879
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.390025818
Short name T2494
Test name
Test status
Simulation time 37829918 ps
CPU time 0.64 seconds
Started Jun 27 06:42:36 PM PDT 24
Finished Jun 27 06:43:05 PM PDT 24
Peak memory 206268 kb
Host smart-10c9ef3c-ece9-4cc3-9d83-da95807f8b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39002
5818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.390025818
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.2126064286
Short name T88
Test name
Test status
Simulation time 16378587658 ps
CPU time 35.07 seconds
Started Jun 27 06:42:40 PM PDT 24
Finished Jun 27 06:43:42 PM PDT 24
Peak memory 206416 kb
Host smart-f3f51221-65d1-48bb-9b76-679737f1a80a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21260
64286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.2126064286
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.357536562
Short name T461
Test name
Test status
Simulation time 180358349 ps
CPU time 0.87 seconds
Started Jun 27 06:42:38 PM PDT 24
Finished Jun 27 06:43:06 PM PDT 24
Peak memory 206288 kb
Host smart-4047e866-3124-46ed-ac35-68a0747b0a7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35753
6562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.357536562
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.2064332337
Short name T674
Test name
Test status
Simulation time 240047115 ps
CPU time 0.92 seconds
Started Jun 27 06:42:35 PM PDT 24
Finished Jun 27 06:43:04 PM PDT 24
Peak memory 206304 kb
Host smart-975d1ef9-c49f-4738-b90d-22e73da46d11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20643
32337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.2064332337
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.1875821370
Short name T1608
Test name
Test status
Simulation time 209857344 ps
CPU time 0.95 seconds
Started Jun 27 06:42:39 PM PDT 24
Finished Jun 27 06:43:07 PM PDT 24
Peak memory 206296 kb
Host smart-8a15818d-5a48-4d5c-b490-3f804f72daa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18758
21370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.1875821370
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.1677864708
Short name T485
Test name
Test status
Simulation time 246376470 ps
CPU time 0.88 seconds
Started Jun 27 06:42:39 PM PDT 24
Finished Jun 27 06:43:07 PM PDT 24
Peak memory 206224 kb
Host smart-61d097a4-461e-485d-8319-b2d09cd0a31d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16778
64708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.1677864708
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.797314369
Short name T1355
Test name
Test status
Simulation time 203241526 ps
CPU time 0.88 seconds
Started Jun 27 06:42:42 PM PDT 24
Finished Jun 27 06:43:09 PM PDT 24
Peak memory 206284 kb
Host smart-2e1a0bec-08e0-4a29-b791-56ba0a13d1ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79731
4369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.797314369
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.3684779245
Short name T2335
Test name
Test status
Simulation time 173831278 ps
CPU time 0.79 seconds
Started Jun 27 06:42:40 PM PDT 24
Finished Jun 27 06:43:08 PM PDT 24
Peak memory 206260 kb
Host smart-95127e6a-d188-4d82-8aa1-bb6279730d4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36847
79245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.3684779245
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.3047615983
Short name T985
Test name
Test status
Simulation time 164055809 ps
CPU time 0.82 seconds
Started Jun 27 06:42:43 PM PDT 24
Finished Jun 27 06:43:09 PM PDT 24
Peak memory 206200 kb
Host smart-9847e5f4-c4db-47fb-8d7e-73b122c4f1ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30476
15983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.3047615983
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.1880890996
Short name T33
Test name
Test status
Simulation time 195755919 ps
CPU time 0.91 seconds
Started Jun 27 06:42:38 PM PDT 24
Finished Jun 27 06:43:05 PM PDT 24
Peak memory 206304 kb
Host smart-64544c63-cdaa-41ec-8074-2a8b084b695d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18808
90996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.1880890996
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.482083020
Short name T1697
Test name
Test status
Simulation time 6838196012 ps
CPU time 47.29 seconds
Started Jun 27 06:42:41 PM PDT 24
Finished Jun 27 06:43:54 PM PDT 24
Peak memory 206400 kb
Host smart-b42f9d81-54d0-464f-9133-e48a3c78c45d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=482083020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.482083020
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.682472491
Short name T960
Test name
Test status
Simulation time 177882733 ps
CPU time 0.8 seconds
Started Jun 27 06:42:39 PM PDT 24
Finished Jun 27 06:43:07 PM PDT 24
Peak memory 206152 kb
Host smart-cce2fedd-7c61-45a0-b3ec-72a1d2885261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68247
2491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.682472491
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.3444228007
Short name T1049
Test name
Test status
Simulation time 191186350 ps
CPU time 0.85 seconds
Started Jun 27 06:42:40 PM PDT 24
Finished Jun 27 06:43:08 PM PDT 24
Peak memory 206252 kb
Host smart-1840be5b-4ab8-4a80-8ba3-3f30122e98e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34442
28007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.3444228007
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.2129648566
Short name T2149
Test name
Test status
Simulation time 5138556958 ps
CPU time 35.26 seconds
Started Jun 27 06:42:43 PM PDT 24
Finished Jun 27 06:43:43 PM PDT 24
Peak memory 206280 kb
Host smart-9dfc1542-00b1-49d7-adcb-1ff345369e91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21296
48566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.2129648566
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.2227842713
Short name T1357
Test name
Test status
Simulation time 50998462 ps
CPU time 0.72 seconds
Started Jun 27 06:43:04 PM PDT 24
Finished Jun 27 06:43:21 PM PDT 24
Peak memory 206068 kb
Host smart-cd79068e-c3d1-4989-974e-d43583090807
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2227842713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.2227842713
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.3217774110
Short name T10
Test name
Test status
Simulation time 3944298808 ps
CPU time 5.03 seconds
Started Jun 27 06:42:39 PM PDT 24
Finished Jun 27 06:43:12 PM PDT 24
Peak memory 206340 kb
Host smart-28649761-1282-4196-ab57-c3253789f8e1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3217774110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.3217774110
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.1252145517
Short name T2018
Test name
Test status
Simulation time 13364810925 ps
CPU time 12.55 seconds
Started Jun 27 06:42:51 PM PDT 24
Finished Jun 27 06:43:24 PM PDT 24
Peak memory 206432 kb
Host smart-dc8827dd-cee1-4331-b9f7-ef9e60d1e600
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1252145517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.1252145517
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.4123954093
Short name T845
Test name
Test status
Simulation time 23342004056 ps
CPU time 24.63 seconds
Started Jun 27 06:42:53 PM PDT 24
Finished Jun 27 06:43:38 PM PDT 24
Peak memory 206332 kb
Host smart-27ebfa33-34a4-4728-853e-39aea74244cd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4123954093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.4123954093
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.2330305185
Short name T2567
Test name
Test status
Simulation time 201718510 ps
CPU time 0.83 seconds
Started Jun 27 06:42:52 PM PDT 24
Finished Jun 27 06:43:13 PM PDT 24
Peak memory 206280 kb
Host smart-03d540ab-495b-49c5-ae37-4c1863fa52db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23303
05185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.2330305185
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.997712617
Short name T2519
Test name
Test status
Simulation time 236291058 ps
CPU time 0.9 seconds
Started Jun 27 06:42:52 PM PDT 24
Finished Jun 27 06:43:13 PM PDT 24
Peak memory 206260 kb
Host smart-61351f50-0644-4986-baa8-befa5da74583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99771
2617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.997712617
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.952273523
Short name T1
Test name
Test status
Simulation time 443879061 ps
CPU time 1.41 seconds
Started Jun 27 06:42:52 PM PDT 24
Finished Jun 27 06:43:13 PM PDT 24
Peak memory 206292 kb
Host smart-6f5d0d25-4562-454f-8064-d24a358e5f91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95227
3523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.952273523
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_device_address.529075401
Short name T1704
Test name
Test status
Simulation time 12162745885 ps
CPU time 22.77 seconds
Started Jun 27 06:42:55 PM PDT 24
Finished Jun 27 06:43:36 PM PDT 24
Peak memory 206480 kb
Host smart-6116fcff-6f9a-42fe-af8a-ab5c2fbcd696
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52907
5401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.529075401
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.346266534
Short name T1130
Test name
Test status
Simulation time 467356615 ps
CPU time 1.37 seconds
Started Jun 27 06:42:57 PM PDT 24
Finished Jun 27 06:43:17 PM PDT 24
Peak memory 206292 kb
Host smart-848e9421-7215-4642-9bf2-b3a721879766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34626
6534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.346266534
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.2376429394
Short name T690
Test name
Test status
Simulation time 138783980 ps
CPU time 0.74 seconds
Started Jun 27 06:42:51 PM PDT 24
Finished Jun 27 06:43:12 PM PDT 24
Peak memory 206280 kb
Host smart-5582a77a-9904-47c8-812f-ab39b0764d74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23764
29394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.2376429394
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.565166126
Short name T586
Test name
Test status
Simulation time 69826195 ps
CPU time 0.67 seconds
Started Jun 27 06:42:51 PM PDT 24
Finished Jun 27 06:43:12 PM PDT 24
Peak memory 206304 kb
Host smart-53685448-29c8-461e-a3fe-269f0313effa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56516
6126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.565166126
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.3186620590
Short name T916
Test name
Test status
Simulation time 748021534 ps
CPU time 1.87 seconds
Started Jun 27 06:42:55 PM PDT 24
Finished Jun 27 06:43:15 PM PDT 24
Peak memory 206436 kb
Host smart-773d9769-06f9-4080-b3df-abadf7a8efbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31866
20590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.3186620590
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.3518071292
Short name T1496
Test name
Test status
Simulation time 177110051 ps
CPU time 1.95 seconds
Started Jun 27 06:42:53 PM PDT 24
Finished Jun 27 06:43:15 PM PDT 24
Peak memory 206420 kb
Host smart-3b548575-d51a-43d0-b90f-2d952d499e9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35180
71292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.3518071292
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.609027677
Short name T109
Test name
Test status
Simulation time 223531024 ps
CPU time 0.89 seconds
Started Jun 27 06:42:51 PM PDT 24
Finished Jun 27 06:43:13 PM PDT 24
Peak memory 206292 kb
Host smart-96fd110d-93a1-47a0-b57e-db692495d3de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60902
7677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.609027677
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.3288341854
Short name T2175
Test name
Test status
Simulation time 140395750 ps
CPU time 0.78 seconds
Started Jun 27 06:42:56 PM PDT 24
Finished Jun 27 06:43:16 PM PDT 24
Peak memory 206276 kb
Host smart-69131c5f-4ce9-4fb2-8e12-0cd849d26402
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32883
41854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.3288341854
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.200554503
Short name T799
Test name
Test status
Simulation time 197456904 ps
CPU time 0.9 seconds
Started Jun 27 06:42:52 PM PDT 24
Finished Jun 27 06:43:13 PM PDT 24
Peak memory 206220 kb
Host smart-b90066cb-c90c-4afa-abd6-f0a57a1f4531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20055
4503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.200554503
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_invalid_sync.4155019014
Short name T1672
Test name
Test status
Simulation time 9578366437 ps
CPU time 65.09 seconds
Started Jun 27 06:42:55 PM PDT 24
Finished Jun 27 06:44:19 PM PDT 24
Peak memory 206420 kb
Host smart-c0b5ace0-6e96-4e14-990c-9dd6e7e08353
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4155019014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.4155019014
Directory /workspace/48.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.3949100253
Short name T1655
Test name
Test status
Simulation time 232553617 ps
CPU time 0.94 seconds
Started Jun 27 06:42:50 PM PDT 24
Finished Jun 27 06:43:12 PM PDT 24
Peak memory 206272 kb
Host smart-e8695f4a-b6c6-4997-ba74-610f6f6f3f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39491
00253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.3949100253
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.2939614134
Short name T1354
Test name
Test status
Simulation time 23292769370 ps
CPU time 24.23 seconds
Started Jun 27 06:42:58 PM PDT 24
Finished Jun 27 06:43:41 PM PDT 24
Peak memory 206308 kb
Host smart-3d314416-428a-4169-8e3a-d49ffb51151c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29396
14134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.2939614134
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.1703948354
Short name T2379
Test name
Test status
Simulation time 3268448987 ps
CPU time 4.28 seconds
Started Jun 27 06:42:52 PM PDT 24
Finished Jun 27 06:43:16 PM PDT 24
Peak memory 206328 kb
Host smart-eeb06b59-e7e8-4c26-b4be-0921db6ba373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17039
48354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.1703948354
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.2144180456
Short name T1296
Test name
Test status
Simulation time 8250831538 ps
CPU time 56.89 seconds
Started Jun 27 06:42:57 PM PDT 24
Finished Jun 27 06:44:14 PM PDT 24
Peak memory 206456 kb
Host smart-208622ad-f321-48ba-a94e-23bfae62d2f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21441
80456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.2144180456
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.3760847743
Short name T1392
Test name
Test status
Simulation time 3007699173 ps
CPU time 27.9 seconds
Started Jun 27 06:42:55 PM PDT 24
Finished Jun 27 06:43:41 PM PDT 24
Peak memory 206612 kb
Host smart-ebb69e11-4dd9-4107-9078-443ab175aa77
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3760847743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.3760847743
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.3951995649
Short name T1210
Test name
Test status
Simulation time 260196656 ps
CPU time 0.87 seconds
Started Jun 27 06:42:57 PM PDT 24
Finished Jun 27 06:43:17 PM PDT 24
Peak memory 206264 kb
Host smart-32b97d0c-03b5-4fd8-be5a-f68cfd08169b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3951995649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.3951995649
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.3336498982
Short name T2117
Test name
Test status
Simulation time 184926952 ps
CPU time 0.81 seconds
Started Jun 27 06:42:58 PM PDT 24
Finished Jun 27 06:43:18 PM PDT 24
Peak memory 206308 kb
Host smart-44f08220-20e3-434a-8caa-b1cf389445fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33364
98982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.3336498982
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.1900383822
Short name T2525
Test name
Test status
Simulation time 4702450754 ps
CPU time 126.99 seconds
Started Jun 27 06:42:55 PM PDT 24
Finished Jun 27 06:45:22 PM PDT 24
Peak memory 206444 kb
Host smart-6b085fff-3886-4865-954b-4cf60a4964a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19003
83822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.1900383822
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.2995288565
Short name T2220
Test name
Test status
Simulation time 6005228480 ps
CPU time 164.13 seconds
Started Jun 27 06:42:55 PM PDT 24
Finished Jun 27 06:45:58 PM PDT 24
Peak memory 206432 kb
Host smart-1b9a0593-c48e-4953-99e5-dd72c38975fd
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2995288565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.2995288565
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.310606543
Short name T1739
Test name
Test status
Simulation time 154701650 ps
CPU time 0.83 seconds
Started Jun 27 06:42:55 PM PDT 24
Finished Jun 27 06:43:16 PM PDT 24
Peak memory 206288 kb
Host smart-155c61cf-6805-451c-9380-1903b3ceac1f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=310606543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.310606543
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.1304323252
Short name T325
Test name
Test status
Simulation time 169597805 ps
CPU time 0.79 seconds
Started Jun 27 06:42:55 PM PDT 24
Finished Jun 27 06:43:14 PM PDT 24
Peak memory 206284 kb
Host smart-0c8835f5-77ac-48cb-9629-e698350df3c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13043
23252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.1304323252
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.1237713473
Short name T124
Test name
Test status
Simulation time 154703803 ps
CPU time 0.79 seconds
Started Jun 27 06:42:55 PM PDT 24
Finished Jun 27 06:43:15 PM PDT 24
Peak memory 206284 kb
Host smart-ce158eda-f101-4206-a05e-9131e8f7c245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12377
13473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.1237713473
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.3819855290
Short name T1466
Test name
Test status
Simulation time 159545028 ps
CPU time 0.8 seconds
Started Jun 27 06:43:03 PM PDT 24
Finished Jun 27 06:43:21 PM PDT 24
Peak memory 206304 kb
Host smart-08ce9a57-7434-44d3-87b8-353ea95dd7bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38198
55290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.3819855290
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.2442883998
Short name T1199
Test name
Test status
Simulation time 178756961 ps
CPU time 0.81 seconds
Started Jun 27 06:43:03 PM PDT 24
Finished Jun 27 06:43:21 PM PDT 24
Peak memory 206292 kb
Host smart-b0c79244-d5a5-4386-906e-87ec89086c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24428
83998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.2442883998
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.3043407665
Short name T1374
Test name
Test status
Simulation time 225578015 ps
CPU time 0.84 seconds
Started Jun 27 06:42:57 PM PDT 24
Finished Jun 27 06:43:17 PM PDT 24
Peak memory 206284 kb
Host smart-495a362b-7092-49a9-8392-0b15a3d618be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30434
07665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.3043407665
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.2914557127
Short name T157
Test name
Test status
Simulation time 158116262 ps
CPU time 0.75 seconds
Started Jun 27 06:42:59 PM PDT 24
Finished Jun 27 06:43:18 PM PDT 24
Peak memory 206260 kb
Host smart-8acf9494-33da-447e-bbc2-641dca518be7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29145
57127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.2914557127
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.1239562412
Short name T1447
Test name
Test status
Simulation time 187082359 ps
CPU time 0.91 seconds
Started Jun 27 06:43:04 PM PDT 24
Finished Jun 27 06:43:21 PM PDT 24
Peak memory 206308 kb
Host smart-209d76fd-9ab9-45f9-b3f0-4356903e37ff
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1239562412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.1239562412
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.152790928
Short name T194
Test name
Test status
Simulation time 177878623 ps
CPU time 0.78 seconds
Started Jun 27 06:42:56 PM PDT 24
Finished Jun 27 06:43:16 PM PDT 24
Peak memory 206280 kb
Host smart-e8800769-0736-4d23-94f7-e32ad216e288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15279
0928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.152790928
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.1435779102
Short name T2054
Test name
Test status
Simulation time 42094671 ps
CPU time 0.67 seconds
Started Jun 27 06:42:57 PM PDT 24
Finished Jun 27 06:43:17 PM PDT 24
Peak memory 206264 kb
Host smart-82526ded-79c2-45cd-a996-10fa17c95fb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14357
79102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.1435779102
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.831444429
Short name T1452
Test name
Test status
Simulation time 13159843320 ps
CPU time 28.4 seconds
Started Jun 27 06:43:00 PM PDT 24
Finished Jun 27 06:43:46 PM PDT 24
Peak memory 206496 kb
Host smart-a1bcbae3-2e1e-476c-9a4a-3d14ac224895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83144
4429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.831444429
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.4118707497
Short name T810
Test name
Test status
Simulation time 218975956 ps
CPU time 0.88 seconds
Started Jun 27 06:42:57 PM PDT 24
Finished Jun 27 06:43:17 PM PDT 24
Peak memory 206276 kb
Host smart-79e963fc-dfff-40e0-b588-ec94c9f042aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41187
07497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.4118707497
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.2485216237
Short name T2096
Test name
Test status
Simulation time 197791905 ps
CPU time 0.83 seconds
Started Jun 27 06:42:57 PM PDT 24
Finished Jun 27 06:43:17 PM PDT 24
Peak memory 206284 kb
Host smart-86fe8bfb-60a8-4235-8dbb-9bf60df2bb78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24852
16237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.2485216237
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.2141622793
Short name T655
Test name
Test status
Simulation time 261450561 ps
CPU time 0.89 seconds
Started Jun 27 06:42:56 PM PDT 24
Finished Jun 27 06:43:16 PM PDT 24
Peak memory 206296 kb
Host smart-3b3f1b1f-3d52-4666-bf58-1e5cc27a9b83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21416
22793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.2141622793
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.585319643
Short name T2459
Test name
Test status
Simulation time 183369284 ps
CPU time 0.77 seconds
Started Jun 27 06:42:57 PM PDT 24
Finished Jun 27 06:43:17 PM PDT 24
Peak memory 206272 kb
Host smart-ce8ff9ed-050a-4e7c-8f58-c1eed94576fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58531
9643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.585319643
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.1115752263
Short name T2167
Test name
Test status
Simulation time 150470519 ps
CPU time 0.8 seconds
Started Jun 27 06:42:54 PM PDT 24
Finished Jun 27 06:43:14 PM PDT 24
Peak memory 206272 kb
Host smart-41546303-6d49-402b-896e-e923e3f848aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11157
52263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.1115752263
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.3816912892
Short name T1278
Test name
Test status
Simulation time 174242531 ps
CPU time 0.81 seconds
Started Jun 27 06:42:56 PM PDT 24
Finished Jun 27 06:43:16 PM PDT 24
Peak memory 206268 kb
Host smart-7d2a94ef-25b9-45bf-b418-0a7ae4873a8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38169
12892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.3816912892
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.2784312394
Short name T1218
Test name
Test status
Simulation time 169398930 ps
CPU time 0.79 seconds
Started Jun 27 06:42:57 PM PDT 24
Finished Jun 27 06:43:17 PM PDT 24
Peak memory 206296 kb
Host smart-1e768658-e069-493b-8390-b40e9cadf31e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27843
12394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.2784312394
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.3301587516
Short name T2301
Test name
Test status
Simulation time 263250525 ps
CPU time 0.95 seconds
Started Jun 27 06:42:59 PM PDT 24
Finished Jun 27 06:43:19 PM PDT 24
Peak memory 206268 kb
Host smart-8ea6abd2-60a0-4102-8c1d-a83c5df5b4dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33015
87516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.3301587516
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.3353412468
Short name T838
Test name
Test status
Simulation time 5049917276 ps
CPU time 138.25 seconds
Started Jun 27 06:42:54 PM PDT 24
Finished Jun 27 06:45:32 PM PDT 24
Peak memory 206440 kb
Host smart-f411c484-1825-4181-bbd8-fc578ed8a444
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3353412468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.3353412468
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.4128275185
Short name T504
Test name
Test status
Simulation time 165253051 ps
CPU time 0.81 seconds
Started Jun 27 06:42:59 PM PDT 24
Finished Jun 27 06:43:19 PM PDT 24
Peak memory 206256 kb
Host smart-0f8802d4-d5e2-4d9d-a11e-50eefe06538d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41282
75185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.4128275185
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.567350806
Short name T2179
Test name
Test status
Simulation time 175898555 ps
CPU time 0.83 seconds
Started Jun 27 06:42:59 PM PDT 24
Finished Jun 27 06:43:19 PM PDT 24
Peak memory 206252 kb
Host smart-d4e9bc31-30e1-49da-ac6a-0383867c7dbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56735
0806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.567350806
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.492438753
Short name T143
Test name
Test status
Simulation time 4105177937 ps
CPU time 37.96 seconds
Started Jun 27 06:43:00 PM PDT 24
Finished Jun 27 06:43:56 PM PDT 24
Peak memory 206392 kb
Host smart-5252225a-1b2d-4ed7-a939-d71dcb416348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49243
8753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.492438753
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.3578339128
Short name T1518
Test name
Test status
Simulation time 70049080 ps
CPU time 0.69 seconds
Started Jun 27 06:43:11 PM PDT 24
Finished Jun 27 06:43:23 PM PDT 24
Peak memory 206364 kb
Host smart-2f6f2213-c5a0-4009-8c72-13134c0b665d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3578339128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.3578339128
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.974165242
Short name T2276
Test name
Test status
Simulation time 13380706039 ps
CPU time 11.89 seconds
Started Jun 27 06:43:04 PM PDT 24
Finished Jun 27 06:43:32 PM PDT 24
Peak memory 206340 kb
Host smart-30ab9afe-a90b-43eb-8ff7-c9e4f7d1c30c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=974165242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.974165242
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.1393378853
Short name T1250
Test name
Test status
Simulation time 23292736022 ps
CPU time 24.15 seconds
Started Jun 27 06:42:54 PM PDT 24
Finished Jun 27 06:43:38 PM PDT 24
Peak memory 206344 kb
Host smart-6d2c46e6-f8bc-4b40-8441-d3c1415bbba8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1393378853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.1393378853
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.4212177209
Short name T2205
Test name
Test status
Simulation time 172517534 ps
CPU time 0.79 seconds
Started Jun 27 06:42:54 PM PDT 24
Finished Jun 27 06:43:14 PM PDT 24
Peak memory 206280 kb
Host smart-ca19b371-9dab-4b7f-997b-2d223be1595d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42121
77209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.4212177209
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.311160688
Short name T980
Test name
Test status
Simulation time 146704495 ps
CPU time 0.77 seconds
Started Jun 27 06:42:54 PM PDT 24
Finished Jun 27 06:43:14 PM PDT 24
Peak memory 206288 kb
Host smart-11671003-1a00-40a9-a265-2b151db1f242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31116
0688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.311160688
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.4140290471
Short name T2352
Test name
Test status
Simulation time 388690482 ps
CPU time 1.25 seconds
Started Jun 27 06:43:04 PM PDT 24
Finished Jun 27 06:43:21 PM PDT 24
Peak memory 206272 kb
Host smart-37339c16-0ef4-4f47-a963-9b50afaf037e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41402
90471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.4140290471
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.3981259858
Short name T153
Test name
Test status
Simulation time 1270583400 ps
CPU time 2.87 seconds
Started Jun 27 06:43:04 PM PDT 24
Finished Jun 27 06:43:23 PM PDT 24
Peak memory 206104 kb
Host smart-6c22d377-827f-4466-bc2a-d2bd4045e6fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39812
59858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.3981259858
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.536593621
Short name T2058
Test name
Test status
Simulation time 9782140385 ps
CPU time 17.77 seconds
Started Jun 27 06:42:56 PM PDT 24
Finished Jun 27 06:43:33 PM PDT 24
Peak memory 206420 kb
Host smart-2732cd3e-12fa-4085-96cd-750e4163458c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53659
3621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.536593621
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.125110000
Short name T664
Test name
Test status
Simulation time 425160795 ps
CPU time 1.28 seconds
Started Jun 27 06:42:57 PM PDT 24
Finished Jun 27 06:43:17 PM PDT 24
Peak memory 206264 kb
Host smart-f4d87aae-7d3f-44b6-807b-5dc101e94b72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12511
0000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.125110000
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.850199947
Short name T551
Test name
Test status
Simulation time 207793426 ps
CPU time 0.84 seconds
Started Jun 27 06:42:53 PM PDT 24
Finished Jun 27 06:43:13 PM PDT 24
Peak memory 206272 kb
Host smart-ad5d5e2b-8071-45ad-ba22-35ffbab7dbe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85019
9947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.850199947
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.1780898581
Short name T858
Test name
Test status
Simulation time 38008491 ps
CPU time 0.69 seconds
Started Jun 27 06:42:53 PM PDT 24
Finished Jun 27 06:43:13 PM PDT 24
Peak memory 206260 kb
Host smart-12f928ec-b3de-4ab7-8fe7-e046a87e6d91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17808
98581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.1780898581
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.4283686976
Short name T1196
Test name
Test status
Simulation time 1074672029 ps
CPU time 2.25 seconds
Started Jun 27 06:42:53 PM PDT 24
Finished Jun 27 06:43:14 PM PDT 24
Peak memory 206444 kb
Host smart-ad28783e-091c-4387-b494-108736106e15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42836
86976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.4283686976
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.4272401151
Short name T1664
Test name
Test status
Simulation time 220569264 ps
CPU time 1.25 seconds
Started Jun 27 06:42:56 PM PDT 24
Finished Jun 27 06:43:16 PM PDT 24
Peak memory 206376 kb
Host smart-1ddb97c9-e77c-4b89-8f98-964846120356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42724
01151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.4272401151
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.2261640858
Short name T1925
Test name
Test status
Simulation time 190627469 ps
CPU time 0.81 seconds
Started Jun 27 06:42:55 PM PDT 24
Finished Jun 27 06:43:14 PM PDT 24
Peak memory 206284 kb
Host smart-b02fcce1-8ddb-4e24-a81a-0167b850d9cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22616
40858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.2261640858
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.1083597694
Short name T1944
Test name
Test status
Simulation time 135180257 ps
CPU time 0.77 seconds
Started Jun 27 06:42:56 PM PDT 24
Finished Jun 27 06:43:16 PM PDT 24
Peak memory 206264 kb
Host smart-02c73d48-d5f4-45b9-ae07-6afc31807540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10835
97694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.1083597694
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.2684139416
Short name T2190
Test name
Test status
Simulation time 190550890 ps
CPU time 0.88 seconds
Started Jun 27 06:42:52 PM PDT 24
Finished Jun 27 06:43:13 PM PDT 24
Peak memory 206288 kb
Host smart-e7821032-ef39-49ee-a789-6af3060a661d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26841
39416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.2684139416
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_invalid_sync.3066812340
Short name T1263
Test name
Test status
Simulation time 7081288544 ps
CPU time 186.38 seconds
Started Jun 27 06:42:55 PM PDT 24
Finished Jun 27 06:46:20 PM PDT 24
Peak memory 206444 kb
Host smart-8b5233ea-2c93-4cf2-8226-920fe32d2211
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3066812340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.3066812340
Directory /workspace/49.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.3572466133
Short name T2336
Test name
Test status
Simulation time 224695554 ps
CPU time 0.88 seconds
Started Jun 27 06:42:52 PM PDT 24
Finished Jun 27 06:43:13 PM PDT 24
Peak memory 206268 kb
Host smart-7691f4d0-99d2-41a0-91cb-9f298b58b017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35724
66133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.3572466133
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.3939878860
Short name T1062
Test name
Test status
Simulation time 23346185462 ps
CPU time 23.81 seconds
Started Jun 27 06:42:56 PM PDT 24
Finished Jun 27 06:43:39 PM PDT 24
Peak memory 206336 kb
Host smart-a98ddbc0-723e-4b03-92b2-6641bf4ad372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39398
78860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.3939878860
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.2686006209
Short name T1717
Test name
Test status
Simulation time 3352340927 ps
CPU time 3.81 seconds
Started Jun 27 06:42:56 PM PDT 24
Finished Jun 27 06:43:19 PM PDT 24
Peak memory 206328 kb
Host smart-ff548c42-be04-4a09-8c2d-7b60ea5ac2a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26860
06209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.2686006209
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.1588779124
Short name T599
Test name
Test status
Simulation time 6746795630 ps
CPU time 63.41 seconds
Started Jun 27 06:42:54 PM PDT 24
Finished Jun 27 06:44:17 PM PDT 24
Peak memory 206648 kb
Host smart-1d52f5b4-0934-49a2-a57d-406b56b00f42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15887
79124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.1588779124
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.4283107696
Short name T2384
Test name
Test status
Simulation time 7585070968 ps
CPU time 204.19 seconds
Started Jun 27 06:42:57 PM PDT 24
Finished Jun 27 06:46:41 PM PDT 24
Peak memory 206408 kb
Host smart-f2bdd654-482b-4f54-be60-55dcca8f330c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4283107696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.4283107696
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.4054681392
Short name T382
Test name
Test status
Simulation time 241432515 ps
CPU time 0.88 seconds
Started Jun 27 06:42:58 PM PDT 24
Finished Jun 27 06:43:18 PM PDT 24
Peak memory 206284 kb
Host smart-f359839b-7de2-4e50-8927-43991557b228
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4054681392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.4054681392
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.2751443076
Short name T886
Test name
Test status
Simulation time 194513584 ps
CPU time 0.92 seconds
Started Jun 27 06:42:53 PM PDT 24
Finished Jun 27 06:43:13 PM PDT 24
Peak memory 206260 kb
Host smart-94593382-c160-4c80-bebf-1b61cc5837ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27514
43076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.2751443076
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.1355425717
Short name T420
Test name
Test status
Simulation time 6035077461 ps
CPU time 56.27 seconds
Started Jun 27 06:42:59 PM PDT 24
Finished Jun 27 06:44:14 PM PDT 24
Peak memory 206504 kb
Host smart-f0990318-c731-4098-a1a4-c2d8b85df22e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13554
25717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.1355425717
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.3126197165
Short name T2110
Test name
Test status
Simulation time 7093968336 ps
CPU time 63.61 seconds
Started Jun 27 06:42:59 PM PDT 24
Finished Jun 27 06:44:21 PM PDT 24
Peak memory 206508 kb
Host smart-eb1f5c4b-0acb-453d-9d68-be0344cc9f42
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3126197165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.3126197165
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.1595386047
Short name T2238
Test name
Test status
Simulation time 178083263 ps
CPU time 0.84 seconds
Started Jun 27 06:42:57 PM PDT 24
Finished Jun 27 06:43:17 PM PDT 24
Peak memory 206300 kb
Host smart-c9265c9e-80a4-48ed-98e0-1476504fbe10
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1595386047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.1595386047
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.1962907667
Short name T2256
Test name
Test status
Simulation time 188397626 ps
CPU time 0.79 seconds
Started Jun 27 06:42:59 PM PDT 24
Finished Jun 27 06:43:18 PM PDT 24
Peak memory 206308 kb
Host smart-306305d5-8dc1-4e06-8dd1-0ada394723e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19629
07667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.1962907667
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.2430968147
Short name T117
Test name
Test status
Simulation time 176082832 ps
CPU time 0.86 seconds
Started Jun 27 06:42:56 PM PDT 24
Finished Jun 27 06:43:16 PM PDT 24
Peak memory 206208 kb
Host smart-b02183c8-e9e6-4d0e-82a2-01c25673f1b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24309
68147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.2430968147
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.1081620381
Short name T338
Test name
Test status
Simulation time 240179960 ps
CPU time 0.92 seconds
Started Jun 27 06:42:53 PM PDT 24
Finished Jun 27 06:43:13 PM PDT 24
Peak memory 206316 kb
Host smart-92d6a60e-a3d0-4614-ba74-b1639b63913f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10816
20381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.1081620381
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.1775876208
Short name T1694
Test name
Test status
Simulation time 188214146 ps
CPU time 0.79 seconds
Started Jun 27 06:42:59 PM PDT 24
Finished Jun 27 06:43:18 PM PDT 24
Peak memory 206260 kb
Host smart-57fe4a95-f00f-44c8-a766-531fb03b02b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17758
76208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.1775876208
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.2455440479
Short name T1958
Test name
Test status
Simulation time 153923463 ps
CPU time 0.76 seconds
Started Jun 27 06:43:04 PM PDT 24
Finished Jun 27 06:43:21 PM PDT 24
Peak memory 206292 kb
Host smart-35796413-3b07-4a2e-8c67-694a23b80739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24554
40479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.2455440479
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.2388350512
Short name T831
Test name
Test status
Simulation time 155638238 ps
CPU time 0.79 seconds
Started Jun 27 06:43:00 PM PDT 24
Finished Jun 27 06:43:19 PM PDT 24
Peak memory 206244 kb
Host smart-47e946e4-e496-4b6a-a272-8703cf725ec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23883
50512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.2388350512
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.826737491
Short name T1414
Test name
Test status
Simulation time 243814097 ps
CPU time 0.95 seconds
Started Jun 27 06:42:59 PM PDT 24
Finished Jun 27 06:43:19 PM PDT 24
Peak memory 206280 kb
Host smart-03fd3a04-0c43-4256-9b68-41df16be7113
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=826737491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.826737491
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.2356425633
Short name T1154
Test name
Test status
Simulation time 150644620 ps
CPU time 0.76 seconds
Started Jun 27 06:43:03 PM PDT 24
Finished Jun 27 06:43:21 PM PDT 24
Peak memory 206292 kb
Host smart-c5d212af-6a2f-4f0e-a194-989c5a260324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23564
25633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.2356425633
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.3948170459
Short name T2146
Test name
Test status
Simulation time 115633587 ps
CPU time 0.8 seconds
Started Jun 27 06:43:03 PM PDT 24
Finished Jun 27 06:43:21 PM PDT 24
Peak memory 206284 kb
Host smart-119e572a-5f07-4bd3-85f1-4850f2fd4fbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39481
70459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.3948170459
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.1837423841
Short name T1994
Test name
Test status
Simulation time 19205602351 ps
CPU time 39.84 seconds
Started Jun 27 06:43:00 PM PDT 24
Finished Jun 27 06:43:58 PM PDT 24
Peak memory 206480 kb
Host smart-342d7b6a-1ca8-4155-bc55-389a4c351558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18374
23841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.1837423841
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.3890201358
Short name T1604
Test name
Test status
Simulation time 166031534 ps
CPU time 0.87 seconds
Started Jun 27 06:42:51 PM PDT 24
Finished Jun 27 06:43:12 PM PDT 24
Peak memory 206268 kb
Host smart-83e3c219-d26f-4acf-a681-1ba3393a9402
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38902
01358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.3890201358
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.1666482501
Short name T1564
Test name
Test status
Simulation time 205800999 ps
CPU time 0.87 seconds
Started Jun 27 06:42:52 PM PDT 24
Finished Jun 27 06:43:13 PM PDT 24
Peak memory 206296 kb
Host smart-9ef2ae00-6dd2-42e2-82a5-4a9f199b6bfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16664
82501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.1666482501
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.467892945
Short name T2566
Test name
Test status
Simulation time 227185756 ps
CPU time 0.88 seconds
Started Jun 27 06:42:56 PM PDT 24
Finished Jun 27 06:43:16 PM PDT 24
Peak memory 206288 kb
Host smart-e10f727a-2a5b-40d6-827d-8dc354a753a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46789
2945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.467892945
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.2737340219
Short name T1169
Test name
Test status
Simulation time 161320902 ps
CPU time 0.87 seconds
Started Jun 27 06:42:53 PM PDT 24
Finished Jun 27 06:43:14 PM PDT 24
Peak memory 206208 kb
Host smart-fa0c0634-fcfa-4008-8570-945bf5de19c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27373
40219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.2737340219
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.835755035
Short name T2174
Test name
Test status
Simulation time 142630793 ps
CPU time 0.78 seconds
Started Jun 27 06:43:11 PM PDT 24
Finished Jun 27 06:43:24 PM PDT 24
Peak memory 206284 kb
Host smart-ff5d5e9c-96bc-4ad1-8458-e68234dce4c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83575
5035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.835755035
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.1147139158
Short name T1976
Test name
Test status
Simulation time 158804323 ps
CPU time 0.8 seconds
Started Jun 27 06:43:16 PM PDT 24
Finished Jun 27 06:43:26 PM PDT 24
Peak memory 206256 kb
Host smart-7ac78a87-46c9-4d16-aaac-bfc03afc970a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11471
39158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.1147139158
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.167326035
Short name T1358
Test name
Test status
Simulation time 207623242 ps
CPU time 0.86 seconds
Started Jun 27 06:43:12 PM PDT 24
Finished Jun 27 06:43:25 PM PDT 24
Peak memory 206288 kb
Host smart-63b62136-4328-4e8d-9e0b-39429f473701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16732
6035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.167326035
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.2492082786
Short name T329
Test name
Test status
Simulation time 233729196 ps
CPU time 0.93 seconds
Started Jun 27 06:43:14 PM PDT 24
Finished Jun 27 06:43:26 PM PDT 24
Peak memory 206440 kb
Host smart-af930a7a-ff09-42ee-b730-6484ca8c92ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24920
82786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.2492082786
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.350322600
Short name T479
Test name
Test status
Simulation time 4889369777 ps
CPU time 43.74 seconds
Started Jun 27 06:43:19 PM PDT 24
Finished Jun 27 06:44:12 PM PDT 24
Peak memory 206416 kb
Host smart-7ccb2bd6-2454-4817-a247-ba0b4e65af1e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=350322600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.350322600
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.290908489
Short name T521
Test name
Test status
Simulation time 188695323 ps
CPU time 0.82 seconds
Started Jun 27 06:43:12 PM PDT 24
Finished Jun 27 06:43:25 PM PDT 24
Peak memory 206248 kb
Host smart-49edb08f-3d05-4c1a-83c4-2a734ab03551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29090
8489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.290908489
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.3236055681
Short name T101
Test name
Test status
Simulation time 164371663 ps
CPU time 0.79 seconds
Started Jun 27 06:43:14 PM PDT 24
Finished Jun 27 06:43:26 PM PDT 24
Peak memory 206276 kb
Host smart-b5eae8ef-b129-4100-b563-88dd4f0ac4c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32360
55681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.3236055681
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.3889468574
Short name T2242
Test name
Test status
Simulation time 6215901864 ps
CPU time 43.28 seconds
Started Jun 27 06:43:13 PM PDT 24
Finished Jun 27 06:44:08 PM PDT 24
Peak memory 206428 kb
Host smart-9ceeb040-0996-439d-bdc5-eb680a9589d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38894
68574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.3889468574
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.2864132969
Short name T21
Test name
Test status
Simulation time 60628984 ps
CPU time 0.7 seconds
Started Jun 27 06:35:30 PM PDT 24
Finished Jun 27 06:35:35 PM PDT 24
Peak memory 206352 kb
Host smart-3442e61a-3c3b-43a6-9c57-ece794f26356
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2864132969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.2864132969
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.655089664
Short name T2610
Test name
Test status
Simulation time 4396304054 ps
CPU time 4.89 seconds
Started Jun 27 06:35:12 PM PDT 24
Finished Jun 27 06:35:22 PM PDT 24
Peak memory 206456 kb
Host smart-9b0c2308-0df5-49ea-979f-ca6348bb51c6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=655089664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.655089664
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.1288101649
Short name T1907
Test name
Test status
Simulation time 13545843919 ps
CPU time 13.98 seconds
Started Jun 27 06:35:09 PM PDT 24
Finished Jun 27 06:35:29 PM PDT 24
Peak memory 206420 kb
Host smart-4e60e012-a645-4d73-a620-a4d01179b184
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1288101649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.1288101649
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.3790219044
Short name T505
Test name
Test status
Simulation time 23368702285 ps
CPU time 23.13 seconds
Started Jun 27 06:35:10 PM PDT 24
Finished Jun 27 06:35:39 PM PDT 24
Peak memory 206476 kb
Host smart-4015ba3c-9b24-4d8f-a3ca-292701b520bb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3790219044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.3790219044
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.365831733
Short name T2279
Test name
Test status
Simulation time 152908591 ps
CPU time 0.76 seconds
Started Jun 27 06:35:11 PM PDT 24
Finished Jun 27 06:35:17 PM PDT 24
Peak memory 206264 kb
Host smart-eb7ba0aa-652a-4cda-a234-ab58119aa179
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36583
1733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.365831733
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.3843595767
Short name T2328
Test name
Test status
Simulation time 180629050 ps
CPU time 0.79 seconds
Started Jun 27 06:35:13 PM PDT 24
Finished Jun 27 06:35:19 PM PDT 24
Peak memory 206248 kb
Host smart-4e439269-76e0-448d-a1d0-686bbf519e2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38435
95767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.3843595767
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.762358954
Short name T106
Test name
Test status
Simulation time 437609143 ps
CPU time 1.31 seconds
Started Jun 27 06:35:12 PM PDT 24
Finished Jun 27 06:35:19 PM PDT 24
Peak memory 206276 kb
Host smart-475cec7c-6852-4fc8-9c46-6bdc133eac4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76235
8954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.762358954
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.3395241430
Short name T837
Test name
Test status
Simulation time 1020861917 ps
CPU time 2.68 seconds
Started Jun 27 06:35:12 PM PDT 24
Finished Jun 27 06:35:20 PM PDT 24
Peak memory 206348 kb
Host smart-6870f84c-f683-48b3-be54-945aa02621df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33952
41430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.3395241430
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.3669785846
Short name T953
Test name
Test status
Simulation time 7392143149 ps
CPU time 13.08 seconds
Started Jun 27 06:35:15 PM PDT 24
Finished Jun 27 06:35:33 PM PDT 24
Peak memory 206392 kb
Host smart-82375089-3008-41f9-bbe2-e3d4ab7ad65f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36697
85846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.3669785846
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.536669589
Short name T467
Test name
Test status
Simulation time 331963846 ps
CPU time 1.31 seconds
Started Jun 27 06:35:15 PM PDT 24
Finished Jun 27 06:35:22 PM PDT 24
Peak memory 206296 kb
Host smart-398683ce-f027-4186-a8e1-60925c458b98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53666
9589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.536669589
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.1745725132
Short name T1780
Test name
Test status
Simulation time 149352215 ps
CPU time 0.76 seconds
Started Jun 27 06:35:12 PM PDT 24
Finished Jun 27 06:35:19 PM PDT 24
Peak memory 206256 kb
Host smart-6c28d359-bb3a-4b8b-88f0-644879137bd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17457
25132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.1745725132
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.2789250978
Short name T246
Test name
Test status
Simulation time 54637976 ps
CPU time 0.68 seconds
Started Jun 27 06:35:11 PM PDT 24
Finished Jun 27 06:35:16 PM PDT 24
Peak memory 206272 kb
Host smart-67d2508d-5a97-413b-8c9d-03d04552ba94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27892
50978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.2789250978
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.791748421
Short name T571
Test name
Test status
Simulation time 865468465 ps
CPU time 1.97 seconds
Started Jun 27 06:35:09 PM PDT 24
Finished Jun 27 06:35:17 PM PDT 24
Peak memory 206356 kb
Host smart-a78f35b3-8f6e-423d-960a-a03a407c20e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79174
8421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.791748421
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.2910155300
Short name T1238
Test name
Test status
Simulation time 167956522 ps
CPU time 1.65 seconds
Started Jun 27 06:35:09 PM PDT 24
Finished Jun 27 06:35:16 PM PDT 24
Peak memory 206376 kb
Host smart-814baa87-ee94-42d1-91ae-2db601a37ddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29101
55300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.2910155300
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.4231798720
Short name T1756
Test name
Test status
Simulation time 214873525 ps
CPU time 0.89 seconds
Started Jun 27 06:35:12 PM PDT 24
Finished Jun 27 06:35:19 PM PDT 24
Peak memory 206300 kb
Host smart-72c8f46b-d298-4912-b6d8-f93f77501e4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42317
98720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.4231798720
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.3172940262
Short name T1513
Test name
Test status
Simulation time 152526650 ps
CPU time 0.77 seconds
Started Jun 27 06:35:12 PM PDT 24
Finished Jun 27 06:35:19 PM PDT 24
Peak memory 206308 kb
Host smart-5060902f-c38c-4bb2-b97b-ce1ac14e0bc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31729
40262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.3172940262
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.3996346909
Short name T2463
Test name
Test status
Simulation time 229876447 ps
CPU time 0.87 seconds
Started Jun 27 06:35:10 PM PDT 24
Finished Jun 27 06:35:16 PM PDT 24
Peak memory 206296 kb
Host smart-58da71ad-5195-431c-b0fd-ada2100df72b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39963
46909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.3996346909
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_invalid_sync.728688225
Short name T2540
Test name
Test status
Simulation time 8217490214 ps
CPU time 230.05 seconds
Started Jun 27 06:35:12 PM PDT 24
Finished Jun 27 06:39:08 PM PDT 24
Peak memory 206484 kb
Host smart-0a252c27-33f3-4b58-afdc-ce28bad5d233
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=728688225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.728688225
Directory /workspace/5.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.1249307078
Short name T2034
Test name
Test status
Simulation time 196931835 ps
CPU time 0.84 seconds
Started Jun 27 06:35:11 PM PDT 24
Finished Jun 27 06:35:16 PM PDT 24
Peak memory 206268 kb
Host smart-9bad0d24-29b0-4bad-8c10-78e1acbc81ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12493
07078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.1249307078
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.4097290728
Short name T2574
Test name
Test status
Simulation time 23361370115 ps
CPU time 22.02 seconds
Started Jun 27 06:35:12 PM PDT 24
Finished Jun 27 06:35:39 PM PDT 24
Peak memory 206316 kb
Host smart-e719fa47-f0dc-4583-b540-adc108ccdfaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40972
90728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.4097290728
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.654872271
Short name T2441
Test name
Test status
Simulation time 3322122366 ps
CPU time 3.8 seconds
Started Jun 27 06:35:12 PM PDT 24
Finished Jun 27 06:35:21 PM PDT 24
Peak memory 206328 kb
Host smart-21289971-bd0d-4c14-a2a2-8318e97e15fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65487
2271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.654872271
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.1118013153
Short name T2003
Test name
Test status
Simulation time 9905635744 ps
CPU time 260.03 seconds
Started Jun 27 06:35:11 PM PDT 24
Finished Jun 27 06:39:37 PM PDT 24
Peak memory 206512 kb
Host smart-98ff8ebc-cbca-4cf5-b73b-fe58038d8cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11180
13153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.1118013153
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.1828386742
Short name T898
Test name
Test status
Simulation time 6370789947 ps
CPU time 167.06 seconds
Started Jun 27 06:35:12 PM PDT 24
Finished Jun 27 06:38:04 PM PDT 24
Peak memory 206420 kb
Host smart-ecd41bfe-0727-473d-9f42-5c8701587dfb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1828386742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.1828386742
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.2409427933
Short name T808
Test name
Test status
Simulation time 286533048 ps
CPU time 0.91 seconds
Started Jun 27 06:35:15 PM PDT 24
Finished Jun 27 06:35:21 PM PDT 24
Peak memory 206264 kb
Host smart-427882d1-a7ea-40ba-955e-d5c9b7b1125a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2409427933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.2409427933
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.3416742367
Short name T1383
Test name
Test status
Simulation time 182950487 ps
CPU time 0.84 seconds
Started Jun 27 06:35:12 PM PDT 24
Finished Jun 27 06:35:18 PM PDT 24
Peak memory 206276 kb
Host smart-910f0a4f-e985-4ee0-b14a-92cfb59bc04e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34167
42367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.3416742367
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.2222643880
Short name T83
Test name
Test status
Simulation time 4727108794 ps
CPU time 42.5 seconds
Started Jun 27 06:35:11 PM PDT 24
Finished Jun 27 06:35:58 PM PDT 24
Peak memory 206488 kb
Host smart-af704f20-6147-40d3-bbea-8ca43b220cc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22226
43880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.2222643880
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.2219095243
Short name T936
Test name
Test status
Simulation time 3300917476 ps
CPU time 84.68 seconds
Started Jun 27 06:35:13 PM PDT 24
Finished Jun 27 06:36:43 PM PDT 24
Peak memory 206444 kb
Host smart-7fdfe368-4303-4ff1-877d-6b73ec3067e4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2219095243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.2219095243
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.2423201182
Short name T1014
Test name
Test status
Simulation time 150388033 ps
CPU time 0.75 seconds
Started Jun 27 06:35:12 PM PDT 24
Finished Jun 27 06:35:19 PM PDT 24
Peak memory 206292 kb
Host smart-26f2c40d-a1a3-4416-ae18-8ebf46aecc92
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2423201182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.2423201182
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.4142864183
Short name T949
Test name
Test status
Simulation time 158286988 ps
CPU time 0.8 seconds
Started Jun 27 06:35:12 PM PDT 24
Finished Jun 27 06:35:19 PM PDT 24
Peak memory 206268 kb
Host smart-6ff76a50-61ba-422a-8b63-73c648361598
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41428
64183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.4142864183
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.1689959117
Short name T133
Test name
Test status
Simulation time 210692342 ps
CPU time 0.87 seconds
Started Jun 27 06:35:14 PM PDT 24
Finished Jun 27 06:35:21 PM PDT 24
Peak memory 206272 kb
Host smart-b4743c9e-e903-4a52-bedf-ef7f52bb0e58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16899
59117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.1689959117
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.610814545
Short name T669
Test name
Test status
Simulation time 154447127 ps
CPU time 0.77 seconds
Started Jun 27 06:35:14 PM PDT 24
Finished Jun 27 06:35:21 PM PDT 24
Peak memory 206288 kb
Host smart-dbc0251b-8f62-4cd2-9eee-86528ac1a55c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61081
4545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.610814545
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.566664279
Short name T1133
Test name
Test status
Simulation time 166300902 ps
CPU time 0.78 seconds
Started Jun 27 06:35:13 PM PDT 24
Finished Jun 27 06:35:19 PM PDT 24
Peak memory 206288 kb
Host smart-72569f9d-7224-43cb-8cea-99ef0ea0c4e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56666
4279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.566664279
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.965926690
Short name T311
Test name
Test status
Simulation time 204841541 ps
CPU time 0.82 seconds
Started Jun 27 06:35:13 PM PDT 24
Finished Jun 27 06:35:19 PM PDT 24
Peak memory 206268 kb
Host smart-c521bc5c-c7f7-4603-8bb2-7a7359e68789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96592
6690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.965926690
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.824184783
Short name T171
Test name
Test status
Simulation time 169966152 ps
CPU time 0.83 seconds
Started Jun 27 06:35:12 PM PDT 24
Finished Jun 27 06:35:19 PM PDT 24
Peak memory 206288 kb
Host smart-9cb58bd2-10f9-498c-a680-9366e93788a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82418
4783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.824184783
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.4077279537
Short name T867
Test name
Test status
Simulation time 245820125 ps
CPU time 0.96 seconds
Started Jun 27 06:35:15 PM PDT 24
Finished Jun 27 06:35:21 PM PDT 24
Peak memory 206272 kb
Host smart-165fa9a0-38c9-41b4-af1e-0f00c1a2ef7d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4077279537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.4077279537
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.128211942
Short name T1598
Test name
Test status
Simulation time 145801536 ps
CPU time 0.73 seconds
Started Jun 27 06:35:12 PM PDT 24
Finished Jun 27 06:35:18 PM PDT 24
Peak memory 206280 kb
Host smart-c7c6ee11-7509-4276-ad08-295d37f4c995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12821
1942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.128211942
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.2443762707
Short name T2620
Test name
Test status
Simulation time 89939126 ps
CPU time 0.71 seconds
Started Jun 27 06:35:27 PM PDT 24
Finished Jun 27 06:35:30 PM PDT 24
Peak memory 206268 kb
Host smart-f28e038d-36a3-43d4-b1e2-1e5fc59bd513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24437
62707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.2443762707
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.1786795955
Short name T1863
Test name
Test status
Simulation time 13852216544 ps
CPU time 30.63 seconds
Started Jun 27 06:35:29 PM PDT 24
Finished Jun 27 06:36:03 PM PDT 24
Peak memory 206456 kb
Host smart-ebc5205a-f96c-4741-b8f2-8767b5a29db8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17867
95955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.1786795955
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.3631177443
Short name T1934
Test name
Test status
Simulation time 180381992 ps
CPU time 0.86 seconds
Started Jun 27 06:35:29 PM PDT 24
Finished Jun 27 06:35:33 PM PDT 24
Peak memory 206272 kb
Host smart-75809700-87c2-4582-bfd9-9b436f3d51cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36311
77443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.3631177443
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.321786313
Short name T2506
Test name
Test status
Simulation time 172299257 ps
CPU time 0.81 seconds
Started Jun 27 06:35:29 PM PDT 24
Finished Jun 27 06:35:34 PM PDT 24
Peak memory 206264 kb
Host smart-06cabcc2-4fb4-48b5-ab5c-51a2746988d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32178
6313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.321786313
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.1578109732
Short name T2297
Test name
Test status
Simulation time 5063296982 ps
CPU time 39.7 seconds
Started Jun 27 06:35:32 PM PDT 24
Finished Jun 27 06:36:16 PM PDT 24
Peak memory 206452 kb
Host smart-f559f10b-bfb4-4d24-9e49-f286d3edac40
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1578109732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.1578109732
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.644376884
Short name T747
Test name
Test status
Simulation time 18278496856 ps
CPU time 394.5 seconds
Started Jun 27 06:35:26 PM PDT 24
Finished Jun 27 06:42:03 PM PDT 24
Peak memory 206376 kb
Host smart-f0ab8541-d9ed-4446-9b72-bb27c6efdd22
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=644376884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.644376884
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.190028148
Short name T396
Test name
Test status
Simulation time 226530739 ps
CPU time 0.82 seconds
Started Jun 27 06:35:27 PM PDT 24
Finished Jun 27 06:35:30 PM PDT 24
Peak memory 206292 kb
Host smart-0105bee0-39fc-44de-a86c-3a6e8d86352b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19002
8148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.190028148
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.2425751538
Short name T654
Test name
Test status
Simulation time 161581377 ps
CPU time 0.83 seconds
Started Jun 27 06:35:26 PM PDT 24
Finished Jun 27 06:35:29 PM PDT 24
Peak memory 206172 kb
Host smart-5a341aee-38e4-4405-b469-ced56d463d91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24257
51538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.2425751538
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.3848006187
Short name T1457
Test name
Test status
Simulation time 168008444 ps
CPU time 0.83 seconds
Started Jun 27 06:35:28 PM PDT 24
Finished Jun 27 06:35:32 PM PDT 24
Peak memory 206272 kb
Host smart-91c8d485-e90f-41d6-b582-95e1742f3424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38480
06187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.3848006187
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.1110887813
Short name T2036
Test name
Test status
Simulation time 151080661 ps
CPU time 0.79 seconds
Started Jun 27 06:35:31 PM PDT 24
Finished Jun 27 06:35:36 PM PDT 24
Peak memory 206204 kb
Host smart-b5e344dc-b0b7-40a8-8377-6993313b8ad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11108
87813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.1110887813
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.3533704385
Short name T2497
Test name
Test status
Simulation time 186514893 ps
CPU time 0.77 seconds
Started Jun 27 06:35:29 PM PDT 24
Finished Jun 27 06:35:34 PM PDT 24
Peak memory 206292 kb
Host smart-3e850e0c-fcea-4e51-b518-99099587bfdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35337
04385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.3533704385
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.3160200646
Short name T1308
Test name
Test status
Simulation time 247346264 ps
CPU time 0.95 seconds
Started Jun 27 06:35:24 PM PDT 24
Finished Jun 27 06:35:26 PM PDT 24
Peak memory 206264 kb
Host smart-c2098010-860f-4830-a7ee-120c6534a12f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31602
00646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.3160200646
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.216363813
Short name T2267
Test name
Test status
Simulation time 4080149721 ps
CPU time 107.8 seconds
Started Jun 27 06:35:29 PM PDT 24
Finished Jun 27 06:37:21 PM PDT 24
Peak memory 206484 kb
Host smart-4f94ae9d-6af7-4a46-a66a-16e1447545ee
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=216363813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.216363813
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.2231337243
Short name T853
Test name
Test status
Simulation time 179071573 ps
CPU time 0.8 seconds
Started Jun 27 06:35:27 PM PDT 24
Finished Jun 27 06:35:31 PM PDT 24
Peak memory 206280 kb
Host smart-69e9c9a5-0f2f-4ad5-a62a-8ddb90afeef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22313
37243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.2231337243
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.2821559559
Short name T1804
Test name
Test status
Simulation time 172460318 ps
CPU time 0.77 seconds
Started Jun 27 06:35:28 PM PDT 24
Finished Jun 27 06:35:32 PM PDT 24
Peak memory 206272 kb
Host smart-a96d1afa-6316-4735-8f81-c7b93698dffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28215
59559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.2821559559
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.594111245
Short name T1093
Test name
Test status
Simulation time 6351046595 ps
CPU time 54.84 seconds
Started Jun 27 06:35:23 PM PDT 24
Finished Jun 27 06:36:19 PM PDT 24
Peak memory 206428 kb
Host smart-1a4656d1-e6f5-423e-9789-1a8ac2784e16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59411
1245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.594111245
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.491846878
Short name T1386
Test name
Test status
Simulation time 47048440 ps
CPU time 0.72 seconds
Started Jun 27 06:35:31 PM PDT 24
Finished Jun 27 06:35:35 PM PDT 24
Peak memory 206356 kb
Host smart-4c9c112c-7609-44c1-8d2b-5f37f514d385
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=491846878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.491846878
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.121273047
Short name T1985
Test name
Test status
Simulation time 4106647436 ps
CPU time 5.34 seconds
Started Jun 27 06:35:30 PM PDT 24
Finished Jun 27 06:35:40 PM PDT 24
Peak memory 206344 kb
Host smart-d5714c22-d08e-4081-9620-298b235a18f7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=121273047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.121273047
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.977649707
Short name T516
Test name
Test status
Simulation time 13399547691 ps
CPU time 14.3 seconds
Started Jun 27 06:35:31 PM PDT 24
Finished Jun 27 06:35:50 PM PDT 24
Peak memory 206276 kb
Host smart-301d212a-24b1-48db-8bc4-1a01b69735e6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=977649707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.977649707
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.959517953
Short name T1281
Test name
Test status
Simulation time 23323003221 ps
CPU time 27.25 seconds
Started Jun 27 06:35:26 PM PDT 24
Finished Jun 27 06:35:56 PM PDT 24
Peak memory 206396 kb
Host smart-3684982a-dcf7-4dd6-9109-7bcbd8b55c77
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=959517953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.959517953
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.2742216757
Short name T1318
Test name
Test status
Simulation time 157091292 ps
CPU time 0.82 seconds
Started Jun 27 06:35:27 PM PDT 24
Finished Jun 27 06:35:30 PM PDT 24
Peak memory 206264 kb
Host smart-eb8494ca-f9fb-4716-952d-a816f8ad8341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27422
16757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.2742216757
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.2967282885
Short name T1146
Test name
Test status
Simulation time 175765673 ps
CPU time 0.81 seconds
Started Jun 27 06:35:29 PM PDT 24
Finished Jun 27 06:35:33 PM PDT 24
Peak memory 206236 kb
Host smart-11f6abd3-b853-40e0-b552-8cb7b7192da6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29672
82885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.2967282885
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.637292639
Short name T2405
Test name
Test status
Simulation time 324121089 ps
CPU time 1.09 seconds
Started Jun 27 06:35:33 PM PDT 24
Finished Jun 27 06:35:38 PM PDT 24
Peak memory 206284 kb
Host smart-fd591456-4b15-4b41-86ab-3da55f557ead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63729
2639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.637292639
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.2658013818
Short name T2019
Test name
Test status
Simulation time 1120824683 ps
CPU time 2.35 seconds
Started Jun 27 06:35:31 PM PDT 24
Finished Jun 27 06:35:37 PM PDT 24
Peak memory 206180 kb
Host smart-b9a15d9b-91ef-4756-910a-3eb4c3fef5f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26580
13818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.2658013818
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.2742880651
Short name T1237
Test name
Test status
Simulation time 21191302265 ps
CPU time 39.24 seconds
Started Jun 27 06:35:33 PM PDT 24
Finished Jun 27 06:36:16 PM PDT 24
Peak memory 206496 kb
Host smart-cfe32bc1-d0c8-40e7-a635-456c8e8bab6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27428
80651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.2742880651
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.4099612269
Short name T941
Test name
Test status
Simulation time 422309710 ps
CPU time 1.27 seconds
Started Jun 27 06:35:33 PM PDT 24
Finished Jun 27 06:35:38 PM PDT 24
Peak memory 206300 kb
Host smart-72d1c6a3-70be-492e-a3f8-8fd7f31d9eba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40996
12269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.4099612269
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.3676191767
Short name T2281
Test name
Test status
Simulation time 135672731 ps
CPU time 0.76 seconds
Started Jun 27 06:35:29 PM PDT 24
Finished Jun 27 06:35:33 PM PDT 24
Peak memory 206272 kb
Host smart-cacfa002-1e2d-436c-a496-742ed71b208c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36761
91767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.3676191767
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.3213634600
Short name T1092
Test name
Test status
Simulation time 45899486 ps
CPU time 0.64 seconds
Started Jun 27 06:35:26 PM PDT 24
Finished Jun 27 06:35:29 PM PDT 24
Peak memory 206272 kb
Host smart-9aee9b6c-37d1-4f32-a45b-a472c1029597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32136
34600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.3213634600
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.1354067268
Short name T1926
Test name
Test status
Simulation time 828864103 ps
CPU time 2 seconds
Started Jun 27 06:35:26 PM PDT 24
Finished Jun 27 06:35:30 PM PDT 24
Peak memory 206384 kb
Host smart-09fa0fdd-1101-4053-8122-7488e461418b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13540
67268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.1354067268
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.1453987482
Short name T2204
Test name
Test status
Simulation time 392045511 ps
CPU time 2.21 seconds
Started Jun 27 06:35:29 PM PDT 24
Finished Jun 27 06:35:35 PM PDT 24
Peak memory 206444 kb
Host smart-f1a55aa7-72c6-482a-9bb2-d06ef4432414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14539
87482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.1453987482
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.3911891469
Short name T1723
Test name
Test status
Simulation time 222383552 ps
CPU time 0.87 seconds
Started Jun 27 06:35:27 PM PDT 24
Finished Jun 27 06:35:30 PM PDT 24
Peak memory 206276 kb
Host smart-23c69c52-3002-4af0-bdd8-2c70c0865a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39118
91469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.3911891469
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.90288438
Short name T523
Test name
Test status
Simulation time 139059154 ps
CPU time 0.76 seconds
Started Jun 27 06:35:25 PM PDT 24
Finished Jun 27 06:35:27 PM PDT 24
Peak memory 206268 kb
Host smart-8fcdda01-524e-46d1-8f2f-454275f00efd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90288
438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.90288438
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.4254958175
Short name T1229
Test name
Test status
Simulation time 248114544 ps
CPU time 0.95 seconds
Started Jun 27 06:35:30 PM PDT 24
Finished Jun 27 06:35:35 PM PDT 24
Peak memory 206296 kb
Host smart-f4d1b73d-d400-4522-aeae-abaf71f90acc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42549
58175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.4254958175
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_invalid_sync.979289323
Short name T2529
Test name
Test status
Simulation time 5592025427 ps
CPU time 54.65 seconds
Started Jun 27 06:35:31 PM PDT 24
Finished Jun 27 06:36:30 PM PDT 24
Peak memory 206412 kb
Host smart-7e05bedd-0ffe-4a31-b667-ee99b6299c48
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=979289323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.979289323
Directory /workspace/6.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.227295683
Short name T550
Test name
Test status
Simulation time 259598724 ps
CPU time 0.99 seconds
Started Jun 27 06:35:27 PM PDT 24
Finished Jun 27 06:35:31 PM PDT 24
Peak memory 206280 kb
Host smart-7cb86563-dc00-4d2f-83d8-66e82f526e5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22729
5683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.227295683
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.3316155654
Short name T1811
Test name
Test status
Simulation time 23330517893 ps
CPU time 23.78 seconds
Started Jun 27 06:35:28 PM PDT 24
Finished Jun 27 06:35:55 PM PDT 24
Peak memory 206344 kb
Host smart-95aa15cf-6628-46b9-9726-41f4566be560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33161
55654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.3316155654
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.92732637
Short name T1500
Test name
Test status
Simulation time 3317419960 ps
CPU time 4.37 seconds
Started Jun 27 06:35:29 PM PDT 24
Finished Jun 27 06:35:38 PM PDT 24
Peak memory 206332 kb
Host smart-ea49490f-38a8-4a53-9155-1a0ea60b92b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92732
637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.92732637
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.2389160155
Short name T904
Test name
Test status
Simulation time 7850755394 ps
CPU time 68.05 seconds
Started Jun 27 06:35:27 PM PDT 24
Finished Jun 27 06:36:38 PM PDT 24
Peak memory 206500 kb
Host smart-d0c444cf-96f2-4ab3-8573-a3b499a7d880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23891
60155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.2389160155
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.3639788743
Short name T694
Test name
Test status
Simulation time 5339949349 ps
CPU time 36.25 seconds
Started Jun 27 06:35:28 PM PDT 24
Finished Jun 27 06:36:09 PM PDT 24
Peak memory 206456 kb
Host smart-53f15d93-f5ba-4d6d-b8aa-9a8420e39a32
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3639788743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.3639788743
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.368817937
Short name T1507
Test name
Test status
Simulation time 256609987 ps
CPU time 0.86 seconds
Started Jun 27 06:35:24 PM PDT 24
Finished Jun 27 06:35:26 PM PDT 24
Peak memory 206308 kb
Host smart-296a1119-391e-4362-bc73-f5262663dcc5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=368817937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.368817937
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.2826592074
Short name T1941
Test name
Test status
Simulation time 230983685 ps
CPU time 0.85 seconds
Started Jun 27 06:35:29 PM PDT 24
Finished Jun 27 06:35:34 PM PDT 24
Peak memory 206240 kb
Host smart-08430fb9-f10c-4b57-b140-516dcfaf59c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28265
92074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.2826592074
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.4164953942
Short name T417
Test name
Test status
Simulation time 3893849641 ps
CPU time 106.23 seconds
Started Jun 27 06:35:29 PM PDT 24
Finished Jun 27 06:37:19 PM PDT 24
Peak memory 206440 kb
Host smart-2cfcb96f-3528-42c2-b555-a0991b7a2073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41649
53942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.4164953942
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.2288623181
Short name T2303
Test name
Test status
Simulation time 5224974047 ps
CPU time 47.13 seconds
Started Jun 27 06:35:31 PM PDT 24
Finished Jun 27 06:36:22 PM PDT 24
Peak memory 206272 kb
Host smart-78e49fa2-51b2-465b-be86-1657168b14a5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2288623181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.2288623181
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.3624473223
Short name T310
Test name
Test status
Simulation time 169806921 ps
CPU time 0.78 seconds
Started Jun 27 06:35:31 PM PDT 24
Finished Jun 27 06:35:36 PM PDT 24
Peak memory 206292 kb
Host smart-5725e634-595f-4a42-99ec-d0fc3be0e20a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3624473223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.3624473223
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.3185271879
Short name T1864
Test name
Test status
Simulation time 143248053 ps
CPU time 0.75 seconds
Started Jun 27 06:35:27 PM PDT 24
Finished Jun 27 06:35:31 PM PDT 24
Peak memory 206272 kb
Host smart-dc379910-ce38-4749-b02e-1b45f2fd6eed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31852
71879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.3185271879
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.3969603576
Short name T2120
Test name
Test status
Simulation time 226796645 ps
CPU time 0.87 seconds
Started Jun 27 06:35:31 PM PDT 24
Finished Jun 27 06:35:36 PM PDT 24
Peak memory 206272 kb
Host smart-6ee5fc15-ee6b-45e8-bc04-633294a99950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39696
03576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.3969603576
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.3049015060
Short name T1786
Test name
Test status
Simulation time 180695908 ps
CPU time 0.8 seconds
Started Jun 27 06:35:28 PM PDT 24
Finished Jun 27 06:35:32 PM PDT 24
Peak memory 206300 kb
Host smart-3448990a-9727-4366-ba52-c5e7263025ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30490
15060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.3049015060
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.675953228
Short name T1256
Test name
Test status
Simulation time 147015434 ps
CPU time 0.75 seconds
Started Jun 27 06:35:27 PM PDT 24
Finished Jun 27 06:35:30 PM PDT 24
Peak memory 206276 kb
Host smart-bc31dea6-4129-446e-abfd-a4b91d989b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67595
3228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.675953228
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.2872880509
Short name T1503
Test name
Test status
Simulation time 195373567 ps
CPU time 0.81 seconds
Started Jun 27 06:35:29 PM PDT 24
Finished Jun 27 06:35:33 PM PDT 24
Peak memory 206236 kb
Host smart-e7c4bfb1-f392-42ee-923b-35599a24b992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28728
80509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.2872880509
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.527800324
Short name T2539
Test name
Test status
Simulation time 151064670 ps
CPU time 0.75 seconds
Started Jun 27 06:35:29 PM PDT 24
Finished Jun 27 06:35:33 PM PDT 24
Peak memory 206308 kb
Host smart-6fcd6907-0c56-4cdb-9eca-419014fa2b21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52780
0324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.527800324
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.434223930
Short name T1835
Test name
Test status
Simulation time 294065799 ps
CPU time 1.12 seconds
Started Jun 27 06:35:28 PM PDT 24
Finished Jun 27 06:35:33 PM PDT 24
Peak memory 206296 kb
Host smart-e9967b15-d976-40a0-97c3-21ce25d136a5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=434223930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.434223930
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.2601677040
Short name T681
Test name
Test status
Simulation time 148577379 ps
CPU time 0.76 seconds
Started Jun 27 06:35:29 PM PDT 24
Finished Jun 27 06:35:33 PM PDT 24
Peak memory 206272 kb
Host smart-70553fda-ddbe-4204-bcc2-b18510099ab2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26016
77040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.2601677040
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.2210026275
Short name T1743
Test name
Test status
Simulation time 95785942 ps
CPU time 0.72 seconds
Started Jun 27 06:35:29 PM PDT 24
Finished Jun 27 06:35:35 PM PDT 24
Peak memory 206272 kb
Host smart-66de2228-ad89-4527-b025-c96387c01908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22100
26275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.2210026275
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.2653946018
Short name T2196
Test name
Test status
Simulation time 11878295499 ps
CPU time 27.15 seconds
Started Jun 27 06:35:27 PM PDT 24
Finished Jun 27 06:35:57 PM PDT 24
Peak memory 206420 kb
Host smart-7b13010f-577d-424e-b196-1dd65cdec0da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26539
46018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.2653946018
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.1355234292
Short name T1073
Test name
Test status
Simulation time 157295798 ps
CPU time 0.8 seconds
Started Jun 27 06:35:33 PM PDT 24
Finished Jun 27 06:35:38 PM PDT 24
Peak memory 206276 kb
Host smart-de65f295-0e2d-4843-b890-25221bc82c84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13552
34292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.1355234292
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.1183536687
Short name T2148
Test name
Test status
Simulation time 160682945 ps
CPU time 0.76 seconds
Started Jun 27 06:35:32 PM PDT 24
Finished Jun 27 06:35:37 PM PDT 24
Peak memory 206236 kb
Host smart-0b2efc2e-da95-4b2c-b0c8-1b6719608d3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11835
36687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.1183536687
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.3507737530
Short name T2140
Test name
Test status
Simulation time 8824214770 ps
CPU time 57.87 seconds
Started Jun 27 06:35:32 PM PDT 24
Finished Jun 27 06:36:34 PM PDT 24
Peak memory 206512 kb
Host smart-9dbb3017-53d9-4cea-9441-3eedcd99884c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3507737530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.3507737530
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.1078101618
Short name T2390
Test name
Test status
Simulation time 8332248217 ps
CPU time 77.3 seconds
Started Jun 27 06:35:32 PM PDT 24
Finished Jun 27 06:36:54 PM PDT 24
Peak memory 206528 kb
Host smart-d2764eca-f067-4f8b-9d01-75c6d01d679a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1078101618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.1078101618
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.1764688349
Short name T1321
Test name
Test status
Simulation time 14628764571 ps
CPU time 77.25 seconds
Started Jun 27 06:35:32 PM PDT 24
Finished Jun 27 06:36:53 PM PDT 24
Peak memory 206436 kb
Host smart-0f923d40-6166-44bf-8ccf-486813f6da61
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1764688349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.1764688349
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.1949269138
Short name T1871
Test name
Test status
Simulation time 164245055 ps
CPU time 0.79 seconds
Started Jun 27 06:35:32 PM PDT 24
Finished Jun 27 06:35:37 PM PDT 24
Peak memory 206320 kb
Host smart-b924056e-6372-4d7f-aca9-63721f3a5973
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19492
69138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.1949269138
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.3191364603
Short name T1623
Test name
Test status
Simulation time 205449918 ps
CPU time 0.92 seconds
Started Jun 27 06:35:31 PM PDT 24
Finished Jun 27 06:35:36 PM PDT 24
Peak memory 206208 kb
Host smart-c046b2d5-8fcc-488d-89bf-f3fb59fb67ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31913
64603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.3191364603
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.147198483
Short name T50
Test name
Test status
Simulation time 190946668 ps
CPU time 0.83 seconds
Started Jun 27 06:35:32 PM PDT 24
Finished Jun 27 06:35:37 PM PDT 24
Peak memory 206124 kb
Host smart-c37ab191-0d1e-4a3f-bf09-b857f905b928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14719
8483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.147198483
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.2591486844
Short name T1176
Test name
Test status
Simulation time 146871561 ps
CPU time 0.76 seconds
Started Jun 27 06:35:33 PM PDT 24
Finished Jun 27 06:35:38 PM PDT 24
Peak memory 206280 kb
Host smart-6809600e-309c-426a-ac8d-b2b1354a4c28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25914
86844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.2591486844
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.4022136173
Short name T859
Test name
Test status
Simulation time 172685600 ps
CPU time 0.78 seconds
Started Jun 27 06:35:32 PM PDT 24
Finished Jun 27 06:35:37 PM PDT 24
Peak memory 206312 kb
Host smart-bd96dc4e-b324-4cb4-8036-0995a084f5a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40221
36173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.4022136173
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.3284646516
Short name T1713
Test name
Test status
Simulation time 208868073 ps
CPU time 0.87 seconds
Started Jun 27 06:35:32 PM PDT 24
Finished Jun 27 06:35:37 PM PDT 24
Peak memory 206120 kb
Host smart-89efbf52-2547-4ff5-af33-b0f32fe46e74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32846
46516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.3284646516
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.1118096668
Short name T2069
Test name
Test status
Simulation time 6157152296 ps
CPU time 41.85 seconds
Started Jun 27 06:35:32 PM PDT 24
Finished Jun 27 06:36:18 PM PDT 24
Peak memory 206448 kb
Host smart-f24366ed-3cd6-42e0-b5b2-8a62aea170c9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1118096668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.1118096668
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.4165115964
Short name T1160
Test name
Test status
Simulation time 184404223 ps
CPU time 0.8 seconds
Started Jun 27 06:35:31 PM PDT 24
Finished Jun 27 06:35:36 PM PDT 24
Peak memory 206276 kb
Host smart-ca91d062-8940-41c8-8e89-993e8e84c249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41651
15964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.4165115964
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.2714866404
Short name T2067
Test name
Test status
Simulation time 209950210 ps
CPU time 0.84 seconds
Started Jun 27 06:35:30 PM PDT 24
Finished Jun 27 06:35:35 PM PDT 24
Peak memory 206256 kb
Host smart-87baab85-ca92-4f24-8516-c15d39b2447f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27148
66404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.2714866404
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.2422066997
Short name T2596
Test name
Test status
Simulation time 5432721153 ps
CPU time 50.79 seconds
Started Jun 27 06:35:34 PM PDT 24
Finished Jun 27 06:36:28 PM PDT 24
Peak memory 206456 kb
Host smart-611f1de8-0e1d-4c10-aa1e-cf9dc8b703f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24220
66997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.2422066997
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.1755719583
Short name T1637
Test name
Test status
Simulation time 45082060 ps
CPU time 0.72 seconds
Started Jun 27 06:35:45 PM PDT 24
Finished Jun 27 06:35:48 PM PDT 24
Peak memory 206048 kb
Host smart-da919b8e-4e5d-46e9-bc95-8d7b826e9f72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1755719583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.1755719583
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.3907633827
Short name T1300
Test name
Test status
Simulation time 4093381974 ps
CPU time 4.77 seconds
Started Jun 27 06:35:34 PM PDT 24
Finished Jun 27 06:35:42 PM PDT 24
Peak memory 206432 kb
Host smart-2d8c636e-84bf-425e-8f31-9d6b925a0eb1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3907633827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.3907633827
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.281480475
Short name T2411
Test name
Test status
Simulation time 13359352520 ps
CPU time 12.98 seconds
Started Jun 27 06:35:34 PM PDT 24
Finished Jun 27 06:35:51 PM PDT 24
Peak memory 206472 kb
Host smart-e19d5326-a440-411e-a364-b4955bcd194a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=281480475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.281480475
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.2029217523
Short name T2296
Test name
Test status
Simulation time 23497819122 ps
CPU time 24.36 seconds
Started Jun 27 06:35:35 PM PDT 24
Finished Jun 27 06:36:02 PM PDT 24
Peak memory 206468 kb
Host smart-abf0424c-1d0b-4bbc-9a99-5db746a5bffa
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2029217523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.2029217523
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.1390001122
Short name T1917
Test name
Test status
Simulation time 183316574 ps
CPU time 0.85 seconds
Started Jun 27 06:35:28 PM PDT 24
Finished Jun 27 06:35:32 PM PDT 24
Peak memory 206456 kb
Host smart-f68bda68-4d18-48af-839f-db5f6b19f7db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13900
01122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.1390001122
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.3206417453
Short name T2094
Test name
Test status
Simulation time 197332247 ps
CPU time 0.88 seconds
Started Jun 27 06:35:31 PM PDT 24
Finished Jun 27 06:35:36 PM PDT 24
Peak memory 205972 kb
Host smart-497f4324-74b6-4657-bb27-374151e49588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32064
17453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.3206417453
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.2357955322
Short name T1732
Test name
Test status
Simulation time 210179061 ps
CPU time 0.81 seconds
Started Jun 27 06:35:37 PM PDT 24
Finished Jun 27 06:35:40 PM PDT 24
Peak memory 206272 kb
Host smart-44123b19-5795-4999-900b-d37acccaa3e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23579
55322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.2357955322
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.2541173479
Short name T1006
Test name
Test status
Simulation time 954418071 ps
CPU time 2.12 seconds
Started Jun 27 06:35:37 PM PDT 24
Finished Jun 27 06:35:41 PM PDT 24
Peak memory 206420 kb
Host smart-bfc34a2e-d361-4a41-bd1a-746a348dade9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25411
73479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.2541173479
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.3144535968
Short name T2088
Test name
Test status
Simulation time 17793290508 ps
CPU time 35.15 seconds
Started Jun 27 06:35:31 PM PDT 24
Finished Jun 27 06:36:10 PM PDT 24
Peak memory 206132 kb
Host smart-237ba1be-170d-45cd-82a3-7b906f647fe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31445
35968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.3144535968
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.3767157165
Short name T1360
Test name
Test status
Simulation time 433993699 ps
CPU time 1.44 seconds
Started Jun 27 06:35:32 PM PDT 24
Finished Jun 27 06:35:37 PM PDT 24
Peak memory 206288 kb
Host smart-18f5dfa4-518c-4afa-b564-21919af6195e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37671
57165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.3767157165
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.3292303084
Short name T553
Test name
Test status
Simulation time 149447391 ps
CPU time 0.75 seconds
Started Jun 27 06:35:29 PM PDT 24
Finished Jun 27 06:35:34 PM PDT 24
Peak memory 206248 kb
Host smart-2de4793c-af23-420a-b7f9-d6e07c235a0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32923
03084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.3292303084
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.143032857
Short name T1731
Test name
Test status
Simulation time 37964212 ps
CPU time 0.68 seconds
Started Jun 27 06:35:38 PM PDT 24
Finished Jun 27 06:35:40 PM PDT 24
Peak memory 206280 kb
Host smart-2cecba06-411e-4821-9497-3ba909060eb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14303
2857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.143032857
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.4029402783
Short name T866
Test name
Test status
Simulation time 799214612 ps
CPU time 1.88 seconds
Started Jun 27 06:35:38 PM PDT 24
Finished Jun 27 06:35:41 PM PDT 24
Peak memory 206360 kb
Host smart-82ea3fef-7fff-490f-8602-931ce5b8b5eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40294
02783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.4029402783
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.4119227087
Short name T737
Test name
Test status
Simulation time 234186772 ps
CPU time 1.58 seconds
Started Jun 27 06:35:39 PM PDT 24
Finished Jun 27 06:35:41 PM PDT 24
Peak memory 206368 kb
Host smart-67a38e6d-001f-4148-9cb7-60b7bf076b18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41192
27087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.4119227087
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.170862405
Short name T1312
Test name
Test status
Simulation time 229761581 ps
CPU time 0.92 seconds
Started Jun 27 06:35:32 PM PDT 24
Finished Jun 27 06:35:37 PM PDT 24
Peak memory 206272 kb
Host smart-cc904d2d-f124-4dde-956b-643199fa8cb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17086
2405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.170862405
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.2801386638
Short name T696
Test name
Test status
Simulation time 174988016 ps
CPU time 0.78 seconds
Started Jun 27 06:35:44 PM PDT 24
Finished Jun 27 06:35:46 PM PDT 24
Peak memory 206284 kb
Host smart-5c15e886-2186-48f1-a059-d2a0d5a44e54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28013
86638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.2801386638
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.2394201875
Short name T1274
Test name
Test status
Simulation time 200971161 ps
CPU time 0.9 seconds
Started Jun 27 06:35:49 PM PDT 24
Finished Jun 27 06:35:54 PM PDT 24
Peak memory 206296 kb
Host smart-519eab24-c4b0-43d0-872d-85f21bf7dae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23942
01875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.2394201875
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.585568246
Short name T1892
Test name
Test status
Simulation time 270499164 ps
CPU time 0.9 seconds
Started Jun 27 06:35:47 PM PDT 24
Finished Jun 27 06:35:51 PM PDT 24
Peak memory 206304 kb
Host smart-d6a5ca1e-d533-4d51-af50-18d94d0f1bb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58556
8246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.585568246
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.1817557771
Short name T341
Test name
Test status
Simulation time 23367636544 ps
CPU time 21.9 seconds
Started Jun 27 06:35:44 PM PDT 24
Finished Jun 27 06:36:07 PM PDT 24
Peak memory 206348 kb
Host smart-7cc255f9-a28f-4876-b812-f8c16b32dd2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18175
57771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.1817557771
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.4261423027
Short name T2116
Test name
Test status
Simulation time 3298806493 ps
CPU time 4.39 seconds
Started Jun 27 06:35:44 PM PDT 24
Finished Jun 27 06:35:50 PM PDT 24
Peak memory 206328 kb
Host smart-31db9e7b-0ac6-4832-99e3-50c7d961fb67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42614
23027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.4261423027
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.1061260263
Short name T1575
Test name
Test status
Simulation time 9347656311 ps
CPU time 79.65 seconds
Started Jun 27 06:35:43 PM PDT 24
Finished Jun 27 06:37:04 PM PDT 24
Peak memory 206492 kb
Host smart-e034b4ed-a9a5-44b4-a95f-87b8936c0cee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10612
60263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.1061260263
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.3225213045
Short name T697
Test name
Test status
Simulation time 3853876736 ps
CPU time 37.8 seconds
Started Jun 27 06:35:47 PM PDT 24
Finished Jun 27 06:36:28 PM PDT 24
Peak memory 206404 kb
Host smart-05e23795-9b6e-417c-a3d0-1a4a2db7b16c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3225213045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.3225213045
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.462389588
Short name T2343
Test name
Test status
Simulation time 248705048 ps
CPU time 0.93 seconds
Started Jun 27 06:35:45 PM PDT 24
Finished Jun 27 06:35:48 PM PDT 24
Peak memory 206296 kb
Host smart-6a49486f-f6e7-4c45-9721-d1f1d4e70a15
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=462389588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.462389588
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.336924696
Short name T982
Test name
Test status
Simulation time 205210308 ps
CPU time 0.88 seconds
Started Jun 27 06:35:48 PM PDT 24
Finished Jun 27 06:35:53 PM PDT 24
Peak memory 206284 kb
Host smart-e3563baf-a44f-4d05-8da8-50eac5e59873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33692
4696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.336924696
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.1963567425
Short name T1326
Test name
Test status
Simulation time 4815825869 ps
CPU time 47.56 seconds
Started Jun 27 06:35:43 PM PDT 24
Finished Jun 27 06:36:31 PM PDT 24
Peak memory 206632 kb
Host smart-58b4f309-15a9-445d-bd96-6a1a8a59af3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19635
67425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.1963567425
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.3427500711
Short name T2466
Test name
Test status
Simulation time 4825553474 ps
CPU time 44.77 seconds
Started Jun 27 06:35:45 PM PDT 24
Finished Jun 27 06:36:33 PM PDT 24
Peak memory 206344 kb
Host smart-0caea2d9-f562-48e8-b0a8-296dbb580bbe
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3427500711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.3427500711
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.251703787
Short name T1028
Test name
Test status
Simulation time 172742233 ps
CPU time 0.79 seconds
Started Jun 27 06:35:46 PM PDT 24
Finished Jun 27 06:35:51 PM PDT 24
Peak memory 206316 kb
Host smart-077de731-bb52-4d93-a1ae-b5d0541adb78
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=251703787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.251703787
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.1611391337
Short name T686
Test name
Test status
Simulation time 175866377 ps
CPU time 0.78 seconds
Started Jun 27 06:35:47 PM PDT 24
Finished Jun 27 06:35:52 PM PDT 24
Peak memory 206228 kb
Host smart-45454f8e-12f0-457a-a496-73b817216d3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16113
91337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.1611391337
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.1582460851
Short name T126
Test name
Test status
Simulation time 202075322 ps
CPU time 0.96 seconds
Started Jun 27 06:35:45 PM PDT 24
Finished Jun 27 06:35:48 PM PDT 24
Peak memory 206272 kb
Host smart-5cd2e59c-b649-40ce-8ea8-4c0199c81971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15824
60851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.1582460851
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.1206922254
Short name T2363
Test name
Test status
Simulation time 140851678 ps
CPU time 0.75 seconds
Started Jun 27 06:35:44 PM PDT 24
Finished Jun 27 06:35:46 PM PDT 24
Peak memory 206260 kb
Host smart-08a3ae12-a055-4054-a434-11271c66589e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12069
22254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.1206922254
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.1222161624
Short name T2575
Test name
Test status
Simulation time 168855574 ps
CPU time 0.83 seconds
Started Jun 27 06:35:45 PM PDT 24
Finished Jun 27 06:35:49 PM PDT 24
Peak memory 206272 kb
Host smart-002201cd-f833-4ff2-8fc1-4789b34ef95c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12221
61624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.1222161624
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.3758089551
Short name T742
Test name
Test status
Simulation time 184263499 ps
CPU time 0.8 seconds
Started Jun 27 06:35:44 PM PDT 24
Finished Jun 27 06:35:47 PM PDT 24
Peak memory 206276 kb
Host smart-59494a1d-fe4f-49c2-8443-3ec5ea298cc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37580
89551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.3758089551
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.3403575536
Short name T170
Test name
Test status
Simulation time 169276013 ps
CPU time 0.79 seconds
Started Jun 27 06:35:46 PM PDT 24
Finished Jun 27 06:35:51 PM PDT 24
Peak memory 206288 kb
Host smart-d1808ddd-ed65-4838-a1f3-69bb911a9df3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34035
75536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.3403575536
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.1124285784
Short name T1197
Test name
Test status
Simulation time 197310713 ps
CPU time 0.87 seconds
Started Jun 27 06:35:45 PM PDT 24
Finished Jun 27 06:35:49 PM PDT 24
Peak memory 206280 kb
Host smart-b3f713bb-f82a-4762-a6f4-0693fc90d6ef
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1124285784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.1124285784
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.914174296
Short name T981
Test name
Test status
Simulation time 177710126 ps
CPU time 0.85 seconds
Started Jun 27 06:35:42 PM PDT 24
Finished Jun 27 06:35:44 PM PDT 24
Peak memory 206260 kb
Host smart-315f788c-dbd5-439d-8659-20134720a4e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91417
4296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.914174296
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.2582059283
Short name T1520
Test name
Test status
Simulation time 38904226 ps
CPU time 0.68 seconds
Started Jun 27 06:35:50 PM PDT 24
Finished Jun 27 06:35:55 PM PDT 24
Peak memory 206276 kb
Host smart-51b2e64f-fdf2-4b46-9058-a3249795d9ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25820
59283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.2582059283
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.3843628662
Short name T87
Test name
Test status
Simulation time 15768096618 ps
CPU time 38.71 seconds
Started Jun 27 06:35:44 PM PDT 24
Finished Jun 27 06:36:24 PM PDT 24
Peak memory 206512 kb
Host smart-164a9f34-200d-41bf-aeb0-b953af334b29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38436
28662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.3843628662
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.1785409249
Short name T1905
Test name
Test status
Simulation time 173285866 ps
CPU time 0.78 seconds
Started Jun 27 06:35:45 PM PDT 24
Finished Jun 27 06:35:49 PM PDT 24
Peak memory 206252 kb
Host smart-b8ac9888-8717-4c44-8b14-048f3bfef84b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17854
09249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.1785409249
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.4233373576
Short name T1588
Test name
Test status
Simulation time 181264754 ps
CPU time 0.84 seconds
Started Jun 27 06:35:47 PM PDT 24
Finished Jun 27 06:35:52 PM PDT 24
Peak memory 206292 kb
Host smart-576c148d-be30-4f99-bbc5-995b59172a33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42333
73576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.4233373576
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.411404515
Short name T1569
Test name
Test status
Simulation time 11979913114 ps
CPU time 64.37 seconds
Started Jun 27 06:35:47 PM PDT 24
Finished Jun 27 06:36:55 PM PDT 24
Peak memory 206508 kb
Host smart-ef24e254-abb8-4800-81b7-3b9ab6769d89
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=411404515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.411404515
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.2347481907
Short name T1990
Test name
Test status
Simulation time 10443433403 ps
CPU time 67.54 seconds
Started Jun 27 06:35:44 PM PDT 24
Finished Jun 27 06:36:53 PM PDT 24
Peak memory 206404 kb
Host smart-315a7f96-a9d6-4fb6-9005-04549677202d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2347481907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.2347481907
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.2638378054
Short name T1035
Test name
Test status
Simulation time 17136113816 ps
CPU time 373.38 seconds
Started Jun 27 06:35:45 PM PDT 24
Finished Jun 27 06:42:01 PM PDT 24
Peak memory 206380 kb
Host smart-fb6ebbc9-959f-498e-86c5-a68bd0ee45ca
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2638378054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.2638378054
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.224113604
Short name T2623
Test name
Test status
Simulation time 232053619 ps
CPU time 0.89 seconds
Started Jun 27 06:35:44 PM PDT 24
Finished Jun 27 06:35:47 PM PDT 24
Peak memory 206220 kb
Host smart-b0698439-f7ed-4710-b9ff-969a9e828f7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22411
3604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.224113604
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.3924218508
Short name T483
Test name
Test status
Simulation time 137356666 ps
CPU time 0.84 seconds
Started Jun 27 06:35:47 PM PDT 24
Finished Jun 27 06:35:51 PM PDT 24
Peak memory 206272 kb
Host smart-17a00675-2978-441b-b5ac-b0c84ef0a2dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39242
18508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.3924218508
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.115656900
Short name T1030
Test name
Test status
Simulation time 142944378 ps
CPU time 0.77 seconds
Started Jun 27 06:35:47 PM PDT 24
Finished Jun 27 06:35:51 PM PDT 24
Peak memory 206304 kb
Host smart-48cce862-377e-48f1-9830-939b3e413953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11565
6900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.115656900
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.2895864811
Short name T2514
Test name
Test status
Simulation time 153582314 ps
CPU time 0.82 seconds
Started Jun 27 06:35:43 PM PDT 24
Finished Jun 27 06:35:45 PM PDT 24
Peak memory 206276 kb
Host smart-a3361765-9ebc-4f32-8366-ee4fadd10939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28958
64811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.2895864811
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.7029947
Short name T337
Test name
Test status
Simulation time 149165962 ps
CPU time 0.76 seconds
Started Jun 27 06:35:46 PM PDT 24
Finished Jun 27 06:35:51 PM PDT 24
Peak memory 206272 kb
Host smart-4865b78d-40fe-49c2-a89f-90afc1cb19c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70299
47 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.7029947
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.882262728
Short name T673
Test name
Test status
Simulation time 202109105 ps
CPU time 0.89 seconds
Started Jun 27 06:35:44 PM PDT 24
Finished Jun 27 06:35:47 PM PDT 24
Peak memory 206292 kb
Host smart-0396288a-7db0-464e-9735-75a44a27dd10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88226
2728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.882262728
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.2402647662
Short name T935
Test name
Test status
Simulation time 5484877750 ps
CPU time 50.53 seconds
Started Jun 27 06:35:48 PM PDT 24
Finished Jun 27 06:36:42 PM PDT 24
Peak memory 206372 kb
Host smart-c415d852-42b2-44dc-83a8-189b0774bc12
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2402647662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.2402647662
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.902386188
Short name T2002
Test name
Test status
Simulation time 194352098 ps
CPU time 0.87 seconds
Started Jun 27 06:35:45 PM PDT 24
Finished Jun 27 06:35:48 PM PDT 24
Peak memory 206000 kb
Host smart-60a37dc2-127d-44ef-9737-9b873b1a321e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90238
6188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.902386188
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.1897462803
Short name T1143
Test name
Test status
Simulation time 176279838 ps
CPU time 0.78 seconds
Started Jun 27 06:35:48 PM PDT 24
Finished Jun 27 06:35:53 PM PDT 24
Peak memory 206272 kb
Host smart-5d4bf190-478b-4b98-adbb-3dd2b83a4c2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18974
62803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.1897462803
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.1223394877
Short name T514
Test name
Test status
Simulation time 4371767716 ps
CPU time 121.2 seconds
Started Jun 27 06:35:48 PM PDT 24
Finished Jun 27 06:37:53 PM PDT 24
Peak memory 206412 kb
Host smart-fe08d4a7-f52a-4a8b-8ebf-a92fad09623a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12233
94877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.1223394877
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.2661795370
Short name T2365
Test name
Test status
Simulation time 42615574 ps
CPU time 0.67 seconds
Started Jun 27 06:36:12 PM PDT 24
Finished Jun 27 06:36:16 PM PDT 24
Peak memory 206340 kb
Host smart-5bbbe479-e5c0-4e71-997a-2ff9cb10ffa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2661795370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.2661795370
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.1986736383
Short name T2491
Test name
Test status
Simulation time 3871621646 ps
CPU time 4.21 seconds
Started Jun 27 06:35:47 PM PDT 24
Finished Jun 27 06:35:55 PM PDT 24
Peak memory 206312 kb
Host smart-dc1528bc-b1e2-4236-85ba-ebbbb09bbc95
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1986736383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.1986736383
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.2616793749
Short name T710
Test name
Test status
Simulation time 13340574416 ps
CPU time 12.66 seconds
Started Jun 27 06:35:46 PM PDT 24
Finished Jun 27 06:36:02 PM PDT 24
Peak memory 206344 kb
Host smart-d6a10f24-fc87-4fec-b1c3-a7a7359f5c6e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2616793749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.2616793749
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.2825273255
Short name T1037
Test name
Test status
Simulation time 23327955684 ps
CPU time 23.25 seconds
Started Jun 27 06:35:48 PM PDT 24
Finished Jun 27 06:36:15 PM PDT 24
Peak memory 206340 kb
Host smart-5ecc328c-9cef-4690-9498-4ebe06615620
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2825273255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.2825273255
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.2641417299
Short name T1083
Test name
Test status
Simulation time 150471897 ps
CPU time 0.77 seconds
Started Jun 27 06:35:48 PM PDT 24
Finished Jun 27 06:35:53 PM PDT 24
Peak memory 206280 kb
Host smart-7270f393-a32d-4a27-ad06-87d71ac8d4b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26414
17299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.2641417299
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.2729506889
Short name T590
Test name
Test status
Simulation time 142392960 ps
CPU time 0.77 seconds
Started Jun 27 06:35:48 PM PDT 24
Finished Jun 27 06:35:52 PM PDT 24
Peak memory 206276 kb
Host smart-f9a7da18-3004-4b51-a5c3-bdb455acd40b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27295
06889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.2729506889
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.3330977814
Short name T2265
Test name
Test status
Simulation time 542195429 ps
CPU time 1.58 seconds
Started Jun 27 06:35:47 PM PDT 24
Finished Jun 27 06:35:53 PM PDT 24
Peak memory 206336 kb
Host smart-2e19790c-7619-41e9-9b93-fadbcdb17beb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33309
77814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.3330977814
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.872860634
Short name T1527
Test name
Test status
Simulation time 350050047 ps
CPU time 1.09 seconds
Started Jun 27 06:35:49 PM PDT 24
Finished Jun 27 06:35:54 PM PDT 24
Peak memory 206292 kb
Host smart-da8b6e8b-e3de-4bbb-bf9d-e97bfc7ae36a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87286
0634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.872860634
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.2698690614
Short name T156
Test name
Test status
Simulation time 14128315820 ps
CPU time 24.52 seconds
Started Jun 27 06:35:47 PM PDT 24
Finished Jun 27 06:36:15 PM PDT 24
Peak memory 206472 kb
Host smart-db807881-0c74-41ba-bce6-cf2d31bb79ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26986
90614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.2698690614
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.1704776518
Short name T2483
Test name
Test status
Simulation time 420814039 ps
CPU time 1.31 seconds
Started Jun 27 06:35:45 PM PDT 24
Finished Jun 27 06:35:47 PM PDT 24
Peak memory 206268 kb
Host smart-4d4d1e22-a79c-4a77-88e4-522fb0646b2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17047
76518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.1704776518
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.2355443429
Short name T1472
Test name
Test status
Simulation time 164410619 ps
CPU time 0.75 seconds
Started Jun 27 06:35:46 PM PDT 24
Finished Jun 27 06:35:51 PM PDT 24
Peak memory 206272 kb
Host smart-32cd4ff1-8524-4584-b4ca-4d6019064787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23554
43429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.2355443429
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.2929259830
Short name T851
Test name
Test status
Simulation time 55486020 ps
CPU time 0.69 seconds
Started Jun 27 06:35:48 PM PDT 24
Finished Jun 27 06:35:53 PM PDT 24
Peak memory 206268 kb
Host smart-65198fc7-b99a-4088-9e9e-623700e4f301
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29292
59830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.2929259830
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.608479103
Short name T612
Test name
Test status
Simulation time 845250143 ps
CPU time 2.01 seconds
Started Jun 27 06:35:48 PM PDT 24
Finished Jun 27 06:35:54 PM PDT 24
Peak memory 206392 kb
Host smart-52d7e51d-b2d5-4129-86fb-1c520b220053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60847
9103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.608479103
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.1765676820
Short name T2627
Test name
Test status
Simulation time 242232460 ps
CPU time 1.47 seconds
Started Jun 27 06:35:47 PM PDT 24
Finished Jun 27 06:35:52 PM PDT 24
Peak memory 206436 kb
Host smart-56d4371d-f6f9-440d-8dd2-8a65c22fb4b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17656
76820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.1765676820
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.790545637
Short name T1540
Test name
Test status
Simulation time 193907073 ps
CPU time 0.84 seconds
Started Jun 27 06:35:47 PM PDT 24
Finished Jun 27 06:35:52 PM PDT 24
Peak memory 206296 kb
Host smart-5aa37d80-ad8c-4a45-8a80-3fa4fb17211e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79054
5637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.790545637
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.1993017229
Short name T1580
Test name
Test status
Simulation time 157382726 ps
CPU time 0.77 seconds
Started Jun 27 06:35:48 PM PDT 24
Finished Jun 27 06:35:53 PM PDT 24
Peak memory 206292 kb
Host smart-16d426dd-eab9-49ee-942d-025fed553f08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19930
17229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.1993017229
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.3404847728
Short name T2118
Test name
Test status
Simulation time 167844329 ps
CPU time 0.85 seconds
Started Jun 27 06:35:46 PM PDT 24
Finished Jun 27 06:35:51 PM PDT 24
Peak memory 206288 kb
Host smart-18fb6626-d7f8-4b0f-862d-f015d9b5cdb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34048
47728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.3404847728
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.850575592
Short name T1558
Test name
Test status
Simulation time 251634055 ps
CPU time 0.85 seconds
Started Jun 27 06:35:53 PM PDT 24
Finished Jun 27 06:35:56 PM PDT 24
Peak memory 206248 kb
Host smart-a81778b2-4f6d-4e9e-85fb-68995cc0098d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85057
5592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.850575592
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.4253355618
Short name T1530
Test name
Test status
Simulation time 23310808064 ps
CPU time 22.43 seconds
Started Jun 27 06:35:51 PM PDT 24
Finished Jun 27 06:36:17 PM PDT 24
Peak memory 206340 kb
Host smart-611b3852-e251-45db-a5b1-9d31817952ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42533
55618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.4253355618
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.3869596567
Short name T765
Test name
Test status
Simulation time 3307743352 ps
CPU time 3.78 seconds
Started Jun 27 06:35:45 PM PDT 24
Finished Jun 27 06:35:52 PM PDT 24
Peak memory 206344 kb
Host smart-df8e1c93-1ef3-4b10-8724-aa12454fd8a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38695
96567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.3869596567
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.1975108865
Short name T895
Test name
Test status
Simulation time 9355906227 ps
CPU time 256.19 seconds
Started Jun 27 06:35:48 PM PDT 24
Finished Jun 27 06:40:08 PM PDT 24
Peak memory 206492 kb
Host smart-a5fdb29b-1aa8-4f7d-9b7f-f7579ef3f006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19751
08865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.1975108865
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.4049837138
Short name T2358
Test name
Test status
Simulation time 3779379533 ps
CPU time 101.69 seconds
Started Jun 27 06:35:50 PM PDT 24
Finished Jun 27 06:37:36 PM PDT 24
Peak memory 206440 kb
Host smart-02c12fab-d7a2-4211-9461-fc299a4fcbe5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4049837138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.4049837138
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.1574744880
Short name T2302
Test name
Test status
Simulation time 239885223 ps
CPU time 0.97 seconds
Started Jun 27 06:35:49 PM PDT 24
Finished Jun 27 06:35:54 PM PDT 24
Peak memory 206280 kb
Host smart-e6c0826d-8dbb-4fd0-9468-cab572bd1aab
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1574744880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.1574744880
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.2726617524
Short name T967
Test name
Test status
Simulation time 189091645 ps
CPU time 0.87 seconds
Started Jun 27 06:35:52 PM PDT 24
Finished Jun 27 06:35:56 PM PDT 24
Peak memory 206280 kb
Host smart-3da955f0-e194-4b64-a632-0d24d7e2da1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27266
17524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.2726617524
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.2282121689
Short name T1157
Test name
Test status
Simulation time 3246844151 ps
CPU time 89.27 seconds
Started Jun 27 06:35:47 PM PDT 24
Finished Jun 27 06:37:20 PM PDT 24
Peak memory 206400 kb
Host smart-17404540-a480-45bb-ac98-caa41b9acd13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22821
21689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.2282121689
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.791144160
Short name T2577
Test name
Test status
Simulation time 5415710069 ps
CPU time 152.74 seconds
Started Jun 27 06:35:47 PM PDT 24
Finished Jun 27 06:38:23 PM PDT 24
Peak memory 206400 kb
Host smart-12405c37-7097-4d41-8d61-292a0d7bee79
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=791144160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.791144160
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.3680638881
Short name T1464
Test name
Test status
Simulation time 158301959 ps
CPU time 0.76 seconds
Started Jun 27 06:35:53 PM PDT 24
Finished Jun 27 06:35:56 PM PDT 24
Peak memory 206292 kb
Host smart-b7a32ca4-d3e2-4f43-aa13-faa27dc397a9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3680638881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.3680638881
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.3972753884
Short name T1206
Test name
Test status
Simulation time 144636319 ps
CPU time 0.78 seconds
Started Jun 27 06:35:52 PM PDT 24
Finished Jun 27 06:35:56 PM PDT 24
Peak memory 206276 kb
Host smart-64c472bd-98c1-4ec4-ac63-5f0c3362c13e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39727
53884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.3972753884
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.275834570
Short name T1679
Test name
Test status
Simulation time 234571451 ps
CPU time 0.85 seconds
Started Jun 27 06:35:54 PM PDT 24
Finished Jun 27 06:35:57 PM PDT 24
Peak memory 206268 kb
Host smart-fe373d2d-96ca-45e7-8ff8-fdefdd7d31c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27583
4570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.275834570
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.4147723973
Short name T501
Test name
Test status
Simulation time 176268662 ps
CPU time 0.83 seconds
Started Jun 27 06:35:47 PM PDT 24
Finished Jun 27 06:35:51 PM PDT 24
Peak memory 206252 kb
Host smart-62090cb9-3e04-49a1-b135-749ad105288f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41477
23973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.4147723973
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.3456760580
Short name T565
Test name
Test status
Simulation time 169789866 ps
CPU time 0.78 seconds
Started Jun 27 06:35:53 PM PDT 24
Finished Jun 27 06:35:56 PM PDT 24
Peak memory 206272 kb
Host smart-141402e9-c5e5-4570-aace-c829678a0ab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34567
60580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.3456760580
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.986369137
Short name T2414
Test name
Test status
Simulation time 143306785 ps
CPU time 0.75 seconds
Started Jun 27 06:35:53 PM PDT 24
Finished Jun 27 06:35:56 PM PDT 24
Peak memory 206276 kb
Host smart-2d1c37f3-83cf-4729-a820-9a0c284443af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98636
9137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.986369137
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.1807068735
Short name T1413
Test name
Test status
Simulation time 173850348 ps
CPU time 0.81 seconds
Started Jun 27 06:35:52 PM PDT 24
Finished Jun 27 06:35:56 PM PDT 24
Peak memory 206292 kb
Host smart-315e2dfc-8c89-4fa5-a411-4b3698789a06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18070
68735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.1807068735
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.3326424980
Short name T659
Test name
Test status
Simulation time 228370318 ps
CPU time 0.92 seconds
Started Jun 27 06:35:47 PM PDT 24
Finished Jun 27 06:35:51 PM PDT 24
Peak memory 206300 kb
Host smart-379b842b-3416-415a-8737-86a3e6dc2da2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3326424980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.3326424980
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.1750806000
Short name T2295
Test name
Test status
Simulation time 148507459 ps
CPU time 0.75 seconds
Started Jun 27 06:35:50 PM PDT 24
Finished Jun 27 06:35:55 PM PDT 24
Peak memory 206268 kb
Host smart-7d5900f0-eec4-41c0-8be0-993beeedd344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17508
06000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.1750806000
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.3439771751
Short name T2628
Test name
Test status
Simulation time 49698168 ps
CPU time 0.7 seconds
Started Jun 27 06:35:54 PM PDT 24
Finished Jun 27 06:35:57 PM PDT 24
Peak memory 206248 kb
Host smart-b251eaec-d5a1-4450-b4a7-a45c2ab3fbe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34397
71751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.3439771751
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.50872965
Short name T1486
Test name
Test status
Simulation time 12780339823 ps
CPU time 28.39 seconds
Started Jun 27 06:35:48 PM PDT 24
Finished Jun 27 06:36:20 PM PDT 24
Peak memory 206512 kb
Host smart-bd0f5c1c-9979-41df-b325-4b462446cd80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50872
965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.50872965
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.2918937215
Short name T754
Test name
Test status
Simulation time 181535397 ps
CPU time 0.85 seconds
Started Jun 27 06:35:54 PM PDT 24
Finished Jun 27 06:35:57 PM PDT 24
Peak memory 206252 kb
Host smart-a2f8cba3-10ea-4ad4-aaa9-d5a3168c2a39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29189
37215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.2918937215
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.3357552894
Short name T1606
Test name
Test status
Simulation time 276508844 ps
CPU time 0.97 seconds
Started Jun 27 06:35:53 PM PDT 24
Finished Jun 27 06:35:57 PM PDT 24
Peak memory 206268 kb
Host smart-3e316b60-6309-404d-80fd-9f96f0d6223c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33575
52894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.3357552894
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.2720500248
Short name T1904
Test name
Test status
Simulation time 4844405504 ps
CPU time 128 seconds
Started Jun 27 06:35:53 PM PDT 24
Finished Jun 27 06:38:03 PM PDT 24
Peak memory 206412 kb
Host smart-82e59c87-958c-4a3c-9880-225729f81b87
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2720500248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.2720500248
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.1062239238
Short name T380
Test name
Test status
Simulation time 18341358405 ps
CPU time 396.94 seconds
Started Jun 27 06:35:46 PM PDT 24
Finished Jun 27 06:42:27 PM PDT 24
Peak memory 206416 kb
Host smart-551cc357-7caf-4df6-a518-83cd6a0267c9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1062239238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.1062239238
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.393149608
Short name T1644
Test name
Test status
Simulation time 245700205 ps
CPU time 0.91 seconds
Started Jun 27 06:35:48 PM PDT 24
Finished Jun 27 06:35:53 PM PDT 24
Peak memory 206284 kb
Host smart-f215852a-00d3-475e-81cc-295a82617f04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39314
9608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.393149608
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.4115450101
Short name T795
Test name
Test status
Simulation time 190559981 ps
CPU time 0.85 seconds
Started Jun 27 06:35:53 PM PDT 24
Finished Jun 27 06:35:56 PM PDT 24
Peak memory 206252 kb
Host smart-de1b8a22-44ef-4c11-8bd2-5ab113955279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41154
50101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.4115450101
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.3245416502
Short name T1180
Test name
Test status
Simulation time 141044023 ps
CPU time 0.74 seconds
Started Jun 27 06:36:06 PM PDT 24
Finished Jun 27 06:36:09 PM PDT 24
Peak memory 206304 kb
Host smart-1bb03f20-47d0-4117-a724-fa093001bed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32454
16502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.3245416502
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.1710504507
Short name T679
Test name
Test status
Simulation time 201836435 ps
CPU time 0.82 seconds
Started Jun 27 06:36:12 PM PDT 24
Finished Jun 27 06:36:16 PM PDT 24
Peak memory 206256 kb
Host smart-38087d20-1bef-4d87-96ca-e25ed0629f55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17105
04507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.1710504507
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.2057342483
Short name T1116
Test name
Test status
Simulation time 170439815 ps
CPU time 0.78 seconds
Started Jun 27 06:36:11 PM PDT 24
Finished Jun 27 06:36:15 PM PDT 24
Peak memory 206296 kb
Host smart-c65e201d-121b-40c4-907a-6ae8d8a16b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20573
42483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.2057342483
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.1717791182
Short name T484
Test name
Test status
Simulation time 224022339 ps
CPU time 0.94 seconds
Started Jun 27 06:36:10 PM PDT 24
Finished Jun 27 06:36:15 PM PDT 24
Peak memory 206292 kb
Host smart-ee92b5f4-3845-45e3-9100-61c2c335095b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17177
91182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.1717791182
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.2407135784
Short name T356
Test name
Test status
Simulation time 6256724048 ps
CPU time 175.29 seconds
Started Jun 27 06:36:09 PM PDT 24
Finished Jun 27 06:39:08 PM PDT 24
Peak memory 206456 kb
Host smart-7030b64b-8b71-4be9-9dbb-7d64b84cc66e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2407135784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.2407135784
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.2707894063
Short name T1865
Test name
Test status
Simulation time 167768255 ps
CPU time 0.87 seconds
Started Jun 27 06:36:11 PM PDT 24
Finished Jun 27 06:36:15 PM PDT 24
Peak memory 206196 kb
Host smart-aa8d7158-1d74-49d1-8a10-8ab1b49a2b24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27078
94063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.2707894063
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.2431545764
Short name T1785
Test name
Test status
Simulation time 159109856 ps
CPU time 0.81 seconds
Started Jun 27 06:36:12 PM PDT 24
Finished Jun 27 06:36:15 PM PDT 24
Peak memory 206260 kb
Host smart-e669e88a-6eb9-4c93-90a6-d4e294c2479d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24315
45764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.2431545764
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.1238744998
Short name T872
Test name
Test status
Simulation time 6268164776 ps
CPU time 167.15 seconds
Started Jun 27 06:36:12 PM PDT 24
Finished Jun 27 06:39:02 PM PDT 24
Peak memory 206400 kb
Host smart-713c2870-8da1-40cd-8a0a-8c65c27e208b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12387
44998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.1238744998
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.3027894545
Short name T1057
Test name
Test status
Simulation time 47322482 ps
CPU time 0.68 seconds
Started Jun 27 06:36:01 PM PDT 24
Finished Jun 27 06:36:03 PM PDT 24
Peak memory 206488 kb
Host smart-b0918540-92c9-45dc-b7cd-a7b763bdbcf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3027894545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.3027894545
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.224261235
Short name T2311
Test name
Test status
Simulation time 3612657497 ps
CPU time 4.46 seconds
Started Jun 27 06:36:06 PM PDT 24
Finished Jun 27 06:36:13 PM PDT 24
Peak memory 206388 kb
Host smart-43305bba-a2b1-439a-82d3-8ccb6d9b34fe
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=224261235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.224261235
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.4263517891
Short name T1849
Test name
Test status
Simulation time 13496193603 ps
CPU time 12.82 seconds
Started Jun 27 06:36:10 PM PDT 24
Finished Jun 27 06:36:26 PM PDT 24
Peak memory 206496 kb
Host smart-27b25cef-b91b-403d-a127-8e792e23bb31
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4263517891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.4263517891
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.3337381852
Short name T2093
Test name
Test status
Simulation time 23416910062 ps
CPU time 22.69 seconds
Started Jun 27 06:36:08 PM PDT 24
Finished Jun 27 06:36:35 PM PDT 24
Peak memory 206156 kb
Host smart-74640b75-74a0-42be-adb1-56ed5d1f98d5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3337381852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.3337381852
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.2516607094
Short name T635
Test name
Test status
Simulation time 185046470 ps
CPU time 0.8 seconds
Started Jun 27 06:36:04 PM PDT 24
Finished Jun 27 06:36:07 PM PDT 24
Peak memory 206288 kb
Host smart-35be53f8-a555-46e6-aee3-a79512a8f008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25166
07094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.2516607094
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.1868472297
Short name T1935
Test name
Test status
Simulation time 153435335 ps
CPU time 0.78 seconds
Started Jun 27 06:36:05 PM PDT 24
Finished Jun 27 06:36:08 PM PDT 24
Peak memory 206288 kb
Host smart-3f150d32-2e42-43fd-98cc-9d3b9e23021f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18684
72297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.1868472297
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.1608490026
Short name T496
Test name
Test status
Simulation time 242992576 ps
CPU time 0.94 seconds
Started Jun 27 06:36:05 PM PDT 24
Finished Jun 27 06:36:09 PM PDT 24
Peak memory 206268 kb
Host smart-66e8095b-983e-4f3e-b9a2-c1881b3bcd61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16084
90026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.1608490026
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.768460010
Short name T683
Test name
Test status
Simulation time 608795389 ps
CPU time 1.64 seconds
Started Jun 27 06:36:10 PM PDT 24
Finished Jun 27 06:36:16 PM PDT 24
Peak memory 206296 kb
Host smart-0b8fbd33-f3dc-4552-9bd7-70dfe0a08585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76846
0010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.768460010
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.1213396880
Short name T1999
Test name
Test status
Simulation time 6040110766 ps
CPU time 14.05 seconds
Started Jun 27 06:36:06 PM PDT 24
Finished Jun 27 06:36:23 PM PDT 24
Peak memory 206424 kb
Host smart-cb0e1a06-af15-40d4-bf80-f17c58165f77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12133
96880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.1213396880
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.1985099928
Short name T1027
Test name
Test status
Simulation time 441855516 ps
CPU time 1.44 seconds
Started Jun 27 06:36:03 PM PDT 24
Finished Jun 27 06:36:07 PM PDT 24
Peak memory 206288 kb
Host smart-4eaa571a-c6ff-4423-ab1f-12c320df8c5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19850
99928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.1985099928
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.26128818
Short name T2239
Test name
Test status
Simulation time 147856903 ps
CPU time 0.79 seconds
Started Jun 27 06:36:03 PM PDT 24
Finished Jun 27 06:36:06 PM PDT 24
Peak memory 206248 kb
Host smart-9a780fd4-3d0b-4faf-8833-7f770efcca6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26128
818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.26128818
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.3650866167
Short name T1942
Test name
Test status
Simulation time 38349865 ps
CPU time 0.63 seconds
Started Jun 27 06:36:00 PM PDT 24
Finished Jun 27 06:36:02 PM PDT 24
Peak memory 206276 kb
Host smart-2467287d-4f1a-49b4-9f31-300b5c9d845b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36508
66167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.3650866167
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.2297520153
Short name T1729
Test name
Test status
Simulation time 924441639 ps
CPU time 2.15 seconds
Started Jun 27 06:36:03 PM PDT 24
Finished Jun 27 06:36:08 PM PDT 24
Peak memory 206444 kb
Host smart-c5c488af-1e03-4abf-9744-b170ef2354f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22975
20153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.2297520153
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.3486611270
Short name T1454
Test name
Test status
Simulation time 160917375 ps
CPU time 1.44 seconds
Started Jun 27 06:36:00 PM PDT 24
Finished Jun 27 06:36:03 PM PDT 24
Peak memory 206436 kb
Host smart-736f8fd5-13e8-43c2-9fbb-8ae802e94fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34866
11270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.3486611270
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.925806925
Short name T2177
Test name
Test status
Simulation time 171312880 ps
CPU time 0.79 seconds
Started Jun 27 06:36:03 PM PDT 24
Finished Jun 27 06:36:06 PM PDT 24
Peak memory 206284 kb
Host smart-10545e0f-4b7e-426d-87f1-5ebed85e3d53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92580
6925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.925806925
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.3435656101
Short name T925
Test name
Test status
Simulation time 148309007 ps
CPU time 0.76 seconds
Started Jun 27 06:36:00 PM PDT 24
Finished Jun 27 06:36:02 PM PDT 24
Peak memory 206292 kb
Host smart-be13005b-25ff-46bf-8b54-3f07caa1704b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34356
56101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.3435656101
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.3838710019
Short name T493
Test name
Test status
Simulation time 249979139 ps
CPU time 1.05 seconds
Started Jun 27 06:36:05 PM PDT 24
Finished Jun 27 06:36:09 PM PDT 24
Peak memory 206288 kb
Host smart-91f5526d-e325-4983-b496-cb861ef8af80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38387
10019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.3838710019
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_invalid_sync.718069409
Short name T788
Test name
Test status
Simulation time 7237666522 ps
CPU time 68.39 seconds
Started Jun 27 06:36:05 PM PDT 24
Finished Jun 27 06:37:15 PM PDT 24
Peak memory 206516 kb
Host smart-834b960c-41a5-4ef6-8d65-77f56245b6da
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=718069409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.718069409
Directory /workspace/9.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.2481556617
Short name T1090
Test name
Test status
Simulation time 241608893 ps
CPU time 0.98 seconds
Started Jun 27 06:36:02 PM PDT 24
Finished Jun 27 06:36:05 PM PDT 24
Peak memory 206248 kb
Host smart-37e9267c-db06-4b1c-b460-e3aa1316456a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24815
56617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.2481556617
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.3432724560
Short name T1362
Test name
Test status
Simulation time 23286709012 ps
CPU time 23.91 seconds
Started Jun 27 06:36:05 PM PDT 24
Finished Jun 27 06:36:32 PM PDT 24
Peak memory 206320 kb
Host smart-8a1f016b-9c0e-49dc-879b-aa67f9037b54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34327
24560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.3432724560
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.102493103
Short name T632
Test name
Test status
Simulation time 3291557535 ps
CPU time 4.37 seconds
Started Jun 27 06:36:06 PM PDT 24
Finished Jun 27 06:36:13 PM PDT 24
Peak memory 206320 kb
Host smart-f8cc99de-0e62-432b-8341-140db2539a32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10249
3103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.102493103
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.470914327
Short name T723
Test name
Test status
Simulation time 8469902002 ps
CPU time 218.42 seconds
Started Jun 27 06:36:05 PM PDT 24
Finished Jun 27 06:39:46 PM PDT 24
Peak memory 206488 kb
Host smart-479f26ea-85f3-45fc-ac89-a190298e44bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47091
4327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.470914327
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.2659145842
Short name T2290
Test name
Test status
Simulation time 5569367114 ps
CPU time 158.38 seconds
Started Jun 27 06:36:03 PM PDT 24
Finished Jun 27 06:38:43 PM PDT 24
Peak memory 206388 kb
Host smart-369273ae-28ac-4c4d-9282-1fb88eadfb2b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2659145842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.2659145842
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.2336203093
Short name T1244
Test name
Test status
Simulation time 230633950 ps
CPU time 0.9 seconds
Started Jun 27 06:36:06 PM PDT 24
Finished Jun 27 06:36:10 PM PDT 24
Peak memory 206292 kb
Host smart-84aa1a99-542f-474b-b2a9-4465d3f61567
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2336203093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.2336203093
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.2197832023
Short name T408
Test name
Test status
Simulation time 193785990 ps
CPU time 0.82 seconds
Started Jun 27 06:36:06 PM PDT 24
Finished Jun 27 06:36:11 PM PDT 24
Peak memory 206276 kb
Host smart-648c3729-cf0e-4cee-8c39-7f2ae95e03a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21978
32023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.2197832023
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.3563375692
Short name T1077
Test name
Test status
Simulation time 3521652921 ps
CPU time 33.01 seconds
Started Jun 27 06:36:05 PM PDT 24
Finished Jun 27 06:36:40 PM PDT 24
Peak memory 206444 kb
Host smart-0bb33058-8948-48f3-a02c-a92db7261a37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35633
75692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.3563375692
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.1386798288
Short name T1253
Test name
Test status
Simulation time 5045318947 ps
CPU time 34.53 seconds
Started Jun 27 06:36:04 PM PDT 24
Finished Jun 27 06:36:41 PM PDT 24
Peak memory 206492 kb
Host smart-b308cdd3-0388-4f11-8134-00608247fb23
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1386798288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.1386798288
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.4205113358
Short name T976
Test name
Test status
Simulation time 157303247 ps
CPU time 0.76 seconds
Started Jun 27 06:36:06 PM PDT 24
Finished Jun 27 06:36:10 PM PDT 24
Peak memory 206068 kb
Host smart-94242736-aa9a-4601-99ed-d4d7bef11eb1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4205113358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.4205113358
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.4120912989
Short name T775
Test name
Test status
Simulation time 191195023 ps
CPU time 0.83 seconds
Started Jun 27 06:36:08 PM PDT 24
Finished Jun 27 06:36:13 PM PDT 24
Peak memory 206256 kb
Host smart-1621d988-ed4e-4ccb-a042-90eac2005144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41209
12989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.4120912989
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.390582597
Short name T30
Test name
Test status
Simulation time 259229283 ps
CPU time 0.9 seconds
Started Jun 27 06:36:01 PM PDT 24
Finished Jun 27 06:36:04 PM PDT 24
Peak memory 206264 kb
Host smart-4e01537e-5cbc-47c4-9536-07e69a7b2b92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39058
2597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.390582597
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.9234193
Short name T99
Test name
Test status
Simulation time 169789788 ps
CPU time 0.83 seconds
Started Jun 27 06:36:07 PM PDT 24
Finished Jun 27 06:36:12 PM PDT 24
Peak memory 206276 kb
Host smart-b13c6ff5-37b6-48f0-8979-55cc48044e25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92341
93 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.9234193
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.3210243752
Short name T1150
Test name
Test status
Simulation time 179994270 ps
CPU time 0.8 seconds
Started Jun 27 06:36:06 PM PDT 24
Finished Jun 27 06:36:10 PM PDT 24
Peak memory 206264 kb
Host smart-4b874350-5e29-449e-bb26-6c532e5dacec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32102
43752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.3210243752
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.1072376615
Short name T1239
Test name
Test status
Simulation time 150923980 ps
CPU time 0.76 seconds
Started Jun 27 06:36:16 PM PDT 24
Finished Jun 27 06:36:18 PM PDT 24
Peak memory 206256 kb
Host smart-503476f9-67e9-4d84-9365-8343d48039db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10723
76615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.1072376615
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.4193488961
Short name T1741
Test name
Test status
Simulation time 187766724 ps
CPU time 0.82 seconds
Started Jun 27 06:36:10 PM PDT 24
Finished Jun 27 06:36:15 PM PDT 24
Peak memory 206300 kb
Host smart-6cb38679-21b4-47f5-857e-3a68e686196e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41934
88961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.4193488961
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.1947912072
Short name T1893
Test name
Test status
Simulation time 212934131 ps
CPU time 0.9 seconds
Started Jun 27 06:36:16 PM PDT 24
Finished Jun 27 06:36:18 PM PDT 24
Peak memory 206264 kb
Host smart-008e1b95-230c-4356-b22d-5d5f8e7690f2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1947912072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.1947912072
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.949850237
Short name T2355
Test name
Test status
Simulation time 145607522 ps
CPU time 0.74 seconds
Started Jun 27 06:36:09 PM PDT 24
Finished Jun 27 06:36:14 PM PDT 24
Peak memory 206272 kb
Host smart-ea2fdac9-beb4-4ef5-874a-1ff3428f3bd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94985
0237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.949850237
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.1793227130
Short name T1816
Test name
Test status
Simulation time 55715803 ps
CPU time 0.65 seconds
Started Jun 27 06:36:08 PM PDT 24
Finished Jun 27 06:36:13 PM PDT 24
Peak memory 206264 kb
Host smart-0f629e6d-97fa-478f-a135-074bae54f88f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17932
27130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.1793227130
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.2150749496
Short name T1465
Test name
Test status
Simulation time 12415694559 ps
CPU time 27.29 seconds
Started Jun 27 06:36:12 PM PDT 24
Finished Jun 27 06:36:42 PM PDT 24
Peak memory 206444 kb
Host smart-adc645aa-de5e-4641-a068-619c01189646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21507
49496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.2150749496
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.3299718453
Short name T1735
Test name
Test status
Simulation time 195724439 ps
CPU time 0.85 seconds
Started Jun 27 06:36:07 PM PDT 24
Finished Jun 27 06:36:11 PM PDT 24
Peak memory 206300 kb
Host smart-2a430a89-a351-43f1-9216-22c70a2d2849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32997
18453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.3299718453
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.896046092
Short name T954
Test name
Test status
Simulation time 237019402 ps
CPU time 0.92 seconds
Started Jun 27 06:36:07 PM PDT 24
Finished Jun 27 06:36:12 PM PDT 24
Peak memory 206312 kb
Host smart-e321035e-6f46-4ecb-870d-b61fa19e4dd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89604
6092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.896046092
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.2088293463
Short name T149
Test name
Test status
Simulation time 4630023851 ps
CPU time 114.16 seconds
Started Jun 27 06:36:12 PM PDT 24
Finished Jun 27 06:38:09 PM PDT 24
Peak memory 206408 kb
Host smart-a6b6d3b0-f7a5-4a5b-bc05-12c4a672b61a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2088293463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.2088293463
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.3186060727
Short name T155
Test name
Test status
Simulation time 4325812126 ps
CPU time 29.26 seconds
Started Jun 27 06:36:05 PM PDT 24
Finished Jun 27 06:36:36 PM PDT 24
Peak memory 206472 kb
Host smart-72b7b378-570e-47bd-a802-476e68d14bb5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3186060727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.3186060727
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.1117131224
Short name T660
Test name
Test status
Simulation time 8090232182 ps
CPU time 131.87 seconds
Started Jun 27 06:36:10 PM PDT 24
Finished Jun 27 06:38:26 PM PDT 24
Peak memory 206420 kb
Host smart-7bf11459-2644-44cc-8d8e-73cb4aacfabd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1117131224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.1117131224
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.3827784150
Short name T1122
Test name
Test status
Simulation time 196462805 ps
CPU time 0.81 seconds
Started Jun 27 06:36:16 PM PDT 24
Finished Jun 27 06:36:18 PM PDT 24
Peak memory 206264 kb
Host smart-f26f3d1e-96d8-4e78-929f-bb2b56201447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38277
84150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.3827784150
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.3966992372
Short name T1803
Test name
Test status
Simulation time 181901846 ps
CPU time 0.81 seconds
Started Jun 27 06:36:08 PM PDT 24
Finished Jun 27 06:36:13 PM PDT 24
Peak memory 206160 kb
Host smart-60e4acc2-d763-49a2-864c-657cf4c7c210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39669
92372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.3966992372
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.1357945751
Short name T2553
Test name
Test status
Simulation time 146116319 ps
CPU time 0.71 seconds
Started Jun 27 06:36:11 PM PDT 24
Finished Jun 27 06:36:15 PM PDT 24
Peak memory 206260 kb
Host smart-db77d0f2-67ce-4e7e-be7f-761fe77cbbd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13579
45751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.1357945751
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.401517566
Short name T367
Test name
Test status
Simulation time 158885130 ps
CPU time 0.8 seconds
Started Jun 27 06:36:06 PM PDT 24
Finished Jun 27 06:36:10 PM PDT 24
Peak memory 206244 kb
Host smart-43ee7e05-acab-477d-b727-953c5cee2b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40151
7566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.401517566
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.2408323025
Short name T670
Test name
Test status
Simulation time 157977747 ps
CPU time 0.78 seconds
Started Jun 27 06:36:11 PM PDT 24
Finished Jun 27 06:36:15 PM PDT 24
Peak memory 206276 kb
Host smart-46159153-453b-4fa8-abf4-d784bec5feda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24083
23025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.2408323025
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.1390678005
Short name T721
Test name
Test status
Simulation time 213718496 ps
CPU time 0.98 seconds
Started Jun 27 06:36:06 PM PDT 24
Finished Jun 27 06:36:09 PM PDT 24
Peak memory 206184 kb
Host smart-001db099-9bf4-4d66-a24d-9fdc5d3c8183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13906
78005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.1390678005
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.2958676658
Short name T1335
Test name
Test status
Simulation time 5565349093 ps
CPU time 51.29 seconds
Started Jun 27 06:36:03 PM PDT 24
Finished Jun 27 06:36:56 PM PDT 24
Peak memory 206484 kb
Host smart-8e21c687-742d-4dbc-b983-7ff74dc62793
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2958676658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.2958676658
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.3873612470
Short name T357
Test name
Test status
Simulation time 199129077 ps
CPU time 0.85 seconds
Started Jun 27 06:36:05 PM PDT 24
Finished Jun 27 06:36:08 PM PDT 24
Peak memory 206276 kb
Host smart-4a51f215-6410-452e-9213-922279fc4d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38736
12470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.3873612470
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.2137378781
Short name T1593
Test name
Test status
Simulation time 145765193 ps
CPU time 0.81 seconds
Started Jun 27 06:36:02 PM PDT 24
Finished Jun 27 06:36:05 PM PDT 24
Peak memory 206276 kb
Host smart-ef747b30-dbe4-43a5-9117-2051ad5ecf26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21373
78781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.2137378781
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.2937846932
Short name T1777
Test name
Test status
Simulation time 3206739077 ps
CPU time 88.6 seconds
Started Jun 27 06:35:59 PM PDT 24
Finished Jun 27 06:37:29 PM PDT 24
Peak memory 206416 kb
Host smart-73340cb4-ee27-411a-aa3c-2d3fed8b9134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29378
46932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.2937846932
Directory /workspace/9.usbdev_streaming_out/latest
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