Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	120527	1		T1	3		T2	2		T3	2
all_values[1]	120527	1		T1	3		T2	2		T3	2
all_values[2]	120527	1		T1	3		T2	2		T3	2
all_values[3]	120527	1		T1	3		T2	2		T3	2
all_values[4]	120527	1		T1	3		T2	2		T3	2
all_values[5]	120527	1		T1	3		T2	2		T3	2
all_values[6]	120527	1		T1	3		T2	2		T3	2
all_values[7]	120527	1		T1	3		T2	2		T3	2
all_values[8]	120527	1		T1	3		T2	2		T3	2
all_values[9]	120527	1		T1	3		T2	2		T3	2
all_values[10]	120527	1		T1	3		T2	2		T3	2
all_values[11]	120527	1		T1	3		T2	2		T3	2
all_values[12]	120527	1		T1	3		T2	2		T3	2
all_values[13]	120527	1		T1	3		T2	2		T3	2
all_values[14]	120527	1		T1	3		T2	2		T3	2
all_values[15]	120527	1		T1	3		T2	2		T3	2
all_values[16]	120527	1		T1	3		T2	2		T3	2
all_values[17]	120527	1		T1	3		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2162487	1		T1	54		T2	36		T3	36
auto[1]	6999	1		T27	3		T29	3		T6	2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2164286	1		T1	54		T2	36		T3	36
auto[1]	5200	1		T210	130		T211	136		T212	76

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	119542	1		T1	3		T2	2		T3	2
all_values[0]	auto[0]	auto[1]	150	1		T210	1		T213	1		T296	2
all_values[0]	auto[1]	auto[0]	698	1		T29	3		T22	3		T41	3
all_values[0]	auto[1]	auto[1]	137	1		T210	7		T211	4		T212	4
all_values[1]	auto[0]	auto[0]	118708	1		T1	3		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	149	1		T210	3		T211	4		T213	2
all_values[1]	auto[1]	auto[0]	1522	1		T27	3		T6	2		T16	2
all_values[1]	auto[1]	auto[1]	148	1		T210	5		T211	4		T212	3
all_values[2]	auto[0]	auto[0]	120110	1		T1	3		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	132	1		T210	3		T211	4		T212	1
all_values[2]	auto[1]	auto[0]	132	1		T21	2		T35	2		T36	2
all_values[2]	auto[1]	auto[1]	153	1		T210	4		T211	4		T212	3
all_values[3]	auto[0]	auto[0]	118828	1		T1	3		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	132	1		T210	6		T211	1		T212	1
all_values[3]	auto[1]	auto[0]	1428	1		T60	1394		T213	1		T296	2
all_values[3]	auto[1]	auto[1]	139	1		T210	2		T211	6		T212	4
all_values[4]	auto[0]	auto[0]	120223	1		T1	3		T2	2		T3	2
all_values[4]	auto[0]	auto[1]	138	1		T210	7		T211	1		T212	5
all_values[4]	auto[1]	auto[0]	23	1		T61	2		T297	5		T298	1
all_values[4]	auto[1]	auto[1]	143	1		T210	1		T211	7		T213	4
all_values[5]	auto[0]	auto[0]	120207	1		T1	3		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	151	1		T210	3		T211	6		T296	3
all_values[5]	auto[1]	auto[0]	29	1		T212	1		T213	5		T296	1
all_values[5]	auto[1]	auto[1]	140	1		T210	4		T211	2		T212	3
all_values[6]	auto[0]	auto[0]	120205	1		T1	3		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	151	1		T210	4		T211	3		T213	3
all_values[6]	auto[1]	auto[0]	23	1		T212	1		T299	2		T298	1
all_values[6]	auto[1]	auto[1]	148	1		T210	4		T211	3		T212	4
all_values[7]	auto[0]	auto[0]	120201	1		T1	3		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	142	1		T210	2		T211	2		T212	4
all_values[7]	auto[1]	auto[0]	21	1		T43	2		T44	2		T210	2
all_values[7]	auto[1]	auto[1]	163	1		T210	4		T211	5		T212	1
all_values[8]	auto[0]	auto[0]	120203	1		T1	3		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	168	1		T210	5		T211	7		T212	1
all_values[8]	auto[1]	auto[0]	35	1		T48	11		T210	1		T300	1
all_values[8]	auto[1]	auto[1]	121	1		T210	2		T211	1		T212	4
all_values[9]	auto[0]	auto[0]	120191	1		T1	3		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	142	1		T210	4		T211	5		T212	1
all_values[9]	auto[1]	auto[0]	53	1		T57	5		T58	5		T59	5
all_values[9]	auto[1]	auto[1]	141	1		T210	2		T211	3		T212	3
all_values[10]	auto[0]	auto[0]	120210	1		T1	3		T2	2		T3	2
all_values[10]	auto[0]	auto[1]	140	1		T210	2		T211	7		T212	3
all_values[10]	auto[1]	auto[0]	27	1		T299	2		T297	1		T301	1
all_values[10]	auto[1]	auto[1]	150	1		T210	6		T211	1		T212	2
all_values[11]	auto[0]	auto[0]	120114	1		T1	3		T2	2		T3	2
all_values[11]	auto[0]	auto[1]	123	1		T210	1		T211	3		T212	4
all_values[11]	auto[1]	auto[0]	134	1		T67	2		T68	2		T69	2
all_values[11]	auto[1]	auto[1]	156	1		T210	7		T211	5		T212	1
all_values[12]	auto[0]	auto[0]	120206	1		T1	3		T2	2		T3	2
all_values[12]	auto[0]	auto[1]	125	1		T210	3		T211	2		T212	4
all_values[12]	auto[1]	auto[0]	37	1		T71	3		T72	3		T73	3
all_values[12]	auto[1]	auto[1]	159	1		T210	3		T211	6		T212	1
all_values[13]	auto[0]	auto[0]	120210	1		T1	3		T2	2		T3	2
all_values[13]	auto[0]	auto[1]	142	1		T210	5		T211	6		T213	3
all_values[13]	auto[1]	auto[0]	28	1		T212	4		T213	1		T300	1
all_values[13]	auto[1]	auto[1]	147	1		T210	3		T211	2		T213	1
all_values[14]	auto[0]	auto[0]	120207	1		T1	3		T2	2		T3	2
all_values[14]	auto[0]	auto[1]	130	1		T210	3		T211	1		T212	4
all_values[14]	auto[1]	auto[0]	20	1		T210	1		T296	1		T292	1
all_values[14]	auto[1]	auto[1]	170	1		T210	4		T211	7		T212	1
all_values[15]	auto[0]	auto[0]	120214	1		T1	3		T2	2		T3	2
all_values[15]	auto[0]	auto[1]	132	1		T210	4		T211	2		T296	3
all_values[15]	auto[1]	auto[0]	20	1		T210	1		T213	1		T299	1
all_values[15]	auto[1]	auto[1]	161	1		T210	2		T211	6		T212	5
all_values[16]	auto[0]	auto[0]	120190	1		T1	3		T2	2		T3	2
all_values[16]	auto[0]	auto[1]	136	1		T210	2		T211	6		T212	3
all_values[16]	auto[1]	auto[0]	50	1		T40	8		T64	8		T65	8
all_values[16]	auto[1]	auto[1]	151	1		T210	5		T211	2		T212	1
all_values[17]	auto[0]	auto[0]	120204	1		T1	3		T2	2		T3	2
all_values[17]	auto[0]	auto[1]	131	1		T210	2		T211	5		T212	4
all_values[17]	auto[1]	auto[0]	33	1		T49	2		T50	2		T51	2
all_values[17]	auto[1]	auto[1]	159	1		T210	5		T211	3		T212	1