Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	120527	1		T1	3		T2	2		T3	2
all_pins[1]	120527	1		T1	3		T2	2		T3	2
all_pins[2]	120527	1		T1	3		T2	2		T3	2
all_pins[3]	120527	1		T1	3		T2	2		T3	2
all_pins[4]	120527	1		T1	3		T2	2		T3	2
all_pins[5]	120527	1		T1	3		T2	2		T3	2
all_pins[6]	120527	1		T1	3		T2	2		T3	2
all_pins[7]	120527	1		T1	3		T2	2		T3	2
all_pins[8]	120527	1		T1	3		T2	2		T3	2
all_pins[9]	120527	1		T1	3		T2	2		T3	2
all_pins[10]	120527	1		T1	3		T2	2		T3	2
all_pins[11]	120527	1		T1	3		T2	2		T3	2
all_pins[12]	120527	1		T1	3		T2	2		T3	2
all_pins[13]	120527	1		T1	3		T2	2		T3	2
all_pins[14]	120527	1		T1	3		T2	2		T3	2
all_pins[15]	120527	1		T1	3		T2	2		T3	2
all_pins[16]	120527	1		T1	3		T2	2		T3	2
all_pins[17]	120527	1		T1	3		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2167118	1		T1	54		T2	36		T3	36
values[0x1]	2368	1		T27	1		T6	1		T16	1
transitions[0x0=>0x1]	2024	1		T27	1		T6	1		T16	1
transitions[0x1=>0x0]	2039	1		T27	1		T6	1		T16	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	120420	1		T1	3		T2	2		T3	2
all_pins[0]	values[0x1]	107	1		T302	1		T303	1		T304	1
all_pins[0]	transitions[0x0=>0x1]	89	1		T302	1		T303	1		T304	1
all_pins[0]	transitions[0x1=>0x0]	992	1		T27	1		T6	1		T16	1
all_pins[1]	values[0x0]	119517	1		T1	3		T2	2		T3	2
all_pins[1]	values[0x1]	1010	1		T27	1		T6	1		T16	1
all_pins[1]	transitions[0x0=>0x1]	994	1		T27	1		T6	1		T16	1
all_pins[1]	transitions[0x1=>0x0]	112	1		T21	1		T35	1		T36	1
all_pins[2]	values[0x0]	120399	1		T1	3		T2	2		T3	2
all_pins[2]	values[0x1]	128	1		T21	1		T35	1		T36	1
all_pins[2]	transitions[0x0=>0x1]	105	1		T21	1		T35	1		T36	1
all_pins[2]	transitions[0x1=>0x0]	38	1		T60	1		T210	1		T211	3
all_pins[3]	values[0x0]	120466	1		T1	3		T2	2		T3	2
all_pins[3]	values[0x1]	61	1		T60	1		T210	1		T211	4
all_pins[3]	transitions[0x0=>0x1]	52	1		T60	1		T210	1		T211	3
all_pins[3]	transitions[0x1=>0x0]	52	1		T61	1		T211	1		T296	2
all_pins[4]	values[0x0]	120466	1		T1	3		T2	2		T3	2
all_pins[4]	values[0x1]	61	1		T61	1		T211	2		T296	2
all_pins[4]	transitions[0x0=>0x1]	42	1		T61	1		T211	1		T296	2
all_pins[4]	transitions[0x1=>0x0]	50	1		T211	1		T212	2		T296	1
all_pins[5]	values[0x0]	120458	1		T1	3		T2	2		T3	2
all_pins[5]	values[0x1]	69	1		T211	2		T212	2		T296	1
all_pins[5]	transitions[0x0=>0x1]	52	1		T211	1		T296	1		T299	2
all_pins[5]	transitions[0x1=>0x0]	51	1		T210	2		T212	1		T213	1
all_pins[6]	values[0x0]	120459	1		T1	3		T2	2		T3	2
all_pins[6]	values[0x1]	68	1		T210	2		T211	1		T212	3
all_pins[6]	transitions[0x0=>0x1]	53	1		T210	2		T211	1		T212	3
all_pins[6]	transitions[0x1=>0x0]	52	1		T43	1		T44	1		T210	2
all_pins[7]	values[0x0]	120460	1		T1	3		T2	2		T3	2
all_pins[7]	values[0x1]	67	1		T43	1		T44	1		T210	2
all_pins[7]	transitions[0x0=>0x1]	57	1		T43	1		T44	1		T210	2
all_pins[7]	transitions[0x1=>0x0]	40	1		T48	1		T210	1		T212	1
all_pins[8]	values[0x0]	120477	1		T1	3		T2	2		T3	2
all_pins[8]	values[0x1]	50	1		T48	1		T210	1		T211	1
all_pins[8]	transitions[0x0=>0x1]	34	1		T48	1		T211	1		T212	1
all_pins[8]	transitions[0x1=>0x0]	59	1		T57	2		T58	2		T59	2
all_pins[9]	values[0x0]	120452	1		T1	3		T2	2		T3	2
all_pins[9]	values[0x1]	75	1		T57	2		T58	2		T59	2
all_pins[9]	transitions[0x0=>0x1]	59	1		T57	2		T58	2		T59	2
all_pins[9]	transitions[0x1=>0x0]	62	1		T210	4		T213	2		T296	3
all_pins[10]	values[0x0]	120449	1		T1	3		T2	2		T3	2
all_pins[10]	values[0x1]	78	1		T210	5		T211	1		T213	3
all_pins[10]	transitions[0x0=>0x1]	61	1		T210	4		T211	1		T296	3
all_pins[10]	transitions[0x1=>0x0]	104	1		T67	1		T68	1		T69	1
all_pins[11]	values[0x0]	120406	1		T1	3		T2	2		T3	2
all_pins[11]	values[0x1]	121	1		T67	1		T68	1		T69	1
all_pins[11]	transitions[0x0=>0x1]	99	1		T67	1		T68	1		T69	1
all_pins[11]	transitions[0x1=>0x0]	63	1		T71	1		T72	1		T73	1
all_pins[12]	values[0x0]	120442	1		T1	3		T2	2		T3	2
all_pins[12]	values[0x1]	85	1		T71	1		T72	1		T73	1
all_pins[12]	transitions[0x0=>0x1]	64	1		T71	1		T72	1		T73	1
all_pins[12]	transitions[0x1=>0x0]	52	1		T210	1		T211	1		T296	3
all_pins[13]	values[0x0]	120454	1		T1	3		T2	2		T3	2
all_pins[13]	values[0x1]	73	1		T210	1		T211	2		T296	3
all_pins[13]	transitions[0x0=>0x1]	45	1		T211	1		T296	3		T300	1
all_pins[13]	transitions[0x1=>0x0]	54	1		T211	4		T212	1		T213	3
all_pins[14]	values[0x0]	120445	1		T1	3		T2	2		T3	2
all_pins[14]	values[0x1]	82	1		T210	1		T211	5		T212	1
all_pins[14]	transitions[0x0=>0x1]	54	1		T210	1		T211	1		T213	3
all_pins[14]	transitions[0x1=>0x0]	51	1		T210	1		T211	1		T212	3
all_pins[15]	values[0x0]	120448	1		T1	3		T2	2		T3	2
all_pins[15]	values[0x1]	79	1		T210	1		T211	5		T212	4
all_pins[15]	transitions[0x0=>0x1]	52	1		T211	4		T212	3		T296	1
all_pins[15]	transitions[0x1=>0x0]	54	1		T40	4		T64	4		T65	4
all_pins[16]	values[0x0]	120446	1		T1	3		T2	2		T3	2
all_pins[16]	values[0x1]	81	1		T40	4		T64	4		T65	4
all_pins[16]	transitions[0x0=>0x1]	66	1		T40	4		T64	4		T65	4
all_pins[16]	transitions[0x1=>0x0]	58	1		T49	1		T50	1		T51	1
all_pins[17]	values[0x0]	120454	1		T1	3		T2	2		T3	2
all_pins[17]	values[0x1]	73	1		T49	1		T50	1		T51	1
all_pins[17]	transitions[0x0=>0x1]	46	1		T49	1		T50	1		T51	1
all_pins[17]	transitions[0x1=>0x0]	95	1		T302	1		T303	1		T304	1