Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	290	1		T210	7		T211	7		T212	4
all_values[1]	290	1		T210	7		T211	7		T212	4
all_values[2]	290	1		T210	7		T211	7		T212	4
all_values[3]	290	1		T210	7		T211	7		T212	4
all_values[4]	290	1		T210	7		T211	7		T212	4
all_values[5]	290	1		T210	7		T211	7		T212	4
all_values[6]	290	1		T210	7		T211	7		T212	4
all_values[7]	290	1		T210	7		T211	7		T212	4
all_values[8]	290	1		T210	7		T211	7		T212	4
all_values[9]	290	1		T210	7		T211	7		T212	4
all_values[10]	290	1		T210	7		T211	7		T212	4
all_values[11]	290	1		T210	7		T211	7		T212	4
all_values[12]	290	1		T210	7		T211	7		T212	4
all_values[13]	290	1		T210	7		T211	7		T212	4
all_values[14]	290	1		T210	7		T211	7		T212	4
all_values[15]	290	1		T210	7		T211	7		T212	4
all_values[16]	290	1		T210	7		T211	7		T212	4
all_values[17]	290	1		T210	7		T211	7		T212	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2789	1		T210	61		T211	61		T212	24
auto[1]	2431	1		T210	65		T211	65		T212	48

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	872	1		T210	14		T211	8		T212	13
auto[1]	4348	1		T210	112		T211	118		T212	59

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3034	1		T210	62		T211	59		T212	41
auto[1]	2186	1		T210	64		T211	67		T212	31

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	31	1		T211	2		T296	1		T299	1
all_values[0]	auto[0]	auto[0]	auto[1]	72	1		T213	1		T296	1		T300	1
all_values[0]	auto[0]	auto[1]	auto[0]	17	1		T211	2		T212	1		T294	2
all_values[0]	auto[0]	auto[1]	auto[1]	57	1		T210	2		T211	1		T212	1
all_values[0]	auto[1]	auto[0]	auto[1]	60	1		T210	1		T211	1		T213	1
all_values[0]	auto[1]	auto[1]	auto[1]	53	1		T210	4		T211	1		T212	2
all_values[1]	auto[0]	auto[0]	auto[0]	27	1		T299	1		T305	1		T293	3
all_values[1]	auto[0]	auto[0]	auto[1]	61	1		T211	2		T213	1		T296	2
all_values[1]	auto[0]	auto[1]	auto[0]	13	1		T212	2		T300	1		T293	1
all_values[1]	auto[0]	auto[1]	auto[1]	64	1		T210	2		T211	1		T212	1
all_values[1]	auto[1]	auto[0]	auto[1]	74	1		T210	3		T211	2		T213	2
all_values[1]	auto[1]	auto[1]	auto[1]	51	1		T210	2		T211	2		T212	1
all_values[2]	auto[0]	auto[0]	auto[0]	29	1		T296	1		T292	1		T299	1
all_values[2]	auto[0]	auto[0]	auto[1]	70	1		T210	2		T211	1		T296	2
all_values[2]	auto[0]	auto[1]	auto[0]	23	1		T210	1		T212	1		T213	1
all_values[2]	auto[0]	auto[1]	auto[1]	57	1		T210	1		T211	2		T212	1
all_values[2]	auto[1]	auto[0]	auto[1]	48	1		T210	1		T300	2		T299	1
all_values[2]	auto[1]	auto[1]	auto[1]	63	1		T210	2		T211	4		T212	2
all_values[3]	auto[0]	auto[0]	auto[0]	43	1		T211	1		T296	4		T292	1
all_values[3]	auto[0]	auto[0]	auto[1]	59	1		T210	3		T211	1		T213	1
all_values[3]	auto[0]	auto[1]	auto[0]	20	1		T213	1		T296	3		T300	2
all_values[3]	auto[0]	auto[1]	auto[1]	64	1		T210	1		T211	3		T212	2
all_values[3]	auto[1]	auto[0]	auto[1]	59	1		T210	2		T211	2		T300	1
all_values[3]	auto[1]	auto[1]	auto[1]	45	1		T210	1		T212	2		T213	1
all_values[4]	auto[0]	auto[0]	auto[0]	39	1		T292	1		T297	3		T306	1
all_values[4]	auto[0]	auto[0]	auto[1]	61	1		T210	2		T212	3		T296	2
all_values[4]	auto[0]	auto[1]	auto[0]	14	1		T297	4		T307	2		T308	3
all_values[4]	auto[0]	auto[1]	auto[1]	60	1		T211	2		T213	2		T296	1
all_values[4]	auto[1]	auto[0]	auto[1]	73	1		T210	4		T212	1		T213	2
all_values[4]	auto[1]	auto[1]	auto[1]	43	1		T210	1		T211	5		T296	2
all_values[5]	auto[0]	auto[0]	auto[0]	29	1		T210	1		T300	2		T292	1
all_values[5]	auto[0]	auto[0]	auto[1]	59	1		T211	1		T296	1		T300	1
all_values[5]	auto[0]	auto[1]	auto[0]	19	1		T212	2		T213	4		T296	1
all_values[5]	auto[0]	auto[1]	auto[1]	59	1		T210	2		T212	1		T296	2
all_values[5]	auto[1]	auto[0]	auto[1]	67	1		T210	3		T211	4		T296	1
all_values[5]	auto[1]	auto[1]	auto[1]	57	1		T210	1		T211	2		T212	1
all_values[6]	auto[0]	auto[0]	auto[0]	27	1		T211	2		T299	1		T297	1
all_values[6]	auto[0]	auto[0]	auto[1]	60	1		T210	3		T211	1		T213	1
all_values[6]	auto[0]	auto[1]	auto[0]	13	1		T212	1		T299	1		T309	1
all_values[6]	auto[0]	auto[1]	auto[1]	58	1		T210	1		T211	2		T212	1
all_values[6]	auto[1]	auto[0]	auto[1]	67	1		T211	1		T296	4		T300	1
all_values[6]	auto[1]	auto[1]	auto[1]	65	1		T210	3		T211	1		T212	2
all_values[7]	auto[0]	auto[0]	auto[0]	23	1		T211	1		T292	2		T299	1
all_values[7]	auto[0]	auto[0]	auto[1]	64	1		T211	2		T212	2		T213	1
all_values[7]	auto[0]	auto[1]	auto[0]	11	1		T210	2		T295	1		T310	1
all_values[7]	auto[0]	auto[1]	auto[1]	66	1		T210	1		T211	2		T213	2
all_values[7]	auto[1]	auto[0]	auto[1]	61	1		T210	2		T211	1		T212	2
all_values[7]	auto[1]	auto[1]	auto[1]	65	1		T210	2		T211	1		T296	2
all_values[8]	auto[0]	auto[0]	auto[0]	31	1		T296	1		T299	1		T306	1
all_values[8]	auto[0]	auto[0]	auto[1]	67	1		T210	1		T211	1		T213	2
all_values[8]	auto[0]	auto[1]	auto[0]	18	1		T210	1		T300	1		T294	1
all_values[8]	auto[0]	auto[1]	auto[1]	53	1		T210	1		T211	1		T212	2
all_values[8]	auto[1]	auto[0]	auto[1]	75	1		T210	3		T211	5		T213	2
all_values[8]	auto[1]	auto[1]	auto[1]	46	1		T210	1		T212	2		T296	1
all_values[9]	auto[0]	auto[0]	auto[0]	34	1		T210	2		T292	2		T297	2
all_values[9]	auto[0]	auto[0]	auto[1]	54	1		T210	1		T211	2		T296	1
all_values[9]	auto[0]	auto[1]	auto[0]	22	1		T212	1		T296	3		T300	3
all_values[9]	auto[0]	auto[1]	auto[1]	57	1		T211	2		T212	2		T213	2
all_values[9]	auto[1]	auto[0]	auto[1]	68	1		T210	2		T211	2		T296	1
all_values[9]	auto[1]	auto[1]	auto[1]	55	1		T210	2		T211	1		T212	1
all_values[10]	auto[0]	auto[0]	auto[0]	32	1		T299	1		T297	1		T307	2
all_values[10]	auto[0]	auto[0]	auto[1]	54	1		T210	1		T211	4		T212	1
all_values[10]	auto[0]	auto[1]	auto[0]	15	1		T299	1		T311	1		T312	2
all_values[10]	auto[0]	auto[1]	auto[1]	58	1		T210	4		T212	1		T213	2
all_values[10]	auto[1]	auto[0]	auto[1]	68	1		T210	1		T211	1		T212	1
all_values[10]	auto[1]	auto[1]	auto[1]	63	1		T210	1		T211	2		T212	1
all_values[11]	auto[0]	auto[0]	auto[0]	35	1		T306	1		T305	1		T293	1
all_values[11]	auto[0]	auto[0]	auto[1]	51	1		T211	3		T212	2		T296	4
all_values[11]	auto[0]	auto[1]	auto[0]	23	1		T306	1		T293	1		T294	2
all_values[11]	auto[0]	auto[1]	auto[1]	67	1		T210	3		T211	2		T213	2
all_values[11]	auto[1]	auto[0]	auto[1]	64	1		T210	1		T211	1		T296	2
all_values[11]	auto[1]	auto[1]	auto[1]	50	1		T210	3		T211	1		T212	2
all_values[12]	auto[0]	auto[0]	auto[0]	41	1		T210	2		T296	4		T299	1
all_values[12]	auto[0]	auto[0]	auto[1]	44	1		T210	1		T211	1		T212	1
all_values[12]	auto[0]	auto[1]	auto[0]	13	1		T297	1		T307	1		T294	3
all_values[12]	auto[0]	auto[1]	auto[1]	64	1		T210	2		T211	2		T213	1
all_values[12]	auto[1]	auto[0]	auto[1]	67	1		T210	2		T211	2		T212	1
all_values[12]	auto[1]	auto[1]	auto[1]	61	1		T211	2		T212	2		T213	2
all_values[13]	auto[0]	auto[0]	auto[0]	25	1		T212	2		T294	1		T313	1
all_values[13]	auto[0]	auto[0]	auto[1]	56	1		T210	1		T211	2		T213	1
all_values[13]	auto[0]	auto[1]	auto[0]	21	1		T212	2		T213	1		T300	1
all_values[13]	auto[0]	auto[1]	auto[1]	61	1		T210	2		T296	2		T299	1
all_values[13]	auto[1]	auto[0]	auto[1]	72	1		T210	3		T211	2		T296	2
all_values[13]	auto[1]	auto[1]	auto[1]	55	1		T210	1		T211	3		T213	2
all_values[14]	auto[0]	auto[0]	auto[0]	24	1		T292	3		T293	1		T298	1
all_values[14]	auto[0]	auto[0]	auto[1]	54	1		T212	2		T213	1		T296	1
all_values[14]	auto[0]	auto[1]	auto[0]	14	1		T210	1		T296	1		T292	1
all_values[14]	auto[0]	auto[1]	auto[1]	66	1		T210	2		T211	2		T213	1
all_values[14]	auto[1]	auto[0]	auto[1]	65	1		T210	3		T211	2		T212	2
all_values[14]	auto[1]	auto[1]	auto[1]	67	1		T210	1		T211	3		T213	2
all_values[15]	auto[0]	auto[0]	auto[0]	29	1		T210	1		T292	1		T299	1
all_values[15]	auto[0]	auto[0]	auto[1]	53	1		T210	2		T296	1		T300	3
all_values[15]	auto[0]	auto[1]	auto[0]	17	1		T210	1		T213	2		T307	3
all_values[15]	auto[0]	auto[1]	auto[1]	66	1		T210	1		T211	2		T212	1
all_values[15]	auto[1]	auto[0]	auto[1]	68	1		T210	1		T211	1		T213	1
all_values[15]	auto[1]	auto[1]	auto[1]	57	1		T210	1		T211	4		T212	3
all_values[16]	auto[0]	auto[0]	auto[0]	31	1		T210	1		T292	2		T299	1
all_values[16]	auto[0]	auto[0]	auto[1]	59	1		T210	1		T211	2		T212	2
all_values[16]	auto[0]	auto[1]	auto[0]	20	1		T212	1		T296	2		T292	2
all_values[16]	auto[0]	auto[1]	auto[1]	66	1		T210	2		T296	1		T300	2
all_values[16]	auto[1]	auto[0]	auto[1]	64	1		T210	1		T211	2		T213	3
all_values[16]	auto[1]	auto[1]	auto[1]	50	1		T210	2		T211	3		T212	1
all_values[17]	auto[0]	auto[0]	auto[0]	32	1		T210	1		T300	1		T292	1
all_values[17]	auto[0]	auto[0]	auto[1]	60	1		T210	1		T211	2		T212	2
all_values[17]	auto[0]	auto[1]	auto[0]	17	1		T300	1		T292	1		T299	1
all_values[17]	auto[0]	auto[1]	auto[1]	61	1		T210	2		T211	2		T296	5
all_values[17]	auto[1]	auto[0]	auto[1]	49	1		T210	1		T211	1		T296	1
all_values[17]	auto[1]	auto[1]	auto[1]	71	1		T210	2		T211	2		T212	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal