Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.35 97.82 93.81 97.44 73.44 96.21 98.17 96.58


Total test records in report: 2736
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T2574 /workspace/coverage/default/21.usbdev_aon_wake_resume.2577598071 Jun 28 06:11:31 PM PDT 24 Jun 28 06:12:03 PM PDT 24 23493751801 ps
T2575 /workspace/coverage/default/35.usbdev_disconnected.2077086227 Jun 28 06:13:51 PM PDT 24 Jun 28 06:13:54 PM PDT 24 163864586 ps
T2576 /workspace/coverage/default/22.usbdev_low_speed_traffic.1612623492 Jun 28 06:11:56 PM PDT 24 Jun 28 06:13:36 PM PDT 24 10246199304 ps
T2577 /workspace/coverage/default/4.usbdev_max_length_out_transaction.964141784 Jun 28 06:09:03 PM PDT 24 Jun 28 06:09:05 PM PDT 24 247235465 ps
T2578 /workspace/coverage/default/5.usbdev_device_address.2892924456 Jun 28 06:09:07 PM PDT 24 Jun 28 06:09:49 PM PDT 24 21807911495 ps
T2579 /workspace/coverage/default/30.usbdev_data_toggle_clear.67082443 Jun 28 06:13:04 PM PDT 24 Jun 28 06:13:12 PM PDT 24 338626843 ps
T2580 /workspace/coverage/default/37.usbdev_endpoint_access.4278450946 Jun 28 06:14:04 PM PDT 24 Jun 28 06:14:10 PM PDT 24 885533019 ps
T2581 /workspace/coverage/default/8.usbdev_bitstuff_err.2586766047 Jun 28 06:09:42 PM PDT 24 Jun 28 06:09:47 PM PDT 24 170285915 ps
T2582 /workspace/coverage/default/23.usbdev_alert_test.2018942662 Jun 28 06:12:12 PM PDT 24 Jun 28 06:12:20 PM PDT 24 36237029 ps
T2583 /workspace/coverage/default/13.usbdev_fifo_rst.3252759035 Jun 28 06:10:41 PM PDT 24 Jun 28 06:10:47 PM PDT 24 307201882 ps
T2584 /workspace/coverage/default/19.usbdev_spurious_pids_ignored.1253019672 Jun 28 06:11:29 PM PDT 24 Jun 28 06:12:18 PM PDT 24 5064879048 ps
T2585 /workspace/coverage/default/18.usbdev_smoke.3087633619 Jun 28 06:11:20 PM PDT 24 Jun 28 06:11:24 PM PDT 24 211911826 ps
T2586 /workspace/coverage/default/27.usbdev_random_length_out_transaction.3056499597 Jun 28 06:12:47 PM PDT 24 Jun 28 06:12:53 PM PDT 24 171225722 ps
T2587 /workspace/coverage/default/3.usbdev_aon_wake_reset.2194229254 Jun 28 06:08:53 PM PDT 24 Jun 28 06:09:10 PM PDT 24 13308999076 ps
T2588 /workspace/coverage/default/31.usbdev_data_toggle_clear.3554527481 Jun 28 06:13:19 PM PDT 24 Jun 28 06:13:27 PM PDT 24 444996007 ps
T2589 /workspace/coverage/default/14.usbdev_setup_trans_ignored.1947434538 Jun 28 06:10:50 PM PDT 24 Jun 28 06:10:55 PM PDT 24 153301341 ps
T2590 /workspace/coverage/default/38.usbdev_link_in_err.3932905299 Jun 28 06:14:03 PM PDT 24 Jun 28 06:14:07 PM PDT 24 204331659 ps
T2591 /workspace/coverage/default/25.usbdev_phy_config_pinflip.2040830868 Jun 28 06:12:15 PM PDT 24 Jun 28 06:12:25 PM PDT 24 247256864 ps
T2592 /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.95080284 Jun 28 06:08:26 PM PDT 24 Jun 28 06:08:29 PM PDT 24 135362629 ps
T2593 /workspace/coverage/default/9.usbdev_in_trans.750660186 Jun 28 06:09:54 PM PDT 24 Jun 28 06:09:58 PM PDT 24 203130933 ps
T2594 /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.3273372841 Jun 28 06:15:21 PM PDT 24 Jun 28 06:15:27 PM PDT 24 171467115 ps
T2595 /workspace/coverage/default/10.usbdev_data_toggle_restore.3464563287 Jun 28 06:09:58 PM PDT 24 Jun 28 06:10:01 PM PDT 24 642328544 ps
T2596 /workspace/coverage/default/36.usbdev_out_stall.2182510390 Jun 28 06:13:57 PM PDT 24 Jun 28 06:14:01 PM PDT 24 170158187 ps
T2597 /workspace/coverage/default/28.usbdev_max_length_out_transaction.3298739589 Jun 28 06:12:58 PM PDT 24 Jun 28 06:13:00 PM PDT 24 186393014 ps
T2598 /workspace/coverage/default/2.usbdev_smoke.29169564 Jun 28 06:08:48 PM PDT 24 Jun 28 06:08:51 PM PDT 24 237955504 ps
T2599 /workspace/coverage/default/14.usbdev_max_usb_traffic.4038665970 Jun 28 06:10:50 PM PDT 24 Jun 28 06:11:37 PM PDT 24 6052416754 ps
T2600 /workspace/coverage/default/18.usbdev_pending_in_trans.788518457 Jun 28 06:11:27 PM PDT 24 Jun 28 06:11:29 PM PDT 24 162660584 ps
T2601 /workspace/coverage/default/37.usbdev_setup_stage.1341637776 Jun 28 06:14:08 PM PDT 24 Jun 28 06:14:14 PM PDT 24 147022376 ps
T2602 /workspace/coverage/default/14.usbdev_pkt_buffer.2094120266 Jun 28 06:10:56 PM PDT 24 Jun 28 06:11:33 PM PDT 24 13020638511 ps
T2603 /workspace/coverage/default/35.usbdev_stall_priority_over_nak.4189365677 Jun 28 06:13:51 PM PDT 24 Jun 28 06:13:52 PM PDT 24 237473409 ps
T2604 /workspace/coverage/default/29.usbdev_av_buffer.619811734 Jun 28 06:13:00 PM PDT 24 Jun 28 06:13:04 PM PDT 24 174940010 ps
T2605 /workspace/coverage/default/9.usbdev_pending_in_trans.2166817663 Jun 28 06:09:53 PM PDT 24 Jun 28 06:09:57 PM PDT 24 161043056 ps
T2606 /workspace/coverage/default/33.usbdev_aon_wake_reset.1454459823 Jun 28 06:13:21 PM PDT 24 Jun 28 06:13:44 PM PDT 24 13343809567 ps
T2607 /workspace/coverage/default/38.usbdev_max_length_out_transaction.2068845296 Jun 28 06:14:23 PM PDT 24 Jun 28 06:14:27 PM PDT 24 207573642 ps
T2608 /workspace/coverage/default/8.usbdev_max_length_in_transaction.1401565326 Jun 28 06:09:40 PM PDT 24 Jun 28 06:09:46 PM PDT 24 254332596 ps
T2609 /workspace/coverage/default/20.usbdev_enable.3771370403 Jun 28 06:11:28 PM PDT 24 Jun 28 06:11:30 PM PDT 24 45446061 ps
T2610 /workspace/coverage/default/25.usbdev_in_trans.2407068586 Jun 28 06:12:21 PM PDT 24 Jun 28 06:12:29 PM PDT 24 190950322 ps
T128 /workspace/coverage/default/34.usbdev_nak_trans.1203733930 Jun 28 06:13:29 PM PDT 24 Jun 28 06:13:36 PM PDT 24 235159623 ps
T2611 /workspace/coverage/default/15.usbdev_aon_wake_resume.3280465767 Jun 28 06:10:51 PM PDT 24 Jun 28 06:11:21 PM PDT 24 23480940082 ps
T2612 /workspace/coverage/default/35.usbdev_random_length_in_transaction.1975299168 Jun 28 06:13:52 PM PDT 24 Jun 28 06:13:55 PM PDT 24 196219245 ps
T2613 /workspace/coverage/default/45.usbdev_phy_config_pinflip.4287528237 Jun 28 06:15:20 PM PDT 24 Jun 28 06:15:27 PM PDT 24 305009694 ps
T2614 /workspace/coverage/default/8.usbdev_data_toggle_restore.616543201 Jun 28 06:09:37 PM PDT 24 Jun 28 06:09:43 PM PDT 24 1052516312 ps
T2615 /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.171126152 Jun 28 06:13:31 PM PDT 24 Jun 28 06:15:30 PM PDT 24 4441071730 ps
T2616 /workspace/coverage/default/0.usbdev_pkt_received.711693802 Jun 28 06:08:32 PM PDT 24 Jun 28 06:08:34 PM PDT 24 184658687 ps
T2617 /workspace/coverage/default/7.usbdev_link_resume.1902652240 Jun 28 06:09:31 PM PDT 24 Jun 28 06:09:57 PM PDT 24 23335230467 ps
T2618 /workspace/coverage/default/36.usbdev_pkt_buffer.688857365 Jun 28 06:13:55 PM PDT 24 Jun 28 06:14:14 PM PDT 24 7693692323 ps
T2619 /workspace/coverage/default/10.usbdev_random_length_out_transaction.4057453241 Jun 28 06:10:04 PM PDT 24 Jun 28 06:10:08 PM PDT 24 155655059 ps
T2620 /workspace/coverage/default/9.usbdev_pkt_sent.160516329 Jun 28 06:09:49 PM PDT 24 Jun 28 06:09:53 PM PDT 24 291495496 ps
T2621 /workspace/coverage/default/38.usbdev_disconnected.952788440 Jun 28 06:14:13 PM PDT 24 Jun 28 06:14:20 PM PDT 24 146281527 ps
T2622 /workspace/coverage/default/46.usbdev_min_length_out_transaction.3818120314 Jun 28 06:15:17 PM PDT 24 Jun 28 06:15:23 PM PDT 24 154933336 ps
T2623 /workspace/coverage/default/40.usbdev_streaming_out.779767481 Jun 28 06:14:41 PM PDT 24 Jun 28 06:15:27 PM PDT 24 4613969768 ps
T2624 /workspace/coverage/default/10.usbdev_phy_pins_sense.3123691625 Jun 28 06:10:08 PM PDT 24 Jun 28 06:10:11 PM PDT 24 48427525 ps
T2625 /workspace/coverage/default/46.usbdev_aon_wake_resume.3615427207 Jun 28 06:15:22 PM PDT 24 Jun 28 06:15:50 PM PDT 24 23375457397 ps
T2626 /workspace/coverage/default/39.usbdev_stall_priority_over_nak.2153963092 Jun 28 06:14:24 PM PDT 24 Jun 28 06:14:29 PM PDT 24 213015959 ps
T2627 /workspace/coverage/default/13.usbdev_out_stall.2114611355 Jun 28 06:10:37 PM PDT 24 Jun 28 06:10:42 PM PDT 24 184349233 ps
T2628 /workspace/coverage/default/39.usbdev_phy_pins_sense.29074861 Jun 28 06:14:14 PM PDT 24 Jun 28 06:14:21 PM PDT 24 44706391 ps
T2629 /workspace/coverage/default/39.usbdev_out_iso.3082506458 Jun 28 06:14:20 PM PDT 24 Jun 28 06:14:26 PM PDT 24 183393409 ps
T2630 /workspace/coverage/default/44.usbdev_stall_priority_over_nak.1507418896 Jun 28 06:15:16 PM PDT 24 Jun 28 06:15:21 PM PDT 24 173896944 ps
T2631 /workspace/coverage/default/29.usbdev_in_trans.3380950934 Jun 28 06:13:03 PM PDT 24 Jun 28 06:13:11 PM PDT 24 245256007 ps
T2632 /workspace/coverage/default/23.usbdev_max_length_out_transaction.576900673 Jun 28 06:12:10 PM PDT 24 Jun 28 06:12:19 PM PDT 24 202972285 ps
T2633 /workspace/coverage/default/9.usbdev_fifo_rst.1865732471 Jun 28 06:09:43 PM PDT 24 Jun 28 06:09:49 PM PDT 24 269750674 ps
T265 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1088530906 Jun 28 05:40:17 PM PDT 24 Jun 28 05:40:20 PM PDT 24 73646565 ps
T203 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.3930740403 Jun 28 05:40:33 PM PDT 24 Jun 28 05:40:43 PM PDT 24 1015112036 ps
T210 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1061103345 Jun 28 05:40:33 PM PDT 24 Jun 28 05:40:39 PM PDT 24 49670661 ps
T211 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1758597150 Jun 28 05:41:06 PM PDT 24 Jun 28 05:41:11 PM PDT 24 36780638 ps
T212 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1927732161 Jun 28 05:40:36 PM PDT 24 Jun 28 05:40:42 PM PDT 24 57165017 ps
T204 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3538042671 Jun 28 05:40:21 PM PDT 24 Jun 28 05:40:25 PM PDT 24 566612592 ps
T213 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.4185641696 Jun 28 05:40:42 PM PDT 24 Jun 28 05:40:48 PM PDT 24 45129444 ps
T206 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.945165824 Jun 28 05:40:50 PM PDT 24 Jun 28 05:40:55 PM PDT 24 89257772 ps
T296 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.516215524 Jun 28 05:40:41 PM PDT 24 Jun 28 05:40:47 PM PDT 24 113422449 ps
T279 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.462121757 Jun 28 05:40:32 PM PDT 24 Jun 28 05:40:37 PM PDT 24 73766425 ps
T205 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2039737585 Jun 28 05:40:15 PM PDT 24 Jun 28 05:40:17 PM PDT 24 118352851 ps
T231 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.4031265987 Jun 28 05:40:35 PM PDT 24 Jun 28 05:40:44 PM PDT 24 794505375 ps
T300 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3925472263 Jun 28 05:40:41 PM PDT 24 Jun 28 05:40:47 PM PDT 24 57575772 ps
T292 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1239014582 Jun 28 05:40:37 PM PDT 24 Jun 28 05:40:43 PM PDT 24 42593949 ps
T299 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.3882956396 Jun 28 05:40:37 PM PDT 24 Jun 28 05:40:44 PM PDT 24 52059843 ps
T266 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1843795897 Jun 28 05:40:11 PM PDT 24 Jun 28 05:40:14 PM PDT 24 98222929 ps
T251 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2515123661 Jun 28 05:40:49 PM PDT 24 Jun 28 05:40:59 PM PDT 24 946129170 ps
T297 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.2608268932 Jun 28 05:40:22 PM PDT 24 Jun 28 05:40:23 PM PDT 24 41242520 ps
T306 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2446836200 Jun 28 05:40:56 PM PDT 24 Jun 28 05:41:00 PM PDT 24 60909189 ps
T267 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2444581795 Jun 28 05:40:27 PM PDT 24 Jun 28 05:40:29 PM PDT 24 76448807 ps
T305 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.3528587019 Jun 28 05:40:33 PM PDT 24 Jun 28 05:40:38 PM PDT 24 30665244 ps
T268 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3310683923 Jun 28 05:40:58 PM PDT 24 Jun 28 05:41:04 PM PDT 24 81813466 ps
T293 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2555623648 Jun 28 05:40:29 PM PDT 24 Jun 28 05:40:31 PM PDT 24 58347258 ps
T298 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1772936101 Jun 28 05:40:54 PM PDT 24 Jun 28 05:40:58 PM PDT 24 41311305 ps
T307 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1173345797 Jun 28 05:40:16 PM PDT 24 Jun 28 05:40:18 PM PDT 24 58428202 ps
T269 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1474218008 Jun 28 05:40:12 PM PDT 24 Jun 28 05:40:15 PM PDT 24 194959647 ps
T294 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2821564766 Jun 28 05:40:50 PM PDT 24 Jun 28 05:40:55 PM PDT 24 52432696 ps
T309 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3470877146 Jun 28 05:40:35 PM PDT 24 Jun 28 05:40:41 PM PDT 24 48936895 ps
T295 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.321383947 Jun 28 05:40:37 PM PDT 24 Jun 28 05:40:43 PM PDT 24 53645373 ps
T2634 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.991150333 Jun 28 05:40:13 PM PDT 24 Jun 28 05:40:15 PM PDT 24 61987694 ps
T246 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.486387591 Jun 28 05:40:26 PM PDT 24 Jun 28 05:40:30 PM PDT 24 1295068356 ps
T247 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3633040304 Jun 28 05:40:38 PM PDT 24 Jun 28 05:40:47 PM PDT 24 354647584 ps
T226 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2074852148 Jun 28 05:40:34 PM PDT 24 Jun 28 05:40:41 PM PDT 24 152590306 ps
T227 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.468666433 Jun 28 05:40:33 PM PDT 24 Jun 28 05:40:39 PM PDT 24 163593772 ps
T301 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3284058257 Jun 28 05:40:36 PM PDT 24 Jun 28 05:40:42 PM PDT 24 40508374 ps
T280 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3491811389 Jun 28 05:40:47 PM PDT 24 Jun 28 05:40:53 PM PDT 24 118802321 ps
T2635 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.1310555636 Jun 28 05:40:46 PM PDT 24 Jun 28 05:40:51 PM PDT 24 85922420 ps
T234 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.4245123669 Jun 28 05:40:32 PM PDT 24 Jun 28 05:40:37 PM PDT 24 83478861 ps
T248 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.333179534 Jun 28 05:40:40 PM PDT 24 Jun 28 05:40:47 PM PDT 24 118477831 ps
T249 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.288883802 Jun 28 05:40:39 PM PDT 24 Jun 28 05:40:47 PM PDT 24 72012375 ps
T281 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3607836884 Jun 28 05:40:39 PM PDT 24 Jun 28 05:40:46 PM PDT 24 93282916 ps
T238 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3550923734 Jun 28 05:40:41 PM PDT 24 Jun 28 05:40:49 PM PDT 24 95874177 ps
T313 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.434131031 Jun 28 05:40:46 PM PDT 24 Jun 28 05:40:51 PM PDT 24 90351585 ps
T232 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1120491034 Jun 28 05:40:37 PM PDT 24 Jun 28 05:40:44 PM PDT 24 117141732 ps
T270 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1516551634 Jun 28 05:40:45 PM PDT 24 Jun 28 05:40:52 PM PDT 24 76623868 ps
T250 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1559589203 Jun 28 05:41:07 PM PDT 24 Jun 28 05:41:14 PM PDT 24 868185655 ps
T286 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1948394834 Jun 28 05:40:37 PM PDT 24 Jun 28 05:40:44 PM PDT 24 97967980 ps
T311 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.375880024 Jun 28 05:40:51 PM PDT 24 Jun 28 05:40:56 PM PDT 24 43767690 ps
T233 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3589792129 Jun 28 05:40:50 PM PDT 24 Jun 28 05:40:56 PM PDT 24 79232840 ps
T271 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1232424906 Jun 28 05:40:18 PM PDT 24 Jun 28 05:40:32 PM PDT 24 492670661 ps
T2636 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.679856834 Jun 28 05:40:29 PM PDT 24 Jun 28 05:40:32 PM PDT 24 46244178 ps
T274 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2252751659 Jun 28 05:40:33 PM PDT 24 Jun 28 05:40:38 PM PDT 24 75655209 ps
T2637 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2204142956 Jun 28 05:40:43 PM PDT 24 Jun 28 05:40:50 PM PDT 24 44411824 ps
T2638 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.89603734 Jun 28 05:40:43 PM PDT 24 Jun 28 05:40:49 PM PDT 24 54255054 ps
T272 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.708073445 Jun 28 05:40:13 PM PDT 24 Jun 28 05:40:15 PM PDT 24 94055190 ps
T2639 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1380343162 Jun 28 05:40:15 PM PDT 24 Jun 28 05:40:19 PM PDT 24 161406842 ps
T236 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.4029189204 Jun 28 05:40:35 PM PDT 24 Jun 28 05:40:42 PM PDT 24 187308509 ps
T278 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2450951883 Jun 28 05:40:46 PM PDT 24 Jun 28 05:40:52 PM PDT 24 69694286 ps
T2640 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.350806999 Jun 28 05:40:32 PM PDT 24 Jun 28 05:40:37 PM PDT 24 57491141 ps
T312 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3263822375 Jun 28 05:40:43 PM PDT 24 Jun 28 05:40:49 PM PDT 24 49482817 ps
T2641 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.645276990 Jun 28 05:40:53 PM PDT 24 Jun 28 05:40:57 PM PDT 24 40895329 ps
T308 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.3411741904 Jun 28 05:40:44 PM PDT 24 Jun 28 05:40:50 PM PDT 24 42535007 ps
T2642 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1349257210 Jun 28 05:40:35 PM PDT 24 Jun 28 05:40:42 PM PDT 24 98445750 ps
T2643 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3873632048 Jun 28 05:40:42 PM PDT 24 Jun 28 05:40:48 PM PDT 24 39578467 ps
T287 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.798474725 Jun 28 05:40:40 PM PDT 24 Jun 28 05:40:47 PM PDT 24 227041967 ps
T310 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3511357491 Jun 28 05:40:43 PM PDT 24 Jun 28 05:40:49 PM PDT 24 62828786 ps
T288 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.595348532 Jun 28 05:40:26 PM PDT 24 Jun 28 05:40:29 PM PDT 24 216243329 ps
T314 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1826853278 Jun 28 05:40:33 PM PDT 24 Jun 28 05:40:43 PM PDT 24 2040439911 ps
T2644 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1533943270 Jun 28 05:40:31 PM PDT 24 Jun 28 05:40:35 PM PDT 24 72534822 ps
T2645 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.4107216923 Jun 28 05:40:35 PM PDT 24 Jun 28 05:40:42 PM PDT 24 97450977 ps
T273 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.4268839746 Jun 28 05:40:20 PM PDT 24 Jun 28 05:40:22 PM PDT 24 194935269 ps
T2646 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3852596594 Jun 28 05:40:43 PM PDT 24 Jun 28 05:40:49 PM PDT 24 33705494 ps
T2647 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.4074093317 Jun 28 05:40:33 PM PDT 24 Jun 28 05:40:38 PM PDT 24 245578778 ps
T275 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1075635295 Jun 28 05:40:28 PM PDT 24 Jun 28 05:40:36 PM PDT 24 381528835 ps
T276 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2790706474 Jun 28 05:40:34 PM PDT 24 Jun 28 05:40:40 PM PDT 24 61793621 ps
T289 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2458485455 Jun 28 05:40:49 PM PDT 24 Jun 28 05:40:59 PM PDT 24 773845546 ps
T315 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2364161604 Jun 28 05:40:41 PM PDT 24 Jun 28 05:40:49 PM PDT 24 552786009 ps
T277 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.260676670 Jun 28 05:40:11 PM PDT 24 Jun 28 05:40:25 PM PDT 24 3155722587 ps
T2648 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.941895695 Jun 28 05:40:44 PM PDT 24 Jun 28 05:40:50 PM PDT 24 55565842 ps
T2649 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3139206929 Jun 28 05:40:45 PM PDT 24 Jun 28 05:40:51 PM PDT 24 58550992 ps
T235 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3587724289 Jun 28 05:40:46 PM PDT 24 Jun 28 05:40:53 PM PDT 24 171256198 ps
T2650 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1882395199 Jun 28 05:40:18 PM PDT 24 Jun 28 05:40:22 PM PDT 24 328490017 ps
T2651 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1800002430 Jun 28 05:40:35 PM PDT 24 Jun 28 05:40:41 PM PDT 24 36785816 ps
T290 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.983311081 Jun 28 05:40:14 PM PDT 24 Jun 28 05:40:17 PM PDT 24 128407538 ps
T291 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2770224594 Jun 28 05:40:32 PM PDT 24 Jun 28 05:40:38 PM PDT 24 206388373 ps
T2652 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1834861297 Jun 28 05:40:39 PM PDT 24 Jun 28 05:40:46 PM PDT 24 44119069 ps
T237 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.348733261 Jun 28 05:40:23 PM PDT 24 Jun 28 05:40:27 PM PDT 24 343464507 ps
T239 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.616838246 Jun 28 05:40:34 PM PDT 24 Jun 28 05:40:42 PM PDT 24 125463778 ps
T2653 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.709704508 Jun 28 05:40:32 PM PDT 24 Jun 28 05:40:35 PM PDT 24 35611215 ps
T2654 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1291531602 Jun 28 05:40:32 PM PDT 24 Jun 28 05:40:36 PM PDT 24 155817508 ps
T2655 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1642662970 Jun 28 05:40:11 PM PDT 24 Jun 28 05:40:13 PM PDT 24 46996386 ps
T2656 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2000788517 Jun 28 05:40:46 PM PDT 24 Jun 28 05:40:52 PM PDT 24 158918072 ps
T2657 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1218589762 Jun 28 05:40:42 PM PDT 24 Jun 28 05:40:48 PM PDT 24 33580360 ps
T2658 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.361514555 Jun 28 05:40:11 PM PDT 24 Jun 28 05:40:16 PM PDT 24 358541733 ps
T2659 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2210248138 Jun 28 05:40:37 PM PDT 24 Jun 28 05:40:45 PM PDT 24 415157652 ps
T2660 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.44291324 Jun 28 05:40:44 PM PDT 24 Jun 28 05:40:51 PM PDT 24 175537568 ps
T2661 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2127814980 Jun 28 05:40:37 PM PDT 24 Jun 28 05:40:43 PM PDT 24 39539803 ps
T241 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2608871849 Jun 28 05:40:29 PM PDT 24 Jun 28 05:40:32 PM PDT 24 197510158 ps
T2662 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3859504273 Jun 28 05:40:31 PM PDT 24 Jun 28 05:40:34 PM PDT 24 77534614 ps
T2663 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3177207320 Jun 28 05:40:44 PM PDT 24 Jun 28 05:40:50 PM PDT 24 136734463 ps
T316 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2710135626 Jun 28 05:40:16 PM PDT 24 Jun 28 05:40:20 PM PDT 24 599071396 ps
T2664 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3590081741 Jun 28 05:40:37 PM PDT 24 Jun 28 05:40:45 PM PDT 24 195771062 ps
T2665 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.230202226 Jun 28 05:40:29 PM PDT 24 Jun 28 05:40:32 PM PDT 24 156330521 ps
T2666 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2960655988 Jun 28 05:40:55 PM PDT 24 Jun 28 05:40:59 PM PDT 24 48322520 ps
T2667 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.844626588 Jun 28 05:40:29 PM PDT 24 Jun 28 05:40:34 PM PDT 24 477607627 ps
T2668 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2267235259 Jun 28 05:40:33 PM PDT 24 Jun 28 05:40:39 PM PDT 24 40035884 ps
T2669 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.863275774 Jun 28 05:40:15 PM PDT 24 Jun 28 05:40:18 PM PDT 24 129441646 ps
T2670 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.442594181 Jun 28 05:40:33 PM PDT 24 Jun 28 05:40:40 PM PDT 24 525421013 ps
T2671 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.981664629 Jun 28 05:40:33 PM PDT 24 Jun 28 05:40:42 PM PDT 24 385646762 ps
T2672 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.2147243939 Jun 28 05:40:48 PM PDT 24 Jun 28 05:40:54 PM PDT 24 52855568 ps
T2673 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1693723486 Jun 28 05:40:54 PM PDT 24 Jun 28 05:40:58 PM PDT 24 81072218 ps
T2674 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3804416035 Jun 28 05:40:33 PM PDT 24 Jun 28 05:40:41 PM PDT 24 460605752 ps
T2675 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.122344079 Jun 28 05:40:35 PM PDT 24 Jun 28 05:40:43 PM PDT 24 187379292 ps
T2676 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2304092855 Jun 28 05:40:32 PM PDT 24 Jun 28 05:40:36 PM PDT 24 58040075 ps
T317 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3363820507 Jun 28 05:40:50 PM PDT 24 Jun 28 05:41:00 PM PDT 24 2071083824 ps
T2677 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.256843899 Jun 28 05:40:43 PM PDT 24 Jun 28 05:40:49 PM PDT 24 36755615 ps
T2678 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3310447529 Jun 28 05:40:54 PM PDT 24 Jun 28 05:40:58 PM PDT 24 143475293 ps
T2679 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.210633205 Jun 28 05:40:53 PM PDT 24 Jun 28 05:40:57 PM PDT 24 63597754 ps
T2680 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.4152850783 Jun 28 05:40:57 PM PDT 24 Jun 28 05:41:05 PM PDT 24 177091767 ps
T2681 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1312573002 Jun 28 05:40:35 PM PDT 24 Jun 28 05:40:41 PM PDT 24 37934846 ps
T2682 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.182711956 Jun 28 05:40:31 PM PDT 24 Jun 28 05:40:35 PM PDT 24 191530454 ps
T2683 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3138064317 Jun 28 05:40:44 PM PDT 24 Jun 28 05:40:50 PM PDT 24 34694885 ps
T2684 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.585707785 Jun 28 05:40:18 PM PDT 24 Jun 28 05:40:20 PM PDT 24 138696058 ps
T2685 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2176240157 Jun 28 05:40:44 PM PDT 24 Jun 28 05:40:51 PM PDT 24 104663131 ps
T2686 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2401698094 Jun 28 05:40:53 PM PDT 24 Jun 28 05:40:57 PM PDT 24 100577292 ps
T2687 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.237061114 Jun 28 05:40:34 PM PDT 24 Jun 28 05:40:40 PM PDT 24 67915107 ps
T2688 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.2574692093 Jun 28 05:40:41 PM PDT 24 Jun 28 05:40:47 PM PDT 24 61244758 ps
T2689 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1370892406 Jun 28 05:40:36 PM PDT 24 Jun 28 05:40:43 PM PDT 24 137949043 ps
T2690 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1905536217 Jun 28 05:40:32 PM PDT 24 Jun 28 05:40:40 PM PDT 24 698432110 ps
T2691 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2314643631 Jun 28 05:40:33 PM PDT 24 Jun 28 05:40:39 PM PDT 24 187699512 ps
T2692 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2810998915 Jun 28 05:40:13 PM PDT 24 Jun 28 05:40:15 PM PDT 24 145790685 ps
T2693 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.4088874368 Jun 28 05:40:53 PM PDT 24 Jun 28 05:40:57 PM PDT 24 67279406 ps
T2694 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.682082408 Jun 28 05:40:34 PM PDT 24 Jun 28 05:40:40 PM PDT 24 201974551 ps
T2695 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2812162223 Jun 28 05:40:12 PM PDT 24 Jun 28 05:40:16 PM PDT 24 277617902 ps
T2696 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3900522910 Jun 28 05:40:43 PM PDT 24 Jun 28 05:40:55 PM PDT 24 1795042293 ps
T2697 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.4072872717 Jun 28 05:40:40 PM PDT 24 Jun 28 05:40:48 PM PDT 24 230607909 ps
T2698 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3079076715 Jun 28 05:40:46 PM PDT 24 Jun 28 05:40:52 PM PDT 24 188976288 ps
T2699 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1930367195 Jun 28 05:40:37 PM PDT 24 Jun 28 05:40:43 PM PDT 24 44347218 ps
T2700 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.179644407 Jun 28 05:40:10 PM PDT 24 Jun 28 05:40:11 PM PDT 24 41727448 ps
T2701 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.2965013469 Jun 28 05:40:49 PM PDT 24 Jun 28 05:40:54 PM PDT 24 39511166 ps
T2702 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2649633993 Jun 28 05:40:35 PM PDT 24 Jun 28 05:40:45 PM PDT 24 687910672 ps
T2703 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3743396344 Jun 28 05:40:52 PM PDT 24 Jun 28 05:40:58 PM PDT 24 94748439 ps
T2704 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3336159169 Jun 28 05:40:34 PM PDT 24 Jun 28 05:40:40 PM PDT 24 82013152 ps
T2705 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.4081948052 Jun 28 05:40:38 PM PDT 24 Jun 28 05:40:45 PM PDT 24 194354094 ps
T2706 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.4016210865 Jun 28 05:40:14 PM PDT 24 Jun 28 05:40:19 PM PDT 24 496602037 ps
T2707 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1124576606 Jun 28 05:40:48 PM PDT 24 Jun 28 05:40:56 PM PDT 24 315637986 ps
T2708 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.1661905823 Jun 28 05:40:40 PM PDT 24 Jun 28 05:40:47 PM PDT 24 166752574 ps
T2709 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3732697065 Jun 28 05:40:30 PM PDT 24 Jun 28 05:40:34 PM PDT 24 257394676 ps
T2710 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.921743865 Jun 28 05:40:31 PM PDT 24 Jun 28 05:40:36 PM PDT 24 453167155 ps
T2711 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2769205894 Jun 28 05:40:26 PM PDT 24 Jun 28 05:40:30 PM PDT 24 401711263 ps
T2712 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.233809469 Jun 28 05:40:12 PM PDT 24 Jun 28 05:40:16 PM PDT 24 467267847 ps
T2713 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3993164754 Jun 28 05:40:34 PM PDT 24 Jun 28 05:40:39 PM PDT 24 59163158 ps
T2714 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.419244761 Jun 28 05:40:55 PM PDT 24 Jun 28 05:41:01 PM PDT 24 66062473 ps
T2715 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1681395353 Jun 28 05:40:34 PM PDT 24 Jun 28 05:40:43 PM PDT 24 1000115896 ps
T2716 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.4112283397 Jun 28 05:40:32 PM PDT 24 Jun 28 05:40:37 PM PDT 24 45789431 ps
T2717 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3342711184 Jun 28 05:40:32 PM PDT 24 Jun 28 05:40:37 PM PDT 24 265564934 ps
T2718 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2962934972 Jun 28 05:40:32 PM PDT 24 Jun 28 05:40:36 PM PDT 24 84197117 ps
T2719 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1574164975 Jun 28 05:40:31 PM PDT 24 Jun 28 05:40:35 PM PDT 24 201620357 ps
T2720 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1459896182 Jun 28 05:40:30 PM PDT 24 Jun 28 05:40:34 PM PDT 24 197668198 ps
T2721 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3199366386 Jun 28 05:40:31 PM PDT 24 Jun 28 05:40:34 PM PDT 24 162846758 ps
T2722 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2779514261 Jun 28 05:40:34 PM PDT 24 Jun 28 05:40:39 PM PDT 24 121232459 ps
T2723 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2476519806 Jun 28 05:40:37 PM PDT 24 Jun 28 05:40:45 PM PDT 24 177743060 ps
T2724 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.4062549372 Jun 28 05:40:26 PM PDT 24 Jun 28 05:40:28 PM PDT 24 55393873 ps
T2725 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1302917369 Jun 28 05:40:34 PM PDT 24 Jun 28 05:40:40 PM PDT 24 119605435 ps
T2726 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1408143138 Jun 28 05:40:33 PM PDT 24 Jun 28 05:40:39 PM PDT 24 148407868 ps
T2727 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.188042062 Jun 28 05:41:01 PM PDT 24 Jun 28 05:41:08 PM PDT 24 102881202 ps
T2728 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1105519273 Jun 28 05:40:33 PM PDT 24 Jun 28 05:40:39 PM PDT 24 43613663 ps
T2729 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.182215887 Jun 28 05:40:35 PM PDT 24 Jun 28 05:40:41 PM PDT 24 46313997 ps
T2730 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.517236519 Jun 28 05:40:22 PM PDT 24 Jun 28 05:40:25 PM PDT 24 91789124 ps
T2731 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2880562260 Jun 28 05:40:23 PM PDT 24 Jun 28 05:40:24 PM PDT 24 44634316 ps
T2732 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.69805870 Jun 28 05:40:31 PM PDT 24 Jun 28 05:40:36 PM PDT 24 384158232 ps
T2733 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3452596629 Jun 28 05:40:53 PM PDT 24 Jun 28 05:40:58 PM PDT 24 66186297 ps
T2734 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1505936333 Jun 28 05:40:13 PM PDT 24 Jun 28 05:40:16 PM PDT 24 144580419 ps
T2735 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1629110193 Jun 28 05:40:39 PM PDT 24 Jun 28 05:40:46 PM PDT 24 40192993 ps
T2736 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2812695453 Jun 28 05:40:42 PM PDT 24 Jun 28 05:40:48 PM PDT 24 41722006 ps

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.948302206
Short name T6
Test name
Test status
Simulation time 13396629317 ps
CPU time 11.52 seconds
Started Jun 28 06:09:40 PM PDT 24
Finished Jun 28 06:09:56 PM PDT 24
Peak memory 206276 kb
Host smart-d0e3496f-017a-4332-bfbc-89e3ccc5913f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=948302206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.948302206
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_invalid_sync.664122137
Short name T4
Test name
Test status
Simulation time 7553185077 ps
CPU time 212.6 seconds
Started Jun 28 06:13:55 PM PDT 24
Finished Jun 28 06:17:31 PM PDT 24
Peak memory 206476 kb
Host smart-c5ad4f21-cddd-4864-86cb-84baa5831677
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=664122137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.664122137
Directory /workspace/35.usbdev_invalid_sync/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1061103345
Short name T210
Test name
Test status
Simulation time 49670661 ps
CPU time 0.73 seconds
Started Jun 28 05:40:33 PM PDT 24
Finished Jun 28 05:40:39 PM PDT 24
Peak memory 205792 kb
Host smart-78978578-a7e3-4c56-842c-2921977a700a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1061103345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.1061103345
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.2889510891
Short name T76
Test name
Test status
Simulation time 20726469472 ps
CPU time 44.07 seconds
Started Jun 28 06:11:31 PM PDT 24
Finished Jun 28 06:12:18 PM PDT 24
Peak memory 206448 kb
Host smart-389db6b4-8884-4ff4-a301-9adcdd5ffffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28895
10891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.2889510891
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.3930740403
Short name T203
Test name
Test status
Simulation time 1015112036 ps
CPU time 4.68 seconds
Started Jun 28 05:40:33 PM PDT 24
Finished Jun 28 05:40:43 PM PDT 24
Peak memory 206076 kb
Host smart-0d455c27-3890-41ea-ad06-972083689d4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3930740403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.3930740403
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.2020580696
Short name T1
Test name
Test status
Simulation time 184073531 ps
CPU time 0.82 seconds
Started Jun 28 06:09:23 PM PDT 24
Finished Jun 28 06:09:28 PM PDT 24
Peak memory 206152 kb
Host smart-ccdbb40b-c48d-48b6-979f-0006efaa3121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20205
80696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.2020580696
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.3194508621
Short name T92
Test name
Test status
Simulation time 207318256 ps
CPU time 0.85 seconds
Started Jun 28 06:09:53 PM PDT 24
Finished Jun 28 06:09:57 PM PDT 24
Peak memory 206144 kb
Host smart-4e4affca-bc62-4e4d-bc6a-20041d39e732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31945
08621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.3194508621
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_device_address.2169603717
Short name T82
Test name
Test status
Simulation time 22184731458 ps
CPU time 41.34 seconds
Started Jun 28 06:13:57 PM PDT 24
Finished Jun 28 06:14:42 PM PDT 24
Peak memory 206408 kb
Host smart-c4407824-3c96-4417-bf07-6ad4e3d386f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21696
03717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.2169603717
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.516215524
Short name T296
Test name
Test status
Simulation time 113422449 ps
CPU time 0.75 seconds
Started Jun 28 05:40:41 PM PDT 24
Finished Jun 28 05:40:47 PM PDT 24
Peak memory 205792 kb
Host smart-82cb58ed-ca1b-4172-a429-51a2f9fb7c9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=516215524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.516215524
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.348648443
Short name T30
Test name
Test status
Simulation time 193688968 ps
CPU time 0.9 seconds
Started Jun 28 06:08:25 PM PDT 24
Finished Jun 28 06:08:28 PM PDT 24
Peak memory 206204 kb
Host smart-aae5901b-40e5-444d-a1c4-5ee09e3785eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34864
8443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.348648443
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.468666433
Short name T227
Test name
Test status
Simulation time 163593772 ps
CPU time 2.04 seconds
Started Jun 28 05:40:33 PM PDT 24
Finished Jun 28 05:40:39 PM PDT 24
Peak memory 222016 kb
Host smart-02ba481f-ef7f-4130-8b8d-3bcae7468320
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=468666433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.468666433
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.1453898526
Short name T7
Test name
Test status
Simulation time 23382918564 ps
CPU time 22.83 seconds
Started Jun 28 06:09:13 PM PDT 24
Finished Jun 28 06:09:38 PM PDT 24
Peak memory 206324 kb
Host smart-6fe8bf1c-57ec-4144-adf5-ddd6838848f0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1453898526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.1453898526
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.3531602823
Short name T200
Test name
Test status
Simulation time 1866614715 ps
CPU time 2.63 seconds
Started Jun 28 06:08:56 PM PDT 24
Finished Jun 28 06:09:03 PM PDT 24
Peak memory 225092 kb
Host smart-a8fe6eb8-6340-4442-94fa-b483b86bd3e0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3531602823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.3531602823
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.2424302084
Short name T745
Test name
Test status
Simulation time 246694864 ps
CPU time 1 seconds
Started Jun 28 06:11:10 PM PDT 24
Finished Jun 28 06:11:15 PM PDT 24
Peak memory 206192 kb
Host smart-7ccded8c-d3fc-4bc8-a443-38c7f87584a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24243
02084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.2424302084
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.478730879
Short name T23
Test name
Test status
Simulation time 75249683 ps
CPU time 0.7 seconds
Started Jun 28 06:10:37 PM PDT 24
Finished Jun 28 06:10:42 PM PDT 24
Peak memory 206200 kb
Host smart-f124d429-1506-4556-95ea-5513db04a13b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47873
0879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.478730879
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.598958032
Short name T377
Test name
Test status
Simulation time 148956184 ps
CPU time 0.76 seconds
Started Jun 28 06:10:39 PM PDT 24
Finished Jun 28 06:10:44 PM PDT 24
Peak memory 206156 kb
Host smart-0476e9e4-de23-4b1f-84ed-d9deeb3cf19b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59895
8032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.598958032
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.2608268932
Short name T297
Test name
Test status
Simulation time 41242520 ps
CPU time 0.72 seconds
Started Jun 28 05:40:22 PM PDT 24
Finished Jun 28 05:40:23 PM PDT 24
Peak memory 205844 kb
Host smart-a9dee57e-8b38-4fa0-93e3-e5607715e315
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2608268932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.2608268932
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.2127272163
Short name T74
Test name
Test status
Simulation time 340441313 ps
CPU time 1.2 seconds
Started Jun 28 06:08:24 PM PDT 24
Finished Jun 28 06:08:29 PM PDT 24
Peak memory 206196 kb
Host smart-8b0ed781-fbb7-41d9-b4eb-5f22146124c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21272
72163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.2127272163
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.1026043555
Short name T39
Test name
Test status
Simulation time 20216493181 ps
CPU time 19.82 seconds
Started Jun 28 06:08:30 PM PDT 24
Finished Jun 28 06:08:52 PM PDT 24
Peak memory 206308 kb
Host smart-cfb944f7-573e-4aae-9a91-355a6b7a593c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10260
43555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.1026043555
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.3151986421
Short name T28
Test name
Test status
Simulation time 1064688700 ps
CPU time 2.37 seconds
Started Jun 28 06:13:02 PM PDT 24
Finished Jun 28 06:13:12 PM PDT 24
Peak memory 206296 kb
Host smart-e058535c-0174-44d4-95c9-26490eda4496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31519
86421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.3151986421
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1927732161
Short name T212
Test name
Test status
Simulation time 57165017 ps
CPU time 0.7 seconds
Started Jun 28 05:40:36 PM PDT 24
Finished Jun 28 05:40:42 PM PDT 24
Peak memory 205844 kb
Host smart-54e46f4d-04cb-4b86-8cae-b1484f0b364d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1927732161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.1927732161
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1088530906
Short name T265
Test name
Test status
Simulation time 73646565 ps
CPU time 1.32 seconds
Started Jun 28 05:40:17 PM PDT 24
Finished Jun 28 05:40:20 PM PDT 24
Peak memory 214256 kb
Host smart-b0bcfffa-c666-4ebf-97d0-4980591c8a9b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1088530906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.1088530906
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.345843139
Short name T140
Test name
Test status
Simulation time 5921953286 ps
CPU time 44.29 seconds
Started Jun 28 06:15:48 PM PDT 24
Finished Jun 28 06:16:37 PM PDT 24
Peak memory 206472 kb
Host smart-daec6793-e200-41cb-9124-3e0a60040511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34584
3139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.345843139
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.3682152014
Short name T69
Test name
Test status
Simulation time 192403734 ps
CPU time 0.83 seconds
Started Jun 28 06:10:02 PM PDT 24
Finished Jun 28 06:10:06 PM PDT 24
Peak memory 206196 kb
Host smart-28801572-90b1-439b-b509-66938b68df84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36821
52014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.3682152014
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.516314683
Short name T302
Test name
Test status
Simulation time 187309326 ps
CPU time 0.84 seconds
Started Jun 28 06:14:26 PM PDT 24
Finished Jun 28 06:14:32 PM PDT 24
Peak memory 206188 kb
Host smart-5f237b8c-57e8-4ac4-94db-d0ed45b1f087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51631
4683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.516314683
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3263822375
Short name T312
Test name
Test status
Simulation time 49482817 ps
CPU time 0.68 seconds
Started Jun 28 05:40:43 PM PDT 24
Finished Jun 28 05:40:49 PM PDT 24
Peak memory 205832 kb
Host smart-af708164-a626-4a3a-99a8-58ffc3480740
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3263822375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.3263822375
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1826853278
Short name T314
Test name
Test status
Simulation time 2040439911 ps
CPU time 6.1 seconds
Started Jun 28 05:40:33 PM PDT 24
Finished Jun 28 05:40:43 PM PDT 24
Peak memory 206080 kb
Host smart-56a96837-3188-4adf-a864-d87f0bbafe98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1826853278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.1826853278
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.1302283700
Short name T192
Test name
Test status
Simulation time 48939939 ps
CPU time 0.71 seconds
Started Jun 28 06:12:59 PM PDT 24
Finished Jun 28 06:13:03 PM PDT 24
Peak memory 206216 kb
Host smart-72351df9-69fd-43e4-92cb-58b9c3f5143e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1302283700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.1302283700
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1681395353
Short name T2715
Test name
Test status
Simulation time 1000115896 ps
CPU time 4.41 seconds
Started Jun 28 05:40:34 PM PDT 24
Finished Jun 28 05:40:43 PM PDT 24
Peak memory 205972 kb
Host smart-8701dd78-8b08-4a69-8fd4-31ed1788137e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1681395353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.1681395353
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1239014582
Short name T292
Test name
Test status
Simulation time 42593949 ps
CPU time 0.7 seconds
Started Jun 28 05:40:37 PM PDT 24
Finished Jun 28 05:40:43 PM PDT 24
Peak memory 205848 kb
Host smart-c6234bc1-8058-4a44-9dd4-8b74f981066a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1239014582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.1239014582
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.1466032432
Short name T161
Test name
Test status
Simulation time 8991897544 ps
CPU time 154.94 seconds
Started Jun 28 06:09:21 PM PDT 24
Finished Jun 28 06:12:00 PM PDT 24
Peak memory 206496 kb
Host smart-877e833f-0a55-4573-9b68-665c5b1be5cc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1466032432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.1466032432
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.1396514169
Short name T546
Test name
Test status
Simulation time 178506262 ps
CPU time 0.87 seconds
Started Jun 28 06:09:50 PM PDT 24
Finished Jun 28 06:09:53 PM PDT 24
Peak memory 206196 kb
Host smart-db696bac-aeb4-41d0-95ed-285bbbbd7ca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13965
14169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.1396514169
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.2747451823
Short name T65
Test name
Test status
Simulation time 524122023 ps
CPU time 1.4 seconds
Started Jun 28 06:08:11 PM PDT 24
Finished Jun 28 06:08:13 PM PDT 24
Peak memory 206220 kb
Host smart-6972026c-f8b1-4373-8e1c-c16e138b540b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27474
51823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.2747451823
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.3037899904
Short name T445
Test name
Test status
Simulation time 4350755429 ps
CPU time 5.39 seconds
Started Jun 28 06:10:13 PM PDT 24
Finished Jun 28 06:10:20 PM PDT 24
Peak memory 206332 kb
Host smart-34e72f1e-a324-4e15-beaa-c992ff521951
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3037899904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.3037899904
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.834048349
Short name T163
Test name
Test status
Simulation time 26163008740 ps
CPU time 214.96 seconds
Started Jun 28 06:08:25 PM PDT 24
Finished Jun 28 06:12:02 PM PDT 24
Peak memory 206452 kb
Host smart-c0b59270-e053-4cfe-8d80-99941c7d55ab
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=834048349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.834048349
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.122344079
Short name T2675
Test name
Test status
Simulation time 187379292 ps
CPU time 2.23 seconds
Started Jun 28 05:40:35 PM PDT 24
Finished Jun 28 05:40:43 PM PDT 24
Peak memory 214308 kb
Host smart-fd7af0aa-e62a-4908-9018-f6a2d4d7f8ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=122344079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.122344079
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.443252155
Short name T48
Test name
Test status
Simulation time 318438771 ps
CPU time 1.01 seconds
Started Jun 28 06:08:26 PM PDT 24
Finished Jun 28 06:08:30 PM PDT 24
Peak memory 206208 kb
Host smart-beb59acf-3785-47f1-a0c1-c4cdc28f4c2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44325
2155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.443252155
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.1291000666
Short name T59
Test name
Test status
Simulation time 163244769 ps
CPU time 0.81 seconds
Started Jun 28 06:08:12 PM PDT 24
Finished Jun 28 06:08:15 PM PDT 24
Peak memory 206172 kb
Host smart-a4d20ce5-6574-4142-a2f7-4efbf507f854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12910
00666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.1291000666
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.2998673667
Short name T159
Test name
Test status
Simulation time 1414539745 ps
CPU time 3.42 seconds
Started Jun 28 06:08:53 PM PDT 24
Finished Jun 28 06:09:00 PM PDT 24
Peak memory 206256 kb
Host smart-258f6154-bfec-444c-997c-39720f007841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29986
73667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.2998673667
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.1101490586
Short name T718
Test name
Test status
Simulation time 150835893 ps
CPU time 0.77 seconds
Started Jun 28 06:10:54 PM PDT 24
Finished Jun 28 06:11:01 PM PDT 24
Peak memory 206200 kb
Host smart-622d2a89-9bb2-4f0a-b367-130ef71c60c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11014
90586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.1101490586
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.2219051531
Short name T15
Test name
Test status
Simulation time 13321099619 ps
CPU time 13.23 seconds
Started Jun 28 06:11:16 PM PDT 24
Finished Jun 28 06:11:31 PM PDT 24
Peak memory 206384 kb
Host smart-e681013a-6ba3-4e80-a695-3672365048fd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2219051531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.2219051531
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.3118114230
Short name T111
Test name
Test status
Simulation time 249297827 ps
CPU time 0.9 seconds
Started Jun 28 06:10:19 PM PDT 24
Finished Jun 28 06:10:23 PM PDT 24
Peak memory 206152 kb
Host smart-36be4fb5-c52a-4d01-95b6-c7ff88389040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31181
14230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.3118114230
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.530267912
Short name T191
Test name
Test status
Simulation time 317713765 ps
CPU time 2.22 seconds
Started Jun 28 06:10:04 PM PDT 24
Finished Jun 28 06:10:10 PM PDT 24
Peak memory 206364 kb
Host smart-234437fd-19bf-40e3-bce6-509021f1b109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53026
7912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.530267912
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_device_address.1632123089
Short name T84
Test name
Test status
Simulation time 12489626368 ps
CPU time 25.51 seconds
Started Jun 28 06:11:21 PM PDT 24
Finished Jun 28 06:11:50 PM PDT 24
Peak memory 206472 kb
Host smart-d399c1f0-f67e-4619-bcc0-a0c1046183eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16321
23089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.1632123089
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.1721725025
Short name T77
Test name
Test status
Simulation time 145118632 ps
CPU time 0.79 seconds
Started Jun 28 06:08:51 PM PDT 24
Finished Jun 28 06:08:56 PM PDT 24
Peak memory 206164 kb
Host smart-7cfd1161-e361-447c-a719-dbd78c152aff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17217
25025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.1721725025
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.731838661
Short name T51
Test name
Test status
Simulation time 152118429 ps
CPU time 0.82 seconds
Started Jun 28 06:08:13 PM PDT 24
Finished Jun 28 06:08:15 PM PDT 24
Peak memory 206180 kb
Host smart-b2790e73-b40e-47e0-ae2f-c3e23201df31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73183
8661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.731838661
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.792858813
Short name T60
Test name
Test status
Simulation time 4172166585 ps
CPU time 9.07 seconds
Started Jun 28 06:08:18 PM PDT 24
Finished Jun 28 06:08:28 PM PDT 24
Peak memory 206568 kb
Host smart-cfcc38ce-8063-4968-96fc-5bdce575e6c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79285
8813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.792858813
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.1136585899
Short name T61
Test name
Test status
Simulation time 174863141 ps
CPU time 0.81 seconds
Started Jun 28 06:08:11 PM PDT 24
Finished Jun 28 06:08:14 PM PDT 24
Peak memory 206200 kb
Host smart-34ddfd1a-324e-417f-b354-5f7ec14917be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11365
85899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.1136585899
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.965998100
Short name T2496
Test name
Test status
Simulation time 155538626 ps
CPU time 0.8 seconds
Started Jun 28 06:08:25 PM PDT 24
Finished Jun 28 06:08:29 PM PDT 24
Peak memory 206192 kb
Host smart-12c23674-de5f-41f6-9b60-9f1e2fdf3011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96599
8100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.965998100
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.1523383156
Short name T44
Test name
Test status
Simulation time 171004239 ps
CPU time 0.8 seconds
Started Jun 28 06:08:25 PM PDT 24
Finished Jun 28 06:08:29 PM PDT 24
Peak memory 206204 kb
Host smart-d03396d8-5166-4a00-85bc-a7f0e03ecba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15233
83156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.1523383156
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/10.usbdev_smoke.3846002750
Short name T22
Test name
Test status
Simulation time 198432170 ps
CPU time 0.85 seconds
Started Jun 28 06:10:03 PM PDT 24
Finished Jun 28 06:10:07 PM PDT 24
Peak memory 206184 kb
Host smart-ac1a3bf6-6689-4cfa-bfc9-6e007d33d2b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38460
02750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.3846002750
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.1417818575
Short name T663
Test name
Test status
Simulation time 72278230 ps
CPU time 0.65 seconds
Started Jun 28 06:10:17 PM PDT 24
Finished Jun 28 06:10:21 PM PDT 24
Peak memory 206208 kb
Host smart-2acd3d0e-e05c-40f3-bfa2-72e388c8f342
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14178
18575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.1417818575
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.1805021169
Short name T150
Test name
Test status
Simulation time 6414351281 ps
CPU time 179.86 seconds
Started Jun 28 06:10:51 PM PDT 24
Finished Jun 28 06:13:57 PM PDT 24
Peak memory 206492 kb
Host smart-3daa5b0f-2eb0-4112-ba28-948266ac785b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18050
21169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.1805021169
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.2351277744
Short name T90
Test name
Test status
Simulation time 19072487581 ps
CPU time 167.75 seconds
Started Jun 28 06:09:13 PM PDT 24
Finished Jun 28 06:12:03 PM PDT 24
Peak memory 206584 kb
Host smart-7d291c78-e18a-4879-98c9-010a434b2ded
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2351277744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.2351277744
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2039737585
Short name T205
Test name
Test status
Simulation time 118352851 ps
CPU time 1.69 seconds
Started Jun 28 05:40:15 PM PDT 24
Finished Jun 28 05:40:17 PM PDT 24
Peak memory 221896 kb
Host smart-ebc51b00-513a-448a-80b2-63c314aed1c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2039737585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.2039737585
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.2488026895
Short name T1562
Test name
Test status
Simulation time 1346788823 ps
CPU time 3.15 seconds
Started Jun 28 06:08:12 PM PDT 24
Finished Jun 28 06:08:17 PM PDT 24
Peak memory 206300 kb
Host smart-37d38c25-3d69-401c-941d-621dea1c9a26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24880
26895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.2488026895
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.1582992662
Short name T1949
Test name
Test status
Simulation time 235980759 ps
CPU time 1.03 seconds
Started Jun 28 06:08:24 PM PDT 24
Finished Jun 28 06:08:28 PM PDT 24
Peak memory 206196 kb
Host smart-481c070f-d77e-499a-a2c0-e4ead6f218ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15829
92662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.1582992662
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.1873139529
Short name T1930
Test name
Test status
Simulation time 451400007 ps
CPU time 1.41 seconds
Started Jun 28 06:08:23 PM PDT 24
Finished Jun 28 06:08:26 PM PDT 24
Peak memory 206188 kb
Host smart-0243b38a-845d-4ed8-894d-539dfb128666
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18731
39529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.1873139529
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.4286706882
Short name T109
Test name
Test status
Simulation time 248241970 ps
CPU time 0.91 seconds
Started Jun 28 06:08:37 PM PDT 24
Finished Jun 28 06:08:39 PM PDT 24
Peak memory 206216 kb
Host smart-22cd3963-ec38-4b10-b600-cf3ae2c735c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42867
06882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.4286706882
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.596702773
Short name T167
Test name
Test status
Simulation time 10169546417 ps
CPU time 61.64 seconds
Started Jun 28 06:08:38 PM PDT 24
Finished Jun 28 06:09:41 PM PDT 24
Peak memory 206504 kb
Host smart-e49ee137-e8fb-46c1-9a84-06636342994b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=596702773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.596702773
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/10.usbdev_invalid_sync.1893990954
Short name T101
Test name
Test status
Simulation time 5892572432 ps
CPU time 52.72 seconds
Started Jun 28 06:09:53 PM PDT 24
Finished Jun 28 06:10:50 PM PDT 24
Peak memory 206416 kb
Host smart-f3aa2b2c-11e4-494d-a6c7-15f27a5f0414
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1893990954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.1893990954
Directory /workspace/10.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.3023051448
Short name T114
Test name
Test status
Simulation time 171502745 ps
CPU time 0.85 seconds
Started Jun 28 06:10:06 PM PDT 24
Finished Jun 28 06:10:10 PM PDT 24
Peak memory 206204 kb
Host smart-64ecbcaa-4e2b-4733-a4fa-b06ddc1f33fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30230
51448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.3023051448
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.3178961470
Short name T2414
Test name
Test status
Simulation time 23477926715 ps
CPU time 23.43 seconds
Started Jun 28 06:10:37 PM PDT 24
Finished Jun 28 06:11:03 PM PDT 24
Peak memory 206480 kb
Host smart-168fb95c-fcf7-4b78-a77b-6d1addc89ae4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3178961470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.3178961470
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.3619948082
Short name T132
Test name
Test status
Simulation time 209756232 ps
CPU time 0.88 seconds
Started Jun 28 06:10:35 PM PDT 24
Finished Jun 28 06:10:38 PM PDT 24
Peak memory 206200 kb
Host smart-662a03c1-744f-470d-b1b3-f2fa5cd33299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36199
48082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.3619948082
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.2213548747
Short name T1279
Test name
Test status
Simulation time 23455189237 ps
CPU time 57.31 seconds
Started Jun 28 06:10:36 PM PDT 24
Finished Jun 28 06:11:36 PM PDT 24
Peak memory 206468 kb
Host smart-628bae9d-eaf2-4816-adc4-ff4d29d3d7c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22135
48747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.2213548747
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.3955051514
Short name T124
Test name
Test status
Simulation time 227632056 ps
CPU time 0.87 seconds
Started Jun 28 06:10:54 PM PDT 24
Finished Jun 28 06:11:01 PM PDT 24
Peak memory 206192 kb
Host smart-63c258e6-a111-4809-b427-8d48d86675b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39550
51514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.3955051514
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.1015067995
Short name T181
Test name
Test status
Simulation time 1050346546 ps
CPU time 2.48 seconds
Started Jun 28 06:10:51 PM PDT 24
Finished Jun 28 06:10:59 PM PDT 24
Peak memory 206276 kb
Host smart-d458693c-2afe-4dc0-99c4-dc81f8e75ca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10150
67995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.1015067995
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.4241695234
Short name T137
Test name
Test status
Simulation time 206974664 ps
CPU time 0.89 seconds
Started Jun 28 06:10:55 PM PDT 24
Finished Jun 28 06:11:02 PM PDT 24
Peak memory 206348 kb
Host smart-289c3e40-e4a8-479c-b1cb-86533c08fd5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42416
95234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.4241695234
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.2742110699
Short name T116
Test name
Test status
Simulation time 247390196 ps
CPU time 0.91 seconds
Started Jun 28 06:11:09 PM PDT 24
Finished Jun 28 06:11:14 PM PDT 24
Peak memory 206156 kb
Host smart-a570c58d-ee29-43d9-9749-e824e5d5db6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27421
10699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.2742110699
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.4194262750
Short name T126
Test name
Test status
Simulation time 213566650 ps
CPU time 0.83 seconds
Started Jun 28 06:08:39 PM PDT 24
Finished Jun 28 06:08:43 PM PDT 24
Peak memory 206216 kb
Host smart-0f3bda74-1b53-4798-ba20-04b4eb201636
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41942
62750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.4194262750
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.90225972
Short name T129
Test name
Test status
Simulation time 254635810 ps
CPU time 0.93 seconds
Started Jun 28 06:11:31 PM PDT 24
Finished Jun 28 06:11:36 PM PDT 24
Peak memory 206204 kb
Host smart-e62e9c8b-da24-4bf1-9398-50066e9c82ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90225
972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.90225972
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.3999359011
Short name T138
Test name
Test status
Simulation time 235938989 ps
CPU time 0.93 seconds
Started Jun 28 06:11:41 PM PDT 24
Finished Jun 28 06:11:43 PM PDT 24
Peak memory 206180 kb
Host smart-8e59319e-20ac-43bc-b8fb-eef9593d77e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39993
59011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.3999359011
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.1442595173
Short name T122
Test name
Test status
Simulation time 269119687 ps
CPU time 0.98 seconds
Started Jun 28 06:12:04 PM PDT 24
Finished Jun 28 06:12:11 PM PDT 24
Peak memory 206196 kb
Host smart-d306a55c-a37e-4fcc-94ea-e80f5befc02e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14425
95173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.1442595173
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.147394104
Short name T175
Test name
Test status
Simulation time 455323485 ps
CPU time 1.48 seconds
Started Jun 28 06:12:25 PM PDT 24
Finished Jun 28 06:12:34 PM PDT 24
Peak memory 206164 kb
Host smart-455c6ed5-f78b-4f0e-8e25-2e63ed3e160c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14739
4104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.147394104
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.981664629
Short name T2671
Test name
Test status
Simulation time 385646762 ps
CPU time 3.74 seconds
Started Jun 28 05:40:33 PM PDT 24
Finished Jun 28 05:40:42 PM PDT 24
Peak memory 206012 kb
Host smart-d9b4c7d1-9a25-4ebe-a7a4-0abd9bfffac8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=981664629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.981664629
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1232424906
Short name T271
Test name
Test status
Simulation time 492670661 ps
CPU time 7.67 seconds
Started Jun 28 05:40:18 PM PDT 24
Finished Jun 28 05:40:32 PM PDT 24
Peak memory 206076 kb
Host smart-55637cd5-7f4d-4c19-aa53-83dd5bd6e1a6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1232424906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.1232424906
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.708073445
Short name T272
Test name
Test status
Simulation time 94055190 ps
CPU time 0.86 seconds
Started Jun 28 05:40:13 PM PDT 24
Finished Jun 28 05:40:15 PM PDT 24
Peak memory 205896 kb
Host smart-42ab784d-af2c-4299-8517-4b1fb6c28f02
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=708073445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.708073445
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.333179534
Short name T248
Test name
Test status
Simulation time 118477831 ps
CPU time 1.32 seconds
Started Jun 28 05:40:40 PM PDT 24
Finished Jun 28 05:40:47 PM PDT 24
Peak memory 214228 kb
Host smart-27db42c2-5674-4db9-a455-879e0848e55b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333179534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev
_csr_mem_rw_with_rand_reset.333179534
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.179644407
Short name T2700
Test name
Test status
Simulation time 41727448 ps
CPU time 0.92 seconds
Started Jun 28 05:40:10 PM PDT 24
Finished Jun 28 05:40:11 PM PDT 24
Peak memory 205948 kb
Host smart-e81383ff-a205-4f83-93fd-457b10a84681
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=179644407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.179644407
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2812162223
Short name T2695
Test name
Test status
Simulation time 277617902 ps
CPU time 2.64 seconds
Started Jun 28 05:40:12 PM PDT 24
Finished Jun 28 05:40:16 PM PDT 24
Peak memory 205992 kb
Host smart-462e61c2-8655-4e0b-93f6-26f16cdabedb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2812162223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.2812162223
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.517236519
Short name T2730
Test name
Test status
Simulation time 91789124 ps
CPU time 1.51 seconds
Started Jun 28 05:40:22 PM PDT 24
Finished Jun 28 05:40:25 PM PDT 24
Peak memory 205984 kb
Host smart-28d45c9d-dba9-40c2-9b45-9ee52f365f3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=517236519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.517236519
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.233809469
Short name T2712
Test name
Test status
Simulation time 467267847 ps
CPU time 3 seconds
Started Jun 28 05:40:12 PM PDT 24
Finished Jun 28 05:40:16 PM PDT 24
Peak memory 206032 kb
Host smart-bf3e2db9-fc59-452c-9b92-312514e8ec68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=233809469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.233809469
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.863275774
Short name T2669
Test name
Test status
Simulation time 129441646 ps
CPU time 2.08 seconds
Started Jun 28 05:40:15 PM PDT 24
Finished Jun 28 05:40:18 PM PDT 24
Peak memory 206028 kb
Host smart-de25e8ca-b07a-4e4b-b03e-74c7595e6cd3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=863275774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.863275774
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.260676670
Short name T277
Test name
Test status
Simulation time 3155722587 ps
CPU time 13.27 seconds
Started Jun 28 05:40:11 PM PDT 24
Finished Jun 28 05:40:25 PM PDT 24
Peak memory 206160 kb
Host smart-ab708ed2-0921-4f9c-a2ca-40a9348de195
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=260676670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.260676670
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.4268839746
Short name T273
Test name
Test status
Simulation time 194935269 ps
CPU time 0.91 seconds
Started Jun 28 05:40:20 PM PDT 24
Finished Jun 28 05:40:22 PM PDT 24
Peak memory 205860 kb
Host smart-acf7b8ae-69c0-4be4-9990-35bdb47427bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4268839746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.4268839746
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2810998915
Short name T2692
Test name
Test status
Simulation time 145790685 ps
CPU time 1.73 seconds
Started Jun 28 05:40:13 PM PDT 24
Finished Jun 28 05:40:15 PM PDT 24
Peak memory 214256 kb
Host smart-0da4da34-b527-44c3-994c-1c8ec1131637
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810998915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.2810998915
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.4062549372
Short name T2724
Test name
Test status
Simulation time 55393873 ps
CPU time 0.87 seconds
Started Jun 28 05:40:26 PM PDT 24
Finished Jun 28 05:40:28 PM PDT 24
Peak memory 205864 kb
Host smart-90e0b6de-1e44-4caf-9e31-a157550a0f8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4062549372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.4062549372
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.679856834
Short name T2636
Test name
Test status
Simulation time 46244178 ps
CPU time 0.68 seconds
Started Jun 28 05:40:29 PM PDT 24
Finished Jun 28 05:40:32 PM PDT 24
Peak memory 205844 kb
Host smart-12c008ad-15fb-4a20-9210-6e10be126538
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=679856834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.679856834
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2304092855
Short name T2676
Test name
Test status
Simulation time 58040075 ps
CPU time 1.36 seconds
Started Jun 28 05:40:32 PM PDT 24
Finished Jun 28 05:40:36 PM PDT 24
Peak memory 214264 kb
Host smart-a9e10360-7115-423a-b824-9efdb171db4d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2304092855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2304092855
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1505936333
Short name T2734
Test name
Test status
Simulation time 144580419 ps
CPU time 2.46 seconds
Started Jun 28 05:40:13 PM PDT 24
Finished Jun 28 05:40:16 PM PDT 24
Peak memory 206028 kb
Host smart-f3a4c1d6-e8c8-42c9-b802-7e9ab34d2cf6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1505936333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.1505936333
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.462121757
Short name T279
Test name
Test status
Simulation time 73766425 ps
CPU time 1.07 seconds
Started Jun 28 05:40:32 PM PDT 24
Finished Jun 28 05:40:37 PM PDT 24
Peak memory 206088 kb
Host smart-c3469b1a-e71b-42e3-95fb-dfc78e6c7bf2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=462121757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.462121757
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.348733261
Short name T237
Test name
Test status
Simulation time 343464507 ps
CPU time 3.19 seconds
Started Jun 28 05:40:23 PM PDT 24
Finished Jun 28 05:40:27 PM PDT 24
Peak memory 206104 kb
Host smart-2f89cdec-6e55-40cb-847b-99cfcb7f5e85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=348733261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.348733261
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.486387591
Short name T246
Test name
Test status
Simulation time 1295068356 ps
CPU time 3.36 seconds
Started Jun 28 05:40:26 PM PDT 24
Finished Jun 28 05:40:30 PM PDT 24
Peak memory 205904 kb
Host smart-694342cf-35de-4403-b5ba-e951d0e7905b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=486387591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.486387591
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1349257210
Short name T2642
Test name
Test status
Simulation time 98445750 ps
CPU time 1.44 seconds
Started Jun 28 05:40:35 PM PDT 24
Finished Jun 28 05:40:42 PM PDT 24
Peak memory 214340 kb
Host smart-21ffc67a-d956-418c-bb49-19b15b1b0742
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349257210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.1349257210
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2790706474
Short name T276
Test name
Test status
Simulation time 61793621 ps
CPU time 0.8 seconds
Started Jun 28 05:40:34 PM PDT 24
Finished Jun 28 05:40:40 PM PDT 24
Peak memory 205924 kb
Host smart-48219458-8e30-469d-a889-8eebf52f72d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2790706474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.2790706474
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.1310555636
Short name T2635
Test name
Test status
Simulation time 85922420 ps
CPU time 0.74 seconds
Started Jun 28 05:40:46 PM PDT 24
Finished Jun 28 05:40:51 PM PDT 24
Peak memory 205848 kb
Host smart-b179b41f-d3b4-47b6-8855-c7bbb91c9d28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1310555636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.1310555636
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2401698094
Short name T2686
Test name
Test status
Simulation time 100577292 ps
CPU time 1.14 seconds
Started Jun 28 05:40:53 PM PDT 24
Finished Jun 28 05:40:57 PM PDT 24
Peak memory 206060 kb
Host smart-6958a06b-8573-4d9d-98ad-ec25cbd2e0e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2401698094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.2401698094
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1574164975
Short name T2719
Test name
Test status
Simulation time 201620357 ps
CPU time 1.81 seconds
Started Jun 28 05:40:31 PM PDT 24
Finished Jun 28 05:40:35 PM PDT 24
Peak memory 221944 kb
Host smart-65fca5d0-d727-4c7d-aca0-9ae5264e7917
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1574164975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.1574164975
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2000788517
Short name T2656
Test name
Test status
Simulation time 158918072 ps
CPU time 1.21 seconds
Started Jun 28 05:40:46 PM PDT 24
Finished Jun 28 05:40:52 PM PDT 24
Peak memory 215816 kb
Host smart-e592284c-ff74-458b-b22c-e31a75329f23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000788517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.2000788517
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1408143138
Short name T2726
Test name
Test status
Simulation time 148407868 ps
CPU time 1.07 seconds
Started Jun 28 05:40:33 PM PDT 24
Finished Jun 28 05:40:39 PM PDT 24
Peak memory 206028 kb
Host smart-5cd646d6-8278-48c0-aca6-7fc2331f8f9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1408143138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.1408143138
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1800002430
Short name T2651
Test name
Test status
Simulation time 36785816 ps
CPU time 0.66 seconds
Started Jun 28 05:40:35 PM PDT 24
Finished Jun 28 05:40:41 PM PDT 24
Peak memory 205812 kb
Host smart-c592d77b-d26b-4e0e-9bf6-346de1d2fa82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1800002430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.1800002430
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3993164754
Short name T2713
Test name
Test status
Simulation time 59163158 ps
CPU time 1.03 seconds
Started Jun 28 05:40:34 PM PDT 24
Finished Jun 28 05:40:39 PM PDT 24
Peak memory 205980 kb
Host smart-4bb1bcf0-fed4-43db-8889-b5eb8bbacdea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3993164754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.3993164754
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.682082408
Short name T2694
Test name
Test status
Simulation time 201974551 ps
CPU time 1.71 seconds
Started Jun 28 05:40:34 PM PDT 24
Finished Jun 28 05:40:40 PM PDT 24
Peak memory 221984 kb
Host smart-bbf9a049-99f0-4898-8a0d-3076e0adca13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=682082408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.682082408
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.442594181
Short name T2670
Test name
Test status
Simulation time 525421013 ps
CPU time 2.71 seconds
Started Jun 28 05:40:33 PM PDT 24
Finished Jun 28 05:40:40 PM PDT 24
Peak memory 206068 kb
Host smart-0a33ae81-a5c0-4847-a0ad-92ed9cd1c1e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=442594181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.442594181
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3139206929
Short name T2649
Test name
Test status
Simulation time 58550992 ps
CPU time 1.35 seconds
Started Jun 28 05:40:45 PM PDT 24
Finished Jun 28 05:40:51 PM PDT 24
Peak memory 214328 kb
Host smart-b51835d1-fb69-4bf7-8f33-1fcdbc5127f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139206929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.3139206929
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.1516551634
Short name T270
Test name
Test status
Simulation time 76623868 ps
CPU time 1 seconds
Started Jun 28 05:40:45 PM PDT 24
Finished Jun 28 05:40:52 PM PDT 24
Peak memory 206028 kb
Host smart-1a29d544-3755-49e5-9fb7-30439c93c107
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1516551634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.1516551634
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1629110193
Short name T2735
Test name
Test status
Simulation time 40192993 ps
CPU time 0.66 seconds
Started Jun 28 05:40:39 PM PDT 24
Finished Jun 28 05:40:46 PM PDT 24
Peak memory 205844 kb
Host smart-a2fb3ea7-bf6d-452b-b962-6151744b1aca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1629110193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.1629110193
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3079076715
Short name T2698
Test name
Test status
Simulation time 188976288 ps
CPU time 1.6 seconds
Started Jun 28 05:40:46 PM PDT 24
Finished Jun 28 05:40:52 PM PDT 24
Peak memory 206000 kb
Host smart-93307d4e-29ea-4be2-8165-49ddc86aefe5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3079076715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3079076715
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2769205894
Short name T2711
Test name
Test status
Simulation time 401711263 ps
CPU time 3.54 seconds
Started Jun 28 05:40:26 PM PDT 24
Finished Jun 28 05:40:30 PM PDT 24
Peak memory 222268 kb
Host smart-04d7223c-4e4a-45a8-9eff-0b58ebb3d377
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2769205894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2769205894
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.921743865
Short name T2710
Test name
Test status
Simulation time 453167155 ps
CPU time 2.62 seconds
Started Jun 28 05:40:31 PM PDT 24
Finished Jun 28 05:40:36 PM PDT 24
Peak memory 205988 kb
Host smart-db039ab7-8463-4eb2-ac06-da723c84b4ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=921743865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.921743865
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1948394834
Short name T286
Test name
Test status
Simulation time 97967980 ps
CPU time 1.26 seconds
Started Jun 28 05:40:37 PM PDT 24
Finished Jun 28 05:40:44 PM PDT 24
Peak memory 214260 kb
Host smart-b06c5a48-85a0-434c-a46b-a248a6b90885
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948394834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.1948394834
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.350806999
Short name T2640
Test name
Test status
Simulation time 57491141 ps
CPU time 0.87 seconds
Started Jun 28 05:40:32 PM PDT 24
Finished Jun 28 05:40:37 PM PDT 24
Peak memory 205944 kb
Host smart-0253c3be-8ab1-451a-9a6e-6151e4919766
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=350806999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.350806999
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.321383947
Short name T295
Test name
Test status
Simulation time 53645373 ps
CPU time 0.71 seconds
Started Jun 28 05:40:37 PM PDT 24
Finished Jun 28 05:40:43 PM PDT 24
Peak memory 205852 kb
Host smart-0253b768-f578-4a9d-bfc4-2ddfad481686
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=321383947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.321383947
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3310447529
Short name T2678
Test name
Test status
Simulation time 143475293 ps
CPU time 1.13 seconds
Started Jun 28 05:40:54 PM PDT 24
Finished Jun 28 05:40:58 PM PDT 24
Peak memory 206012 kb
Host smart-30846354-2e64-48a7-b0ff-fb08de09aa96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3310447529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.3310447529
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.1661905823
Short name T2708
Test name
Test status
Simulation time 166752574 ps
CPU time 1.69 seconds
Started Jun 28 05:40:40 PM PDT 24
Finished Jun 28 05:40:47 PM PDT 24
Peak memory 221632 kb
Host smart-802f03e2-6d60-4d4e-a4be-0de9a4f6b612
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1661905823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.1661905823
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3363820507
Short name T317
Test name
Test status
Simulation time 2071083824 ps
CPU time 6.32 seconds
Started Jun 28 05:40:50 PM PDT 24
Finished Jun 28 05:41:00 PM PDT 24
Peak memory 205992 kb
Host smart-23906300-701d-4e29-88c6-cbae40f681b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3363820507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.3363820507
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2176240157
Short name T2685
Test name
Test status
Simulation time 104663131 ps
CPU time 1.46 seconds
Started Jun 28 05:40:44 PM PDT 24
Finished Jun 28 05:40:51 PM PDT 24
Peak memory 214316 kb
Host smart-2f3b77aa-456f-4511-8450-0020a3c351ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176240157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.2176240157
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.210633205
Short name T2679
Test name
Test status
Simulation time 63597754 ps
CPU time 0.99 seconds
Started Jun 28 05:40:53 PM PDT 24
Finished Jun 28 05:40:57 PM PDT 24
Peak memory 206040 kb
Host smart-686a4a78-a5d7-402d-98a2-fe28f1933f45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=210633205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.210633205
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.434131031
Short name T313
Test name
Test status
Simulation time 90351585 ps
CPU time 0.74 seconds
Started Jun 28 05:40:46 PM PDT 24
Finished Jun 28 05:40:51 PM PDT 24
Peak memory 205844 kb
Host smart-8f981c65-469a-4c2e-a4c9-d180fd07231f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=434131031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.434131031
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.182711956
Short name T2682
Test name
Test status
Simulation time 191530454 ps
CPU time 1.48 seconds
Started Jun 28 05:40:31 PM PDT 24
Finished Jun 28 05:40:35 PM PDT 24
Peak memory 205996 kb
Host smart-ca2019a9-843c-4f1e-ab12-24d419da2ab2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=182711956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.182711956
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3743396344
Short name T2703
Test name
Test status
Simulation time 94748439 ps
CPU time 2.46 seconds
Started Jun 28 05:40:52 PM PDT 24
Finished Jun 28 05:40:58 PM PDT 24
Peak memory 221884 kb
Host smart-249a5af4-0d5d-46f6-af78-b4ab42c2d37f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3743396344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.3743396344
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2364161604
Short name T315
Test name
Test status
Simulation time 552786009 ps
CPU time 2.56 seconds
Started Jun 28 05:40:41 PM PDT 24
Finished Jun 28 05:40:49 PM PDT 24
Peak memory 206020 kb
Host smart-9e0b57e3-bd43-4181-b800-801503c2e3f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2364161604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.2364161604
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3550923734
Short name T238
Test name
Test status
Simulation time 95874177 ps
CPU time 2.56 seconds
Started Jun 28 05:40:41 PM PDT 24
Finished Jun 28 05:40:49 PM PDT 24
Peak memory 214208 kb
Host smart-c497fb1f-7f57-423b-adb1-520ad00383af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550923734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.3550923734
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3310683923
Short name T268
Test name
Test status
Simulation time 81813466 ps
CPU time 1.04 seconds
Started Jun 28 05:40:58 PM PDT 24
Finished Jun 28 05:41:04 PM PDT 24
Peak memory 205976 kb
Host smart-36f9ee08-6419-4359-84b5-c63e63ab705a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3310683923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.3310683923
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2960655988
Short name T2666
Test name
Test status
Simulation time 48322520 ps
CPU time 0.69 seconds
Started Jun 28 05:40:55 PM PDT 24
Finished Jun 28 05:40:59 PM PDT 24
Peak memory 205824 kb
Host smart-79c3985f-24d9-4bc1-b04e-549fcd1d7e74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2960655988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.2960655988
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.237061114
Short name T2687
Test name
Test status
Simulation time 67915107 ps
CPU time 0.97 seconds
Started Jun 28 05:40:34 PM PDT 24
Finished Jun 28 05:40:40 PM PDT 24
Peak memory 205992 kb
Host smart-5366711c-f04f-4a54-aba9-436b17a876a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=237061114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.237061114
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.188042062
Short name T2727
Test name
Test status
Simulation time 102881202 ps
CPU time 2.74 seconds
Started Jun 28 05:41:01 PM PDT 24
Finished Jun 28 05:41:08 PM PDT 24
Peak memory 222084 kb
Host smart-1c76c4c3-626e-44d9-9a0f-0796c1557535
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=188042062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.188042062
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2458485455
Short name T289
Test name
Test status
Simulation time 773845546 ps
CPU time 5.18 seconds
Started Jun 28 05:40:49 PM PDT 24
Finished Jun 28 05:40:59 PM PDT 24
Peak memory 205576 kb
Host smart-eb9d810a-de08-46e8-9f44-22b1463783dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2458485455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.2458485455
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2074852148
Short name T226
Test name
Test status
Simulation time 152590306 ps
CPU time 1.7 seconds
Started Jun 28 05:40:34 PM PDT 24
Finished Jun 28 05:40:41 PM PDT 24
Peak memory 214296 kb
Host smart-3a2a8fc2-64c9-4af4-9489-a984511d62e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074852148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.2074852148
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2267235259
Short name T2668
Test name
Test status
Simulation time 40035884 ps
CPU time 0.78 seconds
Started Jun 28 05:40:33 PM PDT 24
Finished Jun 28 05:40:39 PM PDT 24
Peak memory 205896 kb
Host smart-fb1ce027-da3a-4893-9c3a-2c8adcd97d46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2267235259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2267235259
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1930367195
Short name T2699
Test name
Test status
Simulation time 44347218 ps
CPU time 0.66 seconds
Started Jun 28 05:40:37 PM PDT 24
Finished Jun 28 05:40:43 PM PDT 24
Peak memory 205852 kb
Host smart-2e376ac6-7366-40de-a060-b80e4289d181
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1930367195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.1930367195
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1370892406
Short name T2689
Test name
Test status
Simulation time 137949043 ps
CPU time 1.13 seconds
Started Jun 28 05:40:36 PM PDT 24
Finished Jun 28 05:40:43 PM PDT 24
Peak memory 206012 kb
Host smart-3e58d7eb-149b-4e56-aa13-0626a4d624d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1370892406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.1370892406
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3589792129
Short name T233
Test name
Test status
Simulation time 79232840 ps
CPU time 1.39 seconds
Started Jun 28 05:40:50 PM PDT 24
Finished Jun 28 05:40:56 PM PDT 24
Peak memory 206140 kb
Host smart-c338e502-2dc8-4ed4-9cbe-5d94d5daafb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3589792129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.3589792129
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2515123661
Short name T251
Test name
Test status
Simulation time 946129170 ps
CPU time 5.33 seconds
Started Jun 28 05:40:49 PM PDT 24
Finished Jun 28 05:40:59 PM PDT 24
Peak memory 205996 kb
Host smart-aa35dae4-2c7d-487b-9056-178834e6b38e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2515123661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.2515123661
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.288883802
Short name T249
Test name
Test status
Simulation time 72012375 ps
CPU time 1.94 seconds
Started Jun 28 05:40:39 PM PDT 24
Finished Jun 28 05:40:47 PM PDT 24
Peak memory 214336 kb
Host smart-5407f948-8d48-42b1-8d95-fc62963dae10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288883802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbde
v_csr_mem_rw_with_rand_reset.288883802
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1105519273
Short name T2728
Test name
Test status
Simulation time 43613663 ps
CPU time 0.79 seconds
Started Jun 28 05:40:33 PM PDT 24
Finished Jun 28 05:40:39 PM PDT 24
Peak memory 205916 kb
Host smart-59a6071e-c3bf-4649-ad21-05724bfca02d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1105519273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.1105519273
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.4107216923
Short name T2645
Test name
Test status
Simulation time 97450977 ps
CPU time 1.19 seconds
Started Jun 28 05:40:35 PM PDT 24
Finished Jun 28 05:40:42 PM PDT 24
Peak memory 205992 kb
Host smart-ef76d215-84ee-43ee-8221-e8fcaacc5c46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4107216923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.4107216923
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1124576606
Short name T2707
Test name
Test status
Simulation time 315637986 ps
CPU time 3.05 seconds
Started Jun 28 05:40:48 PM PDT 24
Finished Jun 28 05:40:56 PM PDT 24
Peak memory 221640 kb
Host smart-1d3408c8-2c78-4371-8b90-400aefef785f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1124576606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.1124576606
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2210248138
Short name T2659
Test name
Test status
Simulation time 415157652 ps
CPU time 2.81 seconds
Started Jun 28 05:40:37 PM PDT 24
Finished Jun 28 05:40:45 PM PDT 24
Peak memory 206076 kb
Host smart-4c392ed8-f7ca-4954-8fd4-78c9c6ec7786
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2210248138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.2210248138
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.4152850783
Short name T2680
Test name
Test status
Simulation time 177091767 ps
CPU time 2.17 seconds
Started Jun 28 05:40:57 PM PDT 24
Finished Jun 28 05:41:05 PM PDT 24
Peak memory 214356 kb
Host smart-1396780f-66c3-455a-9807-e7f226dcea18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152850783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.4152850783
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.182215887
Short name T2729
Test name
Test status
Simulation time 46313997 ps
CPU time 0.78 seconds
Started Jun 28 05:40:35 PM PDT 24
Finished Jun 28 05:40:41 PM PDT 24
Peak memory 205884 kb
Host smart-f2990f38-df3f-459a-bdbf-d59ff7fc0428
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=182215887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.182215887
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.2965013469
Short name T2701
Test name
Test status
Simulation time 39511166 ps
CPU time 0.67 seconds
Started Jun 28 05:40:49 PM PDT 24
Finished Jun 28 05:40:54 PM PDT 24
Peak memory 205788 kb
Host smart-b640ea1d-4d1e-432f-bbd6-a3cbbb4973e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2965013469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.2965013469
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3607836884
Short name T281
Test name
Test status
Simulation time 93282916 ps
CPU time 1.15 seconds
Started Jun 28 05:40:39 PM PDT 24
Finished Jun 28 05:40:46 PM PDT 24
Peak memory 206036 kb
Host smart-970b7faf-1a7b-47aa-8f9d-c898de9bc06c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3607836884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.3607836884
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3587724289
Short name T235
Test name
Test status
Simulation time 171256198 ps
CPU time 2.05 seconds
Started Jun 28 05:40:46 PM PDT 24
Finished Jun 28 05:40:53 PM PDT 24
Peak memory 206092 kb
Host smart-33bc7690-de7c-4ae5-8dc5-11130accc73d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3587724289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.3587724289
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1559589203
Short name T250
Test name
Test status
Simulation time 868185655 ps
CPU time 3.17 seconds
Started Jun 28 05:41:07 PM PDT 24
Finished Jun 28 05:41:14 PM PDT 24
Peak memory 205940 kb
Host smart-25ce7c7e-bb60-4869-8aeb-b63929f64ecf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1559589203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.1559589203
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2476519806
Short name T2723
Test name
Test status
Simulation time 177743060 ps
CPU time 1.83 seconds
Started Jun 28 05:40:37 PM PDT 24
Finished Jun 28 05:40:45 PM PDT 24
Peak memory 214280 kb
Host smart-49c683e1-37b5-4a71-b93d-486d3dcc03ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476519806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.2476519806
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.945165824
Short name T206
Test name
Test status
Simulation time 89257772 ps
CPU time 1.13 seconds
Started Jun 28 05:40:50 PM PDT 24
Finished Jun 28 05:40:55 PM PDT 24
Peak memory 205664 kb
Host smart-e61352c7-b010-4fe1-a745-57b653fb43d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=945165824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.945165824
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3284058257
Short name T301
Test name
Test status
Simulation time 40508374 ps
CPU time 0.65 seconds
Started Jun 28 05:40:36 PM PDT 24
Finished Jun 28 05:40:42 PM PDT 24
Peak memory 205776 kb
Host smart-549fb73e-fa44-4435-b465-4e339878b1f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3284058257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.3284058257
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3491811389
Short name T280
Test name
Test status
Simulation time 118802321 ps
CPU time 1.18 seconds
Started Jun 28 05:40:47 PM PDT 24
Finished Jun 28 05:40:53 PM PDT 24
Peak memory 206020 kb
Host smart-d4243e29-294c-4121-84ff-37abe25b0191
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3491811389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.3491811389
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1120491034
Short name T232
Test name
Test status
Simulation time 117141732 ps
CPU time 1.72 seconds
Started Jun 28 05:40:37 PM PDT 24
Finished Jun 28 05:40:44 PM PDT 24
Peak memory 205960 kb
Host smart-5f67712c-394c-47c7-a109-8bcb0a0fc318
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1120491034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.1120491034
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.361514555
Short name T2658
Test name
Test status
Simulation time 358541733 ps
CPU time 3.46 seconds
Started Jun 28 05:40:11 PM PDT 24
Finished Jun 28 05:40:16 PM PDT 24
Peak memory 205972 kb
Host smart-7e46a9b9-8c90-4b83-b77d-f5899be46a53
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=361514555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.361514555
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1075635295
Short name T275
Test name
Test status
Simulation time 381528835 ps
CPU time 7.05 seconds
Started Jun 28 05:40:28 PM PDT 24
Finished Jun 28 05:40:36 PM PDT 24
Peak memory 206084 kb
Host smart-e7fd3f0c-25b5-40a3-aaec-473dd2df2315
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1075635295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.1075635295
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.585707785
Short name T2684
Test name
Test status
Simulation time 138696058 ps
CPU time 1.04 seconds
Started Jun 28 05:40:18 PM PDT 24
Finished Jun 28 05:40:20 PM PDT 24
Peak memory 205916 kb
Host smart-877b8ad0-562f-4df1-8949-f8f2a977b366
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=585707785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.585707785
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1380343162
Short name T2639
Test name
Test status
Simulation time 161406842 ps
CPU time 1.96 seconds
Started Jun 28 05:40:15 PM PDT 24
Finished Jun 28 05:40:19 PM PDT 24
Peak memory 214280 kb
Host smart-441bee23-afad-4280-b404-07aa0f6d18ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380343162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.1380343162
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1642662970
Short name T2655
Test name
Test status
Simulation time 46996386 ps
CPU time 1.01 seconds
Started Jun 28 05:40:11 PM PDT 24
Finished Jun 28 05:40:13 PM PDT 24
Peak memory 205968 kb
Host smart-f9abc0ea-6efb-4481-a169-ded9b598d578
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1642662970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.1642662970
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2880562260
Short name T2731
Test name
Test status
Simulation time 44634316 ps
CPU time 0.66 seconds
Started Jun 28 05:40:23 PM PDT 24
Finished Jun 28 05:40:24 PM PDT 24
Peak memory 205844 kb
Host smart-b1efdb18-dcf5-46ff-a301-5f0143b444d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2880562260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.2880562260
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.1843795897
Short name T266
Test name
Test status
Simulation time 98222929 ps
CPU time 2.17 seconds
Started Jun 28 05:40:11 PM PDT 24
Finished Jun 28 05:40:14 PM PDT 24
Peak memory 222420 kb
Host smart-ebf88679-e5f8-4a16-a4fe-a369c9a04543
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1843795897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.1843795897
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1882395199
Short name T2650
Test name
Test status
Simulation time 328490017 ps
CPU time 2.58 seconds
Started Jun 28 05:40:18 PM PDT 24
Finished Jun 28 05:40:22 PM PDT 24
Peak memory 205988 kb
Host smart-71721470-927b-436a-a389-43dbeb3ffb06
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1882395199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.1882395199
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.983311081
Short name T290
Test name
Test status
Simulation time 128407538 ps
CPU time 1.21 seconds
Started Jun 28 05:40:14 PM PDT 24
Finished Jun 28 05:40:17 PM PDT 24
Peak memory 206000 kb
Host smart-bad42bd0-c2ce-496e-bf49-c0c4b2ec6746
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=983311081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.983311081
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1302917369
Short name T2725
Test name
Test status
Simulation time 119605435 ps
CPU time 1.63 seconds
Started Jun 28 05:40:34 PM PDT 24
Finished Jun 28 05:40:40 PM PDT 24
Peak memory 206164 kb
Host smart-a5897550-bcd8-43d3-94ec-ac62d0b4fda5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1302917369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.1302917369
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2710135626
Short name T316
Test name
Test status
Simulation time 599071396 ps
CPU time 3.01 seconds
Started Jun 28 05:40:16 PM PDT 24
Finished Jun 28 05:40:20 PM PDT 24
Peak memory 206104 kb
Host smart-b7dcf6aa-2075-4c16-995d-ac7f72bed81a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2710135626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.2710135626
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.3882956396
Short name T299
Test name
Test status
Simulation time 52059843 ps
CPU time 0.7 seconds
Started Jun 28 05:40:37 PM PDT 24
Finished Jun 28 05:40:44 PM PDT 24
Peak memory 205844 kb
Host smart-7d021fa7-2eed-416c-91e5-d85947457f12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3882956396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.3882956396
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2446836200
Short name T306
Test name
Test status
Simulation time 60909189 ps
CPU time 0.69 seconds
Started Jun 28 05:40:56 PM PDT 24
Finished Jun 28 05:41:00 PM PDT 24
Peak memory 205848 kb
Host smart-7276f400-7770-4bfb-b8fe-11a8de5a49a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2446836200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.2446836200
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.3528587019
Short name T305
Test name
Test status
Simulation time 30665244 ps
CPU time 0.64 seconds
Started Jun 28 05:40:33 PM PDT 24
Finished Jun 28 05:40:38 PM PDT 24
Peak memory 205680 kb
Host smart-63b6d90f-f65d-4064-8a43-3c92c23dd68f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3528587019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.3528587019
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3470877146
Short name T309
Test name
Test status
Simulation time 48936895 ps
CPU time 0.71 seconds
Started Jun 28 05:40:35 PM PDT 24
Finished Jun 28 05:40:41 PM PDT 24
Peak memory 205776 kb
Host smart-61ffa10f-05f5-4462-8550-5359fd4e329d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3470877146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.3470877146
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.3411741904
Short name T308
Test name
Test status
Simulation time 42535007 ps
CPU time 0.67 seconds
Started Jun 28 05:40:44 PM PDT 24
Finished Jun 28 05:40:50 PM PDT 24
Peak memory 205852 kb
Host smart-ecf48028-d5c1-4c47-9aa2-c578b9d1bb47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3411741904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.3411741904
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2127814980
Short name T2661
Test name
Test status
Simulation time 39539803 ps
CPU time 0.67 seconds
Started Jun 28 05:40:37 PM PDT 24
Finished Jun 28 05:40:43 PM PDT 24
Peak memory 205712 kb
Host smart-3dbcf6de-76ba-4725-ac11-b45a063f8aa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2127814980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.2127814980
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1758597150
Short name T211
Test name
Test status
Simulation time 36780638 ps
CPU time 0.69 seconds
Started Jun 28 05:41:06 PM PDT 24
Finished Jun 28 05:41:11 PM PDT 24
Peak memory 205848 kb
Host smart-bd488940-767b-4110-baa0-81a562c05879
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1758597150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.1758597150
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3138064317
Short name T2683
Test name
Test status
Simulation time 34694885 ps
CPU time 0.69 seconds
Started Jun 28 05:40:44 PM PDT 24
Finished Jun 28 05:40:50 PM PDT 24
Peak memory 205828 kb
Host smart-43498cc7-2adb-405e-93cc-6748766157f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3138064317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.3138064317
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2204142956
Short name T2637
Test name
Test status
Simulation time 44411824 ps
CPU time 0.7 seconds
Started Jun 28 05:40:43 PM PDT 24
Finished Jun 28 05:40:50 PM PDT 24
Peak memory 205836 kb
Host smart-96221b0e-ee59-4460-bbbf-8a292d026a75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2204142956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.2204142956
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3873632048
Short name T2643
Test name
Test status
Simulation time 39578467 ps
CPU time 0.68 seconds
Started Jun 28 05:40:42 PM PDT 24
Finished Jun 28 05:40:48 PM PDT 24
Peak memory 205784 kb
Host smart-cb141afd-855c-45ca-9904-5b23003ad6ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3873632048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.3873632048
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1291531602
Short name T2654
Test name
Test status
Simulation time 155817508 ps
CPU time 2.07 seconds
Started Jun 28 05:40:32 PM PDT 24
Finished Jun 28 05:40:36 PM PDT 24
Peak memory 205960 kb
Host smart-ee4c68fe-1501-4acb-8485-71608bfcee5d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1291531602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.1291531602
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3804416035
Short name T2674
Test name
Test status
Simulation time 460605752 ps
CPU time 4.11 seconds
Started Jun 28 05:40:33 PM PDT 24
Finished Jun 28 05:40:41 PM PDT 24
Peak memory 206076 kb
Host smart-69f4ce15-4bae-4211-bbb5-10634f79b4ea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3804416035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.3804416035
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.991150333
Short name T2634
Test name
Test status
Simulation time 61987694 ps
CPU time 0.85 seconds
Started Jun 28 05:40:13 PM PDT 24
Finished Jun 28 05:40:15 PM PDT 24
Peak memory 205948 kb
Host smart-9419a249-d03c-4b59-afb6-4efbe301d35e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=991150333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.991150333
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3732697065
Short name T2709
Test name
Test status
Simulation time 257394676 ps
CPU time 1.99 seconds
Started Jun 28 05:40:30 PM PDT 24
Finished Jun 28 05:40:34 PM PDT 24
Peak memory 217708 kb
Host smart-5e297b49-abce-4d0a-992f-764cc3ac3010
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732697065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.3732697065
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2444581795
Short name T267
Test name
Test status
Simulation time 76448807 ps
CPU time 1.01 seconds
Started Jun 28 05:40:27 PM PDT 24
Finished Jun 28 05:40:29 PM PDT 24
Peak memory 206056 kb
Host smart-639828b4-82e2-482d-9a3c-dfbfad3d7976
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2444581795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2444581795
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.1173345797
Short name T307
Test name
Test status
Simulation time 58428202 ps
CPU time 0.68 seconds
Started Jun 28 05:40:16 PM PDT 24
Finished Jun 28 05:40:18 PM PDT 24
Peak memory 205848 kb
Host smart-699de29c-e438-4acb-9427-811b50f5a072
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1173345797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.1173345797
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1474218008
Short name T269
Test name
Test status
Simulation time 194959647 ps
CPU time 2.51 seconds
Started Jun 28 05:40:12 PM PDT 24
Finished Jun 28 05:40:15 PM PDT 24
Peak memory 215260 kb
Host smart-da30c862-d654-4279-a627-34457fb32183
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1474218008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.1474218008
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.4016210865
Short name T2706
Test name
Test status
Simulation time 496602037 ps
CPU time 4.22 seconds
Started Jun 28 05:40:14 PM PDT 24
Finished Jun 28 05:40:19 PM PDT 24
Peak memory 205988 kb
Host smart-cd44db9a-d3e5-4b46-99f6-baff7e8344af
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4016210865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.4016210865
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3342711184
Short name T2717
Test name
Test status
Simulation time 265564934 ps
CPU time 1.95 seconds
Started Jun 28 05:40:32 PM PDT 24
Finished Jun 28 05:40:37 PM PDT 24
Peak memory 206036 kb
Host smart-cf414e21-1b97-41a8-a720-7b12479e03ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3342711184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.3342711184
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2608871849
Short name T241
Test name
Test status
Simulation time 197510158 ps
CPU time 2.24 seconds
Started Jun 28 05:40:29 PM PDT 24
Finished Jun 28 05:40:32 PM PDT 24
Peak memory 206092 kb
Host smart-f46b3460-296e-43bc-9a9e-828649462d74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2608871849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2608871849
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3538042671
Short name T204
Test name
Test status
Simulation time 566612592 ps
CPU time 2.7 seconds
Started Jun 28 05:40:21 PM PDT 24
Finished Jun 28 05:40:25 PM PDT 24
Peak memory 206072 kb
Host smart-4a860faa-d9cd-4f8f-a3d4-e32b2ba3e0c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3538042671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.3538042671
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.256843899
Short name T2677
Test name
Test status
Simulation time 36755615 ps
CPU time 0.68 seconds
Started Jun 28 05:40:43 PM PDT 24
Finished Jun 28 05:40:49 PM PDT 24
Peak memory 205808 kb
Host smart-83d9e106-ef95-493b-b111-475bdec9b3d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=256843899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.256843899
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3511357491
Short name T310
Test name
Test status
Simulation time 62828786 ps
CPU time 0.68 seconds
Started Jun 28 05:40:43 PM PDT 24
Finished Jun 28 05:40:49 PM PDT 24
Peak memory 205836 kb
Host smart-203db548-b7de-4319-8cc6-0386c6e4e1a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3511357491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.3511357491
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3852596594
Short name T2646
Test name
Test status
Simulation time 33705494 ps
CPU time 0.69 seconds
Started Jun 28 05:40:43 PM PDT 24
Finished Jun 28 05:40:49 PM PDT 24
Peak memory 205836 kb
Host smart-1092e2d6-340c-4b7f-beb2-c99744dc0c6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3852596594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.3852596594
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1834861297
Short name T2652
Test name
Test status
Simulation time 44119069 ps
CPU time 0.71 seconds
Started Jun 28 05:40:39 PM PDT 24
Finished Jun 28 05:40:46 PM PDT 24
Peak memory 205828 kb
Host smart-dae891fd-40f2-4258-8e03-fdf41d63c471
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1834861297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.1834861297
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.4088874368
Short name T2693
Test name
Test status
Simulation time 67279406 ps
CPU time 0.75 seconds
Started Jun 28 05:40:53 PM PDT 24
Finished Jun 28 05:40:57 PM PDT 24
Peak memory 205844 kb
Host smart-d568e223-2efd-4bbb-b1d2-17a646ecca6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4088874368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.4088874368
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.375880024
Short name T311
Test name
Test status
Simulation time 43767690 ps
CPU time 0.69 seconds
Started Jun 28 05:40:51 PM PDT 24
Finished Jun 28 05:40:56 PM PDT 24
Peak memory 205848 kb
Host smart-9f9be75b-2e69-407a-83ec-2c2cfa258540
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=375880024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.375880024
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1312573002
Short name T2681
Test name
Test status
Simulation time 37934846 ps
CPU time 0.68 seconds
Started Jun 28 05:40:35 PM PDT 24
Finished Jun 28 05:40:41 PM PDT 24
Peak memory 205852 kb
Host smart-509fb85a-fa33-4c4f-a811-31d287c18160
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1312573002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.1312573002
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.645276990
Short name T2641
Test name
Test status
Simulation time 40895329 ps
CPU time 0.69 seconds
Started Jun 28 05:40:53 PM PDT 24
Finished Jun 28 05:40:57 PM PDT 24
Peak memory 205812 kb
Host smart-be5622d7-361e-446f-8d47-8cc5d70c6cba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=645276990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.645276990
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.595348532
Short name T288
Test name
Test status
Simulation time 216243329 ps
CPU time 2.23 seconds
Started Jun 28 05:40:26 PM PDT 24
Finished Jun 28 05:40:29 PM PDT 24
Peak memory 206040 kb
Host smart-b311f2cd-6706-4e78-8732-879b9e2e82b6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=595348532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.595348532
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2649633993
Short name T2702
Test name
Test status
Simulation time 687910672 ps
CPU time 4.53 seconds
Started Jun 28 05:40:35 PM PDT 24
Finished Jun 28 05:40:45 PM PDT 24
Peak memory 206040 kb
Host smart-bc075f6e-fb35-409a-bcf3-42f33edf88d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2649633993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.2649633993
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3199366386
Short name T2721
Test name
Test status
Simulation time 162846758 ps
CPU time 0.96 seconds
Started Jun 28 05:40:31 PM PDT 24
Finished Jun 28 05:40:34 PM PDT 24
Peak memory 205916 kb
Host smart-e9049565-62fa-43ca-b347-a7487c5ebb28
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3199366386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.3199366386
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.4074093317
Short name T2647
Test name
Test status
Simulation time 245578778 ps
CPU time 1.93 seconds
Started Jun 28 05:40:33 PM PDT 24
Finished Jun 28 05:40:38 PM PDT 24
Peak memory 218184 kb
Host smart-3fa9765c-0a09-474e-bf4b-327d850cb099
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074093317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.4074093317
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3177207320
Short name T2663
Test name
Test status
Simulation time 136734463 ps
CPU time 1.09 seconds
Started Jun 28 05:40:44 PM PDT 24
Finished Jun 28 05:40:50 PM PDT 24
Peak memory 206028 kb
Host smart-552adaea-1c63-4447-a004-0c9a9a24c27f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3177207320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.3177207320
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.4072872717
Short name T2697
Test name
Test status
Simulation time 230607909 ps
CPU time 2.52 seconds
Started Jun 28 05:40:40 PM PDT 24
Finished Jun 28 05:40:48 PM PDT 24
Peak memory 215324 kb
Host smart-8bee4184-f316-40e7-84ee-089c2d4651a0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4072872717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.4072872717
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.69805870
Short name T2732
Test name
Test status
Simulation time 384158232 ps
CPU time 2.91 seconds
Started Jun 28 05:40:31 PM PDT 24
Finished Jun 28 05:40:36 PM PDT 24
Peak memory 205944 kb
Host smart-ceb44212-0607-4efe-8961-1469ade457f8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=69805870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.69805870
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.230202226
Short name T2665
Test name
Test status
Simulation time 156330521 ps
CPU time 1.48 seconds
Started Jun 28 05:40:29 PM PDT 24
Finished Jun 28 05:40:32 PM PDT 24
Peak memory 206024 kb
Host smart-c22df1cc-cf0d-42e3-8d97-442a4be8ecb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=230202226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.230202226
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.4029189204
Short name T236
Test name
Test status
Simulation time 187308509 ps
CPU time 2.05 seconds
Started Jun 28 05:40:35 PM PDT 24
Finished Jun 28 05:40:42 PM PDT 24
Peak memory 206072 kb
Host smart-4c91836d-9d48-4282-8622-2009e85bd003
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4029189204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.4029189204
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2812695453
Short name T2736
Test name
Test status
Simulation time 41722006 ps
CPU time 0.69 seconds
Started Jun 28 05:40:42 PM PDT 24
Finished Jun 28 05:40:48 PM PDT 24
Peak memory 205788 kb
Host smart-e8c1e11b-439e-4fa6-9f30-4486ded5c9e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2812695453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.2812695453
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3925472263
Short name T300
Test name
Test status
Simulation time 57575772 ps
CPU time 0.68 seconds
Started Jun 28 05:40:41 PM PDT 24
Finished Jun 28 05:40:47 PM PDT 24
Peak memory 205788 kb
Host smart-16366780-a1f4-4906-a4da-0b0fb9d00c79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3925472263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.3925472263
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.4185641696
Short name T213
Test name
Test status
Simulation time 45129444 ps
CPU time 0.68 seconds
Started Jun 28 05:40:42 PM PDT 24
Finished Jun 28 05:40:48 PM PDT 24
Peak memory 205784 kb
Host smart-f248005f-7484-4875-b31f-880216e2bbd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4185641696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.4185641696
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.2574692093
Short name T2688
Test name
Test status
Simulation time 61244758 ps
CPU time 0.68 seconds
Started Jun 28 05:40:41 PM PDT 24
Finished Jun 28 05:40:47 PM PDT 24
Peak memory 205788 kb
Host smart-e518900a-b81e-422b-b2ee-05fd78338129
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2574692093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.2574692093
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.941895695
Short name T2648
Test name
Test status
Simulation time 55565842 ps
CPU time 0.73 seconds
Started Jun 28 05:40:44 PM PDT 24
Finished Jun 28 05:40:50 PM PDT 24
Peak memory 205944 kb
Host smart-f327a26f-5767-4441-a3f9-f3b546a64c96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=941895695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.941895695
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2821564766
Short name T294
Test name
Test status
Simulation time 52432696 ps
CPU time 0.73 seconds
Started Jun 28 05:40:50 PM PDT 24
Finished Jun 28 05:40:55 PM PDT 24
Peak memory 205848 kb
Host smart-d9203cb6-a672-4504-989c-707be374dc15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2821564766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.2821564766
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.419244761
Short name T2714
Test name
Test status
Simulation time 66062473 ps
CPU time 0.73 seconds
Started Jun 28 05:40:55 PM PDT 24
Finished Jun 28 05:41:01 PM PDT 24
Peak memory 205848 kb
Host smart-a7745f1c-3f7a-4a4f-86e6-b732c2d866f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=419244761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.419244761
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.2147243939
Short name T2672
Test name
Test status
Simulation time 52855568 ps
CPU time 0.7 seconds
Started Jun 28 05:40:48 PM PDT 24
Finished Jun 28 05:40:54 PM PDT 24
Peak memory 205820 kb
Host smart-6983308c-a21d-460b-964b-536dbf81a693
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2147243939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.2147243939
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.89603734
Short name T2638
Test name
Test status
Simulation time 54255054 ps
CPU time 0.65 seconds
Started Jun 28 05:40:43 PM PDT 24
Finished Jun 28 05:40:49 PM PDT 24
Peak memory 205796 kb
Host smart-6ccc65f6-7f42-417a-ba02-2619ae66f616
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=89603734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.89603734
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1772936101
Short name T298
Test name
Test status
Simulation time 41311305 ps
CPU time 0.72 seconds
Started Jun 28 05:40:54 PM PDT 24
Finished Jun 28 05:40:58 PM PDT 24
Peak memory 205852 kb
Host smart-5c3154a1-bb72-4e5b-8d0e-1185e27820eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1772936101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.1772936101
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.4245123669
Short name T234
Test name
Test status
Simulation time 83478861 ps
CPU time 1.54 seconds
Started Jun 28 05:40:32 PM PDT 24
Finished Jun 28 05:40:37 PM PDT 24
Peak memory 214256 kb
Host smart-f24d54a6-57c6-4379-9a36-437790ebb8ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245123669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.4245123669
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3336159169
Short name T2704
Test name
Test status
Simulation time 82013152 ps
CPU time 0.98 seconds
Started Jun 28 05:40:34 PM PDT 24
Finished Jun 28 05:40:40 PM PDT 24
Peak memory 206008 kb
Host smart-ef183b3b-7476-4ad7-9d54-2826564029b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3336159169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.3336159169
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1218589762
Short name T2657
Test name
Test status
Simulation time 33580360 ps
CPU time 0.66 seconds
Started Jun 28 05:40:42 PM PDT 24
Finished Jun 28 05:40:48 PM PDT 24
Peak memory 205800 kb
Host smart-f619dd08-50fc-4a45-a666-648c31de599e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1218589762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.1218589762
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.798474725
Short name T287
Test name
Test status
Simulation time 227041967 ps
CPU time 1.89 seconds
Started Jun 28 05:40:40 PM PDT 24
Finished Jun 28 05:40:47 PM PDT 24
Peak memory 206056 kb
Host smart-64a37787-0f93-45f2-bb46-86a3fbc0ebb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=798474725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.798474725
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3900522910
Short name T2696
Test name
Test status
Simulation time 1795042293 ps
CPU time 6.28 seconds
Started Jun 28 05:40:43 PM PDT 24
Finished Jun 28 05:40:55 PM PDT 24
Peak memory 206048 kb
Host smart-f7ed55f9-0421-46b7-82d9-accf17c4d7ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3900522910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.3900522910
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.4081948052
Short name T2705
Test name
Test status
Simulation time 194354094 ps
CPU time 1.33 seconds
Started Jun 28 05:40:38 PM PDT 24
Finished Jun 28 05:40:45 PM PDT 24
Peak memory 215788 kb
Host smart-21eefc28-16ef-48ba-b749-3e08e3a79113
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081948052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.4081948052
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1693723486
Short name T2673
Test name
Test status
Simulation time 81072218 ps
CPU time 1.08 seconds
Started Jun 28 05:40:54 PM PDT 24
Finished Jun 28 05:40:58 PM PDT 24
Peak memory 205996 kb
Host smart-b3a39228-e591-4134-90e4-e70a30456762
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1693723486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.1693723486
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.709704508
Short name T2653
Test name
Test status
Simulation time 35611215 ps
CPU time 0.69 seconds
Started Jun 28 05:40:32 PM PDT 24
Finished Jun 28 05:40:35 PM PDT 24
Peak memory 205848 kb
Host smart-2bbddfcd-78d6-4a54-8436-08d47459fb64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=709704508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.709704508
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1459896182
Short name T2720
Test name
Test status
Simulation time 197668198 ps
CPU time 1.61 seconds
Started Jun 28 05:40:30 PM PDT 24
Finished Jun 28 05:40:34 PM PDT 24
Peak memory 206008 kb
Host smart-b9aff19d-b6c4-4c02-891e-56062201b394
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1459896182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.1459896182
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3590081741
Short name T2664
Test name
Test status
Simulation time 195771062 ps
CPU time 1.72 seconds
Started Jun 28 05:40:37 PM PDT 24
Finished Jun 28 05:40:45 PM PDT 24
Peak memory 206172 kb
Host smart-136c1b8c-23ef-4199-b22b-acc06e0fc927
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3590081741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.3590081741
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3633040304
Short name T247
Test name
Test status
Simulation time 354647584 ps
CPU time 2.66 seconds
Started Jun 28 05:40:38 PM PDT 24
Finished Jun 28 05:40:47 PM PDT 24
Peak memory 206072 kb
Host smart-74c6bbae-125d-45ac-a1c5-ce5b8a440bb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3633040304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.3633040304
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2770224594
Short name T291
Test name
Test status
Simulation time 206388373 ps
CPU time 2 seconds
Started Jun 28 05:40:32 PM PDT 24
Finished Jun 28 05:40:38 PM PDT 24
Peak memory 217988 kb
Host smart-de9de95b-3589-4beb-8780-210f10b44726
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770224594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.2770224594
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2450951883
Short name T278
Test name
Test status
Simulation time 69694286 ps
CPU time 0.85 seconds
Started Jun 28 05:40:46 PM PDT 24
Finished Jun 28 05:40:52 PM PDT 24
Peak memory 205912 kb
Host smart-20f5b3a7-a1e3-4bd2-b29e-059c9e182880
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2450951883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.2450951883
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2962934972
Short name T2718
Test name
Test status
Simulation time 84197117 ps
CPU time 0.72 seconds
Started Jun 28 05:40:32 PM PDT 24
Finished Jun 28 05:40:36 PM PDT 24
Peak memory 205848 kb
Host smart-8142bb23-e9fd-4d00-8da9-c05f97689393
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2962934972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.2962934972
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2314643631
Short name T2691
Test name
Test status
Simulation time 187699512 ps
CPU time 1.68 seconds
Started Jun 28 05:40:33 PM PDT 24
Finished Jun 28 05:40:39 PM PDT 24
Peak memory 205984 kb
Host smart-09898fcf-dbc9-451a-8020-f47c378f6c36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2314643631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.2314643631
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.616838246
Short name T239
Test name
Test status
Simulation time 125463778 ps
CPU time 3.21 seconds
Started Jun 28 05:40:34 PM PDT 24
Finished Jun 28 05:40:42 PM PDT 24
Peak memory 214304 kb
Host smart-0536d1b3-9c79-4767-8f61-26c857ea81f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=616838246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.616838246
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1905536217
Short name T2690
Test name
Test status
Simulation time 698432110 ps
CPU time 4.67 seconds
Started Jun 28 05:40:32 PM PDT 24
Finished Jun 28 05:40:40 PM PDT 24
Peak memory 206032 kb
Host smart-41532371-5ff9-4942-bd93-53734a3cff15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1905536217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.1905536217
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.44291324
Short name T2660
Test name
Test status
Simulation time 175537568 ps
CPU time 1.91 seconds
Started Jun 28 05:40:44 PM PDT 24
Finished Jun 28 05:40:51 PM PDT 24
Peak memory 214260 kb
Host smart-8e620cdf-a24d-403a-9729-24e12999f498
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44291324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_
csr_mem_rw_with_rand_reset.44291324
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.4112283397
Short name T2716
Test name
Test status
Simulation time 45789431 ps
CPU time 0.98 seconds
Started Jun 28 05:40:32 PM PDT 24
Finished Jun 28 05:40:37 PM PDT 24
Peak memory 206004 kb
Host smart-a21d50d9-6f2a-4b90-a1f8-6aade8f829af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4112283397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.4112283397
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2555623648
Short name T293
Test name
Test status
Simulation time 58347258 ps
CPU time 0.67 seconds
Started Jun 28 05:40:29 PM PDT 24
Finished Jun 28 05:40:31 PM PDT 24
Peak memory 205792 kb
Host smart-31ce776d-b65e-45cf-9f25-6d44bb29bc4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2555623648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.2555623648
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3859504273
Short name T2662
Test name
Test status
Simulation time 77534614 ps
CPU time 1.15 seconds
Started Jun 28 05:40:31 PM PDT 24
Finished Jun 28 05:40:34 PM PDT 24
Peak memory 206028 kb
Host smart-10bc00c6-cdbe-43dc-87bc-f47c5ddf91e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3859504273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.3859504273
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.844626588
Short name T2667
Test name
Test status
Simulation time 477607627 ps
CPU time 2.96 seconds
Started Jun 28 05:40:29 PM PDT 24
Finished Jun 28 05:40:34 PM PDT 24
Peak memory 206036 kb
Host smart-83b0c32d-a7ff-4e82-852e-34c92a244f77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=844626588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.844626588
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1533943270
Short name T2644
Test name
Test status
Simulation time 72534822 ps
CPU time 1.71 seconds
Started Jun 28 05:40:31 PM PDT 24
Finished Jun 28 05:40:35 PM PDT 24
Peak memory 214280 kb
Host smart-57e01a91-bc59-4ee4-b09b-3d31fe3b8102
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533943270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.1533943270
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2252751659
Short name T274
Test name
Test status
Simulation time 75655209 ps
CPU time 1.02 seconds
Started Jun 28 05:40:33 PM PDT 24
Finished Jun 28 05:40:38 PM PDT 24
Peak memory 205924 kb
Host smart-ff8892ea-0c22-4726-8680-382a1d7ec1cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2252751659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.2252751659
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2779514261
Short name T2722
Test name
Test status
Simulation time 121232459 ps
CPU time 1.19 seconds
Started Jun 28 05:40:34 PM PDT 24
Finished Jun 28 05:40:39 PM PDT 24
Peak memory 206164 kb
Host smart-29dff345-f282-4a5b-aaaf-936db5581161
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2779514261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.2779514261
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3452596629
Short name T2733
Test name
Test status
Simulation time 66186297 ps
CPU time 1.64 seconds
Started Jun 28 05:40:53 PM PDT 24
Finished Jun 28 05:40:58 PM PDT 24
Peak memory 205952 kb
Host smart-527193f7-9b83-4089-b3d5-b8cfa6bbfbbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3452596629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.3452596629
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.4031265987
Short name T231
Test name
Test status
Simulation time 794505375 ps
CPU time 3.13 seconds
Started Jun 28 05:40:35 PM PDT 24
Finished Jun 28 05:40:44 PM PDT 24
Peak memory 206056 kb
Host smart-6006b01e-8896-4040-923c-0e4ce6602fdf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4031265987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.4031265987
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.3514239401
Short name T774
Test name
Test status
Simulation time 51673799 ps
CPU time 0.68 seconds
Started Jun 28 06:08:29 PM PDT 24
Finished Jun 28 06:08:32 PM PDT 24
Peak memory 206204 kb
Host smart-cb00c8be-2022-4c61-9047-897a0c4bd492
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3514239401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.3514239401
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.2871245620
Short name T1756
Test name
Test status
Simulation time 4220208165 ps
CPU time 5.35 seconds
Started Jun 28 06:08:13 PM PDT 24
Finished Jun 28 06:08:19 PM PDT 24
Peak memory 206356 kb
Host smart-97f5296b-e925-428b-8f2f-87ce79f9d51f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2871245620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.2871245620
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.625201595
Short name T2422
Test name
Test status
Simulation time 13441260383 ps
CPU time 14.22 seconds
Started Jun 28 06:08:11 PM PDT 24
Finished Jun 28 06:08:26 PM PDT 24
Peak memory 206340 kb
Host smart-ff6167f5-08c4-4023-8ae2-ac0fa026bda9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=625201595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.625201595
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.2065190963
Short name T1525
Test name
Test status
Simulation time 23343805245 ps
CPU time 26.49 seconds
Started Jun 28 06:08:11 PM PDT 24
Finished Jun 28 06:08:38 PM PDT 24
Peak memory 206312 kb
Host smart-1fe8998a-7a36-4961-9194-05f3bc71f08e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2065190963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.2065190963
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.1521405465
Short name T898
Test name
Test status
Simulation time 146036456 ps
CPU time 0.79 seconds
Started Jun 28 06:08:09 PM PDT 24
Finished Jun 28 06:08:11 PM PDT 24
Peak memory 206192 kb
Host smart-6210d684-f1aa-420a-a8c2-4acc1a79bd5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15214
05465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.1521405465
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.683066467
Short name T2162
Test name
Test status
Simulation time 163011855 ps
CPU time 0.78 seconds
Started Jun 28 06:08:12 PM PDT 24
Finished Jun 28 06:08:14 PM PDT 24
Peak memory 206192 kb
Host smart-a1a71ebb-c03e-4e06-abe4-fd392db75188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68306
6467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.683066467
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.1290321263
Short name T1946
Test name
Test status
Simulation time 214321535 ps
CPU time 0.94 seconds
Started Jun 28 06:08:13 PM PDT 24
Finished Jun 28 06:08:15 PM PDT 24
Peak memory 206116 kb
Host smart-1e36859a-82b7-414c-b95b-51511dc99222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12903
21263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.1290321263
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_device_address.3161496355
Short name T1030
Test name
Test status
Simulation time 7906898930 ps
CPU time 15.73 seconds
Started Jun 28 06:08:11 PM PDT 24
Finished Jun 28 06:08:28 PM PDT 24
Peak memory 206432 kb
Host smart-f6c7cf98-8308-414f-9610-850cb9452c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31614
96355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.3161496355
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.22148130
Short name T790
Test name
Test status
Simulation time 330763199 ps
CPU time 1.06 seconds
Started Jun 28 06:08:10 PM PDT 24
Finished Jun 28 06:08:12 PM PDT 24
Peak memory 206216 kb
Host smart-f62ea894-5256-41a7-b5ef-399243a84d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22148
130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.22148130
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.2343099537
Short name T1065
Test name
Test status
Simulation time 166727643 ps
CPU time 0.85 seconds
Started Jun 28 06:08:10 PM PDT 24
Finished Jun 28 06:08:12 PM PDT 24
Peak memory 206168 kb
Host smart-b1070b9c-457d-4b36-b51e-68c60a1fc583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23430
99537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.2343099537
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.1028731739
Short name T877
Test name
Test status
Simulation time 5149110665 ps
CPU time 128.43 seconds
Started Jun 28 06:08:13 PM PDT 24
Finished Jun 28 06:10:23 PM PDT 24
Peak memory 206464 kb
Host smart-48fdf8a6-791d-4e17-841e-e499d3376ddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10287
31739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.1028731739
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_enable.573353376
Short name T1322
Test name
Test status
Simulation time 47000753 ps
CPU time 0.67 seconds
Started Jun 28 06:08:12 PM PDT 24
Finished Jun 28 06:08:14 PM PDT 24
Peak memory 206200 kb
Host smart-a0ee32ba-27c9-49f1-8072-5420e15cd763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57335
3376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.573353376
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.3144392763
Short name T1013
Test name
Test status
Simulation time 870490281 ps
CPU time 2.3 seconds
Started Jun 28 06:08:14 PM PDT 24
Finished Jun 28 06:08:18 PM PDT 24
Peak memory 206320 kb
Host smart-955929fd-b0b0-4530-a66b-dd693ae55d62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31443
92763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.3144392763
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.3459611065
Short name T1945
Test name
Test status
Simulation time 319064460 ps
CPU time 1.81 seconds
Started Jun 28 06:08:08 PM PDT 24
Finished Jun 28 06:08:11 PM PDT 24
Peak memory 206316 kb
Host smart-fe79cced-3aca-450c-9fd2-f4fc47af40e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34596
11065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.3459611065
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.1812013464
Short name T446
Test name
Test status
Simulation time 182198008 ps
CPU time 0.85 seconds
Started Jun 28 06:08:17 PM PDT 24
Finished Jun 28 06:08:19 PM PDT 24
Peak memory 206344 kb
Host smart-faf9f280-3ea9-4908-a40a-5940624bcb7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18120
13464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.1812013464
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.751703409
Short name T2107
Test name
Test status
Simulation time 143098803 ps
CPU time 0.78 seconds
Started Jun 28 06:08:11 PM PDT 24
Finished Jun 28 06:08:13 PM PDT 24
Peak memory 206192 kb
Host smart-171ce20e-dd57-41b5-8aab-bee74d81d13e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75170
3409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.751703409
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.2127096122
Short name T2002
Test name
Test status
Simulation time 155810994 ps
CPU time 0.84 seconds
Started Jun 28 06:08:18 PM PDT 24
Finished Jun 28 06:08:19 PM PDT 24
Peak memory 206348 kb
Host smart-c50acf83-cf9a-487b-86b7-6ca6b7a099f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21270
96122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.2127096122
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_invalid_sync.1144629045
Short name T242
Test name
Test status
Simulation time 9842972570 ps
CPU time 91.38 seconds
Started Jun 28 06:08:11 PM PDT 24
Finished Jun 28 06:09:43 PM PDT 24
Peak memory 206424 kb
Host smart-fce3a773-9495-4562-b8d8-b8d711e01ed4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1144629045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.1144629045
Directory /workspace/0.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.3712928151
Short name T1133
Test name
Test status
Simulation time 250222191 ps
CPU time 0.98 seconds
Started Jun 28 06:08:17 PM PDT 24
Finished Jun 28 06:08:19 PM PDT 24
Peak memory 206352 kb
Host smart-454071fa-04d1-413a-a397-1a195aaa2766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37129
28151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.3712928151
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.816755632
Short name T64
Test name
Test status
Simulation time 627332186 ps
CPU time 1.59 seconds
Started Jun 28 06:08:15 PM PDT 24
Finished Jun 28 06:08:17 PM PDT 24
Peak memory 206192 kb
Host smart-c21f35f7-3d24-4758-976c-57fd1a6a52e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81675
5632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.816755632
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.3286585620
Short name T1336
Test name
Test status
Simulation time 23308142783 ps
CPU time 22.15 seconds
Started Jun 28 06:08:11 PM PDT 24
Finished Jun 28 06:08:35 PM PDT 24
Peak memory 206316 kb
Host smart-3b0cc0be-69b3-4829-8139-55eceaaad0bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32865
85620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.3286585620
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.3571576578
Short name T2501
Test name
Test status
Simulation time 3341000117 ps
CPU time 4.06 seconds
Started Jun 28 06:08:13 PM PDT 24
Finished Jun 28 06:08:19 PM PDT 24
Peak memory 206180 kb
Host smart-2d589b36-7838-46bb-bbe4-d7f099329c0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35715
76578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.3571576578
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.3642872800
Short name T1340
Test name
Test status
Simulation time 7242919520 ps
CPU time 203.98 seconds
Started Jun 28 06:08:16 PM PDT 24
Finished Jun 28 06:11:41 PM PDT 24
Peak memory 206660 kb
Host smart-a002cb6e-952e-487f-a214-cc7af438ea09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36428
72800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.3642872800
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.128492404
Short name T1663
Test name
Test status
Simulation time 3680520671 ps
CPU time 26.91 seconds
Started Jun 28 06:08:14 PM PDT 24
Finished Jun 28 06:08:42 PM PDT 24
Peak memory 206480 kb
Host smart-538c185d-c0e3-4afe-8bf4-f07790f5da55
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=128492404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.128492404
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.1238719944
Short name T347
Test name
Test status
Simulation time 241459654 ps
CPU time 0.88 seconds
Started Jun 28 06:08:31 PM PDT 24
Finished Jun 28 06:08:34 PM PDT 24
Peak memory 206216 kb
Host smart-cad8480c-4b91-4a31-bf79-82ab8e9cabf2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1238719944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.1238719944
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.3731023507
Short name T1449
Test name
Test status
Simulation time 205859494 ps
CPU time 0.91 seconds
Started Jun 28 06:08:26 PM PDT 24
Finished Jun 28 06:08:30 PM PDT 24
Peak memory 206188 kb
Host smart-3922936f-d68c-49e1-af10-30bc63b71446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37310
23507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.3731023507
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.959538621
Short name T2040
Test name
Test status
Simulation time 3978476405 ps
CPU time 38.43 seconds
Started Jun 28 06:08:24 PM PDT 24
Finished Jun 28 06:09:05 PM PDT 24
Peak memory 206400 kb
Host smart-00f280df-dca4-42d7-b264-06c6d7d93d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95953
8621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.959538621
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.3084943746
Short name T722
Test name
Test status
Simulation time 3584403067 ps
CPU time 24.51 seconds
Started Jun 28 06:08:23 PM PDT 24
Finished Jun 28 06:08:48 PM PDT 24
Peak memory 206504 kb
Host smart-45821ddf-3e10-4388-89b6-fca65f6670db
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3084943746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.3084943746
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.3989106715
Short name T219
Test name
Test status
Simulation time 209012688 ps
CPU time 0.84 seconds
Started Jun 28 06:08:22 PM PDT 24
Finished Jun 28 06:08:24 PM PDT 24
Peak memory 206212 kb
Host smart-cf7cb1bc-7b5c-4304-8a2a-68fedc2a6afb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3989106715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.3989106715
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.536712536
Short name T2465
Test name
Test status
Simulation time 151955415 ps
CPU time 0.79 seconds
Started Jun 28 06:08:25 PM PDT 24
Finished Jun 28 06:08:29 PM PDT 24
Peak memory 206212 kb
Host smart-00684577-a713-41cf-9df2-b8cb46e2a8d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53671
2536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.536712536
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.3132658199
Short name T40
Test name
Test status
Simulation time 505570989 ps
CPU time 1.39 seconds
Started Jun 28 06:08:28 PM PDT 24
Finished Jun 28 06:08:32 PM PDT 24
Peak memory 206192 kb
Host smart-cf58840e-c3e7-404e-8cf8-9b4a8fa365fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31326
58199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.3132658199
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.2352988613
Short name T1313
Test name
Test status
Simulation time 185068118 ps
CPU time 0.89 seconds
Started Jun 28 06:08:31 PM PDT 24
Finished Jun 28 06:08:34 PM PDT 24
Peak memory 206196 kb
Host smart-55ae369a-2d67-4009-9405-82c0602ba2c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23529
88613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.2352988613
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.3944534976
Short name T1615
Test name
Test status
Simulation time 179144119 ps
CPU time 0.81 seconds
Started Jun 28 06:08:28 PM PDT 24
Finished Jun 28 06:08:31 PM PDT 24
Peak memory 206208 kb
Host smart-8f34fc2e-5dca-4649-abee-9631943cb43b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39445
34976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.3944534976
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.677231782
Short name T706
Test name
Test status
Simulation time 179831106 ps
CPU time 0.83 seconds
Started Jun 28 06:08:24 PM PDT 24
Finished Jun 28 06:08:27 PM PDT 24
Peak memory 206172 kb
Host smart-c9628af6-c718-43e8-aad9-6db8cb0541d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67723
1782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.677231782
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.2256307099
Short name T1822
Test name
Test status
Simulation time 159405057 ps
CPU time 0.83 seconds
Started Jun 28 06:08:25 PM PDT 24
Finished Jun 28 06:08:28 PM PDT 24
Peak memory 206216 kb
Host smart-bc9cb6cb-a2a5-4668-91a5-20297dd14576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22563
07099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.2256307099
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.68891328
Short name T2539
Test name
Test status
Simulation time 187430259 ps
CPU time 0.88 seconds
Started Jun 28 06:08:24 PM PDT 24
Finished Jun 28 06:08:27 PM PDT 24
Peak memory 206200 kb
Host smart-e7a21256-cf8e-4cbc-8ea4-07b74116f694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68891
328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.68891328
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.4211826307
Short name T776
Test name
Test status
Simulation time 225496398 ps
CPU time 1.01 seconds
Started Jun 28 06:08:24 PM PDT 24
Finished Jun 28 06:08:28 PM PDT 24
Peak memory 206180 kb
Host smart-14064bfb-4fae-4696-a209-6d401194656e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4211826307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.4211826307
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.1242568196
Short name T209
Test name
Test status
Simulation time 245272558 ps
CPU time 0.97 seconds
Started Jun 28 06:08:28 PM PDT 24
Finished Jun 28 06:08:32 PM PDT 24
Peak memory 205948 kb
Host smart-e3a0a81d-f457-4be4-b0ac-d63f35934a02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12425
68196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.1242568196
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.3606282743
Short name T2115
Test name
Test status
Simulation time 255327813 ps
CPU time 1.02 seconds
Started Jun 28 06:08:31 PM PDT 24
Finished Jun 28 06:08:34 PM PDT 24
Peak memory 206216 kb
Host smart-bd6574dc-e495-414b-9425-315ca6895d66
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3606282743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.3606282743
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.1772902596
Short name T208
Test name
Test status
Simulation time 259452524 ps
CPU time 0.98 seconds
Started Jun 28 06:08:24 PM PDT 24
Finished Jun 28 06:08:27 PM PDT 24
Peak memory 206212 kb
Host smart-3188ffe1-a156-4d4e-9c8c-7c6a7badfd5e
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1772902596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.1772902596
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.95080284
Short name T2592
Test name
Test status
Simulation time 135362629 ps
CPU time 0.78 seconds
Started Jun 28 06:08:26 PM PDT 24
Finished Jun 28 06:08:29 PM PDT 24
Peak memory 206200 kb
Host smart-357017b3-a235-4ecb-afc2-f60336a5e543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95080
284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.95080284
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.810194037
Short name T436
Test name
Test status
Simulation time 41522208 ps
CPU time 0.69 seconds
Started Jun 28 06:08:31 PM PDT 24
Finished Jun 28 06:08:33 PM PDT 24
Peak memory 206216 kb
Host smart-aca36fc8-59c9-489b-91ea-88c7bff87755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81019
4037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.810194037
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.2733999200
Short name T262
Test name
Test status
Simulation time 22844853271 ps
CPU time 50.84 seconds
Started Jun 28 06:08:29 PM PDT 24
Finished Jun 28 06:09:22 PM PDT 24
Peak memory 206460 kb
Host smart-ba3e89c3-6b5c-4965-b797-161937e77149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27339
99200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.2733999200
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.711693802
Short name T2616
Test name
Test status
Simulation time 184658687 ps
CPU time 0.83 seconds
Started Jun 28 06:08:32 PM PDT 24
Finished Jun 28 06:08:34 PM PDT 24
Peak memory 206148 kb
Host smart-53ae1212-0bab-4e92-9cbb-7bdd8fae8643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71169
3802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.711693802
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.1875351438
Short name T465
Test name
Test status
Simulation time 187609192 ps
CPU time 0.84 seconds
Started Jun 28 06:08:31 PM PDT 24
Finished Jun 28 06:08:34 PM PDT 24
Peak memory 206204 kb
Host smart-3cd96c59-23d9-468d-88e7-4f29f93be4fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18753
51438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.1875351438
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.815011848
Short name T1458
Test name
Test status
Simulation time 5873611247 ps
CPU time 37.88 seconds
Started Jun 28 06:08:28 PM PDT 24
Finished Jun 28 06:09:08 PM PDT 24
Peak memory 206468 kb
Host smart-b1650c83-809d-45e5-9a96-1f6da0d6b40b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=815011848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.815011848
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.2359344717
Short name T1205
Test name
Test status
Simulation time 15933940426 ps
CPU time 116.04 seconds
Started Jun 28 06:08:26 PM PDT 24
Finished Jun 28 06:10:25 PM PDT 24
Peak memory 206504 kb
Host smart-1331594c-06f0-4720-a491-f2722fa9a32a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2359344717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.2359344717
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.1335066801
Short name T404
Test name
Test status
Simulation time 194888805 ps
CPU time 0.79 seconds
Started Jun 28 06:08:30 PM PDT 24
Finished Jun 28 06:08:33 PM PDT 24
Peak memory 206212 kb
Host smart-fcbd3dd0-2fcb-48bc-9213-51cc37022d65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13350
66801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.1335066801
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.719916019
Short name T709
Test name
Test status
Simulation time 190614593 ps
CPU time 0.88 seconds
Started Jun 28 06:08:25 PM PDT 24
Finished Jun 28 06:08:29 PM PDT 24
Peak memory 206168 kb
Host smart-4625e616-95ee-4bb3-9a78-e9a4693eaa78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71991
6019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.719916019
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.156635348
Short name T1664
Test name
Test status
Simulation time 212752389 ps
CPU time 0.84 seconds
Started Jun 28 06:08:28 PM PDT 24
Finished Jun 28 06:08:31 PM PDT 24
Peak memory 205964 kb
Host smart-2a9491e2-cf8d-4afe-a9dc-d5b215e29c71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15663
5348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.156635348
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.3161695646
Short name T214
Test name
Test status
Simulation time 262560529 ps
CPU time 1.07 seconds
Started Jun 28 06:08:28 PM PDT 24
Finished Jun 28 06:08:32 PM PDT 24
Peak memory 224076 kb
Host smart-e3325a66-6bc4-486b-ad89-83430bd8447d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3161695646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.3161695646
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.498472186
Short name T179
Test name
Test status
Simulation time 194975889 ps
CPU time 0.88 seconds
Started Jun 28 06:08:24 PM PDT 24
Finished Jun 28 06:08:27 PM PDT 24
Peak memory 206196 kb
Host smart-b59c48e4-0996-460f-b59b-a54ffea1ddb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49847
2186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.498472186
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.2541269766
Short name T1545
Test name
Test status
Simulation time 155595580 ps
CPU time 0.86 seconds
Started Jun 28 06:08:24 PM PDT 24
Finished Jun 28 06:08:27 PM PDT 24
Peak memory 206116 kb
Host smart-252a4bf5-af3d-4e8e-be91-d5e1d2388d07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25412
69766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.2541269766
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.4231177918
Short name T1436
Test name
Test status
Simulation time 164382694 ps
CPU time 0.8 seconds
Started Jun 28 06:08:28 PM PDT 24
Finished Jun 28 06:08:31 PM PDT 24
Peak memory 206192 kb
Host smart-7a5367ff-8f7a-44df-b7d0-2010529fd3c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42311
77918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.4231177918
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.374685640
Short name T1798
Test name
Test status
Simulation time 228443786 ps
CPU time 0.94 seconds
Started Jun 28 06:08:24 PM PDT 24
Finished Jun 28 06:08:28 PM PDT 24
Peak memory 206164 kb
Host smart-d1165094-8c07-42c4-b975-1cb2209012ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37468
5640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.374685640
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.2392832010
Short name T1683
Test name
Test status
Simulation time 4918595320 ps
CPU time 46.17 seconds
Started Jun 28 06:08:26 PM PDT 24
Finished Jun 28 06:09:14 PM PDT 24
Peak memory 206428 kb
Host smart-7d79b58e-d584-421e-867d-1a6280a7b09a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2392832010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.2392832010
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.1817324059
Short name T1106
Test name
Test status
Simulation time 192813308 ps
CPU time 0.9 seconds
Started Jun 28 06:08:32 PM PDT 24
Finished Jun 28 06:08:34 PM PDT 24
Peak memory 206176 kb
Host smart-095778d9-6ea8-4e19-b6a1-4304882f8b7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18173
24059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.1817324059
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.1169914501
Short name T1255
Test name
Test status
Simulation time 189487202 ps
CPU time 0.89 seconds
Started Jun 28 06:08:32 PM PDT 24
Finished Jun 28 06:08:34 PM PDT 24
Peak memory 206156 kb
Host smart-fe25aa3d-b1cb-4d1f-9896-c1b091075582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11699
14501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.1169914501
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.234065684
Short name T2386
Test name
Test status
Simulation time 5234212391 ps
CPU time 49.17 seconds
Started Jun 28 06:08:25 PM PDT 24
Finished Jun 28 06:09:17 PM PDT 24
Peak memory 206388 kb
Host smart-a125e0ed-02f6-4acb-a71d-afabcac7b087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23406
5684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.234065684
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.1511074173
Short name T2249
Test name
Test status
Simulation time 12185311192 ps
CPU time 66.94 seconds
Started Jun 28 06:08:32 PM PDT 24
Finished Jun 28 06:09:40 PM PDT 24
Peak memory 205804 kb
Host smart-8fd84c98-bbf0-4501-9f6b-dc58eae1d61a
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1511074173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.1511074173
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.2096154194
Short name T1527
Test name
Test status
Simulation time 88203595 ps
CPU time 0.75 seconds
Started Jun 28 06:08:47 PM PDT 24
Finished Jun 28 06:08:50 PM PDT 24
Peak memory 206208 kb
Host smart-08622dd5-529b-479e-b916-34d1b3090b74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2096154194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.2096154194
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.3964139104
Short name T2109
Test name
Test status
Simulation time 3524775246 ps
CPU time 4.22 seconds
Started Jun 28 06:08:29 PM PDT 24
Finished Jun 28 06:08:35 PM PDT 24
Peak memory 206272 kb
Host smart-18b46127-bfb0-4936-93fd-93b54b19b342
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3964139104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.3964139104
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.1727736456
Short name T1927
Test name
Test status
Simulation time 13398129254 ps
CPU time 12.83 seconds
Started Jun 28 06:08:29 PM PDT 24
Finished Jun 28 06:08:44 PM PDT 24
Peak memory 205836 kb
Host smart-6a287859-16a5-45d5-bbb2-a926e780db68
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1727736456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.1727736456
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.3722865729
Short name T1387
Test name
Test status
Simulation time 23498887453 ps
CPU time 24.91 seconds
Started Jun 28 06:08:29 PM PDT 24
Finished Jun 28 06:08:56 PM PDT 24
Peak memory 205904 kb
Host smart-fef53267-419b-4393-bd28-5868ab402c41
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3722865729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.3722865729
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.3693871371
Short name T356
Test name
Test status
Simulation time 148475057 ps
CPU time 0.8 seconds
Started Jun 28 06:08:25 PM PDT 24
Finished Jun 28 06:08:28 PM PDT 24
Peak memory 206144 kb
Host smart-13342e25-3d66-4b89-9b41-b0a962ab863e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36938
71371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.3693871371
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.1079958160
Short name T2524
Test name
Test status
Simulation time 138420939 ps
CPU time 0.8 seconds
Started Jun 28 06:08:25 PM PDT 24
Finished Jun 28 06:08:29 PM PDT 24
Peak memory 206188 kb
Host smart-abe830ba-8b6b-4b7b-a5f9-728fcc8cc00d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10799
58160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.1079958160
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.4147202794
Short name T2543
Test name
Test status
Simulation time 144022840 ps
CPU time 0.83 seconds
Started Jun 28 06:08:28 PM PDT 24
Finished Jun 28 06:08:31 PM PDT 24
Peak memory 206196 kb
Host smart-6ac9f4a3-fbac-4d92-af9a-8f55207a8e3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41472
02794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.4147202794
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.2675942879
Short name T1768
Test name
Test status
Simulation time 164958062 ps
CPU time 0.82 seconds
Started Jun 28 06:08:32 PM PDT 24
Finished Jun 28 06:08:34 PM PDT 24
Peak memory 205544 kb
Host smart-6df67c07-b4d4-4685-98c4-4c7c8f0f1ee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26759
42879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.2675942879
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.162049949
Short name T98
Test name
Test status
Simulation time 663262480 ps
CPU time 1.63 seconds
Started Jun 28 06:08:28 PM PDT 24
Finished Jun 28 06:08:32 PM PDT 24
Peak memory 206192 kb
Host smart-a4f8244c-7c1e-480d-9413-c0c16864fab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16204
9949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.162049949
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.2289781765
Short name T1199
Test name
Test status
Simulation time 6444389056 ps
CPU time 11.12 seconds
Started Jun 28 06:08:25 PM PDT 24
Finished Jun 28 06:08:39 PM PDT 24
Peak memory 206412 kb
Host smart-31ef1cbd-66a7-4907-9f58-ec512d3080d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22897
81765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.2289781765
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.2146146201
Short name T1498
Test name
Test status
Simulation time 334596428 ps
CPU time 1.12 seconds
Started Jun 28 06:08:26 PM PDT 24
Finished Jun 28 06:08:30 PM PDT 24
Peak memory 206212 kb
Host smart-81302e10-ba72-4ae6-88c5-bf2e6207aeeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21461
46201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.2146146201
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.3495093240
Short name T1741
Test name
Test status
Simulation time 153456486 ps
CPU time 0.83 seconds
Started Jun 28 06:08:28 PM PDT 24
Finished Jun 28 06:08:31 PM PDT 24
Peak memory 206192 kb
Host smart-de7cdbdb-9a5d-48d9-8035-b9f4ec61cb02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34950
93240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.3495093240
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.144506268
Short name T1706
Test name
Test status
Simulation time 38653162 ps
CPU time 0.66 seconds
Started Jun 28 06:08:25 PM PDT 24
Finished Jun 28 06:08:28 PM PDT 24
Peak memory 206156 kb
Host smart-dfbf9e9b-31e6-482a-9901-d4c6e94d6714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14450
6268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.144506268
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.1971593388
Short name T782
Test name
Test status
Simulation time 1088402628 ps
CPU time 2.34 seconds
Started Jun 28 06:08:26 PM PDT 24
Finished Jun 28 06:08:31 PM PDT 24
Peak memory 206288 kb
Host smart-d507ef7a-b2b8-400f-8a35-a98b48943b06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19715
93388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.1971593388
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.1828023214
Short name T1325
Test name
Test status
Simulation time 289920901 ps
CPU time 1.65 seconds
Started Jun 28 06:08:26 PM PDT 24
Finished Jun 28 06:08:31 PM PDT 24
Peak memory 206368 kb
Host smart-a984a870-8eaf-4267-a525-d3b13cf974be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18280
23214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.1828023214
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.3926025279
Short name T770
Test name
Test status
Simulation time 201166815 ps
CPU time 0.82 seconds
Started Jun 28 06:08:29 PM PDT 24
Finished Jun 28 06:08:32 PM PDT 24
Peak memory 206204 kb
Host smart-a13df125-d801-4d0a-bbe4-25ede9c57427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39260
25279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.3926025279
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.1252087835
Short name T1792
Test name
Test status
Simulation time 255339948 ps
CPU time 1.01 seconds
Started Jun 28 06:08:38 PM PDT 24
Finished Jun 28 06:08:40 PM PDT 24
Peak memory 206208 kb
Host smart-a23ca567-840f-481e-a357-47b870e3b4be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12520
87835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.1252087835
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.1095022726
Short name T2357
Test name
Test status
Simulation time 4939490671 ps
CPU time 46.85 seconds
Started Jun 28 06:08:28 PM PDT 24
Finished Jun 28 06:09:17 PM PDT 24
Peak memory 206420 kb
Host smart-3d045f46-900c-4188-b71f-ab4a90265f03
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1095022726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.1095022726
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.3613961147
Short name T2510
Test name
Test status
Simulation time 248780432 ps
CPU time 0.96 seconds
Started Jun 28 06:08:38 PM PDT 24
Finished Jun 28 06:08:41 PM PDT 24
Peak memory 206192 kb
Host smart-27f6da32-719a-452f-9212-634c4d28c914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36139
61147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.3613961147
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.2451720472
Short name T413
Test name
Test status
Simulation time 23316191340 ps
CPU time 22.85 seconds
Started Jun 28 06:08:39 PM PDT 24
Finished Jun 28 06:09:03 PM PDT 24
Peak memory 206308 kb
Host smart-bc45dab5-6622-461a-ae3c-b68ed030c8e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24517
20472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.2451720472
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.671216728
Short name T1986
Test name
Test status
Simulation time 3298862331 ps
CPU time 4.16 seconds
Started Jun 28 06:08:38 PM PDT 24
Finished Jun 28 06:08:43 PM PDT 24
Peak memory 206248 kb
Host smart-94520aec-2ceb-4ee3-bfa4-2b4b2564962b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67121
6728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.671216728
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.274225731
Short name T422
Test name
Test status
Simulation time 7469844383 ps
CPU time 56.17 seconds
Started Jun 28 06:08:39 PM PDT 24
Finished Jun 28 06:09:37 PM PDT 24
Peak memory 206480 kb
Host smart-a60a1767-1edc-4579-a746-7d081884a1f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27422
5731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.274225731
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.903981590
Short name T867
Test name
Test status
Simulation time 2829666993 ps
CPU time 20.06 seconds
Started Jun 28 06:08:38 PM PDT 24
Finished Jun 28 06:09:00 PM PDT 24
Peak memory 206424 kb
Host smart-e41be172-8cf4-4237-963c-2cb929a86c68
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=903981590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.903981590
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.3623812197
Short name T879
Test name
Test status
Simulation time 296534877 ps
CPU time 0.96 seconds
Started Jun 28 06:08:37 PM PDT 24
Finished Jun 28 06:08:39 PM PDT 24
Peak memory 206168 kb
Host smart-248451f8-8966-4665-bed2-b10bf5a667f1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3623812197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.3623812197
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.2860941081
Short name T1040
Test name
Test status
Simulation time 195720367 ps
CPU time 0.85 seconds
Started Jun 28 06:08:41 PM PDT 24
Finished Jun 28 06:08:46 PM PDT 24
Peak memory 206068 kb
Host smart-24c0f016-f16e-48ce-89dc-8b6aa8798f20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28609
41081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.2860941081
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.3813770976
Short name T364
Test name
Test status
Simulation time 6390879212 ps
CPU time 177.2 seconds
Started Jun 28 06:08:39 PM PDT 24
Finished Jun 28 06:11:38 PM PDT 24
Peak memory 206376 kb
Host smart-03a4bf87-8ac9-4393-b5df-b618d6f609ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38137
70976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.3813770976
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.2708207899
Short name T1883
Test name
Test status
Simulation time 7079600866 ps
CPU time 66.51 seconds
Started Jun 28 06:08:38 PM PDT 24
Finished Jun 28 06:09:45 PM PDT 24
Peak memory 206372 kb
Host smart-899c61f0-e99e-4278-97c8-34e83616611c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2708207899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.2708207899
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.4056727215
Short name T1494
Test name
Test status
Simulation time 244662916 ps
CPU time 0.91 seconds
Started Jun 28 06:08:40 PM PDT 24
Finished Jun 28 06:08:44 PM PDT 24
Peak memory 206220 kb
Host smart-bab043ad-07fb-479e-93f5-382f5ca1fd45
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4056727215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.4056727215
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.2387106224
Short name T887
Test name
Test status
Simulation time 164507100 ps
CPU time 0.8 seconds
Started Jun 28 06:08:37 PM PDT 24
Finished Jun 28 06:08:39 PM PDT 24
Peak memory 206188 kb
Host smart-e4079d64-33d2-4c3b-b0d0-577beccb998e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23871
06224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.2387106224
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.4168687004
Short name T535
Test name
Test status
Simulation time 176102421 ps
CPU time 0.84 seconds
Started Jun 28 06:08:39 PM PDT 24
Finished Jun 28 06:08:42 PM PDT 24
Peak memory 206196 kb
Host smart-66f18939-7d66-4df3-bdf3-4035de7ca882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41686
87004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.4168687004
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.2214009337
Short name T515
Test name
Test status
Simulation time 154775657 ps
CPU time 0.82 seconds
Started Jun 28 06:08:40 PM PDT 24
Finished Jun 28 06:08:45 PM PDT 24
Peak memory 206212 kb
Host smart-d0d2d1a6-97b6-43d5-a43d-30afe7e4064b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22140
09337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.2214009337
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.3439793168
Short name T2451
Test name
Test status
Simulation time 180842832 ps
CPU time 0.8 seconds
Started Jun 28 06:08:39 PM PDT 24
Finished Jun 28 06:08:41 PM PDT 24
Peak memory 206192 kb
Host smart-915754df-e8e0-423e-917f-204fc3fd7819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34397
93168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.3439793168
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.828849831
Short name T1661
Test name
Test status
Simulation time 164654013 ps
CPU time 0.8 seconds
Started Jun 28 06:08:37 PM PDT 24
Finished Jun 28 06:08:39 PM PDT 24
Peak memory 206192 kb
Host smart-a24f99bf-93f4-44d1-8af8-113274753b60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82884
9831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.828849831
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.643673879
Short name T674
Test name
Test status
Simulation time 212641266 ps
CPU time 0.91 seconds
Started Jun 28 06:08:40 PM PDT 24
Finished Jun 28 06:08:45 PM PDT 24
Peak memory 206180 kb
Host smart-1fa8084a-9a56-4b49-b9df-a76e8e1864e9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=643673879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.643673879
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.1239983416
Short name T2330
Test name
Test status
Simulation time 230710160 ps
CPU time 0.96 seconds
Started Jun 28 06:08:40 PM PDT 24
Finished Jun 28 06:08:43 PM PDT 24
Peak memory 206196 kb
Host smart-6a42c0ef-e217-45ca-b041-20e9b36f96fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12399
83416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.1239983416
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.1465187269
Short name T737
Test name
Test status
Simulation time 144570790 ps
CPU time 0.79 seconds
Started Jun 28 06:08:43 PM PDT 24
Finished Jun 28 06:08:47 PM PDT 24
Peak memory 206208 kb
Host smart-01956c5e-f7e0-481d-b56a-c472fdaba47b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14651
87269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.1465187269
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.1762636006
Short name T1602
Test name
Test status
Simulation time 45851284 ps
CPU time 0.71 seconds
Started Jun 28 06:08:41 PM PDT 24
Finished Jun 28 06:08:45 PM PDT 24
Peak memory 206200 kb
Host smart-6ba988a6-ea8e-40d4-8537-c5bef50bf374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17626
36006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.1762636006
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.2886577662
Short name T2453
Test name
Test status
Simulation time 12528705128 ps
CPU time 29.31 seconds
Started Jun 28 06:08:39 PM PDT 24
Finished Jun 28 06:09:10 PM PDT 24
Peak memory 206432 kb
Host smart-dbf8b3bb-9850-4664-8fd8-19c6ea095f7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28865
77662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.2886577662
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.4000769763
Short name T2398
Test name
Test status
Simulation time 161438188 ps
CPU time 0.8 seconds
Started Jun 28 06:08:40 PM PDT 24
Finished Jun 28 06:08:44 PM PDT 24
Peak memory 206188 kb
Host smart-cab1b69b-8880-4471-ae7d-8608e6746cce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40007
69763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.4000769763
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.349443406
Short name T1358
Test name
Test status
Simulation time 242452338 ps
CPU time 0.9 seconds
Started Jun 28 06:08:38 PM PDT 24
Finished Jun 28 06:08:41 PM PDT 24
Peak memory 206188 kb
Host smart-702b118a-b319-47f9-9d45-a993b2632b35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34944
3406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.349443406
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.37726689
Short name T1488
Test name
Test status
Simulation time 10308363187 ps
CPU time 52.52 seconds
Started Jun 28 06:08:42 PM PDT 24
Finished Jun 28 06:09:38 PM PDT 24
Peak memory 206452 kb
Host smart-53f5dc5f-6cf9-4b08-8056-a2243f33b081
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=37726689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.37726689
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.4055274515
Short name T1937
Test name
Test status
Simulation time 8979012172 ps
CPU time 56.24 seconds
Started Jun 28 06:08:40 PM PDT 24
Finished Jun 28 06:09:39 PM PDT 24
Peak memory 206504 kb
Host smart-de1b334c-f15e-403d-84c2-55f4b2afef81
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4055274515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.4055274515
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.200529628
Short name T2197
Test name
Test status
Simulation time 230488189 ps
CPU time 0.88 seconds
Started Jun 28 06:08:40 PM PDT 24
Finished Jun 28 06:08:45 PM PDT 24
Peak memory 206216 kb
Host smart-7fe32dd3-d7de-4198-a879-58d26a20f7c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20052
9628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.200529628
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.3082806603
Short name T1063
Test name
Test status
Simulation time 188121077 ps
CPU time 0.84 seconds
Started Jun 28 06:08:43 PM PDT 24
Finished Jun 28 06:08:47 PM PDT 24
Peak memory 206196 kb
Host smart-b772993d-0c03-458b-8db8-534a5b904339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30828
06603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.3082806603
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.656383078
Short name T1616
Test name
Test status
Simulation time 208630923 ps
CPU time 0.82 seconds
Started Jun 28 06:08:41 PM PDT 24
Finished Jun 28 06:08:46 PM PDT 24
Peak memory 206188 kb
Host smart-c9d878d8-2aca-4600-9707-15981784e1dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65638
3078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.656383078
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.1521249835
Short name T71
Test name
Test status
Simulation time 185273147 ps
CPU time 0.84 seconds
Started Jun 28 06:08:46 PM PDT 24
Finished Jun 28 06:08:49 PM PDT 24
Peak memory 206200 kb
Host smart-a364d9f8-dbc2-43d8-9d2c-4fddb426aeeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15212
49835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.1521249835
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.3028371304
Short name T202
Test name
Test status
Simulation time 218641864 ps
CPU time 1.06 seconds
Started Jun 28 06:08:46 PM PDT 24
Finished Jun 28 06:08:50 PM PDT 24
Peak memory 224076 kb
Host smart-c07b2020-f8eb-4f2e-97ff-5a0881612fa7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3028371304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.3028371304
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.3291179676
Short name T47
Test name
Test status
Simulation time 400955417 ps
CPU time 1.36 seconds
Started Jun 28 06:08:43 PM PDT 24
Finished Jun 28 06:08:48 PM PDT 24
Peak memory 206188 kb
Host smart-5c73926a-28f4-40e8-afae-558d3078abf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32911
79676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.3291179676
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.192936611
Short name T639
Test name
Test status
Simulation time 207776250 ps
CPU time 0.93 seconds
Started Jun 28 06:08:40 PM PDT 24
Finished Jun 28 06:08:44 PM PDT 24
Peak memory 206172 kb
Host smart-61d04351-ddd2-4922-8a78-31e866bb0d44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19293
6611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.192936611
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.3037380053
Short name T621
Test name
Test status
Simulation time 163077073 ps
CPU time 0.78 seconds
Started Jun 28 06:08:46 PM PDT 24
Finished Jun 28 06:08:49 PM PDT 24
Peak memory 206196 kb
Host smart-31502f76-fa6c-498b-b118-b8ae532c4a9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30373
80053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.3037380053
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.2253772086
Short name T2475
Test name
Test status
Simulation time 148528081 ps
CPU time 0.78 seconds
Started Jun 28 06:08:43 PM PDT 24
Finished Jun 28 06:08:47 PM PDT 24
Peak memory 206184 kb
Host smart-25057f07-cf0f-4522-bd7c-9086d112c70f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22537
72086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.2253772086
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.3373227386
Short name T1974
Test name
Test status
Simulation time 245202368 ps
CPU time 1.03 seconds
Started Jun 28 06:08:46 PM PDT 24
Finished Jun 28 06:08:49 PM PDT 24
Peak memory 206180 kb
Host smart-24a981fb-0aac-4513-909a-ba095fcc3136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33732
27386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.3373227386
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.1282469168
Short name T337
Test name
Test status
Simulation time 4553329984 ps
CPU time 124.43 seconds
Started Jun 28 06:08:41 PM PDT 24
Finished Jun 28 06:10:49 PM PDT 24
Peak memory 206452 kb
Host smart-a1ed5a29-0e05-4b86-b192-e6e2fbdd8237
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1282469168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.1282469168
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.1268087287
Short name T1234
Test name
Test status
Simulation time 206401645 ps
CPU time 0.83 seconds
Started Jun 28 06:08:41 PM PDT 24
Finished Jun 28 06:08:46 PM PDT 24
Peak memory 206216 kb
Host smart-f8a77da3-3320-4097-816c-bdcf17e4d064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12680
87287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.1268087287
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.1709663562
Short name T1623
Test name
Test status
Simulation time 193516015 ps
CPU time 0.82 seconds
Started Jun 28 06:08:48 PM PDT 24
Finished Jun 28 06:08:51 PM PDT 24
Peak memory 206188 kb
Host smart-b19d8566-78d2-48ae-b859-f0f257e2cb71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17096
63562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.1709663562
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.3332827733
Short name T849
Test name
Test status
Simulation time 5058206025 ps
CPU time 48.82 seconds
Started Jun 28 06:08:45 PM PDT 24
Finished Jun 28 06:09:36 PM PDT 24
Peak memory 206356 kb
Host smart-312fc17d-118a-4eb5-a36f-bbe5e3c4ae94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33328
27733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.3332827733
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.157419674
Short name T1580
Test name
Test status
Simulation time 11017314669 ps
CPU time 95.05 seconds
Started Jun 28 06:08:43 PM PDT 24
Finished Jun 28 06:10:21 PM PDT 24
Peak memory 206488 kb
Host smart-e56040d7-6a0b-47a6-b053-8fa4232a08ae
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=157419674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.157419674
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.64682994
Short name T2571
Test name
Test status
Simulation time 26864288 ps
CPU time 0.69 seconds
Started Jun 28 06:10:04 PM PDT 24
Finished Jun 28 06:10:08 PM PDT 24
Peak memory 206196 kb
Host smart-756651dd-9ff0-489a-9bee-229a56f9d331
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=64682994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.64682994
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.47427635
Short name T2216
Test name
Test status
Simulation time 4224957141 ps
CPU time 4.9 seconds
Started Jun 28 06:10:06 PM PDT 24
Finished Jun 28 06:10:14 PM PDT 24
Peak memory 206268 kb
Host smart-b26b651c-518c-4bfa-964b-a2c396c28fe5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=47427635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.47427635
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.3261360961
Short name T1213
Test name
Test status
Simulation time 13325882431 ps
CPU time 15.77 seconds
Started Jun 28 06:09:51 PM PDT 24
Finished Jun 28 06:10:11 PM PDT 24
Peak memory 206372 kb
Host smart-9c723346-a8b4-403f-af0e-f0e5fb594c05
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3261360961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.3261360961
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.1163838305
Short name T1697
Test name
Test status
Simulation time 23382917918 ps
CPU time 28.78 seconds
Started Jun 28 06:10:02 PM PDT 24
Finished Jun 28 06:10:33 PM PDT 24
Peak memory 206332 kb
Host smart-62ed72aa-42f1-402a-84cb-d42a91509a5c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1163838305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.1163838305
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.3266816716
Short name T1434
Test name
Test status
Simulation time 155071173 ps
CPU time 0.8 seconds
Started Jun 28 06:09:52 PM PDT 24
Finished Jun 28 06:09:57 PM PDT 24
Peak memory 206188 kb
Host smart-9cefdc8a-8529-41e6-adbd-42bb394fe02a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32668
16716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.3266816716
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.3658716151
Short name T2443
Test name
Test status
Simulation time 343847437 ps
CPU time 1.16 seconds
Started Jun 28 06:09:50 PM PDT 24
Finished Jun 28 06:09:55 PM PDT 24
Peak memory 206168 kb
Host smart-ac5b9e5b-554a-47df-bb50-4db171af026c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36587
16151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.3658716151
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.3464563287
Short name T2595
Test name
Test status
Simulation time 642328544 ps
CPU time 1.61 seconds
Started Jun 28 06:09:58 PM PDT 24
Finished Jun 28 06:10:01 PM PDT 24
Peak memory 206352 kb
Host smart-98db4087-d324-44a9-9d4c-db4381845d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34645
63287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.3464563287
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.883389544
Short name T2152
Test name
Test status
Simulation time 10492592434 ps
CPU time 20.89 seconds
Started Jun 28 06:09:52 PM PDT 24
Finished Jun 28 06:10:17 PM PDT 24
Peak memory 206468 kb
Host smart-2cd5ada5-92df-4c8b-ab82-4017b8d44501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88338
9544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.883389544
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.1189295826
Short name T1524
Test name
Test status
Simulation time 374155335 ps
CPU time 1.26 seconds
Started Jun 28 06:09:53 PM PDT 24
Finished Jun 28 06:09:58 PM PDT 24
Peak memory 206092 kb
Host smart-49ca28dc-54ee-4689-b44a-20ab21b2047e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11892
95826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.1189295826
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.2946585786
Short name T529
Test name
Test status
Simulation time 196212251 ps
CPU time 0.83 seconds
Started Jun 28 06:09:52 PM PDT 24
Finished Jun 28 06:09:57 PM PDT 24
Peak memory 206168 kb
Host smart-f7444f1d-bb5d-4ea7-9f7b-e129e1099b34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29465
85786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.2946585786
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.3788121062
Short name T1581
Test name
Test status
Simulation time 67575015 ps
CPU time 0.68 seconds
Started Jun 28 06:09:52 PM PDT 24
Finished Jun 28 06:09:56 PM PDT 24
Peak memory 206184 kb
Host smart-e86e31e1-fdab-4e94-8f41-b5afccca6774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37881
21062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.3788121062
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.914228616
Short name T2182
Test name
Test status
Simulation time 883622691 ps
CPU time 2.06 seconds
Started Jun 28 06:09:50 PM PDT 24
Finished Jun 28 06:09:56 PM PDT 24
Peak memory 206340 kb
Host smart-75fade07-c16d-4abd-9a65-51754aa3f674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91422
8616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.914228616
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.3046528283
Short name T103
Test name
Test status
Simulation time 183312249 ps
CPU time 0.84 seconds
Started Jun 28 06:09:54 PM PDT 24
Finished Jun 28 06:09:58 PM PDT 24
Peak memory 206184 kb
Host smart-3455a36a-6dbf-42a7-a0af-ca28dcc452ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30465
28283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.3046528283
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.1258474488
Short name T949
Test name
Test status
Simulation time 210748758 ps
CPU time 0.86 seconds
Started Jun 28 06:09:52 PM PDT 24
Finished Jun 28 06:09:57 PM PDT 24
Peak memory 206188 kb
Host smart-1b230338-a5e9-4f63-a564-c2fcda1c5c61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12584
74488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.1258474488
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.3454184237
Short name T1188
Test name
Test status
Simulation time 187587846 ps
CPU time 0.88 seconds
Started Jun 28 06:09:49 PM PDT 24
Finished Jun 28 06:09:52 PM PDT 24
Peak memory 206208 kb
Host smart-71cd6380-6988-4fe3-8d1d-c740576143eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34541
84237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.3454184237
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.3686915699
Short name T1588
Test name
Test status
Simulation time 192322128 ps
CPU time 0.87 seconds
Started Jun 28 06:09:54 PM PDT 24
Finished Jun 28 06:09:58 PM PDT 24
Peak memory 206008 kb
Host smart-2dfe8d9e-cc6b-4792-91ca-ba5d7616f961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36869
15699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.3686915699
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.843644454
Short name T2183
Test name
Test status
Simulation time 23285542718 ps
CPU time 24.01 seconds
Started Jun 28 06:10:05 PM PDT 24
Finished Jun 28 06:10:33 PM PDT 24
Peak memory 206284 kb
Host smart-42c22ccd-ed3e-4cc9-8071-b6c26e880f3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84364
4454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.843644454
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.1786835829
Short name T1654
Test name
Test status
Simulation time 3336102061 ps
CPU time 3.49 seconds
Started Jun 28 06:10:03 PM PDT 24
Finished Jun 28 06:10:10 PM PDT 24
Peak memory 206220 kb
Host smart-b459262c-b8fa-4ca6-8b7f-43c9d6c15e39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17868
35829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.1786835829
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.3725543748
Short name T2012
Test name
Test status
Simulation time 8225367764 ps
CPU time 75.8 seconds
Started Jun 28 06:10:04 PM PDT 24
Finished Jun 28 06:11:24 PM PDT 24
Peak memory 206420 kb
Host smart-d022809d-b9ef-4114-b3e0-9de3477e7383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37255
43748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.3725543748
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.845123982
Short name T2258
Test name
Test status
Simulation time 4652489242 ps
CPU time 134.63 seconds
Started Jun 28 06:10:04 PM PDT 24
Finished Jun 28 06:12:22 PM PDT 24
Peak memory 206376 kb
Host smart-0163099e-5787-4495-9745-b75611215da1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=845123982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.845123982
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.4045921128
Short name T2171
Test name
Test status
Simulation time 274492311 ps
CPU time 1.01 seconds
Started Jun 28 06:10:03 PM PDT 24
Finished Jun 28 06:10:06 PM PDT 24
Peak memory 206212 kb
Host smart-2e333fad-3646-41df-ab5e-8651c4cbb179
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4045921128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.4045921128
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.3693326210
Short name T2378
Test name
Test status
Simulation time 185187035 ps
CPU time 0.84 seconds
Started Jun 28 06:10:07 PM PDT 24
Finished Jun 28 06:10:10 PM PDT 24
Peak memory 206140 kb
Host smart-5c7e248b-e5d2-4e0e-aaaf-cae00d1c72ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36933
26210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.3693326210
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.3987026654
Short name T1642
Test name
Test status
Simulation time 4279114008 ps
CPU time 122.69 seconds
Started Jun 28 06:10:04 PM PDT 24
Finished Jun 28 06:12:10 PM PDT 24
Peak memory 206448 kb
Host smart-29822196-7272-4b23-adb4-d8a79df93b84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39870
26654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.3987026654
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.1611636452
Short name T651
Test name
Test status
Simulation time 4083189573 ps
CPU time 29.02 seconds
Started Jun 28 06:10:01 PM PDT 24
Finished Jun 28 06:10:32 PM PDT 24
Peak memory 206460 kb
Host smart-a5f35aa5-4783-4aeb-8fd7-03cc8a27c53c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1611636452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.1611636452
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.1339902145
Short name T1620
Test name
Test status
Simulation time 145517132 ps
CPU time 0.79 seconds
Started Jun 28 06:10:04 PM PDT 24
Finished Jun 28 06:10:08 PM PDT 24
Peak memory 206216 kb
Host smart-41ef5824-eea6-4262-a33e-4f444700d233
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1339902145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.1339902145
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.1803373417
Short name T1857
Test name
Test status
Simulation time 145962881 ps
CPU time 0.75 seconds
Started Jun 28 06:10:05 PM PDT 24
Finished Jun 28 06:10:10 PM PDT 24
Peak memory 206332 kb
Host smart-b9bb4c1b-9868-4510-91b4-8e32948da7eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18033
73417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.1803373417
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.2852960290
Short name T2019
Test name
Test status
Simulation time 203216490 ps
CPU time 0.86 seconds
Started Jun 28 06:10:03 PM PDT 24
Finished Jun 28 06:10:07 PM PDT 24
Peak memory 206172 kb
Host smart-4c1f2108-5cbb-4db3-a52c-f9445c86cb6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28529
60290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.2852960290
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.857536961
Short name T1787
Test name
Test status
Simulation time 164617565 ps
CPU time 0.8 seconds
Started Jun 28 06:10:05 PM PDT 24
Finished Jun 28 06:10:10 PM PDT 24
Peak memory 206216 kb
Host smart-05c9f4c0-bca0-45b0-a50e-ff3ded54a8af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85753
6961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.857536961
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.2729443065
Short name T1397
Test name
Test status
Simulation time 172720480 ps
CPU time 0.81 seconds
Started Jun 28 06:10:07 PM PDT 24
Finished Jun 28 06:10:10 PM PDT 24
Peak memory 206216 kb
Host smart-36951be4-2f9e-4a05-bf1a-849277f01cf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27294
43065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.2729443065
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.632629220
Short name T1956
Test name
Test status
Simulation time 195548164 ps
CPU time 0.82 seconds
Started Jun 28 06:10:03 PM PDT 24
Finished Jun 28 06:10:07 PM PDT 24
Peak memory 206216 kb
Host smart-a57b36ce-cf3d-4ca6-b7f1-2b61e6a3feb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63262
9220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.632629220
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.1990753307
Short name T2407
Test name
Test status
Simulation time 248624936 ps
CPU time 0.97 seconds
Started Jun 28 06:10:02 PM PDT 24
Finished Jun 28 06:10:06 PM PDT 24
Peak memory 206216 kb
Host smart-b8c2cbcd-d10d-453a-b7ab-a105994f59c6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1990753307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.1990753307
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.2755322864
Short name T2546
Test name
Test status
Simulation time 157566446 ps
CPU time 0.77 seconds
Started Jun 28 06:10:05 PM PDT 24
Finished Jun 28 06:10:09 PM PDT 24
Peak memory 206196 kb
Host smart-f64c6395-9faa-4445-8290-0f8ed87f6a3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27553
22864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.2755322864
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.3123691625
Short name T2624
Test name
Test status
Simulation time 48427525 ps
CPU time 0.67 seconds
Started Jun 28 06:10:08 PM PDT 24
Finished Jun 28 06:10:11 PM PDT 24
Peak memory 206144 kb
Host smart-dce0af70-e4bb-447c-b2b7-8ed41ec14e96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31236
91625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.3123691625
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.542721404
Short name T1428
Test name
Test status
Simulation time 8032915259 ps
CPU time 16.75 seconds
Started Jun 28 06:10:05 PM PDT 24
Finished Jun 28 06:10:26 PM PDT 24
Peak memory 206404 kb
Host smart-7f259a97-b76e-4856-8b9b-c38b280f87af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54272
1404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.542721404
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.2828891925
Short name T1920
Test name
Test status
Simulation time 203092445 ps
CPU time 0.83 seconds
Started Jun 28 06:10:03 PM PDT 24
Finished Jun 28 06:10:07 PM PDT 24
Peak memory 206168 kb
Host smart-5ae4e23d-f919-4a7a-a530-8cfe82d3aff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28288
91925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.2828891925
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.2955251911
Short name T760
Test name
Test status
Simulation time 243047665 ps
CPU time 0.89 seconds
Started Jun 28 06:10:05 PM PDT 24
Finished Jun 28 06:10:09 PM PDT 24
Peak memory 206192 kb
Host smart-c243e6c3-28fa-452b-b06b-8bb59f6d93a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29552
51911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.2955251911
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.1012983610
Short name T479
Test name
Test status
Simulation time 257823870 ps
CPU time 0.88 seconds
Started Jun 28 06:10:01 PM PDT 24
Finished Jun 28 06:10:04 PM PDT 24
Peak memory 206212 kb
Host smart-7a9b898a-9f36-4661-b98e-7e23f067da89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10129
83610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.1012983610
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.4057453241
Short name T2619
Test name
Test status
Simulation time 155655059 ps
CPU time 0.8 seconds
Started Jun 28 06:10:04 PM PDT 24
Finished Jun 28 06:10:08 PM PDT 24
Peak memory 206176 kb
Host smart-7bbdce23-774d-4a85-b6e8-5ec8954092d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40574
53241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.4057453241
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.4120875058
Short name T874
Test name
Test status
Simulation time 157484685 ps
CPU time 0.74 seconds
Started Jun 28 06:10:04 PM PDT 24
Finished Jun 28 06:10:08 PM PDT 24
Peak memory 206188 kb
Host smart-f283e69c-9452-469b-8e75-92f58bb33f69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41208
75058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.4120875058
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.3532194102
Short name T1579
Test name
Test status
Simulation time 195738903 ps
CPU time 0.84 seconds
Started Jun 28 06:10:06 PM PDT 24
Finished Jun 28 06:10:10 PM PDT 24
Peak memory 206324 kb
Host smart-a2efb5ca-bf44-4bed-beb6-33dd827aee11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35321
94102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.3532194102
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.3862442165
Short name T2165
Test name
Test status
Simulation time 4978853003 ps
CPU time 141.68 seconds
Started Jun 28 06:10:04 PM PDT 24
Finished Jun 28 06:12:29 PM PDT 24
Peak memory 206464 kb
Host smart-8660e32f-8c47-4aa1-aa1b-9ac6d715b1f5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3862442165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.3862442165
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.1040322853
Short name T223
Test name
Test status
Simulation time 215988433 ps
CPU time 0.87 seconds
Started Jun 28 06:10:01 PM PDT 24
Finished Jun 28 06:10:04 PM PDT 24
Peak memory 206220 kb
Host smart-3bf050b8-2980-48b6-861a-971b265ed1ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10403
22853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.1040322853
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.4084234816
Short name T63
Test name
Test status
Simulation time 194910606 ps
CPU time 0.79 seconds
Started Jun 28 06:10:02 PM PDT 24
Finished Jun 28 06:10:06 PM PDT 24
Peak memory 206192 kb
Host smart-80b9c214-cb0f-460b-b3e0-13602b57eb43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40842
34816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.4084234816
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.3989463376
Short name T385
Test name
Test status
Simulation time 5371065640 ps
CPU time 37.18 seconds
Started Jun 28 06:10:03 PM PDT 24
Finished Jun 28 06:10:43 PM PDT 24
Peak memory 206472 kb
Host smart-1c86817f-ec84-4d68-9a93-6ffbe5f60fd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39894
63376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.3989463376
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.3822790490
Short name T1911
Test name
Test status
Simulation time 44695560 ps
CPU time 0.7 seconds
Started Jun 28 06:10:13 PM PDT 24
Finished Jun 28 06:10:15 PM PDT 24
Peak memory 206216 kb
Host smart-cff8b0d0-9e07-4856-8a4f-9c7979c0a776
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3822790490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.3822790490
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.2175445073
Short name T1729
Test name
Test status
Simulation time 3658698942 ps
CPU time 4.1 seconds
Started Jun 28 06:10:01 PM PDT 24
Finished Jun 28 06:10:07 PM PDT 24
Peak memory 206356 kb
Host smart-1dace271-0b8c-4733-93b8-1008298be120
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2175445073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.2175445073
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.1281472126
Short name T609
Test name
Test status
Simulation time 13350761741 ps
CPU time 12.94 seconds
Started Jun 28 06:10:03 PM PDT 24
Finished Jun 28 06:10:18 PM PDT 24
Peak memory 206268 kb
Host smart-687ee71b-e42e-4ff1-bfaf-56a832c916c2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1281472126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.1281472126
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.1852278443
Short name T1764
Test name
Test status
Simulation time 23300984140 ps
CPU time 21.9 seconds
Started Jun 28 06:10:03 PM PDT 24
Finished Jun 28 06:10:27 PM PDT 24
Peak memory 206372 kb
Host smart-c2af7d55-0d2e-4293-a0ef-98ab0443933f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1852278443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.1852278443
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.459798923
Short name T923
Test name
Test status
Simulation time 157832939 ps
CPU time 0.8 seconds
Started Jun 28 06:10:04 PM PDT 24
Finished Jun 28 06:10:08 PM PDT 24
Peak memory 206208 kb
Host smart-3d905aca-becd-4972-910c-5d89868f1181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45979
8923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.459798923
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.211023851
Short name T1168
Test name
Test status
Simulation time 190783060 ps
CPU time 0.81 seconds
Started Jun 28 06:10:03 PM PDT 24
Finished Jun 28 06:10:07 PM PDT 24
Peak memory 206156 kb
Host smart-b4396402-3bfa-46e9-a8b2-578c194fbc8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21102
3851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.211023851
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.4797180
Short name T1180
Test name
Test status
Simulation time 220680518 ps
CPU time 0.94 seconds
Started Jun 28 06:10:04 PM PDT 24
Finished Jun 28 06:10:09 PM PDT 24
Peak memory 206196 kb
Host smart-27b59a36-3767-400e-8ce2-df853c7ad1a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47971
80 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.4797180
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.2802155865
Short name T93
Test name
Test status
Simulation time 377817214 ps
CPU time 1.11 seconds
Started Jun 28 06:10:01 PM PDT 24
Finished Jun 28 06:10:04 PM PDT 24
Peak memory 206188 kb
Host smart-c71025a0-07a1-48d3-86e3-24e524cdbf1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28021
55865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.2802155865
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.826898048
Short name T1921
Test name
Test status
Simulation time 13386845101 ps
CPU time 23.81 seconds
Started Jun 28 06:10:05 PM PDT 24
Finished Jun 28 06:10:32 PM PDT 24
Peak memory 206440 kb
Host smart-5a5c0aba-dab9-4d49-bab4-1a166b620ed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82689
8048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.826898048
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.1442615745
Short name T2569
Test name
Test status
Simulation time 335674646 ps
CPU time 1.13 seconds
Started Jun 28 06:10:03 PM PDT 24
Finished Jun 28 06:10:07 PM PDT 24
Peak memory 206204 kb
Host smart-b219d74f-fe50-4289-8150-eb596d93b4f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14426
15745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.1442615745
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.1687524055
Short name T728
Test name
Test status
Simulation time 168158851 ps
CPU time 0.76 seconds
Started Jun 28 06:10:03 PM PDT 24
Finished Jun 28 06:10:07 PM PDT 24
Peak memory 206168 kb
Host smart-80ad3ec4-9b3f-4b20-af5d-f9b2ec820702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16875
24055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.1687524055
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.1790245429
Short name T1600
Test name
Test status
Simulation time 66663837 ps
CPU time 0.68 seconds
Started Jun 28 06:10:05 PM PDT 24
Finished Jun 28 06:10:10 PM PDT 24
Peak memory 206188 kb
Host smart-82795ef4-3b7a-4dc7-ac7d-8905d100f732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17902
45429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.1790245429
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.290820661
Short name T1804
Test name
Test status
Simulation time 915633125 ps
CPU time 2.2 seconds
Started Jun 28 06:10:04 PM PDT 24
Finished Jun 28 06:10:10 PM PDT 24
Peak memory 206232 kb
Host smart-5e270cc7-be2d-4515-a2f5-61449dcc2e7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29082
0661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.290820661
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.368545059
Short name T573
Test name
Test status
Simulation time 341154559 ps
CPU time 1.94 seconds
Started Jun 28 06:10:01 PM PDT 24
Finished Jun 28 06:10:05 PM PDT 24
Peak memory 206364 kb
Host smart-46ffa820-f02f-4c56-a400-4ea64893a91f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36854
5059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.368545059
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.1931203613
Short name T2136
Test name
Test status
Simulation time 164372834 ps
CPU time 0.85 seconds
Started Jun 28 06:10:09 PM PDT 24
Finished Jun 28 06:10:12 PM PDT 24
Peak memory 206192 kb
Host smart-cec2bdec-c5eb-4dc6-b3e9-3f965baf3b4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19312
03613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.1931203613
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.3863873903
Short name T1020
Test name
Test status
Simulation time 141331649 ps
CPU time 0.78 seconds
Started Jun 28 06:10:06 PM PDT 24
Finished Jun 28 06:10:10 PM PDT 24
Peak memory 206212 kb
Host smart-cdde0d82-ac76-4c32-94d8-a75e2added0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38638
73903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.3863873903
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.115402121
Short name T2573
Test name
Test status
Simulation time 197663194 ps
CPU time 0.91 seconds
Started Jun 28 06:10:03 PM PDT 24
Finished Jun 28 06:10:07 PM PDT 24
Peak memory 206208 kb
Host smart-4a17ff7e-a439-4ea6-a3ab-573aacd318eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11540
2121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.115402121
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_invalid_sync.1745669156
Short name T694
Test name
Test status
Simulation time 5864989831 ps
CPU time 52.11 seconds
Started Jun 28 06:10:04 PM PDT 24
Finished Jun 28 06:10:59 PM PDT 24
Peak memory 206412 kb
Host smart-b1cdf855-4327-41f0-ab6e-c9ec438af0e0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1745669156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_invalid_sync.1745669156
Directory /workspace/11.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.378594420
Short name T2207
Test name
Test status
Simulation time 215579555 ps
CPU time 0.91 seconds
Started Jun 28 06:10:02 PM PDT 24
Finished Jun 28 06:10:05 PM PDT 24
Peak memory 206172 kb
Host smart-f9ccee5a-372f-40b0-94ed-432943ae4e7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37859
4420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.378594420
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.1982093919
Short name T918
Test name
Test status
Simulation time 23287593461 ps
CPU time 23.5 seconds
Started Jun 28 06:10:03 PM PDT 24
Finished Jun 28 06:10:30 PM PDT 24
Peak memory 206316 kb
Host smart-014f77a4-6786-4769-be0c-c8f9c0653397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19820
93919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.1982093919
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.769180158
Short name T474
Test name
Test status
Simulation time 3263384004 ps
CPU time 3.91 seconds
Started Jun 28 06:10:01 PM PDT 24
Finished Jun 28 06:10:07 PM PDT 24
Peak memory 206252 kb
Host smart-accad908-d8fe-49ef-bdad-86609e58b597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76918
0158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.769180158
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.299302472
Short name T2325
Test name
Test status
Simulation time 7393148840 ps
CPU time 53.68 seconds
Started Jun 28 06:10:05 PM PDT 24
Finished Jun 28 06:11:03 PM PDT 24
Peak memory 206444 kb
Host smart-20c7a5f0-97e6-42f2-897c-2beabdf3e519
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29930
2472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.299302472
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.3637500838
Short name T2030
Test name
Test status
Simulation time 4187521946 ps
CPU time 29.82 seconds
Started Jun 28 06:10:10 PM PDT 24
Finished Jun 28 06:10:42 PM PDT 24
Peak memory 206500 kb
Host smart-068d574d-265a-4730-b2ad-b52fbce61b15
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3637500838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.3637500838
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.2017433601
Short name T1295
Test name
Test status
Simulation time 250507662 ps
CPU time 0.89 seconds
Started Jun 28 06:10:05 PM PDT 24
Finished Jun 28 06:10:10 PM PDT 24
Peak memory 206300 kb
Host smart-eeb04916-d364-4af0-8485-d6deba18c0d4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2017433601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.2017433601
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.501237685
Short name T331
Test name
Test status
Simulation time 196350887 ps
CPU time 0.96 seconds
Started Jun 28 06:10:10 PM PDT 24
Finished Jun 28 06:10:13 PM PDT 24
Peak memory 206216 kb
Host smart-34ee7865-d753-401a-b8c4-724b5b8fdb1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50123
7685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.501237685
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.1255158958
Short name T1955
Test name
Test status
Simulation time 6280161807 ps
CPU time 59.04 seconds
Started Jun 28 06:10:05 PM PDT 24
Finished Jun 28 06:11:07 PM PDT 24
Peak memory 206432 kb
Host smart-0edecb01-da87-476b-8f57-00dede30cf98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12551
58958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.1255158958
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.294092517
Short name T2228
Test name
Test status
Simulation time 5084688589 ps
CPU time 50.89 seconds
Started Jun 28 06:10:02 PM PDT 24
Finished Jun 28 06:10:55 PM PDT 24
Peak memory 206384 kb
Host smart-2fb7111f-e17f-4d34-8d6c-8cb91c5def2a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=294092517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.294092517
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.1121267215
Short name T925
Test name
Test status
Simulation time 145971550 ps
CPU time 0.83 seconds
Started Jun 28 06:10:10 PM PDT 24
Finished Jun 28 06:10:13 PM PDT 24
Peak memory 206068 kb
Host smart-5aa34412-8518-4862-b8ac-a7681f59ebe1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1121267215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.1121267215
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.2698485579
Short name T1002
Test name
Test status
Simulation time 155192489 ps
CPU time 0.82 seconds
Started Jun 28 06:10:02 PM PDT 24
Finished Jun 28 06:10:06 PM PDT 24
Peak memory 206200 kb
Host smart-1d19f798-28f3-4339-8461-67e85fe3b08d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26984
85579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.2698485579
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.379984734
Short name T1636
Test name
Test status
Simulation time 186451447 ps
CPU time 0.87 seconds
Started Jun 28 06:10:16 PM PDT 24
Finished Jun 28 06:10:20 PM PDT 24
Peak memory 206168 kb
Host smart-5322b79e-834d-4afc-9aa7-33aa01b9db9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37998
4734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.379984734
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.1844134835
Short name T1638
Test name
Test status
Simulation time 153086680 ps
CPU time 0.81 seconds
Started Jun 28 06:10:14 PM PDT 24
Finished Jun 28 06:10:16 PM PDT 24
Peak memory 206196 kb
Host smart-a6ae59cb-3718-4797-9516-aab8c7366fb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18441
34835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.1844134835
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.1768726349
Short name T948
Test name
Test status
Simulation time 147248988 ps
CPU time 0.87 seconds
Started Jun 28 06:10:12 PM PDT 24
Finished Jun 28 06:10:15 PM PDT 24
Peak memory 206216 kb
Host smart-098124b4-9a93-4cf1-9f3f-65ff7a7e2d66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17687
26349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.1768726349
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.3888648219
Short name T1311
Test name
Test status
Simulation time 149337540 ps
CPU time 0.83 seconds
Started Jun 28 06:10:15 PM PDT 24
Finished Jun 28 06:10:18 PM PDT 24
Peak memory 206188 kb
Host smart-702b8005-0265-4ff7-b349-554f29c603ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38886
48219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.3888648219
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.1918170125
Short name T1915
Test name
Test status
Simulation time 258235871 ps
CPU time 1.03 seconds
Started Jun 28 06:10:14 PM PDT 24
Finished Jun 28 06:10:16 PM PDT 24
Peak memory 206164 kb
Host smart-6afd0b29-16f7-4601-84b5-89b67c77c987
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1918170125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.1918170125
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.3287095663
Short name T1282
Test name
Test status
Simulation time 157575395 ps
CPU time 0.83 seconds
Started Jun 28 06:10:17 PM PDT 24
Finished Jun 28 06:10:22 PM PDT 24
Peak memory 206196 kb
Host smart-94b7f264-830d-4535-aa75-53323cbf1850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32870
95663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.3287095663
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.3674316506
Short name T1080
Test name
Test status
Simulation time 48585108 ps
CPU time 0.66 seconds
Started Jun 28 06:10:13 PM PDT 24
Finished Jun 28 06:10:15 PM PDT 24
Peak memory 206204 kb
Host smart-bd985783-713a-4c46-ab7c-de823dacfbfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36743
16506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.3674316506
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.384882137
Short name T2518
Test name
Test status
Simulation time 19984077169 ps
CPU time 49.51 seconds
Started Jun 28 06:10:12 PM PDT 24
Finished Jun 28 06:11:03 PM PDT 24
Peak memory 206516 kb
Host smart-43244f54-fc0b-4794-9fb5-083f486915fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38488
2137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.384882137
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.547565974
Short name T601
Test name
Test status
Simulation time 163232552 ps
CPU time 0.78 seconds
Started Jun 28 06:10:14 PM PDT 24
Finished Jun 28 06:10:16 PM PDT 24
Peak memory 206168 kb
Host smart-f3e0481b-60b8-4fdf-9915-1e3ad9bcce42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54756
5974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.547565974
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.502243999
Short name T2138
Test name
Test status
Simulation time 194765218 ps
CPU time 0.87 seconds
Started Jun 28 06:10:15 PM PDT 24
Finished Jun 28 06:10:18 PM PDT 24
Peak memory 206200 kb
Host smart-1d7f491f-b14f-4cbb-a873-15d8ff8cfe48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50224
3999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.502243999
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.1287238779
Short name T936
Test name
Test status
Simulation time 218901734 ps
CPU time 0.94 seconds
Started Jun 28 06:10:21 PM PDT 24
Finished Jun 28 06:10:25 PM PDT 24
Peak memory 206212 kb
Host smart-b3dcd2c6-6da7-442b-9ef7-b161dd9a0b81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12872
38779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.1287238779
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.1810600719
Short name T2370
Test name
Test status
Simulation time 187270776 ps
CPU time 0.87 seconds
Started Jun 28 06:10:16 PM PDT 24
Finished Jun 28 06:10:21 PM PDT 24
Peak memory 206204 kb
Host smart-532d6dd7-463a-4788-8044-adab9ad55287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18106
00719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.1810600719
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.1202010552
Short name T453
Test name
Test status
Simulation time 138668727 ps
CPU time 0.76 seconds
Started Jun 28 06:10:16 PM PDT 24
Finished Jun 28 06:10:20 PM PDT 24
Peak memory 206196 kb
Host smart-021613b7-7ebf-4dff-b3b2-eb13671e87e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12020
10552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.1202010552
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.3887081652
Short name T665
Test name
Test status
Simulation time 152671932 ps
CPU time 0.76 seconds
Started Jun 28 06:10:21 PM PDT 24
Finished Jun 28 06:10:24 PM PDT 24
Peak memory 206156 kb
Host smart-9d5b9b65-809b-4ab2-9529-23e00ba03927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38870
81652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.3887081652
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.2531897182
Short name T2053
Test name
Test status
Simulation time 168001731 ps
CPU time 0.78 seconds
Started Jun 28 06:10:16 PM PDT 24
Finished Jun 28 06:10:19 PM PDT 24
Peak memory 206160 kb
Host smart-cdf42597-ba70-4b92-b694-8cbcfbfe7de9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25318
97182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.2531897182
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.2721937819
Short name T1711
Test name
Test status
Simulation time 180043656 ps
CPU time 0.94 seconds
Started Jun 28 06:10:15 PM PDT 24
Finished Jun 28 06:10:18 PM PDT 24
Peak memory 206212 kb
Host smart-9d95b3cb-8a21-4c6b-b939-13a631fc1c2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27219
37819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.2721937819
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.497449154
Short name T1814
Test name
Test status
Simulation time 3620613940 ps
CPU time 26.94 seconds
Started Jun 28 06:10:13 PM PDT 24
Finished Jun 28 06:10:42 PM PDT 24
Peak memory 206436 kb
Host smart-6f83e3d1-218c-49e7-834a-16bb9e43c77b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=497449154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.497449154
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.1002768827
Short name T762
Test name
Test status
Simulation time 194033386 ps
CPU time 0.84 seconds
Started Jun 28 06:10:16 PM PDT 24
Finished Jun 28 06:10:20 PM PDT 24
Peak memory 206196 kb
Host smart-c2c1e7b2-0865-4c82-b0de-792716655c0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10027
68827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.1002768827
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.3882012711
Short name T850
Test name
Test status
Simulation time 153985125 ps
CPU time 0.79 seconds
Started Jun 28 06:10:16 PM PDT 24
Finished Jun 28 06:10:20 PM PDT 24
Peak memory 206164 kb
Host smart-98586909-7032-4d59-8279-b9a905dce938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38820
12711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.3882012711
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.1835758318
Short name T2025
Test name
Test status
Simulation time 3887309753 ps
CPU time 38.18 seconds
Started Jun 28 06:10:17 PM PDT 24
Finished Jun 28 06:10:59 PM PDT 24
Peak memory 206392 kb
Host smart-c3e93fe5-21d7-43b5-b041-9a317c0beb1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18357
58318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.1835758318
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.781932651
Short name T1766
Test name
Test status
Simulation time 42523859 ps
CPU time 0.69 seconds
Started Jun 28 06:10:39 PM PDT 24
Finished Jun 28 06:10:44 PM PDT 24
Peak memory 206208 kb
Host smart-934ca184-a033-4cb4-b154-3708f6fafe68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=781932651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.781932651
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.1142576180
Short name T1268
Test name
Test status
Simulation time 13327229867 ps
CPU time 12.78 seconds
Started Jun 28 06:10:21 PM PDT 24
Finished Jun 28 06:10:37 PM PDT 24
Peak memory 206252 kb
Host smart-8b9922ce-682d-4440-be33-4ff414217f27
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1142576180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.1142576180
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.209477568
Short name T968
Test name
Test status
Simulation time 23307157221 ps
CPU time 23.74 seconds
Started Jun 28 06:10:16 PM PDT 24
Finished Jun 28 06:10:42 PM PDT 24
Peak memory 206296 kb
Host smart-d9e9839d-97ec-46d3-8744-901137fb72f0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=209477568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.209477568
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.1698059356
Short name T642
Test name
Test status
Simulation time 221367116 ps
CPU time 0.91 seconds
Started Jun 28 06:10:18 PM PDT 24
Finished Jun 28 06:10:23 PM PDT 24
Peak memory 206152 kb
Host smart-84a0cc31-7631-498d-9cca-ea24d3d0f29b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16980
59356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.1698059356
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.998983079
Short name T55
Test name
Test status
Simulation time 181303399 ps
CPU time 0.8 seconds
Started Jun 28 06:10:13 PM PDT 24
Finished Jun 28 06:10:16 PM PDT 24
Peak memory 206172 kb
Host smart-ca062493-55fb-4a28-a5e3-02eadf06e971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99898
3079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.998983079
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.3038522507
Short name T1181
Test name
Test status
Simulation time 432169963 ps
CPU time 1.35 seconds
Started Jun 28 06:10:14 PM PDT 24
Finished Jun 28 06:10:17 PM PDT 24
Peak memory 206324 kb
Host smart-74d14663-8d89-4f81-baa2-757eb597634e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30385
22507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.3038522507
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.254430152
Short name T1877
Test name
Test status
Simulation time 963624305 ps
CPU time 2.23 seconds
Started Jun 28 06:10:21 PM PDT 24
Finished Jun 28 06:10:27 PM PDT 24
Peak memory 206292 kb
Host smart-cb702e9a-1dbd-42f3-987c-e68955c037d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25443
0152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.254430152
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.1223417773
Short name T1307
Test name
Test status
Simulation time 14937052555 ps
CPU time 32.45 seconds
Started Jun 28 06:10:17 PM PDT 24
Finished Jun 28 06:10:53 PM PDT 24
Peak memory 206452 kb
Host smart-3e0ce426-cd33-4d9b-adba-018f0ffe93e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12234
17773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.1223417773
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.414841585
Short name T1990
Test name
Test status
Simulation time 459629725 ps
CPU time 1.41 seconds
Started Jun 28 06:10:17 PM PDT 24
Finished Jun 28 06:10:22 PM PDT 24
Peak memory 206216 kb
Host smart-1859ee52-f72b-4159-9147-24ce951f00a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41484
1585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.414841585
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.2893073434
Short name T554
Test name
Test status
Simulation time 145536325 ps
CPU time 0.79 seconds
Started Jun 28 06:10:15 PM PDT 24
Finished Jun 28 06:10:18 PM PDT 24
Peak memory 206156 kb
Host smart-d2219ed8-2713-49f4-bcd5-055e296822c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28930
73434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.2893073434
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.1810227156
Short name T1559
Test name
Test status
Simulation time 62662816 ps
CPU time 0.71 seconds
Started Jun 28 06:10:16 PM PDT 24
Finished Jun 28 06:10:20 PM PDT 24
Peak memory 206192 kb
Host smart-f8b6a47d-31cf-4c4c-a87f-4c78ff5f846d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18102
27156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.1810227156
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.3656248825
Short name T627
Test name
Test status
Simulation time 1112419951 ps
CPU time 2.36 seconds
Started Jun 28 06:10:17 PM PDT 24
Finished Jun 28 06:10:23 PM PDT 24
Peak memory 206336 kb
Host smart-4556e99a-590e-4a14-9167-b8a5283d6f51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36562
48825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.3656248825
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.2625779575
Short name T1211
Test name
Test status
Simulation time 188952648 ps
CPU time 1.26 seconds
Started Jun 28 06:10:15 PM PDT 24
Finished Jun 28 06:10:18 PM PDT 24
Peak memory 206332 kb
Host smart-dc04a81e-87ec-4aac-b231-e6ed510c13be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26257
79575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.2625779575
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.1868399236
Short name T1905
Test name
Test status
Simulation time 165114564 ps
CPU time 0.83 seconds
Started Jun 28 06:10:17 PM PDT 24
Finished Jun 28 06:10:21 PM PDT 24
Peak memory 206188 kb
Host smart-19e8a981-c228-4ebc-a704-4c7174e0220e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18683
99236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.1868399236
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.1114496186
Short name T1300
Test name
Test status
Simulation time 155579578 ps
CPU time 0.89 seconds
Started Jun 28 06:10:12 PM PDT 24
Finished Jun 28 06:10:14 PM PDT 24
Peak memory 206212 kb
Host smart-0935a357-a932-434a-9d7b-99d98f4e8872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11144
96186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.1114496186
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.4037129507
Short name T1347
Test name
Test status
Simulation time 235693927 ps
CPU time 0.92 seconds
Started Jun 28 06:10:14 PM PDT 24
Finished Jun 28 06:10:17 PM PDT 24
Peak memory 205820 kb
Host smart-889ac83b-4da8-4394-9d9b-5bda962f498c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40371
29507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.4037129507
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_invalid_sync.2953461188
Short name T1450
Test name
Test status
Simulation time 10432105105 ps
CPU time 97.34 seconds
Started Jun 28 06:10:11 PM PDT 24
Finished Jun 28 06:11:50 PM PDT 24
Peak memory 206436 kb
Host smart-dcbc3cb9-2173-42b7-8229-1de3d104c00b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2953461188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.2953461188
Directory /workspace/12.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.2784945614
Short name T1849
Test name
Test status
Simulation time 216132476 ps
CPU time 1 seconds
Started Jun 28 06:10:21 PM PDT 24
Finished Jun 28 06:10:25 PM PDT 24
Peak memory 206132 kb
Host smart-c390a97a-2d33-4f83-9fea-84d77d39e9ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27849
45614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.2784945614
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.819479111
Short name T1160
Test name
Test status
Simulation time 23323885570 ps
CPU time 29.38 seconds
Started Jun 28 06:10:12 PM PDT 24
Finished Jun 28 06:10:43 PM PDT 24
Peak memory 206308 kb
Host smart-5dd70f84-3d43-4a60-89b4-7edf389f2d37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81947
9111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.819479111
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.2646971827
Short name T2155
Test name
Test status
Simulation time 3346337607 ps
CPU time 4.38 seconds
Started Jun 28 06:10:17 PM PDT 24
Finished Jun 28 06:10:25 PM PDT 24
Peak memory 206248 kb
Host smart-9eb498ba-ad3c-4f0c-aa13-dfa1049ae212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26469
71827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.2646971827
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.2532132602
Short name T2093
Test name
Test status
Simulation time 6684305970 ps
CPU time 60.82 seconds
Started Jun 28 06:10:13 PM PDT 24
Finished Jun 28 06:11:15 PM PDT 24
Peak memory 206388 kb
Host smart-7f7e7391-1134-49f1-bb2e-9a318e88ff86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25321
32602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.2532132602
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.438157304
Short name T432
Test name
Test status
Simulation time 7084976788 ps
CPU time 187.17 seconds
Started Jun 28 06:10:20 PM PDT 24
Finished Jun 28 06:13:31 PM PDT 24
Peak memory 206488 kb
Host smart-102f2c20-d50d-42fa-a421-2f2abf6fcc6b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=438157304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.438157304
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.3418653481
Short name T2488
Test name
Test status
Simulation time 273427004 ps
CPU time 0.93 seconds
Started Jun 28 06:10:15 PM PDT 24
Finished Jun 28 06:10:18 PM PDT 24
Peak memory 206216 kb
Host smart-f25f613d-5741-4f7e-9d40-eddffa311548
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3418653481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.3418653481
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.3810988568
Short name T2099
Test name
Test status
Simulation time 198845074 ps
CPU time 0.84 seconds
Started Jun 28 06:10:14 PM PDT 24
Finished Jun 28 06:10:17 PM PDT 24
Peak memory 205736 kb
Host smart-4f7872bc-5042-4b0f-abaa-5a607a7c2104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38109
88568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.3810988568
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.1873923784
Short name T858
Test name
Test status
Simulation time 6914440015 ps
CPU time 51.69 seconds
Started Jun 28 06:10:16 PM PDT 24
Finished Jun 28 06:11:10 PM PDT 24
Peak memory 206404 kb
Host smart-78fea63f-bb0e-4a27-b018-d18ca048fb5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18739
23784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.1873923784
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.1365378849
Short name T2047
Test name
Test status
Simulation time 7018445807 ps
CPU time 49.28 seconds
Started Jun 28 06:10:21 PM PDT 24
Finished Jun 28 06:11:13 PM PDT 24
Peak memory 206360 kb
Host smart-909370b7-39e6-4ad3-8b04-0021bd0eaaf8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1365378849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.1365378849
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.3383957997
Short name T454
Test name
Test status
Simulation time 162188174 ps
CPU time 0.79 seconds
Started Jun 28 06:10:21 PM PDT 24
Finished Jun 28 06:10:25 PM PDT 24
Peak memory 206156 kb
Host smart-e33f3f38-85dc-4f0a-8a09-f2cd329c8fbd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3383957997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.3383957997
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.3109881884
Short name T1599
Test name
Test status
Simulation time 150152025 ps
CPU time 0.75 seconds
Started Jun 28 06:10:21 PM PDT 24
Finished Jun 28 06:10:25 PM PDT 24
Peak memory 206072 kb
Host smart-af3bd7b6-d80f-43ac-8104-e4d52b81ff7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31098
81884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.3109881884
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.3633003866
Short name T112
Test name
Test status
Simulation time 166483074 ps
CPU time 0.79 seconds
Started Jun 28 06:10:15 PM PDT 24
Finished Jun 28 06:10:18 PM PDT 24
Peak memory 206196 kb
Host smart-e597e466-dfae-471f-9655-28031ffb9900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36330
03866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.3633003866
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.3736589
Short name T1866
Test name
Test status
Simulation time 172896664 ps
CPU time 0.76 seconds
Started Jun 28 06:10:17 PM PDT 24
Finished Jun 28 06:10:21 PM PDT 24
Peak memory 206212 kb
Host smart-b19df163-114b-4bf7-a8e7-2564265d02ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37365
89 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.3736589
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.4191665731
Short name T1662
Test name
Test status
Simulation time 186443248 ps
CPU time 0.84 seconds
Started Jun 28 06:10:15 PM PDT 24
Finished Jun 28 06:10:18 PM PDT 24
Peak memory 206192 kb
Host smart-b180c186-0c85-4b80-a324-a72c0939b114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41916
65731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.4191665731
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.1233345950
Short name T585
Test name
Test status
Simulation time 179332703 ps
CPU time 0.83 seconds
Started Jun 28 06:10:20 PM PDT 24
Finished Jun 28 06:10:24 PM PDT 24
Peak memory 206212 kb
Host smart-acf35593-ad38-42b8-9963-9a5974ab9cb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12333
45950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.1233345950
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.3309207534
Short name T965
Test name
Test status
Simulation time 187653357 ps
CPU time 0.82 seconds
Started Jun 28 06:10:20 PM PDT 24
Finished Jun 28 06:10:24 PM PDT 24
Peak memory 206200 kb
Host smart-9fc0f5a0-58d4-456d-99a3-bae3509549df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33092
07534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.3309207534
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.771727178
Short name T2230
Test name
Test status
Simulation time 202390305 ps
CPU time 0.89 seconds
Started Jun 28 06:10:21 PM PDT 24
Finished Jun 28 06:10:25 PM PDT 24
Peak memory 206176 kb
Host smart-e017fffc-7034-45f3-a549-f8661ba8cea0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=771727178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.771727178
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.3047601607
Short name T2492
Test name
Test status
Simulation time 138021724 ps
CPU time 0.79 seconds
Started Jun 28 06:10:17 PM PDT 24
Finished Jun 28 06:10:21 PM PDT 24
Peak memory 206164 kb
Host smart-e51dffde-e9a1-4211-971e-6697ae69c506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30476
01607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.3047601607
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.670930341
Short name T245
Test name
Test status
Simulation time 20657891344 ps
CPU time 45.25 seconds
Started Jun 28 06:10:16 PM PDT 24
Finished Jun 28 06:11:04 PM PDT 24
Peak memory 214700 kb
Host smart-d9baf158-a5dd-489d-93c0-80e29e29a692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67093
0341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.670930341
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.3859709167
Short name T1989
Test name
Test status
Simulation time 176727963 ps
CPU time 0.85 seconds
Started Jun 28 06:10:19 PM PDT 24
Finished Jun 28 06:10:23 PM PDT 24
Peak memory 206192 kb
Host smart-bed62261-cd2a-4329-b8ae-0e0a9b3670fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38597
09167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.3859709167
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.1410729689
Short name T721
Test name
Test status
Simulation time 200639992 ps
CPU time 0.86 seconds
Started Jun 28 06:10:18 PM PDT 24
Finished Jun 28 06:10:22 PM PDT 24
Peak memory 206208 kb
Host smart-68896769-201f-44e6-8d59-513f302244cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14107
29689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.1410729689
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.2008507457
Short name T2096
Test name
Test status
Simulation time 244736657 ps
CPU time 0.91 seconds
Started Jun 28 06:10:15 PM PDT 24
Finished Jun 28 06:10:19 PM PDT 24
Peak memory 206220 kb
Host smart-2f82229b-da17-4505-94bb-2f4468968a8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20085
07457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.2008507457
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.3845693475
Short name T1831
Test name
Test status
Simulation time 148648224 ps
CPU time 0.79 seconds
Started Jun 28 06:10:19 PM PDT 24
Finished Jun 28 06:10:23 PM PDT 24
Peak memory 206160 kb
Host smart-a458e200-f54a-40a1-8937-75072c46c83e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38456
93475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.3845693475
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.258480453
Short name T708
Test name
Test status
Simulation time 167688656 ps
CPU time 0.81 seconds
Started Jun 28 06:10:36 PM PDT 24
Finished Jun 28 06:10:39 PM PDT 24
Peak memory 206204 kb
Host smart-d390e8eb-154b-4b32-ab58-0bb41888140c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25848
0453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.258480453
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.3564212710
Short name T18
Test name
Test status
Simulation time 154976245 ps
CPU time 0.77 seconds
Started Jun 28 06:10:41 PM PDT 24
Finished Jun 28 06:10:46 PM PDT 24
Peak memory 206184 kb
Host smart-76ceaf00-3bee-417d-bb7d-d000979e86c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35642
12710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.3564212710
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.3123574146
Short name T1522
Test name
Test status
Simulation time 158531817 ps
CPU time 0.87 seconds
Started Jun 28 06:10:37 PM PDT 24
Finished Jun 28 06:10:41 PM PDT 24
Peak memory 205864 kb
Host smart-f6f1e21b-fccf-4c4e-b901-3718db5b298a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31235
74146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.3123574146
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.2620750327
Short name T676
Test name
Test status
Simulation time 220971074 ps
CPU time 0.95 seconds
Started Jun 28 06:10:37 PM PDT 24
Finished Jun 28 06:10:41 PM PDT 24
Peak memory 206216 kb
Host smart-cb3d3055-a874-4629-bf89-2f1fa91c7307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26207
50327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.2620750327
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.1824967663
Short name T1901
Test name
Test status
Simulation time 4965012520 ps
CPU time 33.55 seconds
Started Jun 28 06:10:39 PM PDT 24
Finished Jun 28 06:11:17 PM PDT 24
Peak memory 206396 kb
Host smart-f980fa01-53d6-40d4-a613-853d5ed69bb1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1824967663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.1824967663
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.4032845972
Short name T851
Test name
Test status
Simulation time 192475116 ps
CPU time 0.85 seconds
Started Jun 28 06:10:36 PM PDT 24
Finished Jun 28 06:10:39 PM PDT 24
Peak memory 206144 kb
Host smart-3ab23fcf-2283-4dea-b9ea-0f69cbecd9c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40328
45972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.4032845972
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.2435028492
Short name T2085
Test name
Test status
Simulation time 160866843 ps
CPU time 0.8 seconds
Started Jun 28 06:10:37 PM PDT 24
Finished Jun 28 06:10:42 PM PDT 24
Peak memory 206180 kb
Host smart-50e3439f-2f42-45a9-9f52-8571bfc2296c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24350
28492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.2435028492
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.2033583780
Short name T451
Test name
Test status
Simulation time 4014254296 ps
CPU time 31.84 seconds
Started Jun 28 06:10:36 PM PDT 24
Finished Jun 28 06:11:10 PM PDT 24
Peak memory 206476 kb
Host smart-fe124c4d-58dd-493b-b3a9-042ab2b1d64f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20335
83780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.2033583780
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.1781129260
Short name T2000
Test name
Test status
Simulation time 55066920 ps
CPU time 0.73 seconds
Started Jun 28 06:10:38 PM PDT 24
Finished Jun 28 06:10:42 PM PDT 24
Peak memory 206212 kb
Host smart-c3063a0a-be80-4bb8-ba1f-97d06973254c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1781129260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.1781129260
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.4074524763
Short name T2315
Test name
Test status
Simulation time 4479311786 ps
CPU time 5.67 seconds
Started Jun 28 06:10:39 PM PDT 24
Finished Jun 28 06:10:49 PM PDT 24
Peak memory 206340 kb
Host smart-d3c9d064-5295-474d-a0f6-f42f363bc548
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4074524763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.4074524763
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.1424125328
Short name T1272
Test name
Test status
Simulation time 13372823428 ps
CPU time 15.17 seconds
Started Jun 28 06:10:39 PM PDT 24
Finished Jun 28 06:10:59 PM PDT 24
Peak memory 206388 kb
Host smart-c386a0be-755a-416f-89c3-ed7fa3d22752
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1424125328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.1424125328
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.1855104530
Short name T1466
Test name
Test status
Simulation time 162111840 ps
CPU time 0.87 seconds
Started Jun 28 06:10:37 PM PDT 24
Finished Jun 28 06:10:40 PM PDT 24
Peak memory 206196 kb
Host smart-98672fad-cbd1-493a-9f32-9edf868fbea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18551
04530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.1855104530
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.2930043827
Short name T398
Test name
Test status
Simulation time 140132125 ps
CPU time 0.77 seconds
Started Jun 28 06:10:34 PM PDT 24
Finished Jun 28 06:10:36 PM PDT 24
Peak memory 206192 kb
Host smart-b5037b5d-ba5c-4105-9e1d-ee92cd5b612a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29300
43827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.2930043827
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.1368100679
Short name T1210
Test name
Test status
Simulation time 178504009 ps
CPU time 0.86 seconds
Started Jun 28 06:10:35 PM PDT 24
Finished Jun 28 06:10:37 PM PDT 24
Peak memory 206188 kb
Host smart-593a543b-9303-4581-b84a-6d2bf44cd8f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13681
00679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.1368100679
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.1521090865
Short name T1940
Test name
Test status
Simulation time 620409795 ps
CPU time 1.61 seconds
Started Jun 28 06:10:56 PM PDT 24
Finished Jun 28 06:11:04 PM PDT 24
Peak memory 206192 kb
Host smart-dd4a2965-d2e5-4a7c-a9dd-1d09ccc8da2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15210
90865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.1521090865
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.1882973666
Short name T2032
Test name
Test status
Simulation time 10700288522 ps
CPU time 21.94 seconds
Started Jun 28 06:10:37 PM PDT 24
Finished Jun 28 06:11:02 PM PDT 24
Peak memory 206500 kb
Host smart-7b1a8eb6-8bf8-4a51-af30-4256cc269c6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18829
73666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.1882973666
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.2430194794
Short name T1557
Test name
Test status
Simulation time 353847416 ps
CPU time 1.19 seconds
Started Jun 28 06:10:35 PM PDT 24
Finished Jun 28 06:10:38 PM PDT 24
Peak memory 206176 kb
Host smart-adb3fe8c-b00d-4e0e-8c12-9ac1f642b4f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24301
94794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.2430194794
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.2037957833
Short name T827
Test name
Test status
Simulation time 148553613 ps
CPU time 0.8 seconds
Started Jun 28 06:10:57 PM PDT 24
Finished Jun 28 06:11:04 PM PDT 24
Peak memory 206188 kb
Host smart-7f2050c0-77fd-447e-b4bc-09e50593947f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20379
57833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.2037957833
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.3857016163
Short name T892
Test name
Test status
Simulation time 36701578 ps
CPU time 0.74 seconds
Started Jun 28 06:10:37 PM PDT 24
Finished Jun 28 06:10:41 PM PDT 24
Peak memory 205840 kb
Host smart-ffd32da4-db94-436d-aac0-970cd9f0514d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38570
16163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.3857016163
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.4067586134
Short name T1216
Test name
Test status
Simulation time 866010354 ps
CPU time 2.04 seconds
Started Jun 28 06:10:36 PM PDT 24
Finished Jun 28 06:10:40 PM PDT 24
Peak memory 206336 kb
Host smart-c474fb37-76fa-40f3-bdaf-24e03f15fb03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40675
86134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.4067586134
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.3252759035
Short name T2583
Test name
Test status
Simulation time 307201882 ps
CPU time 1.79 seconds
Started Jun 28 06:10:41 PM PDT 24
Finished Jun 28 06:10:47 PM PDT 24
Peak memory 206316 kb
Host smart-a9979564-2bba-465f-9233-15ec447c616f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32527
59035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.3252759035
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.3669178830
Short name T1189
Test name
Test status
Simulation time 235009064 ps
CPU time 0.89 seconds
Started Jun 28 06:10:39 PM PDT 24
Finished Jun 28 06:10:45 PM PDT 24
Peak memory 206192 kb
Host smart-7f87eae3-897a-42e2-b6a1-980407d8a3b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36691
78830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.3669178830
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.1292609343
Short name T2430
Test name
Test status
Simulation time 143969184 ps
CPU time 0.79 seconds
Started Jun 28 06:10:38 PM PDT 24
Finished Jun 28 06:10:43 PM PDT 24
Peak memory 206188 kb
Host smart-49e9d73c-87b8-4b0f-a7b5-e791ec91d9a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12926
09343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.1292609343
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.4240787123
Short name T2105
Test name
Test status
Simulation time 175927760 ps
CPU time 0.84 seconds
Started Jun 28 06:10:34 PM PDT 24
Finished Jun 28 06:10:36 PM PDT 24
Peak memory 206204 kb
Host smart-86bccc40-668f-4212-8d4a-7642a7866e62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42407
87123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.4240787123
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_invalid_sync.630813481
Short name T1021
Test name
Test status
Simulation time 6057252431 ps
CPU time 44.27 seconds
Started Jun 28 06:10:36 PM PDT 24
Finished Jun 28 06:11:22 PM PDT 24
Peak memory 206384 kb
Host smart-83820ac2-449c-40ef-889d-19adc8342dd7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=630813481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.630813481
Directory /workspace/13.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.1968283500
Short name T1743
Test name
Test status
Simulation time 196765670 ps
CPU time 0.83 seconds
Started Jun 28 06:10:34 PM PDT 24
Finished Jun 28 06:10:36 PM PDT 24
Peak memory 206152 kb
Host smart-403ed8eb-84ca-4bf1-a3cb-059102d76245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19682
83500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.1968283500
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.2032694788
Short name T574
Test name
Test status
Simulation time 23304085515 ps
CPU time 25.07 seconds
Started Jun 28 06:10:35 PM PDT 24
Finished Jun 28 06:11:01 PM PDT 24
Peak memory 206312 kb
Host smart-6730ac73-0bc8-40ba-9487-f6b529fdef2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20326
94788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.2032694788
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.2997939584
Short name T816
Test name
Test status
Simulation time 3308734392 ps
CPU time 3.76 seconds
Started Jun 28 06:10:41 PM PDT 24
Finished Jun 28 06:10:49 PM PDT 24
Peak memory 206244 kb
Host smart-08351328-abfe-42ef-bf0a-e6c24f2cba23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29979
39584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.2997939584
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.2675953062
Short name T775
Test name
Test status
Simulation time 9226358303 ps
CPU time 90.95 seconds
Started Jun 28 06:10:39 PM PDT 24
Finished Jun 28 06:12:15 PM PDT 24
Peak memory 206424 kb
Host smart-63561fd5-a9ce-4c8e-8cb0-5b165cf0e439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26759
53062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.2675953062
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.3830807055
Short name T2355
Test name
Test status
Simulation time 7411352303 ps
CPU time 212.09 seconds
Started Jun 28 06:10:35 PM PDT 24
Finished Jun 28 06:14:09 PM PDT 24
Peak memory 206452 kb
Host smart-98fea7b1-182c-4f6e-8913-095ce093b398
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3830807055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.3830807055
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.2294663088
Short name T1473
Test name
Test status
Simulation time 305066668 ps
CPU time 0.94 seconds
Started Jun 28 06:10:36 PM PDT 24
Finished Jun 28 06:10:39 PM PDT 24
Peak memory 206204 kb
Host smart-13689917-7751-4f57-9663-9c354732cf3d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2294663088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.2294663088
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.3539214156
Short name T1078
Test name
Test status
Simulation time 192270030 ps
CPU time 0.94 seconds
Started Jun 28 06:10:37 PM PDT 24
Finished Jun 28 06:10:40 PM PDT 24
Peak memory 206200 kb
Host smart-2b63d4e3-cdee-4768-bd5a-8a7d42cba712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35392
14156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.3539214156
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.292263231
Short name T2506
Test name
Test status
Simulation time 5278772249 ps
CPU time 37.59 seconds
Started Jun 28 06:10:41 PM PDT 24
Finished Jun 28 06:11:23 PM PDT 24
Peak memory 206464 kb
Host smart-e0b7766a-c079-4951-9308-971b5ee474f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29226
3231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.292263231
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.2307701783
Short name T2568
Test name
Test status
Simulation time 6577723604 ps
CPU time 59.43 seconds
Started Jun 28 06:10:37 PM PDT 24
Finished Jun 28 06:11:40 PM PDT 24
Peak memory 206452 kb
Host smart-346d5150-e3a2-4ef4-9725-68b14e0ead88
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2307701783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.2307701783
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.4142074354
Short name T1676
Test name
Test status
Simulation time 234683546 ps
CPU time 0.88 seconds
Started Jun 28 06:10:38 PM PDT 24
Finished Jun 28 06:10:42 PM PDT 24
Peak memory 206196 kb
Host smart-08b97977-21cd-4e12-bd77-2383b08138e2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4142074354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.4142074354
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.3036958513
Short name T1339
Test name
Test status
Simulation time 138371864 ps
CPU time 0.78 seconds
Started Jun 28 06:10:37 PM PDT 24
Finished Jun 28 06:10:40 PM PDT 24
Peak memory 206188 kb
Host smart-e8efe3dd-71b4-43ab-a14d-d6d1c65c8f4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30369
58513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.3036958513
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.1348398519
Short name T2483
Test name
Test status
Simulation time 200719431 ps
CPU time 0.83 seconds
Started Jun 28 06:10:39 PM PDT 24
Finished Jun 28 06:10:44 PM PDT 24
Peak memory 206196 kb
Host smart-dade1710-c1b2-46fe-8bfe-8095e0d215f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13483
98519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.1348398519
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.2114611355
Short name T2627
Test name
Test status
Simulation time 184349233 ps
CPU time 0.79 seconds
Started Jun 28 06:10:37 PM PDT 24
Finished Jun 28 06:10:42 PM PDT 24
Peak memory 206196 kb
Host smart-dfb39a42-15cb-480a-bdbb-298e5cd342c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21146
11355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.2114611355
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.2189047537
Short name T688
Test name
Test status
Simulation time 151971116 ps
CPU time 0.76 seconds
Started Jun 28 06:10:41 PM PDT 24
Finished Jun 28 06:10:46 PM PDT 24
Peak memory 206176 kb
Host smart-f9779902-2cb0-414b-973c-19b2065a6d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21890
47537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.2189047537
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.1007511259
Short name T1004
Test name
Test status
Simulation time 152824953 ps
CPU time 0.83 seconds
Started Jun 28 06:10:37 PM PDT 24
Finished Jun 28 06:10:42 PM PDT 24
Peak memory 206164 kb
Host smart-2d35ac82-dbef-48e8-8089-1341d42ce4e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10075
11259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.1007511259
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.3399199835
Short name T29
Test name
Test status
Simulation time 201990569 ps
CPU time 0.91 seconds
Started Jun 28 06:10:37 PM PDT 24
Finished Jun 28 06:10:42 PM PDT 24
Peak memory 206212 kb
Host smart-fc7233a8-0bf8-4b43-a450-ee20c62472ff
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3399199835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.3399199835
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.157964588
Short name T832
Test name
Test status
Simulation time 159320067 ps
CPU time 0.85 seconds
Started Jun 28 06:10:35 PM PDT 24
Finished Jun 28 06:10:36 PM PDT 24
Peak memory 206184 kb
Host smart-96ecf70c-1cb3-494a-b246-e5f1261204be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15796
4588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.157964588
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.1227014114
Short name T1618
Test name
Test status
Simulation time 163724457 ps
CPU time 0.88 seconds
Started Jun 28 06:10:36 PM PDT 24
Finished Jun 28 06:10:38 PM PDT 24
Peak memory 206164 kb
Host smart-14819977-bbca-450e-a3f2-df0ed7c3fa76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12270
14114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.1227014114
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.3487894950
Short name T988
Test name
Test status
Simulation time 237106524 ps
CPU time 0.91 seconds
Started Jun 28 06:10:37 PM PDT 24
Finished Jun 28 06:10:41 PM PDT 24
Peak memory 206212 kb
Host smart-69d4427a-d84d-4ca8-94d1-88541fc7bbcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34878
94950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.3487894950
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.2817855997
Short name T1425
Test name
Test status
Simulation time 229009640 ps
CPU time 0.88 seconds
Started Jun 28 06:10:36 PM PDT 24
Finished Jun 28 06:10:38 PM PDT 24
Peak memory 206220 kb
Host smart-f3ae0785-95cb-4032-ab99-33524a03231b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28178
55997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.2817855997
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.985910715
Short name T928
Test name
Test status
Simulation time 223959019 ps
CPU time 0.91 seconds
Started Jun 28 06:10:39 PM PDT 24
Finished Jun 28 06:10:45 PM PDT 24
Peak memory 206196 kb
Host smart-829b7c09-2100-47fd-8fd9-259e5e846fb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98591
0715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.985910715
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.1098810412
Short name T1699
Test name
Test status
Simulation time 137895797 ps
CPU time 0.77 seconds
Started Jun 28 06:10:37 PM PDT 24
Finished Jun 28 06:10:40 PM PDT 24
Peak memory 206176 kb
Host smart-ad239cdd-e78b-4104-b118-d1869e0ebb46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10988
10412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.1098810412
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.1435904238
Short name T1963
Test name
Test status
Simulation time 197624416 ps
CPU time 0.79 seconds
Started Jun 28 06:10:38 PM PDT 24
Finished Jun 28 06:10:42 PM PDT 24
Peak memory 206184 kb
Host smart-75acd257-f88b-4481-8c26-194c7544ac7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14359
04238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.1435904238
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.958217915
Short name T1292
Test name
Test status
Simulation time 157998688 ps
CPU time 0.77 seconds
Started Jun 28 06:10:36 PM PDT 24
Finished Jun 28 06:10:39 PM PDT 24
Peak memory 206196 kb
Host smart-1fdbfed1-434b-47e6-b8fe-23451eda518a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95821
7915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.958217915
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.4166581166
Short name T590
Test name
Test status
Simulation time 223759759 ps
CPU time 1.04 seconds
Started Jun 28 06:10:38 PM PDT 24
Finished Jun 28 06:10:43 PM PDT 24
Peak memory 206208 kb
Host smart-64c181ac-51fe-4f06-ab2d-dc1d6d2efb8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41665
81166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.4166581166
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.844541126
Short name T1793
Test name
Test status
Simulation time 3090460891 ps
CPU time 22.2 seconds
Started Jun 28 06:10:39 PM PDT 24
Finished Jun 28 06:11:05 PM PDT 24
Peak memory 206456 kb
Host smart-0f1c6999-a0d4-46e3-9ab9-de534b9c0dc1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=844541126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.844541126
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.3622881845
Short name T725
Test name
Test status
Simulation time 192883200 ps
CPU time 0.86 seconds
Started Jun 28 06:10:37 PM PDT 24
Finished Jun 28 06:10:40 PM PDT 24
Peak memory 206224 kb
Host smart-f4a46db4-a79e-4619-9878-2378cd475889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36228
81845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.3622881845
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.1897574801
Short name T1342
Test name
Test status
Simulation time 160426145 ps
CPU time 0.84 seconds
Started Jun 28 06:10:38 PM PDT 24
Finished Jun 28 06:10:43 PM PDT 24
Peak memory 206152 kb
Host smart-42a1984f-3833-4aad-aed9-211a4f5f91a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18975
74801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.1897574801
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.3615153038
Short name T1139
Test name
Test status
Simulation time 4842976269 ps
CPU time 42.4 seconds
Started Jun 28 06:10:37 PM PDT 24
Finished Jun 28 06:11:23 PM PDT 24
Peak memory 206472 kb
Host smart-e351adf3-fe92-4e81-897e-9024a5291d8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36151
53038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.3615153038
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.2552300606
Short name T1637
Test name
Test status
Simulation time 42605100 ps
CPU time 0.66 seconds
Started Jun 28 06:10:51 PM PDT 24
Finished Jun 28 06:10:57 PM PDT 24
Peak memory 206180 kb
Host smart-fc6f6364-3f6e-4431-bb4a-449d534ea334
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2552300606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.2552300606
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.3338472446
Short name T1183
Test name
Test status
Simulation time 4065126936 ps
CPU time 4.59 seconds
Started Jun 28 06:10:39 PM PDT 24
Finished Jun 28 06:10:48 PM PDT 24
Peak memory 206272 kb
Host smart-7ab4c6fd-28e0-4db5-ae6c-5a680be6fd7e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3338472446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.3338472446
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.2258448018
Short name T2285
Test name
Test status
Simulation time 13469173487 ps
CPU time 12.83 seconds
Started Jun 28 06:10:38 PM PDT 24
Finished Jun 28 06:10:55 PM PDT 24
Peak memory 206300 kb
Host smart-4a6e632d-b9e8-410c-91c2-ef2381a8bb9a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2258448018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.2258448018
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.2617097237
Short name T2382
Test name
Test status
Simulation time 23382984370 ps
CPU time 25.22 seconds
Started Jun 28 06:10:39 PM PDT 24
Finished Jun 28 06:11:08 PM PDT 24
Peak memory 206396 kb
Host smart-ce708a56-c592-4e47-bd99-9b9ae0f396c1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2617097237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.2617097237
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.1280076635
Short name T889
Test name
Test status
Simulation time 205104406 ps
CPU time 0.91 seconds
Started Jun 28 06:10:57 PM PDT 24
Finished Jun 28 06:11:04 PM PDT 24
Peak memory 206192 kb
Host smart-e6fc52f8-198a-4062-9e6a-6daec0d18773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12800
76635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.1280076635
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.2679955481
Short name T427
Test name
Test status
Simulation time 142277072 ps
CPU time 0.76 seconds
Started Jun 28 06:10:38 PM PDT 24
Finished Jun 28 06:10:43 PM PDT 24
Peak memory 206196 kb
Host smart-90dbd061-eda2-4f24-9724-b9a889c54511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26799
55481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.2679955481
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.3971099823
Short name T164
Test name
Test status
Simulation time 547465064 ps
CPU time 1.58 seconds
Started Jun 28 06:10:38 PM PDT 24
Finished Jun 28 06:10:43 PM PDT 24
Peak memory 206292 kb
Host smart-18c00bbc-8549-4c29-b196-76cfb15489c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39710
99823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.3971099823
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.3259040299
Short name T1426
Test name
Test status
Simulation time 1033058263 ps
CPU time 2.25 seconds
Started Jun 28 06:10:40 PM PDT 24
Finished Jun 28 06:10:46 PM PDT 24
Peak memory 206324 kb
Host smart-0600cb16-9303-4d3f-ae29-2f617abebc5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32590
40299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.3259040299
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.3905995664
Short name T1952
Test name
Test status
Simulation time 21238592637 ps
CPU time 41.04 seconds
Started Jun 28 06:10:38 PM PDT 24
Finished Jun 28 06:11:23 PM PDT 24
Peak memory 206496 kb
Host smart-9d3004a4-3366-4d28-a0b0-4ce1bfe05add
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39059
95664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.3905995664
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.2560840455
Short name T2189
Test name
Test status
Simulation time 457193925 ps
CPU time 1.36 seconds
Started Jun 28 06:10:39 PM PDT 24
Finished Jun 28 06:10:44 PM PDT 24
Peak memory 206200 kb
Host smart-8cbbb1bc-75e5-47bf-af33-795e0ac28551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25608
40455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.2560840455
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_enable.3774239371
Short name T1526
Test name
Test status
Simulation time 36505035 ps
CPU time 0.64 seconds
Started Jun 28 06:10:39 PM PDT 24
Finished Jun 28 06:10:44 PM PDT 24
Peak memory 206148 kb
Host smart-10b641a9-7dc7-4087-af96-6f5a8815fc19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37742
39371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.3774239371
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.4013384873
Short name T2127
Test name
Test status
Simulation time 987299806 ps
CPU time 2.21 seconds
Started Jun 28 06:10:39 PM PDT 24
Finished Jun 28 06:10:46 PM PDT 24
Peak memory 206276 kb
Host smart-dc9c7a43-5e3d-40fd-9a1d-fc573f611b1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40133
84873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.4013384873
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.3768827177
Short name T2044
Test name
Test status
Simulation time 307275867 ps
CPU time 1.77 seconds
Started Jun 28 06:10:39 PM PDT 24
Finished Jun 28 06:10:45 PM PDT 24
Peak memory 206368 kb
Host smart-6e0d0f20-a399-4290-898b-85738a7fbac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37688
27177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.3768827177
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.1248478945
Short name T1187
Test name
Test status
Simulation time 232650670 ps
CPU time 0.95 seconds
Started Jun 28 06:10:39 PM PDT 24
Finished Jun 28 06:10:44 PM PDT 24
Peak memory 206152 kb
Host smart-905dc856-b0ee-450c-afe8-126df8c1ae3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12484
78945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.1248478945
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.1668433637
Short name T957
Test name
Test status
Simulation time 212640423 ps
CPU time 0.79 seconds
Started Jun 28 06:10:39 PM PDT 24
Finished Jun 28 06:10:44 PM PDT 24
Peak memory 206196 kb
Host smart-e22c48b0-f960-463f-ae1a-0e02cbc374d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16684
33637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.1668433637
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.581862073
Short name T1495
Test name
Test status
Simulation time 213954108 ps
CPU time 0.92 seconds
Started Jun 28 06:10:39 PM PDT 24
Finished Jun 28 06:10:44 PM PDT 24
Peak memory 206192 kb
Host smart-7be28a35-8073-409c-bc8c-3612382ec736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58186
2073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.581862073
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_invalid_sync.1396958857
Short name T2035
Test name
Test status
Simulation time 7072608249 ps
CPU time 201.37 seconds
Started Jun 28 06:10:39 PM PDT 24
Finished Jun 28 06:14:05 PM PDT 24
Peak memory 206508 kb
Host smart-577ce49c-2bb9-45ef-9e20-5a387de69858
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1396958857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.1396958857
Directory /workspace/14.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.4140900289
Short name T1413
Test name
Test status
Simulation time 265203834 ps
CPU time 1.01 seconds
Started Jun 28 06:10:38 PM PDT 24
Finished Jun 28 06:10:44 PM PDT 24
Peak memory 206192 kb
Host smart-9200ba84-5dae-47c6-ae0d-477d18faa457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41409
00289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.4140900289
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.2466636081
Short name T637
Test name
Test status
Simulation time 23311227591 ps
CPU time 21.58 seconds
Started Jun 28 06:10:40 PM PDT 24
Finished Jun 28 06:11:06 PM PDT 24
Peak memory 206280 kb
Host smart-76d58bd2-907a-47b9-95ec-184c20aa7663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24666
36081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.2466636081
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.1804107399
Short name T1284
Test name
Test status
Simulation time 3338542989 ps
CPU time 3.72 seconds
Started Jun 28 06:10:40 PM PDT 24
Finished Jun 28 06:10:48 PM PDT 24
Peak memory 206220 kb
Host smart-fbc9a898-41cf-4cac-bccf-9854927b26b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18041
07399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.1804107399
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.2620066230
Short name T2300
Test name
Test status
Simulation time 10173462863 ps
CPU time 68.11 seconds
Started Jun 28 06:10:39 PM PDT 24
Finished Jun 28 06:11:52 PM PDT 24
Peak memory 206400 kb
Host smart-d85a4fff-3b23-416d-9639-aa3d43500e5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26200
66230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.2620066230
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.54588218
Short name T1550
Test name
Test status
Simulation time 3935872679 ps
CPU time 38.49 seconds
Started Jun 28 06:10:51 PM PDT 24
Finished Jun 28 06:11:35 PM PDT 24
Peak memory 206548 kb
Host smart-af816160-0fb5-46e4-96b2-469aa42e1497
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=54588218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.54588218
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.2777028314
Short name T810
Test name
Test status
Simulation time 247468896 ps
CPU time 0.93 seconds
Started Jun 28 06:10:49 PM PDT 24
Finished Jun 28 06:10:51 PM PDT 24
Peak memory 206216 kb
Host smart-40a53f90-4aed-4a7a-804c-78dde0bee014
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2777028314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.2777028314
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.2704310388
Short name T1867
Test name
Test status
Simulation time 222965002 ps
CPU time 0.9 seconds
Started Jun 28 06:10:50 PM PDT 24
Finished Jun 28 06:10:55 PM PDT 24
Peak memory 206196 kb
Host smart-50d694cb-b2e8-43d0-8306-bfbcaa880015
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27043
10388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.2704310388
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.4038665970
Short name T2599
Test name
Test status
Simulation time 6052416754 ps
CPU time 43.94 seconds
Started Jun 28 06:10:50 PM PDT 24
Finished Jun 28 06:11:37 PM PDT 24
Peak memory 206500 kb
Host smart-1247f952-c57a-4dd8-9fba-dc0993b006c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40386
65970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.4038665970
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.2748770049
Short name T2125
Test name
Test status
Simulation time 3565905295 ps
CPU time 99.62 seconds
Started Jun 28 06:10:50 PM PDT 24
Finished Jun 28 06:12:34 PM PDT 24
Peak memory 206456 kb
Host smart-ee388e1c-c2ec-4fb2-b69c-5c7ac0cb6abd
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2748770049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.2748770049
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.977311738
Short name T336
Test name
Test status
Simulation time 178820385 ps
CPU time 0.82 seconds
Started Jun 28 06:10:50 PM PDT 24
Finished Jun 28 06:10:55 PM PDT 24
Peak memory 206140 kb
Host smart-d3c31daa-4353-43e0-99cf-577f6a8072f3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=977311738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.977311738
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.403464975
Short name T2572
Test name
Test status
Simulation time 142293257 ps
CPU time 0.79 seconds
Started Jun 28 06:10:51 PM PDT 24
Finished Jun 28 06:10:56 PM PDT 24
Peak memory 206212 kb
Host smart-3f4ba82e-a4b0-41ae-8b36-07c4a3e9eda0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40346
4975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.403464975
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.3230089591
Short name T2441
Test name
Test status
Simulation time 261315633 ps
CPU time 0.89 seconds
Started Jun 28 06:10:49 PM PDT 24
Finished Jun 28 06:10:52 PM PDT 24
Peak memory 206180 kb
Host smart-f56054b7-dd56-4726-ba10-5b897b0d60b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32300
89591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.3230089591
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.1461913022
Short name T1079
Test name
Test status
Simulation time 186708798 ps
CPU time 0.87 seconds
Started Jun 28 06:10:50 PM PDT 24
Finished Jun 28 06:10:53 PM PDT 24
Peak memory 206152 kb
Host smart-de59c7d6-8989-4174-abf8-634f2f08a8c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14619
13022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.1461913022
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.2909594298
Short name T318
Test name
Test status
Simulation time 160936421 ps
CPU time 0.82 seconds
Started Jun 28 06:10:49 PM PDT 24
Finished Jun 28 06:10:52 PM PDT 24
Peak memory 206196 kb
Host smart-af9a065d-a6e4-44f8-b986-7ca32e650e00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29095
94298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.2909594298
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.2626222114
Short name T2552
Test name
Test status
Simulation time 239011359 ps
CPU time 0.95 seconds
Started Jun 28 06:10:50 PM PDT 24
Finished Jun 28 06:10:55 PM PDT 24
Peak memory 206200 kb
Host smart-66190b69-248a-4e97-aa47-e8fb0673116c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26262
22114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.2626222114
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.760611488
Short name T2255
Test name
Test status
Simulation time 145838838 ps
CPU time 0.81 seconds
Started Jun 28 06:10:52 PM PDT 24
Finished Jun 28 06:10:59 PM PDT 24
Peak memory 206216 kb
Host smart-3362c2a8-46b7-4925-9dc4-4a3a3b8f6df3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76061
1488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.760611488
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.492337629
Short name T556
Test name
Test status
Simulation time 241162866 ps
CPU time 0.92 seconds
Started Jun 28 06:10:52 PM PDT 24
Finished Jun 28 06:10:59 PM PDT 24
Peak memory 206212 kb
Host smart-94265619-e6c9-4a42-8e6b-21f7717b984f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=492337629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.492337629
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.3972108424
Short name T2048
Test name
Test status
Simulation time 142722850 ps
CPU time 0.81 seconds
Started Jun 28 06:10:49 PM PDT 24
Finished Jun 28 06:10:52 PM PDT 24
Peak memory 206196 kb
Host smart-e0ebcd84-73d0-4f36-b4e5-5984f8181c65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39721
08424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.3972108424
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.3455597219
Short name T540
Test name
Test status
Simulation time 58014992 ps
CPU time 0.69 seconds
Started Jun 28 06:10:50 PM PDT 24
Finished Jun 28 06:10:55 PM PDT 24
Peak memory 206204 kb
Host smart-0d8737a9-9f8c-4565-aa9d-a7726dc6c505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34555
97219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.3455597219
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.2094120266
Short name T2602
Test name
Test status
Simulation time 13020638511 ps
CPU time 31 seconds
Started Jun 28 06:10:56 PM PDT 24
Finished Jun 28 06:11:33 PM PDT 24
Peak memory 206428 kb
Host smart-6ea7c6bb-c4bf-4a2c-b4de-60929c1baaf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20941
20266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.2094120266
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.3095711106
Short name T2523
Test name
Test status
Simulation time 184074713 ps
CPU time 0.87 seconds
Started Jun 28 06:10:50 PM PDT 24
Finished Jun 28 06:10:54 PM PDT 24
Peak memory 206196 kb
Host smart-28de7816-7492-4794-9c94-6c2ad1266ca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30957
11106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.3095711106
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.4217206038
Short name T1816
Test name
Test status
Simulation time 226827816 ps
CPU time 0.93 seconds
Started Jun 28 06:10:51 PM PDT 24
Finished Jun 28 06:10:56 PM PDT 24
Peak memory 206136 kb
Host smart-241373d0-c637-40cf-bbcb-96904205bc99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42172
06038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.4217206038
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.497436036
Short name T1254
Test name
Test status
Simulation time 171224843 ps
CPU time 0.84 seconds
Started Jun 28 06:10:49 PM PDT 24
Finished Jun 28 06:10:51 PM PDT 24
Peak memory 206212 kb
Host smart-c481fe47-beeb-41f9-a057-33450bf23b8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49743
6036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.497436036
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.3932667841
Short name T808
Test name
Test status
Simulation time 177343222 ps
CPU time 0.9 seconds
Started Jun 28 06:10:49 PM PDT 24
Finished Jun 28 06:10:51 PM PDT 24
Peak memory 206200 kb
Host smart-80f99ad5-30bc-4d5c-bbeb-f2651dc67c28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39326
67841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.3932667841
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.298615434
Short name T1841
Test name
Test status
Simulation time 145984218 ps
CPU time 0.76 seconds
Started Jun 28 06:10:51 PM PDT 24
Finished Jun 28 06:10:56 PM PDT 24
Peak memory 206324 kb
Host smart-c32210b9-89d1-48e3-97c7-e7c209a6f0d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29861
5434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.298615434
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.3960256555
Short name T580
Test name
Test status
Simulation time 190881315 ps
CPU time 0.84 seconds
Started Jun 28 06:10:54 PM PDT 24
Finished Jun 28 06:11:01 PM PDT 24
Peak memory 206172 kb
Host smart-ada54b19-70bd-49d6-a411-2120f1bf0a0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39602
56555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.3960256555
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.1947434538
Short name T2589
Test name
Test status
Simulation time 153301341 ps
CPU time 0.82 seconds
Started Jun 28 06:10:50 PM PDT 24
Finished Jun 28 06:10:55 PM PDT 24
Peak memory 206192 kb
Host smart-3bb31cc0-4fb4-47ac-9dc0-6127b1c3481f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19474
34538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.1947434538
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.2310575563
Short name T1350
Test name
Test status
Simulation time 198203229 ps
CPU time 0.89 seconds
Started Jun 28 06:10:51 PM PDT 24
Finished Jun 28 06:10:56 PM PDT 24
Peak memory 206212 kb
Host smart-54f9dfe2-8999-48f1-adb0-4c2147a69c60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23105
75563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.2310575563
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.423463516
Short name T1028
Test name
Test status
Simulation time 6202915396 ps
CPU time 45.1 seconds
Started Jun 28 06:10:51 PM PDT 24
Finished Jun 28 06:11:41 PM PDT 24
Peak memory 206380 kb
Host smart-7d10afe0-b7cf-4752-8d2f-b28c87acac02
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=423463516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.423463516
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.3925981254
Short name T2188
Test name
Test status
Simulation time 163981642 ps
CPU time 0.87 seconds
Started Jun 28 06:10:50 PM PDT 24
Finished Jun 28 06:10:55 PM PDT 24
Peak memory 206224 kb
Host smart-022ce516-e031-4498-b1dc-6970c04b8995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39259
81254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.3925981254
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.4269254274
Short name T1010
Test name
Test status
Simulation time 183087409 ps
CPU time 0.86 seconds
Started Jun 28 06:10:55 PM PDT 24
Finished Jun 28 06:11:03 PM PDT 24
Peak memory 206196 kb
Host smart-527b337c-05ce-45ea-ae10-2883b629cf9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42692
54274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.4269254274
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.1010676123
Short name T384
Test name
Test status
Simulation time 4518988313 ps
CPU time 34.8 seconds
Started Jun 28 06:10:52 PM PDT 24
Finished Jun 28 06:11:32 PM PDT 24
Peak memory 206440 kb
Host smart-83a22b42-6600-4b1d-a793-2b9e7848453c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10106
76123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.1010676123
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.2630544078
Short name T738
Test name
Test status
Simulation time 45878679 ps
CPU time 0.69 seconds
Started Jun 28 06:11:00 PM PDT 24
Finished Jun 28 06:11:06 PM PDT 24
Peak memory 206184 kb
Host smart-74c74922-3f24-448d-86e7-cd20e84f8934
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2630544078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.2630544078
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.1434304115
Short name T1119
Test name
Test status
Simulation time 4444662873 ps
CPU time 5.03 seconds
Started Jun 28 06:10:49 PM PDT 24
Finished Jun 28 06:10:55 PM PDT 24
Peak memory 206424 kb
Host smart-0917acef-acc5-4e10-82b5-a609b10c40e9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1434304115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.1434304115
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.574986625
Short name T715
Test name
Test status
Simulation time 13460729778 ps
CPU time 13.28 seconds
Started Jun 28 06:10:50 PM PDT 24
Finished Jun 28 06:11:07 PM PDT 24
Peak memory 206460 kb
Host smart-7a39c28a-e248-43a8-b108-ae5bb09b4a6d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=574986625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.574986625
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.3280465767
Short name T2611
Test name
Test status
Simulation time 23480940082 ps
CPU time 24.73 seconds
Started Jun 28 06:10:51 PM PDT 24
Finished Jun 28 06:11:21 PM PDT 24
Peak memory 206500 kb
Host smart-9699e711-49b7-46f8-9a53-212518f51b1f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3280465767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.3280465767
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.2475373085
Short name T1427
Test name
Test status
Simulation time 171290128 ps
CPU time 0.86 seconds
Started Jun 28 06:10:56 PM PDT 24
Finished Jun 28 06:11:04 PM PDT 24
Peak memory 206196 kb
Host smart-85b30656-2862-43a6-8ff6-54c7cf43c1de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24753
73085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.2475373085
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.1658578314
Short name T56
Test name
Test status
Simulation time 172184380 ps
CPU time 0.81 seconds
Started Jun 28 06:10:50 PM PDT 24
Finished Jun 28 06:10:54 PM PDT 24
Peak memory 206200 kb
Host smart-68e445c3-2b49-4d9a-b546-59a309ca9d9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16585
78314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.1658578314
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.3033020089
Short name T2567
Test name
Test status
Simulation time 447439191 ps
CPU time 1.4 seconds
Started Jun 28 06:10:50 PM PDT 24
Finished Jun 28 06:10:54 PM PDT 24
Peak memory 206192 kb
Host smart-e58b6245-ca21-42ed-91df-7b61997a6d74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30330
20089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.3033020089
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.2565941345
Short name T2185
Test name
Test status
Simulation time 386224484 ps
CPU time 1.09 seconds
Started Jun 28 06:10:49 PM PDT 24
Finished Jun 28 06:10:52 PM PDT 24
Peak memory 206188 kb
Host smart-5f4d3ff6-cfac-4e33-82c4-bbaec7c7a9b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25659
41345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.2565941345
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.3299477997
Short name T1379
Test name
Test status
Simulation time 10470175242 ps
CPU time 20.33 seconds
Started Jun 28 06:10:51 PM PDT 24
Finished Jun 28 06:11:17 PM PDT 24
Peak memory 206412 kb
Host smart-e7591b57-4bc4-4e98-80de-2f23011fbd4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32994
77997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.3299477997
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.3034740943
Short name T1000
Test name
Test status
Simulation time 334819175 ps
CPU time 1.12 seconds
Started Jun 28 06:10:51 PM PDT 24
Finished Jun 28 06:10:58 PM PDT 24
Peak memory 206124 kb
Host smart-a1eeb39f-4a3e-4a79-baac-11347baf3994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30347
40943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.3034740943
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.3399560870
Short name T344
Test name
Test status
Simulation time 195665369 ps
CPU time 0.87 seconds
Started Jun 28 06:10:53 PM PDT 24
Finished Jun 28 06:11:00 PM PDT 24
Peak memory 206196 kb
Host smart-4a82e89b-73eb-4544-82e1-d35973789df2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33995
60870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.3399560870
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.857391691
Short name T2276
Test name
Test status
Simulation time 65588657 ps
CPU time 0.7 seconds
Started Jun 28 06:10:53 PM PDT 24
Finished Jun 28 06:10:59 PM PDT 24
Peak memory 206208 kb
Host smart-6bd5e8a0-cbfd-4f62-8591-481477a6d935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85739
1691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.857391691
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.3739413022
Short name T751
Test name
Test status
Simulation time 944183677 ps
CPU time 2.27 seconds
Started Jun 28 06:10:51 PM PDT 24
Finished Jun 28 06:10:57 PM PDT 24
Peak memory 206164 kb
Host smart-0414fe7b-0d33-4c6f-ab5a-9dea2671de9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37394
13022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.3739413022
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.2466222226
Short name T416
Test name
Test status
Simulation time 274295339 ps
CPU time 1.59 seconds
Started Jun 28 06:10:50 PM PDT 24
Finished Jun 28 06:10:56 PM PDT 24
Peak memory 206332 kb
Host smart-9e8356d3-98cc-4bc9-a582-f499b6dac83c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24662
22226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.2466222226
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.73133542
Short name T2480
Test name
Test status
Simulation time 165878822 ps
CPU time 0.8 seconds
Started Jun 28 06:10:48 PM PDT 24
Finished Jun 28 06:10:51 PM PDT 24
Peak memory 206212 kb
Host smart-29150c62-dea0-4724-8540-be29f5311453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73133
542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.73133542
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.3804265434
Short name T105
Test name
Test status
Simulation time 156696236 ps
CPU time 0.82 seconds
Started Jun 28 06:10:57 PM PDT 24
Finished Jun 28 06:11:04 PM PDT 24
Peak memory 206188 kb
Host smart-c58cf580-57f2-4b74-8eee-9a98e354094d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38042
65434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.3804265434
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.1844399558
Short name T1512
Test name
Test status
Simulation time 235976825 ps
CPU time 0.98 seconds
Started Jun 28 06:10:51 PM PDT 24
Finished Jun 28 06:10:57 PM PDT 24
Peak memory 206200 kb
Host smart-f4b8da67-aa64-4847-a4d5-2affbf5d63c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18443
99558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.1844399558
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.2582999410
Short name T1432
Test name
Test status
Simulation time 5937644746 ps
CPU time 40.93 seconds
Started Jun 28 06:10:51 PM PDT 24
Finished Jun 28 06:11:36 PM PDT 24
Peak memory 205636 kb
Host smart-b0d85ce1-ed5a-499c-b427-c2abb4dde805
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2582999410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.2582999410
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.4185869793
Short name T53
Test name
Test status
Simulation time 273249674 ps
CPU time 0.99 seconds
Started Jun 28 06:10:48 PM PDT 24
Finished Jun 28 06:10:51 PM PDT 24
Peak memory 206188 kb
Host smart-c02ecf5f-3169-444f-939b-58a0c39cf8d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41858
69793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.4185869793
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.1071262351
Short name T1220
Test name
Test status
Simulation time 23306891822 ps
CPU time 26.84 seconds
Started Jun 28 06:10:53 PM PDT 24
Finished Jun 28 06:11:26 PM PDT 24
Peak memory 206316 kb
Host smart-8847aa82-b81f-4481-86c5-269c36f242dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10712
62351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.1071262351
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.2907020144
Short name T530
Test name
Test status
Simulation time 3265834029 ps
CPU time 4.1 seconds
Started Jun 28 06:10:48 PM PDT 24
Finished Jun 28 06:10:54 PM PDT 24
Peak memory 206248 kb
Host smart-a560c8e0-7650-4c01-bf75-0bf150fe068b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29070
20144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.2907020144
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.2075408425
Short name T2104
Test name
Test status
Simulation time 11468780939 ps
CPU time 323.56 seconds
Started Jun 28 06:10:56 PM PDT 24
Finished Jun 28 06:16:26 PM PDT 24
Peak memory 206472 kb
Host smart-54cf399c-49a8-4c73-8f87-9424df787414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20754
08425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.2075408425
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.2844307336
Short name T1532
Test name
Test status
Simulation time 3306022899 ps
CPU time 23.56 seconds
Started Jun 28 06:10:51 PM PDT 24
Finished Jun 28 06:11:19 PM PDT 24
Peak memory 205844 kb
Host smart-7b4e8970-de32-4da2-b97b-16d97cacf8e7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2844307336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.2844307336
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.61879833
Short name T2385
Test name
Test status
Simulation time 244262706 ps
CPU time 0.96 seconds
Started Jun 28 06:10:54 PM PDT 24
Finished Jun 28 06:11:01 PM PDT 24
Peak memory 206192 kb
Host smart-f0296277-e7e3-42c1-bc30-de9896936ce5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=61879833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.61879833
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.2231220051
Short name T542
Test name
Test status
Simulation time 199894960 ps
CPU time 0.94 seconds
Started Jun 28 06:10:57 PM PDT 24
Finished Jun 28 06:11:04 PM PDT 24
Peak memory 206176 kb
Host smart-e3e80bdc-42e8-4e31-88f0-702ea66c6258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22312
20051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.2231220051
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.1052958686
Short name T689
Test name
Test status
Simulation time 4593723011 ps
CPU time 34.84 seconds
Started Jun 28 06:10:54 PM PDT 24
Finished Jun 28 06:11:35 PM PDT 24
Peak memory 206432 kb
Host smart-f9b225e5-aab9-4511-840b-7b3146319eda
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1052958686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.1052958686
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.2046077117
Short name T26
Test name
Test status
Simulation time 192683493 ps
CPU time 0.82 seconds
Started Jun 28 06:10:54 PM PDT 24
Finished Jun 28 06:11:01 PM PDT 24
Peak memory 206216 kb
Host smart-ff943b3c-f782-49bc-82d5-a59ca395563c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2046077117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.2046077117
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.4128569886
Short name T672
Test name
Test status
Simulation time 200219731 ps
CPU time 0.87 seconds
Started Jun 28 06:10:57 PM PDT 24
Finished Jun 28 06:11:04 PM PDT 24
Peak memory 206212 kb
Host smart-040de037-09b5-4f0b-be68-1e6f184f3d26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41285
69886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.4128569886
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.2722744111
Short name T743
Test name
Test status
Simulation time 183162161 ps
CPU time 0.81 seconds
Started Jun 28 06:10:52 PM PDT 24
Finished Jun 28 06:10:59 PM PDT 24
Peak memory 206168 kb
Host smart-86a5cf2e-652c-40cf-8263-960c0b7f6f75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27227
44111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.2722744111
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.2266270056
Short name T1643
Test name
Test status
Simulation time 158363579 ps
CPU time 0.76 seconds
Started Jun 28 06:10:54 PM PDT 24
Finished Jun 28 06:11:01 PM PDT 24
Peak memory 206132 kb
Host smart-44fb6e4f-b5c4-4d6e-a748-f377019fa7d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22662
70056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.2266270056
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.2122111875
Short name T1109
Test name
Test status
Simulation time 191197302 ps
CPU time 0.87 seconds
Started Jun 28 06:10:56 PM PDT 24
Finished Jun 28 06:11:04 PM PDT 24
Peak memory 206216 kb
Host smart-ca7944f6-ed77-4ded-91d3-c31067c05999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21221
11875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.2122111875
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.4102912490
Short name T182
Test name
Test status
Simulation time 186568254 ps
CPU time 0.83 seconds
Started Jun 28 06:10:49 PM PDT 24
Finished Jun 28 06:10:52 PM PDT 24
Peak memory 206200 kb
Host smart-097de51c-f85b-487f-8dc4-8f19d9fdcafe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41029
12490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.4102912490
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.3136817229
Short name T2243
Test name
Test status
Simulation time 196317242 ps
CPU time 0.93 seconds
Started Jun 28 06:10:52 PM PDT 24
Finished Jun 28 06:10:59 PM PDT 24
Peak memory 206188 kb
Host smart-ee381dfc-249a-412d-b60c-15eac8ec19d3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3136817229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.3136817229
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.2002387075
Short name T493
Test name
Test status
Simulation time 59576308 ps
CPU time 0.66 seconds
Started Jun 28 06:10:51 PM PDT 24
Finished Jun 28 06:10:57 PM PDT 24
Peak memory 206204 kb
Host smart-2a6022d6-e3b9-4da2-a1af-25668b232a39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20023
87075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.2002387075
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.4222549214
Short name T264
Test name
Test status
Simulation time 20590185763 ps
CPU time 44.94 seconds
Started Jun 28 06:10:54 PM PDT 24
Finished Jun 28 06:11:45 PM PDT 24
Peak memory 206584 kb
Host smart-2c78bb18-a2e3-4879-97e7-6dd4fa4d8478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42225
49214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.4222549214
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.2095219110
Short name T2320
Test name
Test status
Simulation time 186704422 ps
CPU time 0.85 seconds
Started Jun 28 06:10:59 PM PDT 24
Finished Jun 28 06:11:06 PM PDT 24
Peak memory 206188 kb
Host smart-34a44a2f-de60-4655-860c-ed639c93574f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20952
19110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.2095219110
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.2541856373
Short name T1847
Test name
Test status
Simulation time 229733981 ps
CPU time 0.84 seconds
Started Jun 28 06:10:58 PM PDT 24
Finished Jun 28 06:11:05 PM PDT 24
Peak memory 206204 kb
Host smart-407ddaa1-1047-4ae0-bdf0-bd4e2e52b886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25418
56373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.2541856373
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.3432013870
Short name T2461
Test name
Test status
Simulation time 253046378 ps
CPU time 0.95 seconds
Started Jun 28 06:10:56 PM PDT 24
Finished Jun 28 06:11:03 PM PDT 24
Peak memory 206196 kb
Host smart-9b2bdaf1-00f6-4c77-958e-1a4c34a5a431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34320
13870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.3432013870
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.2009352541
Short name T2094
Test name
Test status
Simulation time 227960484 ps
CPU time 0.84 seconds
Started Jun 28 06:10:56 PM PDT 24
Finished Jun 28 06:11:03 PM PDT 24
Peak memory 206176 kb
Host smart-20e9d092-e83b-4c31-8ace-8ae5d5c2aa83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20093
52541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.2009352541
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.2301747324
Short name T1328
Test name
Test status
Simulation time 184262811 ps
CPU time 0.81 seconds
Started Jun 28 06:10:59 PM PDT 24
Finished Jun 28 06:11:05 PM PDT 24
Peak memory 206196 kb
Host smart-e8a49a4c-f907-4647-9049-a8c623b01f6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23017
47324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.2301747324
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.2824852494
Short name T1050
Test name
Test status
Simulation time 162321477 ps
CPU time 0.78 seconds
Started Jun 28 06:10:52 PM PDT 24
Finished Jun 28 06:10:59 PM PDT 24
Peak memory 206176 kb
Host smart-55612606-1a5c-4dfb-82cf-8f990adf7d2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28248
52494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.2824852494
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.3350835915
Short name T829
Test name
Test status
Simulation time 146136433 ps
CPU time 0.78 seconds
Started Jun 28 06:10:59 PM PDT 24
Finished Jun 28 06:11:06 PM PDT 24
Peak memory 206188 kb
Host smart-97bae860-08aa-4be9-8528-b4caa4dc63ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33508
35915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.3350835915
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.3090475596
Short name T691
Test name
Test status
Simulation time 216184262 ps
CPU time 0.95 seconds
Started Jun 28 06:10:58 PM PDT 24
Finished Jun 28 06:11:05 PM PDT 24
Peak memory 206212 kb
Host smart-6e46630b-138e-42d3-913b-76d041a6fcf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30904
75596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.3090475596
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.3315294220
Short name T1838
Test name
Test status
Simulation time 4690742386 ps
CPU time 44.86 seconds
Started Jun 28 06:10:54 PM PDT 24
Finished Jun 28 06:11:45 PM PDT 24
Peak memory 206416 kb
Host smart-d4c17e54-82c3-4f29-9c9b-fb3ef149eab9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3315294220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.3315294220
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.1660247380
Short name T789
Test name
Test status
Simulation time 225291187 ps
CPU time 0.87 seconds
Started Jun 28 06:10:54 PM PDT 24
Finished Jun 28 06:11:01 PM PDT 24
Peak memory 206216 kb
Host smart-588db50f-3bdd-402c-bb77-ede8c7fa313b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16602
47380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.1660247380
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.1190992733
Short name T1304
Test name
Test status
Simulation time 165235518 ps
CPU time 0.8 seconds
Started Jun 28 06:10:52 PM PDT 24
Finished Jun 28 06:10:58 PM PDT 24
Peak memory 206196 kb
Host smart-5b95b05f-3ee8-4df6-ad3b-dbd5943b0cc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11909
92733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.1190992733
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.4084945412
Short name T473
Test name
Test status
Simulation time 4554656097 ps
CPU time 117.65 seconds
Started Jun 28 06:10:58 PM PDT 24
Finished Jun 28 06:13:01 PM PDT 24
Peak memory 206436 kb
Host smart-b5416c9c-e1fd-401f-9701-335ce1832654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40849
45412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.4084945412
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.3857415062
Short name T1781
Test name
Test status
Simulation time 43782513 ps
CPU time 0.68 seconds
Started Jun 28 06:11:04 PM PDT 24
Finished Jun 28 06:11:09 PM PDT 24
Peak memory 206212 kb
Host smart-e869a2b7-a9cc-4473-b3ab-c5dd245ec5d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3857415062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.3857415062
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.3718558791
Short name T2504
Test name
Test status
Simulation time 3888506409 ps
CPU time 4.37 seconds
Started Jun 28 06:10:54 PM PDT 24
Finished Jun 28 06:11:05 PM PDT 24
Peak memory 206392 kb
Host smart-729bbaa7-64b6-494c-bd66-9cc50f4d335a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3718558791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.3718558791
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.2817520345
Short name T986
Test name
Test status
Simulation time 13392867439 ps
CPU time 12.94 seconds
Started Jun 28 06:11:00 PM PDT 24
Finished Jun 28 06:11:19 PM PDT 24
Peak memory 206320 kb
Host smart-083544ed-a497-4ed6-a5de-15f0b8f24dd7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2817520345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.2817520345
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.3512242916
Short name T1511
Test name
Test status
Simulation time 23358998182 ps
CPU time 24.45 seconds
Started Jun 28 06:10:54 PM PDT 24
Finished Jun 28 06:11:25 PM PDT 24
Peak memory 206312 kb
Host smart-86b81c5e-6ada-4e8c-8697-adeb9d0857cc
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3512242916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.3512242916
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.4013128318
Short name T455
Test name
Test status
Simulation time 158027130 ps
CPU time 0.78 seconds
Started Jun 28 06:11:00 PM PDT 24
Finished Jun 28 06:11:06 PM PDT 24
Peak memory 206184 kb
Host smart-6846c67e-9bef-4929-9fe1-2f9a97a916d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40131
28318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.4013128318
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.713695560
Short name T1132
Test name
Test status
Simulation time 164258482 ps
CPU time 0.78 seconds
Started Jun 28 06:11:00 PM PDT 24
Finished Jun 28 06:11:06 PM PDT 24
Peak memory 206192 kb
Host smart-cdb4741c-ba5f-410b-b18d-497c2dff6634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71369
5560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.713695560
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.4180198634
Short name T909
Test name
Test status
Simulation time 363504190 ps
CPU time 1.12 seconds
Started Jun 28 06:10:53 PM PDT 24
Finished Jun 28 06:11:00 PM PDT 24
Peak memory 206192 kb
Host smart-df97a7b6-5d2f-4bb5-a86d-734353bbb279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41801
98634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.4180198634
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_device_address.2289305185
Short name T2072
Test name
Test status
Simulation time 6110876013 ps
CPU time 12.2 seconds
Started Jun 28 06:10:52 PM PDT 24
Finished Jun 28 06:11:09 PM PDT 24
Peak memory 206580 kb
Host smart-431d8232-3364-48ea-9669-0f6d9e59e79b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22893
05185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.2289305185
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.4246105614
Short name T1966
Test name
Test status
Simulation time 476552958 ps
CPU time 1.35 seconds
Started Jun 28 06:11:00 PM PDT 24
Finished Jun 28 06:11:07 PM PDT 24
Peak memory 206200 kb
Host smart-0b8a697e-443a-45a3-9972-afacf9977390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42461
05614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.4246105614
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.375592114
Short name T1177
Test name
Test status
Simulation time 143711547 ps
CPU time 0.77 seconds
Started Jun 28 06:10:55 PM PDT 24
Finished Jun 28 06:11:02 PM PDT 24
Peak memory 206184 kb
Host smart-de40f472-0360-442e-91e6-b52ad26b12aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37559
2114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.375592114
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.337943428
Short name T1218
Test name
Test status
Simulation time 30211933 ps
CPU time 0.7 seconds
Started Jun 28 06:10:57 PM PDT 24
Finished Jun 28 06:11:04 PM PDT 24
Peak memory 206208 kb
Host smart-ce6dd4e5-45e4-4d1c-abee-b51380b752f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33794
3428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.337943428
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.4019085512
Short name T578
Test name
Test status
Simulation time 1023160223 ps
CPU time 2.39 seconds
Started Jun 28 06:11:00 PM PDT 24
Finished Jun 28 06:11:08 PM PDT 24
Peak memory 206320 kb
Host smart-fff56298-1ccd-41ab-b503-e7a54b743c09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40190
85512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.4019085512
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.2992974375
Short name T1988
Test name
Test status
Simulation time 214868901 ps
CPU time 2.36 seconds
Started Jun 28 06:10:52 PM PDT 24
Finished Jun 28 06:11:00 PM PDT 24
Peak memory 206288 kb
Host smart-a32ffce8-3acd-4104-aba7-e1ebc38b0a20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29929
74375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.2992974375
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.3188715771
Short name T2296
Test name
Test status
Simulation time 203758614 ps
CPU time 0.89 seconds
Started Jun 28 06:11:14 PM PDT 24
Finished Jun 28 06:11:16 PM PDT 24
Peak memory 206188 kb
Host smart-fd4754ce-59de-4de7-ab42-fe9a6e521c2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31887
15771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.3188715771
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.2650291826
Short name T966
Test name
Test status
Simulation time 146968010 ps
CPU time 0.78 seconds
Started Jun 28 06:10:56 PM PDT 24
Finished Jun 28 06:11:03 PM PDT 24
Peak memory 206212 kb
Host smart-309f0dff-3f1f-4965-9a7c-fa07009044a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26502
91826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.2650291826
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.4056266476
Short name T1519
Test name
Test status
Simulation time 256531301 ps
CPU time 0.94 seconds
Started Jun 28 06:11:05 PM PDT 24
Finished Jun 28 06:11:10 PM PDT 24
Peak memory 206152 kb
Host smart-34bbc08d-c758-4c78-acf5-39c78e4470c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40562
66476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.4056266476
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_invalid_sync.2101988134
Short name T2282
Test name
Test status
Simulation time 8472278699 ps
CPU time 77.95 seconds
Started Jun 28 06:10:57 PM PDT 24
Finished Jun 28 06:12:21 PM PDT 24
Peak memory 206416 kb
Host smart-2b20e3ec-e780-4fca-ab96-1fca3e551b4a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2101988134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.2101988134
Directory /workspace/16.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.3664910065
Short name T2279
Test name
Test status
Simulation time 239577846 ps
CPU time 0.97 seconds
Started Jun 28 06:10:54 PM PDT 24
Finished Jun 28 06:11:01 PM PDT 24
Peak memory 206144 kb
Host smart-d40746fc-0533-42d0-915d-3973f09de8a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36649
10065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.3664910065
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.2776850549
Short name T2466
Test name
Test status
Simulation time 23277527913 ps
CPU time 22.28 seconds
Started Jun 28 06:11:05 PM PDT 24
Finished Jun 28 06:11:32 PM PDT 24
Peak memory 206248 kb
Host smart-4ec5aca5-9b39-4757-979b-e3a64c1eb0b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27768
50549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.2776850549
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.363614208
Short name T2529
Test name
Test status
Simulation time 3322802222 ps
CPU time 4.25 seconds
Started Jun 28 06:11:05 PM PDT 24
Finished Jun 28 06:11:15 PM PDT 24
Peak memory 206196 kb
Host smart-69232b29-4b65-444b-a0a7-aad8bd9040d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36361
4208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.363614208
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.39493361
Short name T1868
Test name
Test status
Simulation time 10038416648 ps
CPU time 268.99 seconds
Started Jun 28 06:11:05 PM PDT 24
Finished Jun 28 06:15:39 PM PDT 24
Peak memory 206408 kb
Host smart-58eac2c4-8e49-4cb9-b3aa-94c8ddb49d3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39493
361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.39493361
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.1105913530
Short name T435
Test name
Test status
Simulation time 3795946294 ps
CPU time 34.96 seconds
Started Jun 28 06:11:05 PM PDT 24
Finished Jun 28 06:11:44 PM PDT 24
Peak memory 206432 kb
Host smart-64f4e39e-067a-4561-ac11-69358d2b9c33
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1105913530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.1105913530
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.822532966
Short name T256
Test name
Test status
Simulation time 274491814 ps
CPU time 0.99 seconds
Started Jun 28 06:11:05 PM PDT 24
Finished Jun 28 06:11:10 PM PDT 24
Peak memory 206156 kb
Host smart-fb2bb63a-6269-4bce-9153-c1b3df84a1cd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=822532966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.822532966
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.1183437071
Short name T1722
Test name
Test status
Simulation time 185556541 ps
CPU time 0.87 seconds
Started Jun 28 06:10:55 PM PDT 24
Finished Jun 28 06:11:02 PM PDT 24
Peak memory 206196 kb
Host smart-63a6a681-9c32-4ac4-98d2-4af809d177ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11834
37071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.1183437071
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.3466002468
Short name T1631
Test name
Test status
Simulation time 7266491205 ps
CPU time 50.43 seconds
Started Jun 28 06:10:55 PM PDT 24
Finished Jun 28 06:11:52 PM PDT 24
Peak memory 206428 kb
Host smart-cd407cf2-f082-4889-9eda-fe21365bfe7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34660
02468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.3466002468
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.555512726
Short name T2194
Test name
Test status
Simulation time 5678577956 ps
CPU time 158.83 seconds
Started Jun 28 06:10:52 PM PDT 24
Finished Jun 28 06:13:37 PM PDT 24
Peak memory 206428 kb
Host smart-aa8e03a3-b84d-4544-a174-71bb030464da
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=555512726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.555512726
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.3682331209
Short name T1995
Test name
Test status
Simulation time 156454414 ps
CPU time 0.86 seconds
Started Jun 28 06:10:54 PM PDT 24
Finished Jun 28 06:11:01 PM PDT 24
Peak memory 206328 kb
Host smart-bd14cae3-efa2-4e71-8e9d-e57bf2a35efa
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3682331209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.3682331209
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.2461764753
Short name T712
Test name
Test status
Simulation time 158672177 ps
CPU time 0.81 seconds
Started Jun 28 06:10:58 PM PDT 24
Finished Jun 28 06:11:05 PM PDT 24
Peak memory 206196 kb
Host smart-c3204116-2378-4120-92bf-6e92ed7af12d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24617
64753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.2461764753
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.1004394072
Short name T1865
Test name
Test status
Simulation time 178772770 ps
CPU time 0.87 seconds
Started Jun 28 06:10:53 PM PDT 24
Finished Jun 28 06:11:00 PM PDT 24
Peak memory 206168 kb
Host smart-9d910ed2-d7f2-408f-93e0-52a6fd79f9c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10043
94072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.1004394072
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.3777688399
Short name T854
Test name
Test status
Simulation time 184137037 ps
CPU time 0.78 seconds
Started Jun 28 06:10:55 PM PDT 24
Finished Jun 28 06:11:01 PM PDT 24
Peak memory 206132 kb
Host smart-348c0a26-7947-492a-8780-93984aa4ad8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37776
88399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.3777688399
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.1884106138
Short name T2146
Test name
Test status
Simulation time 165755304 ps
CPU time 0.86 seconds
Started Jun 28 06:10:55 PM PDT 24
Finished Jun 28 06:11:02 PM PDT 24
Peak memory 206352 kb
Host smart-a18a714f-abf3-41ae-a2b3-ea21e785bfb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18841
06138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.1884106138
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.1345731684
Short name T441
Test name
Test status
Simulation time 159788901 ps
CPU time 0.85 seconds
Started Jun 28 06:10:57 PM PDT 24
Finished Jun 28 06:11:04 PM PDT 24
Peak memory 206196 kb
Host smart-e2b74c43-36e0-41f0-add2-8eec8d5ca71d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13457
31684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.1345731684
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.334006871
Short name T1639
Test name
Test status
Simulation time 245549292 ps
CPU time 1.02 seconds
Started Jun 28 06:10:55 PM PDT 24
Finished Jun 28 06:11:02 PM PDT 24
Peak memory 206328 kb
Host smart-93b46f65-ef85-4131-9a29-66fe29f3b60c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=334006871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.334006871
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.2559436130
Short name T1454
Test name
Test status
Simulation time 149410334 ps
CPU time 0.75 seconds
Started Jun 28 06:10:54 PM PDT 24
Finished Jun 28 06:11:01 PM PDT 24
Peak memory 206196 kb
Host smart-6d86c438-6698-4a0b-a3ef-667cb4259e7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25594
36130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.2559436130
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.2606877147
Short name T1962
Test name
Test status
Simulation time 44693216 ps
CPU time 0.65 seconds
Started Jun 28 06:10:56 PM PDT 24
Finished Jun 28 06:11:02 PM PDT 24
Peak memory 206200 kb
Host smart-f7b345d4-a224-4d6d-b3f5-9caf447296e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26068
77147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.2606877147
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.2446300537
Short name T1892
Test name
Test status
Simulation time 12803207543 ps
CPU time 30.93 seconds
Started Jun 28 06:10:54 PM PDT 24
Finished Jun 28 06:11:31 PM PDT 24
Peak memory 206404 kb
Host smart-25b08fac-f74a-4a0e-b03c-f455cfe15f40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24463
00537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.2446300537
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.721191561
Short name T999
Test name
Test status
Simulation time 171277252 ps
CPU time 0.81 seconds
Started Jun 28 06:10:55 PM PDT 24
Finished Jun 28 06:11:02 PM PDT 24
Peak memory 206132 kb
Host smart-ab17e5fe-1d30-48e7-bdab-7a5d4c39c16f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72119
1561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.721191561
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.1809426543
Short name T950
Test name
Test status
Simulation time 186255665 ps
CPU time 0.86 seconds
Started Jun 28 06:10:58 PM PDT 24
Finished Jun 28 06:11:04 PM PDT 24
Peak memory 206212 kb
Host smart-41f22af7-2729-44bc-9c75-4cdac8a2ee50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18094
26543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.1809426543
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.1509118063
Short name T1739
Test name
Test status
Simulation time 220480001 ps
CPU time 0.92 seconds
Started Jun 28 06:10:56 PM PDT 24
Finished Jun 28 06:11:03 PM PDT 24
Peak memory 206196 kb
Host smart-514c14fd-cdf5-4d7f-aa9f-16fc9c22d54e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15091
18063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.1509118063
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.2485796679
Short name T1912
Test name
Test status
Simulation time 147720552 ps
CPU time 0.82 seconds
Started Jun 28 06:10:58 PM PDT 24
Finished Jun 28 06:11:05 PM PDT 24
Peak memory 206196 kb
Host smart-7d600de9-612f-4f67-8b3c-ed868c40723c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24857
96679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.2485796679
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.3532388876
Short name T1024
Test name
Test status
Simulation time 180204391 ps
CPU time 0.84 seconds
Started Jun 28 06:10:55 PM PDT 24
Finished Jun 28 06:11:03 PM PDT 24
Peak memory 206168 kb
Host smart-dc80c47c-684e-4f2e-9f17-ebc796e36135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35323
88876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.3532388876
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.2198099481
Short name T1141
Test name
Test status
Simulation time 156241081 ps
CPU time 0.79 seconds
Started Jun 28 06:10:51 PM PDT 24
Finished Jun 28 06:10:57 PM PDT 24
Peak memory 206196 kb
Host smart-03aff271-2033-4067-8a6a-d4cc01b8d63f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21980
99481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.2198099481
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.742628146
Short name T1237
Test name
Test status
Simulation time 145060598 ps
CPU time 0.76 seconds
Started Jun 28 06:10:56 PM PDT 24
Finished Jun 28 06:11:03 PM PDT 24
Peak memory 206140 kb
Host smart-66c896a3-2851-44b8-bbd5-8c3b6671476b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74262
8146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.742628146
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.36578717
Short name T1334
Test name
Test status
Simulation time 203212533 ps
CPU time 0.9 seconds
Started Jun 28 06:10:58 PM PDT 24
Finished Jun 28 06:11:05 PM PDT 24
Peak memory 206188 kb
Host smart-71a76da8-6a61-42ed-bf86-9abf719457da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36578
717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.36578717
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.4156653426
Short name T1345
Test name
Test status
Simulation time 4537339962 ps
CPU time 31.15 seconds
Started Jun 28 06:10:58 PM PDT 24
Finished Jun 28 06:11:35 PM PDT 24
Peak memory 206432 kb
Host smart-fda0d03e-4510-414e-bde4-39d9ac0f0e5c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4156653426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.4156653426
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.28648399
Short name T254
Test name
Test status
Simulation time 154307322 ps
CPU time 0.8 seconds
Started Jun 28 06:11:04 PM PDT 24
Finished Jun 28 06:11:10 PM PDT 24
Peak memory 206188 kb
Host smart-4a76873a-0393-40b9-a5cb-8d6d2ec6a06d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28648
399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.28648399
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.1355941202
Short name T767
Test name
Test status
Simulation time 171225927 ps
CPU time 0.8 seconds
Started Jun 28 06:11:03 PM PDT 24
Finished Jun 28 06:11:08 PM PDT 24
Peak memory 206172 kb
Host smart-10784d13-c398-4617-9e19-821f84e2d45e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13559
41202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.1355941202
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.173692133
Short name T2306
Test name
Test status
Simulation time 5169952749 ps
CPU time 37.21 seconds
Started Jun 28 06:11:06 PM PDT 24
Finished Jun 28 06:11:48 PM PDT 24
Peak memory 206480 kb
Host smart-fdd18a33-210f-4d0a-a08d-a4e399005e94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17369
2133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.173692133
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.1361345057
Short name T1208
Test name
Test status
Simulation time 34130742 ps
CPU time 0.67 seconds
Started Jun 28 06:11:08 PM PDT 24
Finished Jun 28 06:11:14 PM PDT 24
Peak memory 206176 kb
Host smart-dc5528c0-78f5-4ee9-910e-876d6d4b341b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1361345057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.1361345057
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.3830089603
Short name T636
Test name
Test status
Simulation time 4099813586 ps
CPU time 4.99 seconds
Started Jun 28 06:11:03 PM PDT 24
Finished Jun 28 06:11:13 PM PDT 24
Peak memory 206352 kb
Host smart-ee0d26cf-fa59-4f14-9ee6-106308e7062f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3830089603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.3830089603
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.2924538121
Short name T230
Test name
Test status
Simulation time 23400998369 ps
CPU time 23.08 seconds
Started Jun 28 06:11:10 PM PDT 24
Finished Jun 28 06:11:37 PM PDT 24
Peak memory 206320 kb
Host smart-0d6ac4f0-bb42-47cd-aeca-f5ce477ea9b6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2924538121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.2924538121
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.1481512813
Short name T360
Test name
Test status
Simulation time 220338781 ps
CPU time 0.9 seconds
Started Jun 28 06:11:07 PM PDT 24
Finished Jun 28 06:11:13 PM PDT 24
Peak memory 206188 kb
Host smart-98501852-dabc-4ba6-9f89-a765838c9288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14815
12813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.1481512813
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.968527280
Short name T541
Test name
Test status
Simulation time 147557905 ps
CPU time 0.78 seconds
Started Jun 28 06:11:04 PM PDT 24
Finished Jun 28 06:11:09 PM PDT 24
Peak memory 206196 kb
Host smart-b28b9abd-c35f-4baf-937e-d10e000db37f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96852
7280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.968527280
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.1097336948
Short name T2464
Test name
Test status
Simulation time 576538234 ps
CPU time 1.65 seconds
Started Jun 28 06:11:05 PM PDT 24
Finished Jun 28 06:11:11 PM PDT 24
Peak memory 206256 kb
Host smart-013f2c85-4601-49f1-82c6-fe15a92b40a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10973
36948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.1097336948
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.193821169
Short name T2062
Test name
Test status
Simulation time 1345685044 ps
CPU time 2.74 seconds
Started Jun 28 06:11:07 PM PDT 24
Finished Jun 28 06:11:15 PM PDT 24
Peak memory 206248 kb
Host smart-27cf772a-76be-4f42-ac2a-e433b5a43d0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19382
1169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.193821169
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.3349382702
Short name T85
Test name
Test status
Simulation time 18299847430 ps
CPU time 34.42 seconds
Started Jun 28 06:11:20 PM PDT 24
Finished Jun 28 06:11:57 PM PDT 24
Peak memory 206412 kb
Host smart-6a8b72ca-51cb-43e2-b8af-9dfb4fa75253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33493
82702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.3349382702
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.2877999493
Short name T1565
Test name
Test status
Simulation time 504921697 ps
CPU time 1.61 seconds
Started Jun 28 06:11:04 PM PDT 24
Finished Jun 28 06:11:10 PM PDT 24
Peak memory 206196 kb
Host smart-9aa6e3ff-6b83-4dbc-93e8-f3bd2aa0089c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28779
99493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.2877999493
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.2605871204
Short name T1778
Test name
Test status
Simulation time 144970182 ps
CPU time 0.75 seconds
Started Jun 28 06:11:07 PM PDT 24
Finished Jun 28 06:11:13 PM PDT 24
Peak memory 206148 kb
Host smart-97d18e08-eb87-4dbf-95ef-c3dfe338df41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26058
71204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.2605871204
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.3926403994
Short name T780
Test name
Test status
Simulation time 37112433 ps
CPU time 0.65 seconds
Started Jun 28 06:11:04 PM PDT 24
Finished Jun 28 06:11:09 PM PDT 24
Peak memory 206184 kb
Host smart-ef8c8547-ee6f-4140-9edc-967c36ca6544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39264
03994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.3926403994
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.556440860
Short name T1567
Test name
Test status
Simulation time 855501663 ps
CPU time 2.04 seconds
Started Jun 28 06:11:05 PM PDT 24
Finished Jun 28 06:11:12 PM PDT 24
Peak memory 206292 kb
Host smart-9db88768-5dc4-4cf3-97c2-0d61d2076db5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55644
0860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.556440860
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.2828432906
Short name T610
Test name
Test status
Simulation time 203708391 ps
CPU time 1.97 seconds
Started Jun 28 06:11:02 PM PDT 24
Finished Jun 28 06:11:09 PM PDT 24
Peak memory 206288 kb
Host smart-14359aba-5ab3-43a7-9a32-954cf756f0c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28284
32906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.2828432906
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.3981254165
Short name T516
Test name
Test status
Simulation time 178002858 ps
CPU time 0.88 seconds
Started Jun 28 06:11:09 PM PDT 24
Finished Jun 28 06:11:14 PM PDT 24
Peak memory 206104 kb
Host smart-fa980d9a-cc7c-4231-9bf7-004dd76c55db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39812
54165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.3981254165
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.2513752069
Short name T2150
Test name
Test status
Simulation time 152312480 ps
CPU time 0.74 seconds
Started Jun 28 06:11:03 PM PDT 24
Finished Jun 28 06:11:08 PM PDT 24
Peak memory 206184 kb
Host smart-4b00192d-df9c-4f36-b5c9-af213c31473a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25137
52069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.2513752069
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.356385564
Short name T1820
Test name
Test status
Simulation time 196193598 ps
CPU time 0.89 seconds
Started Jun 28 06:11:03 PM PDT 24
Finished Jun 28 06:11:09 PM PDT 24
Peak memory 206204 kb
Host smart-e7b557e7-9589-4203-92c0-8d7c035f9cdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35638
5564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.356385564
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_invalid_sync.1774342466
Short name T912
Test name
Test status
Simulation time 6599682302 ps
CPU time 45.79 seconds
Started Jun 28 06:11:04 PM PDT 24
Finished Jun 28 06:11:54 PM PDT 24
Peak memory 206412 kb
Host smart-c9680961-36ce-417a-ab1b-1e338d304736
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1774342466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.1774342466
Directory /workspace/17.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.3235412823
Short name T1773
Test name
Test status
Simulation time 208455080 ps
CPU time 0.84 seconds
Started Jun 28 06:11:07 PM PDT 24
Finished Jun 28 06:11:13 PM PDT 24
Peak memory 206192 kb
Host smart-33917aba-4a14-4447-9dfb-207f4fae3a8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32354
12823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.3235412823
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.2099158712
Short name T16
Test name
Test status
Simulation time 23289233367 ps
CPU time 22.99 seconds
Started Jun 28 06:11:04 PM PDT 24
Finished Jun 28 06:11:32 PM PDT 24
Peak memory 206316 kb
Host smart-8fe4af38-7438-4926-a80b-fda85aaf7207
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20991
58712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.2099158712
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.3322236673
Short name T365
Test name
Test status
Simulation time 3325841632 ps
CPU time 4.7 seconds
Started Jun 28 06:11:05 PM PDT 24
Finished Jun 28 06:11:15 PM PDT 24
Peak memory 206244 kb
Host smart-e00faefa-c27f-4ddd-87cb-5a52c28acd47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33222
36673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.3322236673
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.1695350687
Short name T444
Test name
Test status
Simulation time 7694991468 ps
CPU time 55.03 seconds
Started Jun 28 06:11:05 PM PDT 24
Finished Jun 28 06:12:05 PM PDT 24
Peak memory 206452 kb
Host smart-8ddb731c-d7da-4587-9828-bd1b8c0d3e86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16953
50687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.1695350687
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.3286827953
Short name T494
Test name
Test status
Simulation time 6203918545 ps
CPU time 56.79 seconds
Started Jun 28 06:11:06 PM PDT 24
Finished Jun 28 06:12:07 PM PDT 24
Peak memory 206224 kb
Host smart-b171fe06-2ccc-44eb-8822-2a5e40885499
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3286827953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.3286827953
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.538428643
Short name T2290
Test name
Test status
Simulation time 234463170 ps
CPU time 0.9 seconds
Started Jun 28 06:11:04 PM PDT 24
Finished Jun 28 06:11:10 PM PDT 24
Peak memory 206220 kb
Host smart-0eee2e2c-381f-4aaa-bbe6-551aab6bdcb7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=538428643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.538428643
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.248506738
Short name T2087
Test name
Test status
Simulation time 191342997 ps
CPU time 0.85 seconds
Started Jun 28 06:11:16 PM PDT 24
Finished Jun 28 06:11:18 PM PDT 24
Peak memory 206208 kb
Host smart-ff7d3b7b-6a5d-4a1e-93d0-bc7f739adae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24850
6738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.248506738
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.4039300343
Short name T1670
Test name
Test status
Simulation time 6155909249 ps
CPU time 171.15 seconds
Started Jun 28 06:11:03 PM PDT 24
Finished Jun 28 06:13:59 PM PDT 24
Peak memory 206464 kb
Host smart-61cd05e3-9540-45ba-8e4f-e48966e7e4f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40393
00343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.4039300343
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.1006742241
Short name T2232
Test name
Test status
Simulation time 6323820582 ps
CPU time 59.95 seconds
Started Jun 28 06:11:09 PM PDT 24
Finished Jun 28 06:12:13 PM PDT 24
Peak memory 206340 kb
Host smart-b6cc2037-2e3e-4a01-9bab-314fe98765bf
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1006742241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.1006742241
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.3382752219
Short name T661
Test name
Test status
Simulation time 148220366 ps
CPU time 0.77 seconds
Started Jun 28 06:11:04 PM PDT 24
Finished Jun 28 06:11:09 PM PDT 24
Peak memory 206168 kb
Host smart-32c6f818-03c6-433e-9b5c-2244f4348977
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3382752219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.3382752219
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.3156495987
Short name T1791
Test name
Test status
Simulation time 172353709 ps
CPU time 0.78 seconds
Started Jun 28 06:11:03 PM PDT 24
Finished Jun 28 06:11:09 PM PDT 24
Peak memory 206168 kb
Host smart-ddc9488e-94a5-4ff0-997f-464bdf5f76ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31564
95987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.3156495987
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.4191643099
Short name T1137
Test name
Test status
Simulation time 155461053 ps
CPU time 0.82 seconds
Started Jun 28 06:11:06 PM PDT 24
Finished Jun 28 06:11:12 PM PDT 24
Peak memory 206164 kb
Host smart-76cc71f2-0885-44a6-a99e-d4d531b6483b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41916
43099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.4191643099
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.3953751445
Short name T418
Test name
Test status
Simulation time 185138979 ps
CPU time 0.85 seconds
Started Jun 28 06:11:05 PM PDT 24
Finished Jun 28 06:11:11 PM PDT 24
Peak memory 206160 kb
Host smart-0b89509c-e59f-4ae3-aeb8-9503708258d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39537
51445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.3953751445
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.1039114467
Short name T2366
Test name
Test status
Simulation time 169369500 ps
CPU time 0.83 seconds
Started Jun 28 06:11:10 PM PDT 24
Finished Jun 28 06:11:15 PM PDT 24
Peak memory 206216 kb
Host smart-78cb6404-edad-4924-92ee-224b5c21318e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10391
14467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.1039114467
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.614212668
Short name T1448
Test name
Test status
Simulation time 150251155 ps
CPU time 0.8 seconds
Started Jun 28 06:11:05 PM PDT 24
Finished Jun 28 06:11:12 PM PDT 24
Peak memory 206176 kb
Host smart-98c925b6-9f25-4b2b-9771-be55c64b53b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61421
2668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.614212668
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.344497559
Short name T1719
Test name
Test status
Simulation time 212902346 ps
CPU time 0.9 seconds
Started Jun 28 06:11:16 PM PDT 24
Finished Jun 28 06:11:19 PM PDT 24
Peak memory 206204 kb
Host smart-99bd44ef-9fbb-4349-9375-b494a730e9c6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=344497559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.344497559
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.4080361683
Short name T940
Test name
Test status
Simulation time 147049773 ps
CPU time 0.77 seconds
Started Jun 28 06:11:04 PM PDT 24
Finished Jun 28 06:11:09 PM PDT 24
Peak memory 206196 kb
Host smart-fa105c30-7062-455f-b6ba-720f90d1a85e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40803
61683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.4080361683
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.1185273695
Short name T25
Test name
Test status
Simulation time 51649562 ps
CPU time 0.67 seconds
Started Jun 28 06:11:08 PM PDT 24
Finished Jun 28 06:11:14 PM PDT 24
Peak memory 206168 kb
Host smart-23681943-f70c-4584-a19e-7ed0ac8c9ffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11852
73695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.1185273695
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.2949953938
Short name T1705
Test name
Test status
Simulation time 21871903212 ps
CPU time 54.37 seconds
Started Jun 28 06:11:04 PM PDT 24
Finished Jun 28 06:12:03 PM PDT 24
Peak memory 206424 kb
Host smart-e3050a97-8ed6-4169-af50-afb642a058cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29499
53938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.2949953938
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.1891483239
Short name T1406
Test name
Test status
Simulation time 161873871 ps
CPU time 0.82 seconds
Started Jun 28 06:11:06 PM PDT 24
Finished Jun 28 06:11:11 PM PDT 24
Peak memory 205916 kb
Host smart-5e9cc6db-5579-4ce0-b216-3ef96da49470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18914
83239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.1891483239
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.1512828729
Short name T1215
Test name
Test status
Simulation time 210715198 ps
CPU time 0.89 seconds
Started Jun 28 06:11:06 PM PDT 24
Finished Jun 28 06:11:12 PM PDT 24
Peak memory 206180 kb
Host smart-87f518e7-8bb9-4277-8f1d-afcb9747417d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15128
28729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.1512828729
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.3955496559
Short name T1725
Test name
Test status
Simulation time 186165019 ps
CPU time 0.82 seconds
Started Jun 28 06:11:19 PM PDT 24
Finished Jun 28 06:11:22 PM PDT 24
Peak memory 206220 kb
Host smart-27d96827-7703-47bb-8899-ee5f767f61e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39554
96559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.3955496559
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.2268164398
Short name T1076
Test name
Test status
Simulation time 162953137 ps
CPU time 0.79 seconds
Started Jun 28 06:11:05 PM PDT 24
Finished Jun 28 06:11:11 PM PDT 24
Peak memory 206200 kb
Host smart-e7bc52b6-9f06-46d8-b6b6-ac3366470b1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22681
64398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.2268164398
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.136025303
Short name T1499
Test name
Test status
Simulation time 218825272 ps
CPU time 0.8 seconds
Started Jun 28 06:11:03 PM PDT 24
Finished Jun 28 06:11:08 PM PDT 24
Peak memory 206200 kb
Host smart-4cdd89c5-cc0d-4cb6-9fdb-358ec10ce8d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13602
5303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.136025303
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.3258052931
Short name T437
Test name
Test status
Simulation time 167746356 ps
CPU time 0.81 seconds
Started Jun 28 06:11:03 PM PDT 24
Finished Jun 28 06:11:09 PM PDT 24
Peak memory 206188 kb
Host smart-66a913cf-5f0e-422a-a5fe-356f8ccf80e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32580
52931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.3258052931
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.2983715100
Short name T1755
Test name
Test status
Simulation time 158570827 ps
CPU time 0.8 seconds
Started Jun 28 06:11:03 PM PDT 24
Finished Jun 28 06:11:09 PM PDT 24
Peak memory 206160 kb
Host smart-d6478bb7-7065-4ef9-b840-2344e3dd82cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29837
15100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.2983715100
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.3341176562
Short name T341
Test name
Test status
Simulation time 241951939 ps
CPU time 0.96 seconds
Started Jun 28 06:11:05 PM PDT 24
Finished Jun 28 06:11:11 PM PDT 24
Peak memory 206216 kb
Host smart-30d6160a-77c7-4791-abd7-5263c95ca08a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33411
76562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.3341176562
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.1839365811
Short name T612
Test name
Test status
Simulation time 5202938048 ps
CPU time 50.28 seconds
Started Jun 28 06:11:03 PM PDT 24
Finished Jun 28 06:11:58 PM PDT 24
Peak memory 206392 kb
Host smart-1077c0b1-7ee2-473a-a00a-6c348bd62c65
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1839365811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.1839365811
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.3572784304
Short name T1823
Test name
Test status
Simulation time 200509406 ps
CPU time 0.83 seconds
Started Jun 28 06:11:16 PM PDT 24
Finished Jun 28 06:11:18 PM PDT 24
Peak memory 206192 kb
Host smart-3d4d5646-ebb3-4979-9cdf-0c03a44dc0c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35727
84304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.3572784304
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.856890620
Short name T1578
Test name
Test status
Simulation time 152661403 ps
CPU time 0.79 seconds
Started Jun 28 06:11:16 PM PDT 24
Finished Jun 28 06:11:18 PM PDT 24
Peak memory 206116 kb
Host smart-fe3debbd-2ab6-452b-b345-72a2f25fd5e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85689
0620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.856890620
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.1437769558
Short name T1571
Test name
Test status
Simulation time 6284566156 ps
CPU time 172.88 seconds
Started Jun 28 06:11:03 PM PDT 24
Finished Jun 28 06:14:01 PM PDT 24
Peak memory 206436 kb
Host smart-bf1c9f1d-6dfa-4332-94fa-bfda6010ebda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14377
69558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.1437769558
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.263182657
Short name T2365
Test name
Test status
Simulation time 54446918 ps
CPU time 0.68 seconds
Started Jun 28 06:11:16 PM PDT 24
Finished Jun 28 06:11:18 PM PDT 24
Peak memory 206208 kb
Host smart-302b0d02-fa76-4b3e-93c9-8fbca5f31c9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=263182657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.263182657
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.3822534630
Short name T38
Test name
Test status
Simulation time 3512359787 ps
CPU time 4.73 seconds
Started Jun 28 06:11:16 PM PDT 24
Finished Jun 28 06:11:22 PM PDT 24
Peak memory 206392 kb
Host smart-9f0b1a2c-4e72-42a8-8f67-21f4c71c245c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3822534630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.3822534630
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.1364982922
Short name T1365
Test name
Test status
Simulation time 13451405231 ps
CPU time 12.92 seconds
Started Jun 28 06:11:10 PM PDT 24
Finished Jun 28 06:11:27 PM PDT 24
Peak memory 206320 kb
Host smart-79033c76-4897-4954-824a-09dc49ede7f1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1364982922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.1364982922
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.1108933799
Short name T195
Test name
Test status
Simulation time 23375266145 ps
CPU time 24.43 seconds
Started Jun 28 06:11:09 PM PDT 24
Finished Jun 28 06:11:38 PM PDT 24
Peak memory 206320 kb
Host smart-3efb0e74-5819-4e27-9e31-ade29b76728b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1108933799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.1108933799
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.2310072217
Short name T1730
Test name
Test status
Simulation time 185646188 ps
CPU time 0.87 seconds
Started Jun 28 06:11:06 PM PDT 24
Finished Jun 28 06:11:12 PM PDT 24
Peak memory 206136 kb
Host smart-c141cc41-aadc-4b6c-b7c3-662a0546257c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23100
72217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.2310072217
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.405035884
Short name T1700
Test name
Test status
Simulation time 148542124 ps
CPU time 0.75 seconds
Started Jun 28 06:11:08 PM PDT 24
Finished Jun 28 06:11:14 PM PDT 24
Peak memory 206172 kb
Host smart-b08ed430-601d-4c8a-9b48-6689254e887b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40503
5884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.405035884
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.1159792281
Short name T186
Test name
Test status
Simulation time 584192747 ps
CPU time 1.53 seconds
Started Jun 28 06:11:09 PM PDT 24
Finished Jun 28 06:11:15 PM PDT 24
Peak memory 206192 kb
Host smart-d3820101-0824-4197-86fd-fe20dbc99356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11597
92281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.1159792281
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.3631728996
Short name T2533
Test name
Test status
Simulation time 18539851700 ps
CPU time 36.43 seconds
Started Jun 28 06:11:05 PM PDT 24
Finished Jun 28 06:11:47 PM PDT 24
Peak memory 206412 kb
Host smart-44d651f1-e4fa-465c-a961-732ed3eb21ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36317
28996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.3631728996
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.1967545671
Short name T1535
Test name
Test status
Simulation time 380433054 ps
CPU time 1.32 seconds
Started Jun 28 06:11:05 PM PDT 24
Finished Jun 28 06:11:11 PM PDT 24
Peak memory 206192 kb
Host smart-d85b3e29-b83f-4d1a-83e4-6205a243ce6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19675
45671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.1967545671
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.2273250200
Short name T2129
Test name
Test status
Simulation time 151900033 ps
CPU time 0.8 seconds
Started Jun 28 06:11:06 PM PDT 24
Finished Jun 28 06:11:12 PM PDT 24
Peak memory 206192 kb
Host smart-5568dd73-cf0a-44c6-abf1-346daee4347e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22732
50200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.2273250200
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.2999673147
Short name T962
Test name
Test status
Simulation time 59898468 ps
CPU time 0.69 seconds
Started Jun 28 06:11:04 PM PDT 24
Finished Jun 28 06:11:10 PM PDT 24
Peak memory 206136 kb
Host smart-32dc894f-e236-45c4-8092-ebaacc215053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29996
73147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.2999673147
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.271570545
Short name T1073
Test name
Test status
Simulation time 974177817 ps
CPU time 2.4 seconds
Started Jun 28 06:11:10 PM PDT 24
Finished Jun 28 06:11:16 PM PDT 24
Peak memory 206292 kb
Host smart-3f681979-aaeb-42d5-bb7e-138f1b0a5d9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27157
0545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.271570545
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.399578733
Short name T2202
Test name
Test status
Simulation time 304481280 ps
CPU time 2.25 seconds
Started Jun 28 06:11:09 PM PDT 24
Finished Jun 28 06:11:16 PM PDT 24
Peak memory 206304 kb
Host smart-36ba0111-862a-4aa1-9bbd-e8e0bf1643ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39957
8733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.399578733
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.2540114480
Short name T1252
Test name
Test status
Simulation time 208264461 ps
CPU time 0.93 seconds
Started Jun 28 06:11:10 PM PDT 24
Finished Jun 28 06:11:15 PM PDT 24
Peak memory 206172 kb
Host smart-f1cb6324-5c49-4467-9747-a59c1956a514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25401
14480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.2540114480
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.2801323729
Short name T104
Test name
Test status
Simulation time 138885530 ps
CPU time 0.8 seconds
Started Jun 28 06:11:04 PM PDT 24
Finished Jun 28 06:11:10 PM PDT 24
Peak memory 206204 kb
Host smart-93ffa3cf-7eeb-4e7b-a01b-ec8ac79554df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28013
23729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.2801323729
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.2720764042
Short name T1482
Test name
Test status
Simulation time 215845590 ps
CPU time 0.93 seconds
Started Jun 28 06:11:10 PM PDT 24
Finished Jun 28 06:11:15 PM PDT 24
Peak memory 206192 kb
Host smart-376b7b43-afce-4bc2-aea3-cce46c2f571d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27207
64042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.2720764042
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.2621175411
Short name T768
Test name
Test status
Simulation time 205984035 ps
CPU time 0.85 seconds
Started Jun 28 06:11:04 PM PDT 24
Finished Jun 28 06:11:09 PM PDT 24
Peak memory 206192 kb
Host smart-03398c23-6653-4a35-b67f-1730cacb8fd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26211
75411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.2621175411
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.905977394
Short name T1377
Test name
Test status
Simulation time 23284185843 ps
CPU time 24.75 seconds
Started Jun 28 06:11:09 PM PDT 24
Finished Jun 28 06:11:38 PM PDT 24
Peak memory 206308 kb
Host smart-fdb24190-38be-4422-ad9c-47c8ed605040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90597
7394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.905977394
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.134137776
Short name T2117
Test name
Test status
Simulation time 3390833135 ps
CPU time 4.37 seconds
Started Jun 28 06:11:10 PM PDT 24
Finished Jun 28 06:11:18 PM PDT 24
Peak memory 206252 kb
Host smart-f1c1ddb6-56e8-40ee-8854-ce898a26b3c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13413
7776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.134137776
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.371864582
Short name T1646
Test name
Test status
Simulation time 6879896878 ps
CPU time 65.4 seconds
Started Jun 28 06:11:08 PM PDT 24
Finished Jun 28 06:12:19 PM PDT 24
Peak memory 206428 kb
Host smart-98990fb5-469f-4ab8-83ca-1581f806370d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37186
4582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.371864582
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.4258672676
Short name T678
Test name
Test status
Simulation time 4147489095 ps
CPU time 115.05 seconds
Started Jun 28 06:11:11 PM PDT 24
Finished Jun 28 06:13:09 PM PDT 24
Peak memory 206428 kb
Host smart-b208dc2c-623d-4a4a-a470-09077851c956
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4258672676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.4258672676
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.951614838
Short name T1832
Test name
Test status
Simulation time 249012185 ps
CPU time 0.94 seconds
Started Jun 28 06:11:11 PM PDT 24
Finished Jun 28 06:11:15 PM PDT 24
Peak memory 206196 kb
Host smart-11ac4532-efe2-4898-a12f-86522d57a4da
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=951614838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.951614838
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.1873604886
Short name T1212
Test name
Test status
Simulation time 184585070 ps
CPU time 0.83 seconds
Started Jun 28 06:11:16 PM PDT 24
Finished Jun 28 06:11:18 PM PDT 24
Peak memory 206156 kb
Host smart-ac4c4844-f2cf-48ac-a4fd-c2cbcae11a04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18736
04886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.1873604886
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.1467617841
Short name T1811
Test name
Test status
Simulation time 6588925864 ps
CPU time 66.35 seconds
Started Jun 28 06:11:23 PM PDT 24
Finished Jun 28 06:12:31 PM PDT 24
Peak memory 206416 kb
Host smart-9d8f3e5b-4a29-4f74-9c96-1e40f7525227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14676
17841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.1467617841
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.1827338331
Short name T2260
Test name
Test status
Simulation time 7388217896 ps
CPU time 68.05 seconds
Started Jun 28 06:11:19 PM PDT 24
Finished Jun 28 06:12:30 PM PDT 24
Peak memory 206292 kb
Host smart-eaaff3aa-50ea-4d2c-8f80-44b708eeb6a8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1827338331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.1827338331
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.4085091050
Short name T2393
Test name
Test status
Simulation time 153479075 ps
CPU time 0.81 seconds
Started Jun 28 06:11:22 PM PDT 24
Finished Jun 28 06:11:25 PM PDT 24
Peak memory 206196 kb
Host smart-e68e932e-3125-4fb6-9e7a-863a10661372
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4085091050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.4085091050
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.3065561006
Short name T1094
Test name
Test status
Simulation time 182532494 ps
CPU time 0.78 seconds
Started Jun 28 06:11:17 PM PDT 24
Finished Jun 28 06:11:19 PM PDT 24
Peak memory 206180 kb
Host smart-d5f4e317-e7b7-44b3-a1ce-263a7380db93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30655
61006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.3065561006
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.1012231449
Short name T2259
Test name
Test status
Simulation time 209953761 ps
CPU time 0.9 seconds
Started Jun 28 06:11:17 PM PDT 24
Finished Jun 28 06:11:19 PM PDT 24
Peak memory 206320 kb
Host smart-bd7572c8-b28a-4da1-8e91-155bd2133519
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10122
31449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.1012231449
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.3614287519
Short name T1903
Test name
Test status
Simulation time 196717086 ps
CPU time 0.84 seconds
Started Jun 28 06:11:23 PM PDT 24
Finished Jun 28 06:11:25 PM PDT 24
Peak memory 206132 kb
Host smart-fc26c700-dffb-4b5e-b8e0-c0516efeb974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36142
87519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.3614287519
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.3975490545
Short name T2060
Test name
Test status
Simulation time 194693972 ps
CPU time 0.82 seconds
Started Jun 28 06:11:18 PM PDT 24
Finished Jun 28 06:11:21 PM PDT 24
Peak memory 206196 kb
Host smart-0aa8e14a-f4a6-416d-99b7-6b783fb7b77e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39754
90545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.3975490545
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.1455096824
Short name T1957
Test name
Test status
Simulation time 165707892 ps
CPU time 0.81 seconds
Started Jun 28 06:11:16 PM PDT 24
Finished Jun 28 06:11:18 PM PDT 24
Peak memory 206212 kb
Host smart-9b6c5c2b-19ff-4642-91ed-b1af2542eb27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14550
96824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.1455096824
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.788518457
Short name T2600
Test name
Test status
Simulation time 162660584 ps
CPU time 0.75 seconds
Started Jun 28 06:11:27 PM PDT 24
Finished Jun 28 06:11:29 PM PDT 24
Peak memory 206216 kb
Host smart-5c892576-5e14-4618-bc4f-93d8de1ce46b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78851
8457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.788518457
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.1852538994
Short name T622
Test name
Test status
Simulation time 223366191 ps
CPU time 0.91 seconds
Started Jun 28 06:11:26 PM PDT 24
Finished Jun 28 06:11:29 PM PDT 24
Peak memory 206144 kb
Host smart-e8b4cdfc-fdf1-4004-9d8c-382513864d7d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1852538994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.1852538994
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.3830344483
Short name T2054
Test name
Test status
Simulation time 152231347 ps
CPU time 0.77 seconds
Started Jun 28 06:11:21 PM PDT 24
Finished Jun 28 06:11:24 PM PDT 24
Peak memory 206200 kb
Host smart-fac419c4-3cc7-4b7b-9003-236b689270c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38303
44483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.3830344483
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.2794646788
Short name T2531
Test name
Test status
Simulation time 39489516 ps
CPU time 0.67 seconds
Started Jun 28 06:11:26 PM PDT 24
Finished Jun 28 06:11:29 PM PDT 24
Peak memory 206200 kb
Host smart-4d7c4a47-5715-4840-9646-f06626a03a76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27946
46788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.2794646788
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.2672989450
Short name T1884
Test name
Test status
Simulation time 12171044702 ps
CPU time 27.69 seconds
Started Jun 28 06:11:18 PM PDT 24
Finished Jun 28 06:11:48 PM PDT 24
Peak memory 206432 kb
Host smart-200fa2eb-3a48-4755-a487-a14a7206acbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26729
89450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.2672989450
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.1340889725
Short name T1408
Test name
Test status
Simulation time 256036791 ps
CPU time 0.88 seconds
Started Jun 28 06:11:19 PM PDT 24
Finished Jun 28 06:11:22 PM PDT 24
Peak memory 206196 kb
Host smart-ab133646-dab5-47ed-ad99-a4c4853b8bcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13408
89725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.1340889725
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.223007080
Short name T2135
Test name
Test status
Simulation time 197206887 ps
CPU time 0.89 seconds
Started Jun 28 06:11:20 PM PDT 24
Finished Jun 28 06:11:24 PM PDT 24
Peak memory 206212 kb
Host smart-32f51c59-3d3f-4836-8d62-365cc5752cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22300
7080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.223007080
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.2573120397
Short name T458
Test name
Test status
Simulation time 212136483 ps
CPU time 0.94 seconds
Started Jun 28 06:11:15 PM PDT 24
Finished Jun 28 06:11:18 PM PDT 24
Peak memory 206208 kb
Host smart-f17469dc-1bd7-4b39-8c6c-77ab1c5b51af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25731
20397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.2573120397
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.1868743617
Short name T2391
Test name
Test status
Simulation time 212266455 ps
CPU time 0.87 seconds
Started Jun 28 06:11:20 PM PDT 24
Finished Jun 28 06:11:23 PM PDT 24
Peak memory 206196 kb
Host smart-d17308a1-659f-417e-a94b-ad3ab1cadf1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18687
43617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.1868743617
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.1358905457
Short name T1514
Test name
Test status
Simulation time 165946395 ps
CPU time 0.79 seconds
Started Jun 28 06:11:20 PM PDT 24
Finished Jun 28 06:11:24 PM PDT 24
Peak memory 206168 kb
Host smart-376e0072-18ab-4a09-8f63-45a1c8efbdd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13589
05457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.1358905457
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.2048798986
Short name T1762
Test name
Test status
Simulation time 150212933 ps
CPU time 0.78 seconds
Started Jun 28 06:11:20 PM PDT 24
Finished Jun 28 06:11:23 PM PDT 24
Peak memory 205372 kb
Host smart-14e1023e-24bd-43c5-b993-4aaf4e8dbed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20487
98986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.2048798986
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.122318839
Short name T1288
Test name
Test status
Simulation time 197299623 ps
CPU time 0.86 seconds
Started Jun 28 06:11:20 PM PDT 24
Finished Jun 28 06:11:23 PM PDT 24
Peak memory 205264 kb
Host smart-5b2de1d4-fb37-41e8-9612-3a46dbb3d3f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12231
8839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.122318839
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.3087633619
Short name T2585
Test name
Test status
Simulation time 211911826 ps
CPU time 0.88 seconds
Started Jun 28 06:11:20 PM PDT 24
Finished Jun 28 06:11:24 PM PDT 24
Peak memory 206216 kb
Host smart-b366070c-497f-499d-bb4f-ca93f8400528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30876
33619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.3087633619
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.2886542354
Short name T1737
Test name
Test status
Simulation time 5887535647 ps
CPU time 163.42 seconds
Started Jun 28 06:11:20 PM PDT 24
Finished Jun 28 06:14:06 PM PDT 24
Peak memory 206464 kb
Host smart-a63fe386-5407-4c75-b487-d32e1a7bab3b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2886542354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.2886542354
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.3372332108
Short name T1047
Test name
Test status
Simulation time 170842746 ps
CPU time 0.83 seconds
Started Jun 28 06:11:27 PM PDT 24
Finished Jun 28 06:11:30 PM PDT 24
Peak memory 206216 kb
Host smart-7e1a86ec-a685-4554-83cf-ef958120ecdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33723
32108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.3372332108
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.1779728415
Short name T730
Test name
Test status
Simulation time 158229636 ps
CPU time 0.74 seconds
Started Jun 28 06:11:19 PM PDT 24
Finished Jun 28 06:11:22 PM PDT 24
Peak memory 206168 kb
Host smart-ea48ece2-9c91-40bb-8d21-4b4d9ef149e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17797
28415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.1779728415
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.278936467
Short name T2397
Test name
Test status
Simulation time 4561128088 ps
CPU time 32.84 seconds
Started Jun 28 06:11:19 PM PDT 24
Finished Jun 28 06:11:55 PM PDT 24
Peak memory 206376 kb
Host smart-c18166f8-40a5-4c36-abda-50742eb54734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27893
6467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.278936467
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.314357118
Short name T777
Test name
Test status
Simulation time 76502504 ps
CPU time 0.69 seconds
Started Jun 28 06:11:29 PM PDT 24
Finished Jun 28 06:11:33 PM PDT 24
Peak memory 206196 kb
Host smart-65559dd4-77fb-4510-9f65-d54e84f83ed3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=314357118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.314357118
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.4042571500
Short name T531
Test name
Test status
Simulation time 4298126025 ps
CPU time 4.75 seconds
Started Jun 28 06:11:18 PM PDT 24
Finished Jun 28 06:11:25 PM PDT 24
Peak memory 206416 kb
Host smart-2a6c8e6b-5505-4edd-b591-00aeb3974e39
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4042571500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.4042571500
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.2546375159
Short name T426
Test name
Test status
Simulation time 13327236126 ps
CPU time 13 seconds
Started Jun 28 06:11:20 PM PDT 24
Finished Jun 28 06:11:36 PM PDT 24
Peak memory 206308 kb
Host smart-021f0bd4-b34a-47eb-ab08-96e6bea45631
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2546375159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.2546375159
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.1019735063
Short name T1976
Test name
Test status
Simulation time 23355301501 ps
CPU time 23.27 seconds
Started Jun 28 06:11:19 PM PDT 24
Finished Jun 28 06:11:44 PM PDT 24
Peak memory 206468 kb
Host smart-792b922d-c8cf-4ab0-8999-e07d32542f4e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1019735063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.1019735063
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.492218535
Short name T2029
Test name
Test status
Simulation time 182424824 ps
CPU time 0.84 seconds
Started Jun 28 06:11:26 PM PDT 24
Finished Jun 28 06:11:28 PM PDT 24
Peak memory 206196 kb
Host smart-01c84134-3934-424e-8834-3fd0e0a5526f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49221
8535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.492218535
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.1030172454
Short name T1114
Test name
Test status
Simulation time 195436765 ps
CPU time 0.85 seconds
Started Jun 28 06:11:17 PM PDT 24
Finished Jun 28 06:11:19 PM PDT 24
Peak memory 206196 kb
Host smart-304e6483-d4a2-4624-ae8a-126e51b92522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10301
72454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.1030172454
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.3636774162
Short name T796
Test name
Test status
Simulation time 275702756 ps
CPU time 1.06 seconds
Started Jun 28 06:11:22 PM PDT 24
Finished Jun 28 06:11:25 PM PDT 24
Peak memory 206192 kb
Host smart-bbabeb83-3770-421a-8530-a362418e75ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36367
74162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.3636774162
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.1866537025
Short name T94
Test name
Test status
Simulation time 625605047 ps
CPU time 1.65 seconds
Started Jun 28 06:11:19 PM PDT 24
Finished Jun 28 06:11:23 PM PDT 24
Peak memory 206312 kb
Host smart-e505541a-cce7-481f-95d7-bb3195336ec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18665
37025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.1866537025
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.3663187773
Short name T582
Test name
Test status
Simulation time 371235475 ps
CPU time 1.14 seconds
Started Jun 28 06:11:18 PM PDT 24
Finished Jun 28 06:11:21 PM PDT 24
Peak memory 206196 kb
Host smart-a106dffb-32c5-4ce3-a6c1-20282b7f96b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36631
87773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.3663187773
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.386802466
Short name T2158
Test name
Test status
Simulation time 139627119 ps
CPU time 0.75 seconds
Started Jun 28 06:11:19 PM PDT 24
Finished Jun 28 06:11:23 PM PDT 24
Peak memory 206184 kb
Host smart-a1aef0c6-c2ca-4324-81c0-ad4599ce070c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38680
2466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.386802466
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.4158842714
Short name T1121
Test name
Test status
Simulation time 45165805 ps
CPU time 0.66 seconds
Started Jun 28 06:11:20 PM PDT 24
Finished Jun 28 06:11:23 PM PDT 24
Peak memory 206184 kb
Host smart-1efd2e82-dd65-43e9-b7d4-88c6a98ca540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41588
42714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.4158842714
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.1072489795
Short name T1544
Test name
Test status
Simulation time 932602991 ps
CPU time 2.24 seconds
Started Jun 28 06:11:20 PM PDT 24
Finished Jun 28 06:11:25 PM PDT 24
Peak memory 206336 kb
Host smart-9da8dd6a-9709-4661-a6cf-c94a1e4ca2b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10724
89795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.1072489795
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.2299762943
Short name T606
Test name
Test status
Simulation time 170883048 ps
CPU time 1.36 seconds
Started Jun 28 06:11:26 PM PDT 24
Finished Jun 28 06:11:29 PM PDT 24
Peak memory 206280 kb
Host smart-1b11d3f6-c50a-4dcb-ab9a-b2e96c166750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22997
62943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.2299762943
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.129800568
Short name T1316
Test name
Test status
Simulation time 215796983 ps
CPU time 0.86 seconds
Started Jun 28 06:11:18 PM PDT 24
Finished Jun 28 06:11:21 PM PDT 24
Peak memory 206172 kb
Host smart-4e97db4f-e2c8-4c38-929a-981db87757d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12980
0568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.129800568
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.3686667100
Short name T2339
Test name
Test status
Simulation time 150831492 ps
CPU time 0.79 seconds
Started Jun 28 06:11:26 PM PDT 24
Finished Jun 28 06:11:29 PM PDT 24
Peak memory 206176 kb
Host smart-17384f0b-a3a2-47fa-85a3-5a36a9f8216c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36866
67100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.3686667100
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.646233707
Short name T2222
Test name
Test status
Simulation time 184801763 ps
CPU time 0.9 seconds
Started Jun 28 06:11:17 PM PDT 24
Finished Jun 28 06:11:19 PM PDT 24
Peak memory 206208 kb
Host smart-ce61db1d-ace2-43ae-851f-7bf9c521318e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64623
3707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.646233707
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_invalid_sync.2261401827
Short name T686
Test name
Test status
Simulation time 5888080363 ps
CPU time 44.56 seconds
Started Jun 28 06:11:23 PM PDT 24
Finished Jun 28 06:12:09 PM PDT 24
Peak memory 206348 kb
Host smart-32b1824d-28e4-41b2-a2eb-6874606f6356
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2261401827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.2261401827
Directory /workspace/19.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.2186768033
Short name T1275
Test name
Test status
Simulation time 225986328 ps
CPU time 0.96 seconds
Started Jun 28 06:11:18 PM PDT 24
Finished Jun 28 06:11:20 PM PDT 24
Peak memory 206116 kb
Host smart-cd115208-884a-4545-a3d0-0b6020f1c9a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21867
68033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.2186768033
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.207502647
Short name T1251
Test name
Test status
Simulation time 23319353760 ps
CPU time 22.89 seconds
Started Jun 28 06:11:27 PM PDT 24
Finished Jun 28 06:11:52 PM PDT 24
Peak memory 206312 kb
Host smart-c9674736-545e-4743-beaa-97603bbb1e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20750
2647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.207502647
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.1975305282
Short name T1407
Test name
Test status
Simulation time 3357396471 ps
CPU time 3.82 seconds
Started Jun 28 06:11:26 PM PDT 24
Finished Jun 28 06:11:32 PM PDT 24
Peak memory 206248 kb
Host smart-5ee7b06f-73bc-42d2-a8bd-5ad211edc165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19753
05282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.1975305282
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.25464061
Short name T681
Test name
Test status
Simulation time 7128062739 ps
CPU time 65.47 seconds
Started Jun 28 06:11:18 PM PDT 24
Finished Jun 28 06:12:25 PM PDT 24
Peak memory 206400 kb
Host smart-70a839c7-9587-4bd2-aecd-a0b9b83b6088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25464
061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.25464061
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.679577967
Short name T596
Test name
Test status
Simulation time 5557502543 ps
CPU time 40.1 seconds
Started Jun 28 06:11:19 PM PDT 24
Finished Jun 28 06:12:02 PM PDT 24
Peak memory 206496 kb
Host smart-d0070683-6529-469f-b5b2-4d6647ed0b82
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=679577967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.679577967
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.477348301
Short name T1182
Test name
Test status
Simulation time 245381923 ps
CPU time 0.98 seconds
Started Jun 28 06:11:20 PM PDT 24
Finished Jun 28 06:11:24 PM PDT 24
Peak memory 206212 kb
Host smart-06ab163c-7da0-479e-9eef-4c2e7870b13a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=477348301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.477348301
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.1962187150
Short name T2426
Test name
Test status
Simulation time 187857244 ps
CPU time 0.86 seconds
Started Jun 28 06:11:23 PM PDT 24
Finished Jun 28 06:11:25 PM PDT 24
Peak memory 206200 kb
Host smart-5cb72b95-6393-4231-9ccb-6552cf6eec1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19621
87150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.1962187150
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.1508583230
Short name T1250
Test name
Test status
Simulation time 5784378978 ps
CPU time 50.98 seconds
Started Jun 28 06:11:28 PM PDT 24
Finished Jun 28 06:12:21 PM PDT 24
Peak memory 206416 kb
Host smart-6e683832-00f3-4cd9-9a00-0aba970dbab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15085
83230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.1508583230
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.2423544221
Short name T1381
Test name
Test status
Simulation time 5292555069 ps
CPU time 149.65 seconds
Started Jun 28 06:11:28 PM PDT 24
Finished Jun 28 06:14:00 PM PDT 24
Peak memory 206456 kb
Host smart-e0a8fcb6-3554-4fba-adb7-67e3b6cdc2ab
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2423544221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.2423544221
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.3038757853
Short name T1412
Test name
Test status
Simulation time 171235951 ps
CPU time 0.81 seconds
Started Jun 28 06:11:19 PM PDT 24
Finished Jun 28 06:11:22 PM PDT 24
Peak memory 206216 kb
Host smart-f944c60b-1164-467e-b95c-d67968bb33a2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3038757853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.3038757853
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.3287191150
Short name T324
Test name
Test status
Simulation time 158768871 ps
CPU time 0.78 seconds
Started Jun 28 06:11:27 PM PDT 24
Finished Jun 28 06:11:30 PM PDT 24
Peak memory 206200 kb
Host smart-e5779e74-7d75-4576-b6b9-024e1ea65580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32871
91150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.3287191150
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.2627189685
Short name T125
Test name
Test status
Simulation time 215252757 ps
CPU time 0.86 seconds
Started Jun 28 06:11:20 PM PDT 24
Finished Jun 28 06:11:24 PM PDT 24
Peak memory 206152 kb
Host smart-d8baa764-ec79-4306-896d-fe3c8bd780bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26271
89685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.2627189685
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.2584618622
Short name T1253
Test name
Test status
Simulation time 175143880 ps
CPU time 0.85 seconds
Started Jun 28 06:11:27 PM PDT 24
Finished Jun 28 06:11:30 PM PDT 24
Peak memory 206064 kb
Host smart-c2b980c1-3932-4ed3-a096-ecaf1df77627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25846
18622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.2584618622
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.4091221460
Short name T1324
Test name
Test status
Simulation time 173367168 ps
CPU time 0.82 seconds
Started Jun 28 06:11:22 PM PDT 24
Finished Jun 28 06:11:25 PM PDT 24
Peak memory 206192 kb
Host smart-3c9891be-6cf3-4d3d-bc04-22b8b3789954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40912
21460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.4091221460
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.284670376
Short name T1464
Test name
Test status
Simulation time 184526018 ps
CPU time 0.86 seconds
Started Jun 28 06:11:23 PM PDT 24
Finished Jun 28 06:11:25 PM PDT 24
Peak memory 206192 kb
Host smart-735e1b48-99f7-4c18-a40b-1f5decf14092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28467
0376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.284670376
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.1493820746
Short name T170
Test name
Test status
Simulation time 149282639 ps
CPU time 0.77 seconds
Started Jun 28 06:11:27 PM PDT 24
Finished Jun 28 06:11:30 PM PDT 24
Peak memory 206016 kb
Host smart-a1f4a8db-5289-4fd3-ab34-f202bbabdfef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14938
20746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.1493820746
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.1829463279
Short name T2234
Test name
Test status
Simulation time 226300250 ps
CPU time 0.94 seconds
Started Jun 28 06:11:28 PM PDT 24
Finished Jun 28 06:11:31 PM PDT 24
Peak memory 206212 kb
Host smart-c0b1a47e-582c-4d84-88bb-a8961822b52f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1829463279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.1829463279
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.1148607482
Short name T1042
Test name
Test status
Simulation time 180094432 ps
CPU time 0.81 seconds
Started Jun 28 06:11:30 PM PDT 24
Finished Jun 28 06:11:34 PM PDT 24
Peak memory 206208 kb
Host smart-b4ba1936-327a-4ad2-9763-92c4e6676a3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11486
07482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.1148607482
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.1062633659
Short name T31
Test name
Test status
Simulation time 47685356 ps
CPU time 0.68 seconds
Started Jun 28 06:11:28 PM PDT 24
Finished Jun 28 06:11:31 PM PDT 24
Peak memory 206180 kb
Host smart-f97e12cd-2c11-4c86-aba1-36d5b50f2fa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10626
33659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.1062633659
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.533490272
Short name T1647
Test name
Test status
Simulation time 182615218 ps
CPU time 0.85 seconds
Started Jun 28 06:11:26 PM PDT 24
Finished Jun 28 06:11:29 PM PDT 24
Peak memory 206192 kb
Host smart-73a4fda6-51f7-4928-bd56-6a3065a86b08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53349
0272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.533490272
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.855722617
Short name T1147
Test name
Test status
Simulation time 252722241 ps
CPU time 0.99 seconds
Started Jun 28 06:11:30 PM PDT 24
Finished Jun 28 06:11:34 PM PDT 24
Peak memory 206200 kb
Host smart-23cce332-f40f-4562-81d3-dccb320d3b58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85572
2617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.855722617
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.729522872
Short name T548
Test name
Test status
Simulation time 190608706 ps
CPU time 0.85 seconds
Started Jun 28 06:11:28 PM PDT 24
Finished Jun 28 06:11:31 PM PDT 24
Peak memory 206208 kb
Host smart-cc7f215d-54e5-49ed-978a-6032a94dfdaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72952
2872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.729522872
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.1203060285
Short name T1054
Test name
Test status
Simulation time 163914988 ps
CPU time 0.77 seconds
Started Jun 28 06:11:29 PM PDT 24
Finished Jun 28 06:11:32 PM PDT 24
Peak memory 206204 kb
Host smart-fe07a8bb-67f8-477f-9c60-660a76cc8c23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12030
60285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.1203060285
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.960429822
Short name T352
Test name
Test status
Simulation time 156649588 ps
CPU time 0.77 seconds
Started Jun 28 06:11:28 PM PDT 24
Finished Jun 28 06:11:31 PM PDT 24
Peak memory 206196 kb
Host smart-3ff83cdf-2784-4d12-a4bf-86f06c9b0ac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96042
9822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.960429822
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.2374320457
Short name T861
Test name
Test status
Simulation time 200840641 ps
CPU time 0.9 seconds
Started Jun 28 06:11:27 PM PDT 24
Finished Jun 28 06:11:30 PM PDT 24
Peak memory 206196 kb
Host smart-044d6ce2-7224-4024-949a-050b92a483c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23743
20457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.2374320457
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.1277120413
Short name T2299
Test name
Test status
Simulation time 166570748 ps
CPU time 0.83 seconds
Started Jun 28 06:11:27 PM PDT 24
Finished Jun 28 06:11:30 PM PDT 24
Peak memory 206192 kb
Host smart-f3e19c68-a898-4af5-86eb-ae70aa2d9f85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12771
20413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.1277120413
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.811213920
Short name T1560
Test name
Test status
Simulation time 205497767 ps
CPU time 0.95 seconds
Started Jun 28 06:11:29 PM PDT 24
Finished Jun 28 06:11:33 PM PDT 24
Peak memory 206188 kb
Host smart-38ec4198-adb6-40eb-b731-3a2efa62d7e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81121
3920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.811213920
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.1253019672
Short name T2584
Test name
Test status
Simulation time 5064879048 ps
CPU time 46.17 seconds
Started Jun 28 06:11:29 PM PDT 24
Finished Jun 28 06:12:18 PM PDT 24
Peak memory 206364 kb
Host smart-258b0a4c-076a-4feb-b845-fce0ef60c5b1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1253019672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.1253019672
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.1148470900
Short name T2110
Test name
Test status
Simulation time 164612060 ps
CPU time 0.83 seconds
Started Jun 28 06:11:31 PM PDT 24
Finished Jun 28 06:11:35 PM PDT 24
Peak memory 206220 kb
Host smart-e0115fc1-8bbf-4b69-ae96-2e187cc169ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11484
70900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.1148470900
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.3933838946
Short name T626
Test name
Test status
Simulation time 156015835 ps
CPU time 0.81 seconds
Started Jun 28 06:11:31 PM PDT 24
Finished Jun 28 06:11:35 PM PDT 24
Peak memory 206192 kb
Host smart-c1a70b10-decc-4024-b7c1-cf5fa4a2519f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39338
38946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.3933838946
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.334500575
Short name T367
Test name
Test status
Simulation time 3759710267 ps
CPU time 37.33 seconds
Started Jun 28 06:11:31 PM PDT 24
Finished Jun 28 06:12:12 PM PDT 24
Peak memory 206380 kb
Host smart-4c908e3d-d1e1-43f0-8d34-33217b1b02db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33450
0575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.334500575
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.3177426868
Short name T2458
Test name
Test status
Simulation time 42496059 ps
CPU time 0.69 seconds
Started Jun 28 06:08:55 PM PDT 24
Finished Jun 28 06:09:00 PM PDT 24
Peak memory 206188 kb
Host smart-ebb98fbe-d60f-45d3-8482-f503b63ca56a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3177426868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.3177426868
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.1423750498
Short name T2455
Test name
Test status
Simulation time 4047243102 ps
CPU time 4.5 seconds
Started Jun 28 06:08:41 PM PDT 24
Finished Jun 28 06:08:48 PM PDT 24
Peak memory 206436 kb
Host smart-823b05e6-5de0-428f-bed6-57f11a7c082a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1423750498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.1423750498
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.911285849
Short name T1219
Test name
Test status
Simulation time 13350627114 ps
CPU time 11.58 seconds
Started Jun 28 06:08:47 PM PDT 24
Finished Jun 28 06:09:01 PM PDT 24
Peak memory 206492 kb
Host smart-fdb79577-472d-47b1-aa59-b757ae33c327
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=911285849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.911285849
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.1771291370
Short name T1982
Test name
Test status
Simulation time 23411936952 ps
CPU time 21.98 seconds
Started Jun 28 06:08:48 PM PDT 24
Finished Jun 28 06:09:13 PM PDT 24
Peak memory 206384 kb
Host smart-680c936f-f4ef-4ed1-90f5-a320c9a78a46
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1771291370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.1771291370
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.249129707
Short name T491
Test name
Test status
Simulation time 193262103 ps
CPU time 0.82 seconds
Started Jun 28 06:08:47 PM PDT 24
Finished Jun 28 06:08:51 PM PDT 24
Peak memory 206208 kb
Host smart-7cf677b6-70f2-4085-879f-dae5732a9bc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24912
9707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.249129707
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.4005854385
Short name T50
Test name
Test status
Simulation time 145943864 ps
CPU time 0.8 seconds
Started Jun 28 06:08:46 PM PDT 24
Finished Jun 28 06:08:49 PM PDT 24
Peak memory 206208 kb
Host smart-6dc8e743-1f62-47cc-84be-59bef6bd916a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40058
54385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.4005854385
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.4294863289
Short name T58
Test name
Test status
Simulation time 140486230 ps
CPU time 0.8 seconds
Started Jun 28 06:08:50 PM PDT 24
Finished Jun 28 06:08:54 PM PDT 24
Peak memory 206188 kb
Host smart-82a8408e-bd58-4105-bacd-05b90eccf2be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42948
63289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.4294863289
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.4249495005
Short name T1723
Test name
Test status
Simulation time 168080997 ps
CPU time 0.85 seconds
Started Jun 28 06:08:47 PM PDT 24
Finished Jun 28 06:08:50 PM PDT 24
Peak memory 206136 kb
Host smart-bd714996-92fe-4e1d-9a4c-b3877d3fda73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42494
95005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.4249495005
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.2046661537
Short name T1305
Test name
Test status
Simulation time 596479664 ps
CPU time 1.69 seconds
Started Jun 28 06:08:48 PM PDT 24
Finished Jun 28 06:08:52 PM PDT 24
Peak memory 206268 kb
Host smart-91695ec0-8f00-4012-89ac-9589f4433111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20466
61537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.2046661537
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.2910730798
Short name T176
Test name
Test status
Simulation time 1517369815 ps
CPU time 3.05 seconds
Started Jun 28 06:08:47 PM PDT 24
Finished Jun 28 06:08:53 PM PDT 24
Peak memory 206224 kb
Host smart-0de8728c-92fa-453f-bab8-436ef76d133c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29107
30798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.2910730798
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.927160235
Short name T2344
Test name
Test status
Simulation time 20881218598 ps
CPU time 34.85 seconds
Started Jun 28 06:08:48 PM PDT 24
Finished Jun 28 06:09:25 PM PDT 24
Peak memory 206416 kb
Host smart-188915f2-b124-421b-bfbe-c77cf48f7f39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92716
0235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.927160235
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.1844843910
Short name T547
Test name
Test status
Simulation time 388657598 ps
CPU time 1.23 seconds
Started Jun 28 06:08:49 PM PDT 24
Finished Jun 28 06:08:53 PM PDT 24
Peak memory 206216 kb
Host smart-08d4f022-ab56-48bd-b58e-a0d1ac54bddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18448
43910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.1844843910
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.2567954085
Short name T1574
Test name
Test status
Simulation time 147107556 ps
CPU time 0.78 seconds
Started Jun 28 06:08:49 PM PDT 24
Finished Jun 28 06:08:52 PM PDT 24
Peak memory 206196 kb
Host smart-fc7400eb-d3a8-4bda-b6c9-8c09cf337410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25679
54085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.2567954085
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.2999737665
Short name T2166
Test name
Test status
Simulation time 52256678 ps
CPU time 0.68 seconds
Started Jun 28 06:08:49 PM PDT 24
Finished Jun 28 06:08:52 PM PDT 24
Peak memory 206200 kb
Host smart-71964d9a-0b1b-49d8-b3f8-b73d5934a2e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29997
37665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.2999737665
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.4209899366
Short name T1629
Test name
Test status
Simulation time 962834858 ps
CPU time 2.16 seconds
Started Jun 28 06:08:47 PM PDT 24
Finished Jun 28 06:08:51 PM PDT 24
Peak memory 206244 kb
Host smart-5efbdf32-2cb1-4de5-b4ea-06ad303db12b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42098
99366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.4209899366
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.2761372816
Short name T2187
Test name
Test status
Simulation time 292060505 ps
CPU time 1.74 seconds
Started Jun 28 06:08:43 PM PDT 24
Finished Jun 28 06:08:48 PM PDT 24
Peak memory 206284 kb
Host smart-d71bb697-00a3-4d47-adde-2afe0b7af133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27613
72816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.2761372816
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.1876707612
Short name T649
Test name
Test status
Simulation time 217832864 ps
CPU time 0.88 seconds
Started Jun 28 06:08:41 PM PDT 24
Finished Jun 28 06:08:46 PM PDT 24
Peak memory 206200 kb
Host smart-6d72d82c-a6ee-4548-9a13-6adf8bff1e97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18767
07612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.1876707612
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.3494739823
Short name T1752
Test name
Test status
Simulation time 139396020 ps
CPU time 0.79 seconds
Started Jun 28 06:08:39 PM PDT 24
Finished Jun 28 06:08:41 PM PDT 24
Peak memory 206208 kb
Host smart-b15f3229-8cdf-4af9-a038-dffc67e75039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34947
39823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.3494739823
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.1965555482
Short name T1878
Test name
Test status
Simulation time 229613861 ps
CPU time 0.91 seconds
Started Jun 28 06:08:39 PM PDT 24
Finished Jun 28 06:08:42 PM PDT 24
Peak memory 206212 kb
Host smart-24e1fc44-0b1d-4871-899c-8d6c2f3995de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19655
55482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.1965555482
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.3876318061
Short name T1089
Test name
Test status
Simulation time 165480680 ps
CPU time 0.81 seconds
Started Jun 28 06:08:39 PM PDT 24
Finished Jun 28 06:08:42 PM PDT 24
Peak memory 206196 kb
Host smart-f20e9012-6135-4e7b-86aa-88d119fc9476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38763
18061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.3876318061
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.3329900311
Short name T1577
Test name
Test status
Simulation time 23269561269 ps
CPU time 21.51 seconds
Started Jun 28 06:08:40 PM PDT 24
Finished Jun 28 06:09:04 PM PDT 24
Peak memory 206320 kb
Host smart-201d71bb-4d82-4137-886e-7b2188f5400b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33299
00311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.3329900311
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.1886760952
Short name T2489
Test name
Test status
Simulation time 3325990841 ps
CPU time 3.54 seconds
Started Jun 28 06:08:41 PM PDT 24
Finished Jun 28 06:08:48 PM PDT 24
Peak memory 206232 kb
Host smart-4d5fef9f-a17a-4df9-9eec-de4b147c5d9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18867
60952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.1886760952
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.4051482920
Short name T1712
Test name
Test status
Simulation time 7762934058 ps
CPU time 218.76 seconds
Started Jun 28 06:08:40 PM PDT 24
Finished Jun 28 06:12:22 PM PDT 24
Peak memory 206432 kb
Host smart-a172f1d2-06de-4321-be79-2c2b517ad20a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40514
82920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.4051482920
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.1908234150
Short name T1855
Test name
Test status
Simulation time 3467599909 ps
CPU time 31.41 seconds
Started Jun 28 06:08:39 PM PDT 24
Finished Jun 28 06:09:13 PM PDT 24
Peak memory 206416 kb
Host smart-7c2cbd25-04cb-4585-9d05-c6a36815d1c8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1908234150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.1908234150
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.861197343
Short name T1321
Test name
Test status
Simulation time 281027987 ps
CPU time 0.98 seconds
Started Jun 28 06:08:43 PM PDT 24
Finished Jun 28 06:08:47 PM PDT 24
Peak memory 206216 kb
Host smart-c1c5f177-782d-4c4b-a47b-2f725a62267a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=861197343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.861197343
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.653456447
Short name T2317
Test name
Test status
Simulation time 187016372 ps
CPU time 0.92 seconds
Started Jun 28 06:08:39 PM PDT 24
Finished Jun 28 06:08:41 PM PDT 24
Peak memory 206208 kb
Host smart-2ddb8be3-252e-4963-a44d-4e1b45b2576a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65345
6447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.653456447
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.189131333
Short name T2322
Test name
Test status
Simulation time 4478594283 ps
CPU time 31.57 seconds
Started Jun 28 06:08:40 PM PDT 24
Finished Jun 28 06:09:13 PM PDT 24
Peak memory 206404 kb
Host smart-692042ea-dd58-44a8-9637-e37b8d080941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18913
1333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.189131333
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.4248996934
Short name T408
Test name
Test status
Simulation time 3365937648 ps
CPU time 23.94 seconds
Started Jun 28 06:08:41 PM PDT 24
Finished Jun 28 06:09:09 PM PDT 24
Peak memory 206476 kb
Host smart-2080415c-848d-45ab-acd8-97541f02455f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4248996934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.4248996934
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.755028924
Short name T652
Test name
Test status
Simulation time 170530591 ps
CPU time 0.82 seconds
Started Jun 28 06:08:40 PM PDT 24
Finished Jun 28 06:08:44 PM PDT 24
Peak memory 206192 kb
Host smart-98788691-a093-4ac2-ae7a-9988532f8f9c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=755028924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.755028924
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.3681838006
Short name T490
Test name
Test status
Simulation time 154771135 ps
CPU time 0.78 seconds
Started Jun 28 06:08:40 PM PDT 24
Finished Jun 28 06:08:44 PM PDT 24
Peak memory 206212 kb
Host smart-4069c3b4-9873-44f2-93bd-5b6bc5ee63e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36818
38006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.3681838006
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.808523092
Short name T2410
Test name
Test status
Simulation time 239547108 ps
CPU time 0.9 seconds
Started Jun 28 06:08:42 PM PDT 24
Finished Jun 28 06:08:46 PM PDT 24
Peak memory 206200 kb
Host smart-8fb985e3-796a-4407-b568-7f2b76625822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80852
3092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.808523092
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.819674395
Short name T739
Test name
Test status
Simulation time 164095663 ps
CPU time 0.8 seconds
Started Jun 28 06:08:39 PM PDT 24
Finished Jun 28 06:08:42 PM PDT 24
Peak memory 206216 kb
Host smart-71595fea-d2a0-4065-9f56-57a93099ea7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81967
4395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.819674395
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.1906084113
Short name T717
Test name
Test status
Simulation time 180001977 ps
CPU time 0.8 seconds
Started Jun 28 06:08:45 PM PDT 24
Finished Jun 28 06:08:48 PM PDT 24
Peak memory 206160 kb
Host smart-91898b21-cf2f-4349-9929-fdc2fb7fa804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19060
84113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.1906084113
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.941587376
Short name T154
Test name
Test status
Simulation time 174439052 ps
CPU time 0.83 seconds
Started Jun 28 06:08:41 PM PDT 24
Finished Jun 28 06:08:46 PM PDT 24
Peak memory 206216 kb
Host smart-da1e25b5-c0ed-41ff-baf5-0d3bea66d44d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94158
7376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.941587376
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.1692315892
Short name T1978
Test name
Test status
Simulation time 209837054 ps
CPU time 0.89 seconds
Started Jun 28 06:08:41 PM PDT 24
Finished Jun 28 06:08:46 PM PDT 24
Peak memory 206036 kb
Host smart-fbcc0bdd-9a67-4e23-9cbb-ff5dc3d0d46e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1692315892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.1692315892
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.3080914354
Short name T481
Test name
Test status
Simulation time 200158785 ps
CPU time 0.89 seconds
Started Jun 28 06:08:42 PM PDT 24
Finished Jun 28 06:08:47 PM PDT 24
Peak memory 206196 kb
Host smart-01407697-a246-4554-b69f-5aec1d2115f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30809
14354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.3080914354
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.1611806447
Short name T1914
Test name
Test status
Simulation time 146356875 ps
CPU time 0.77 seconds
Started Jun 28 06:08:43 PM PDT 24
Finished Jun 28 06:08:47 PM PDT 24
Peak memory 206192 kb
Host smart-c2c9f266-5f31-4bd5-b626-35bd3066ac1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16118
06447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.1611806447
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.3170217349
Short name T1209
Test name
Test status
Simulation time 36853260 ps
CPU time 0.67 seconds
Started Jun 28 06:08:46 PM PDT 24
Finished Jun 28 06:08:49 PM PDT 24
Peak memory 206172 kb
Host smart-ddf080d7-e73f-4726-8766-820cefad0bc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31702
17349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.3170217349
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.3418442729
Short name T2176
Test name
Test status
Simulation time 6480705551 ps
CPU time 14.78 seconds
Started Jun 28 06:08:47 PM PDT 24
Finished Jun 28 06:09:04 PM PDT 24
Peak memory 206436 kb
Host smart-5b676417-15cf-4a18-ab25-d54fd6d3249d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34184
42729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.3418442729
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.4271073882
Short name T645
Test name
Test status
Simulation time 158707103 ps
CPU time 0.81 seconds
Started Jun 28 06:08:48 PM PDT 24
Finished Jun 28 06:08:52 PM PDT 24
Peak memory 206096 kb
Host smart-5fdb39d9-ff5b-4325-ba41-2fdb6719a452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42710
73882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.4271073882
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.405397669
Short name T2565
Test name
Test status
Simulation time 224014494 ps
CPU time 0.92 seconds
Started Jun 28 06:08:43 PM PDT 24
Finished Jun 28 06:08:47 PM PDT 24
Peak memory 206168 kb
Host smart-f6d413b9-fa05-488f-95b1-252786218305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40539
7669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.405397669
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.464393944
Short name T2526
Test name
Test status
Simulation time 10356422397 ps
CPU time 52.51 seconds
Started Jun 28 06:08:49 PM PDT 24
Finished Jun 28 06:09:44 PM PDT 24
Peak memory 206456 kb
Host smart-1b522683-d673-44e4-bb44-3f5dbe4f884b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=464393944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.464393944
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.4198624016
Short name T2490
Test name
Test status
Simulation time 11511430375 ps
CPU time 221.14 seconds
Started Jun 28 06:08:48 PM PDT 24
Finished Jun 28 06:12:32 PM PDT 24
Peak memory 206476 kb
Host smart-16ac7f8a-fd8b-4b88-8579-bf2ed532cd2b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4198624016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.4198624016
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.3330719696
Short name T153
Test name
Test status
Simulation time 21796026546 ps
CPU time 127.56 seconds
Started Jun 28 06:08:48 PM PDT 24
Finished Jun 28 06:10:59 PM PDT 24
Peak memory 206412 kb
Host smart-6f8f0232-3f31-4016-b654-c83f7569f7cd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3330719696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.3330719696
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.2033071657
Short name T766
Test name
Test status
Simulation time 188747728 ps
CPU time 0.89 seconds
Started Jun 28 06:08:42 PM PDT 24
Finished Jun 28 06:08:46 PM PDT 24
Peak memory 206216 kb
Host smart-bf288365-1ec5-49ae-8210-c48e5a4bb735
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20330
71657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.2033071657
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.1779022299
Short name T466
Test name
Test status
Simulation time 142528004 ps
CPU time 0.76 seconds
Started Jun 28 06:08:47 PM PDT 24
Finished Jun 28 06:08:50 PM PDT 24
Peak memory 206200 kb
Host smart-d23b3cff-2db6-4179-9081-7eae5fff9529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17790
22299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.1779022299
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.4103407807
Short name T2448
Test name
Test status
Simulation time 193615954 ps
CPU time 0.91 seconds
Started Jun 28 06:08:49 PM PDT 24
Finished Jun 28 06:08:52 PM PDT 24
Peak memory 205816 kb
Host smart-51279b97-b24c-472a-b97d-4a806fffcc50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41034
07807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.4103407807
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.4075993912
Short name T72
Test name
Test status
Simulation time 195915179 ps
CPU time 0.88 seconds
Started Jun 28 06:08:48 PM PDT 24
Finished Jun 28 06:08:52 PM PDT 24
Peak memory 206200 kb
Host smart-628d3d20-e234-4655-810e-d6d9c07413e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40759
93912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.4075993912
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.2944216560
Short name T45
Test name
Test status
Simulation time 420194478 ps
CPU time 1.28 seconds
Started Jun 28 06:08:48 PM PDT 24
Finished Jun 28 06:08:51 PM PDT 24
Peak memory 206200 kb
Host smart-073f352d-59dd-4d84-ac55-feb7fa343b7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29442
16560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.2944216560
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.3385550916
Short name T724
Test name
Test status
Simulation time 296797782 ps
CPU time 1.03 seconds
Started Jun 28 06:08:48 PM PDT 24
Finished Jun 28 06:08:51 PM PDT 24
Peak memory 206196 kb
Host smart-f57d118c-3767-4478-a404-7e2f58a8d629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33855
50916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.3385550916
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.1293823339
Short name T1510
Test name
Test status
Simulation time 152421400 ps
CPU time 0.76 seconds
Started Jun 28 06:08:41 PM PDT 24
Finished Jun 28 06:08:45 PM PDT 24
Peak memory 206192 kb
Host smart-162d62fc-292c-4cf7-ab16-8e6c32bce769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12938
23339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.1293823339
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.1748949561
Short name T650
Test name
Test status
Simulation time 155109486 ps
CPU time 0.78 seconds
Started Jun 28 06:08:47 PM PDT 24
Finished Jun 28 06:08:50 PM PDT 24
Peak memory 206184 kb
Host smart-c80c1222-6db6-4131-87a5-cfe3837e60a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17489
49561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.1748949561
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.29169564
Short name T2598
Test name
Test status
Simulation time 237955504 ps
CPU time 0.89 seconds
Started Jun 28 06:08:48 PM PDT 24
Finished Jun 28 06:08:51 PM PDT 24
Peak memory 206184 kb
Host smart-b6ac0094-05b7-467c-be8f-07f3fcdc3c71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29169
564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.29169564
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.918975712
Short name T2400
Test name
Test status
Simulation time 7144722688 ps
CPU time 53.14 seconds
Started Jun 28 06:08:42 PM PDT 24
Finished Jun 28 06:09:38 PM PDT 24
Peak memory 206408 kb
Host smart-1dff8314-7139-4224-a6f3-a0e882d5ab0c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=918975712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.918975712
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.2041660883
Short name T1105
Test name
Test status
Simulation time 170932546 ps
CPU time 0.83 seconds
Started Jun 28 06:08:47 PM PDT 24
Finished Jun 28 06:08:50 PM PDT 24
Peak memory 206196 kb
Host smart-59883eb6-afb8-4153-844d-563f03b082e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20416
60883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.2041660883
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.516029220
Short name T2267
Test name
Test status
Simulation time 224113822 ps
CPU time 0.94 seconds
Started Jun 28 06:08:48 PM PDT 24
Finished Jun 28 06:08:52 PM PDT 24
Peak memory 206112 kb
Host smart-4f8581c8-56f2-490b-94be-ae5fab8feab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51602
9220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.516029220
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.3058520853
Short name T1844
Test name
Test status
Simulation time 4346615555 ps
CPU time 30.43 seconds
Started Jun 28 06:08:54 PM PDT 24
Finished Jun 28 06:09:29 PM PDT 24
Peak memory 206388 kb
Host smart-613bc228-d3b3-4437-866b-1c1e887f3ff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30585
20853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.3058520853
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.2586396005
Short name T1586
Test name
Test status
Simulation time 47880697 ps
CPU time 0.65 seconds
Started Jun 28 06:11:41 PM PDT 24
Finished Jun 28 06:11:43 PM PDT 24
Peak memory 206196 kb
Host smart-e0789cbb-5b20-4f3f-b150-6e8a9dac6754
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2586396005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.2586396005
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.2743275500
Short name T2474
Test name
Test status
Simulation time 3717460108 ps
CPU time 4.8 seconds
Started Jun 28 06:11:28 PM PDT 24
Finished Jun 28 06:11:35 PM PDT 24
Peak memory 206352 kb
Host smart-9f1f83f7-ef99-44db-87b7-349a98a83f91
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2743275500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.2743275500
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.694991636
Short name T769
Test name
Test status
Simulation time 13413249633 ps
CPU time 13.95 seconds
Started Jun 28 06:11:29 PM PDT 24
Finished Jun 28 06:11:46 PM PDT 24
Peak memory 206504 kb
Host smart-7ca7abdc-327b-4716-a153-5bdfaf659b61
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=694991636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.694991636
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.2162069086
Short name T2084
Test name
Test status
Simulation time 23367971767 ps
CPU time 23.49 seconds
Started Jun 28 06:11:29 PM PDT 24
Finished Jun 28 06:11:56 PM PDT 24
Peak memory 206312 kb
Host smart-3ed32ea2-9c8d-47fa-95cc-7c2360c4ba99
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2162069086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.2162069086
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.621018062
Short name T1386
Test name
Test status
Simulation time 160447337 ps
CPU time 0.86 seconds
Started Jun 28 06:11:31 PM PDT 24
Finished Jun 28 06:11:35 PM PDT 24
Peak memory 206212 kb
Host smart-fbf96517-76d8-4326-b2e8-af5697c0251f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62101
8062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.621018062
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.3909642493
Short name T1468
Test name
Test status
Simulation time 179635104 ps
CPU time 0.8 seconds
Started Jun 28 06:11:30 PM PDT 24
Finished Jun 28 06:11:33 PM PDT 24
Peak memory 206160 kb
Host smart-08780995-6134-419f-9ee1-608c2186fcee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39096
42493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.3909642493
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.1364157550
Short name T744
Test name
Test status
Simulation time 657179159 ps
CPU time 1.81 seconds
Started Jun 28 06:11:29 PM PDT 24
Finished Jun 28 06:11:33 PM PDT 24
Peak memory 206268 kb
Host smart-e87c8fd3-9b8f-424c-a4c6-4037ba17e532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13641
57550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.1364157550
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.1761040268
Short name T2477
Test name
Test status
Simulation time 1073535833 ps
CPU time 2.4 seconds
Started Jun 28 06:11:30 PM PDT 24
Finished Jun 28 06:11:35 PM PDT 24
Peak memory 206308 kb
Host smart-fa810d2c-458d-420f-93d2-ccd1f1dd1d0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17610
40268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.1761040268
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.3640929555
Short name T803
Test name
Test status
Simulation time 15959243977 ps
CPU time 34.62 seconds
Started Jun 28 06:11:32 PM PDT 24
Finished Jun 28 06:12:10 PM PDT 24
Peak memory 206424 kb
Host smart-08a1ff55-07a3-4018-a554-1c6e38bd22de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36409
29555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.3640929555
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.2748169870
Short name T972
Test name
Test status
Simulation time 467822723 ps
CPU time 1.38 seconds
Started Jun 28 06:11:31 PM PDT 24
Finished Jun 28 06:11:35 PM PDT 24
Peak memory 206196 kb
Host smart-90452076-94ac-46f9-b9ec-305e737e20d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27481
69870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.2748169870
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.766588177
Short name T1062
Test name
Test status
Simulation time 135623440 ps
CPU time 0.79 seconds
Started Jun 28 06:11:29 PM PDT 24
Finished Jun 28 06:11:32 PM PDT 24
Peak memory 206192 kb
Host smart-3ff5373c-f492-401b-81e9-d9ec8e1bb1dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76658
8177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.766588177
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.3771370403
Short name T2609
Test name
Test status
Simulation time 45446061 ps
CPU time 0.68 seconds
Started Jun 28 06:11:28 PM PDT 24
Finished Jun 28 06:11:30 PM PDT 24
Peak memory 206180 kb
Host smart-2d7ca18b-24fd-4de3-b894-809f882c77a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37713
70403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.3771370403
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.758788115
Short name T834
Test name
Test status
Simulation time 906942509 ps
CPU time 2.11 seconds
Started Jun 28 06:11:31 PM PDT 24
Finished Jun 28 06:11:36 PM PDT 24
Peak memory 206372 kb
Host smart-46c5769a-e8c9-43ea-8974-a1dae135229c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75878
8115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.758788115
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.3803211413
Short name T975
Test name
Test status
Simulation time 357853150 ps
CPU time 2.12 seconds
Started Jun 28 06:11:32 PM PDT 24
Finished Jun 28 06:11:38 PM PDT 24
Peak memory 206288 kb
Host smart-77380075-317f-4728-a908-442ccca16ca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38032
11413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.3803211413
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.53344505
Short name T1052
Test name
Test status
Simulation time 212386975 ps
CPU time 0.89 seconds
Started Jun 28 06:11:28 PM PDT 24
Finished Jun 28 06:11:31 PM PDT 24
Peak memory 206204 kb
Host smart-458865c8-92b8-43e9-8d01-41f3a29b9ec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53344
505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.53344505
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.2722086070
Short name T1520
Test name
Test status
Simulation time 212108907 ps
CPU time 0.86 seconds
Started Jun 28 06:11:30 PM PDT 24
Finished Jun 28 06:11:34 PM PDT 24
Peak memory 206212 kb
Host smart-dbbe78fd-7b49-45f6-be1e-d33fa35fc79f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27220
86070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.2722086070
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.3579192115
Short name T2333
Test name
Test status
Simulation time 206464452 ps
CPU time 0.85 seconds
Started Jun 28 06:11:31 PM PDT 24
Finished Jun 28 06:11:35 PM PDT 24
Peak memory 206188 kb
Host smart-323e5cc5-d831-4159-a94b-c71eda547071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35791
92115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.3579192115
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.3904621228
Short name T600
Test name
Test status
Simulation time 200237961 ps
CPU time 0.84 seconds
Started Jun 28 06:11:31 PM PDT 24
Finished Jun 28 06:11:35 PM PDT 24
Peak memory 206200 kb
Host smart-d267075e-e3da-4001-97e7-bcf10242c288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39046
21228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.3904621228
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.3512624442
Short name T2206
Test name
Test status
Simulation time 23351830388 ps
CPU time 23.81 seconds
Started Jun 28 06:11:31 PM PDT 24
Finished Jun 28 06:11:58 PM PDT 24
Peak memory 206312 kb
Host smart-8d579aaf-645d-4bf7-8fbe-b5e5e11e33f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35126
24442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.3512624442
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.2863019117
Short name T764
Test name
Test status
Simulation time 3277857885 ps
CPU time 3.51 seconds
Started Jun 28 06:11:35 PM PDT 24
Finished Jun 28 06:11:42 PM PDT 24
Peak memory 206256 kb
Host smart-bbcd376b-aa84-4f79-b377-c4b585d23047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28630
19117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.2863019117
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.907825975
Short name T2498
Test name
Test status
Simulation time 7541473558 ps
CPU time 53.25 seconds
Started Jun 28 06:11:32 PM PDT 24
Finished Jun 28 06:12:29 PM PDT 24
Peak memory 206472 kb
Host smart-8d4fcf35-e6f2-47f3-8527-1d834e660ca4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90782
5975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.907825975
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.3054667532
Short name T1287
Test name
Test status
Simulation time 3717541748 ps
CPU time 26.16 seconds
Started Jun 28 06:11:31 PM PDT 24
Finished Jun 28 06:12:01 PM PDT 24
Peak memory 206452 kb
Host smart-fad4f9b2-7924-4dd3-b183-7985fb2b119c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3054667532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.3054667532
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.2309235081
Short name T2265
Test name
Test status
Simulation time 234914915 ps
CPU time 0.92 seconds
Started Jun 28 06:11:32 PM PDT 24
Finished Jun 28 06:11:37 PM PDT 24
Peak memory 206220 kb
Host smart-43fc3a5c-98f1-4edc-b8bf-b15efc143dc8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2309235081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.2309235081
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.4284890079
Short name T522
Test name
Test status
Simulation time 202186957 ps
CPU time 0.9 seconds
Started Jun 28 06:11:32 PM PDT 24
Finished Jun 28 06:11:37 PM PDT 24
Peak memory 206204 kb
Host smart-041278a1-1b27-45cc-9557-4e36a65d6b02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42848
90079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.4284890079
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.1557703739
Short name T2180
Test name
Test status
Simulation time 6339838982 ps
CPU time 171.53 seconds
Started Jun 28 06:11:35 PM PDT 24
Finished Jun 28 06:14:30 PM PDT 24
Peak memory 206464 kb
Host smart-0c446a56-b1fd-47fe-ad6a-210e9143771b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15577
03739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.1557703739
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.185330186
Short name T2557
Test name
Test status
Simulation time 4746927974 ps
CPU time 132.19 seconds
Started Jun 28 06:11:32 PM PDT 24
Finished Jun 28 06:13:48 PM PDT 24
Peak memory 206452 kb
Host smart-b5b51c87-18b1-4a3d-ba3a-05e78d0227ae
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=185330186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.185330186
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.552261560
Short name T702
Test name
Test status
Simulation time 147370252 ps
CPU time 0.79 seconds
Started Jun 28 06:11:32 PM PDT 24
Finished Jun 28 06:11:37 PM PDT 24
Peak memory 206220 kb
Host smart-349d5217-72c8-411e-9779-0d40c6f394ee
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=552261560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.552261560
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.457455435
Short name T2128
Test name
Test status
Simulation time 170203908 ps
CPU time 0.8 seconds
Started Jun 28 06:11:32 PM PDT 24
Finished Jun 28 06:11:36 PM PDT 24
Peak memory 206204 kb
Host smart-c922aa23-d8b9-4118-8d24-477f9f099e73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45745
5435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.457455435
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.3115083827
Short name T991
Test name
Test status
Simulation time 165079374 ps
CPU time 0.78 seconds
Started Jun 28 06:11:30 PM PDT 24
Finished Jun 28 06:11:34 PM PDT 24
Peak memory 206168 kb
Host smart-c2d97a1b-d5a4-46e3-845d-4f8e9d01168b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31150
83827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.3115083827
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.13827670
Short name T759
Test name
Test status
Simulation time 156674205 ps
CPU time 0.9 seconds
Started Jun 28 06:11:34 PM PDT 24
Finished Jun 28 06:11:38 PM PDT 24
Peak memory 206204 kb
Host smart-9cbd2ef3-26a2-41f0-b3cd-a9a866365a4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13827
670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.13827670
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.2950473255
Short name T667
Test name
Test status
Simulation time 159681690 ps
CPU time 0.78 seconds
Started Jun 28 06:11:32 PM PDT 24
Finished Jun 28 06:11:37 PM PDT 24
Peak memory 206168 kb
Host smart-9d25e6cf-b416-4c48-b887-0e727d6e152c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29504
73255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.2950473255
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.2794715375
Short name T544
Test name
Test status
Simulation time 153459463 ps
CPU time 0.8 seconds
Started Jun 28 06:11:33 PM PDT 24
Finished Jun 28 06:11:38 PM PDT 24
Peak memory 206200 kb
Host smart-c540b200-1e7b-4465-ad2a-5b54d550a559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27947
15375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.2794715375
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.3763487930
Short name T1164
Test name
Test status
Simulation time 236154497 ps
CPU time 0.92 seconds
Started Jun 28 06:11:36 PM PDT 24
Finished Jun 28 06:11:39 PM PDT 24
Peak memory 206200 kb
Host smart-18cc37f0-3380-4734-8821-29f907c03003
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3763487930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.3763487930
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.108260696
Short name T1129
Test name
Test status
Simulation time 146688189 ps
CPU time 0.82 seconds
Started Jun 28 06:11:32 PM PDT 24
Finished Jun 28 06:11:36 PM PDT 24
Peak memory 206332 kb
Host smart-a305f6de-86c0-4e66-acdc-7717db0ec913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10826
0696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.108260696
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.2787243005
Short name T1707
Test name
Test status
Simulation time 46254647 ps
CPU time 0.66 seconds
Started Jun 28 06:11:31 PM PDT 24
Finished Jun 28 06:11:35 PM PDT 24
Peak memory 206204 kb
Host smart-a317b3b0-7866-466b-9ac2-833ab0e9ff75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27872
43005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.2787243005
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.306212558
Short name T1245
Test name
Test status
Simulation time 9995749086 ps
CPU time 22.07 seconds
Started Jun 28 06:11:32 PM PDT 24
Finished Jun 28 06:11:58 PM PDT 24
Peak memory 206388 kb
Host smart-59f1ea31-252f-40cd-a4a1-ae3ff0c69d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30621
2558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.306212558
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.1590050810
Short name T629
Test name
Test status
Simulation time 171674623 ps
CPU time 0.86 seconds
Started Jun 28 06:11:34 PM PDT 24
Finished Jun 28 06:11:38 PM PDT 24
Peak memory 206116 kb
Host smart-2284fb2f-09c1-416c-9560-81adce95825b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15900
50810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.1590050810
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.200782983
Short name T387
Test name
Test status
Simulation time 197418587 ps
CPU time 0.83 seconds
Started Jun 28 06:11:35 PM PDT 24
Finished Jun 28 06:11:38 PM PDT 24
Peak memory 206208 kb
Host smart-c620c330-282b-4c39-858a-60d638fd9b5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20078
2983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.200782983
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.785405253
Short name T2348
Test name
Test status
Simulation time 197043998 ps
CPU time 0.91 seconds
Started Jun 28 06:11:40 PM PDT 24
Finished Jun 28 06:11:42 PM PDT 24
Peak memory 206176 kb
Host smart-890830d3-3632-4d90-9e40-1e6db8c0c15f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78540
5253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.785405253
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.1228276773
Short name T489
Test name
Test status
Simulation time 142964870 ps
CPU time 0.82 seconds
Started Jun 28 06:11:38 PM PDT 24
Finished Jun 28 06:11:40 PM PDT 24
Peak memory 206040 kb
Host smart-3362256e-daea-4eca-b867-ddb29bfad3b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12282
76773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.1228276773
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.1612114324
Short name T711
Test name
Test status
Simulation time 149788524 ps
CPU time 0.78 seconds
Started Jun 28 06:11:35 PM PDT 24
Finished Jun 28 06:11:39 PM PDT 24
Peak memory 206188 kb
Host smart-3311567d-3fc8-43e7-a50d-45c7e46c024e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16121
14324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.1612114324
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.2211294084
Short name T354
Test name
Test status
Simulation time 151102128 ps
CPU time 0.76 seconds
Started Jun 28 06:11:33 PM PDT 24
Finished Jun 28 06:11:38 PM PDT 24
Peak memory 206188 kb
Host smart-4f61d206-4859-4cd3-b20c-064c8a6b0e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22112
94084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.2211294084
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.746497159
Short name T2331
Test name
Test status
Simulation time 150620958 ps
CPU time 0.78 seconds
Started Jun 28 06:11:36 PM PDT 24
Finished Jun 28 06:11:39 PM PDT 24
Peak memory 206192 kb
Host smart-37efd3bb-8825-4b76-99f1-480195f6084e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74649
7159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.746497159
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.2319039719
Short name T888
Test name
Test status
Simulation time 238282438 ps
CPU time 0.97 seconds
Started Jun 28 06:11:32 PM PDT 24
Finished Jun 28 06:11:37 PM PDT 24
Peak memory 206180 kb
Host smart-b0dec1db-15ae-493e-8e36-254a3045e042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23190
39719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.2319039719
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.3630296268
Short name T2263
Test name
Test status
Simulation time 5013903879 ps
CPU time 35.54 seconds
Started Jun 28 06:11:36 PM PDT 24
Finished Jun 28 06:12:14 PM PDT 24
Peak memory 206380 kb
Host smart-eaad42fd-cf65-4ad5-926d-418289d1ac12
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3630296268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.3630296268
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.4128369888
Short name T527
Test name
Test status
Simulation time 187219680 ps
CPU time 0.89 seconds
Started Jun 28 06:11:38 PM PDT 24
Finished Jun 28 06:11:40 PM PDT 24
Peak memory 205960 kb
Host smart-2627d2b5-5e61-48f0-9230-c5aacf47e8a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41283
69888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.4128369888
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.3977231504
Short name T921
Test name
Test status
Simulation time 226241726 ps
CPU time 0.85 seconds
Started Jun 28 06:11:40 PM PDT 24
Finished Jun 28 06:11:41 PM PDT 24
Peak memory 206188 kb
Host smart-3371e91f-aa17-4050-a596-b342f4507db6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39772
31504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.3977231504
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.2190433474
Short name T1422
Test name
Test status
Simulation time 3823722921 ps
CPU time 105.44 seconds
Started Jun 28 06:11:38 PM PDT 24
Finished Jun 28 06:13:25 PM PDT 24
Peak memory 206348 kb
Host smart-e5a12d0e-2b23-48dd-8900-15d531fcd336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21904
33474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.2190433474
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.1905929679
Short name T1337
Test name
Test status
Simulation time 38095093 ps
CPU time 0.73 seconds
Started Jun 28 06:11:56 PM PDT 24
Finished Jun 28 06:12:03 PM PDT 24
Peak memory 206212 kb
Host smart-249f4d04-8511-44f7-ba79-3da1d9233bdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1905929679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.1905929679
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.3107361783
Short name T2001
Test name
Test status
Simulation time 3989974863 ps
CPU time 4.62 seconds
Started Jun 28 06:11:40 PM PDT 24
Finished Jun 28 06:11:46 PM PDT 24
Peak memory 206272 kb
Host smart-60da9b0c-e292-4cec-9d70-d054328a7e6d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3107361783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.3107361783
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.1637624599
Short name T588
Test name
Test status
Simulation time 13386612212 ps
CPU time 13.5 seconds
Started Jun 28 06:11:32 PM PDT 24
Finished Jun 28 06:11:49 PM PDT 24
Peak memory 206400 kb
Host smart-39662632-0a49-4fea-a94c-0d63d5d69d4f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1637624599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.1637624599
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.2577598071
Short name T2574
Test name
Test status
Simulation time 23493751801 ps
CPU time 28.43 seconds
Started Jun 28 06:11:31 PM PDT 24
Finished Jun 28 06:12:03 PM PDT 24
Peak memory 206368 kb
Host smart-23374437-1138-4093-9a01-45f528897730
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2577598071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.2577598071
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.2610811298
Short name T378
Test name
Test status
Simulation time 169327400 ps
CPU time 0.79 seconds
Started Jun 28 06:11:35 PM PDT 24
Finished Jun 28 06:11:39 PM PDT 24
Peak memory 206160 kb
Host smart-c646b041-ce8f-40a3-ab20-d9f81fb45f42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26108
11298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.2610811298
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.4194672799
Short name T1484
Test name
Test status
Simulation time 191523012 ps
CPU time 0.88 seconds
Started Jun 28 06:11:34 PM PDT 24
Finished Jun 28 06:11:38 PM PDT 24
Peak memory 206116 kb
Host smart-54581fb6-5a87-4129-8562-79d670f3826f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41946
72799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.4194672799
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.3921229997
Short name T1420
Test name
Test status
Simulation time 145694477 ps
CPU time 0.77 seconds
Started Jun 28 06:11:32 PM PDT 24
Finished Jun 28 06:11:37 PM PDT 24
Peak memory 206156 kb
Host smart-354ac3bd-beaa-4d2d-b274-dc0e18f7a835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39212
29997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.3921229997
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.3761864733
Short name T180
Test name
Test status
Simulation time 677272486 ps
CPU time 1.68 seconds
Started Jun 28 06:11:45 PM PDT 24
Finished Jun 28 06:11:49 PM PDT 24
Peak memory 206188 kb
Host smart-750497ed-cd05-46e1-95ea-7006837e0f9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37618
64733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.3761864733
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.3693964739
Short name T1850
Test name
Test status
Simulation time 17232837042 ps
CPU time 37.22 seconds
Started Jun 28 06:11:39 PM PDT 24
Finished Jun 28 06:12:17 PM PDT 24
Peak memory 206496 kb
Host smart-30fc1521-d79a-4219-84d7-c2413c849164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36939
64739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.3693964739
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.1873565794
Short name T1055
Test name
Test status
Simulation time 345255505 ps
CPU time 1.17 seconds
Started Jun 28 06:11:41 PM PDT 24
Finished Jun 28 06:11:43 PM PDT 24
Peak memory 206200 kb
Host smart-8ffb9d8e-56b4-46b3-92f0-bc26a49e4a55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18735
65794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.1873565794
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.3993893715
Short name T1872
Test name
Test status
Simulation time 141315685 ps
CPU time 0.8 seconds
Started Jun 28 06:11:39 PM PDT 24
Finished Jun 28 06:11:41 PM PDT 24
Peak memory 206192 kb
Host smart-f6b26529-4a4b-4058-9a21-389c32fa332e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39938
93715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.3993893715
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.1021337218
Short name T1195
Test name
Test status
Simulation time 63150286 ps
CPU time 0.75 seconds
Started Jun 28 06:11:40 PM PDT 24
Finished Jun 28 06:11:43 PM PDT 24
Peak memory 206180 kb
Host smart-3d059f8e-4e11-4c54-99e3-3e1861bb191e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10213
37218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.1021337218
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.1664074268
Short name T2521
Test name
Test status
Simulation time 958272766 ps
CPU time 2.19 seconds
Started Jun 28 06:11:42 PM PDT 24
Finished Jun 28 06:11:47 PM PDT 24
Peak memory 206296 kb
Host smart-2a39fb96-3d88-4970-87b7-203598c67be1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16640
74268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.1664074268
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.122941934
Short name T2337
Test name
Test status
Simulation time 306156437 ps
CPU time 1.93 seconds
Started Jun 28 06:11:39 PM PDT 24
Finished Jun 28 06:11:42 PM PDT 24
Peak memory 206232 kb
Host smart-076149e7-bfe6-4816-a6fe-3273bd3f78f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12294
1934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.122941934
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.474775850
Short name T1190
Test name
Test status
Simulation time 222713165 ps
CPU time 0.92 seconds
Started Jun 28 06:11:44 PM PDT 24
Finished Jun 28 06:11:47 PM PDT 24
Peak memory 206212 kb
Host smart-e9810bcb-8894-4018-bb4e-9ad541db475f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47477
5850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.474775850
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.2087568522
Short name T403
Test name
Test status
Simulation time 139608820 ps
CPU time 0.77 seconds
Started Jun 28 06:11:49 PM PDT 24
Finished Jun 28 06:11:50 PM PDT 24
Peak memory 206208 kb
Host smart-cfe31bcd-28af-4ce4-b7d7-0b5b97e9d466
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20875
68522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.2087568522
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.3901076531
Short name T472
Test name
Test status
Simulation time 230532323 ps
CPU time 0.93 seconds
Started Jun 28 06:11:43 PM PDT 24
Finished Jun 28 06:11:47 PM PDT 24
Peak memory 206212 kb
Host smart-bee6bcb2-2053-467a-8e7f-7003d3cef959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39010
76531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.3901076531
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.377672308
Short name T937
Test name
Test status
Simulation time 252485803 ps
CPU time 1 seconds
Started Jun 28 06:11:42 PM PDT 24
Finished Jun 28 06:11:46 PM PDT 24
Peak memory 206196 kb
Host smart-fc311de4-950c-41ea-8127-0004b3dbbf9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37767
2308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.377672308
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.760515193
Short name T462
Test name
Test status
Simulation time 23336488617 ps
CPU time 27.38 seconds
Started Jun 28 06:11:42 PM PDT 24
Finished Jun 28 06:12:11 PM PDT 24
Peak memory 206252 kb
Host smart-efdcf22d-f846-47d8-852e-2003459c27a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76051
5193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.760515193
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.1322806406
Short name T2205
Test name
Test status
Simulation time 3308160382 ps
CPU time 3.92 seconds
Started Jun 28 06:11:41 PM PDT 24
Finished Jun 28 06:11:47 PM PDT 24
Peak memory 206256 kb
Host smart-f3c6e011-a035-4fba-b634-2c1dfb5672a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13228
06406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.1322806406
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.2193019412
Short name T1875
Test name
Test status
Simulation time 6489418742 ps
CPU time 176.57 seconds
Started Jun 28 06:11:39 PM PDT 24
Finished Jun 28 06:14:37 PM PDT 24
Peak memory 206468 kb
Host smart-76a66d7f-5aca-407a-b88c-2e028103b474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21930
19412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.2193019412
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.1854260841
Short name T2532
Test name
Test status
Simulation time 3481294888 ps
CPU time 23.97 seconds
Started Jun 28 06:11:41 PM PDT 24
Finished Jun 28 06:12:08 PM PDT 24
Peak memory 206440 kb
Host smart-59645e2a-62ce-4156-a77d-488a751fe9b4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1854260841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.1854260841
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.1783203165
Short name T1539
Test name
Test status
Simulation time 256302390 ps
CPU time 0.94 seconds
Started Jun 28 06:11:44 PM PDT 24
Finished Jun 28 06:11:47 PM PDT 24
Peak memory 206124 kb
Host smart-f4ecdf33-ce12-4e9f-9cd8-81ec696110c9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1783203165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.1783203165
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.703381377
Short name T873
Test name
Test status
Simulation time 214629255 ps
CPU time 0.93 seconds
Started Jun 28 06:11:44 PM PDT 24
Finished Jun 28 06:11:47 PM PDT 24
Peak memory 206176 kb
Host smart-a05bbce0-04eb-44f6-a2b1-81464fd301bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70338
1377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.703381377
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.474268594
Short name T1802
Test name
Test status
Simulation time 3572864022 ps
CPU time 98.51 seconds
Started Jun 28 06:11:43 PM PDT 24
Finished Jun 28 06:13:24 PM PDT 24
Peak memory 206464 kb
Host smart-fc4bc0a9-233e-4338-bfdb-bbdcf5474d51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47426
8594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.474268594
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.3804248347
Short name T2305
Test name
Test status
Simulation time 2912097853 ps
CPU time 80.28 seconds
Started Jun 28 06:11:41 PM PDT 24
Finished Jun 28 06:13:04 PM PDT 24
Peak memory 206444 kb
Host smart-3a26e137-5cc1-4640-818c-77a431ae2aeb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3804248347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.3804248347
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.3692810134
Short name T2428
Test name
Test status
Simulation time 155157549 ps
CPU time 0.77 seconds
Started Jun 28 06:11:41 PM PDT 24
Finished Jun 28 06:11:44 PM PDT 24
Peak memory 206152 kb
Host smart-f82ae148-35b7-41e3-9f9f-f4e1acfb485a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3692810134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.3692810134
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.2027339354
Short name T1041
Test name
Test status
Simulation time 162833085 ps
CPU time 0.89 seconds
Started Jun 28 06:11:44 PM PDT 24
Finished Jun 28 06:11:47 PM PDT 24
Peak memory 206176 kb
Host smart-3bf660f9-2e8e-4b2c-9520-1b31f71e6c99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20273
39354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.2027339354
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.2487877951
Short name T463
Test name
Test status
Simulation time 194396941 ps
CPU time 0.87 seconds
Started Jun 28 06:11:41 PM PDT 24
Finished Jun 28 06:11:44 PM PDT 24
Peak memory 206348 kb
Host smart-4e81b98d-8fd7-4a60-b8ef-6620c6d459eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24878
77951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.2487877951
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.1600768291
Short name T2356
Test name
Test status
Simulation time 150317488 ps
CPU time 0.75 seconds
Started Jun 28 06:11:41 PM PDT 24
Finished Jun 28 06:11:44 PM PDT 24
Peak memory 206132 kb
Host smart-3815de81-cc5b-4c78-9464-f3b936b30e0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16007
68291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.1600768291
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.4142413948
Short name T424
Test name
Test status
Simulation time 191672384 ps
CPU time 0.86 seconds
Started Jun 28 06:11:44 PM PDT 24
Finished Jun 28 06:11:47 PM PDT 24
Peak memory 206076 kb
Host smart-779fed17-b673-451b-a539-9dc627e30cbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41424
13948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.4142413948
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.4261857748
Short name T828
Test name
Test status
Simulation time 163058935 ps
CPU time 0.88 seconds
Started Jun 28 06:11:42 PM PDT 24
Finished Jun 28 06:11:45 PM PDT 24
Peak memory 206180 kb
Host smart-16b30a48-19b6-4103-8626-a952db91b998
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42618
57748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.4261857748
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.3455842141
Short name T1445
Test name
Test status
Simulation time 243678920 ps
CPU time 0.96 seconds
Started Jun 28 06:11:43 PM PDT 24
Finished Jun 28 06:11:47 PM PDT 24
Peak memory 206212 kb
Host smart-c37a36a7-0f3b-4aec-9771-869bdda9465e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3455842141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.3455842141
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.1747250464
Short name T2390
Test name
Test status
Simulation time 162104622 ps
CPU time 0.78 seconds
Started Jun 28 06:11:44 PM PDT 24
Finished Jun 28 06:11:47 PM PDT 24
Peak memory 206172 kb
Host smart-4f7530e0-875f-4302-b85a-6e248aafb94d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17472
50464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.1747250464
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.69128431
Short name T34
Test name
Test status
Simulation time 35659656 ps
CPU time 0.66 seconds
Started Jun 28 06:11:49 PM PDT 24
Finished Jun 28 06:11:51 PM PDT 24
Peak memory 206192 kb
Host smart-ffa8009a-8e46-47e5-ac69-7171d7a6151a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69128
431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.69128431
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.3061903856
Short name T259
Test name
Test status
Simulation time 23108510708 ps
CPU time 48.28 seconds
Started Jun 28 06:11:42 PM PDT 24
Finished Jun 28 06:12:32 PM PDT 24
Peak memory 206480 kb
Host smart-81fac256-70f5-4536-a749-39ffdc8831a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30619
03856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.3061903856
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.1212837129
Short name T1045
Test name
Test status
Simulation time 238937274 ps
CPU time 0.94 seconds
Started Jun 28 06:11:41 PM PDT 24
Finished Jun 28 06:11:44 PM PDT 24
Peak memory 206172 kb
Host smart-04cb4755-1af4-417e-a39b-65ae243ef045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12128
37129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.1212837129
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.3972515823
Short name T372
Test name
Test status
Simulation time 233722640 ps
CPU time 0.93 seconds
Started Jun 28 06:11:41 PM PDT 24
Finished Jun 28 06:11:44 PM PDT 24
Peak memory 206188 kb
Host smart-ba5f87b3-027b-4ab6-93c6-4b10b4913304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39725
15823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.3972515823
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.1560704505
Short name T1247
Test name
Test status
Simulation time 203215189 ps
CPU time 0.91 seconds
Started Jun 28 06:11:44 PM PDT 24
Finished Jun 28 06:11:47 PM PDT 24
Peak memory 206224 kb
Host smart-23d0a480-608f-41b2-a0d4-825c0c6daeb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15607
04505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.1560704505
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.4030478658
Short name T1593
Test name
Test status
Simulation time 229644457 ps
CPU time 0.85 seconds
Started Jun 28 06:11:49 PM PDT 24
Finished Jun 28 06:11:51 PM PDT 24
Peak memory 206180 kb
Host smart-31124d9d-f5d4-43f4-9fbe-552627ef0fbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40304
78658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.4030478658
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.49695931
Short name T1178
Test name
Test status
Simulation time 181629291 ps
CPU time 0.86 seconds
Started Jun 28 06:11:51 PM PDT 24
Finished Jun 28 06:11:53 PM PDT 24
Peak memory 206188 kb
Host smart-9e006096-8b38-42ca-a34c-925b3be69d13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49695
931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.49695931
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.25485434
Short name T1167
Test name
Test status
Simulation time 165237403 ps
CPU time 0.76 seconds
Started Jun 28 06:11:41 PM PDT 24
Finished Jun 28 06:11:44 PM PDT 24
Peak memory 206200 kb
Host smart-9db7120c-b79a-483c-8f4f-21f65db1a442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25485
434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.25485434
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.3470838438
Short name T2411
Test name
Test status
Simulation time 188072758 ps
CPU time 0.81 seconds
Started Jun 28 06:11:56 PM PDT 24
Finished Jun 28 06:12:01 PM PDT 24
Peak memory 206184 kb
Host smart-85fcab97-9003-4187-89b8-fcab1121585b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34708
38438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.3470838438
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.748630364
Short name T1097
Test name
Test status
Simulation time 211330579 ps
CPU time 0.97 seconds
Started Jun 28 06:11:55 PM PDT 24
Finished Jun 28 06:11:59 PM PDT 24
Peak memory 206208 kb
Host smart-66898380-6198-4e04-a422-5634a3c9222b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74863
0364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.748630364
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.2575862568
Short name T840
Test name
Test status
Simulation time 3602984164 ps
CPU time 23.94 seconds
Started Jun 28 06:12:02 PM PDT 24
Finished Jun 28 06:12:32 PM PDT 24
Peak memory 206436 kb
Host smart-45d59142-0a91-41f2-808c-8fd2275075d4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2575862568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.2575862568
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.1259665936
Short name T562
Test name
Test status
Simulation time 154319958 ps
CPU time 0.77 seconds
Started Jun 28 06:11:59 PM PDT 24
Finished Jun 28 06:12:06 PM PDT 24
Peak memory 206220 kb
Host smart-3aec8b9f-cca7-4fbc-8794-483311b46b36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12596
65936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.1259665936
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.308201524
Short name T668
Test name
Test status
Simulation time 178597888 ps
CPU time 0.81 seconds
Started Jun 28 06:12:00 PM PDT 24
Finished Jun 28 06:12:07 PM PDT 24
Peak memory 206196 kb
Host smart-43553599-03fc-46df-9c12-ca9f71a0e4b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30820
1524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.308201524
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.2534689992
Short name T1635
Test name
Test status
Simulation time 5675344338 ps
CPU time 51.85 seconds
Started Jun 28 06:11:53 PM PDT 24
Finished Jun 28 06:12:45 PM PDT 24
Peak memory 206396 kb
Host smart-018d6f48-5ed4-4de4-b988-54818edabe92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25346
89992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.2534689992
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.1416957440
Short name T992
Test name
Test status
Simulation time 58833107 ps
CPU time 0.71 seconds
Started Jun 28 06:12:04 PM PDT 24
Finished Jun 28 06:12:11 PM PDT 24
Peak memory 206212 kb
Host smart-937ba583-ab63-4ed4-8d39-942e208e2a87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1416957440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.1416957440
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.2588806685
Short name T1907
Test name
Test status
Simulation time 4131499578 ps
CPU time 4.97 seconds
Started Jun 28 06:11:54 PM PDT 24
Finished Jun 28 06:12:01 PM PDT 24
Peak memory 206512 kb
Host smart-b4c40b59-a5f1-43b7-b8fd-8f6c1b44f832
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2588806685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.2588806685
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.1967738460
Short name T653
Test name
Test status
Simulation time 13387712605 ps
CPU time 14.15 seconds
Started Jun 28 06:11:57 PM PDT 24
Finished Jun 28 06:12:16 PM PDT 24
Peak memory 206316 kb
Host smart-4d61ffb3-ea48-46f9-b7fe-64f5cdc08773
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1967738460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.1967738460
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.754974711
Short name T1596
Test name
Test status
Simulation time 23368311008 ps
CPU time 23.94 seconds
Started Jun 28 06:11:58 PM PDT 24
Finished Jun 28 06:12:28 PM PDT 24
Peak memory 206316 kb
Host smart-af48f9b4-e196-4145-8302-dc34995e9f2c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=754974711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.754974711
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.3510646847
Short name T2503
Test name
Test status
Simulation time 187962899 ps
CPU time 0.88 seconds
Started Jun 28 06:11:59 PM PDT 24
Finished Jun 28 06:12:06 PM PDT 24
Peak memory 206172 kb
Host smart-9037c99a-72c0-430c-bc88-631b2c46cf41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35106
46847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.3510646847
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.1490232391
Short name T2374
Test name
Test status
Simulation time 145015260 ps
CPU time 0.77 seconds
Started Jun 28 06:11:59 PM PDT 24
Finished Jun 28 06:12:07 PM PDT 24
Peak memory 206132 kb
Host smart-11d11974-f8e0-45e5-82ae-42ddf2df3b3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14902
32391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.1490232391
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.148158993
Short name T165
Test name
Test status
Simulation time 286200234 ps
CPU time 1.06 seconds
Started Jun 28 06:11:56 PM PDT 24
Finished Jun 28 06:12:02 PM PDT 24
Peak memory 206196 kb
Host smart-3361c51f-af3f-4413-b4ac-dd89769b28ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14815
8993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.148158993
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.2333549464
Short name T1442
Test name
Test status
Simulation time 996464299 ps
CPU time 2.3 seconds
Started Jun 28 06:11:53 PM PDT 24
Finished Jun 28 06:11:57 PM PDT 24
Peak memory 206304 kb
Host smart-67de659b-bf85-40ff-a337-4a429317cd1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23335
49464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.2333549464
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.642016097
Short name T1402
Test name
Test status
Simulation time 8004000313 ps
CPU time 16.63 seconds
Started Jun 28 06:11:56 PM PDT 24
Finished Jun 28 06:12:17 PM PDT 24
Peak memory 206376 kb
Host smart-7305c24a-de58-4c89-b7fb-d2f33f1fae11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64201
6097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.642016097
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.541732222
Short name T1925
Test name
Test status
Simulation time 423076772 ps
CPU time 1.45 seconds
Started Jun 28 06:12:07 PM PDT 24
Finished Jun 28 06:12:15 PM PDT 24
Peak memory 206196 kb
Host smart-4703c7df-5102-40d4-bb40-1ff30c39974b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54173
2222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.541732222
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.3159340052
Short name T1467
Test name
Test status
Simulation time 153880264 ps
CPU time 0.77 seconds
Started Jun 28 06:11:55 PM PDT 24
Finished Jun 28 06:12:00 PM PDT 24
Peak memory 206148 kb
Host smart-abb25d10-2726-4f1f-bc0f-5fd263f393e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31593
40052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.3159340052
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.1921749570
Short name T1465
Test name
Test status
Simulation time 35335067 ps
CPU time 0.64 seconds
Started Jun 28 06:11:55 PM PDT 24
Finished Jun 28 06:11:58 PM PDT 24
Peak memory 206188 kb
Host smart-d425ec13-2fed-4b21-8078-ab1f26e316fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19217
49570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.1921749570
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.3952748966
Short name T726
Test name
Test status
Simulation time 803313609 ps
CPU time 2.22 seconds
Started Jun 28 06:11:56 PM PDT 24
Finished Jun 28 06:12:03 PM PDT 24
Peak memory 206292 kb
Host smart-227f409f-579c-46a8-b4c6-9162c8508f21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39527
48966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.3952748966
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.1110280891
Short name T2484
Test name
Test status
Simulation time 221768473 ps
CPU time 1.23 seconds
Started Jun 28 06:12:01 PM PDT 24
Finished Jun 28 06:12:09 PM PDT 24
Peak memory 206284 kb
Host smart-4aa9a4f4-3231-4b3e-aa34-24ba13697479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11102
80891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.1110280891
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.1056826146
Short name T1837
Test name
Test status
Simulation time 166865967 ps
CPU time 0.81 seconds
Started Jun 28 06:11:55 PM PDT 24
Finished Jun 28 06:11:59 PM PDT 24
Peak memory 206192 kb
Host smart-fe99af82-ee62-4563-8b42-eda237651f12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10568
26146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.1056826146
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.2829287533
Short name T2353
Test name
Test status
Simulation time 150067346 ps
CPU time 0.75 seconds
Started Jun 28 06:12:09 PM PDT 24
Finished Jun 28 06:12:17 PM PDT 24
Peak memory 206192 kb
Host smart-f28936d2-1f5f-4126-909a-ed9c868d1525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28292
87533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.2829287533
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.2289952260
Short name T17
Test name
Test status
Simulation time 240910364 ps
CPU time 1.01 seconds
Started Jun 28 06:11:58 PM PDT 24
Finished Jun 28 06:12:05 PM PDT 24
Peak memory 206208 kb
Host smart-21b6ae7a-2ff6-4965-9697-269ae4e4ff99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22899
52260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.2289952260
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_invalid_sync.4204438569
Short name T1225
Test name
Test status
Simulation time 6315160775 ps
CPU time 63.76 seconds
Started Jun 28 06:11:54 PM PDT 24
Finished Jun 28 06:12:58 PM PDT 24
Peak memory 206404 kb
Host smart-ce12d6b1-061e-4ddb-8e65-8db81dbd6ad4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4204438569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.4204438569
Directory /workspace/22.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.380780078
Short name T703
Test name
Test status
Simulation time 235659591 ps
CPU time 0.94 seconds
Started Jun 28 06:11:59 PM PDT 24
Finished Jun 28 06:12:07 PM PDT 24
Peak memory 206192 kb
Host smart-9028c127-7097-4d35-9b10-92809876f54a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38078
0078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.380780078
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.1354240731
Short name T220
Test name
Test status
Simulation time 23273057712 ps
CPU time 22.51 seconds
Started Jun 28 06:12:00 PM PDT 24
Finished Jun 28 06:12:29 PM PDT 24
Peak memory 206288 kb
Host smart-3ead17a3-9498-4a03-b3a4-8bc47b962833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13542
40731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.1354240731
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.3910455881
Short name T2311
Test name
Test status
Simulation time 3307492889 ps
CPU time 4 seconds
Started Jun 28 06:11:56 PM PDT 24
Finished Jun 28 06:12:04 PM PDT 24
Peak memory 206216 kb
Host smart-879bfddf-6b0a-472c-8bcd-80e40b07e700
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39104
55881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.3910455881
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.1612623492
Short name T2576
Test name
Test status
Simulation time 10246199304 ps
CPU time 94.81 seconds
Started Jun 28 06:11:56 PM PDT 24
Finished Jun 28 06:13:36 PM PDT 24
Peak memory 206612 kb
Host smart-ae03cd40-15a2-45ca-9e0d-7463d68146b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16126
23492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.1612623492
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.1320781677
Short name T20
Test name
Test status
Simulation time 4761992417 ps
CPU time 46.81 seconds
Started Jun 28 06:11:55 PM PDT 24
Finished Jun 28 06:12:45 PM PDT 24
Peak memory 206412 kb
Host smart-22a731d1-6e05-4d3f-8c9c-838fb8205714
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1320781677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.1320781677
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.2588392231
Short name T2376
Test name
Test status
Simulation time 283124597 ps
CPU time 0.96 seconds
Started Jun 28 06:11:57 PM PDT 24
Finished Jun 28 06:12:03 PM PDT 24
Peak memory 206212 kb
Host smart-d47acca7-c603-4c62-a0ed-4f552dc280aa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2588392231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.2588392231
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.2269580805
Short name T680
Test name
Test status
Simulation time 211284106 ps
CPU time 0.86 seconds
Started Jun 28 06:12:09 PM PDT 24
Finished Jun 28 06:12:17 PM PDT 24
Peak memory 206172 kb
Host smart-8160cf69-e048-4504-88c5-480396bdb16e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22695
80805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.2269580805
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.38398845
Short name T2264
Test name
Test status
Simulation time 3038485458 ps
CPU time 80.52 seconds
Started Jun 28 06:11:57 PM PDT 24
Finished Jun 28 06:13:22 PM PDT 24
Peak memory 206396 kb
Host smart-713bd4c2-089b-4847-8f1d-b53393357b06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38398
845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.38398845
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.2669593883
Short name T2004
Test name
Test status
Simulation time 5613825921 ps
CPU time 144.19 seconds
Started Jun 28 06:12:03 PM PDT 24
Finished Jun 28 06:14:33 PM PDT 24
Peak memory 206456 kb
Host smart-60a0851b-3279-4ace-b8d8-bea9698fc9d7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2669593883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.2669593883
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.140420434
Short name T1239
Test name
Test status
Simulation time 160369348 ps
CPU time 0.81 seconds
Started Jun 28 06:12:01 PM PDT 24
Finished Jun 28 06:12:08 PM PDT 24
Peak memory 206156 kb
Host smart-ca9c83a3-5122-4398-bcb8-ed4763a4ab4d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=140420434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.140420434
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.3004270910
Short name T2421
Test name
Test status
Simulation time 146888847 ps
CPU time 0.77 seconds
Started Jun 28 06:11:59 PM PDT 24
Finished Jun 28 06:12:06 PM PDT 24
Peak memory 206200 kb
Host smart-c9b91b33-2fd6-433c-8860-371795733b11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30042
70910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.3004270910
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.1698810650
Short name T91
Test name
Test status
Simulation time 214590375 ps
CPU time 0.88 seconds
Started Jun 28 06:11:57 PM PDT 24
Finished Jun 28 06:12:05 PM PDT 24
Peak memory 206072 kb
Host smart-b9ebce15-55b7-485c-b3f5-a92ecd46a0c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16988
10650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.1698810650
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.3315884599
Short name T2324
Test name
Test status
Simulation time 214644166 ps
CPU time 0.86 seconds
Started Jun 28 06:11:58 PM PDT 24
Finished Jun 28 06:12:05 PM PDT 24
Peak memory 206184 kb
Host smart-58f01b31-0bf4-40f8-b858-6dce56631a45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33158
84599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.3315884599
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.823518381
Short name T1497
Test name
Test status
Simulation time 208120700 ps
CPU time 0.85 seconds
Started Jun 28 06:11:57 PM PDT 24
Finished Jun 28 06:12:05 PM PDT 24
Peak memory 206188 kb
Host smart-dae61774-927e-483a-8fe7-d84529bfdf5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82351
8381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.823518381
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.236976993
Short name T2209
Test name
Test status
Simulation time 200333465 ps
CPU time 0.89 seconds
Started Jun 28 06:11:59 PM PDT 24
Finished Jun 28 06:12:07 PM PDT 24
Peak memory 206196 kb
Host smart-3be30af7-47fd-4b7d-813b-bcc598fee948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23697
6993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.236976993
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.1656083293
Short name T982
Test name
Test status
Simulation time 157946409 ps
CPU time 0.81 seconds
Started Jun 28 06:12:01 PM PDT 24
Finished Jun 28 06:12:08 PM PDT 24
Peak memory 206200 kb
Host smart-ba1455c1-e451-4c03-adc0-787b19f2ae65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16560
83293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.1656083293
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.1389107155
Short name T1172
Test name
Test status
Simulation time 282460849 ps
CPU time 0.98 seconds
Started Jun 28 06:11:58 PM PDT 24
Finished Jun 28 06:12:05 PM PDT 24
Peak memory 206212 kb
Host smart-ed019781-eb14-4284-83f5-6da8bb637f45
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1389107155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.1389107155
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.1889258503
Short name T1854
Test name
Test status
Simulation time 144295375 ps
CPU time 0.75 seconds
Started Jun 28 06:12:03 PM PDT 24
Finished Jun 28 06:12:10 PM PDT 24
Peak memory 206196 kb
Host smart-f615f044-99f7-4fc8-83c5-d1186a34b992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18892
58503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.1889258503
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.492775703
Short name T1409
Test name
Test status
Simulation time 33348155 ps
CPU time 0.67 seconds
Started Jun 28 06:11:57 PM PDT 24
Finished Jun 28 06:12:05 PM PDT 24
Peak memory 206076 kb
Host smart-090240e9-ccc3-431b-8cbc-1f794ff3ddab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49277
5703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.492775703
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.1042853897
Short name T845
Test name
Test status
Simulation time 10748903356 ps
CPU time 22.11 seconds
Started Jun 28 06:12:00 PM PDT 24
Finished Jun 28 06:12:29 PM PDT 24
Peak memory 206396 kb
Host smart-ec2a9947-ee6f-4417-aad9-63eb2b55d040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10428
53897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.1042853897
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.2735370831
Short name T2065
Test name
Test status
Simulation time 187873367 ps
CPU time 0.9 seconds
Started Jun 28 06:11:58 PM PDT 24
Finished Jun 28 06:12:05 PM PDT 24
Peak memory 206192 kb
Host smart-23fc3cb7-3b15-46fd-b477-9f0f0b6bfa3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27353
70831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.2735370831
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.2359362058
Short name T519
Test name
Test status
Simulation time 196401290 ps
CPU time 0.9 seconds
Started Jun 28 06:12:00 PM PDT 24
Finished Jun 28 06:12:07 PM PDT 24
Peak memory 206184 kb
Host smart-4e50953f-5cc4-43aa-aa37-8a9e61848637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23593
62058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.2359362058
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.3098827370
Short name T1283
Test name
Test status
Simulation time 241465818 ps
CPU time 0.94 seconds
Started Jun 28 06:12:02 PM PDT 24
Finished Jun 28 06:12:09 PM PDT 24
Peak memory 206200 kb
Host smart-66be6cc2-3eec-4e34-8148-4c721e821bb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30988
27370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.3098827370
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.2527704146
Short name T2123
Test name
Test status
Simulation time 180340192 ps
CPU time 0.85 seconds
Started Jun 28 06:12:02 PM PDT 24
Finished Jun 28 06:12:09 PM PDT 24
Peak memory 206176 kb
Host smart-d5851743-1a1d-4453-be9f-6f7c6974d30c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25277
04146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.2527704146
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.1738756543
Short name T595
Test name
Test status
Simulation time 216882785 ps
CPU time 0.97 seconds
Started Jun 28 06:12:00 PM PDT 24
Finished Jun 28 06:12:07 PM PDT 24
Peak memory 206168 kb
Host smart-88d39e7a-00f6-47ec-a2c6-fc3932ae20e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17387
56543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.1738756543
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.4234607196
Short name T2095
Test name
Test status
Simulation time 160731226 ps
CPU time 0.8 seconds
Started Jun 28 06:11:58 PM PDT 24
Finished Jun 28 06:12:05 PM PDT 24
Peak memory 206188 kb
Host smart-3c4f8812-7154-42b4-bf0c-9180b183e2a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42346
07196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.4234607196
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.4089500235
Short name T1533
Test name
Test status
Simulation time 153483269 ps
CPU time 0.79 seconds
Started Jun 28 06:12:00 PM PDT 24
Finished Jun 28 06:12:07 PM PDT 24
Peak memory 206168 kb
Host smart-2068452b-1f82-4e62-a6db-cc27a646d30d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40895
00235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.4089500235
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.1884974122
Short name T2486
Test name
Test status
Simulation time 186071233 ps
CPU time 0.9 seconds
Started Jun 28 06:12:01 PM PDT 24
Finished Jun 28 06:12:08 PM PDT 24
Peak memory 206216 kb
Host smart-5400e73e-1d6b-40ac-83c3-79ebed192945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18849
74122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.1884974122
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.576275929
Short name T423
Test name
Test status
Simulation time 6617499387 ps
CPU time 189.04 seconds
Started Jun 28 06:11:55 PM PDT 24
Finished Jun 28 06:15:08 PM PDT 24
Peak memory 206496 kb
Host smart-d91608c8-19ed-4e9b-99b4-9ed7819e5bbf
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=576275929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.576275929
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.1767109068
Short name T1200
Test name
Test status
Simulation time 195545736 ps
CPU time 0.92 seconds
Started Jun 28 06:12:02 PM PDT 24
Finished Jun 28 06:12:09 PM PDT 24
Peak memory 206216 kb
Host smart-cad5ffa4-1553-4074-93e2-57d88573d910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17671
09068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.1767109068
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.883298778
Short name T1242
Test name
Test status
Simulation time 187233548 ps
CPU time 0.82 seconds
Started Jun 28 06:12:11 PM PDT 24
Finished Jun 28 06:12:20 PM PDT 24
Peak memory 206192 kb
Host smart-a158d4cd-26a8-41bf-b835-1a99aed92be8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88329
8778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.883298778
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.3370835482
Short name T941
Test name
Test status
Simulation time 7225769780 ps
CPU time 50.5 seconds
Started Jun 28 06:12:01 PM PDT 24
Finished Jun 28 06:12:58 PM PDT 24
Peak memory 206452 kb
Host smart-9bef583e-9259-41f6-a374-37df3fadde0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33708
35482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.3370835482
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.2018942662
Short name T2582
Test name
Test status
Simulation time 36237029 ps
CPU time 0.69 seconds
Started Jun 28 06:12:12 PM PDT 24
Finished Jun 28 06:12:20 PM PDT 24
Peak memory 206212 kb
Host smart-adff12a3-834d-492c-8628-70b18a9aa620
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2018942662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.2018942662
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.1238278188
Short name T2043
Test name
Test status
Simulation time 3789376571 ps
CPU time 4.82 seconds
Started Jun 28 06:12:05 PM PDT 24
Finished Jun 28 06:12:16 PM PDT 24
Peak memory 206280 kb
Host smart-c83e2a88-7d93-40e3-84a1-b37b6f111f62
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1238278188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.1238278188
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.3391333320
Short name T1049
Test name
Test status
Simulation time 13322791693 ps
CPU time 12.84 seconds
Started Jun 28 06:12:15 PM PDT 24
Finished Jun 28 06:12:37 PM PDT 24
Peak memory 206316 kb
Host smart-2a0d975e-6e5e-40af-a4b1-18da88522bc5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3391333320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.3391333320
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.2980900426
Short name T984
Test name
Test status
Simulation time 23333279272 ps
CPU time 23.66 seconds
Started Jun 28 06:12:02 PM PDT 24
Finished Jun 28 06:12:32 PM PDT 24
Peak memory 206268 kb
Host smart-a03081ea-0419-4205-b63c-e40948a7a064
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2980900426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.2980900426
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.3443527979
Short name T1087
Test name
Test status
Simulation time 194091272 ps
CPU time 0.82 seconds
Started Jun 28 06:12:03 PM PDT 24
Finished Jun 28 06:12:10 PM PDT 24
Peak memory 206192 kb
Host smart-c4c26ff5-3c14-4795-abe0-622cee2cc104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34435
27979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.3443527979
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.3298658044
Short name T1653
Test name
Test status
Simulation time 172653021 ps
CPU time 0.81 seconds
Started Jun 28 06:12:03 PM PDT 24
Finished Jun 28 06:12:10 PM PDT 24
Peak memory 206188 kb
Host smart-7926ba0f-14b7-4272-829e-3a59c4e1c329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32986
58044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.3298658044
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.1929161652
Short name T1808
Test name
Test status
Simulation time 456358161 ps
CPU time 1.37 seconds
Started Jun 28 06:12:09 PM PDT 24
Finished Jun 28 06:12:17 PM PDT 24
Peak memory 206192 kb
Host smart-40e1b817-5a54-4fa7-8291-f6dd57b27fb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19291
61652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.1929161652
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.4156966539
Short name T1140
Test name
Test status
Simulation time 631824320 ps
CPU time 1.62 seconds
Started Jun 28 06:12:11 PM PDT 24
Finished Jun 28 06:12:20 PM PDT 24
Peak memory 206192 kb
Host smart-f1ccf382-70b4-4f41-a14a-7aec15046fab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41569
66539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.4156966539
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.4087018861
Short name T987
Test name
Test status
Simulation time 11671237059 ps
CPU time 22.65 seconds
Started Jun 28 06:12:03 PM PDT 24
Finished Jun 28 06:12:32 PM PDT 24
Peak memory 206456 kb
Host smart-b9e9b5fc-e233-49dc-9af6-c9f878617a74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40870
18861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.4087018861
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.3013523529
Short name T2535
Test name
Test status
Simulation time 414126034 ps
CPU time 1.19 seconds
Started Jun 28 06:12:08 PM PDT 24
Finished Jun 28 06:12:15 PM PDT 24
Peak memory 206164 kb
Host smart-c31f4802-715a-4e7e-a907-af622275ee9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30135
23529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.3013523529
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.3625374526
Short name T1016
Test name
Test status
Simulation time 135323720 ps
CPU time 0.75 seconds
Started Jun 28 06:12:12 PM PDT 24
Finished Jun 28 06:12:21 PM PDT 24
Peak memory 205924 kb
Host smart-8e035c22-ba6e-4c79-b787-b0fa534daa47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36253
74526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.3625374526
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.1452422711
Short name T620
Test name
Test status
Simulation time 40111865 ps
CPU time 0.68 seconds
Started Jun 28 06:12:11 PM PDT 24
Finished Jun 28 06:12:19 PM PDT 24
Peak memory 206192 kb
Host smart-e5bc4816-3c83-43bd-99c9-17864a59f9cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14524
22711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.1452422711
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.738198974
Short name T1222
Test name
Test status
Simulation time 818589332 ps
CPU time 2.03 seconds
Started Jun 28 06:12:01 PM PDT 24
Finished Jun 28 06:12:10 PM PDT 24
Peak memory 206404 kb
Host smart-59161e9d-ec4e-4672-95c6-6a6d9c89fb7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73819
8974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.738198974
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.814694926
Short name T1124
Test name
Test status
Simulation time 183220206 ps
CPU time 2.1 seconds
Started Jun 28 06:12:01 PM PDT 24
Finished Jun 28 06:12:10 PM PDT 24
Peak memory 206280 kb
Host smart-9e4aa755-f11a-4613-99bb-11af21fc0eaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81469
4926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.814694926
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.160815341
Short name T2008
Test name
Test status
Simulation time 268348831 ps
CPU time 0.97 seconds
Started Jun 28 06:12:03 PM PDT 24
Finished Jun 28 06:12:10 PM PDT 24
Peak memory 206032 kb
Host smart-8a872ac4-83e0-49da-9622-9504391cc937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16081
5341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.160815341
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.2302222893
Short name T1025
Test name
Test status
Simulation time 171788182 ps
CPU time 0.78 seconds
Started Jun 28 06:12:01 PM PDT 24
Finished Jun 28 06:12:08 PM PDT 24
Peak memory 206212 kb
Host smart-9203ab1c-6178-4657-814d-7c3cf0901511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23022
22893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.2302222893
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.3818002950
Short name T375
Test name
Test status
Simulation time 195115068 ps
CPU time 0.89 seconds
Started Jun 28 06:12:01 PM PDT 24
Finished Jun 28 06:12:08 PM PDT 24
Peak memory 206208 kb
Host smart-2cae9a12-3ca9-473b-8526-6badc4ef66a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38180
02950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.3818002950
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.1022075090
Short name T631
Test name
Test status
Simulation time 187531060 ps
CPU time 0.85 seconds
Started Jun 28 06:12:05 PM PDT 24
Finished Jun 28 06:12:12 PM PDT 24
Peak memory 206196 kb
Host smart-41880a72-bf70-43e5-ad07-dccee158c608
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10220
75090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.1022075090
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.1518962513
Short name T1388
Test name
Test status
Simulation time 23302948815 ps
CPU time 28.54 seconds
Started Jun 28 06:12:15 PM PDT 24
Finished Jun 28 06:12:52 PM PDT 24
Peak memory 206308 kb
Host smart-8015212b-5e82-4efe-b856-a6d0074e05a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15189
62513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.1518962513
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.3675025977
Short name T396
Test name
Test status
Simulation time 3290354294 ps
CPU time 4.31 seconds
Started Jun 28 06:12:12 PM PDT 24
Finished Jun 28 06:12:25 PM PDT 24
Peak memory 205984 kb
Host smart-8c1f9e4c-2c66-4a31-95d9-f9396c56be58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36750
25977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.3675025977
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.3795559164
Short name T954
Test name
Test status
Simulation time 4848098067 ps
CPU time 35.39 seconds
Started Jun 28 06:12:15 PM PDT 24
Finished Jun 28 06:12:59 PM PDT 24
Peak memory 206464 kb
Host smart-30045a0d-7621-494a-8f23-2ec380aff7fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37955
59164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.3795559164
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.183812622
Short name T1836
Test name
Test status
Simulation time 3144618653 ps
CPU time 22.71 seconds
Started Jun 28 06:12:15 PM PDT 24
Finished Jun 28 06:12:47 PM PDT 24
Peak memory 206448 kb
Host smart-e30cc488-ed40-446f-8663-55aeb5be6ac8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=183812622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.183812622
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.896178973
Short name T2295
Test name
Test status
Simulation time 260627330 ps
CPU time 0.94 seconds
Started Jun 28 06:12:10 PM PDT 24
Finished Jun 28 06:12:18 PM PDT 24
Peak memory 206216 kb
Host smart-02447de1-1a74-4f18-9b08-35e03bf7a997
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=896178973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.896178973
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.576900673
Short name T2632
Test name
Test status
Simulation time 202972285 ps
CPU time 0.88 seconds
Started Jun 28 06:12:10 PM PDT 24
Finished Jun 28 06:12:19 PM PDT 24
Peak memory 206216 kb
Host smart-981ba805-3066-45de-b9d4-05e1ff70531d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57690
0673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.576900673
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.1334756323
Short name T990
Test name
Test status
Simulation time 3407337591 ps
CPU time 92.31 seconds
Started Jun 28 06:12:10 PM PDT 24
Finished Jun 28 06:13:50 PM PDT 24
Peak memory 206392 kb
Host smart-fb552b3c-43bd-4709-bf71-cc5dd2a58936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13347
56323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.1334756323
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.3276714258
Short name T2527
Test name
Test status
Simulation time 4702651011 ps
CPU time 42.91 seconds
Started Jun 28 06:12:00 PM PDT 24
Finished Jun 28 06:12:49 PM PDT 24
Peak memory 206460 kb
Host smart-29d14e57-2532-4bb6-ac91-0e76d2ccfa0e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3276714258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.3276714258
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.49641154
Short name T1632
Test name
Test status
Simulation time 166557109 ps
CPU time 0.8 seconds
Started Jun 28 06:12:10 PM PDT 24
Finished Jun 28 06:12:18 PM PDT 24
Peak memory 206152 kb
Host smart-6acdb6b6-5ea4-457b-8aad-5e5d49d3abb7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=49641154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.49641154
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.1354474689
Short name T255
Test name
Test status
Simulation time 164132338 ps
CPU time 0.8 seconds
Started Jun 28 06:12:10 PM PDT 24
Finished Jun 28 06:12:18 PM PDT 24
Peak memory 206196 kb
Host smart-e6074246-16c3-4a86-85dc-67c0d53434d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13544
74689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.1354474689
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.3994082666
Short name T1648
Test name
Test status
Simulation time 155129699 ps
CPU time 0.8 seconds
Started Jun 28 06:12:08 PM PDT 24
Finished Jun 28 06:12:15 PM PDT 24
Peak memory 206168 kb
Host smart-88dad982-fc2a-4ab1-8862-39d11b073777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39940
82666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.3994082666
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.63547938
Short name T322
Test name
Test status
Simulation time 174943085 ps
CPU time 0.83 seconds
Started Jun 28 06:12:12 PM PDT 24
Finished Jun 28 06:12:21 PM PDT 24
Peak memory 206172 kb
Host smart-a625dc66-0c10-433b-addf-02a1e77bb33d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63547
938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.63547938
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.3445056075
Short name T714
Test name
Test status
Simulation time 164458151 ps
CPU time 0.84 seconds
Started Jun 28 06:12:09 PM PDT 24
Finished Jun 28 06:12:17 PM PDT 24
Peak memory 206212 kb
Host smart-80332da5-d47e-426e-aeec-628e7de10888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34450
56075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.3445056075
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.1231610595
Short name T1953
Test name
Test status
Simulation time 168866513 ps
CPU time 0.83 seconds
Started Jun 28 06:12:15 PM PDT 24
Finished Jun 28 06:12:25 PM PDT 24
Peak memory 206196 kb
Host smart-dec2ff13-d9a0-4a63-bf82-8bac9f54cf9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12316
10595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.1231610595
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.1046416553
Short name T1371
Test name
Test status
Simulation time 226364653 ps
CPU time 0.89 seconds
Started Jun 28 06:12:07 PM PDT 24
Finished Jun 28 06:12:14 PM PDT 24
Peak memory 206212 kb
Host smart-b75af726-dceb-4cd6-8f3a-591a87a3143a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1046416553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.1046416553
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.3642242794
Short name T2017
Test name
Test status
Simulation time 152327128 ps
CPU time 0.8 seconds
Started Jun 28 06:12:08 PM PDT 24
Finished Jun 28 06:12:15 PM PDT 24
Peak memory 206172 kb
Host smart-d2c3eaa0-a594-42cb-b303-0d1ec77e3ac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36422
42794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.3642242794
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.3422811676
Short name T1879
Test name
Test status
Simulation time 35544337 ps
CPU time 0.7 seconds
Started Jun 28 06:12:02 PM PDT 24
Finished Jun 28 06:12:09 PM PDT 24
Peak memory 206200 kb
Host smart-0c3aaea2-ca1a-4b72-9b4e-6bbd645b25ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34228
11676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.3422811676
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.3862299352
Short name T2384
Test name
Test status
Simulation time 12972297355 ps
CPU time 30.87 seconds
Started Jun 28 06:12:11 PM PDT 24
Finished Jun 28 06:12:50 PM PDT 24
Peak memory 206424 kb
Host smart-bf35dd43-2298-4a1d-8c06-2ee90cd66b74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38622
99352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.3862299352
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.2613992868
Short name T2208
Test name
Test status
Simulation time 163320686 ps
CPU time 0.82 seconds
Started Jun 28 06:12:13 PM PDT 24
Finished Jun 28 06:12:23 PM PDT 24
Peak memory 206156 kb
Host smart-4b9691b6-12b6-43d3-ba36-88a19eceb926
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26139
92868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.2613992868
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.2836699140
Short name T1027
Test name
Test status
Simulation time 242179009 ps
CPU time 0.87 seconds
Started Jun 28 06:12:09 PM PDT 24
Finished Jun 28 06:12:18 PM PDT 24
Peak memory 206208 kb
Host smart-b7827ea2-157f-41d1-91fe-130cf208943f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28366
99140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.2836699140
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.4192970551
Short name T1690
Test name
Test status
Simulation time 195464946 ps
CPU time 0.81 seconds
Started Jun 28 06:12:14 PM PDT 24
Finished Jun 28 06:12:24 PM PDT 24
Peak memory 206216 kb
Host smart-6b725d38-c6f7-40ad-afe9-00d069654794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41929
70551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.4192970551
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.1375246004
Short name T707
Test name
Test status
Simulation time 171993485 ps
CPU time 0.86 seconds
Started Jun 28 06:12:03 PM PDT 24
Finished Jun 28 06:12:10 PM PDT 24
Peak memory 206104 kb
Host smart-5b53326a-0e70-4048-9498-d1932f20dd1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13752
46004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.1375246004
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.938900246
Short name T1474
Test name
Test status
Simulation time 143590427 ps
CPU time 0.78 seconds
Started Jun 28 06:12:10 PM PDT 24
Finished Jun 28 06:12:19 PM PDT 24
Peak memory 206196 kb
Host smart-b80e3abe-2cf3-4e96-a804-05b6d305dcf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93890
0246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.938900246
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.670808776
Short name T697
Test name
Test status
Simulation time 211377394 ps
CPU time 0.81 seconds
Started Jun 28 06:12:12 PM PDT 24
Finished Jun 28 06:12:21 PM PDT 24
Peak memory 206196 kb
Host smart-b8632562-fbfc-47cd-8648-546bf21053a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67080
8776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.670808776
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.119798819
Short name T452
Test name
Test status
Simulation time 152121946 ps
CPU time 0.79 seconds
Started Jun 28 06:12:08 PM PDT 24
Finished Jun 28 06:12:15 PM PDT 24
Peak memory 206156 kb
Host smart-45f2f5ca-1f20-4af7-ae2c-68ac9e947e66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11979
8819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.119798819
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.4004623986
Short name T749
Test name
Test status
Simulation time 221100891 ps
CPU time 1.03 seconds
Started Jun 28 06:12:05 PM PDT 24
Finished Jun 28 06:12:12 PM PDT 24
Peak memory 206212 kb
Host smart-c8bb4dab-6ca4-4e41-8e72-a356ace6c4eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40046
23986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.4004623986
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.1576710881
Short name T148
Test name
Test status
Simulation time 5325879057 ps
CPU time 144.05 seconds
Started Jun 28 06:12:10 PM PDT 24
Finished Jun 28 06:14:42 PM PDT 24
Peak memory 206432 kb
Host smart-cf7428c8-2906-45ba-9517-e5ae8569d2cc
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1576710881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.1576710881
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.2286258531
Short name T1531
Test name
Test status
Simulation time 194996666 ps
CPU time 0.88 seconds
Started Jun 28 06:12:08 PM PDT 24
Finished Jun 28 06:12:16 PM PDT 24
Peak memory 206196 kb
Host smart-d805e4d8-9078-42cd-94bb-fd9bf73a78eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22862
58531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.2286258531
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.2162420370
Short name T1264
Test name
Test status
Simulation time 232831685 ps
CPU time 0.83 seconds
Started Jun 28 06:12:11 PM PDT 24
Finished Jun 28 06:12:21 PM PDT 24
Peak memory 206192 kb
Host smart-f581f580-9a01-46f2-a2f8-810feea6472e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21624
20370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.2162420370
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.2142399981
Short name T2130
Test name
Test status
Simulation time 6513677908 ps
CPU time 44.77 seconds
Started Jun 28 06:12:11 PM PDT 24
Finished Jun 28 06:13:04 PM PDT 24
Peak memory 206476 kb
Host smart-9db66f21-1ac9-4868-ab20-0aa62a0e8c64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21423
99981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.2142399981
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.37111700
Short name T684
Test name
Test status
Simulation time 42606163 ps
CPU time 0.68 seconds
Started Jun 28 06:12:14 PM PDT 24
Finished Jun 28 06:12:23 PM PDT 24
Peak memory 206216 kb
Host smart-035ca881-d627-4769-a60c-bee7d0753b1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=37111700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.37111700
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.2250608027
Short name T658
Test name
Test status
Simulation time 3728654607 ps
CPU time 4.5 seconds
Started Jun 28 06:12:10 PM PDT 24
Finished Jun 28 06:12:22 PM PDT 24
Peak memory 205752 kb
Host smart-c2c5a5b4-cd2f-4e90-81fa-ef3eb3b36ad0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2250608027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.2250608027
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.2581543604
Short name T1996
Test name
Test status
Simulation time 13391380495 ps
CPU time 12.91 seconds
Started Jun 28 06:12:08 PM PDT 24
Finished Jun 28 06:12:27 PM PDT 24
Peak memory 206356 kb
Host smart-c78b737a-31ce-4a6d-aee3-74e9f3492a32
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2581543604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.2581543604
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.493526534
Short name T607
Test name
Test status
Simulation time 23397612591 ps
CPU time 23.6 seconds
Started Jun 28 06:12:11 PM PDT 24
Finished Jun 28 06:12:43 PM PDT 24
Peak memory 206328 kb
Host smart-d9bd7494-7754-4268-b4da-1ec8470a2fec
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=493526534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.493526534
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.788709120
Short name T1500
Test name
Test status
Simulation time 163983738 ps
CPU time 0.77 seconds
Started Jun 28 06:12:11 PM PDT 24
Finished Jun 28 06:12:20 PM PDT 24
Peak memory 206196 kb
Host smart-95eb9291-528c-4056-9b31-e3f3c352df81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78870
9120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.788709120
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.2779278982
Short name T2139
Test name
Test status
Simulation time 141998565 ps
CPU time 0.72 seconds
Started Jun 28 06:12:03 PM PDT 24
Finished Jun 28 06:12:09 PM PDT 24
Peak memory 206012 kb
Host smart-0ee4e70d-ad8f-4130-990a-18356668f73b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27792
78982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.2779278982
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.1981522503
Short name T2332
Test name
Test status
Simulation time 215958599 ps
CPU time 0.89 seconds
Started Jun 28 06:12:19 PM PDT 24
Finished Jun 28 06:12:28 PM PDT 24
Peak memory 206196 kb
Host smart-6034095d-5d93-4b3c-ab13-bcc12eed4e7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19815
22503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.1981522503
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.3475075407
Short name T2379
Test name
Test status
Simulation time 866975237 ps
CPU time 2.08 seconds
Started Jun 28 06:12:12 PM PDT 24
Finished Jun 28 06:12:22 PM PDT 24
Peak memory 206304 kb
Host smart-e83b2d1f-1d65-4a2e-928f-87d5934dd35d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34750
75407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.3475075407
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.1114434753
Short name T95
Test name
Test status
Simulation time 8244574908 ps
CPU time 14.63 seconds
Started Jun 28 06:12:10 PM PDT 24
Finished Jun 28 06:12:32 PM PDT 24
Peak memory 206436 kb
Host smart-8018b5b0-bbaf-4ae6-956f-9a3e6c29203e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11144
34753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.1114434753
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.1878398003
Short name T2319
Test name
Test status
Simulation time 496197162 ps
CPU time 1.41 seconds
Started Jun 28 06:12:11 PM PDT 24
Finished Jun 28 06:12:21 PM PDT 24
Peak memory 206184 kb
Host smart-7e1c4b02-4117-4fa7-8021-6346b51de3aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18783
98003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.1878398003
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.1740064669
Short name T2338
Test name
Test status
Simulation time 180495223 ps
CPU time 0.82 seconds
Started Jun 28 06:12:11 PM PDT 24
Finished Jun 28 06:12:20 PM PDT 24
Peak memory 206192 kb
Host smart-8c40a041-92be-4043-9a74-2859f3a7f0da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17400
64669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.1740064669
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.4108987797
Short name T2423
Test name
Test status
Simulation time 94123746 ps
CPU time 0.68 seconds
Started Jun 28 06:12:12 PM PDT 24
Finished Jun 28 06:12:20 PM PDT 24
Peak memory 206180 kb
Host smart-bc02fc62-0974-4191-bc7c-c7ba55bf7c29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41089
87797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.4108987797
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.330994127
Short name T2159
Test name
Test status
Simulation time 1095713738 ps
CPU time 2.32 seconds
Started Jun 28 06:12:08 PM PDT 24
Finished Jun 28 06:12:18 PM PDT 24
Peak memory 206332 kb
Host smart-42bd1594-fd32-4ffd-b496-2cd8997bf02c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33099
4127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.330994127
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.2824024989
Short name T788
Test name
Test status
Simulation time 300230334 ps
CPU time 1.85 seconds
Started Jun 28 06:12:10 PM PDT 24
Finished Jun 28 06:12:19 PM PDT 24
Peak memory 205700 kb
Host smart-7db4ef7e-4304-4e17-afc4-62a53dd2246a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28240
24989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.2824024989
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.2368516338
Short name T1127
Test name
Test status
Simulation time 260347765 ps
CPU time 0.93 seconds
Started Jun 28 06:12:07 PM PDT 24
Finished Jun 28 06:12:14 PM PDT 24
Peak memory 206188 kb
Host smart-ca3b4b62-0322-4249-b025-72de5d46667f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23685
16338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.2368516338
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.3654032577
Short name T503
Test name
Test status
Simulation time 146645884 ps
CPU time 0.73 seconds
Started Jun 28 06:12:09 PM PDT 24
Finished Jun 28 06:12:18 PM PDT 24
Peak memory 206204 kb
Host smart-3968e75a-a553-49f0-9fd0-f8fdf9159bec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36540
32577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.3654032577
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.2080727628
Short name T27
Test name
Test status
Simulation time 208889826 ps
CPU time 0.87 seconds
Started Jun 28 06:12:08 PM PDT 24
Finished Jun 28 06:12:15 PM PDT 24
Peak memory 206152 kb
Host smart-71e60cc5-a381-4a42-aa86-2b842be27214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20807
27628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.2080727628
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.23578119
Short name T1999
Test name
Test status
Simulation time 282900303 ps
CPU time 0.95 seconds
Started Jun 28 06:12:15 PM PDT 24
Finished Jun 28 06:12:25 PM PDT 24
Peak memory 206192 kb
Host smart-16a09ab4-9294-4867-90d8-2041b075cefe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23578
119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.23578119
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.3651800355
Short name T434
Test name
Test status
Simulation time 23325796214 ps
CPU time 22.82 seconds
Started Jun 28 06:12:13 PM PDT 24
Finished Jun 28 06:12:44 PM PDT 24
Peak memory 206312 kb
Host smart-4b94801a-1688-4ff5-82e0-c98641a85559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36518
00355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.3651800355
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.1329436040
Short name T1665
Test name
Test status
Simulation time 3311924887 ps
CPU time 4.37 seconds
Started Jun 28 06:12:18 PM PDT 24
Finished Jun 28 06:12:31 PM PDT 24
Peak memory 206248 kb
Host smart-c8b70d52-59b9-4f00-95a8-5cf7ea7e7630
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13294
36040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.1329436040
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.662574038
Short name T152
Test name
Test status
Simulation time 7867454782 ps
CPU time 214.02 seconds
Started Jun 28 06:12:11 PM PDT 24
Finished Jun 28 06:15:54 PM PDT 24
Peak memory 206476 kb
Host smart-dd6bd9c9-c3ff-4234-b9f3-fcc9673f39e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66257
4038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.662574038
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.687978595
Short name T905
Test name
Test status
Simulation time 7940982146 ps
CPU time 78.95 seconds
Started Jun 28 06:12:13 PM PDT 24
Finished Jun 28 06:13:41 PM PDT 24
Peak memory 206404 kb
Host smart-4b291a18-92fd-45c7-a8c1-4d6197c0e94f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=687978595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.687978595
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.3954166451
Short name T856
Test name
Test status
Simulation time 258923963 ps
CPU time 0.93 seconds
Started Jun 28 06:12:14 PM PDT 24
Finished Jun 28 06:12:24 PM PDT 24
Peak memory 206300 kb
Host smart-d4218ef5-9ef8-4641-a927-4f21ac716aa3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3954166451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.3954166451
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.1038179464
Short name T2191
Test name
Test status
Simulation time 190276806 ps
CPU time 0.86 seconds
Started Jun 28 06:12:13 PM PDT 24
Finished Jun 28 06:12:23 PM PDT 24
Peak memory 206200 kb
Host smart-9e191f17-7f46-4bc4-a2f9-fcd7e195073f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10381
79464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.1038179464
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.990612761
Short name T2564
Test name
Test status
Simulation time 5716726895 ps
CPU time 38.89 seconds
Started Jun 28 06:12:15 PM PDT 24
Finished Jun 28 06:13:04 PM PDT 24
Peak memory 206472 kb
Host smart-cadf30de-268e-4046-97dc-b6eed381e25a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99061
2761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.990612761
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.1189729715
Short name T1056
Test name
Test status
Simulation time 3832152290 ps
CPU time 37.87 seconds
Started Jun 28 06:12:15 PM PDT 24
Finished Jun 28 06:13:03 PM PDT 24
Peak memory 206384 kb
Host smart-add0b164-36fe-4185-9304-fa2b681fb3b6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1189729715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.1189729715
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.302945954
Short name T1660
Test name
Test status
Simulation time 151186630 ps
CPU time 0.77 seconds
Started Jun 28 06:12:12 PM PDT 24
Finished Jun 28 06:12:21 PM PDT 24
Peak memory 206196 kb
Host smart-4015cc4c-79a7-44ce-8ebf-2debb889fa57
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=302945954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.302945954
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.1827740197
Short name T1975
Test name
Test status
Simulation time 161445644 ps
CPU time 0.8 seconds
Started Jun 28 06:12:15 PM PDT 24
Finished Jun 28 06:12:25 PM PDT 24
Peak memory 206196 kb
Host smart-996e194f-285d-4612-ae8c-3a697e398111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18277
40197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.1827740197
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.484516081
Short name T2278
Test name
Test status
Simulation time 222226393 ps
CPU time 0.9 seconds
Started Jun 28 06:12:14 PM PDT 24
Finished Jun 28 06:12:24 PM PDT 24
Peak memory 206208 kb
Host smart-7d99010b-a668-4c9e-b4b4-c21e02ee8723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48451
6081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.484516081
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.1374499580
Short name T2284
Test name
Test status
Simulation time 182684084 ps
CPU time 0.78 seconds
Started Jun 28 06:12:15 PM PDT 24
Finished Jun 28 06:12:26 PM PDT 24
Peak memory 206192 kb
Host smart-d3a0e4a0-430b-4faf-8509-1d54b0f2f463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13744
99580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.1374499580
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.1269052993
Short name T321
Test name
Test status
Simulation time 170192446 ps
CPU time 0.82 seconds
Started Jun 28 06:12:13 PM PDT 24
Finished Jun 28 06:12:22 PM PDT 24
Peak memory 206128 kb
Host smart-000a826e-707c-47b5-8feb-5ae8c9685977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12690
52993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.1269052993
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.1624034193
Short name T742
Test name
Test status
Simulation time 175961477 ps
CPU time 0.81 seconds
Started Jun 28 06:12:16 PM PDT 24
Finished Jun 28 06:12:26 PM PDT 24
Peak memory 205288 kb
Host smart-e4afb04b-6c78-4548-97db-05c1259fc478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16240
34193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.1624034193
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.868506281
Short name T847
Test name
Test status
Simulation time 222908558 ps
CPU time 0.91 seconds
Started Jun 28 06:12:13 PM PDT 24
Finished Jun 28 06:12:23 PM PDT 24
Peak memory 206184 kb
Host smart-11826d9c-d8aa-4929-ba02-60c10ccee429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86850
6281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.868506281
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.2160869421
Short name T449
Test name
Test status
Simulation time 193471626 ps
CPU time 0.89 seconds
Started Jun 28 06:12:12 PM PDT 24
Finished Jun 28 06:12:21 PM PDT 24
Peak memory 206212 kb
Host smart-eea9181c-9d77-429b-8a8c-93d635c33060
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2160869421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.2160869421
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.2525118055
Short name T1800
Test name
Test status
Simulation time 156444233 ps
CPU time 0.76 seconds
Started Jun 28 06:12:15 PM PDT 24
Finished Jun 28 06:12:26 PM PDT 24
Peak memory 206204 kb
Host smart-989c9871-e32e-43ff-816b-e0265f81f557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25251
18055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.2525118055
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.962220384
Short name T1098
Test name
Test status
Simulation time 75943707 ps
CPU time 0.72 seconds
Started Jun 28 06:12:14 PM PDT 24
Finished Jun 28 06:12:24 PM PDT 24
Peak memory 206200 kb
Host smart-6fa275a6-f46f-42a8-9301-5f2f9581b717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96222
0384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.962220384
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.249776172
Short name T747
Test name
Test status
Simulation time 7879103713 ps
CPU time 18.11 seconds
Started Jun 28 06:12:13 PM PDT 24
Finished Jun 28 06:12:39 PM PDT 24
Peak memory 206432 kb
Host smart-f7676fc4-57ae-4745-82c3-6ce49c1f5765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24977
6172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.249776172
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.2313621953
Short name T1888
Test name
Test status
Simulation time 156206429 ps
CPU time 0.81 seconds
Started Jun 28 06:12:15 PM PDT 24
Finished Jun 28 06:12:26 PM PDT 24
Peak memory 206128 kb
Host smart-3517b3cc-cab5-477b-9ca9-90f102977958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23136
21953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.2313621953
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.31578996
Short name T1916
Test name
Test status
Simulation time 194859414 ps
CPU time 0.81 seconds
Started Jun 28 06:12:21 PM PDT 24
Finished Jun 28 06:12:30 PM PDT 24
Peak memory 206192 kb
Host smart-96ff83a1-22be-4c56-bbfd-6a2dea924357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31578
996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.31578996
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.1754610203
Short name T1948
Test name
Test status
Simulation time 212520678 ps
CPU time 0.91 seconds
Started Jun 28 06:12:13 PM PDT 24
Finished Jun 28 06:12:23 PM PDT 24
Peak memory 206216 kb
Host smart-199a1e07-27f7-4720-8b99-64fa5ac4a9c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17546
10203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.1754610203
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.979690688
Short name T2431
Test name
Test status
Simulation time 149471223 ps
CPU time 0.8 seconds
Started Jun 28 06:12:13 PM PDT 24
Finished Jun 28 06:12:23 PM PDT 24
Peak memory 206196 kb
Host smart-de8d7f6a-6a10-498e-ae2b-dbcca09b0f0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97969
0688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.979690688
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.3106057191
Short name T2460
Test name
Test status
Simulation time 142063432 ps
CPU time 0.76 seconds
Started Jun 28 06:12:18 PM PDT 24
Finished Jun 28 06:12:27 PM PDT 24
Peak memory 206192 kb
Host smart-6c043c23-51dc-4a12-972f-5843e1a3caf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31060
57191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.3106057191
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.3626320407
Short name T1843
Test name
Test status
Simulation time 189122005 ps
CPU time 0.78 seconds
Started Jun 28 06:12:13 PM PDT 24
Finished Jun 28 06:12:23 PM PDT 24
Peak memory 206184 kb
Host smart-31df53d7-1894-469b-8fdb-01192b697d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36263
20407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.3626320407
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.2575326564
Short name T846
Test name
Test status
Simulation time 152566940 ps
CPU time 0.89 seconds
Started Jun 28 06:12:11 PM PDT 24
Finished Jun 28 06:12:20 PM PDT 24
Peak memory 206192 kb
Host smart-15fb4216-6367-4d48-99fb-90020dda5596
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25753
26564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.2575326564
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.3575563530
Short name T1150
Test name
Test status
Simulation time 243546203 ps
CPU time 0.97 seconds
Started Jun 28 06:12:13 PM PDT 24
Finished Jun 28 06:12:23 PM PDT 24
Peak memory 206152 kb
Host smart-d1370fec-8943-48c1-ae9c-446e6bbb128a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35755
63530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.3575563530
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.4213504600
Short name T899
Test name
Test status
Simulation time 5179427550 ps
CPU time 148.43 seconds
Started Jun 28 06:12:16 PM PDT 24
Finished Jun 28 06:14:53 PM PDT 24
Peak memory 206452 kb
Host smart-14c29481-b1cb-4319-9aa3-9650b247c747
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4213504600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.4213504600
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.3017078322
Short name T917
Test name
Test status
Simulation time 181724888 ps
CPU time 0.86 seconds
Started Jun 28 06:12:14 PM PDT 24
Finished Jun 28 06:12:24 PM PDT 24
Peak memory 206220 kb
Host smart-d9ca5230-1c3b-47a2-9e01-a69b45453746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30170
78322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.3017078322
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.1586689109
Short name T386
Test name
Test status
Simulation time 147644413 ps
CPU time 0.83 seconds
Started Jun 28 06:12:15 PM PDT 24
Finished Jun 28 06:12:26 PM PDT 24
Peak memory 206064 kb
Host smart-374ab0ed-5511-4d5b-858f-50c38194aea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15866
89109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.1586689109
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.4011328837
Short name T2540
Test name
Test status
Simulation time 4948181850 ps
CPU time 136.55 seconds
Started Jun 28 06:12:21 PM PDT 24
Finished Jun 28 06:14:45 PM PDT 24
Peak memory 206440 kb
Host smart-11c9f562-09aa-48d9-8fd2-700e509d2793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40113
28837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.4011328837
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.2018904357
Short name T2204
Test name
Test status
Simulation time 37698225 ps
CPU time 0.71 seconds
Started Jun 28 06:12:27 PM PDT 24
Finished Jun 28 06:12:35 PM PDT 24
Peak memory 206216 kb
Host smart-10e4c488-c828-4ef7-9f34-a0565478a7a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2018904357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.2018904357
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.2428351646
Short name T1856
Test name
Test status
Simulation time 4270638133 ps
CPU time 4.62 seconds
Started Jun 28 06:12:15 PM PDT 24
Finished Jun 28 06:12:29 PM PDT 24
Peak memory 206384 kb
Host smart-e4056ed6-cc05-4a93-920e-f6dfbe092fdf
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2428351646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.2428351646
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.4092648059
Short name T1944
Test name
Test status
Simulation time 13388737043 ps
CPU time 12.93 seconds
Started Jun 28 06:12:21 PM PDT 24
Finished Jun 28 06:12:42 PM PDT 24
Peak memory 206324 kb
Host smart-c96d7970-1d20-438d-9750-aa44897cdfb6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4092648059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.4092648059
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.2352830554
Short name T811
Test name
Test status
Simulation time 23405077353 ps
CPU time 21.28 seconds
Started Jun 28 06:12:13 PM PDT 24
Finished Jun 28 06:12:42 PM PDT 24
Peak memory 206392 kb
Host smart-9f29bf7c-2f08-49a2-b0a6-733da5159ce8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2352830554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.2352830554
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.286494535
Short name T570
Test name
Test status
Simulation time 184659873 ps
CPU time 0.81 seconds
Started Jun 28 06:12:18 PM PDT 24
Finished Jun 28 06:12:27 PM PDT 24
Peak memory 206212 kb
Host smart-c7bbeaad-1271-49b8-9b24-331e12fa556b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28649
4535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.286494535
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.2431584042
Short name T1088
Test name
Test status
Simulation time 140682780 ps
CPU time 0.77 seconds
Started Jun 28 06:12:16 PM PDT 24
Finished Jun 28 06:12:26 PM PDT 24
Peak memory 206196 kb
Host smart-4591bfef-e896-4085-b488-ecba7e681999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24315
84042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.2431584042
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.1713925339
Short name T1603
Test name
Test status
Simulation time 403337580 ps
CPU time 1.32 seconds
Started Jun 28 06:12:13 PM PDT 24
Finished Jun 28 06:12:23 PM PDT 24
Peak memory 206160 kb
Host smart-b120fb08-a14c-4b56-b8e1-a6492f35ba78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17139
25339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.1713925339
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.2981195350
Short name T1826
Test name
Test status
Simulation time 1197431550 ps
CPU time 2.95 seconds
Started Jun 28 06:12:13 PM PDT 24
Finished Jun 28 06:12:25 PM PDT 24
Peak memory 206332 kb
Host smart-a49aecd5-1800-4e06-8ef0-32c870b6f410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29811
95350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.2981195350
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.3889811589
Short name T753
Test name
Test status
Simulation time 16146483665 ps
CPU time 31 seconds
Started Jun 28 06:12:13 PM PDT 24
Finished Jun 28 06:12:52 PM PDT 24
Peak memory 206456 kb
Host smart-4b53f849-e317-4654-a5fe-6ec5cfbf99ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38898
11589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.3889811589
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.2645140317
Short name T2291
Test name
Test status
Simulation time 406527608 ps
CPU time 1.25 seconds
Started Jun 28 06:12:14 PM PDT 24
Finished Jun 28 06:12:24 PM PDT 24
Peak memory 206196 kb
Host smart-e8f4a3c7-3023-4a06-849f-686094aadd0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26451
40317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.2645140317
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.2736673728
Short name T1490
Test name
Test status
Simulation time 186258601 ps
CPU time 0.8 seconds
Started Jun 28 06:12:15 PM PDT 24
Finished Jun 28 06:12:25 PM PDT 24
Peak memory 206188 kb
Host smart-de79f736-162b-47fd-b25e-6af6fbdc4c31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27366
73728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.2736673728
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.3393584810
Short name T1555
Test name
Test status
Simulation time 53214571 ps
CPU time 0.67 seconds
Started Jun 28 06:12:17 PM PDT 24
Finished Jun 28 06:12:27 PM PDT 24
Peak memory 206180 kb
Host smart-b0ed45c2-1949-45fc-aa95-799b1f0c42cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33935
84810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.3393584810
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.1161179005
Short name T382
Test name
Test status
Simulation time 932623469 ps
CPU time 2.19 seconds
Started Jun 28 06:12:14 PM PDT 24
Finished Jun 28 06:12:25 PM PDT 24
Peak memory 206280 kb
Host smart-7253f378-71f4-4971-8714-4d08c3018fa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11611
79005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.1161179005
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.4230867048
Short name T221
Test name
Test status
Simulation time 313405001 ps
CPU time 1.87 seconds
Started Jun 28 06:12:18 PM PDT 24
Finished Jun 28 06:12:28 PM PDT 24
Peak memory 206284 kb
Host smart-1bac615c-0363-4bd8-adf8-2d3cbbf7aec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42308
67048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.4230867048
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.2417719657
Short name T1483
Test name
Test status
Simulation time 254890807 ps
CPU time 0.94 seconds
Started Jun 28 06:12:15 PM PDT 24
Finished Jun 28 06:12:26 PM PDT 24
Peak memory 206192 kb
Host smart-aa9d6739-8f54-4537-af55-42393e864eb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24177
19657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.2417719657
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.4146305473
Short name T1950
Test name
Test status
Simulation time 153284840 ps
CPU time 0.76 seconds
Started Jun 28 06:12:17 PM PDT 24
Finished Jun 28 06:12:27 PM PDT 24
Peak memory 206204 kb
Host smart-3d960f36-d910-4395-b140-832f0139ac56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41463
05473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.4146305473
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.2407068586
Short name T2610
Test name
Test status
Simulation time 190950322 ps
CPU time 0.83 seconds
Started Jun 28 06:12:21 PM PDT 24
Finished Jun 28 06:12:29 PM PDT 24
Peak memory 206216 kb
Host smart-6f060125-0ef4-4097-af7c-b7808bf76b8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24070
68586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.2407068586
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_invalid_sync.827427911
Short name T89
Test name
Test status
Simulation time 10318918821 ps
CPU time 295.26 seconds
Started Jun 28 06:12:16 PM PDT 24
Finished Jun 28 06:17:20 PM PDT 24
Peak memory 205756 kb
Host smart-ca52fcc0-7f2d-4aac-a309-391c8a275e20
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=827427911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.827427911
Directory /workspace/25.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.952041132
Short name T901
Test name
Test status
Simulation time 245205787 ps
CPU time 0.88 seconds
Started Jun 28 06:12:16 PM PDT 24
Finished Jun 28 06:12:26 PM PDT 24
Peak memory 206164 kb
Host smart-b6cf2a30-2d39-401e-9fc8-0a614c9547f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95204
1132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.952041132
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.253064172
Short name T1951
Test name
Test status
Simulation time 23329093290 ps
CPU time 22.02 seconds
Started Jun 28 06:12:12 PM PDT 24
Finished Jun 28 06:12:42 PM PDT 24
Peak memory 206312 kb
Host smart-1455cf80-f5d3-4516-b5fd-26375145f17b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25306
4172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.253064172
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.950576611
Short name T521
Test name
Test status
Simulation time 3290427017 ps
CPU time 3.81 seconds
Started Jun 28 06:12:16 PM PDT 24
Finished Jun 28 06:12:29 PM PDT 24
Peak memory 206256 kb
Host smart-092afbe0-9ffe-429a-8769-757dfedeeccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95057
6611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.950576611
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.2864604239
Short name T392
Test name
Test status
Simulation time 11719813471 ps
CPU time 111.21 seconds
Started Jun 28 06:12:15 PM PDT 24
Finished Jun 28 06:14:16 PM PDT 24
Peak memory 206468 kb
Host smart-8f87d2e9-cba3-44a0-ba80-4c740551825f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28646
04239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.2864604239
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.3774740876
Short name T244
Test name
Test status
Simulation time 7271493365 ps
CPU time 67.1 seconds
Started Jun 28 06:12:25 PM PDT 24
Finished Jun 28 06:13:39 PM PDT 24
Peak memory 206492 kb
Host smart-1c749eeb-a64d-4622-889c-94a99f85bf71
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3774740876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.3774740876
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.2293455722
Short name T1186
Test name
Test status
Simulation time 252011477 ps
CPU time 0.93 seconds
Started Jun 28 06:12:23 PM PDT 24
Finished Jun 28 06:12:31 PM PDT 24
Peak memory 206220 kb
Host smart-5c578df6-9885-4699-afec-01e5a76fff24
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2293455722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.2293455722
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.1416434088
Short name T2520
Test name
Test status
Simulation time 197293936 ps
CPU time 0.84 seconds
Started Jun 28 06:12:22 PM PDT 24
Finished Jun 28 06:12:30 PM PDT 24
Peak memory 206204 kb
Host smart-5803f47a-7653-4067-96f8-3c4fa5b22aee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14164
34088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.1416434088
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.967826786
Short name T1851
Test name
Test status
Simulation time 3833922773 ps
CPU time 27.58 seconds
Started Jun 28 06:12:15 PM PDT 24
Finished Jun 28 06:12:52 PM PDT 24
Peak memory 206464 kb
Host smart-fcdeca6d-1f3e-440d-8588-c7482b12b689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96782
6786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.967826786
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.1896112173
Short name T3
Test name
Test status
Simulation time 6789690266 ps
CPU time 197.24 seconds
Started Jun 28 06:12:25 PM PDT 24
Finished Jun 28 06:15:49 PM PDT 24
Peak memory 206452 kb
Host smart-236522f6-846d-4670-bd4e-7c3192f3b3f7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1896112173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.1896112173
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.2574245994
Short name T2286
Test name
Test status
Simulation time 183679051 ps
CPU time 0.82 seconds
Started Jun 28 06:12:15 PM PDT 24
Finished Jun 28 06:12:25 PM PDT 24
Peak memory 206216 kb
Host smart-3f4ec86e-e867-401b-9b4f-7be141f0b5b1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2574245994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.2574245994
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.1080801177
Short name T2447
Test name
Test status
Simulation time 145631228 ps
CPU time 0.77 seconds
Started Jun 28 06:12:25 PM PDT 24
Finished Jun 28 06:12:33 PM PDT 24
Peak memory 206196 kb
Host smart-8d9957d0-6f16-470b-a837-f15ca380042e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10808
01177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.1080801177
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.1597026184
Short name T107
Test name
Test status
Simulation time 201130859 ps
CPU time 0.83 seconds
Started Jun 28 06:12:21 PM PDT 24
Finished Jun 28 06:12:30 PM PDT 24
Peak memory 206196 kb
Host smart-7622664c-e577-4cd8-ab1f-14b351a47b53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15970
26184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.1597026184
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.1509557499
Short name T2177
Test name
Test status
Simulation time 210370988 ps
CPU time 0.88 seconds
Started Jun 28 06:12:25 PM PDT 24
Finished Jun 28 06:12:33 PM PDT 24
Peak memory 206184 kb
Host smart-c319e01d-dee5-46fd-aafb-4d1874399bed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15095
57499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.1509557499
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.3583647556
Short name T62
Test name
Test status
Simulation time 161666884 ps
CPU time 0.82 seconds
Started Jun 28 06:12:14 PM PDT 24
Finished Jun 28 06:12:24 PM PDT 24
Peak memory 206320 kb
Host smart-dafa3d36-5082-405d-a9d9-84c25d095cd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35836
47556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.3583647556
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.2339561695
Short name T1103
Test name
Test status
Simulation time 160600668 ps
CPU time 0.8 seconds
Started Jun 28 06:12:14 PM PDT 24
Finished Jun 28 06:12:24 PM PDT 24
Peak memory 206208 kb
Host smart-95592692-d599-4b71-9b10-d28e9dc78f94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23395
61695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.2339561695
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.551107699
Short name T1039
Test name
Test status
Simulation time 167967116 ps
CPU time 0.77 seconds
Started Jun 28 06:12:25 PM PDT 24
Finished Jun 28 06:12:33 PM PDT 24
Peak memory 206216 kb
Host smart-3d717991-d7a0-4368-927a-c12b52918f4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55110
7699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.551107699
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.2040830868
Short name T2591
Test name
Test status
Simulation time 247256864 ps
CPU time 0.96 seconds
Started Jun 28 06:12:15 PM PDT 24
Finished Jun 28 06:12:25 PM PDT 24
Peak memory 206136 kb
Host smart-7e7f39f6-0cab-44fa-a7ee-516780041a6c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2040830868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.2040830868
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.300962323
Short name T517
Test name
Test status
Simulation time 141209754 ps
CPU time 0.76 seconds
Started Jun 28 06:12:14 PM PDT 24
Finished Jun 28 06:12:24 PM PDT 24
Peak memory 206212 kb
Host smart-532734ea-fe64-41cc-8ca3-a7ae1376b105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30096
2323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.300962323
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.426644620
Short name T1223
Test name
Test status
Simulation time 40373659 ps
CPU time 0.7 seconds
Started Jun 28 06:12:25 PM PDT 24
Finished Jun 28 06:12:32 PM PDT 24
Peak memory 206200 kb
Host smart-3833365d-1b27-4bf6-b354-48816600169e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42664
4620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.426644620
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.613020488
Short name T786
Test name
Test status
Simulation time 15500104235 ps
CPU time 35.4 seconds
Started Jun 28 06:12:27 PM PDT 24
Finished Jun 28 06:13:10 PM PDT 24
Peak memory 206404 kb
Host smart-f18c2e2c-5322-4059-80e7-5f74c8564d58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61302
0488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.613020488
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.3821815951
Short name T2250
Test name
Test status
Simulation time 179527008 ps
CPU time 0.87 seconds
Started Jun 28 06:12:24 PM PDT 24
Finished Jun 28 06:12:32 PM PDT 24
Peak memory 206192 kb
Host smart-94514ca1-caad-486e-a9e8-fcbe60d3a44f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38218
15951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.3821815951
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.3285626011
Short name T593
Test name
Test status
Simulation time 167229926 ps
CPU time 0.81 seconds
Started Jun 28 06:12:27 PM PDT 24
Finished Jun 28 06:12:35 PM PDT 24
Peak memory 206216 kb
Host smart-6b460594-7bf0-4dd4-825c-36b1913f07e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32856
26011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.3285626011
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.3682929694
Short name T1439
Test name
Test status
Simulation time 216041057 ps
CPU time 0.9 seconds
Started Jun 28 06:12:27 PM PDT 24
Finished Jun 28 06:12:35 PM PDT 24
Peak memory 206144 kb
Host smart-452f7cc8-3ea5-4ca9-9fad-c534848d57f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36829
29694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.3682929694
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.2520653754
Short name T1031
Test name
Test status
Simulation time 202852511 ps
CPU time 0.91 seconds
Started Jun 28 06:12:23 PM PDT 24
Finished Jun 28 06:12:31 PM PDT 24
Peak memory 206144 kb
Host smart-1398d0d8-3cff-416a-9768-34c5246543b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25206
53754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.2520653754
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.41301928
Short name T1034
Test name
Test status
Simulation time 154967588 ps
CPU time 0.76 seconds
Started Jun 28 06:12:25 PM PDT 24
Finished Jun 28 06:12:33 PM PDT 24
Peak memory 206152 kb
Host smart-4c439931-501f-4076-8a28-66d105c0f81a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41301
928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.41301928
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.234936849
Short name T819
Test name
Test status
Simulation time 150176543 ps
CPU time 0.79 seconds
Started Jun 28 06:12:25 PM PDT 24
Finished Jun 28 06:12:32 PM PDT 24
Peak memory 206132 kb
Host smart-3776b7fe-2b05-433f-bf14-60b26c3244e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23493
6849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.234936849
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.3467957531
Short name T1123
Test name
Test status
Simulation time 151097927 ps
CPU time 0.83 seconds
Started Jun 28 06:12:26 PM PDT 24
Finished Jun 28 06:12:33 PM PDT 24
Peak memory 206192 kb
Host smart-a792ac14-1d40-4a06-9395-dbd72b588b15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34679
57531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.3467957531
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.2744930308
Short name T349
Test name
Test status
Simulation time 265651168 ps
CPU time 0.98 seconds
Started Jun 28 06:12:29 PM PDT 24
Finished Jun 28 06:12:37 PM PDT 24
Peak memory 206188 kb
Host smart-ff4c4ae2-812f-411d-87e1-46e4627f39b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27449
30308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.2744930308
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.2739258065
Short name T447
Test name
Test status
Simulation time 4912161488 ps
CPU time 34.13 seconds
Started Jun 28 06:12:30 PM PDT 24
Finished Jun 28 06:13:11 PM PDT 24
Peak memory 206460 kb
Host smart-53f04eb3-2488-4692-9339-f3f108527919
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2739258065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.2739258065
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.626509252
Short name T1842
Test name
Test status
Simulation time 151345344 ps
CPU time 0.82 seconds
Started Jun 28 06:12:28 PM PDT 24
Finished Jun 28 06:12:36 PM PDT 24
Peak memory 206356 kb
Host smart-0e2f7084-1533-470e-b43b-98a969cec455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62650
9252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.626509252
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.3700078128
Short name T1155
Test name
Test status
Simulation time 182924232 ps
CPU time 0.87 seconds
Started Jun 28 06:12:30 PM PDT 24
Finished Jun 28 06:12:38 PM PDT 24
Peak memory 206132 kb
Host smart-de089432-cc5b-437e-9041-1e222df31151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37000
78128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.3700078128
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.1297069459
Short name T1671
Test name
Test status
Simulation time 6112035375 ps
CPU time 174.01 seconds
Started Jun 28 06:12:27 PM PDT 24
Finished Jun 28 06:15:28 PM PDT 24
Peak memory 206440 kb
Host smart-c544ccfe-a3e1-49d4-a01f-6a6d348c4430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12970
69459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.1297069459
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.2235728052
Short name T1309
Test name
Test status
Simulation time 34575396 ps
CPU time 0.66 seconds
Started Jun 28 06:12:26 PM PDT 24
Finished Jun 28 06:12:34 PM PDT 24
Peak memory 206208 kb
Host smart-2615fcf1-8343-41f3-ab20-f9bb8ffd0782
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2235728052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.2235728052
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.2380375868
Short name T1812
Test name
Test status
Simulation time 3882565019 ps
CPU time 4.9 seconds
Started Jun 28 06:12:25 PM PDT 24
Finished Jun 28 06:12:37 PM PDT 24
Peak memory 206344 kb
Host smart-18acddc6-65fa-4b60-8984-8c9d30bd433d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2380375868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.2380375868
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.2552623290
Short name T539
Test name
Test status
Simulation time 13332307669 ps
CPU time 14.33 seconds
Started Jun 28 06:12:26 PM PDT 24
Finished Jun 28 06:12:48 PM PDT 24
Peak memory 206184 kb
Host smart-2090e67a-03c1-4e2e-aba3-90041b2ef3d1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2552623290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.2552623290
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.3301716401
Short name T655
Test name
Test status
Simulation time 23330097911 ps
CPU time 24.76 seconds
Started Jun 28 06:12:25 PM PDT 24
Finished Jun 28 06:12:57 PM PDT 24
Peak memory 206316 kb
Host smart-4234e967-4c9e-4868-bbf3-d01865173884
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3301716401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.3301716401
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.3299094648
Short name T2438
Test name
Test status
Simulation time 188812538 ps
CPU time 0.8 seconds
Started Jun 28 06:12:26 PM PDT 24
Finished Jun 28 06:12:34 PM PDT 24
Peak memory 206188 kb
Host smart-03b93f1f-0094-461c-b823-3867d99825c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32990
94648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.3299094648
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.4051881123
Short name T1680
Test name
Test status
Simulation time 159900886 ps
CPU time 0.79 seconds
Started Jun 28 06:12:29 PM PDT 24
Finished Jun 28 06:12:37 PM PDT 24
Peak memory 206132 kb
Host smart-01a10bd0-b070-4838-be5a-ea4010f19bc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40518
81123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.4051881123
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.1240848244
Short name T1918
Test name
Test status
Simulation time 907871476 ps
CPU time 2.14 seconds
Started Jun 28 06:12:25 PM PDT 24
Finished Jun 28 06:12:33 PM PDT 24
Peak memory 206288 kb
Host smart-541bcee9-ecf4-4975-aa6f-199353481936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12408
48244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.1240848244
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.3357356289
Short name T2261
Test name
Test status
Simulation time 15283265703 ps
CPU time 33.23 seconds
Started Jun 28 06:12:26 PM PDT 24
Finished Jun 28 06:13:07 PM PDT 24
Peak memory 206316 kb
Host smart-78e6b5d9-d137-431d-bd59-282c05661494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33573
56289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.3357356289
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.1092307319
Short name T1099
Test name
Test status
Simulation time 328880218 ps
CPU time 1.2 seconds
Started Jun 28 06:12:28 PM PDT 24
Finished Jun 28 06:12:36 PM PDT 24
Peak memory 206204 kb
Host smart-6ba85b80-3759-4302-8bf8-5d2cac16a969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10923
07319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.1092307319
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.1160599781
Short name T1023
Test name
Test status
Simulation time 139547035 ps
CPU time 0.78 seconds
Started Jun 28 06:12:29 PM PDT 24
Finished Jun 28 06:12:37 PM PDT 24
Peak memory 206164 kb
Host smart-85b126d7-bdba-4e04-a5c5-7df418c29685
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11605
99781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.1160599781
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.4050151638
Short name T2287
Test name
Test status
Simulation time 71452076 ps
CPU time 0.69 seconds
Started Jun 28 06:12:25 PM PDT 24
Finished Jun 28 06:12:32 PM PDT 24
Peak memory 206176 kb
Host smart-79013221-5b29-4fdd-a458-dd266a4ba4d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40501
51638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.4050151638
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.3334092861
Short name T2452
Test name
Test status
Simulation time 741579198 ps
CPU time 2 seconds
Started Jun 28 06:12:26 PM PDT 24
Finished Jun 28 06:12:35 PM PDT 24
Peak memory 206336 kb
Host smart-43c0615d-cd91-41cf-a290-66f092d25fac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33340
92861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.3334092861
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.250603333
Short name T502
Test name
Test status
Simulation time 259560107 ps
CPU time 1.47 seconds
Started Jun 28 06:12:28 PM PDT 24
Finished Jun 28 06:12:37 PM PDT 24
Peak memory 206312 kb
Host smart-cb8df9cb-6898-4020-b62c-c72e36a7d3c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25060
3333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.250603333
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.265559651
Short name T102
Test name
Test status
Simulation time 171387570 ps
CPU time 0.77 seconds
Started Jun 28 06:12:25 PM PDT 24
Finished Jun 28 06:12:32 PM PDT 24
Peak memory 206208 kb
Host smart-2e80680e-91aa-4f5d-96e5-3f8c321ce564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26555
9651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.265559651
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.3363612900
Short name T1431
Test name
Test status
Simulation time 198257639 ps
CPU time 0.81 seconds
Started Jun 28 06:12:25 PM PDT 24
Finished Jun 28 06:12:33 PM PDT 24
Peak memory 206212 kb
Host smart-5d3046ec-0606-421d-b633-641d4e22415b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33636
12900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.3363612900
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.2868509159
Short name T2456
Test name
Test status
Simulation time 170798908 ps
CPU time 0.81 seconds
Started Jun 28 06:12:27 PM PDT 24
Finished Jun 28 06:12:35 PM PDT 24
Peak memory 206188 kb
Host smart-56a3adca-f28e-4b46-8370-cb3e82df4bbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28685
09159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.2868509159
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.1743935129
Short name T2083
Test name
Test status
Simulation time 204140873 ps
CPU time 0.87 seconds
Started Jun 28 06:12:29 PM PDT 24
Finished Jun 28 06:12:37 PM PDT 24
Peak memory 206168 kb
Host smart-aa8b8cca-6690-400a-8af0-308e3ceb8d50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17439
35129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.1743935129
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.3372554076
Short name T2509
Test name
Test status
Simulation time 23287809887 ps
CPU time 24.78 seconds
Started Jun 28 06:12:27 PM PDT 24
Finished Jun 28 06:12:59 PM PDT 24
Peak memory 206312 kb
Host smart-8531fa8f-cdee-4712-927a-517774cf6b6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33725
54076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.3372554076
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.1750866981
Short name T1329
Test name
Test status
Simulation time 3258171077 ps
CPU time 4.03 seconds
Started Jun 28 06:12:26 PM PDT 24
Finished Jun 28 06:12:37 PM PDT 24
Peak memory 206236 kb
Host smart-70709ad8-cbfc-4c7e-921a-abbc5e151331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17508
66981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.1750866981
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.175755768
Short name T1584
Test name
Test status
Simulation time 11219938892 ps
CPU time 298.79 seconds
Started Jun 28 06:12:24 PM PDT 24
Finished Jun 28 06:17:29 PM PDT 24
Peak memory 206472 kb
Host smart-f37e77be-f4a5-448d-9959-2354cfeb189d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17575
5768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.175755768
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.3559405440
Short name T2381
Test name
Test status
Simulation time 6246336818 ps
CPU time 55.7 seconds
Started Jun 28 06:12:29 PM PDT 24
Finished Jun 28 06:13:31 PM PDT 24
Peak memory 206376 kb
Host smart-2a64986b-ee5e-4226-a91a-0afe1d3fec4f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3559405440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.3559405440
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.4033119068
Short name T1036
Test name
Test status
Simulation time 290976438 ps
CPU time 0.95 seconds
Started Jun 28 06:12:27 PM PDT 24
Finished Jun 28 06:12:35 PM PDT 24
Peak memory 206328 kb
Host smart-1e006f84-a174-4e53-a548-6bf4c1d08baa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4033119068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.4033119068
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.2564315352
Short name T257
Test name
Test status
Simulation time 190378117 ps
CPU time 0.88 seconds
Started Jun 28 06:12:27 PM PDT 24
Finished Jun 28 06:12:35 PM PDT 24
Peak memory 206204 kb
Host smart-07fb11fc-7d27-4bd5-ad6b-be9a57af04e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25643
15352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.2564315352
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.1664778674
Short name T147
Test name
Test status
Simulation time 4925508857 ps
CPU time 141.39 seconds
Started Jun 28 06:12:24 PM PDT 24
Finished Jun 28 06:14:52 PM PDT 24
Peak memory 206436 kb
Host smart-98ac6bea-fba5-4214-9bb8-436085cca6fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16647
78674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.1664778674
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.558648858
Short name T1184
Test name
Test status
Simulation time 5361143674 ps
CPU time 39.72 seconds
Started Jun 28 06:12:29 PM PDT 24
Finished Jun 28 06:13:16 PM PDT 24
Peak memory 206396 kb
Host smart-d8413eab-322b-4c55-8852-0b2940202ac9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=558648858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.558648858
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.445766765
Short name T355
Test name
Test status
Simulation time 155505692 ps
CPU time 0.8 seconds
Started Jun 28 06:12:27 PM PDT 24
Finished Jun 28 06:12:35 PM PDT 24
Peak memory 206200 kb
Host smart-b35271b2-1269-4ed6-a9ee-ddca47f18c2a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=445766765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.445766765
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.3566290543
Short name T1774
Test name
Test status
Simulation time 143865978 ps
CPU time 0.81 seconds
Started Jun 28 06:12:32 PM PDT 24
Finished Jun 28 06:12:39 PM PDT 24
Peak memory 206200 kb
Host smart-d695f89a-bbe8-4a9f-b5c8-7a45fed1043d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35662
90543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.3566290543
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.678593754
Short name T2547
Test name
Test status
Simulation time 204682541 ps
CPU time 0.91 seconds
Started Jun 28 06:12:32 PM PDT 24
Finished Jun 28 06:12:39 PM PDT 24
Peak memory 206192 kb
Host smart-7026b0ac-14f2-439e-9e38-36025cfec65a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67859
3754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.678593754
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.4174969960
Short name T478
Test name
Test status
Simulation time 223437865 ps
CPU time 0.9 seconds
Started Jun 28 06:12:27 PM PDT 24
Finished Jun 28 06:12:35 PM PDT 24
Peak memory 206116 kb
Host smart-1d56f8c7-0ffd-4356-8735-16931078b45a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41749
69960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.4174969960
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.1942300529
Short name T1077
Test name
Test status
Simulation time 155650760 ps
CPU time 0.79 seconds
Started Jun 28 06:12:28 PM PDT 24
Finished Jun 28 06:12:36 PM PDT 24
Peak memory 206176 kb
Host smart-fbdf64b6-62e4-4b4b-8eba-1f436b5e9c12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19423
00529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.1942300529
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.144842583
Short name T1125
Test name
Test status
Simulation time 156422711 ps
CPU time 0.8 seconds
Started Jun 28 06:12:29 PM PDT 24
Finished Jun 28 06:12:37 PM PDT 24
Peak memory 206160 kb
Host smart-aa5a39f6-af1c-4505-87e5-6d9db939eccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14484
2583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.144842583
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.2538868521
Short name T1192
Test name
Test status
Simulation time 157799677 ps
CPU time 0.82 seconds
Started Jun 28 06:12:28 PM PDT 24
Finished Jun 28 06:12:36 PM PDT 24
Peak memory 206356 kb
Host smart-ed3cdf0b-9b6c-44fe-8de9-cf92341d56ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25388
68521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.2538868521
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.38631196
Short name T971
Test name
Test status
Simulation time 222798996 ps
CPU time 1.1 seconds
Started Jun 28 06:12:27 PM PDT 24
Finished Jun 28 06:12:35 PM PDT 24
Peak memory 206184 kb
Host smart-441e3b1f-374f-4b82-9288-350cb7584fd7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=38631196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.38631196
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.1270518129
Short name T1005
Test name
Test status
Simulation time 150212935 ps
CPU time 0.77 seconds
Started Jun 28 06:12:30 PM PDT 24
Finished Jun 28 06:12:38 PM PDT 24
Peak memory 206196 kb
Host smart-adf115c7-89ab-4d69-a3f9-b0d029b01efb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12705
18129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.1270518129
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.1875288651
Short name T1794
Test name
Test status
Simulation time 46306365 ps
CPU time 0.65 seconds
Started Jun 28 06:12:29 PM PDT 24
Finished Jun 28 06:12:37 PM PDT 24
Peak memory 206056 kb
Host smart-a7e29e5c-afab-4ab1-9cb4-3c86e11fb286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18752
88651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.1875288651
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.4268973021
Short name T2275
Test name
Test status
Simulation time 11074921766 ps
CPU time 24.95 seconds
Started Jun 28 06:12:27 PM PDT 24
Finished Jun 28 06:12:59 PM PDT 24
Peak memory 206432 kb
Host smart-f28d199f-42bb-481a-949f-cb35832404d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42689
73021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.4268973021
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.3612062009
Short name T1326
Test name
Test status
Simulation time 217695226 ps
CPU time 0.89 seconds
Started Jun 28 06:12:30 PM PDT 24
Finished Jun 28 06:12:38 PM PDT 24
Peak memory 206192 kb
Host smart-7495dffb-21e6-4a65-9410-8d1d22cd985d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36120
62009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.3612062009
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.2040277213
Short name T482
Test name
Test status
Simulation time 252744602 ps
CPU time 0.97 seconds
Started Jun 28 06:12:29 PM PDT 24
Finished Jun 28 06:12:37 PM PDT 24
Peak memory 206180 kb
Host smart-75fc2da2-d861-4010-bf60-75580257a3f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20402
77213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.2040277213
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.1433825207
Short name T2218
Test name
Test status
Simulation time 191466236 ps
CPU time 0.82 seconds
Started Jun 28 06:12:27 PM PDT 24
Finished Jun 28 06:12:35 PM PDT 24
Peak memory 206200 kb
Host smart-fa75e714-bbd2-41f4-a5d6-eee931756179
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14338
25207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.1433825207
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.3364810576
Short name T2023
Test name
Test status
Simulation time 181865988 ps
CPU time 0.8 seconds
Started Jun 28 06:12:30 PM PDT 24
Finished Jun 28 06:12:37 PM PDT 24
Peak memory 205988 kb
Host smart-297cf023-0233-4d82-8f08-e234b6d51bbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33648
10576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.3364810576
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.2379572679
Short name T1573
Test name
Test status
Simulation time 200216551 ps
CPU time 0.88 seconds
Started Jun 28 06:12:25 PM PDT 24
Finished Jun 28 06:12:33 PM PDT 24
Peak memory 206200 kb
Host smart-5c5e7988-ae7a-4880-aaf8-b5223dd6ee31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23795
72679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.2379572679
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.1584145571
Short name T750
Test name
Test status
Simulation time 201355334 ps
CPU time 0.81 seconds
Started Jun 28 06:12:28 PM PDT 24
Finished Jun 28 06:12:36 PM PDT 24
Peak memory 206196 kb
Host smart-7999c6ae-5cd0-4e2d-8d28-b8ba89b03fe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15841
45571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.1584145571
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.2788459928
Short name T41
Test name
Test status
Simulation time 149871446 ps
CPU time 0.78 seconds
Started Jun 28 06:12:27 PM PDT 24
Finished Jun 28 06:12:35 PM PDT 24
Peak memory 206180 kb
Host smart-b9ab42a9-ac74-4528-b79e-194643deeb3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27884
59928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.2788459928
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.734483295
Short name T1359
Test name
Test status
Simulation time 184202149 ps
CPU time 0.87 seconds
Started Jun 28 06:12:28 PM PDT 24
Finished Jun 28 06:12:36 PM PDT 24
Peak memory 206216 kb
Host smart-71f59464-9ae2-4f8d-b21f-4960def0f377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73448
3295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.734483295
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.1670058378
Short name T1746
Test name
Test status
Simulation time 5630931507 ps
CPU time 50.9 seconds
Started Jun 28 06:12:32 PM PDT 24
Finished Jun 28 06:13:29 PM PDT 24
Peak memory 206392 kb
Host smart-cb2b91ea-9e04-4dc2-8ab2-25f043e7a023
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1670058378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.1670058378
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.877062302
Short name T698
Test name
Test status
Simulation time 183417496 ps
CPU time 0.77 seconds
Started Jun 28 06:12:25 PM PDT 24
Finished Jun 28 06:12:32 PM PDT 24
Peak memory 206032 kb
Host smart-33f8b4ff-68ff-4452-ab30-8297d50a5dc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87706
2302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.877062302
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.2522829951
Short name T598
Test name
Test status
Simulation time 224054975 ps
CPU time 0.89 seconds
Started Jun 28 06:12:27 PM PDT 24
Finished Jun 28 06:12:35 PM PDT 24
Peak memory 206180 kb
Host smart-7063c73f-29d3-47ed-aa06-0d9dbd870f9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25228
29951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.2522829951
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.1442478061
Short name T2273
Test name
Test status
Simulation time 4195274468 ps
CPU time 29.3 seconds
Started Jun 28 06:12:26 PM PDT 24
Finished Jun 28 06:13:03 PM PDT 24
Peak memory 206368 kb
Host smart-010f224a-1919-41dd-8b54-1e155faca9be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14424
78061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.1442478061
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.2097520387
Short name T1899
Test name
Test status
Simulation time 37080662 ps
CPU time 0.7 seconds
Started Jun 28 06:12:45 PM PDT 24
Finished Jun 28 06:12:49 PM PDT 24
Peak memory 206212 kb
Host smart-b01630eb-c563-4537-92cb-a6f00dd7a4a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2097520387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.2097520387
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.1684558864
Short name T648
Test name
Test status
Simulation time 4067353675 ps
CPU time 4.74 seconds
Started Jun 28 06:12:29 PM PDT 24
Finished Jun 28 06:12:41 PM PDT 24
Peak memory 206216 kb
Host smart-0c7ce709-993d-4856-9295-4fc7c8d2c960
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1684558864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.1684558864
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.1525550906
Short name T638
Test name
Test status
Simulation time 13409007086 ps
CPU time 14.78 seconds
Started Jun 28 06:12:28 PM PDT 24
Finished Jun 28 06:12:50 PM PDT 24
Peak memory 206324 kb
Host smart-1d98b998-6eef-4d0e-bff2-f4f93d0495f0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1525550906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.1525550906
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.607497346
Short name T2137
Test name
Test status
Simulation time 23321902074 ps
CPU time 23.23 seconds
Started Jun 28 06:12:44 PM PDT 24
Finished Jun 28 06:13:09 PM PDT 24
Peak memory 206448 kb
Host smart-18ca1c05-e19a-42cd-9c91-008b39b17eae
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=607497346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.607497346
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.2888016716
Short name T525
Test name
Test status
Simulation time 155969802 ps
CPU time 0.84 seconds
Started Jun 28 06:12:47 PM PDT 24
Finished Jun 28 06:12:53 PM PDT 24
Peak memory 206320 kb
Host smart-ee9aa80f-ad5a-46f6-a198-0e1ff5696a55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28880
16716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.2888016716
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.673105899
Short name T2051
Test name
Test status
Simulation time 164765803 ps
CPU time 0.81 seconds
Started Jun 28 06:12:45 PM PDT 24
Finished Jun 28 06:12:48 PM PDT 24
Peak memory 206160 kb
Host smart-64ffb433-7447-4cc3-836e-e45020b21939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67310
5899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.673105899
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.2617870154
Short name T1668
Test name
Test status
Simulation time 210106046 ps
CPU time 0.88 seconds
Started Jun 28 06:12:48 PM PDT 24
Finished Jun 28 06:12:53 PM PDT 24
Peak memory 206128 kb
Host smart-d03f1409-c143-4b4b-88c8-3ebadaea8a9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26178
70154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.2617870154
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.2651461260
Short name T158
Test name
Test status
Simulation time 1152692888 ps
CPU time 2.73 seconds
Started Jun 28 06:12:47 PM PDT 24
Finished Jun 28 06:12:54 PM PDT 24
Peak memory 206352 kb
Host smart-b41e4625-9bd1-4ab6-898a-fbdb51b3e891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26514
61260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.2651461260
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.2207197378
Short name T720
Test name
Test status
Simulation time 18454875889 ps
CPU time 30.76 seconds
Started Jun 28 06:12:45 PM PDT 24
Finished Jun 28 06:13:19 PM PDT 24
Peak memory 206428 kb
Host smart-8cf6662e-bde9-41a9-baa0-f44848925299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22071
97378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.2207197378
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.1476109741
Short name T1540
Test name
Test status
Simulation time 441098671 ps
CPU time 1.34 seconds
Started Jun 28 06:12:43 PM PDT 24
Finished Jun 28 06:12:45 PM PDT 24
Peak memory 206200 kb
Host smart-8384796c-fe7e-4d00-b1bd-2cc1c4a436d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14761
09741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.1476109741
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.1053021445
Short name T369
Test name
Test status
Simulation time 190802031 ps
CPU time 0.86 seconds
Started Jun 28 06:12:45 PM PDT 24
Finished Jun 28 06:12:49 PM PDT 24
Peak memory 206188 kb
Host smart-d2154288-7bc7-4483-a467-ceeb98cc2d43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10530
21445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.1053021445
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.224138298
Short name T553
Test name
Test status
Simulation time 62412516 ps
CPU time 0.64 seconds
Started Jun 28 06:12:42 PM PDT 24
Finished Jun 28 06:12:43 PM PDT 24
Peak memory 206168 kb
Host smart-19d8bd7f-91c3-45ec-8c6c-8103feb99b26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22413
8298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.224138298
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.3610963041
Short name T1691
Test name
Test status
Simulation time 910929768 ps
CPU time 2.27 seconds
Started Jun 28 06:12:46 PM PDT 24
Finished Jun 28 06:12:52 PM PDT 24
Peak memory 206308 kb
Host smart-502f8a62-3fa8-43f0-b9dd-1746f3f4a12f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36109
63041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.3610963041
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.1699314306
Short name T763
Test name
Test status
Simulation time 324843809 ps
CPU time 2.05 seconds
Started Jun 28 06:12:45 PM PDT 24
Finished Jun 28 06:12:48 PM PDT 24
Peak memory 206312 kb
Host smart-fb67e8b9-cf1e-4933-8f2f-8be8f33cb96a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16993
14306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.1699314306
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.306064268
Short name T1351
Test name
Test status
Simulation time 203355189 ps
CPU time 0.97 seconds
Started Jun 28 06:12:44 PM PDT 24
Finished Jun 28 06:12:46 PM PDT 24
Peak memory 206196 kb
Host smart-b5e3fb5a-b3c0-4043-a0aa-3a73c098b55d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30606
4268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.306064268
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.599625689
Short name T1576
Test name
Test status
Simulation time 136211274 ps
CPU time 0.78 seconds
Started Jun 28 06:12:45 PM PDT 24
Finished Jun 28 06:12:49 PM PDT 24
Peak memory 206144 kb
Host smart-1466b69c-2d45-42bb-beaa-2590c6de9f17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59962
5689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.599625689
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.219399067
Short name T532
Test name
Test status
Simulation time 252942341 ps
CPU time 1.03 seconds
Started Jun 28 06:12:49 PM PDT 24
Finished Jun 28 06:12:54 PM PDT 24
Peak memory 206072 kb
Host smart-1d89a422-ca16-4744-9b8e-69720a70dccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21939
9067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.219399067
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.3393211868
Short name T1597
Test name
Test status
Simulation time 199458790 ps
CPU time 0.82 seconds
Started Jun 28 06:12:45 PM PDT 24
Finished Jun 28 06:12:48 PM PDT 24
Peak memory 206164 kb
Host smart-79e13aca-2d05-48ad-9920-e4a020b03901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33932
11868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.3393211868
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.2049929786
Short name T1144
Test name
Test status
Simulation time 23341087210 ps
CPU time 22.47 seconds
Started Jun 28 06:12:48 PM PDT 24
Finished Jun 28 06:13:15 PM PDT 24
Peak memory 206308 kb
Host smart-d7e8781e-3053-46eb-adbf-a184e46c53dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20499
29786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.2049929786
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.2340829235
Short name T1902
Test name
Test status
Simulation time 3299060435 ps
CPU time 3.7 seconds
Started Jun 28 06:12:45 PM PDT 24
Finished Jun 28 06:12:52 PM PDT 24
Peak memory 206224 kb
Host smart-0c121570-fb80-4b74-a796-59b2ab8e262d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23408
29235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.2340829235
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.1653285615
Short name T1777
Test name
Test status
Simulation time 11181881935 ps
CPU time 301.3 seconds
Started Jun 28 06:12:46 PM PDT 24
Finished Jun 28 06:17:51 PM PDT 24
Peak memory 206468 kb
Host smart-b3f4e2e7-d921-4d9b-a65b-564d1d430a79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16532
85615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.1653285615
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.130096372
Short name T2126
Test name
Test status
Simulation time 4094493096 ps
CPU time 28.08 seconds
Started Jun 28 06:12:46 PM PDT 24
Finished Jun 28 06:13:18 PM PDT 24
Peak memory 206420 kb
Host smart-0e23b5ad-0db6-4e17-b2b1-34b7fa0ae459
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=130096372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.130096372
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.2870391047
Short name T1163
Test name
Test status
Simulation time 240610723 ps
CPU time 0.92 seconds
Started Jun 28 06:12:45 PM PDT 24
Finished Jun 28 06:12:48 PM PDT 24
Peak memory 206168 kb
Host smart-2339852b-b913-4231-a3c5-ecdb3257edb6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2870391047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.2870391047
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.1568191302
Short name T1202
Test name
Test status
Simulation time 224450209 ps
CPU time 0.9 seconds
Started Jun 28 06:12:46 PM PDT 24
Finished Jun 28 06:12:50 PM PDT 24
Peak memory 206196 kb
Host smart-d897f766-5aac-412c-a0d8-cf440c8eeb7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15681
91302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.1568191302
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.1064361055
Short name T1291
Test name
Test status
Simulation time 4565069405 ps
CPU time 30.56 seconds
Started Jun 28 06:12:44 PM PDT 24
Finished Jun 28 06:13:16 PM PDT 24
Peak memory 206416 kb
Host smart-a04cef51-5a47-4b79-9acd-f8e40787ab9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10643
61055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.1064361055
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.900934554
Short name T1265
Test name
Test status
Simulation time 5237881902 ps
CPU time 46.24 seconds
Started Jun 28 06:12:44 PM PDT 24
Finished Jun 28 06:13:31 PM PDT 24
Peak memory 206492 kb
Host smart-baf66465-78a6-43da-8dca-f99c2ef4fdaf
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=900934554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.900934554
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.778373222
Short name T1904
Test name
Test status
Simulation time 154522179 ps
CPU time 0.81 seconds
Started Jun 28 06:12:47 PM PDT 24
Finished Jun 28 06:12:53 PM PDT 24
Peak memory 206216 kb
Host smart-e32fbe09-2bac-4a68-8ce2-af5798b5fcef
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=778373222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.778373222
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.643407555
Short name T625
Test name
Test status
Simulation time 146747643 ps
CPU time 0.79 seconds
Started Jun 28 06:12:44 PM PDT 24
Finished Jun 28 06:12:46 PM PDT 24
Peak memory 206212 kb
Host smart-6479fad6-b52e-4af1-8195-f99bc201b210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64340
7555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.643407555
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.2813510934
Short name T108
Test name
Test status
Simulation time 204042954 ps
CPU time 0.82 seconds
Started Jun 28 06:12:44 PM PDT 24
Finished Jun 28 06:12:46 PM PDT 24
Peak memory 206180 kb
Host smart-6f2e6940-d21e-4c5e-bae4-39fbc448b030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28135
10934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.2813510934
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.3781196048
Short name T2227
Test name
Test status
Simulation time 239399705 ps
CPU time 0.88 seconds
Started Jun 28 06:12:48 PM PDT 24
Finished Jun 28 06:12:53 PM PDT 24
Peak memory 206192 kb
Host smart-1d5c2d48-472a-423a-8c67-523c4022ab0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37811
96048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.3781196048
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.1416816348
Short name T2148
Test name
Test status
Simulation time 186742304 ps
CPU time 0.8 seconds
Started Jun 28 06:12:46 PM PDT 24
Finished Jun 28 06:12:50 PM PDT 24
Peak memory 206196 kb
Host smart-3c2fb5d9-9da6-43ca-b947-4ebb3c53a8fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14168
16348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.1416816348
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.387597804
Short name T1403
Test name
Test status
Simulation time 143999431 ps
CPU time 0.87 seconds
Started Jun 28 06:12:47 PM PDT 24
Finished Jun 28 06:12:52 PM PDT 24
Peak memory 206196 kb
Host smart-8ce6c916-1b7e-44d2-8fea-517bd40562ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38759
7804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.387597804
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.4138144111
Short name T1549
Test name
Test status
Simulation time 152293592 ps
CPU time 0.83 seconds
Started Jun 28 06:12:46 PM PDT 24
Finished Jun 28 06:12:51 PM PDT 24
Peak memory 206176 kb
Host smart-6afe7a0f-6ae8-497f-8ff3-dcb565cc3f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41381
44111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.4138144111
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.2883480937
Short name T1111
Test name
Test status
Simulation time 195029301 ps
CPU time 0.92 seconds
Started Jun 28 06:12:49 PM PDT 24
Finished Jun 28 06:12:54 PM PDT 24
Peak memory 206164 kb
Host smart-9d0041ef-8ca1-49ef-8296-7e89c3ea7378
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2883480937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.2883480937
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.1949546586
Short name T599
Test name
Test status
Simulation time 154305883 ps
CPU time 0.78 seconds
Started Jun 28 06:12:44 PM PDT 24
Finished Jun 28 06:12:46 PM PDT 24
Peak memory 206196 kb
Host smart-4e7779d4-2775-4024-b352-27071839c374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19495
46586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.1949546586
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.2385168880
Short name T409
Test name
Test status
Simulation time 39347910 ps
CPU time 0.7 seconds
Started Jun 28 06:12:49 PM PDT 24
Finished Jun 28 06:12:54 PM PDT 24
Peak memory 206116 kb
Host smart-ac2b62e1-83eb-4134-a5a4-4eb355bbe85e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23851
68880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.2385168880
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.3552536108
Short name T931
Test name
Test status
Simulation time 15675027624 ps
CPU time 36.48 seconds
Started Jun 28 06:12:45 PM PDT 24
Finished Jun 28 06:13:24 PM PDT 24
Peak memory 206452 kb
Host smart-27e5aeb0-02d9-402b-b8c8-4e77e64bb24a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35525
36108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.3552536108
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.3737307317
Short name T569
Test name
Test status
Simulation time 171123854 ps
CPU time 0.87 seconds
Started Jun 28 06:12:46 PM PDT 24
Finished Jun 28 06:12:50 PM PDT 24
Peak memory 206196 kb
Host smart-fef309d6-1072-479b-a3a4-d304cf4cda29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37373
07317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.3737307317
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.1665415989
Short name T1243
Test name
Test status
Simulation time 171723838 ps
CPU time 0.86 seconds
Started Jun 28 06:12:48 PM PDT 24
Finished Jun 28 06:12:53 PM PDT 24
Peak memory 206212 kb
Host smart-d03aa3d5-4c84-4a5d-a733-dd08ce8c267e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16654
15989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.1665415989
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.2201000902
Short name T1757
Test name
Test status
Simulation time 269650085 ps
CPU time 1.05 seconds
Started Jun 28 06:12:46 PM PDT 24
Finished Jun 28 06:12:51 PM PDT 24
Peak memory 206204 kb
Host smart-97c37d79-1a3b-444b-82a6-781e7272d478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22010
00902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.2201000902
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.3056499597
Short name T2586
Test name
Test status
Simulation time 171225722 ps
CPU time 0.88 seconds
Started Jun 28 06:12:47 PM PDT 24
Finished Jun 28 06:12:53 PM PDT 24
Peak memory 206200 kb
Host smart-d9150d65-bb69-4635-8664-ed13e011ceee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30564
99597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.3056499597
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.4218393717
Short name T1763
Test name
Test status
Simulation time 149337250 ps
CPU time 0.75 seconds
Started Jun 28 06:12:46 PM PDT 24
Finished Jun 28 06:12:50 PM PDT 24
Peak memory 206184 kb
Host smart-a2332f2e-17a3-46e6-b45c-e4e267adb814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42183
93717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.4218393717
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.5341689
Short name T1486
Test name
Test status
Simulation time 161889271 ps
CPU time 0.85 seconds
Started Jun 28 06:12:46 PM PDT 24
Finished Jun 28 06:12:51 PM PDT 24
Peak memory 206196 kb
Host smart-462f3790-569d-42f3-ad86-c7e09a5393fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53416
89 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.5341689
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.1074252013
Short name T1806
Test name
Test status
Simulation time 161795572 ps
CPU time 0.81 seconds
Started Jun 28 06:12:45 PM PDT 24
Finished Jun 28 06:12:48 PM PDT 24
Peak memory 206192 kb
Host smart-4b3df7ea-4694-4fb5-a7f9-32510a80d43c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10742
52013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.1074252013
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.2891873762
Short name T2145
Test name
Test status
Simulation time 226390283 ps
CPU time 0.95 seconds
Started Jun 28 06:12:47 PM PDT 24
Finished Jun 28 06:12:52 PM PDT 24
Peak memory 206188 kb
Host smart-e5b435a7-b4cb-418d-8393-fcf8ca4bea9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28918
73762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.2891873762
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.496498893
Short name T1796
Test name
Test status
Simulation time 5217845768 ps
CPU time 139.99 seconds
Started Jun 28 06:12:45 PM PDT 24
Finished Jun 28 06:15:09 PM PDT 24
Peak memory 206472 kb
Host smart-61d4dac2-f08b-41f9-877b-d8a0bc593be3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=496498893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.496498893
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.1436757847
Short name T1546
Test name
Test status
Simulation time 159424823 ps
CPU time 0.78 seconds
Started Jun 28 06:12:47 PM PDT 24
Finished Jun 28 06:12:52 PM PDT 24
Peak memory 206332 kb
Host smart-ca1be47c-be97-4cc5-8479-453541e6ee28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14367
57847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.1436757847
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.512041477
Short name T611
Test name
Test status
Simulation time 161135113 ps
CPU time 0.93 seconds
Started Jun 28 06:12:46 PM PDT 24
Finished Jun 28 06:12:50 PM PDT 24
Peak memory 206192 kb
Host smart-b5004d28-0af1-42d6-ae81-39cfcd88bd49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51204
1477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.512041477
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.571076066
Short name T2425
Test name
Test status
Simulation time 4523651138 ps
CPU time 32.91 seconds
Started Jun 28 06:12:46 PM PDT 24
Finished Jun 28 06:13:23 PM PDT 24
Peak memory 206440 kb
Host smart-60fc7e05-64dc-40e6-a555-5b68b343b886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57107
6066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.571076066
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.3557844882
Short name T11
Test name
Test status
Simulation time 4273571588 ps
CPU time 5.79 seconds
Started Jun 28 06:12:44 PM PDT 24
Finished Jun 28 06:12:52 PM PDT 24
Peak memory 206340 kb
Host smart-5183b1b1-2a8b-4f68-8d3f-f0187849a58f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3557844882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.3557844882
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.3492300212
Short name T229
Test name
Test status
Simulation time 13377403133 ps
CPU time 12.07 seconds
Started Jun 28 06:12:48 PM PDT 24
Finished Jun 28 06:13:04 PM PDT 24
Peak memory 206436 kb
Host smart-8476d9fe-cf7e-4ea3-a2cd-3cf91f9ae041
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3492300212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.3492300212
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.1464853801
Short name T12
Test name
Test status
Simulation time 23343439033 ps
CPU time 24.01 seconds
Started Jun 28 06:12:47 PM PDT 24
Finished Jun 28 06:13:15 PM PDT 24
Peak memory 206348 kb
Host smart-d145efba-8e8e-4a62-8ee0-c4f2486c7903
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1464853801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.1464853801
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.3937341233
Short name T563
Test name
Test status
Simulation time 151020568 ps
CPU time 0.79 seconds
Started Jun 28 06:13:01 PM PDT 24
Finished Jun 28 06:13:08 PM PDT 24
Peak memory 206320 kb
Host smart-7d28b6dd-099e-4580-9290-e29792288999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39373
41233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.3937341233
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.4227169031
Short name T1289
Test name
Test status
Simulation time 152929276 ps
CPU time 0.82 seconds
Started Jun 28 06:13:02 PM PDT 24
Finished Jun 28 06:13:10 PM PDT 24
Peak memory 206188 kb
Host smart-99c355df-a2bf-4caa-995b-db1a5249c155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42271
69031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.4227169031
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.2604168312
Short name T2293
Test name
Test status
Simulation time 318816598 ps
CPU time 1.29 seconds
Started Jun 28 06:12:59 PM PDT 24
Finished Jun 28 06:13:02 PM PDT 24
Peak memory 206192 kb
Host smart-ef6ece2e-5689-4063-9dab-ab0b50cffe79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26041
68312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.2604168312
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.1454274172
Short name T1724
Test name
Test status
Simulation time 287898481 ps
CPU time 1.08 seconds
Started Jun 28 06:13:00 PM PDT 24
Finished Jun 28 06:13:06 PM PDT 24
Peak memory 206132 kb
Host smart-83ea043d-4121-4fa2-b00b-b31729639955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14542
74172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.1454274172
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.536526345
Short name T2372
Test name
Test status
Simulation time 21578639421 ps
CPU time 41.79 seconds
Started Jun 28 06:13:02 PM PDT 24
Finished Jun 28 06:13:51 PM PDT 24
Peak memory 206312 kb
Host smart-b82ba122-9346-447f-a518-76d190ac1675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53652
6345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.536526345
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.4100639661
Short name T2427
Test name
Test status
Simulation time 392360863 ps
CPU time 1.28 seconds
Started Jun 28 06:13:01 PM PDT 24
Finished Jun 28 06:13:09 PM PDT 24
Peak memory 206164 kb
Host smart-aa627d17-d736-482f-8aeb-b2f62e6f36f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41006
39661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.4100639661
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.3684713944
Short name T2014
Test name
Test status
Simulation time 152615868 ps
CPU time 0.76 seconds
Started Jun 28 06:12:58 PM PDT 24
Finished Jun 28 06:13:00 PM PDT 24
Peak memory 206172 kb
Host smart-df4f0c43-4cbf-485e-bd33-d7e9ef0c5897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36847
13944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.3684713944
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.4225954615
Short name T2318
Test name
Test status
Simulation time 57442246 ps
CPU time 0.66 seconds
Started Jun 28 06:13:00 PM PDT 24
Finished Jun 28 06:13:06 PM PDT 24
Peak memory 206120 kb
Host smart-a57ad599-8225-42fa-a6f6-94f0cdd2b974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42259
54615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.4225954615
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.34484014
Short name T1066
Test name
Test status
Simulation time 867296639 ps
CPU time 2.06 seconds
Started Jun 28 06:13:01 PM PDT 24
Finished Jun 28 06:13:10 PM PDT 24
Peak memory 206332 kb
Host smart-4dcba45e-9653-46a2-898f-1765d52122ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34484
014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.34484014
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.2642204018
Short name T1651
Test name
Test status
Simulation time 246661321 ps
CPU time 1.7 seconds
Started Jun 28 06:13:02 PM PDT 24
Finished Jun 28 06:13:10 PM PDT 24
Peak memory 206260 kb
Host smart-2029084d-70b3-4b0c-bdd9-d90d4eb4a327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26422
04018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.2642204018
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.4177028009
Short name T1193
Test name
Test status
Simulation time 217034176 ps
CPU time 0.89 seconds
Started Jun 28 06:12:59 PM PDT 24
Finished Jun 28 06:13:02 PM PDT 24
Peak memory 206188 kb
Host smart-7d4d417f-106d-4331-a465-35352c5addf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41770
28009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.4177028009
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.1434023848
Short name T2067
Test name
Test status
Simulation time 171716452 ps
CPU time 0.86 seconds
Started Jun 28 06:13:01 PM PDT 24
Finished Jun 28 06:13:06 PM PDT 24
Peak memory 206204 kb
Host smart-9db96bce-9d37-44b5-a907-712637f80949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14340
23848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.1434023848
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.735260678
Short name T908
Test name
Test status
Simulation time 232254033 ps
CPU time 0.98 seconds
Started Jun 28 06:13:01 PM PDT 24
Finished Jun 28 06:13:08 PM PDT 24
Peak memory 206208 kb
Host smart-f14ae690-4015-441a-ad80-235013c539df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73526
0678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.735260678
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_invalid_sync.1641714599
Short name T1297
Test name
Test status
Simulation time 9098997664 ps
CPU time 67.17 seconds
Started Jun 28 06:13:02 PM PDT 24
Finished Jun 28 06:14:17 PM PDT 24
Peak memory 206484 kb
Host smart-fa6a10d9-e5e7-4d41-83d1-8b7bfb39b80f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1641714599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.1641714599
Directory /workspace/28.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.4077466825
Short name T1380
Test name
Test status
Simulation time 171393499 ps
CPU time 0.92 seconds
Started Jun 28 06:13:02 PM PDT 24
Finished Jun 28 06:13:10 PM PDT 24
Peak memory 206184 kb
Host smart-8f351451-53dc-4d60-8a55-b0666951175d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40774
66825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.4077466825
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.691752806
Short name T2046
Test name
Test status
Simulation time 23337741852 ps
CPU time 28.78 seconds
Started Jun 28 06:12:57 PM PDT 24
Finished Jun 28 06:13:27 PM PDT 24
Peak memory 206280 kb
Host smart-d2152395-a8f9-4573-b899-b310dd3070f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69175
2806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.691752806
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.3765356171
Short name T700
Test name
Test status
Simulation time 3289685470 ps
CPU time 4 seconds
Started Jun 28 06:13:01 PM PDT 24
Finished Jun 28 06:13:12 PM PDT 24
Peak memory 206228 kb
Host smart-3d46b603-4d27-418f-977b-157be626e4fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37653
56171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.3765356171
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.1255962557
Short name T2233
Test name
Test status
Simulation time 8659516341 ps
CPU time 61.61 seconds
Started Jun 28 06:13:02 PM PDT 24
Finished Jun 28 06:14:11 PM PDT 24
Peak memory 206424 kb
Host smart-78dad577-a8ec-4c33-869a-2c7727d8ab71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12559
62557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.1255962557
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.2903619720
Short name T1523
Test name
Test status
Simulation time 5580768843 ps
CPU time 37.69 seconds
Started Jun 28 06:13:00 PM PDT 24
Finished Jun 28 06:13:43 PM PDT 24
Peak memory 206400 kb
Host smart-1af7e2b0-b061-482e-95aa-dc7a1bf8ad6d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2903619720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.2903619720
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.1998567330
Short name T1032
Test name
Test status
Simulation time 243954106 ps
CPU time 0.95 seconds
Started Jun 28 06:13:01 PM PDT 24
Finished Jun 28 06:13:08 PM PDT 24
Peak memory 206204 kb
Host smart-55476985-d68e-4b5c-a086-67dc420018b1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1998567330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.1998567330
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.3298739589
Short name T2597
Test name
Test status
Simulation time 186393014 ps
CPU time 0.84 seconds
Started Jun 28 06:12:58 PM PDT 24
Finished Jun 28 06:13:00 PM PDT 24
Peak memory 206184 kb
Host smart-5c48f96a-aa2c-4d2a-a0d6-55b7f2af3d42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32987
39589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.3298739589
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.3933330855
Short name T1767
Test name
Test status
Simulation time 4597644090 ps
CPU time 43.93 seconds
Started Jun 28 06:12:59 PM PDT 24
Finished Jun 28 06:13:46 PM PDT 24
Peak memory 206500 kb
Host smart-fa320200-ca7c-4c9e-a815-1548e50f4aa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39333
30855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.3933330855
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.3057842183
Short name T644
Test name
Test status
Simulation time 4919235218 ps
CPU time 36.86 seconds
Started Jun 28 06:12:58 PM PDT 24
Finished Jun 28 06:13:36 PM PDT 24
Peak memory 206496 kb
Host smart-bf4fee5c-430f-4ae3-aa98-5939b7ea73d3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3057842183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.3057842183
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.306994648
Short name T2214
Test name
Test status
Simulation time 146569534 ps
CPU time 0.81 seconds
Started Jun 28 06:13:01 PM PDT 24
Finished Jun 28 06:13:08 PM PDT 24
Peak memory 205952 kb
Host smart-c2a19152-0aa3-43c4-95db-a0dc7e4d3ec5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=306994648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.306994648
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.2412811368
Short name T1058
Test name
Test status
Simulation time 172438044 ps
CPU time 0.8 seconds
Started Jun 28 06:13:02 PM PDT 24
Finished Jun 28 06:13:10 PM PDT 24
Peak memory 206196 kb
Host smart-7adf6f20-975e-432d-bd0d-e10039099f51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24128
11368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.2412811368
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.739105887
Short name T1424
Test name
Test status
Simulation time 183850566 ps
CPU time 0.85 seconds
Started Jun 28 06:13:00 PM PDT 24
Finished Jun 28 06:13:06 PM PDT 24
Peak memory 206180 kb
Host smart-5f261e3a-cedf-4427-8623-8054a1ecd858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73910
5887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.739105887
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.2860756465
Short name T1993
Test name
Test status
Simulation time 188140909 ps
CPU time 0.89 seconds
Started Jun 28 06:13:00 PM PDT 24
Finished Jun 28 06:13:04 PM PDT 24
Peak memory 206212 kb
Host smart-5711fea0-aaad-44ef-9da6-9f6781ebdf01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28607
56465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.2860756465
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.2077988305
Short name T825
Test name
Test status
Simulation time 183804120 ps
CPU time 0.85 seconds
Started Jun 28 06:12:59 PM PDT 24
Finished Jun 28 06:13:03 PM PDT 24
Peak memory 206196 kb
Host smart-50bff791-fb73-46a4-82c4-5d5cda07aa5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20779
88305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.2077988305
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.1627944114
Short name T1933
Test name
Test status
Simulation time 195385511 ps
CPU time 0.84 seconds
Started Jun 28 06:12:58 PM PDT 24
Finished Jun 28 06:13:01 PM PDT 24
Peak memory 206200 kb
Host smart-cfd8fd73-7152-4912-9ec9-6899458ec3c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16279
44114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.1627944114
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.3234696356
Short name T1575
Test name
Test status
Simulation time 153077955 ps
CPU time 0.83 seconds
Started Jun 28 06:13:00 PM PDT 24
Finished Jun 28 06:13:06 PM PDT 24
Peak memory 206196 kb
Host smart-9c53e06d-27cd-47c9-8fe2-73a56a01b23c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32346
96356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.3234696356
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.95550883
Short name T2057
Test name
Test status
Simulation time 200196434 ps
CPU time 0.94 seconds
Started Jun 28 06:13:00 PM PDT 24
Finished Jun 28 06:13:06 PM PDT 24
Peak memory 206216 kb
Host smart-ba37de9e-3b23-46d1-a9af-1cc3d5548236
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=95550883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.95550883
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.1205719479
Short name T2553
Test name
Test status
Simulation time 133152723 ps
CPU time 0.77 seconds
Started Jun 28 06:13:03 PM PDT 24
Finished Jun 28 06:13:11 PM PDT 24
Peak memory 206196 kb
Host smart-3b63a33e-9155-47fe-8946-2d8dd53d1490
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12057
19479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.1205719479
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.2575045113
Short name T1367
Test name
Test status
Simulation time 46796149 ps
CPU time 0.68 seconds
Started Jun 28 06:13:05 PM PDT 24
Finished Jun 28 06:13:12 PM PDT 24
Peak memory 206204 kb
Host smart-f179314d-74ea-43c1-8ce5-c30716bd1a44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25750
45113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.2575045113
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.2442235743
Short name T2468
Test name
Test status
Simulation time 15532983041 ps
CPU time 33.51 seconds
Started Jun 28 06:13:01 PM PDT 24
Finished Jun 28 06:13:40 PM PDT 24
Peak memory 206204 kb
Host smart-85775747-6cae-469f-b502-810c78f0bc4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24422
35743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.2442235743
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.481971440
Short name T2157
Test name
Test status
Simulation time 159956407 ps
CPU time 0.83 seconds
Started Jun 28 06:13:01 PM PDT 24
Finished Jun 28 06:13:08 PM PDT 24
Peak memory 206188 kb
Host smart-58401c4b-4a41-433d-b129-1a3d64ec7769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48197
1440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.481971440
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.2326363137
Short name T2388
Test name
Test status
Simulation time 183232510 ps
CPU time 0.87 seconds
Started Jun 28 06:12:59 PM PDT 24
Finished Jun 28 06:13:03 PM PDT 24
Peak memory 206188 kb
Host smart-fb686431-1aa2-430b-a418-bbec996dc382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23263
63137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.2326363137
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.2820057388
Short name T1485
Test name
Test status
Simulation time 212240095 ps
CPU time 0.88 seconds
Started Jun 28 06:13:01 PM PDT 24
Finished Jun 28 06:13:07 PM PDT 24
Peak memory 206212 kb
Host smart-a1d1c93b-997b-4191-ac3f-a1f473c30e08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28200
57388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.2820057388
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.1643109072
Short name T2220
Test name
Test status
Simulation time 174398078 ps
CPU time 0.88 seconds
Started Jun 28 06:13:00 PM PDT 24
Finished Jun 28 06:13:06 PM PDT 24
Peak memory 206136 kb
Host smart-3e9be253-2a9b-43ae-ad40-28695896b9b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16431
09072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.1643109072
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.4099718218
Short name T2413
Test name
Test status
Simulation time 161987965 ps
CPU time 0.79 seconds
Started Jun 28 06:12:59 PM PDT 24
Finished Jun 28 06:13:03 PM PDT 24
Peak memory 206176 kb
Host smart-2f574fa6-3696-4e38-a21e-f4ef4a894e58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40997
18218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.4099718218
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.3918748728
Short name T1113
Test name
Test status
Simulation time 156675059 ps
CPU time 0.79 seconds
Started Jun 28 06:13:00 PM PDT 24
Finished Jun 28 06:13:06 PM PDT 24
Peak memory 206148 kb
Host smart-3c8fc562-8799-4604-af16-edf4f8316e66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39187
48728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.3918748728
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.3304343268
Short name T1478
Test name
Test status
Simulation time 151670939 ps
CPU time 0.8 seconds
Started Jun 28 06:13:02 PM PDT 24
Finished Jun 28 06:13:10 PM PDT 24
Peak memory 206192 kb
Host smart-31e4a0fd-3c6e-4e09-b598-bf0b519722a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33043
43268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.3304343268
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.2526089316
Short name T981
Test name
Test status
Simulation time 233288774 ps
CPU time 0.95 seconds
Started Jun 28 06:13:01 PM PDT 24
Finished Jun 28 06:13:08 PM PDT 24
Peak memory 206216 kb
Host smart-e940b8ca-7eb4-4910-b2aa-bb33626f870c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25260
89316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.2526089316
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.2976347625
Short name T395
Test name
Test status
Simulation time 3947604796 ps
CPU time 36.92 seconds
Started Jun 28 06:12:59 PM PDT 24
Finished Jun 28 06:13:37 PM PDT 24
Peak memory 206396 kb
Host smart-69336809-e100-4393-991a-a306492907ca
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2976347625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.2976347625
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.3857946626
Short name T2525
Test name
Test status
Simulation time 150816453 ps
CPU time 0.81 seconds
Started Jun 28 06:13:00 PM PDT 24
Finished Jun 28 06:13:04 PM PDT 24
Peak memory 206192 kb
Host smart-51df44f2-4a69-4d45-a5ca-c6d306e4b86a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38579
46626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.3857946626
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.4108105972
Short name T758
Test name
Test status
Simulation time 173089470 ps
CPU time 0.8 seconds
Started Jun 28 06:12:59 PM PDT 24
Finished Jun 28 06:13:02 PM PDT 24
Peak memory 206192 kb
Host smart-ee168b33-8d9a-41c2-bc87-f150812da910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41081
05972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.4108105972
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.1006425188
Short name T1783
Test name
Test status
Simulation time 2774653810 ps
CPU time 26.39 seconds
Started Jun 28 06:13:02 PM PDT 24
Finished Jun 28 06:13:35 PM PDT 24
Peak memory 206432 kb
Host smart-fad8903a-fcf7-4c6c-8630-88a27417fe32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10064
25188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.1006425188
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.3614619326
Short name T1529
Test name
Test status
Simulation time 39635742 ps
CPU time 0.66 seconds
Started Jun 28 06:13:12 PM PDT 24
Finished Jun 28 06:13:17 PM PDT 24
Peak memory 206216 kb
Host smart-2fb09076-7c0f-4c71-9e5e-057395d7fbc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3614619326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.3614619326
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.570336014
Short name T685
Test name
Test status
Simulation time 3749449850 ps
CPU time 5.36 seconds
Started Jun 28 06:13:01 PM PDT 24
Finished Jun 28 06:13:13 PM PDT 24
Peak memory 206248 kb
Host smart-73036b4d-f86f-48b9-84d6-43be5406e189
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=570336014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.570336014
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.3102774876
Short name T2112
Test name
Test status
Simulation time 13304203878 ps
CPU time 12.64 seconds
Started Jun 28 06:12:59 PM PDT 24
Finished Jun 28 06:13:15 PM PDT 24
Peak memory 206324 kb
Host smart-2d2bc647-38a5-4cf2-ae4b-33d340d64475
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3102774876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.3102774876
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.3021005143
Short name T14
Test name
Test status
Simulation time 23418548656 ps
CPU time 22.68 seconds
Started Jun 28 06:13:02 PM PDT 24
Finished Jun 28 06:13:32 PM PDT 24
Peak memory 206316 kb
Host smart-e78a3308-e077-4caf-acc6-a2a17c5b7d1e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3021005143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.3021005143
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.619811734
Short name T2604
Test name
Test status
Simulation time 174940010 ps
CPU time 0.89 seconds
Started Jun 28 06:13:00 PM PDT 24
Finished Jun 28 06:13:04 PM PDT 24
Peak memory 206352 kb
Host smart-201aba17-733a-4ebd-b423-ecdb735df8d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61981
1734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.619811734
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.2254202901
Short name T1859
Test name
Test status
Simulation time 149347368 ps
CPU time 0.76 seconds
Started Jun 28 06:12:58 PM PDT 24
Finished Jun 28 06:13:00 PM PDT 24
Peak memory 206180 kb
Host smart-967fcfd0-4739-4e2f-b909-5c4a38175dab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22542
02901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.2254202901
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.1426326067
Short name T1958
Test name
Test status
Simulation time 364905628 ps
CPU time 1.15 seconds
Started Jun 28 06:13:01 PM PDT 24
Finished Jun 28 06:13:08 PM PDT 24
Peak memory 206180 kb
Host smart-16b426e2-8666-44f6-a98f-6cac113eedb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14263
26067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.1426326067
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_device_address.2031766212
Short name T2558
Test name
Test status
Simulation time 23441694710 ps
CPU time 45.61 seconds
Started Jun 28 06:13:05 PM PDT 24
Finished Jun 28 06:13:58 PM PDT 24
Peak memory 206348 kb
Host smart-e0150c97-dea8-4c0f-8054-54145f647f9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20317
66212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.2031766212
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.4232662626
Short name T1158
Test name
Test status
Simulation time 321055699 ps
CPU time 1.08 seconds
Started Jun 28 06:12:59 PM PDT 24
Finished Jun 28 06:13:01 PM PDT 24
Peak memory 206196 kb
Host smart-1bfe94ae-d518-44ca-a2c9-362a9b0159b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42326
62626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.4232662626
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.3245288754
Short name T36
Test name
Test status
Simulation time 167501454 ps
CPU time 0.8 seconds
Started Jun 28 06:13:02 PM PDT 24
Finished Jun 28 06:13:10 PM PDT 24
Peak memory 206188 kb
Host smart-a182e7fe-8a71-4066-9e19-37bb4329bc3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32452
88754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.3245288754
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.1578779348
Short name T1776
Test name
Test status
Simulation time 41119289 ps
CPU time 0.68 seconds
Started Jun 28 06:13:03 PM PDT 24
Finished Jun 28 06:13:11 PM PDT 24
Peak memory 206184 kb
Host smart-70244c4f-ade8-413e-ab3d-4028776154d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15787
79348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.1578779348
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.96602644
Short name T1784
Test name
Test status
Simulation time 841980689 ps
CPU time 2.21 seconds
Started Jun 28 06:13:00 PM PDT 24
Finished Jun 28 06:13:06 PM PDT 24
Peak memory 206332 kb
Host smart-d5baaf24-a1ae-46a4-96c7-37ed6f200f90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96602
644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.96602644
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.1417128711
Short name T2007
Test name
Test status
Simulation time 175179725 ps
CPU time 1.29 seconds
Started Jun 28 06:13:03 PM PDT 24
Finished Jun 28 06:13:12 PM PDT 24
Peak memory 206284 kb
Host smart-a9323721-20f3-40ba-b79f-63d693f4a943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14171
28711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.1417128711
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.3102742764
Short name T2184
Test name
Test status
Simulation time 186814630 ps
CPU time 0.87 seconds
Started Jun 28 06:13:04 PM PDT 24
Finished Jun 28 06:13:12 PM PDT 24
Peak memory 206196 kb
Host smart-f3b48e3a-8d9f-4e52-9b8d-d1722f4190df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31027
42764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.3102742764
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.2558806798
Short name T1035
Test name
Test status
Simulation time 141293389 ps
CPU time 0.75 seconds
Started Jun 28 06:13:05 PM PDT 24
Finished Jun 28 06:13:13 PM PDT 24
Peak memory 206140 kb
Host smart-75671e01-3085-44b4-b25f-92512fa59fd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25588
06798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.2558806798
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.3380950934
Short name T2631
Test name
Test status
Simulation time 245256007 ps
CPU time 0.94 seconds
Started Jun 28 06:13:03 PM PDT 24
Finished Jun 28 06:13:11 PM PDT 24
Peak memory 206136 kb
Host smart-8a18cd1f-5f9c-4c71-9c64-36c8f61b20c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33809
50934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.3380950934
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_invalid_sync.2378830061
Short name T1714
Test name
Test status
Simulation time 4706794363 ps
CPU time 40.95 seconds
Started Jun 28 06:13:05 PM PDT 24
Finished Jun 28 06:13:53 PM PDT 24
Peak memory 206404 kb
Host smart-0267aace-1c0e-4ddb-8d81-83591ef58b53
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2378830061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_invalid_sync.2378830061
Directory /workspace/29.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.3046715846
Short name T1987
Test name
Test status
Simulation time 218067565 ps
CPU time 0.89 seconds
Started Jun 28 06:13:01 PM PDT 24
Finished Jun 28 06:13:08 PM PDT 24
Peak memory 206188 kb
Host smart-2f57d0b9-2d1d-4a37-bfba-f0f148f5844f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30467
15846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.3046715846
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.220597678
Short name T2383
Test name
Test status
Simulation time 23267613007 ps
CPU time 22.95 seconds
Started Jun 28 06:13:05 PM PDT 24
Finished Jun 28 06:13:34 PM PDT 24
Peak memory 206308 kb
Host smart-217368e7-76c9-4dc9-a71f-5e9cb59b9d9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22059
7678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.220597678
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.2621633720
Short name T2462
Test name
Test status
Simulation time 3287390601 ps
CPU time 4.24 seconds
Started Jun 28 06:13:04 PM PDT 24
Finished Jun 28 06:13:16 PM PDT 24
Peak memory 206164 kb
Host smart-da554d56-495c-4f0b-8a49-5c3f2a612735
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26216
33720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.2621633720
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.2663011087
Short name T723
Test name
Test status
Simulation time 10740157696 ps
CPU time 297.04 seconds
Started Jun 28 06:13:02 PM PDT 24
Finished Jun 28 06:18:07 PM PDT 24
Peak memory 206468 kb
Host smart-73294bb6-d62c-40f1-a2cc-fd3ed32fe467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26630
11087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.2663011087
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.3844591741
Short name T1846
Test name
Test status
Simulation time 2851358728 ps
CPU time 74.14 seconds
Started Jun 28 06:13:06 PM PDT 24
Finished Jun 28 06:14:27 PM PDT 24
Peak memory 206452 kb
Host smart-8181aa32-c021-4a6a-9f2a-79d94c5f31e5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3844591741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.3844591741
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.1305155559
Short name T350
Test name
Test status
Simulation time 249444891 ps
CPU time 0.94 seconds
Started Jun 28 06:13:06 PM PDT 24
Finished Jun 28 06:13:14 PM PDT 24
Peak memory 206216 kb
Host smart-385044b5-7b61-4e67-acc7-04ff406e2e55
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1305155559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.1305155559
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.3307759820
Short name T2200
Test name
Test status
Simulation time 189874490 ps
CPU time 0.96 seconds
Started Jun 28 06:13:04 PM PDT 24
Finished Jun 28 06:13:12 PM PDT 24
Peak memory 206128 kb
Host smart-08623fd1-d6fb-4201-9b94-a5a184b6c215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33077
59820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.3307759820
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.2205700169
Short name T1827
Test name
Test status
Simulation time 4971413231 ps
CPU time 144.86 seconds
Started Jun 28 06:13:02 PM PDT 24
Finished Jun 28 06:15:34 PM PDT 24
Peak memory 206456 kb
Host smart-bff95979-8ce3-4d1a-b9f9-dd7902c25a26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22057
00169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.2205700169
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.3625134041
Short name T417
Test name
Test status
Simulation time 4473661280 ps
CPU time 122.32 seconds
Started Jun 28 06:13:02 PM PDT 24
Finished Jun 28 06:15:11 PM PDT 24
Peak memory 206432 kb
Host smart-205bf9d9-bc1b-4151-85db-61a096ad1789
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3625134041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.3625134041
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.3034717574
Short name T581
Test name
Test status
Simulation time 170071553 ps
CPU time 0.81 seconds
Started Jun 28 06:13:01 PM PDT 24
Finished Jun 28 06:13:09 PM PDT 24
Peak memory 206180 kb
Host smart-b0656b08-e42c-4f27-8ba5-e1e0f3c09d94
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3034717574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.3034717574
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.2434642575
Short name T1145
Test name
Test status
Simulation time 136966886 ps
CPU time 0.86 seconds
Started Jun 28 06:13:01 PM PDT 24
Finished Jun 28 06:13:08 PM PDT 24
Peak memory 206200 kb
Host smart-472f9d74-24fc-4ce1-917d-7f484acce9cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24346
42575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.2434642575
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.3730621881
Short name T2195
Test name
Test status
Simulation time 231597462 ps
CPU time 0.91 seconds
Started Jun 28 06:13:03 PM PDT 24
Finished Jun 28 06:13:11 PM PDT 24
Peak memory 206188 kb
Host smart-9981af93-db2f-4300-9bad-4539834950dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37306
21881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.3730621881
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.3209916525
Short name T87
Test name
Test status
Simulation time 189138359 ps
CPU time 0.86 seconds
Started Jun 28 06:13:05 PM PDT 24
Finished Jun 28 06:13:12 PM PDT 24
Peak memory 206132 kb
Host smart-097ee0cc-68f3-4c68-9eea-0095828ad091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32099
16525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.3209916525
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.479938117
Short name T1174
Test name
Test status
Simulation time 190401064 ps
CPU time 0.79 seconds
Started Jun 28 06:13:01 PM PDT 24
Finished Jun 28 06:13:08 PM PDT 24
Peak memory 206208 kb
Host smart-007ec195-e407-4097-88af-f4c438acfcc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47993
8117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.479938117
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.1357222474
Short name T2508
Test name
Test status
Simulation time 158307690 ps
CPU time 0.79 seconds
Started Jun 28 06:13:01 PM PDT 24
Finished Jun 28 06:13:09 PM PDT 24
Peak memory 206292 kb
Host smart-60c4125c-dcb7-4202-9089-0602c0d592f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13572
22474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.1357222474
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.95637757
Short name T2190
Test name
Test status
Simulation time 194492558 ps
CPU time 0.84 seconds
Started Jun 28 06:13:02 PM PDT 24
Finished Jun 28 06:13:10 PM PDT 24
Peak memory 206216 kb
Host smart-3feb233c-0f24-4ef8-90e4-f40c2e01c22d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95637
757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.95637757
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.1185447523
Short name T733
Test name
Test status
Simulation time 230296838 ps
CPU time 0.96 seconds
Started Jun 28 06:13:01 PM PDT 24
Finished Jun 28 06:13:09 PM PDT 24
Peak memory 206272 kb
Host smart-46b78b6e-c12d-4189-9f8c-3717b4a1416b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1185447523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.1185447523
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.2218143504
Short name T2245
Test name
Test status
Simulation time 166757385 ps
CPU time 0.77 seconds
Started Jun 28 06:13:03 PM PDT 24
Finished Jun 28 06:13:11 PM PDT 24
Peak memory 206196 kb
Host smart-dc57ae96-fb8e-4131-96eb-ca1a08da5a68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22181
43504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.2218143504
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.2103998015
Short name T33
Test name
Test status
Simulation time 41139923 ps
CPU time 0.68 seconds
Started Jun 28 06:13:02 PM PDT 24
Finished Jun 28 06:13:10 PM PDT 24
Peak memory 206204 kb
Host smart-fd7fb6e0-995e-4e16-ad03-73d5b5e75c1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21039
98015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.2103998015
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.4015462492
Short name T2037
Test name
Test status
Simulation time 14596290070 ps
CPU time 32.87 seconds
Started Jun 28 06:13:02 PM PDT 24
Finished Jun 28 06:13:42 PM PDT 24
Peak memory 206428 kb
Host smart-32c7fd16-243d-4506-8318-3c3eb5b6f5ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40154
62492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.4015462492
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.1134864404
Short name T2435
Test name
Test status
Simulation time 182740247 ps
CPU time 0.9 seconds
Started Jun 28 06:13:04 PM PDT 24
Finished Jun 28 06:13:12 PM PDT 24
Peak memory 206188 kb
Host smart-487399ff-4cce-4499-98f4-a939dc31e800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11348
64404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.1134864404
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.4192991116
Short name T1769
Test name
Test status
Simulation time 234664510 ps
CPU time 0.92 seconds
Started Jun 28 06:13:02 PM PDT 24
Finished Jun 28 06:13:10 PM PDT 24
Peak memory 206216 kb
Host smart-c8449861-5fbf-4af9-a747-635538a75770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41929
91116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.4192991116
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.2975872258
Short name T2454
Test name
Test status
Simulation time 193742139 ps
CPU time 0.84 seconds
Started Jun 28 06:13:06 PM PDT 24
Finished Jun 28 06:13:14 PM PDT 24
Peak memory 206216 kb
Host smart-7cb58d8e-e208-4173-9e2f-a21dfba034f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29758
72258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.2975872258
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.1226978572
Short name T804
Test name
Test status
Simulation time 140718940 ps
CPU time 0.75 seconds
Started Jun 28 06:13:05 PM PDT 24
Finished Jun 28 06:13:13 PM PDT 24
Peak memory 206176 kb
Host smart-9f78d0a3-4f93-47a3-a323-922b6f5e11c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12269
78572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.1226978572
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.68831515
Short name T2548
Test name
Test status
Simulation time 149632081 ps
CPU time 0.82 seconds
Started Jun 28 06:13:05 PM PDT 24
Finished Jun 28 06:13:12 PM PDT 24
Peak memory 206112 kb
Host smart-ae5db8c7-780c-451d-9f32-cc7cd71553d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68831
515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.68831515
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.1361449884
Short name T1162
Test name
Test status
Simulation time 217100784 ps
CPU time 0.89 seconds
Started Jun 28 06:13:06 PM PDT 24
Finished Jun 28 06:13:14 PM PDT 24
Peak memory 206188 kb
Host smart-5ac250a4-b3d4-4270-af67-63d09534867b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13614
49884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.1361449884
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.1074548953
Short name T1688
Test name
Test status
Simulation time 152348588 ps
CPU time 0.77 seconds
Started Jun 28 06:13:03 PM PDT 24
Finished Jun 28 06:13:11 PM PDT 24
Peak memory 206152 kb
Host smart-c8830aff-eb73-4946-baca-9324773bc727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10745
48953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.1074548953
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.2182827661
Short name T960
Test name
Test status
Simulation time 221356361 ps
CPU time 0.95 seconds
Started Jun 28 06:13:01 PM PDT 24
Finished Jun 28 06:13:08 PM PDT 24
Peak memory 206216 kb
Host smart-fa3c3ba0-96a3-44c5-a4bf-a95567228358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21828
27661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.2182827661
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.591922462
Short name T1152
Test name
Test status
Simulation time 5192017310 ps
CPU time 145.5 seconds
Started Jun 28 06:13:03 PM PDT 24
Finished Jun 28 06:15:35 PM PDT 24
Peak memory 206532 kb
Host smart-0c2c83b6-5ab6-4dcc-be1c-aad695ff5adb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=591922462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.591922462
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.2408629480
Short name T791
Test name
Test status
Simulation time 174206131 ps
CPU time 0.84 seconds
Started Jun 28 06:13:04 PM PDT 24
Finished Jun 28 06:13:12 PM PDT 24
Peak memory 206216 kb
Host smart-e793c8cf-00eb-4162-aa63-ac54d57c3deb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24086
29480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.2408629480
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.1126649808
Short name T1435
Test name
Test status
Simulation time 202414840 ps
CPU time 0.83 seconds
Started Jun 28 06:13:05 PM PDT 24
Finished Jun 28 06:13:12 PM PDT 24
Peak memory 206188 kb
Host smart-0bbbcba8-5041-48ab-af1f-2054ac93571c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11266
49808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.1126649808
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.3466815890
Short name T2226
Test name
Test status
Simulation time 6048534951 ps
CPU time 42.14 seconds
Started Jun 28 06:13:05 PM PDT 24
Finished Jun 28 06:13:54 PM PDT 24
Peak memory 206348 kb
Host smart-18b06d7b-d80d-44c8-b5f3-ce77159ef0ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34668
15890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.3466815890
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.1340254413
Short name T373
Test name
Test status
Simulation time 39970292 ps
CPU time 0.69 seconds
Started Jun 28 06:08:56 PM PDT 24
Finished Jun 28 06:09:01 PM PDT 24
Peak memory 206188 kb
Host smart-f7e57b8f-6d27-41a9-a986-d3f9753f12b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1340254413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.1340254413
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.1458691682
Short name T1521
Test name
Test status
Simulation time 3607279250 ps
CPU time 4.03 seconds
Started Jun 28 06:08:53 PM PDT 24
Finished Jun 28 06:09:01 PM PDT 24
Peak memory 206268 kb
Host smart-52e2fb02-0fa0-4af2-bb9e-c4d8938b9992
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1458691682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.1458691682
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.2194229254
Short name T2587
Test name
Test status
Simulation time 13308999076 ps
CPU time 13.34 seconds
Started Jun 28 06:08:53 PM PDT 24
Finished Jun 28 06:09:10 PM PDT 24
Peak memory 206492 kb
Host smart-f63dd4d9-efbc-486c-97d9-ef6ae2c1a6b2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2194229254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.2194229254
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.4038938459
Short name T2036
Test name
Test status
Simulation time 23489190864 ps
CPU time 23.56 seconds
Started Jun 28 06:08:55 PM PDT 24
Finished Jun 28 06:09:23 PM PDT 24
Peak memory 206448 kb
Host smart-ab959818-a166-4edc-a8b9-ca03776db50b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4038938459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.4038938459
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.2582414155
Short name T2472
Test name
Test status
Simulation time 153494664 ps
CPU time 0.82 seconds
Started Jun 28 06:08:53 PM PDT 24
Finished Jun 28 06:08:58 PM PDT 24
Peak memory 206216 kb
Host smart-f44dbcaf-711b-45c6-a8ff-868304df405d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25824
14155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.2582414155
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.3338713616
Short name T49
Test name
Test status
Simulation time 194765874 ps
CPU time 0.85 seconds
Started Jun 28 06:08:53 PM PDT 24
Finished Jun 28 06:08:58 PM PDT 24
Peak memory 205976 kb
Host smart-1c171394-c202-4f03-af18-de42118c90f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33387
13616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.3338713616
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.52546211
Short name T1429
Test name
Test status
Simulation time 142818314 ps
CPU time 0.84 seconds
Started Jun 28 06:08:54 PM PDT 24
Finished Jun 28 06:09:00 PM PDT 24
Peak memory 206192 kb
Host smart-5920fc09-85a4-4404-a34f-e546ce2859fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52546
211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.52546211
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.4087743641
Short name T97
Test name
Test status
Simulation time 369382041 ps
CPU time 1.22 seconds
Started Jun 28 06:08:53 PM PDT 24
Finished Jun 28 06:08:58 PM PDT 24
Peak memory 206192 kb
Host smart-4874aaf7-f43a-4ace-9bb0-8223b2a46b94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40877
43641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.4087743641
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_device_address.2970972781
Short name T1553
Test name
Test status
Simulation time 18729833483 ps
CPU time 35.58 seconds
Started Jun 28 06:08:50 PM PDT 24
Finished Jun 28 06:09:29 PM PDT 24
Peak memory 206428 kb
Host smart-4a9a660c-9843-40ae-b2d6-b5a8ec03660e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29709
72781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.2970972781
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.3853683140
Short name T157
Test name
Test status
Simulation time 478243053 ps
CPU time 1.35 seconds
Started Jun 28 06:08:52 PM PDT 24
Finished Jun 28 06:08:57 PM PDT 24
Peak memory 206220 kb
Host smart-446ba776-b391-4dff-87f5-115d2bc07dc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38536
83140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.3853683140
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.2951041738
Short name T1057
Test name
Test status
Simulation time 141592662 ps
CPU time 0.76 seconds
Started Jun 28 06:08:50 PM PDT 24
Finished Jun 28 06:08:55 PM PDT 24
Peak memory 206188 kb
Host smart-b34d911b-4bef-4339-bcd6-0108b04e159f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29510
41738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.2951041738
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.1669428240
Short name T862
Test name
Test status
Simulation time 47356603 ps
CPU time 0.67 seconds
Started Jun 28 06:08:53 PM PDT 24
Finished Jun 28 06:08:58 PM PDT 24
Peak memory 206208 kb
Host smart-75c83438-6a14-49d4-9e34-aaf41eb605f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16694
28240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.1669428240
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.243689094
Short name T1890
Test name
Test status
Simulation time 802692385 ps
CPU time 2.06 seconds
Started Jun 28 06:08:51 PM PDT 24
Finished Jun 28 06:08:57 PM PDT 24
Peak memory 206292 kb
Host smart-0f891b5a-5c1b-4f5b-9012-99ec560498da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24368
9094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.243689094
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.3945343134
Short name T1601
Test name
Test status
Simulation time 182525809 ps
CPU time 1.24 seconds
Started Jun 28 06:08:55 PM PDT 24
Finished Jun 28 06:09:01 PM PDT 24
Peak memory 206320 kb
Host smart-34e740df-9e01-4bb8-abc5-2dba252e7562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39453
43134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.3945343134
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.2488253093
Short name T2154
Test name
Test status
Simulation time 234531859 ps
CPU time 0.92 seconds
Started Jun 28 06:08:52 PM PDT 24
Finished Jun 28 06:08:56 PM PDT 24
Peak memory 206184 kb
Host smart-ffe02ee7-330a-4bac-9f44-2f5622b7c809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24882
53093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.2488253093
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.1739074625
Short name T2396
Test name
Test status
Simulation time 142528608 ps
CPU time 0.79 seconds
Started Jun 28 06:08:53 PM PDT 24
Finished Jun 28 06:08:58 PM PDT 24
Peak memory 206208 kb
Host smart-335107b8-1c18-424b-8665-70a9ae396b18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17390
74625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.1739074625
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.1946038549
Short name T1677
Test name
Test status
Simulation time 191806806 ps
CPU time 0.94 seconds
Started Jun 28 06:08:52 PM PDT 24
Finished Jun 28 06:08:56 PM PDT 24
Peak memory 206192 kb
Host smart-d811d017-3f61-43b2-85eb-449338c1e6e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19460
38549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.1946038549
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_invalid_sync.2290809601
Short name T225
Test name
Test status
Simulation time 5080547710 ps
CPU time 48.63 seconds
Started Jun 28 06:08:56 PM PDT 24
Finished Jun 28 06:09:49 PM PDT 24
Peak memory 206388 kb
Host smart-6356b387-77fa-4411-8592-66156b7dbef9
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2290809601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.2290809601
Directory /workspace/3.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.2135256615
Short name T2170
Test name
Test status
Simulation time 221866293 ps
CPU time 0.87 seconds
Started Jun 28 06:08:51 PM PDT 24
Finished Jun 28 06:08:55 PM PDT 24
Peak memory 206192 kb
Host smart-b4ae837c-9102-4c60-815e-ce0d9e39cac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21352
56615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.2135256615
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.2199870149
Short name T141
Test name
Test status
Simulation time 23343497577 ps
CPU time 23.24 seconds
Started Jun 28 06:08:52 PM PDT 24
Finished Jun 28 06:09:19 PM PDT 24
Peak memory 206316 kb
Host smart-91f17cdc-1218-473f-ac13-ae2357cc7ce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21998
70149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.2199870149
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.636446600
Short name T800
Test name
Test status
Simulation time 3352789700 ps
CPU time 4.82 seconds
Started Jun 28 06:08:53 PM PDT 24
Finished Jun 28 06:09:02 PM PDT 24
Peak memory 206028 kb
Host smart-3284eed7-1589-410f-ad58-b784da57baae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63644
6600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.636446600
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.2205199369
Short name T881
Test name
Test status
Simulation time 8930483744 ps
CPU time 232.01 seconds
Started Jun 28 06:08:53 PM PDT 24
Finished Jun 28 06:12:49 PM PDT 24
Peak memory 206468 kb
Host smart-3c585b9b-4262-415a-b9c8-3ed1bc51d25f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22051
99369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.2205199369
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.771295206
Short name T534
Test name
Test status
Simulation time 6613574275 ps
CPU time 49.52 seconds
Started Jun 28 06:08:54 PM PDT 24
Finished Jun 28 06:09:48 PM PDT 24
Peak memory 206484 kb
Host smart-d7958b9b-9ef5-41d9-af2f-87eb8d3d39ae
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=771295206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.771295206
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.3605603808
Short name T330
Test name
Test status
Simulation time 241055636 ps
CPU time 0.94 seconds
Started Jun 28 06:08:51 PM PDT 24
Finished Jun 28 06:08:55 PM PDT 24
Peak memory 206216 kb
Host smart-32974c06-eec1-4ad0-af9a-c6e7c6e1b703
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3605603808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.3605603808
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.1761008883
Short name T1747
Test name
Test status
Simulation time 212274700 ps
CPU time 0.85 seconds
Started Jun 28 06:08:52 PM PDT 24
Finished Jun 28 06:08:56 PM PDT 24
Peak memory 206164 kb
Host smart-a6a6dfbd-3d11-48ac-bd0d-04841568ca2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17610
08883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.1761008883
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.2678898273
Short name T1913
Test name
Test status
Simulation time 3837857543 ps
CPU time 104.39 seconds
Started Jun 28 06:08:51 PM PDT 24
Finished Jun 28 06:10:39 PM PDT 24
Peak memory 206492 kb
Host smart-bfbbf243-1a8f-4b51-8a14-b0be2cdd61d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26788
98273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.2678898273
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.132690301
Short name T1236
Test name
Test status
Simulation time 6494092567 ps
CPU time 64.75 seconds
Started Jun 28 06:08:54 PM PDT 24
Finished Jun 28 06:10:04 PM PDT 24
Peak memory 206416 kb
Host smart-658db62e-4cfb-4e48-94c4-1888b7627805
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=132690301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.132690301
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.3550992573
Short name T977
Test name
Test status
Simulation time 170137109 ps
CPU time 0.91 seconds
Started Jun 28 06:08:58 PM PDT 24
Finished Jun 28 06:09:02 PM PDT 24
Peak memory 206156 kb
Host smart-83b4bde9-0cd1-45c4-aab8-e50d85791ee6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3550992573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.3550992573
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.2973328946
Short name T830
Test name
Test status
Simulation time 146745965 ps
CPU time 0.8 seconds
Started Jun 28 06:08:52 PM PDT 24
Finished Jun 28 06:08:57 PM PDT 24
Peak memory 206188 kb
Host smart-d0270740-f255-4c1c-8ae0-d9e9fc231098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29733
28946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.2973328946
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.1604155834
Short name T117
Test name
Test status
Simulation time 214775287 ps
CPU time 0.88 seconds
Started Jun 28 06:08:55 PM PDT 24
Finished Jun 28 06:09:00 PM PDT 24
Peak memory 206180 kb
Host smart-3f2be324-e022-4f77-9c1f-f5ad7c03e3c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16041
55834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.1604155834
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.2098632622
Short name T1506
Test name
Test status
Simulation time 159238180 ps
CPU time 0.86 seconds
Started Jun 28 06:08:54 PM PDT 24
Finished Jun 28 06:09:00 PM PDT 24
Peak memory 206188 kb
Host smart-b01bf7ad-dc09-4919-9028-d7b8b9a92ccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20986
32622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.2098632622
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.2384586619
Short name T485
Test name
Test status
Simulation time 152507122 ps
CPU time 0.83 seconds
Started Jun 28 06:08:55 PM PDT 24
Finished Jun 28 06:09:01 PM PDT 24
Peak memory 206192 kb
Host smart-4e5dcbcd-7cad-4c53-92b6-b52622ebcaa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23845
86619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.2384586619
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.2624806698
Short name T784
Test name
Test status
Simulation time 187693341 ps
CPU time 0.85 seconds
Started Jun 28 06:08:56 PM PDT 24
Finished Jun 28 06:09:01 PM PDT 24
Peak memory 206116 kb
Host smart-69c0e64c-ca15-4afd-93ed-b2126f1b0189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26248
06698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.2624806698
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.125931331
Short name T2403
Test name
Test status
Simulation time 154497229 ps
CPU time 0.78 seconds
Started Jun 28 06:08:55 PM PDT 24
Finished Jun 28 06:09:00 PM PDT 24
Peak memory 206184 kb
Host smart-ef3be77c-f47b-41cd-a3a3-87008c682aa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12593
1331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.125931331
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.1883861221
Short name T476
Test name
Test status
Simulation time 229927109 ps
CPU time 0.92 seconds
Started Jun 28 06:08:55 PM PDT 24
Finished Jun 28 06:09:00 PM PDT 24
Peak memory 206208 kb
Host smart-cad5d63c-77ab-46ea-91b1-dfe18751d5f5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1883861221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.1883861221
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.3216542096
Short name T207
Test name
Test status
Simulation time 216107382 ps
CPU time 0.94 seconds
Started Jun 28 06:08:52 PM PDT 24
Finished Jun 28 06:08:56 PM PDT 24
Peak memory 206200 kb
Host smart-54e7ba60-07cd-44de-98e6-3352ae27672e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32165
42096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.3216542096
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.388131356
Short name T773
Test name
Test status
Simulation time 193635427 ps
CPU time 0.82 seconds
Started Jun 28 06:08:51 PM PDT 24
Finished Jun 28 06:08:55 PM PDT 24
Peak memory 206208 kb
Host smart-2b3559f6-d2f7-4666-a92d-4fd2422f6e6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38813
1356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.388131356
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.9410960
Short name T1655
Test name
Test status
Simulation time 101323334 ps
CPU time 0.72 seconds
Started Jun 28 06:08:53 PM PDT 24
Finished Jun 28 06:08:59 PM PDT 24
Peak memory 206180 kb
Host smart-3735da97-9d15-467e-9506-90704105a57b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94109
60 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.9410960
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.2319706500
Short name T1797
Test name
Test status
Simulation time 10496370157 ps
CPU time 21.44 seconds
Started Jun 28 06:08:55 PM PDT 24
Finished Jun 28 06:09:21 PM PDT 24
Peak memory 206424 kb
Host smart-b27f235f-430a-498f-a705-86a2528f982c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23197
06500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.2319706500
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.1166668747
Short name T1461
Test name
Test status
Simulation time 205154811 ps
CPU time 0.87 seconds
Started Jun 28 06:08:52 PM PDT 24
Finished Jun 28 06:08:57 PM PDT 24
Peak memory 206200 kb
Host smart-6df1d42c-24d2-4f11-8c25-87301e386e34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11666
68747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.1166668747
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.331979400
Short name T809
Test name
Test status
Simulation time 243682152 ps
CPU time 0.86 seconds
Started Jun 28 06:08:55 PM PDT 24
Finished Jun 28 06:09:01 PM PDT 24
Peak memory 206184 kb
Host smart-264936b3-2e19-45d2-8bfe-c7ad117492d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33197
9400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.331979400
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.3046785892
Short name T1681
Test name
Test status
Simulation time 14396060330 ps
CPU time 90.26 seconds
Started Jun 28 06:08:56 PM PDT 24
Finished Jun 28 06:10:30 PM PDT 24
Peak memory 206420 kb
Host smart-fa128f76-bba9-4f43-9bd2-667b7b81a757
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3046785892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.3046785892
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.658417027
Short name T2274
Test name
Test status
Simulation time 21226613857 ps
CPU time 136.94 seconds
Started Jun 28 06:08:55 PM PDT 24
Finished Jun 28 06:11:16 PM PDT 24
Peak memory 206480 kb
Host smart-12726b87-8b48-418c-a697-e5500db1e213
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=658417027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.658417027
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.3672979870
Short name T2559
Test name
Test status
Simulation time 12640952964 ps
CPU time 86.22 seconds
Started Jun 28 06:09:00 PM PDT 24
Finished Jun 28 06:10:28 PM PDT 24
Peak memory 206416 kb
Host smart-d9fdb06e-521e-4050-bf09-a97206bc74b2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3672979870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.3672979870
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.2766754653
Short name T2272
Test name
Test status
Simulation time 186573785 ps
CPU time 0.82 seconds
Started Jun 28 06:08:53 PM PDT 24
Finished Jun 28 06:08:58 PM PDT 24
Peak memory 206224 kb
Host smart-ae6e8acf-dd0f-42ef-894a-7ce3af021730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27667
54653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.2766754653
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.129767782
Short name T1834
Test name
Test status
Simulation time 181179625 ps
CPU time 0.83 seconds
Started Jun 28 06:08:56 PM PDT 24
Finished Jun 28 06:09:01 PM PDT 24
Peak memory 206132 kb
Host smart-32e80395-cc56-4ffc-9188-92b49f2e396d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12976
7782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.129767782
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.2894992125
Short name T461
Test name
Test status
Simulation time 140123280 ps
CPU time 0.74 seconds
Started Jun 28 06:08:59 PM PDT 24
Finished Jun 28 06:09:02 PM PDT 24
Peak memory 206196 kb
Host smart-948c8f91-6c9e-4850-814d-f5cc487955a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28949
92125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.2894992125
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.1102384460
Short name T1994
Test name
Test status
Simulation time 149746700 ps
CPU time 0.79 seconds
Started Jun 28 06:08:57 PM PDT 24
Finished Jun 28 06:09:02 PM PDT 24
Peak memory 206204 kb
Host smart-4a91e20d-e420-41cf-9a3b-491946bef5b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11023
84460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.1102384460
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.1696523896
Short name T215
Test name
Test status
Simulation time 229275420 ps
CPU time 1.01 seconds
Started Jun 28 06:08:56 PM PDT 24
Finished Jun 28 06:09:02 PM PDT 24
Peak memory 224008 kb
Host smart-f0197cb5-2de6-4d36-abe6-11f7e8689969
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1696523896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.1696523896
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.1516126753
Short name T2239
Test name
Test status
Simulation time 456852824 ps
CPU time 1.35 seconds
Started Jun 28 06:09:00 PM PDT 24
Finished Jun 28 06:09:03 PM PDT 24
Peak memory 206208 kb
Host smart-5741ffdf-b722-4e1c-8a54-0e9aa1b89dc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15161
26753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.1516126753
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.2085076873
Short name T1936
Test name
Test status
Simulation time 223881917 ps
CPU time 0.9 seconds
Started Jun 28 06:08:53 PM PDT 24
Finished Jun 28 06:08:59 PM PDT 24
Peak memory 206200 kb
Host smart-cd44444d-6530-4fdc-81af-89f67a6372ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20850
76873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.2085076873
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.1335369880
Short name T1657
Test name
Test status
Simulation time 160416718 ps
CPU time 0.81 seconds
Started Jun 28 06:08:53 PM PDT 24
Finished Jun 28 06:08:59 PM PDT 24
Peak memory 206188 kb
Host smart-06fb7be1-46d2-487c-bff2-6999c8735713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13353
69880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.1335369880
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.1847298132
Short name T1290
Test name
Test status
Simulation time 156915383 ps
CPU time 0.87 seconds
Started Jun 28 06:08:52 PM PDT 24
Finished Jun 28 06:08:58 PM PDT 24
Peak memory 206192 kb
Host smart-a1c0ffee-fd3c-4cc2-9b8f-502adadb63b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18472
98132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.1847298132
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.3261788103
Short name T2063
Test name
Test status
Simulation time 269384518 ps
CPU time 0.97 seconds
Started Jun 28 06:08:59 PM PDT 24
Finished Jun 28 06:09:03 PM PDT 24
Peak memory 206208 kb
Host smart-48bb4b0d-acad-488d-953b-19c765f2444e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32617
88103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.3261788103
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.3737244183
Short name T2031
Test name
Test status
Simulation time 3331263283 ps
CPU time 30.03 seconds
Started Jun 28 06:08:52 PM PDT 24
Finished Jun 28 06:09:26 PM PDT 24
Peak memory 206392 kb
Host smart-b66c3b59-d743-43a7-8441-38dade38ff73
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3737244183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.3737244183
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.2834409324
Short name T1120
Test name
Test status
Simulation time 205114177 ps
CPU time 0.82 seconds
Started Jun 28 06:08:56 PM PDT 24
Finished Jun 28 06:09:01 PM PDT 24
Peak memory 206196 kb
Host smart-a53029b0-e260-40ce-80e3-219c31a00178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28344
09324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.2834409324
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.3658242491
Short name T1221
Test name
Test status
Simulation time 168055518 ps
CPU time 0.87 seconds
Started Jun 28 06:08:57 PM PDT 24
Finished Jun 28 06:09:02 PM PDT 24
Peak memory 206172 kb
Host smart-b67e7449-e3a3-45ad-808f-40deb6e34d67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36582
42491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.3658242491
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.1085881536
Short name T1694
Test name
Test status
Simulation time 5267149120 ps
CPU time 48.9 seconds
Started Jun 28 06:08:57 PM PDT 24
Finished Jun 28 06:09:50 PM PDT 24
Peak memory 206396 kb
Host smart-aeb9e5c6-67e8-4947-a443-93054f3af665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10858
81536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.1085881536
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.1830063180
Short name T243
Test name
Test status
Simulation time 23213333418 ps
CPU time 554.73 seconds
Started Jun 28 06:08:59 PM PDT 24
Finished Jun 28 06:18:17 PM PDT 24
Peak memory 206468 kb
Host smart-f4276671-a8ac-47d8-b610-8fcbea884f17
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1830063180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.1830063180
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.3427743465
Short name T1071
Test name
Test status
Simulation time 31706902 ps
CPU time 0.67 seconds
Started Jun 28 06:13:10 PM PDT 24
Finished Jun 28 06:13:16 PM PDT 24
Peak memory 206124 kb
Host smart-20b531f6-130b-40b6-96a1-deab78057eb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3427743465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.3427743465
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.101558987
Short name T10
Test name
Test status
Simulation time 4251156420 ps
CPU time 6 seconds
Started Jun 28 06:13:06 PM PDT 24
Finished Jun 28 06:13:19 PM PDT 24
Peak memory 206272 kb
Host smart-b888a024-b252-42a8-b0a9-4801750c1fec
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=101558987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.101558987
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.1504832839
Short name T1375
Test name
Test status
Simulation time 13438200951 ps
CPU time 13.59 seconds
Started Jun 28 06:13:06 PM PDT 24
Finished Jun 28 06:13:27 PM PDT 24
Peak memory 206332 kb
Host smart-504ee686-23c8-4a6f-8388-23ce2423f912
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1504832839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.1504832839
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.4167773726
Short name T2437
Test name
Test status
Simulation time 23292089958 ps
CPU time 27.42 seconds
Started Jun 28 06:13:06 PM PDT 24
Finished Jun 28 06:13:41 PM PDT 24
Peak memory 206320 kb
Host smart-77723882-cde8-4460-9608-fa86ced5691a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4167773726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.4167773726
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.1083563696
Short name T1064
Test name
Test status
Simulation time 165112660 ps
CPU time 0.85 seconds
Started Jun 28 06:13:04 PM PDT 24
Finished Jun 28 06:13:12 PM PDT 24
Peak memory 206184 kb
Host smart-4483a31b-2c5f-41c0-8207-2b22f16d2c35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10835
63696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.1083563696
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.1644848332
Short name T1003
Test name
Test status
Simulation time 172125411 ps
CPU time 0.76 seconds
Started Jun 28 06:13:04 PM PDT 24
Finished Jun 28 06:13:12 PM PDT 24
Peak memory 206196 kb
Host smart-cdba4a91-e4e5-45f8-a314-e7f69a6e87bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16448
48332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.1644848332
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.67082443
Short name T2579
Test name
Test status
Simulation time 338626843 ps
CPU time 1.15 seconds
Started Jun 28 06:13:04 PM PDT 24
Finished Jun 28 06:13:12 PM PDT 24
Peak memory 206200 kb
Host smart-0bff27c7-902e-4345-8ff5-a5a31929496d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67082
443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.67082443
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.619965782
Short name T1538
Test name
Test status
Simulation time 1116364827 ps
CPU time 2.68 seconds
Started Jun 28 06:13:13 PM PDT 24
Finished Jun 28 06:13:19 PM PDT 24
Peak memory 206272 kb
Host smart-95868cf2-36aa-4fc2-a6bd-b38f8b38d3de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61996
5782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.619965782
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.3937005900
Short name T178
Test name
Test status
Simulation time 19774405839 ps
CPU time 36.99 seconds
Started Jun 28 06:13:04 PM PDT 24
Finished Jun 28 06:13:48 PM PDT 24
Peak memory 206360 kb
Host smart-9af9e16b-b091-4f77-b810-caaebaa3c17f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39370
05900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.3937005900
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.3021967368
Short name T1900
Test name
Test status
Simulation time 460811115 ps
CPU time 1.34 seconds
Started Jun 28 06:13:05 PM PDT 24
Finished Jun 28 06:13:13 PM PDT 24
Peak memory 206168 kb
Host smart-4ab30930-3331-4bd3-87e3-ab2292589895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30219
67368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.3021967368
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.2886538475
Short name T2056
Test name
Test status
Simulation time 137730464 ps
CPU time 0.75 seconds
Started Jun 28 06:13:02 PM PDT 24
Finished Jun 28 06:13:10 PM PDT 24
Peak memory 206096 kb
Host smart-eda4cefb-d526-4565-9777-c87dc83eb377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28865
38475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.2886538475
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.2372570450
Short name T1410
Test name
Test status
Simulation time 100581569 ps
CPU time 0.71 seconds
Started Jun 28 06:13:05 PM PDT 24
Finished Jun 28 06:13:12 PM PDT 24
Peak memory 206184 kb
Host smart-7b101b5e-64af-45c4-a7ad-92a10a9a1a18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23725
70450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.2372570450
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.1078042857
Short name T2268
Test name
Test status
Simulation time 978645881 ps
CPU time 2.26 seconds
Started Jun 28 06:13:02 PM PDT 24
Finished Jun 28 06:13:12 PM PDT 24
Peak memory 206292 kb
Host smart-e294bcbc-562f-477f-8d46-28ecd86c2264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10780
42857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.1078042857
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.1932881450
Short name T1262
Test name
Test status
Simulation time 278761475 ps
CPU time 1.59 seconds
Started Jun 28 06:13:02 PM PDT 24
Finished Jun 28 06:13:11 PM PDT 24
Peak memory 206328 kb
Host smart-932d7cbd-bd48-4eee-96e9-6fe015b3fd4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19328
81450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.1932881450
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.1750278828
Short name T1069
Test name
Test status
Simulation time 228474795 ps
CPU time 0.84 seconds
Started Jun 28 06:13:03 PM PDT 24
Finished Jun 28 06:13:11 PM PDT 24
Peak memory 206192 kb
Host smart-8587b0d9-b930-45fa-9bae-3e92da140ca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17502
78828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.1750278828
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.3454864387
Short name T939
Test name
Test status
Simulation time 145716521 ps
CPU time 0.76 seconds
Started Jun 28 06:13:06 PM PDT 24
Finished Jun 28 06:13:14 PM PDT 24
Peak memory 206208 kb
Host smart-55ec9a2b-f22a-4806-9c76-be7ba991b3c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34548
64387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.3454864387
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.3032673568
Short name T1462
Test name
Test status
Simulation time 165312146 ps
CPU time 0.84 seconds
Started Jun 28 06:13:04 PM PDT 24
Finished Jun 28 06:13:11 PM PDT 24
Peak memory 206212 kb
Host smart-634b62b9-fddf-407c-b686-695b67a024c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30326
73568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.3032673568
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.4209160777
Short name T2160
Test name
Test status
Simulation time 203128958 ps
CPU time 0.9 seconds
Started Jun 28 06:13:02 PM PDT 24
Finished Jun 28 06:13:11 PM PDT 24
Peak memory 206172 kb
Host smart-e84401e7-b31d-4e3e-9e40-d5be70139288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42091
60777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.4209160777
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.895478148
Short name T1203
Test name
Test status
Simulation time 23375324674 ps
CPU time 25.87 seconds
Started Jun 28 06:13:17 PM PDT 24
Finished Jun 28 06:13:49 PM PDT 24
Peak memory 206208 kb
Host smart-084d4c75-790d-4dab-9d2d-0e46336c897c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89547
8148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.895478148
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.2068644545
Short name T342
Test name
Test status
Simulation time 3358038098 ps
CPU time 3.8 seconds
Started Jun 28 06:13:09 PM PDT 24
Finished Jun 28 06:13:18 PM PDT 24
Peak memory 206228 kb
Host smart-f5ac594c-5f46-4bf4-8156-014826cdb61e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20686
44545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.2068644545
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.3038748783
Short name T507
Test name
Test status
Simulation time 6567070056 ps
CPU time 180.18 seconds
Started Jun 28 06:13:19 PM PDT 24
Finished Jun 28 06:16:26 PM PDT 24
Peak memory 206444 kb
Host smart-e8fcd648-b07f-4a63-948b-d564db0498cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30387
48783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.3038748783
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.2274754670
Short name T333
Test name
Test status
Simulation time 3265688857 ps
CPU time 22.48 seconds
Started Jun 28 06:13:17 PM PDT 24
Finished Jun 28 06:13:46 PM PDT 24
Peak memory 206452 kb
Host smart-e4c91145-b292-4774-b5f3-fc5ec0e87acf
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2274754670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.2274754670
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.203200087
Short name T1017
Test name
Test status
Simulation time 274923451 ps
CPU time 0.92 seconds
Started Jun 28 06:13:18 PM PDT 24
Finished Jun 28 06:13:26 PM PDT 24
Peak memory 206220 kb
Host smart-9ebd52af-600a-4691-ae3b-1117a2613126
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=203200087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.203200087
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.3264083569
Short name T871
Test name
Test status
Simulation time 214642621 ps
CPU time 0.87 seconds
Started Jun 28 06:13:14 PM PDT 24
Finished Jun 28 06:13:20 PM PDT 24
Peak memory 206096 kb
Host smart-ba235d80-c303-41ee-9d88-8658b4544f0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32640
83569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.3264083569
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.1270914794
Short name T549
Test name
Test status
Simulation time 6367229648 ps
CPU time 185.56 seconds
Started Jun 28 06:13:14 PM PDT 24
Finished Jun 28 06:16:25 PM PDT 24
Peak memory 206632 kb
Host smart-bd33a023-43c4-4441-8fd7-b632ba2dd359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12709
14794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.1270914794
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.2314545352
Short name T2368
Test name
Test status
Simulation time 3987413839 ps
CPU time 29.75 seconds
Started Jun 28 06:13:10 PM PDT 24
Finished Jun 28 06:13:45 PM PDT 24
Peak memory 206460 kb
Host smart-af3de114-5bb8-4132-85b4-d4bff269ed0d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2314545352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.2314545352
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.2931365240
Short name T561
Test name
Test status
Simulation time 162717458 ps
CPU time 0.79 seconds
Started Jun 28 06:13:18 PM PDT 24
Finished Jun 28 06:13:25 PM PDT 24
Peak memory 206092 kb
Host smart-12ba7c74-0110-4a81-a067-7402b70c7c63
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2931365240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.2931365240
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.935656802
Short name T439
Test name
Test status
Simulation time 147302535 ps
CPU time 0.78 seconds
Started Jun 28 06:13:12 PM PDT 24
Finished Jun 28 06:13:17 PM PDT 24
Peak memory 206188 kb
Host smart-f025174d-9cd9-44a8-9acb-8ecae2205be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93565
6802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.935656802
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.1591435722
Short name T120
Test name
Test status
Simulation time 230214178 ps
CPU time 0.97 seconds
Started Jun 28 06:13:10 PM PDT 24
Finished Jun 28 06:13:15 PM PDT 24
Peak memory 206180 kb
Host smart-11277edc-c503-45e8-9281-67ae85c5cedf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15914
35722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.1591435722
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.1583426457
Short name T2173
Test name
Test status
Simulation time 171890042 ps
CPU time 0.8 seconds
Started Jun 28 06:13:16 PM PDT 24
Finished Jun 28 06:13:23 PM PDT 24
Peak memory 206184 kb
Host smart-22cafbb5-e1b3-46a6-b743-f8aeb142079e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15834
26457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.1583426457
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.1463422830
Short name T911
Test name
Test status
Simulation time 164232650 ps
CPU time 0.78 seconds
Started Jun 28 06:13:12 PM PDT 24
Finished Jun 28 06:13:17 PM PDT 24
Peak memory 206140 kb
Host smart-a46e3481-a4b3-4372-94df-a425a5af6285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14634
22830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.1463422830
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.2381420914
Short name T2163
Test name
Test status
Simulation time 162515682 ps
CPU time 0.81 seconds
Started Jun 28 06:13:09 PM PDT 24
Finished Jun 28 06:13:15 PM PDT 24
Peak memory 206212 kb
Host smart-737febac-a5b1-4ebf-b427-9a636ecf2668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23814
20914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.2381420914
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.3546988810
Short name T843
Test name
Test status
Simulation time 155693689 ps
CPU time 0.8 seconds
Started Jun 28 06:13:19 PM PDT 24
Finished Jun 28 06:13:28 PM PDT 24
Peak memory 206200 kb
Host smart-f589d591-eea2-4a3f-bb4c-76940118c3a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35469
88810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.3546988810
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.1416050276
Short name T513
Test name
Test status
Simulation time 254882983 ps
CPU time 0.99 seconds
Started Jun 28 06:13:18 PM PDT 24
Finished Jun 28 06:13:26 PM PDT 24
Peak memory 205988 kb
Host smart-65bea835-070d-498f-a91c-a297cca9b0b1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1416050276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.1416050276
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.3656663899
Short name T579
Test name
Test status
Simulation time 148749460 ps
CPU time 0.8 seconds
Started Jun 28 06:13:19 PM PDT 24
Finished Jun 28 06:13:27 PM PDT 24
Peak memory 205004 kb
Host smart-39c129ff-6d83-4912-bb2d-baae4d99299c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36566
63899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.3656663899
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.3858748701
Short name T2394
Test name
Test status
Simulation time 30560496 ps
CPU time 0.66 seconds
Started Jun 28 06:13:17 PM PDT 24
Finished Jun 28 06:13:24 PM PDT 24
Peak memory 206200 kb
Host smart-460e50de-ec67-4eb4-972f-25955cd852d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38587
48701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.3858748701
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.2748073465
Short name T261
Test name
Test status
Simulation time 13189039439 ps
CPU time 29.47 seconds
Started Jun 28 06:13:12 PM PDT 24
Finished Jun 28 06:13:46 PM PDT 24
Peak memory 206508 kb
Host smart-60b74c99-6273-4f87-b5a0-45d843674027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27480
73465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.2748073465
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.931126097
Short name T1280
Test name
Test status
Simulation time 181472845 ps
CPU time 0.87 seconds
Started Jun 28 06:13:14 PM PDT 24
Finished Jun 28 06:13:19 PM PDT 24
Peak memory 206196 kb
Host smart-0ab7458c-c96a-4528-bde1-361a6b288da2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93112
6097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.931126097
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.3428482087
Short name T2301
Test name
Test status
Simulation time 248526829 ps
CPU time 0.98 seconds
Started Jun 28 06:13:20 PM PDT 24
Finished Jun 28 06:13:28 PM PDT 24
Peak memory 206212 kb
Host smart-251ebb19-4188-4539-a709-85836d5d94f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34284
82087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.3428482087
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.1425080867
Short name T882
Test name
Test status
Simulation time 175689905 ps
CPU time 0.8 seconds
Started Jun 28 06:13:11 PM PDT 24
Finished Jun 28 06:13:17 PM PDT 24
Peak memory 206220 kb
Host smart-bf17bc83-54b1-4a2f-953a-e5378bb16ff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14250
80867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.1425080867
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.593087626
Short name T2541
Test name
Test status
Simulation time 144233727 ps
CPU time 0.78 seconds
Started Jun 28 06:13:10 PM PDT 24
Finished Jun 28 06:13:16 PM PDT 24
Peak memory 206196 kb
Host smart-fe2b0a38-2f42-4a97-8160-87974fd31378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59308
7626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.593087626
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.4019786690
Short name T1341
Test name
Test status
Simulation time 147024799 ps
CPU time 0.82 seconds
Started Jun 28 06:13:18 PM PDT 24
Finished Jun 28 06:13:26 PM PDT 24
Peak memory 206192 kb
Host smart-66f54c05-d45f-47b3-b635-89e6c20c9c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40197
86690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.4019786690
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.2287173105
Short name T1891
Test name
Test status
Simulation time 159524802 ps
CPU time 0.85 seconds
Started Jun 28 06:13:12 PM PDT 24
Finished Jun 28 06:13:17 PM PDT 24
Peak memory 206144 kb
Host smart-1d7857ee-1ccb-4817-b2b3-77651532c156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22871
73105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.2287173105
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.4107143392
Short name T1610
Test name
Test status
Simulation time 163662488 ps
CPU time 0.83 seconds
Started Jun 28 06:13:17 PM PDT 24
Finished Jun 28 06:13:24 PM PDT 24
Peak memory 206188 kb
Host smart-17a105f2-2804-437c-b25b-9be29232073e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41071
43392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.4107143392
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.3264518796
Short name T460
Test name
Test status
Simulation time 236612503 ps
CPU time 0.95 seconds
Started Jun 28 06:13:11 PM PDT 24
Finished Jun 28 06:13:17 PM PDT 24
Peak memory 206180 kb
Host smart-ce6e3059-1ca5-4348-82c9-4843e0ab4f4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32645
18796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.3264518796
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.2783793400
Short name T1825
Test name
Test status
Simulation time 6587530488 ps
CPU time 47.23 seconds
Started Jun 28 06:13:10 PM PDT 24
Finished Jun 28 06:14:02 PM PDT 24
Peak memory 206308 kb
Host smart-3e2c95e0-328b-4036-8b7f-dc87803abef2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2783793400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.2783793400
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.1196115439
Short name T1317
Test name
Test status
Simulation time 190890874 ps
CPU time 0.81 seconds
Started Jun 28 06:13:23 PM PDT 24
Finished Jun 28 06:13:31 PM PDT 24
Peak memory 206084 kb
Host smart-d6dfa598-2861-4062-a873-ba2a1f1e41c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11961
15439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.1196115439
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.3766889928
Short name T2562
Test name
Test status
Simulation time 176447034 ps
CPU time 0.79 seconds
Started Jun 28 06:13:14 PM PDT 24
Finished Jun 28 06:13:19 PM PDT 24
Peak memory 206192 kb
Host smart-1957715b-df31-421a-9a04-0e861c482192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37668
89928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.3766889928
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.3307215503
Short name T2186
Test name
Test status
Simulation time 5973887952 ps
CPU time 43.6 seconds
Started Jun 28 06:13:16 PM PDT 24
Finished Jun 28 06:14:06 PM PDT 24
Peak memory 206416 kb
Host smart-9e318729-f8d8-4ac2-969a-2f1250a188f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33072
15503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.3307215503
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.2095332800
Short name T1710
Test name
Test status
Simulation time 37273349 ps
CPU time 0.67 seconds
Started Jun 28 06:13:16 PM PDT 24
Finished Jun 28 06:13:22 PM PDT 24
Peak memory 205380 kb
Host smart-ccf42671-7975-4bef-ba83-df92ee7a8193
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2095332800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.2095332800
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.3776547012
Short name T1887
Test name
Test status
Simulation time 3946329498 ps
CPU time 4.7 seconds
Started Jun 28 06:13:08 PM PDT 24
Finished Jun 28 06:13:19 PM PDT 24
Peak memory 206356 kb
Host smart-731c3694-d902-481e-81e0-16ca7a72d9e7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3776547012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.3776547012
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.338947954
Short name T1068
Test name
Test status
Simulation time 13522149853 ps
CPU time 13.93 seconds
Started Jun 28 06:13:16 PM PDT 24
Finished Jun 28 06:13:37 PM PDT 24
Peak memory 206396 kb
Host smart-37703d7e-d981-4762-a356-7d0d2ae6f6bb
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=338947954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.338947954
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.802742743
Short name T2373
Test name
Test status
Simulation time 23371843509 ps
CPU time 22.95 seconds
Started Jun 28 06:13:16 PM PDT 24
Finished Jun 28 06:13:46 PM PDT 24
Peak memory 206272 kb
Host smart-3783f071-650f-4022-8e04-c8cc41607b5c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=802742743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.802742743
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.459929915
Short name T1382
Test name
Test status
Simulation time 176338941 ps
CPU time 0.8 seconds
Started Jun 28 06:13:14 PM PDT 24
Finished Jun 28 06:13:20 PM PDT 24
Peak memory 206212 kb
Host smart-f0fa9dba-245e-4a6f-a69d-e842fd2a6047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45992
9915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.459929915
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.1012179687
Short name T807
Test name
Test status
Simulation time 200090964 ps
CPU time 0.83 seconds
Started Jun 28 06:13:16 PM PDT 24
Finished Jun 28 06:13:23 PM PDT 24
Peak memory 206188 kb
Host smart-f6567d12-10bf-4047-82fc-3175a3224b95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10121
79687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.1012179687
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.3554527481
Short name T2588
Test name
Test status
Simulation time 444996007 ps
CPU time 1.4 seconds
Started Jun 28 06:13:19 PM PDT 24
Finished Jun 28 06:13:27 PM PDT 24
Peak memory 204848 kb
Host smart-cd8c21bc-e349-4634-8ecd-1f02c04e5f89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35545
27481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.3554527481
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.2574869491
Short name T2440
Test name
Test status
Simulation time 1374259576 ps
CPU time 2.87 seconds
Started Jun 28 06:13:16 PM PDT 24
Finished Jun 28 06:13:25 PM PDT 24
Peak memory 206272 kb
Host smart-6c536570-aba1-4f73-ab9f-6bf953ca7d29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25748
69491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.2574869491
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.3906454384
Short name T2345
Test name
Test status
Simulation time 14100361803 ps
CPU time 26.4 seconds
Started Jun 28 06:13:16 PM PDT 24
Finished Jun 28 06:13:48 PM PDT 24
Peak memory 206456 kb
Host smart-63422a9a-5312-4eae-b542-1fa851469818
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39064
54384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.3906454384
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.3783100759
Short name T2088
Test name
Test status
Simulation time 415367880 ps
CPU time 1.37 seconds
Started Jun 28 06:13:14 PM PDT 24
Finished Jun 28 06:13:21 PM PDT 24
Peak memory 206168 kb
Host smart-a44a7fb9-1cf0-4dca-99dd-16bf32fdd6a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37831
00759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.3783100759
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.3502490375
Short name T1561
Test name
Test status
Simulation time 155758919 ps
CPU time 0.75 seconds
Started Jun 28 06:13:20 PM PDT 24
Finished Jun 28 06:13:28 PM PDT 24
Peak memory 206192 kb
Host smart-253dd65e-1fc2-4628-93e4-85f59b955444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35024
90375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.3502490375
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.2451034945
Short name T567
Test name
Test status
Simulation time 92025994 ps
CPU time 0.71 seconds
Started Jun 28 06:13:18 PM PDT 24
Finished Jun 28 06:13:25 PM PDT 24
Peak memory 206060 kb
Host smart-d5cdf299-6ad6-4fd5-b8af-73ed8021da31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24510
34945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.2451034945
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.3417407276
Short name T589
Test name
Test status
Simulation time 1071071868 ps
CPU time 2.6 seconds
Started Jun 28 06:13:16 PM PDT 24
Finished Jun 28 06:13:25 PM PDT 24
Peak memory 206300 kb
Host smart-a07d4d39-11a6-400d-962a-ab48b4ca5a9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34174
07276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.3417407276
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.164381481
Short name T190
Test name
Test status
Simulation time 366275079 ps
CPU time 2.23 seconds
Started Jun 28 06:13:20 PM PDT 24
Finished Jun 28 06:13:29 PM PDT 24
Peak memory 206268 kb
Host smart-8ad75538-4b92-4f57-9f18-3e3c9f0a04bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16438
1481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.164381481
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.3600188169
Short name T1086
Test name
Test status
Simulation time 245584781 ps
CPU time 0.89 seconds
Started Jun 28 06:13:20 PM PDT 24
Finished Jun 28 06:13:28 PM PDT 24
Peak memory 206188 kb
Host smart-e70abf8b-dc67-4fd9-9a8d-b8b1ac613cae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36001
88169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.3600188169
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.2041980728
Short name T927
Test name
Test status
Simulation time 141467653 ps
CPU time 0.8 seconds
Started Jun 28 06:13:20 PM PDT 24
Finished Jun 28 06:13:28 PM PDT 24
Peak memory 206208 kb
Host smart-25e3669f-f673-47a0-830a-818529a98e01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20419
80728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.2041980728
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.1169765379
Short name T1862
Test name
Test status
Simulation time 191623488 ps
CPU time 0.89 seconds
Started Jun 28 06:13:17 PM PDT 24
Finished Jun 28 06:13:25 PM PDT 24
Peak memory 206212 kb
Host smart-9b83d39a-4db1-4cc1-b579-2cd83f9f7ee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11697
65379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.1169765379
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.1636155778
Short name T1740
Test name
Test status
Simulation time 223664723 ps
CPU time 0.9 seconds
Started Jun 28 06:13:17 PM PDT 24
Finished Jun 28 06:13:25 PM PDT 24
Peak memory 206192 kb
Host smart-baba1999-89fe-4074-b4a6-c7dd5cbb9ef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16361
55778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.1636155778
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.850004555
Short name T2429
Test name
Test status
Simulation time 23366788114 ps
CPU time 22.73 seconds
Started Jun 28 06:13:17 PM PDT 24
Finished Jun 28 06:13:47 PM PDT 24
Peak memory 206308 kb
Host smart-ab5f6cf3-85ce-4e6d-99b7-1144cee8aab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85000
4555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.850004555
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.3571231836
Short name T1419
Test name
Test status
Simulation time 3329441827 ps
CPU time 3.97 seconds
Started Jun 28 06:13:18 PM PDT 24
Finished Jun 28 06:13:29 PM PDT 24
Peak memory 206136 kb
Host smart-65c87adf-aa64-483b-a2e7-bee661fdf832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35712
31836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.3571231836
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.1813069763
Short name T1240
Test name
Test status
Simulation time 7154949708 ps
CPU time 59.06 seconds
Started Jun 28 06:13:26 PM PDT 24
Finished Jun 28 06:14:31 PM PDT 24
Peak memory 206464 kb
Host smart-b48e258f-4b9d-4bfa-bd07-80be8568cec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18130
69763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.1813069763
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.291928691
Short name T1395
Test name
Test status
Simulation time 7162414013 ps
CPU time 49.43 seconds
Started Jun 28 06:13:19 PM PDT 24
Finished Jun 28 06:14:16 PM PDT 24
Peak memory 206432 kb
Host smart-418ef65e-8e4d-4e05-b67a-5759a9ced38a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=291928691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.291928691
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.2762812050
Short name T2266
Test name
Test status
Simulation time 266931430 ps
CPU time 0.89 seconds
Started Jun 28 06:13:17 PM PDT 24
Finished Jun 28 06:13:24 PM PDT 24
Peak memory 206212 kb
Host smart-b2655bef-00ff-4777-ac23-520d1905d5e4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2762812050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.2762812050
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.610324283
Short name T420
Test name
Test status
Simulation time 196923357 ps
CPU time 0.97 seconds
Started Jun 28 06:13:14 PM PDT 24
Finished Jun 28 06:13:20 PM PDT 24
Peak memory 206212 kb
Host smart-12bf2ff3-e13d-4139-b0f2-798df3592588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61032
4283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.610324283
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.4138668018
Short name T616
Test name
Test status
Simulation time 5970903977 ps
CPU time 153.47 seconds
Started Jun 28 06:13:19 PM PDT 24
Finished Jun 28 06:16:01 PM PDT 24
Peak memory 206460 kb
Host smart-6465f2b9-2395-43e7-b9a2-b1595ae999c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41386
68018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.4138668018
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.2770635037
Short name T1928
Test name
Test status
Simulation time 4581221801 ps
CPU time 42.03 seconds
Started Jun 28 06:13:16 PM PDT 24
Finished Jun 28 06:14:04 PM PDT 24
Peak memory 206388 kb
Host smart-3693b080-922f-48a6-9434-341024bc0a68
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2770635037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.2770635037
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.3530200887
Short name T2242
Test name
Test status
Simulation time 168958740 ps
CPU time 0.8 seconds
Started Jun 28 06:13:17 PM PDT 24
Finished Jun 28 06:13:24 PM PDT 24
Peak memory 206196 kb
Host smart-09b1d3c2-9422-4f13-9542-3c90ac40f772
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3530200887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.3530200887
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.4077508155
Short name T2316
Test name
Test status
Simulation time 139764828 ps
CPU time 0.76 seconds
Started Jun 28 06:13:19 PM PDT 24
Finished Jun 28 06:13:28 PM PDT 24
Peak memory 206172 kb
Host smart-caee81c6-1cc6-4ed2-8819-e8416c74ea30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40775
08155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.4077508155
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.2258282451
Short name T133
Test name
Test status
Simulation time 207124662 ps
CPU time 0.83 seconds
Started Jun 28 06:13:23 PM PDT 24
Finished Jun 28 06:13:31 PM PDT 24
Peak memory 206192 kb
Host smart-86460a74-5bbc-4d2a-8dd0-2c27a4bc75bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22582
82451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.2258282451
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.1822341136
Short name T1633
Test name
Test status
Simulation time 146615232 ps
CPU time 0.76 seconds
Started Jun 28 06:13:23 PM PDT 24
Finished Jun 28 06:13:31 PM PDT 24
Peak memory 206192 kb
Host smart-298b2a8d-3fd4-47cd-827b-ff641dac35ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18223
41136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.1822341136
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.1918014649
Short name T902
Test name
Test status
Simulation time 177473223 ps
CPU time 0.8 seconds
Started Jun 28 06:13:19 PM PDT 24
Finished Jun 28 06:13:27 PM PDT 24
Peak memory 206192 kb
Host smart-1b75da0f-3e1c-40fd-a9b0-8192b1313ac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19180
14649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.1918014649
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.2189845548
Short name T1438
Test name
Test status
Simulation time 165965603 ps
CPU time 0.81 seconds
Started Jun 28 06:13:15 PM PDT 24
Finished Jun 28 06:13:21 PM PDT 24
Peak memory 206212 kb
Host smart-4815575f-3f2e-4b99-b389-8788f9e99881
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21898
45548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.2189845548
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.3921857526
Short name T1171
Test name
Test status
Simulation time 199301777 ps
CPU time 0.83 seconds
Started Jun 28 06:13:12 PM PDT 24
Finished Jun 28 06:13:17 PM PDT 24
Peak memory 206204 kb
Host smart-aa713b4a-5f91-4735-8ba0-556a0c5f496d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39218
57526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.3921857526
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.21406432
Short name T497
Test name
Test status
Simulation time 236628037 ps
CPU time 0.93 seconds
Started Jun 28 06:13:22 PM PDT 24
Finished Jun 28 06:13:30 PM PDT 24
Peak memory 206216 kb
Host smart-8717a8c4-b842-41f4-99bd-8c41274171ee
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=21406432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.21406432
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.2044159375
Short name T597
Test name
Test status
Simulation time 165676130 ps
CPU time 0.76 seconds
Started Jun 28 06:13:23 PM PDT 24
Finished Jun 28 06:13:31 PM PDT 24
Peak memory 206144 kb
Host smart-59ab6d47-bdd4-4dab-91e8-c45c459caaa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20441
59375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.2044159375
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.863494832
Short name T1227
Test name
Test status
Simulation time 32450178 ps
CPU time 0.64 seconds
Started Jun 28 06:13:12 PM PDT 24
Finished Jun 28 06:13:17 PM PDT 24
Peak memory 206208 kb
Host smart-05d93254-aaad-4bbe-9a36-493cf1348367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86349
4832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.863494832
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.3079554610
Short name T79
Test name
Test status
Simulation time 6767394494 ps
CPU time 15.32 seconds
Started Jun 28 06:13:12 PM PDT 24
Finished Jun 28 06:13:32 PM PDT 24
Peak memory 206468 kb
Host smart-0b6c77f7-ec33-43e6-9097-0e82af9dce38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30795
54610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.3079554610
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.2004993936
Short name T1606
Test name
Test status
Simulation time 200076883 ps
CPU time 0.89 seconds
Started Jun 28 06:13:13 PM PDT 24
Finished Jun 28 06:13:18 PM PDT 24
Peak memory 206192 kb
Host smart-5ff7c098-45e3-4089-be17-c09d80ac373f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20049
93936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.2004993936
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.1530965871
Short name T946
Test name
Test status
Simulation time 259561882 ps
CPU time 0.9 seconds
Started Jun 28 06:13:11 PM PDT 24
Finished Jun 28 06:13:16 PM PDT 24
Peak memory 206208 kb
Host smart-c4225473-7c80-41d2-b9a7-609794eb7947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15309
65871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.1530965871
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.2293657510
Short name T253
Test name
Test status
Simulation time 173448794 ps
CPU time 0.82 seconds
Started Jun 28 06:13:14 PM PDT 24
Finished Jun 28 06:13:19 PM PDT 24
Peak memory 206216 kb
Host smart-d4faef53-3175-4c15-8496-8591e9a8b8b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22936
57510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.2293657510
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.3646205873
Short name T772
Test name
Test status
Simulation time 203984297 ps
CPU time 0.92 seconds
Started Jun 28 06:13:19 PM PDT 24
Finished Jun 28 06:13:28 PM PDT 24
Peak memory 206200 kb
Host smart-cded44d3-0b6f-45f7-8c29-8bbeea54bfb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36462
05873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.3646205873
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.1159466416
Short name T1404
Test name
Test status
Simulation time 151603211 ps
CPU time 0.74 seconds
Started Jun 28 06:13:18 PM PDT 24
Finished Jun 28 06:13:27 PM PDT 24
Peak memory 206188 kb
Host smart-6c659b81-0709-455e-8331-ebf7b823b62a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11594
66416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.1159466416
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.2525636100
Short name T1926
Test name
Test status
Simulation time 159179909 ps
CPU time 0.82 seconds
Started Jun 28 06:13:11 PM PDT 24
Finished Jun 28 06:13:17 PM PDT 24
Peak memory 206180 kb
Host smart-062da27c-7b05-482d-9dcd-c6cade99d12a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25256
36100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.2525636100
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.3390952138
Short name T2478
Test name
Test status
Simulation time 142966912 ps
CPU time 0.78 seconds
Started Jun 28 06:13:15 PM PDT 24
Finished Jun 28 06:13:22 PM PDT 24
Peak memory 206192 kb
Host smart-d9fbce93-04d4-4e8a-a362-cf2d43368154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33909
52138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.3390952138
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.3833065562
Short name T2363
Test name
Test status
Simulation time 259516014 ps
CPU time 0.94 seconds
Started Jun 28 06:13:19 PM PDT 24
Finished Jun 28 06:13:28 PM PDT 24
Peak memory 206152 kb
Host smart-452fae14-bed4-44ce-9400-04f834926723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38330
65562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.3833065562
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.3367432417
Short name T1751
Test name
Test status
Simulation time 4644410188 ps
CPU time 126.65 seconds
Started Jun 28 06:13:15 PM PDT 24
Finished Jun 28 06:15:28 PM PDT 24
Peak memory 206476 kb
Host smart-4b19438a-8ac0-43a2-94c9-09c2287ca2d4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3367432417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.3367432417
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.648442079
Short name T381
Test name
Test status
Simulation time 269086974 ps
CPU time 0.87 seconds
Started Jun 28 06:13:15 PM PDT 24
Finished Jun 28 06:13:21 PM PDT 24
Peak memory 206200 kb
Host smart-4e26101a-c06f-4f59-8325-8c0762231fe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64844
2079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.648442079
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.157972827
Short name T2467
Test name
Test status
Simulation time 157183836 ps
CPU time 0.78 seconds
Started Jun 28 06:13:19 PM PDT 24
Finished Jun 28 06:13:27 PM PDT 24
Peak memory 206192 kb
Host smart-3d757427-e18a-48c2-a7d1-6c5f5153eadb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15797
2827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.157972827
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.3879690154
Short name T1673
Test name
Test status
Simulation time 5564095579 ps
CPU time 38.45 seconds
Started Jun 28 06:13:15 PM PDT 24
Finished Jun 28 06:13:59 PM PDT 24
Peak memory 206464 kb
Host smart-6e289483-761f-4123-9e3f-25ed173e5ac0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38796
90154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.3879690154
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.2513567036
Short name T415
Test name
Test status
Simulation time 32925272 ps
CPU time 0.65 seconds
Started Jun 28 06:13:36 PM PDT 24
Finished Jun 28 06:13:42 PM PDT 24
Peak memory 206208 kb
Host smart-37337c29-dd8a-4248-8025-34f512a3d692
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2513567036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.2513567036
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.2473740028
Short name T660
Test name
Test status
Simulation time 3666990493 ps
CPU time 4.58 seconds
Started Jun 28 06:13:19 PM PDT 24
Finished Jun 28 06:13:31 PM PDT 24
Peak memory 206376 kb
Host smart-9141ec9c-1e26-465d-8074-07c0a601b3f7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2473740028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.2473740028
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.2678390372
Short name T1805
Test name
Test status
Simulation time 13422038272 ps
CPU time 13.41 seconds
Started Jun 28 06:13:15 PM PDT 24
Finished Jun 28 06:13:34 PM PDT 24
Peak memory 206528 kb
Host smart-712d09fa-cc5f-4bf3-8740-98a801bcbbb0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2678390372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.2678390372
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.122589741
Short name T1674
Test name
Test status
Simulation time 23420841479 ps
CPU time 25.16 seconds
Started Jun 28 06:13:22 PM PDT 24
Finished Jun 28 06:13:54 PM PDT 24
Peak memory 206320 kb
Host smart-081713c7-eec9-431d-bd26-69f5e8ad67da
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=122589741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.122589741
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.2873825586
Short name T2203
Test name
Test status
Simulation time 157069749 ps
CPU time 0.81 seconds
Started Jun 28 06:13:17 PM PDT 24
Finished Jun 28 06:13:24 PM PDT 24
Peak memory 206192 kb
Host smart-85d92335-496a-4355-bdc3-2bbad590f561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28738
25586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.2873825586
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.1381561011
Short name T2236
Test name
Test status
Simulation time 140980666 ps
CPU time 0.81 seconds
Started Jun 28 06:13:14 PM PDT 24
Finished Jun 28 06:13:19 PM PDT 24
Peak memory 206168 kb
Host smart-f81899c9-1fda-45ea-9742-bbe8b852b1e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13815
61011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.1381561011
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.2790628832
Short name T1022
Test name
Test status
Simulation time 339298780 ps
CPU time 1.34 seconds
Started Jun 28 06:13:15 PM PDT 24
Finished Jun 28 06:13:22 PM PDT 24
Peak memory 206352 kb
Host smart-d4e25cbc-63d8-4712-a075-c9555357406f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27906
28832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.2790628832
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.2404453222
Short name T1607
Test name
Test status
Simulation time 1504236094 ps
CPU time 3.11 seconds
Started Jun 28 06:13:15 PM PDT 24
Finished Jun 28 06:13:24 PM PDT 24
Peak memory 206272 kb
Host smart-bbeec385-6c0e-4664-a5bf-179677f399a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24044
53222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.2404453222
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.62889374
Short name T1249
Test name
Test status
Simulation time 21445908228 ps
CPU time 38.39 seconds
Started Jun 28 06:13:16 PM PDT 24
Finished Jun 28 06:14:00 PM PDT 24
Peak memory 205548 kb
Host smart-5e7c30f9-e9c0-4b7e-8f51-552082c193cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62889
374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.62889374
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.4277808299
Short name T552
Test name
Test status
Simulation time 447541314 ps
CPU time 1.41 seconds
Started Jun 28 06:13:15 PM PDT 24
Finished Jun 28 06:13:22 PM PDT 24
Peak memory 206200 kb
Host smart-e368e38c-2fc0-42f2-81ef-81ad779646b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42778
08299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.4277808299
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.1177035228
Short name T471
Test name
Test status
Simulation time 138978933 ps
CPU time 0.73 seconds
Started Jun 28 06:13:12 PM PDT 24
Finished Jun 28 06:13:17 PM PDT 24
Peak memory 206168 kb
Host smart-bab6ac78-3ab3-4e32-a5d4-9f170b3f8d47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11770
35228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.1177035228
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.3977233977
Short name T1919
Test name
Test status
Simulation time 43654471 ps
CPU time 0.69 seconds
Started Jun 28 06:13:15 PM PDT 24
Finished Jun 28 06:13:22 PM PDT 24
Peak memory 206156 kb
Host smart-3c75b8ff-ec05-4419-8ef0-4d299be0b95a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39772
33977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.3977233977
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.352058053
Short name T1258
Test name
Test status
Simulation time 898435653 ps
CPU time 2.04 seconds
Started Jun 28 06:13:14 PM PDT 24
Finished Jun 28 06:13:22 PM PDT 24
Peak memory 206324 kb
Host smart-ad8b60d6-fcd1-4d94-b323-622568b33e80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35205
8053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.352058053
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.3649405459
Short name T2409
Test name
Test status
Simulation time 181171137 ps
CPU time 1.93 seconds
Started Jun 28 06:13:15 PM PDT 24
Finished Jun 28 06:13:22 PM PDT 24
Peak memory 206508 kb
Host smart-6bff2428-a37f-4995-8cd7-b6b20a299f0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36494
05459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.3649405459
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.1053366597
Short name T1477
Test name
Test status
Simulation time 200529965 ps
CPU time 0.95 seconds
Started Jun 28 06:13:15 PM PDT 24
Finished Jun 28 06:13:22 PM PDT 24
Peak memory 206164 kb
Host smart-6573bd8f-a33c-4695-bb48-3d738302757e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10533
66597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.1053366597
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.4210276269
Short name T904
Test name
Test status
Simulation time 149902787 ps
CPU time 0.79 seconds
Started Jun 28 06:13:17 PM PDT 24
Finished Jun 28 06:13:24 PM PDT 24
Peak memory 206160 kb
Host smart-4ff85952-29bb-417e-b63b-80c55ece47db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42102
76269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.4210276269
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.2763115275
Short name T947
Test name
Test status
Simulation time 209032191 ps
CPU time 0.94 seconds
Started Jun 28 06:13:18 PM PDT 24
Finished Jun 28 06:13:26 PM PDT 24
Peak memory 206216 kb
Host smart-165ef05e-46b0-4c87-83f6-eabf897a4a48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27631
15275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.2763115275
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.1695997820
Short name T2538
Test name
Test status
Simulation time 227314567 ps
CPU time 0.9 seconds
Started Jun 28 06:13:17 PM PDT 24
Finished Jun 28 06:13:25 PM PDT 24
Peak memory 206184 kb
Host smart-18adf3be-17bb-4df5-af44-7602c57d8649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16959
97820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.1695997820
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.2271291284
Short name T2395
Test name
Test status
Simulation time 23270214679 ps
CPU time 23.1 seconds
Started Jun 28 06:13:19 PM PDT 24
Finished Jun 28 06:13:50 PM PDT 24
Peak memory 206312 kb
Host smart-074a302d-b3e2-465a-9bd4-faf9b185d3de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22712
91284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.2271291284
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.3456438266
Short name T500
Test name
Test status
Simulation time 3345728914 ps
CPU time 3.72 seconds
Started Jun 28 06:13:15 PM PDT 24
Finished Jun 28 06:13:24 PM PDT 24
Peak memory 206256 kb
Host smart-721f45fc-91c3-4825-9df3-c9015257dd6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34564
38266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.3456438266
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.2009448170
Short name T1659
Test name
Test status
Simulation time 10919911629 ps
CPU time 81.73 seconds
Started Jun 28 06:13:17 PM PDT 24
Finished Jun 28 06:14:45 PM PDT 24
Peak memory 206436 kb
Host smart-f77623b0-6dcd-4443-8d35-8e2cb86dfdaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20094
48170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.2009448170
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.815722869
Short name T630
Test name
Test status
Simulation time 5344917615 ps
CPU time 37.25 seconds
Started Jun 28 06:13:14 PM PDT 24
Finished Jun 28 06:13:56 PM PDT 24
Peak memory 206496 kb
Host smart-3b564697-e12a-4647-8b72-960264e9f5e1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=815722869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.815722869
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.1372322975
Short name T358
Test name
Test status
Simulation time 259436979 ps
CPU time 0.99 seconds
Started Jun 28 06:13:14 PM PDT 24
Finished Jun 28 06:13:20 PM PDT 24
Peak memory 206212 kb
Host smart-d6df6f92-3de2-40bc-92d0-3c891b09f27d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1372322975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.1372322975
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.963122561
Short name T863
Test name
Test status
Simulation time 189578419 ps
CPU time 0.85 seconds
Started Jun 28 06:13:19 PM PDT 24
Finished Jun 28 06:13:27 PM PDT 24
Peak memory 206212 kb
Host smart-957fa1af-ce15-4d9f-bcd9-96263bbbcf0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96312
2561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.963122561
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.2379392790
Short name T1548
Test name
Test status
Simulation time 7204951097 ps
CPU time 206.27 seconds
Started Jun 28 06:13:17 PM PDT 24
Finished Jun 28 06:16:50 PM PDT 24
Peak memory 206464 kb
Host smart-cf1a50a0-fb8a-4c1c-82af-78b594fccf6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23793
92790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.2379392790
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.4197411302
Short name T362
Test name
Test status
Simulation time 5219126661 ps
CPU time 50.96 seconds
Started Jun 28 06:13:21 PM PDT 24
Finished Jun 28 06:14:20 PM PDT 24
Peak memory 206396 kb
Host smart-024ae3c4-35f0-47d6-b5e4-6d3492aeddc6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4197411302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.4197411302
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.3168565352
Short name T528
Test name
Test status
Simulation time 199856482 ps
CPU time 0.82 seconds
Started Jun 28 06:13:28 PM PDT 24
Finished Jun 28 06:13:35 PM PDT 24
Peak memory 206216 kb
Host smart-7278e534-c2e5-4639-88f3-74bf8e2d147e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3168565352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.3168565352
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.3575177709
Short name T2556
Test name
Test status
Simulation time 161762462 ps
CPU time 0.81 seconds
Started Jun 28 06:13:21 PM PDT 24
Finished Jun 28 06:13:29 PM PDT 24
Peak memory 206196 kb
Host smart-92bea1bf-0207-46ba-a910-d6cc197a4dae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35751
77709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.3575177709
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.1116241820
Short name T2476
Test name
Test status
Simulation time 190539509 ps
CPU time 0.85 seconds
Started Jun 28 06:13:35 PM PDT 24
Finished Jun 28 06:13:41 PM PDT 24
Peak memory 206188 kb
Host smart-8f4dd8a6-66fa-458e-974c-e1d86769f4d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11162
41820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.1116241820
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.2355490789
Short name T1263
Test name
Test status
Simulation time 180962070 ps
CPU time 0.81 seconds
Started Jun 28 06:13:32 PM PDT 24
Finished Jun 28 06:13:38 PM PDT 24
Peak memory 206156 kb
Host smart-73a11708-edea-4b9b-9196-b4dd64cba6f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23554
90789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.2355490789
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.1775371256
Short name T587
Test name
Test status
Simulation time 169449126 ps
CPU time 0.79 seconds
Started Jun 28 06:13:30 PM PDT 24
Finished Jun 28 06:13:41 PM PDT 24
Peak memory 206184 kb
Host smart-df1e0947-bd44-44ff-9b38-10d65070a4c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17753
71256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.1775371256
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.1091877204
Short name T1634
Test name
Test status
Simulation time 204237944 ps
CPU time 0.81 seconds
Started Jun 28 06:13:21 PM PDT 24
Finished Jun 28 06:13:30 PM PDT 24
Peak memory 206148 kb
Host smart-5b2958b4-3f36-4329-9244-4b63db89c17e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10918
77204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.1091877204
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.3697619555
Short name T2070
Test name
Test status
Simulation time 157053106 ps
CPU time 0.8 seconds
Started Jun 28 06:13:31 PM PDT 24
Finished Jun 28 06:13:37 PM PDT 24
Peak memory 206200 kb
Host smart-e66c9fee-6aa4-473d-a3b0-1b3f97778503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36976
19555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.3697619555
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.3600177921
Short name T1414
Test name
Test status
Simulation time 208871662 ps
CPU time 0.94 seconds
Started Jun 28 06:13:32 PM PDT 24
Finished Jun 28 06:13:39 PM PDT 24
Peak memory 206212 kb
Host smart-4b093bf6-0ee8-4fb3-8fc8-c5dc7a46d777
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3600177921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.3600177921
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.2367941718
Short name T1881
Test name
Test status
Simulation time 169572628 ps
CPU time 0.83 seconds
Started Jun 28 06:13:24 PM PDT 24
Finished Jun 28 06:13:31 PM PDT 24
Peak memory 206180 kb
Host smart-2cf28dcc-c422-49a6-bc2f-fc18b5803aa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23679
41718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.2367941718
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.3065169693
Short name T2024
Test name
Test status
Simulation time 30752257 ps
CPU time 0.65 seconds
Started Jun 28 06:13:23 PM PDT 24
Finished Jun 28 06:13:31 PM PDT 24
Peak memory 206192 kb
Host smart-6ff722d2-3743-47f7-aefb-bfcf09b3e579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30651
69693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.3065169693
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.724620451
Short name T2215
Test name
Test status
Simulation time 6744689070 ps
CPU time 18.45 seconds
Started Jun 28 06:13:20 PM PDT 24
Finished Jun 28 06:13:46 PM PDT 24
Peak memory 206428 kb
Host smart-da89310c-8a2d-48e7-a1d4-23706cdee118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72462
0451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.724620451
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.2913433246
Short name T508
Test name
Test status
Simulation time 206538066 ps
CPU time 0.92 seconds
Started Jun 28 06:13:20 PM PDT 24
Finished Jun 28 06:13:28 PM PDT 24
Peak memory 206196 kb
Host smart-aa917383-5025-48d9-bb50-feba6aa1d323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29134
33246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.2913433246
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.3995491106
Short name T2147
Test name
Test status
Simulation time 207172822 ps
CPU time 0.84 seconds
Started Jun 28 06:13:21 PM PDT 24
Finished Jun 28 06:13:29 PM PDT 24
Peak memory 206144 kb
Host smart-6f4abd93-8e1e-41fc-a9ed-3b0d4425bd45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39954
91106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.3995491106
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.3221034972
Short name T353
Test name
Test status
Simulation time 215193344 ps
CPU time 0.87 seconds
Started Jun 28 06:13:20 PM PDT 24
Finished Jun 28 06:13:28 PM PDT 24
Peak memory 206220 kb
Host smart-2fd56e1f-3dc6-49e9-8179-f0fc0f3cff48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32210
34972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.3221034972
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.2724530594
Short name T1886
Test name
Test status
Simulation time 177082052 ps
CPU time 0.83 seconds
Started Jun 28 06:13:31 PM PDT 24
Finished Jun 28 06:13:37 PM PDT 24
Peak memory 206196 kb
Host smart-250df9ed-bedd-41a4-9b8e-b0fb50f798a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27245
30594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.2724530594
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.801411086
Short name T2124
Test name
Test status
Simulation time 149350587 ps
CPU time 0.84 seconds
Started Jun 28 06:13:23 PM PDT 24
Finished Jun 28 06:13:31 PM PDT 24
Peak memory 206028 kb
Host smart-d5b22a34-16e3-4a9a-a598-3b66495d2c10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80141
1086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.801411086
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.1447683762
Short name T2262
Test name
Test status
Simulation time 157510341 ps
CPU time 0.78 seconds
Started Jun 28 06:13:37 PM PDT 24
Finished Jun 28 06:13:43 PM PDT 24
Peak memory 206304 kb
Host smart-8b89fe77-72fc-4454-b23a-de28a8cdf501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14476
83762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.1447683762
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.3000266034
Short name T1753
Test name
Test status
Simulation time 169671076 ps
CPU time 0.82 seconds
Started Jun 28 06:13:19 PM PDT 24
Finished Jun 28 06:13:27 PM PDT 24
Peak memory 206192 kb
Host smart-8a2cc534-049b-489a-8324-f4739a43ec57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30002
66034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.3000266034
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.274446263
Short name T903
Test name
Test status
Simulation time 187752964 ps
CPU time 0.85 seconds
Started Jun 28 06:13:24 PM PDT 24
Finished Jun 28 06:13:31 PM PDT 24
Peak memory 206212 kb
Host smart-52062599-b7c5-4e3a-b736-3c3cb92157d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27444
6263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.274446263
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.3641281110
Short name T1572
Test name
Test status
Simulation time 3930396782 ps
CPU time 34.65 seconds
Started Jun 28 06:13:23 PM PDT 24
Finished Jun 28 06:14:05 PM PDT 24
Peak memory 206388 kb
Host smart-c8fc94d1-0871-40d1-b79e-a9fe7d92ca4d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3641281110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.3641281110
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.987655063
Short name T509
Test name
Test status
Simulation time 194531537 ps
CPU time 0.83 seconds
Started Jun 28 06:13:35 PM PDT 24
Finished Jun 28 06:13:41 PM PDT 24
Peak memory 206208 kb
Host smart-2009a652-386b-4b01-a73c-2d807b382bd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98765
5063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.987655063
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.1740021370
Short name T1893
Test name
Test status
Simulation time 172595722 ps
CPU time 0.86 seconds
Started Jun 28 06:13:18 PM PDT 24
Finished Jun 28 06:13:27 PM PDT 24
Peak memory 206192 kb
Host smart-20a08a0b-d94c-4da7-a235-e38fa2a228b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17400
21370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.1740021370
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.3854642761
Short name T1701
Test name
Test status
Simulation time 3411208703 ps
CPU time 94.94 seconds
Started Jun 28 06:13:27 PM PDT 24
Finished Jun 28 06:15:09 PM PDT 24
Peak memory 206352 kb
Host smart-94b644bf-9a94-4573-b3af-f7f4af89fe38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38546
42761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.3854642761
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.4189453562
Short name T572
Test name
Test status
Simulation time 46577637 ps
CPU time 0.69 seconds
Started Jun 28 06:13:23 PM PDT 24
Finished Jun 28 06:13:31 PM PDT 24
Peak memory 206136 kb
Host smart-da63eb10-e07d-478a-a49b-e7c424fe6643
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4189453562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.4189453562
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.1395619425
Short name T477
Test name
Test status
Simulation time 3899806530 ps
CPU time 4.58 seconds
Started Jun 28 06:13:30 PM PDT 24
Finished Jun 28 06:13:40 PM PDT 24
Peak memory 206268 kb
Host smart-9c3f756d-7312-405d-85bd-843885fe95d9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1395619425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.1395619425
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.1454459823
Short name T2606
Test name
Test status
Simulation time 13343809567 ps
CPU time 15.5 seconds
Started Jun 28 06:13:21 PM PDT 24
Finished Jun 28 06:13:44 PM PDT 24
Peak memory 206324 kb
Host smart-d6586348-b09e-4c41-9d46-d2728cee8a7f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1454459823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.1454459823
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.1345743268
Short name T1786
Test name
Test status
Simulation time 23339399336 ps
CPU time 23.4 seconds
Started Jun 28 06:13:30 PM PDT 24
Finished Jun 28 06:13:59 PM PDT 24
Peak memory 206432 kb
Host smart-7c332c66-2b30-4cd8-930a-597d31dd200d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1345743268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.1345743268
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.3246450012
Short name T833
Test name
Test status
Simulation time 155259694 ps
CPU time 0.77 seconds
Started Jun 28 06:13:28 PM PDT 24
Finished Jun 28 06:13:35 PM PDT 24
Peak memory 206180 kb
Host smart-455dbe65-2570-40c7-8ef1-7958883deec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32464
50012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.3246450012
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.2082257793
Short name T1366
Test name
Test status
Simulation time 150354150 ps
CPU time 0.86 seconds
Started Jun 28 06:13:23 PM PDT 24
Finished Jun 28 06:13:31 PM PDT 24
Peak memory 205940 kb
Host smart-777857c9-4c0d-4372-813d-944dc564a9a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20822
57793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.2082257793
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.2833038526
Short name T1931
Test name
Test status
Simulation time 211163600 ps
CPU time 0.84 seconds
Started Jun 28 06:13:30 PM PDT 24
Finished Jun 28 06:13:36 PM PDT 24
Peak memory 206188 kb
Host smart-9ab7972e-877e-456c-b58d-44160ab84ef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28330
38526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.2833038526
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.2041655619
Short name T1361
Test name
Test status
Simulation time 1659545846 ps
CPU time 3.48 seconds
Started Jun 28 06:13:34 PM PDT 24
Finished Jun 28 06:13:43 PM PDT 24
Peak memory 206292 kb
Host smart-4d693fae-1d2e-485b-b9da-323d73e2f50b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20416
55619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.2041655619
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.2361571852
Short name T1112
Test name
Test status
Simulation time 20147253839 ps
CPU time 40.11 seconds
Started Jun 28 06:13:21 PM PDT 24
Finished Jun 28 06:14:09 PM PDT 24
Peak memory 206332 kb
Host smart-e47f5d96-6ec0-4f6e-bf2d-d66f9387598d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23615
71852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.2361571852
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.3853023573
Short name T2343
Test name
Test status
Simulation time 371337751 ps
CPU time 1.32 seconds
Started Jun 28 06:13:37 PM PDT 24
Finished Jun 28 06:13:44 PM PDT 24
Peak memory 206304 kb
Host smart-9c52a1bc-c8e5-4bd7-855d-4ba3384007fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38530
23573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.3853023573
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.3757161911
Short name T1489
Test name
Test status
Simulation time 176247422 ps
CPU time 0.82 seconds
Started Jun 28 06:13:24 PM PDT 24
Finished Jun 28 06:13:31 PM PDT 24
Peak memory 206176 kb
Host smart-d26c7952-56b4-4c8e-94e9-3a484b0323d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37571
61911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.3757161911
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.1123590116
Short name T1780
Test name
Test status
Simulation time 114446278 ps
CPU time 0.76 seconds
Started Jun 28 06:13:37 PM PDT 24
Finished Jun 28 06:13:43 PM PDT 24
Peak memory 206060 kb
Host smart-ee1c1d87-df53-404d-8f2e-8eecea185dd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11235
90116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.1123590116
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.221062526
Short name T2336
Test name
Test status
Simulation time 987699063 ps
CPU time 2.23 seconds
Started Jun 28 06:13:31 PM PDT 24
Finished Jun 28 06:13:39 PM PDT 24
Peak memory 206304 kb
Host smart-16048f79-30d7-4f6d-b259-d00477f6c5c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22106
2526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.221062526
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.2439520072
Short name T2122
Test name
Test status
Simulation time 169504610 ps
CPU time 1.79 seconds
Started Jun 28 06:13:30 PM PDT 24
Finished Jun 28 06:13:38 PM PDT 24
Peak memory 206284 kb
Host smart-a8581381-11ef-446f-bd00-d9f4693f7a81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24395
20072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.2439520072
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.2961821295
Short name T900
Test name
Test status
Simulation time 223319768 ps
CPU time 0.84 seconds
Started Jun 28 06:13:35 PM PDT 24
Finished Jun 28 06:13:41 PM PDT 24
Peak memory 206180 kb
Host smart-d157e468-dfbf-467b-ba0a-d7f79ba374fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29618
21295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.2961821295
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.2143777002
Short name T853
Test name
Test status
Simulation time 144615804 ps
CPU time 0.77 seconds
Started Jun 28 06:13:37 PM PDT 24
Finished Jun 28 06:13:43 PM PDT 24
Peak memory 206304 kb
Host smart-8f046d07-8c8c-4e58-91e9-656c95036a2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21437
77002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.2143777002
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.1537758192
Short name T955
Test name
Test status
Simulation time 169414600 ps
CPU time 0.85 seconds
Started Jun 28 06:13:37 PM PDT 24
Finished Jun 28 06:13:43 PM PDT 24
Peak memory 206304 kb
Host smart-7aebf5e8-f95a-4e5a-a64a-750c6ab29786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15377
58192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.1537758192
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_invalid_sync.2585396540
Short name T2198
Test name
Test status
Simulation time 7131264966 ps
CPU time 67.77 seconds
Started Jun 28 06:13:30 PM PDT 24
Finished Jun 28 06:14:43 PM PDT 24
Peak memory 206408 kb
Host smart-62eb2b6b-7675-4435-90fa-a2045bdbe22f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2585396540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.2585396540
Directory /workspace/33.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.151819880
Short name T785
Test name
Test status
Simulation time 250331351 ps
CPU time 0.96 seconds
Started Jun 28 06:13:27 PM PDT 24
Finished Jun 28 06:13:34 PM PDT 24
Peak memory 206152 kb
Host smart-ba852ba3-f66b-4a70-b293-72e541cc1669
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15181
9880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.151819880
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.3804005369
Short name T1650
Test name
Test status
Simulation time 23333156368 ps
CPU time 24.73 seconds
Started Jun 28 06:13:29 PM PDT 24
Finished Jun 28 06:14:00 PM PDT 24
Peak memory 206308 kb
Host smart-7a2beb0f-8863-40b6-b1fd-0b7281a22cd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38040
05369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.3804005369
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.2852872278
Short name T1503
Test name
Test status
Simulation time 3289693351 ps
CPU time 4.04 seconds
Started Jun 28 06:13:20 PM PDT 24
Finished Jun 28 06:13:32 PM PDT 24
Peak memory 206256 kb
Host smart-25f68d50-c15c-4287-bc55-08d8801a5001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28528
72278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.2852872278
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.3274877289
Short name T456
Test name
Test status
Simulation time 13158650121 ps
CPU time 349.38 seconds
Started Jun 28 06:13:26 PM PDT 24
Finished Jun 28 06:19:22 PM PDT 24
Peak memory 206424 kb
Host smart-068525bd-c857-4c13-b371-6008c70414a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32748
77289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.3274877289
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.171126152
Short name T2615
Test name
Test status
Simulation time 4441071730 ps
CPU time 113.87 seconds
Started Jun 28 06:13:31 PM PDT 24
Finished Jun 28 06:15:30 PM PDT 24
Peak memory 206420 kb
Host smart-cdf76c77-c9f3-49fb-9f53-a2036d7ce676
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=171126152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.171126152
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.485182535
Short name T926
Test name
Test status
Simulation time 254874469 ps
CPU time 0.9 seconds
Started Jun 28 06:13:37 PM PDT 24
Finished Jun 28 06:13:43 PM PDT 24
Peak memory 206276 kb
Host smart-4f7df746-aaf7-44c5-8d1e-23672625fe73
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=485182535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.485182535
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.2280145924
Short name T1967
Test name
Test status
Simulation time 194309824 ps
CPU time 0.91 seconds
Started Jun 28 06:13:37 PM PDT 24
Finished Jun 28 06:13:43 PM PDT 24
Peak memory 206304 kb
Host smart-b4dbfbe8-8251-4ea6-9c36-b9ab6e92daa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22801
45924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.2280145924
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.29141804
Short name T734
Test name
Test status
Simulation time 3688978772 ps
CPU time 31.55 seconds
Started Jun 28 06:13:35 PM PDT 24
Finished Jun 28 06:14:12 PM PDT 24
Peak memory 206412 kb
Host smart-21c21377-5de6-4891-816b-e167219543da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29141
804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.29141804
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.2854063315
Short name T1609
Test name
Test status
Simulation time 7437020860 ps
CPU time 201.08 seconds
Started Jun 28 06:13:37 PM PDT 24
Finished Jun 28 06:17:03 PM PDT 24
Peak memory 206256 kb
Host smart-f36b8b33-1bb0-405e-8ab7-20cdd2372de5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2854063315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.2854063315
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.3110188247
Short name T2281
Test name
Test status
Simulation time 149497605 ps
CPU time 0.77 seconds
Started Jun 28 06:13:34 PM PDT 24
Finished Jun 28 06:13:40 PM PDT 24
Peak memory 206212 kb
Host smart-a1f6bc68-72b5-412b-b1b0-46cace772a00
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3110188247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.3110188247
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.597336408
Short name T2238
Test name
Test status
Simulation time 160758134 ps
CPU time 0.82 seconds
Started Jun 28 06:13:37 PM PDT 24
Finished Jun 28 06:13:43 PM PDT 24
Peak memory 206280 kb
Host smart-a58b51c8-e406-4a0b-bbd6-1737cac4dbed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59733
6408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.597336408
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.4277411503
Short name T121
Test name
Test status
Simulation time 208982268 ps
CPU time 0.88 seconds
Started Jun 28 06:13:37 PM PDT 24
Finished Jun 28 06:13:43 PM PDT 24
Peak memory 206316 kb
Host smart-6fd6176b-ee79-4cd9-a630-e6bba30c5551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42774
11503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.4277411503
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.100016079
Short name T2542
Test name
Test status
Simulation time 163976224 ps
CPU time 0.84 seconds
Started Jun 28 06:13:28 PM PDT 24
Finished Jun 28 06:13:36 PM PDT 24
Peak memory 206196 kb
Host smart-ecde7d39-1379-4da8-8c4c-7bd35b804e38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10001
6079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.100016079
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.2720782035
Short name T332
Test name
Test status
Simulation time 164724253 ps
CPU time 0.77 seconds
Started Jun 28 06:13:27 PM PDT 24
Finished Jun 28 06:13:34 PM PDT 24
Peak memory 206156 kb
Host smart-955f400f-c57f-44d9-bd77-b07765d352ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27207
82035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.2720782035
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.2110790035
Short name T1352
Test name
Test status
Simulation time 202929421 ps
CPU time 0.85 seconds
Started Jun 28 06:13:27 PM PDT 24
Finished Jun 28 06:13:34 PM PDT 24
Peak memory 206212 kb
Host smart-bd0afb19-02d8-466c-b3e8-0ac41672bd3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21107
90035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.2110790035
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.2437251407
Short name T1508
Test name
Test status
Simulation time 152310296 ps
CPU time 0.79 seconds
Started Jun 28 06:13:21 PM PDT 24
Finished Jun 28 06:13:30 PM PDT 24
Peak memory 206124 kb
Host smart-eb5cc916-590f-4c13-b142-79989b23b522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24372
51407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.2437251407
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.4293516464
Short name T335
Test name
Test status
Simulation time 230983434 ps
CPU time 0.88 seconds
Started Jun 28 06:13:26 PM PDT 24
Finished Jun 28 06:13:34 PM PDT 24
Peak memory 206160 kb
Host smart-15549810-3e89-4a35-a50c-bd8ec9f7fa9e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4293516464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.4293516464
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.3495736874
Short name T216
Test name
Test status
Simulation time 149766302 ps
CPU time 0.75 seconds
Started Jun 28 06:13:21 PM PDT 24
Finished Jun 28 06:13:29 PM PDT 24
Peak memory 206152 kb
Host smart-dbfe1d54-745a-456b-b31a-2c3f974307e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34957
36874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.3495736874
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.127356194
Short name T557
Test name
Test status
Simulation time 41151552 ps
CPU time 0.64 seconds
Started Jun 28 06:13:35 PM PDT 24
Finished Jun 28 06:13:41 PM PDT 24
Peak memory 206168 kb
Host smart-7c275770-4e14-4b1c-97c4-19e862d13338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12735
6194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.127356194
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.3294770581
Short name T2307
Test name
Test status
Simulation time 7824517166 ps
CPU time 17.22 seconds
Started Jun 28 06:13:28 PM PDT 24
Finished Jun 28 06:13:52 PM PDT 24
Peak memory 206412 kb
Host smart-8e1b7980-575c-4152-b96f-63057d725a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32947
70581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.3294770581
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.3663934182
Short name T2519
Test name
Test status
Simulation time 155028956 ps
CPU time 0.79 seconds
Started Jun 28 06:13:32 PM PDT 24
Finished Jun 28 06:13:39 PM PDT 24
Peak memory 206156 kb
Host smart-37a1b5fb-cf61-4d34-b45f-4fcaeb0427cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36639
34182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.3663934182
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.2100523590
Short name T345
Test name
Test status
Simulation time 241425025 ps
CPU time 0.82 seconds
Started Jun 28 06:13:32 PM PDT 24
Finished Jun 28 06:13:39 PM PDT 24
Peak memory 206176 kb
Host smart-82762f1e-ba04-4ad3-8870-7343646daa54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21005
23590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.2100523590
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.2446222389
Short name T1259
Test name
Test status
Simulation time 264705209 ps
CPU time 0.87 seconds
Started Jun 28 06:13:31 PM PDT 24
Finished Jun 28 06:13:38 PM PDT 24
Peak memory 206184 kb
Host smart-4ba14574-2d49-449c-b3cc-d2d7986d6547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24462
22389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.2446222389
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.4234868963
Short name T835
Test name
Test status
Simulation time 161487633 ps
CPU time 0.76 seconds
Started Jun 28 06:13:32 PM PDT 24
Finished Jun 28 06:13:39 PM PDT 24
Peak memory 206160 kb
Host smart-de0e017c-e15b-4783-aaae-bb0d636b14e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42348
68963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.4234868963
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.3716551348
Short name T401
Test name
Test status
Simulation time 153669729 ps
CPU time 0.79 seconds
Started Jun 28 06:13:27 PM PDT 24
Finished Jun 28 06:13:34 PM PDT 24
Peak memory 206056 kb
Host smart-069719be-06fd-4393-b601-0f68813daa78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37165
51348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.3716551348
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.2087358875
Short name T1898
Test name
Test status
Simulation time 182503263 ps
CPU time 0.81 seconds
Started Jun 28 06:13:31 PM PDT 24
Finished Jun 28 06:13:39 PM PDT 24
Peak memory 206192 kb
Host smart-75da4f4f-79c1-4a83-a898-64b79e5e69c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20873
58875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.2087358875
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.1753888378
Short name T1979
Test name
Test status
Simulation time 147162352 ps
CPU time 0.79 seconds
Started Jun 28 06:13:20 PM PDT 24
Finished Jun 28 06:13:28 PM PDT 24
Peak memory 206188 kb
Host smart-77973af2-cfeb-407d-890d-9302b0c309ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17538
88378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.1753888378
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.1020852027
Short name T433
Test name
Test status
Simulation time 225187942 ps
CPU time 1.06 seconds
Started Jun 28 06:13:29 PM PDT 24
Finished Jun 28 06:13:36 PM PDT 24
Peak memory 206180 kb
Host smart-0d55cb17-034e-40b6-a4fe-614f6c7569b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10208
52027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.1020852027
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.2054085891
Short name T2253
Test name
Test status
Simulation time 4942108574 ps
CPU time 135.07 seconds
Started Jun 28 06:13:31 PM PDT 24
Finished Jun 28 06:15:53 PM PDT 24
Peak memory 206436 kb
Host smart-90c6b1ea-722d-4ac2-9d1d-1422fb6e6334
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2054085891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.2054085891
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.2839166877
Short name T1384
Test name
Test status
Simulation time 178715448 ps
CPU time 0.89 seconds
Started Jun 28 06:13:31 PM PDT 24
Finished Jun 28 06:13:39 PM PDT 24
Peak memory 206224 kb
Host smart-9d8e46fc-6602-4d1a-bcc7-288d597277cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28391
66877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.2839166877
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.3096889990
Short name T2066
Test name
Test status
Simulation time 170058121 ps
CPU time 0.86 seconds
Started Jun 28 06:13:29 PM PDT 24
Finished Jun 28 06:13:36 PM PDT 24
Peak memory 206196 kb
Host smart-ca175653-0476-471d-99f4-7cfe914d41c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30968
89990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.3096889990
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.1501342314
Short name T2141
Test name
Test status
Simulation time 4829043886 ps
CPU time 34.01 seconds
Started Jun 28 06:13:36 PM PDT 24
Finished Jun 28 06:14:15 PM PDT 24
Peak memory 206436 kb
Host smart-162ee78d-291c-4bc0-8361-97dbc8ce9344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15013
42314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.1501342314
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.1647081291
Short name T2352
Test name
Test status
Simulation time 68427411 ps
CPU time 0.71 seconds
Started Jun 28 06:13:42 PM PDT 24
Finished Jun 28 06:13:45 PM PDT 24
Peak memory 206208 kb
Host smart-afd364dc-9254-4d5f-8d0e-1c78ff048727
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1647081291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.1647081291
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.1691481087
Short name T1405
Test name
Test status
Simulation time 3532280766 ps
CPU time 4.41 seconds
Started Jun 28 06:13:29 PM PDT 24
Finished Jun 28 06:13:39 PM PDT 24
Peak memory 206248 kb
Host smart-63cce671-5136-435a-b11a-360a5f0bad27
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1691481087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.1691481087
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.3104645420
Short name T537
Test name
Test status
Simulation time 13308241515 ps
CPU time 15.72 seconds
Started Jun 28 06:13:30 PM PDT 24
Finished Jun 28 06:13:51 PM PDT 24
Peak memory 206348 kb
Host smart-b01fe127-d49d-4b8f-ade3-84961389316f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3104645420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.3104645420
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.4151007583
Short name T2314
Test name
Test status
Simulation time 23307157030 ps
CPU time 22.61 seconds
Started Jun 28 06:13:31 PM PDT 24
Finished Jun 28 06:14:00 PM PDT 24
Peak memory 206276 kb
Host smart-254b38d5-2d72-494b-8e2f-6bf51e7d11db
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4151007583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.4151007583
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.1273480737
Short name T1788
Test name
Test status
Simulation time 198121942 ps
CPU time 0.82 seconds
Started Jun 28 06:13:34 PM PDT 24
Finished Jun 28 06:13:41 PM PDT 24
Peak memory 206192 kb
Host smart-579303a0-7873-4464-988d-e770f518e847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12734
80737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.1273480737
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.3079581441
Short name T2289
Test name
Test status
Simulation time 193295965 ps
CPU time 0.8 seconds
Started Jun 28 06:13:29 PM PDT 24
Finished Jun 28 06:13:36 PM PDT 24
Peak memory 206168 kb
Host smart-911d05e0-b0aa-47c6-b484-ce515e59e764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30795
81441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.3079581441
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.1355296109
Short name T100
Test name
Test status
Simulation time 536633167 ps
CPU time 1.58 seconds
Started Jun 28 06:13:30 PM PDT 24
Finished Jun 28 06:13:37 PM PDT 24
Peak memory 206356 kb
Host smart-efffc08e-2ee7-40e7-b22b-425c1f7ed982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13552
96109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.1355296109
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.4236947043
Short name T1568
Test name
Test status
Simulation time 552348291 ps
CPU time 1.51 seconds
Started Jun 28 06:13:30 PM PDT 24
Finished Jun 28 06:13:38 PM PDT 24
Peak memory 206188 kb
Host smart-eba67062-4f67-436d-8e8b-39cf3181bd87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42369
47043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.4236947043
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.2612998576
Short name T1364
Test name
Test status
Simulation time 10876392295 ps
CPU time 19.52 seconds
Started Jun 28 06:13:31 PM PDT 24
Finished Jun 28 06:13:57 PM PDT 24
Peak memory 206412 kb
Host smart-34abde8c-4c12-4075-aff3-d2eff32e5079
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26129
98576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.2612998576
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.2940702286
Short name T1590
Test name
Test status
Simulation time 376854017 ps
CPU time 1.28 seconds
Started Jun 28 06:13:30 PM PDT 24
Finished Jun 28 06:13:38 PM PDT 24
Peak memory 206324 kb
Host smart-c6c15343-a46f-4819-bdab-ab913c981973
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29407
02286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.2940702286
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.1192851759
Short name T419
Test name
Test status
Simulation time 151991235 ps
CPU time 0.81 seconds
Started Jun 28 06:13:31 PM PDT 24
Finished Jun 28 06:13:38 PM PDT 24
Peak memory 206192 kb
Host smart-bf6302fe-7bec-4914-bac7-1f2cffd44874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11928
51759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.1192851759
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.3729344058
Short name T1046
Test name
Test status
Simulation time 36575477 ps
CPU time 0.68 seconds
Started Jun 28 06:13:33 PM PDT 24
Finished Jun 28 06:13:39 PM PDT 24
Peak memory 206184 kb
Host smart-ef8a01cf-1d04-4ab0-a4e0-94f788c90bec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37293
44058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.3729344058
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.3811566056
Short name T643
Test name
Test status
Simulation time 639835289 ps
CPU time 1.67 seconds
Started Jun 28 06:13:37 PM PDT 24
Finished Jun 28 06:13:44 PM PDT 24
Peak memory 206376 kb
Host smart-64d368d5-bbf0-49ed-a57c-bdceb679dbc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38115
66056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.3811566056
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.3694130602
Short name T2377
Test name
Test status
Simulation time 185475843 ps
CPU time 1.63 seconds
Started Jun 28 06:13:29 PM PDT 24
Finished Jun 28 06:13:37 PM PDT 24
Peak memory 206280 kb
Host smart-cd6de37f-b0b4-4d51-99f4-acf722063d1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36941
30602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.3694130602
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.2210534251
Short name T951
Test name
Test status
Simulation time 169957600 ps
CPU time 0.87 seconds
Started Jun 28 06:13:33 PM PDT 24
Finished Jun 28 06:13:39 PM PDT 24
Peak memory 206152 kb
Host smart-d91cf149-6736-4c38-aaeb-864555a69faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22105
34251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.2210534251
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.2424792141
Short name T1197
Test name
Test status
Simulation time 139487042 ps
CPU time 0.77 seconds
Started Jun 28 06:13:37 PM PDT 24
Finished Jun 28 06:13:43 PM PDT 24
Peak memory 206216 kb
Host smart-7c0522df-a80c-4904-9e62-383e6382cd01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24247
92141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.2424792141
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.2044045390
Short name T1084
Test name
Test status
Simulation time 182396453 ps
CPU time 0.84 seconds
Started Jun 28 06:13:32 PM PDT 24
Finished Jun 28 06:13:39 PM PDT 24
Peak memory 206208 kb
Host smart-d48ba0fb-cc7d-484f-a767-e043b4f00057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20440
45390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.2044045390
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.3620814158
Short name T1399
Test name
Test status
Simulation time 236522690 ps
CPU time 0.86 seconds
Started Jun 28 06:13:31 PM PDT 24
Finished Jun 28 06:13:42 PM PDT 24
Peak memory 206192 kb
Host smart-4d506c2d-f3ed-4a4c-9717-f0f6db2f4042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36208
14158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.3620814158
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.3083769492
Short name T1206
Test name
Test status
Simulation time 23280161309 ps
CPU time 25.59 seconds
Started Jun 28 06:13:29 PM PDT 24
Finished Jun 28 06:14:00 PM PDT 24
Peak memory 206312 kb
Host smart-97ec0de9-136a-4780-8ac0-6bd68737ba94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30837
69492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.3083769492
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.1020798163
Short name T1807
Test name
Test status
Simulation time 3315058516 ps
CPU time 3.8 seconds
Started Jun 28 06:13:29 PM PDT 24
Finished Jun 28 06:13:39 PM PDT 24
Peak memory 206252 kb
Host smart-e19e956d-c65e-44d6-b616-b8a45dfb80ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10207
98163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.1020798163
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.345846672
Short name T2074
Test name
Test status
Simulation time 6411219691 ps
CPU time 164.24 seconds
Started Jun 28 06:13:28 PM PDT 24
Finished Jun 28 06:16:19 PM PDT 24
Peak memory 206472 kb
Host smart-604b5212-4c9b-4d11-970e-89651503f8b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34584
6672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.345846672
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.3897548277
Short name T1130
Test name
Test status
Simulation time 5525402839 ps
CPU time 155.15 seconds
Started Jun 28 06:13:32 PM PDT 24
Finished Jun 28 06:16:13 PM PDT 24
Peak memory 206456 kb
Host smart-012ef92c-6cc1-430c-83e8-9009094f60bc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3897548277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.3897548277
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.2604893533
Short name T1501
Test name
Test status
Simulation time 239034740 ps
CPU time 0.89 seconds
Started Jun 28 06:13:30 PM PDT 24
Finished Jun 28 06:13:37 PM PDT 24
Peak memory 206188 kb
Host smart-639a170c-7a49-4fa7-ba43-018a5574d7fc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2604893533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.2604893533
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.3643124301
Short name T2049
Test name
Test status
Simulation time 202237335 ps
CPU time 0.87 seconds
Started Jun 28 06:13:35 PM PDT 24
Finished Jun 28 06:13:42 PM PDT 24
Peak memory 206204 kb
Host smart-f6b925b9-6dc6-4b6e-9e8d-fbef05ea0e67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36431
24301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.3643124301
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.2565857399
Short name T1929
Test name
Test status
Simulation time 3449482624 ps
CPU time 24.64 seconds
Started Jun 28 06:13:29 PM PDT 24
Finished Jun 28 06:14:00 PM PDT 24
Peak memory 206492 kb
Host smart-f596a722-c1f9-4fe9-b999-964a850cc09b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25658
57399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.2565857399
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.2531742453
Short name T1374
Test name
Test status
Simulation time 4226520219 ps
CPU time 118.61 seconds
Started Jun 28 06:13:36 PM PDT 24
Finished Jun 28 06:15:40 PM PDT 24
Peak memory 206456 kb
Host smart-4c3c10a4-40cb-45f7-819a-d3199181c08a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2531742453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.2531742453
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.7146777
Short name T340
Test name
Test status
Simulation time 160335085 ps
CPU time 0.81 seconds
Started Jun 28 06:13:33 PM PDT 24
Finished Jun 28 06:13:39 PM PDT 24
Peak memory 206200 kb
Host smart-a6e3865a-bfdb-4ebe-b81a-a20bb968a2d3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=7146777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.7146777
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.2026621122
Short name T1977
Test name
Test status
Simulation time 175823686 ps
CPU time 0.83 seconds
Started Jun 28 06:13:32 PM PDT 24
Finished Jun 28 06:13:39 PM PDT 24
Peak memory 206140 kb
Host smart-bad0e08e-7f45-4163-b114-b2706399ca70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20266
21122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.2026621122
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.1203733930
Short name T128
Test name
Test status
Simulation time 235159623 ps
CPU time 0.91 seconds
Started Jun 28 06:13:29 PM PDT 24
Finished Jun 28 06:13:36 PM PDT 24
Peak memory 206192 kb
Host smart-effe0ef0-e960-42a0-9377-cf7d46c53cbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12037
33930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.1203733930
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.3755765008
Short name T1293
Test name
Test status
Simulation time 175137395 ps
CPU time 0.8 seconds
Started Jun 28 06:13:43 PM PDT 24
Finished Jun 28 06:13:46 PM PDT 24
Peak memory 206204 kb
Host smart-be47f151-f8bf-4055-9321-1b8a45bcae37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37557
65008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.3755765008
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.1449403930
Short name T802
Test name
Test status
Simulation time 170319585 ps
CPU time 0.79 seconds
Started Jun 28 06:13:30 PM PDT 24
Finished Jun 28 06:13:36 PM PDT 24
Peak memory 206188 kb
Host smart-f7ecf21c-1cc1-4637-af46-4b8fc259dc9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14494
03930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.1449403930
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.3876737601
Short name T961
Test name
Test status
Simulation time 182149131 ps
CPU time 0.82 seconds
Started Jun 28 06:13:30 PM PDT 24
Finished Jun 28 06:13:37 PM PDT 24
Peak memory 206324 kb
Host smart-c576b18b-e719-4da5-afff-76d7622e41e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38767
37601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.3876737601
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.126413631
Short name T1096
Test name
Test status
Simulation time 164641066 ps
CPU time 0.78 seconds
Started Jun 28 06:13:32 PM PDT 24
Finished Jun 28 06:13:39 PM PDT 24
Peak memory 206200 kb
Host smart-051673ea-361d-4ee4-a0fa-e92eb360b8d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12641
3631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.126413631
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.1709189597
Short name T1260
Test name
Test status
Simulation time 216111679 ps
CPU time 0.89 seconds
Started Jun 28 06:13:29 PM PDT 24
Finished Jun 28 06:13:36 PM PDT 24
Peak memory 206188 kb
Host smart-c6c5fe15-0d4d-433c-a922-67aa29c3d9b2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1709189597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.1709189597
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.986506823
Short name T1074
Test name
Test status
Simulation time 146744149 ps
CPU time 0.77 seconds
Started Jun 28 06:13:36 PM PDT 24
Finished Jun 28 06:13:42 PM PDT 24
Peak memory 206208 kb
Host smart-c8b8aa93-aea2-42a9-bf65-c56b2fde8c8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98650
6823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.986506823
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.79679890
Short name T1053
Test name
Test status
Simulation time 37155142 ps
CPU time 0.64 seconds
Started Jun 28 06:13:31 PM PDT 24
Finished Jun 28 06:13:38 PM PDT 24
Peak memory 206208 kb
Host smart-c6716c9c-c89e-4dfd-94a0-fb7992d83912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79679
890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.79679890
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.2408076820
Short name T1214
Test name
Test status
Simulation time 21479472450 ps
CPU time 47.37 seconds
Started Jun 28 06:13:32 PM PDT 24
Finished Jun 28 06:14:25 PM PDT 24
Peak memory 206508 kb
Host smart-55a23f1b-3bc8-4bc5-90f3-f54ec7b71ab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24080
76820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.2408076820
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.2101955305
Short name T2537
Test name
Test status
Simulation time 188578283 ps
CPU time 0.86 seconds
Started Jun 28 06:13:32 PM PDT 24
Finished Jun 28 06:13:39 PM PDT 24
Peak memory 206132 kb
Host smart-cda9a24a-029a-4341-9281-0bf4a35b764f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21019
55305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.2101955305
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.1191087515
Short name T1685
Test name
Test status
Simulation time 211055471 ps
CPU time 0.87 seconds
Started Jun 28 06:13:31 PM PDT 24
Finished Jun 28 06:13:38 PM PDT 24
Peak memory 206208 kb
Host smart-9600ae9f-04b3-4675-bdf9-de78fad43c82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11910
87515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.1191087515
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.941684294
Short name T842
Test name
Test status
Simulation time 209042973 ps
CPU time 0.88 seconds
Started Jun 28 06:13:36 PM PDT 24
Finished Jun 28 06:13:42 PM PDT 24
Peak memory 206216 kb
Host smart-a844cc06-bbe7-4bea-b657-cce43ab4fbd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94168
4294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.941684294
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.1227761957
Short name T705
Test name
Test status
Simulation time 227371918 ps
CPU time 0.92 seconds
Started Jun 28 06:13:42 PM PDT 24
Finished Jun 28 06:13:46 PM PDT 24
Peak memory 206188 kb
Host smart-bafdbb7a-3db2-4e9c-8b94-3f752ebf2698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12277
61957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.1227761957
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.2923448903
Short name T1285
Test name
Test status
Simulation time 163550019 ps
CPU time 0.75 seconds
Started Jun 28 06:13:51 PM PDT 24
Finished Jun 28 06:13:54 PM PDT 24
Peak memory 206032 kb
Host smart-1e91e827-f8ba-4867-821a-ca7a55e9a84c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29234
48903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.2923448903
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.860076242
Short name T2
Test name
Test status
Simulation time 160316595 ps
CPU time 0.79 seconds
Started Jun 28 06:13:45 PM PDT 24
Finished Jun 28 06:13:47 PM PDT 24
Peak memory 206172 kb
Host smart-a5871c76-57f2-414a-ae84-ad3e24815030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86007
6242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.860076242
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.2723691836
Short name T86
Test name
Test status
Simulation time 199728657 ps
CPU time 0.85 seconds
Started Jun 28 06:13:47 PM PDT 24
Finished Jun 28 06:13:49 PM PDT 24
Peak memory 206176 kb
Host smart-56a7324a-b350-40cd-ae16-e2cfe060df6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27236
91836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.2723691836
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.2727393919
Short name T696
Test name
Test status
Simulation time 242349989 ps
CPU time 0.96 seconds
Started Jun 28 06:13:43 PM PDT 24
Finished Jun 28 06:13:46 PM PDT 24
Peak memory 206196 kb
Host smart-754ba08c-a160-4eb1-b94b-19759125ea6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27273
93919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.2727393919
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.4190428893
Short name T1376
Test name
Test status
Simulation time 4486275036 ps
CPU time 30.87 seconds
Started Jun 28 06:13:42 PM PDT 24
Finished Jun 28 06:14:16 PM PDT 24
Peak memory 206396 kb
Host smart-240a1c65-1a16-425f-9255-392dbf585b51
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4190428893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.4190428893
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.3609515229
Short name T2334
Test name
Test status
Simulation time 199410446 ps
CPU time 0.85 seconds
Started Jun 28 06:13:42 PM PDT 24
Finished Jun 28 06:13:46 PM PDT 24
Peak memory 206224 kb
Host smart-04957cdf-31a5-4ffa-ad13-eac29a0734b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36095
15229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.3609515229
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.1601016481
Short name T2298
Test name
Test status
Simulation time 213601343 ps
CPU time 0.85 seconds
Started Jun 28 06:13:45 PM PDT 24
Finished Jun 28 06:13:47 PM PDT 24
Peak memory 206192 kb
Host smart-8e17da77-7276-47c4-83fd-e1bb0a14bcaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16010
16481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.1601016481
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.123618274
Short name T1165
Test name
Test status
Simulation time 6519847298 ps
CPU time 178.96 seconds
Started Jun 28 06:13:51 PM PDT 24
Finished Jun 28 06:16:51 PM PDT 24
Peak memory 206456 kb
Host smart-33a1bd55-4e84-46e7-aeff-3baae40b21ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12361
8274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.123618274
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.2416760629
Short name T1906
Test name
Test status
Simulation time 40506442 ps
CPU time 0.77 seconds
Started Jun 28 06:14:04 PM PDT 24
Finished Jun 28 06:14:09 PM PDT 24
Peak memory 206208 kb
Host smart-ffc51a8c-eaae-4a4d-b882-69f8afde302c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2416760629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.2416760629
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.1392796916
Short name T1992
Test name
Test status
Simulation time 4286100332 ps
CPU time 5.31 seconds
Started Jun 28 06:13:46 PM PDT 24
Finished Jun 28 06:13:52 PM PDT 24
Peak memory 206272 kb
Host smart-f06a9c99-6a2c-43b4-8d25-7a9543401d6d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1392796916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.1392796916
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.2396118516
Short name T576
Test name
Test status
Simulation time 13436657854 ps
CPU time 13.25 seconds
Started Jun 28 06:13:54 PM PDT 24
Finished Jun 28 06:14:10 PM PDT 24
Peak memory 206436 kb
Host smart-8d5cd9f2-d9c6-44dd-86d2-c5a3a7475a74
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2396118516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.2396118516
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.1028255082
Short name T1452
Test name
Test status
Simulation time 23406924746 ps
CPU time 26.5 seconds
Started Jun 28 06:13:46 PM PDT 24
Finished Jun 28 06:14:13 PM PDT 24
Peak memory 206568 kb
Host smart-e3609949-1d27-448e-be69-0de13de202b1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1028255082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.1028255082
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.2303818901
Short name T1669
Test name
Test status
Simulation time 158351110 ps
CPU time 0.83 seconds
Started Jun 28 06:13:49 PM PDT 24
Finished Jun 28 06:13:50 PM PDT 24
Peak memory 206200 kb
Host smart-2708b7cd-fa69-4442-bd8c-646abbca19aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23038
18901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.2303818901
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.3658863478
Short name T1338
Test name
Test status
Simulation time 154995265 ps
CPU time 0.83 seconds
Started Jun 28 06:13:40 PM PDT 24
Finished Jun 28 06:13:45 PM PDT 24
Peak memory 206160 kb
Host smart-73623896-0896-4222-82cc-3d3d0c08c0d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36588
63478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.3658863478
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.3827362756
Short name T99
Test name
Test status
Simulation time 534721869 ps
CPU time 1.55 seconds
Started Jun 28 06:13:54 PM PDT 24
Finished Jun 28 06:13:59 PM PDT 24
Peak memory 206292 kb
Host smart-eca32e4d-7dc1-4390-aea3-69e667c37fb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38273
62756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.3827362756
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.403746036
Short name T1981
Test name
Test status
Simulation time 1557774234 ps
CPU time 3.46 seconds
Started Jun 28 06:13:46 PM PDT 24
Finished Jun 28 06:13:50 PM PDT 24
Peak memory 206272 kb
Host smart-61cd2ec4-d526-42cf-82aa-5a45db5bbb25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40374
6036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.403746036
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.153667513
Short name T1391
Test name
Test status
Simulation time 6463786413 ps
CPU time 12.35 seconds
Started Jun 28 06:13:48 PM PDT 24
Finished Jun 28 06:14:01 PM PDT 24
Peak memory 206408 kb
Host smart-7244998b-3d39-4d1e-abfb-4ec19cd8a983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15366
7513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.153667513
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.2089782682
Short name T1492
Test name
Test status
Simulation time 465879109 ps
CPU time 1.34 seconds
Started Jun 28 06:13:54 PM PDT 24
Finished Jun 28 06:13:58 PM PDT 24
Peak memory 206192 kb
Host smart-ea054a1b-18c3-4619-9f65-bb7731ef9afc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20897
82682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.2089782682
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.2077086227
Short name T2575
Test name
Test status
Simulation time 163864586 ps
CPU time 0.76 seconds
Started Jun 28 06:13:51 PM PDT 24
Finished Jun 28 06:13:54 PM PDT 24
Peak memory 206032 kb
Host smart-7112e278-28fd-48c2-b3e9-8164ba07a780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20770
86227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.2077086227
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.659559272
Short name T1693
Test name
Test status
Simulation time 27695728 ps
CPU time 0.65 seconds
Started Jun 28 06:13:55 PM PDT 24
Finished Jun 28 06:13:59 PM PDT 24
Peak memory 206200 kb
Host smart-41ebcdeb-aeea-4d54-8c3c-73c3e56dcc15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65955
9272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.659559272
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.3687470348
Short name T604
Test name
Test status
Simulation time 800390048 ps
CPU time 2.19 seconds
Started Jun 28 06:13:49 PM PDT 24
Finished Jun 28 06:13:52 PM PDT 24
Peak memory 206268 kb
Host smart-27501cb9-7832-4460-8ab9-85e437cda82c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36874
70348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.3687470348
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.1732574288
Short name T1441
Test name
Test status
Simulation time 274038372 ps
CPU time 1.95 seconds
Started Jun 28 06:13:54 PM PDT 24
Finished Jun 28 06:13:59 PM PDT 24
Peak memory 206312 kb
Host smart-cf824e94-14f4-4333-820e-f6e8c79e1270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17325
74288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.1732574288
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.3974294131
Short name T2358
Test name
Test status
Simulation time 189098097 ps
CPU time 0.83 seconds
Started Jun 28 06:13:46 PM PDT 24
Finished Jun 28 06:13:48 PM PDT 24
Peak memory 206180 kb
Host smart-f283dfc8-faab-4892-b832-f649d9f94ce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39742
94131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.3974294131
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.2821382860
Short name T824
Test name
Test status
Simulation time 148963223 ps
CPU time 0.74 seconds
Started Jun 28 06:13:55 PM PDT 24
Finished Jun 28 06:13:59 PM PDT 24
Peak memory 206204 kb
Host smart-83bac146-4a2a-4e1f-9da6-5c0fa98357a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28213
82860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.2821382860
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.1358212629
Short name T1813
Test name
Test status
Simulation time 219683621 ps
CPU time 0.97 seconds
Started Jun 28 06:13:46 PM PDT 24
Finished Jun 28 06:13:48 PM PDT 24
Peak memory 206216 kb
Host smart-01524779-38ab-4b18-a3a1-8f203fee7f48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13582
12629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.1358212629
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.2923927184
Short name T710
Test name
Test status
Simulation time 236523578 ps
CPU time 0.86 seconds
Started Jun 28 06:13:53 PM PDT 24
Finished Jun 28 06:13:57 PM PDT 24
Peak memory 206180 kb
Host smart-249fb030-ac34-4381-bd36-84369ccd6b4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29239
27184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.2923927184
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.1915154796
Short name T690
Test name
Test status
Simulation time 23291647933 ps
CPU time 27.11 seconds
Started Jun 28 06:13:47 PM PDT 24
Finished Jun 28 06:14:15 PM PDT 24
Peak memory 206308 kb
Host smart-19583cd9-9fc2-4da1-b331-a20b5897a47e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19151
54796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.1915154796
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.524869
Short name T222
Test name
Test status
Simulation time 3315878535 ps
CPU time 3.7 seconds
Started Jun 28 06:13:49 PM PDT 24
Finished Jun 28 06:13:54 PM PDT 24
Peak memory 206256 kb
Host smart-a6378b36-2cb8-4fa9-b266-110b0630bebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52486
9 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.524869
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.4095984998
Short name T1136
Test name
Test status
Simulation time 7983103415 ps
CPU time 71.78 seconds
Started Jun 28 06:13:50 PM PDT 24
Finished Jun 28 06:15:03 PM PDT 24
Peak memory 206428 kb
Host smart-7ad13db1-7cb7-457d-929c-d2d9edad3d12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40959
84998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.4095984998
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.1826768100
Short name T2091
Test name
Test status
Simulation time 4467193043 ps
CPU time 125.67 seconds
Started Jun 28 06:13:55 PM PDT 24
Finished Jun 28 06:16:05 PM PDT 24
Peak memory 206484 kb
Host smart-1a8a6442-553d-4c9f-b959-788355052620
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1826768100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.1826768100
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.3034687692
Short name T1146
Test name
Test status
Simulation time 255675960 ps
CPU time 0.96 seconds
Started Jun 28 06:13:53 PM PDT 24
Finished Jun 28 06:13:57 PM PDT 24
Peak memory 206188 kb
Host smart-068b5cbc-4c98-431d-a3e0-7fcc3b7613f2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3034687692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.3034687692
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.2856413142
Short name T2335
Test name
Test status
Simulation time 218088126 ps
CPU time 0.86 seconds
Started Jun 28 06:13:54 PM PDT 24
Finished Jun 28 06:13:57 PM PDT 24
Peak memory 206196 kb
Host smart-550bd7b7-a140-4a62-b45d-149624b536ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28564
13142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.2856413142
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.538975363
Short name T1589
Test name
Test status
Simulation time 5227952730 ps
CPU time 37.6 seconds
Started Jun 28 06:13:41 PM PDT 24
Finished Jun 28 06:14:22 PM PDT 24
Peak memory 206420 kb
Host smart-8ccfe63b-7bef-4da0-a8ce-dd348635de62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53897
5363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.538975363
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.654341741
Short name T2392
Test name
Test status
Simulation time 4694772849 ps
CPU time 128.83 seconds
Started Jun 28 06:13:39 PM PDT 24
Finished Jun 28 06:15:52 PM PDT 24
Peak memory 206456 kb
Host smart-fd154c8a-b3f9-4cb2-ae5e-c33b8af288ed
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=654341741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.654341741
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.3024436280
Short name T495
Test name
Test status
Simulation time 156934197 ps
CPU time 0.79 seconds
Started Jun 28 06:13:51 PM PDT 24
Finished Jun 28 06:13:53 PM PDT 24
Peak memory 206220 kb
Host smart-9ed7d3d2-8d10-4465-95f9-8f774ebffdb9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3024436280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.3024436280
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.1195344696
Short name T1095
Test name
Test status
Simulation time 164828862 ps
CPU time 0.87 seconds
Started Jun 28 06:13:51 PM PDT 24
Finished Jun 28 06:13:54 PM PDT 24
Peak memory 206208 kb
Host smart-53d63bde-a8ef-41b1-9deb-96a25d80b843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11953
44696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.1195344696
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.2292261606
Short name T1882
Test name
Test status
Simulation time 264227397 ps
CPU time 1.09 seconds
Started Jun 28 06:13:57 PM PDT 24
Finished Jun 28 06:14:02 PM PDT 24
Peak memory 206188 kb
Host smart-48a63ded-89b5-4d96-9b35-e13355916ef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22922
61606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.2292261606
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.1441359564
Short name T924
Test name
Test status
Simulation time 199582247 ps
CPU time 0.86 seconds
Started Jun 28 06:14:02 PM PDT 24
Finished Jun 28 06:14:07 PM PDT 24
Peak memory 206132 kb
Host smart-65bbf94e-7957-4bc5-948f-8e81f567a819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14413
59564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.1441359564
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.3495450692
Short name T1744
Test name
Test status
Simulation time 186339023 ps
CPU time 0.88 seconds
Started Jun 28 06:13:57 PM PDT 24
Finished Jun 28 06:14:02 PM PDT 24
Peak memory 206192 kb
Host smart-a80d1c45-d705-463e-9f0c-471a4bba8a63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34954
50692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.3495450692
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.2118070811
Short name T480
Test name
Test status
Simulation time 200528239 ps
CPU time 0.89 seconds
Started Jun 28 06:13:57 PM PDT 24
Finished Jun 28 06:14:02 PM PDT 24
Peak memory 206208 kb
Host smart-d6e5172c-1812-4c5b-84ec-20a4272a7d13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21180
70811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.2118070811
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.4053296566
Short name T173
Test name
Test status
Simulation time 144947656 ps
CPU time 0.77 seconds
Started Jun 28 06:13:53 PM PDT 24
Finished Jun 28 06:13:56 PM PDT 24
Peak memory 206188 kb
Host smart-caaf3d23-0169-429a-a17e-9d244906885c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40532
96566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.4053296566
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.1505705512
Short name T2323
Test name
Test status
Simulation time 222543869 ps
CPU time 0.99 seconds
Started Jun 28 06:13:52 PM PDT 24
Finished Jun 28 06:13:55 PM PDT 24
Peak memory 206136 kb
Host smart-eba32426-94c5-4c0c-b4e3-d65afaad211d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1505705512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.1505705512
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.2821539854
Short name T1354
Test name
Test status
Simulation time 170240460 ps
CPU time 0.82 seconds
Started Jun 28 06:13:53 PM PDT 24
Finished Jun 28 06:13:56 PM PDT 24
Peak memory 206188 kb
Host smart-601e5504-921b-40e7-9359-dfb70f2e2a0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28215
39854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.2821539854
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.2103264531
Short name T1090
Test name
Test status
Simulation time 56771783 ps
CPU time 0.7 seconds
Started Jun 28 06:13:52 PM PDT 24
Finished Jun 28 06:13:55 PM PDT 24
Peak memory 206344 kb
Host smart-4a58f02e-f0e9-406e-80b3-97a1788a83e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21032
64531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.2103264531
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.147835412
Short name T1390
Test name
Test status
Simulation time 19795143800 ps
CPU time 47.55 seconds
Started Jun 28 06:13:53 PM PDT 24
Finished Jun 28 06:14:43 PM PDT 24
Peak memory 206492 kb
Host smart-b19898f9-24a1-4145-84f9-a49f930a0e8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14783
5412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.147835412
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.658709593
Short name T1852
Test name
Test status
Simulation time 154516949 ps
CPU time 0.82 seconds
Started Jun 28 06:14:03 PM PDT 24
Finished Jun 28 06:14:07 PM PDT 24
Peak memory 206192 kb
Host smart-c529c7f7-999f-47d9-8fec-0ddc316559d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65870
9593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.658709593
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.823547341
Short name T2078
Test name
Test status
Simulation time 180363218 ps
CPU time 0.89 seconds
Started Jun 28 06:14:03 PM PDT 24
Finished Jun 28 06:14:07 PM PDT 24
Peak memory 206204 kb
Host smart-92139c72-9a1a-4ce6-a06e-7d2500a67a71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82354
7341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.823547341
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.1975299168
Short name T2612
Test name
Test status
Simulation time 196219245 ps
CPU time 0.9 seconds
Started Jun 28 06:13:52 PM PDT 24
Finished Jun 28 06:13:55 PM PDT 24
Peak memory 206224 kb
Host smart-40fe03d2-732b-4569-a248-e717cddf593a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19752
99168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.1975299168
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.704143028
Short name T736
Test name
Test status
Simulation time 242429729 ps
CPU time 0.88 seconds
Started Jun 28 06:13:56 PM PDT 24
Finished Jun 28 06:14:00 PM PDT 24
Peak memory 206192 kb
Host smart-86d93021-f56f-4527-a579-c5b657ad2c95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70414
3028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.704143028
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.3318101399
Short name T487
Test name
Test status
Simulation time 213943482 ps
CPU time 0.83 seconds
Started Jun 28 06:13:52 PM PDT 24
Finished Jun 28 06:13:55 PM PDT 24
Peak memory 206112 kb
Host smart-5065f0e7-8906-438c-ab6f-38e2751a0d58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33181
01399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.3318101399
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.3372727171
Short name T428
Test name
Test status
Simulation time 149575503 ps
CPU time 0.8 seconds
Started Jun 28 06:13:57 PM PDT 24
Finished Jun 28 06:14:01 PM PDT 24
Peak memory 206188 kb
Host smart-32a8dca7-7fa7-4c8c-b191-9a33f4a6e312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33727
27171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.3372727171
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.1476492015
Short name T632
Test name
Test status
Simulation time 174980369 ps
CPU time 0.83 seconds
Started Jun 28 06:13:52 PM PDT 24
Finished Jun 28 06:13:54 PM PDT 24
Peak memory 206196 kb
Host smart-1c579a5d-cf43-43aa-814b-dc3a1b8026d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14764
92015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.1476492015
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.1825464403
Short name T1383
Test name
Test status
Simulation time 229196463 ps
CPU time 0.99 seconds
Started Jun 28 06:13:57 PM PDT 24
Finished Jun 28 06:14:02 PM PDT 24
Peak memory 206212 kb
Host smart-6bde63b6-c0de-4bfe-8c0e-105e35e1fb16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18254
64403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.1825464403
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.646615980
Short name T1469
Test name
Test status
Simulation time 6183281473 ps
CPU time 47.89 seconds
Started Jun 28 06:13:53 PM PDT 24
Finished Jun 28 06:14:43 PM PDT 24
Peak memory 206416 kb
Host smart-9b05a781-5c4b-4bb2-a9db-d69b58923225
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=646615980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.646615980
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.4189365677
Short name T2603
Test name
Test status
Simulation time 237473409 ps
CPU time 0.85 seconds
Started Jun 28 06:13:51 PM PDT 24
Finished Jun 28 06:13:52 PM PDT 24
Peak memory 206220 kb
Host smart-39b9e1ff-9a71-4681-9ee8-71c1710055c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41893
65677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.4189365677
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.4201826693
Short name T878
Test name
Test status
Simulation time 156944766 ps
CPU time 0.81 seconds
Started Jun 28 06:13:56 PM PDT 24
Finished Jun 28 06:14:01 PM PDT 24
Peak memory 206168 kb
Host smart-f5bb2729-9ee7-4599-9efc-b7c4c51be240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42018
26693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.4201826693
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.4000255982
Short name T2283
Test name
Test status
Simulation time 6175672239 ps
CPU time 173.36 seconds
Started Jun 28 06:13:51 PM PDT 24
Finished Jun 28 06:16:46 PM PDT 24
Peak memory 206372 kb
Host smart-df842081-1817-4999-a397-1dff8a3ae3e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40002
55982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.4000255982
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.1236789340
Short name T2179
Test name
Test status
Simulation time 45036676 ps
CPU time 0.69 seconds
Started Jun 28 06:14:03 PM PDT 24
Finished Jun 28 06:14:08 PM PDT 24
Peak memory 206164 kb
Host smart-3d22c6be-c402-4ee0-b4cb-b4f78d597e60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1236789340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.1236789340
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.772234084
Short name T893
Test name
Test status
Simulation time 3775378049 ps
CPU time 4.74 seconds
Started Jun 28 06:13:57 PM PDT 24
Finished Jun 28 06:14:05 PM PDT 24
Peak memory 206384 kb
Host smart-91c88bcc-6ac0-4acb-b14a-5b45892534e8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=772234084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.772234084
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.2192800951
Short name T196
Test name
Test status
Simulation time 13394469415 ps
CPU time 13.2 seconds
Started Jun 28 06:13:57 PM PDT 24
Finished Jun 28 06:14:14 PM PDT 24
Peak memory 206484 kb
Host smart-60d01f66-1fcc-45d3-afe1-41c52cc82add
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2192800951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.2192800951
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.3734055985
Short name T2009
Test name
Test status
Simulation time 23474517398 ps
CPU time 23.5 seconds
Started Jun 28 06:13:56 PM PDT 24
Finished Jun 28 06:14:24 PM PDT 24
Peak memory 206480 kb
Host smart-93ce7c5f-6a7b-4fd5-beb6-f0d56e955a2f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3734055985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.3734055985
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.609661816
Short name T1563
Test name
Test status
Simulation time 194278735 ps
CPU time 0.9 seconds
Started Jun 28 06:13:53 PM PDT 24
Finished Jun 28 06:13:57 PM PDT 24
Peak memory 206212 kb
Host smart-33c221a5-fb99-41e5-b1dd-a4099d09117c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60966
1816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.609661816
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.4061883879
Short name T2500
Test name
Test status
Simulation time 147964065 ps
CPU time 0.77 seconds
Started Jun 28 06:13:51 PM PDT 24
Finished Jun 28 06:13:54 PM PDT 24
Peak memory 206192 kb
Host smart-6c9e15aa-f32e-4c98-ad11-d16fdd4a92ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40618
83879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.4061883879
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.4082784877
Short name T1869
Test name
Test status
Simulation time 324091252 ps
CPU time 1.17 seconds
Started Jun 28 06:13:59 PM PDT 24
Finished Jun 28 06:14:05 PM PDT 24
Peak memory 206196 kb
Host smart-8646d1d3-a905-4a34-aae5-680c9b0f1557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40827
84877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.4082784877
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.579285009
Short name T1142
Test name
Test status
Simulation time 657031456 ps
CPU time 1.51 seconds
Started Jun 28 06:13:55 PM PDT 24
Finished Jun 28 06:14:00 PM PDT 24
Peak memory 206196 kb
Host smart-105a2d3f-5c13-4fed-b072-e6a56210c38d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57928
5009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.579285009
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.2763821568
Short name T1582
Test name
Test status
Simulation time 381549001 ps
CPU time 1.23 seconds
Started Jun 28 06:13:54 PM PDT 24
Finished Jun 28 06:13:58 PM PDT 24
Peak memory 206200 kb
Host smart-8d9e3261-5eeb-4915-80e1-793b6a2b34b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27638
21568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.2763821568
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.4222637620
Short name T1360
Test name
Test status
Simulation time 203831846 ps
CPU time 0.82 seconds
Started Jun 28 06:14:00 PM PDT 24
Finished Jun 28 06:14:05 PM PDT 24
Peak memory 206128 kb
Host smart-342ffa92-a70b-482e-bb11-e96bacfdee97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42226
37620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.4222637620
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.3805848411
Short name T741
Test name
Test status
Simulation time 37785132 ps
CPU time 0.63 seconds
Started Jun 28 06:13:53 PM PDT 24
Finished Jun 28 06:13:56 PM PDT 24
Peak memory 206164 kb
Host smart-3d4a4f09-19c0-4c7c-9f25-bec0dc89ebcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38058
48411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.3805848411
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.1049141727
Short name T564
Test name
Test status
Simulation time 792494506 ps
CPU time 1.98 seconds
Started Jun 28 06:13:57 PM PDT 24
Finished Jun 28 06:14:03 PM PDT 24
Peak memory 206328 kb
Host smart-160e5ac5-df94-4002-9db0-e05cf860e67d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10491
41727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.1049141727
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.353665962
Short name T2436
Test name
Test status
Simulation time 302222326 ps
CPU time 2.1 seconds
Started Jun 28 06:13:57 PM PDT 24
Finished Jun 28 06:14:03 PM PDT 24
Peak memory 206364 kb
Host smart-50dd6d5d-ee33-492b-a311-8fad8de3174a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35366
5962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.353665962
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.809522880
Short name T613
Test name
Test status
Simulation time 210626473 ps
CPU time 0.87 seconds
Started Jun 28 06:14:05 PM PDT 24
Finished Jun 28 06:14:11 PM PDT 24
Peak memory 206212 kb
Host smart-cb458b57-9476-4a28-8341-a690801b7ed1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80952
2880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.809522880
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.2648986192
Short name T2534
Test name
Test status
Simulation time 139008899 ps
CPU time 0.84 seconds
Started Jun 28 06:13:57 PM PDT 24
Finished Jun 28 06:14:01 PM PDT 24
Peak memory 206188 kb
Host smart-0d358a2c-7d5e-4acb-b12b-78ab7d0e0ad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26489
86192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.2648986192
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.523442748
Short name T457
Test name
Test status
Simulation time 189810244 ps
CPU time 0.86 seconds
Started Jun 28 06:13:58 PM PDT 24
Finished Jun 28 06:14:03 PM PDT 24
Peak memory 206212 kb
Host smart-07dc115a-3694-4e15-b9d2-69c84f1c7566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52344
2748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.523442748
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_invalid_sync.2075252499
Short name T545
Test name
Test status
Simulation time 9524215007 ps
CPU time 251.49 seconds
Started Jun 28 06:13:56 PM PDT 24
Finished Jun 28 06:18:11 PM PDT 24
Peak memory 206436 kb
Host smart-a0d1b810-8fd3-49e9-8e60-c96b6447b595
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2075252499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.2075252499
Directory /workspace/36.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.2883784915
Short name T675
Test name
Test status
Simulation time 191441694 ps
CPU time 0.81 seconds
Started Jun 28 06:13:51 PM PDT 24
Finished Jun 28 06:13:54 PM PDT 24
Peak memory 206128 kb
Host smart-382f8602-2353-4536-998f-532d4161e9b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28837
84915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.2883784915
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.970970709
Short name T2256
Test name
Test status
Simulation time 23374868211 ps
CPU time 23.09 seconds
Started Jun 28 06:14:00 PM PDT 24
Finished Jun 28 06:14:27 PM PDT 24
Peak memory 206312 kb
Host smart-54508e44-edcb-4b47-84d3-8fb7f49f579b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97097
0709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.970970709
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.1825187555
Short name T2294
Test name
Test status
Simulation time 3290107535 ps
CPU time 3.78 seconds
Started Jun 28 06:13:57 PM PDT 24
Finished Jun 28 06:14:04 PM PDT 24
Peak memory 206256 kb
Host smart-429b80a7-cba1-430a-b8dd-d96573440bf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18251
87555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.1825187555
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.2881492207
Short name T421
Test name
Test status
Simulation time 9376370135 ps
CPU time 91.07 seconds
Started Jun 28 06:13:52 PM PDT 24
Finished Jun 28 06:15:25 PM PDT 24
Peak memory 206480 kb
Host smart-84dff8f1-f844-4b5f-8f07-57d2274f2e7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28814
92207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.2881492207
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.3824553706
Short name T1703
Test name
Test status
Simulation time 5138660517 ps
CPU time 35.38 seconds
Started Jun 28 06:13:57 PM PDT 24
Finished Jun 28 06:14:36 PM PDT 24
Peak memory 206432 kb
Host smart-a27a8aae-4ee6-435b-affd-3a1b23171489
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3824553706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.3824553706
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.80043111
Short name T1048
Test name
Test status
Simulation time 251344997 ps
CPU time 0.95 seconds
Started Jun 28 06:13:53 PM PDT 24
Finished Jun 28 06:13:57 PM PDT 24
Peak memory 206212 kb
Host smart-c35fa916-d135-4189-9401-3896adc13539
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=80043111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.80043111
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.628248732
Short name T1117
Test name
Test status
Simulation time 194321703 ps
CPU time 0.88 seconds
Started Jun 28 06:13:58 PM PDT 24
Finished Jun 28 06:14:03 PM PDT 24
Peak memory 206212 kb
Host smart-a25faf98-c212-44ee-bb0e-b64aa6d6814a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62824
8732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.628248732
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.436910924
Short name T1896
Test name
Test status
Simulation time 6516434069 ps
CPU time 47.68 seconds
Started Jun 28 06:14:00 PM PDT 24
Finished Jun 28 06:14:51 PM PDT 24
Peak memory 206416 kb
Host smart-9bcd4985-07b4-443b-8093-cc3fea00d384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43691
0924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.436910924
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.1187923835
Short name T2022
Test name
Test status
Simulation time 5329604765 ps
CPU time 36.48 seconds
Started Jun 28 06:13:57 PM PDT 24
Finished Jun 28 06:14:37 PM PDT 24
Peak memory 206496 kb
Host smart-0690ea04-8b55-4f62-a39c-d972c04da4a2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1187923835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.1187923835
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.3433136137
Short name T467
Test name
Test status
Simulation time 158909993 ps
CPU time 0.86 seconds
Started Jun 28 06:13:57 PM PDT 24
Finished Jun 28 06:14:03 PM PDT 24
Peak memory 206212 kb
Host smart-baa526fe-6c35-4f36-8c2e-81d61dce0096
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3433136137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.3433136137
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.1541793793
Short name T1276
Test name
Test status
Simulation time 146769790 ps
CPU time 0.81 seconds
Started Jun 28 06:13:57 PM PDT 24
Finished Jun 28 06:14:02 PM PDT 24
Peak memory 206204 kb
Host smart-0c883c14-595e-4613-8691-cb53bf720356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15417
93793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.1541793793
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.1621083876
Short name T2212
Test name
Test status
Simulation time 240810469 ps
CPU time 0.94 seconds
Started Jun 28 06:13:54 PM PDT 24
Finished Jun 28 06:13:57 PM PDT 24
Peak memory 206196 kb
Host smart-12eaba19-75a2-4692-9119-eb8adfc1a7b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16210
83876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.1621083876
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.322587303
Short name T2457
Test name
Test status
Simulation time 166747480 ps
CPU time 0.86 seconds
Started Jun 28 06:13:59 PM PDT 24
Finished Jun 28 06:14:04 PM PDT 24
Peak memory 206192 kb
Host smart-34ee7b04-1466-4cb7-a33a-14660211bf0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32258
7303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.322587303
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.2182510390
Short name T2596
Test name
Test status
Simulation time 170158187 ps
CPU time 0.84 seconds
Started Jun 28 06:13:57 PM PDT 24
Finished Jun 28 06:14:01 PM PDT 24
Peak memory 206196 kb
Host smart-203ee106-3cb7-4ba2-aaa8-aa359757fdda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21825
10390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.2182510390
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.3776744718
Short name T1312
Test name
Test status
Simulation time 196767675 ps
CPU time 0.84 seconds
Started Jun 28 06:13:55 PM PDT 24
Finished Jun 28 06:13:59 PM PDT 24
Peak memory 206200 kb
Host smart-77a0a5dd-86ac-4e81-a0ac-5644740e70c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37767
44718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.3776744718
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.1618943269
Short name T1530
Test name
Test status
Simulation time 160490815 ps
CPU time 0.76 seconds
Started Jun 28 06:14:00 PM PDT 24
Finished Jun 28 06:14:05 PM PDT 24
Peak memory 205664 kb
Host smart-5f5a39a4-0f68-43b1-8eee-561230202025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16189
43269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.1618943269
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.1897259136
Short name T149
Test name
Test status
Simulation time 245224693 ps
CPU time 1.02 seconds
Started Jun 28 06:13:55 PM PDT 24
Finished Jun 28 06:13:59 PM PDT 24
Peak memory 206204 kb
Host smart-fffa5bc0-1a69-482f-af78-b19e5bfb49b8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1897259136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.1897259136
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.2424147203
Short name T1440
Test name
Test status
Simulation time 156960994 ps
CPU time 0.77 seconds
Started Jun 28 06:13:57 PM PDT 24
Finished Jun 28 06:14:02 PM PDT 24
Peak memory 206172 kb
Host smart-257c7075-6c8c-4408-be63-2f63eeb831df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24241
47203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.2424147203
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.691953170
Short name T959
Test name
Test status
Simulation time 42111360 ps
CPU time 0.71 seconds
Started Jun 28 06:14:06 PM PDT 24
Finished Jun 28 06:14:12 PM PDT 24
Peak memory 206208 kb
Host smart-8ae7ded8-16d8-43ab-a839-9b5e2d1d02f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69195
3170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.691953170
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.688857365
Short name T2618
Test name
Test status
Simulation time 7693692323 ps
CPU time 16 seconds
Started Jun 28 06:13:55 PM PDT 24
Finished Jun 28 06:14:14 PM PDT 24
Peak memory 206408 kb
Host smart-75c30918-a4a2-436b-8500-3dd6e26df6fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68885
7365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.688857365
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.577351746
Short name T303
Test name
Test status
Simulation time 163105798 ps
CPU time 0.88 seconds
Started Jun 28 06:14:01 PM PDT 24
Finished Jun 28 06:14:06 PM PDT 24
Peak memory 206144 kb
Host smart-d9017b9b-58cd-47c3-b680-ad47e0b4c4b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57735
1746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.577351746
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.3415862024
Short name T929
Test name
Test status
Simulation time 189419400 ps
CPU time 0.92 seconds
Started Jun 28 06:14:00 PM PDT 24
Finished Jun 28 06:14:05 PM PDT 24
Peak memory 205788 kb
Host smart-a65d49d5-7b0d-427e-b6db-40f9eab8df65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34158
62024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.3415862024
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.2334460044
Short name T2551
Test name
Test status
Simulation time 192033321 ps
CPU time 0.87 seconds
Started Jun 28 06:13:55 PM PDT 24
Finished Jun 28 06:13:59 PM PDT 24
Peak memory 206196 kb
Host smart-b927f2e5-cc80-426d-b64f-1bfd8f1653b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23344
60044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.2334460044
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.2263584009
Short name T2132
Test name
Test status
Simulation time 154756361 ps
CPU time 0.88 seconds
Started Jun 28 06:14:01 PM PDT 24
Finished Jun 28 06:14:06 PM PDT 24
Peak memory 206136 kb
Host smart-7fda23ad-81ab-4bff-a774-9f4445290fbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22635
84009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.2263584009
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.74962580
Short name T2045
Test name
Test status
Simulation time 193097396 ps
CPU time 0.85 seconds
Started Jun 28 06:13:58 PM PDT 24
Finished Jun 28 06:14:03 PM PDT 24
Peak memory 206188 kb
Host smart-819917e2-b1bb-4e63-b45a-3504897d2426
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74962
580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.74962580
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.252895137
Short name T1621
Test name
Test status
Simulation time 151406730 ps
CPU time 0.77 seconds
Started Jun 28 06:14:01 PM PDT 24
Finished Jun 28 06:14:06 PM PDT 24
Peak memory 206160 kb
Host smart-ddac9122-2e94-4630-8056-bee0bc360f71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25289
5137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.252895137
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.16400733
Short name T1821
Test name
Test status
Simulation time 164416959 ps
CPU time 0.8 seconds
Started Jun 28 06:14:04 PM PDT 24
Finished Jun 28 06:14:09 PM PDT 24
Peak memory 206152 kb
Host smart-03478f16-5857-4fc7-9d44-fefd8ed41d16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16400
733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.16400733
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.1141487779
Short name T1327
Test name
Test status
Simulation time 233825510 ps
CPU time 0.97 seconds
Started Jun 28 06:14:00 PM PDT 24
Finished Jun 28 06:14:05 PM PDT 24
Peak memory 206208 kb
Host smart-0762d346-b02d-402d-bf80-9d86c902a6b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11414
87779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.1141487779
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.2911741478
Short name T1443
Test name
Test status
Simulation time 4799223809 ps
CPU time 134.88 seconds
Started Jun 28 06:14:01 PM PDT 24
Finished Jun 28 06:16:20 PM PDT 24
Peak memory 206472 kb
Host smart-2adca2f6-c61e-455d-81a1-fc8ee8579265
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2911741478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.2911741478
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.1169898851
Short name T746
Test name
Test status
Simulation time 190744300 ps
CPU time 0.83 seconds
Started Jun 28 06:14:10 PM PDT 24
Finished Jun 28 06:14:17 PM PDT 24
Peak memory 206216 kb
Host smart-01e86f24-0afa-46ff-836c-efb1e3bd8678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11698
98851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.1169898851
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.601653808
Short name T1727
Test name
Test status
Simulation time 155181121 ps
CPU time 0.81 seconds
Started Jun 28 06:14:00 PM PDT 24
Finished Jun 28 06:14:05 PM PDT 24
Peak memory 206180 kb
Host smart-3e0d6f5a-31e3-4b76-a7e6-150c525eef9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60165
3808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.601653808
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.932605110
Short name T1924
Test name
Test status
Simulation time 6741274142 ps
CPU time 180.46 seconds
Started Jun 28 06:14:07 PM PDT 24
Finished Jun 28 06:17:13 PM PDT 24
Peak memory 205608 kb
Host smart-440a22cd-afbe-48b9-bd93-8ad448e9a6d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93260
5110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.932605110
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.3405518202
Short name T2248
Test name
Test status
Simulation time 102833707 ps
CPU time 0.78 seconds
Started Jun 28 06:14:10 PM PDT 24
Finished Jun 28 06:14:17 PM PDT 24
Peak memory 206212 kb
Host smart-40f5a0ba-053f-46e1-9941-dd725aeb2a20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3405518202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.3405518202
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.3382150930
Short name T1716
Test name
Test status
Simulation time 4214350751 ps
CPU time 4.78 seconds
Started Jun 28 06:14:06 PM PDT 24
Finished Jun 28 06:14:16 PM PDT 24
Peak memory 206480 kb
Host smart-78738a70-2ba4-4631-bde4-016648c6cf3f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3382150930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.3382150930
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.1099683822
Short name T9
Test name
Test status
Simulation time 13357611425 ps
CPU time 15.98 seconds
Started Jun 28 06:14:05 PM PDT 24
Finished Jun 28 06:14:26 PM PDT 24
Peak memory 206296 kb
Host smart-350a25de-d2db-44ad-8cda-dc3eb1109d7a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1099683822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.1099683822
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.710471434
Short name T1611
Test name
Test status
Simulation time 23376745133 ps
CPU time 25.19 seconds
Started Jun 28 06:14:07 PM PDT 24
Finished Jun 28 06:14:38 PM PDT 24
Peak memory 206400 kb
Host smart-d4818a2f-1c79-4fa7-8b41-1003b9aaffa6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=710471434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.710471434
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.3868991079
Short name T860
Test name
Test status
Simulation time 231238081 ps
CPU time 0.94 seconds
Started Jun 28 06:14:04 PM PDT 24
Finished Jun 28 06:14:09 PM PDT 24
Peak memory 206148 kb
Host smart-baa11a3e-bb62-4690-8a3f-82f8ab4f7c8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38689
91079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.3868991079
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.3227805456
Short name T1346
Test name
Test status
Simulation time 231646340 ps
CPU time 0.84 seconds
Started Jun 28 06:14:07 PM PDT 24
Finished Jun 28 06:14:12 PM PDT 24
Peak memory 206152 kb
Host smart-903336d5-09ec-4e29-85cd-3ac3a3125413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32278
05456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.3227805456
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.1132258535
Short name T1558
Test name
Test status
Simulation time 352126547 ps
CPU time 1.2 seconds
Started Jun 28 06:14:05 PM PDT 24
Finished Jun 28 06:14:11 PM PDT 24
Peak memory 206152 kb
Host smart-b9952ba6-a66c-4c3e-967d-e54485147aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11322
58535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.1132258535
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.3885400446
Short name T2131
Test name
Test status
Simulation time 1104436943 ps
CPU time 2.67 seconds
Started Jun 28 06:14:01 PM PDT 24
Finished Jun 28 06:14:07 PM PDT 24
Peak memory 206296 kb
Host smart-a35b5144-dee8-4448-bed9-944f1e0984f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38854
00446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.3885400446
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.1503983188
Short name T761
Test name
Test status
Simulation time 8389387205 ps
CPU time 16.46 seconds
Started Jun 28 06:14:06 PM PDT 24
Finished Jun 28 06:14:28 PM PDT 24
Peak memory 206496 kb
Host smart-a60adff2-5720-40fd-9105-a8e24da40b53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15039
83188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.1503983188
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.2836603738
Short name T1873
Test name
Test status
Simulation time 401127939 ps
CPU time 1.23 seconds
Started Jun 28 06:14:06 PM PDT 24
Finished Jun 28 06:14:12 PM PDT 24
Peak memory 206164 kb
Host smart-f49e3718-e88f-477d-8f8d-55de5de085cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28366
03738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.2836603738
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.1436505276
Short name T998
Test name
Test status
Simulation time 141615706 ps
CPU time 0.73 seconds
Started Jun 28 06:14:09 PM PDT 24
Finished Jun 28 06:14:16 PM PDT 24
Peak memory 206192 kb
Host smart-19feeeb5-6da9-4019-b455-c0ff11221ff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14365
05276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.1436505276
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.2804212419
Short name T771
Test name
Test status
Simulation time 66670905 ps
CPU time 0.68 seconds
Started Jun 28 06:14:05 PM PDT 24
Finished Jun 28 06:14:10 PM PDT 24
Peak memory 206140 kb
Host smart-ac23112e-5370-472f-bfb1-2c9e93a6f939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28042
12419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.2804212419
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.4278450946
Short name T2580
Test name
Test status
Simulation time 885533019 ps
CPU time 2.14 seconds
Started Jun 28 06:14:04 PM PDT 24
Finished Jun 28 06:14:10 PM PDT 24
Peak memory 205060 kb
Host smart-9364e8fd-b449-4afc-a466-b61f1cef67f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42784
50946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.4278450946
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.3245448672
Short name T431
Test name
Test status
Simulation time 355686672 ps
CPU time 2.21 seconds
Started Jun 28 06:14:05 PM PDT 24
Finished Jun 28 06:14:12 PM PDT 24
Peak memory 206288 kb
Host smart-a0e4dbaa-48eb-4327-80c1-7c9ed02ccdfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32454
48672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.3245448672
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.615796728
Short name T1277
Test name
Test status
Simulation time 177400664 ps
CPU time 0.86 seconds
Started Jun 28 06:14:06 PM PDT 24
Finished Jun 28 06:14:12 PM PDT 24
Peak memory 206324 kb
Host smart-064695ad-1698-446f-a948-eb9abe0c7667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61579
6728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.615796728
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.4242129895
Short name T1081
Test name
Test status
Simulation time 138149187 ps
CPU time 0.79 seconds
Started Jun 28 06:14:08 PM PDT 24
Finished Jun 28 06:14:14 PM PDT 24
Peak memory 206188 kb
Host smart-8e65b9f1-099a-4fae-8601-1e417a8fe090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42421
29895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.4242129895
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.385301311
Short name T754
Test name
Test status
Simulation time 181798653 ps
CPU time 0.87 seconds
Started Jun 28 06:14:10 PM PDT 24
Finished Jun 28 06:14:17 PM PDT 24
Peak memory 206208 kb
Host smart-5bf8b9ca-22b1-490f-b8c8-a4c1e624c3b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38530
1311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.385301311
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.1786365121
Short name T224
Test name
Test status
Simulation time 5829760412 ps
CPU time 53.86 seconds
Started Jun 28 06:14:04 PM PDT 24
Finished Jun 28 06:15:02 PM PDT 24
Peak memory 205180 kb
Host smart-36eed9f2-9158-4552-8848-c5c78afafe25
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1786365121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.1786365121
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.3092063033
Short name T2073
Test name
Test status
Simulation time 211132083 ps
CPU time 0.91 seconds
Started Jun 28 06:14:08 PM PDT 24
Finished Jun 28 06:14:14 PM PDT 24
Peak memory 206188 kb
Host smart-61cfcdc3-cf65-4c32-adc9-69eb853fc7c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30920
63033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.3092063033
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.3659423803
Short name T814
Test name
Test status
Simulation time 23321030168 ps
CPU time 25.05 seconds
Started Jun 28 06:14:05 PM PDT 24
Finished Jun 28 06:14:35 PM PDT 24
Peak memory 206312 kb
Host smart-b9710bf6-5d2b-47e6-9425-e8dfdcf74f3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36594
23803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.3659423803
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.757033540
Short name T1735
Test name
Test status
Simulation time 3303699504 ps
CPU time 3.96 seconds
Started Jun 28 06:14:01 PM PDT 24
Finished Jun 28 06:14:09 PM PDT 24
Peak memory 206228 kb
Host smart-77f8349f-d2bc-4247-9353-f077bead803a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75703
3540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.757033540
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.1015533144
Short name T505
Test name
Test status
Simulation time 12918224198 ps
CPU time 121.21 seconds
Started Jun 28 06:14:09 PM PDT 24
Finished Jun 28 06:16:16 PM PDT 24
Peak memory 206468 kb
Host smart-1638f0fe-6af5-499b-a114-08da5ed4a131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10155
33144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.1015533144
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.597460441
Short name T2444
Test name
Test status
Simulation time 5123058498 ps
CPU time 44.49 seconds
Started Jun 28 06:14:09 PM PDT 24
Finished Jun 28 06:14:59 PM PDT 24
Peak memory 206496 kb
Host smart-904f1cb2-6318-4aef-9527-73a98bb14dc5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=597460441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.597460441
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.1785242446
Short name T2482
Test name
Test status
Simulation time 268732093 ps
CPU time 0.9 seconds
Started Jun 28 06:14:07 PM PDT 24
Finished Jun 28 06:14:13 PM PDT 24
Peak memory 206220 kb
Host smart-3df73486-2539-4019-b600-74c524d89708
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1785242446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.1785242446
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.2294638491
Short name T1281
Test name
Test status
Simulation time 224680005 ps
CPU time 0.92 seconds
Started Jun 28 06:14:05 PM PDT 24
Finished Jun 28 06:14:11 PM PDT 24
Peak memory 206204 kb
Host smart-7558791b-523c-4670-a001-095b3dab0a71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22946
38491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.2294638491
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.2839502630
Short name T727
Test name
Test status
Simulation time 5273790717 ps
CPU time 48.84 seconds
Started Jun 28 06:14:01 PM PDT 24
Finished Jun 28 06:14:54 PM PDT 24
Peak memory 206404 kb
Host smart-37932d05-8a2b-424e-a3d4-d274c96be1e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28395
02630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.2839502630
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.1496589952
Short name T492
Test name
Test status
Simulation time 4736199566 ps
CPU time 121.92 seconds
Started Jun 28 06:14:04 PM PDT 24
Finished Jun 28 06:16:10 PM PDT 24
Peak memory 206424 kb
Host smart-3a511ec8-ca32-4dbc-8ba0-f78463eb25dc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1496589952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.1496589952
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.4234102399
Short name T943
Test name
Test status
Simulation time 149904370 ps
CPU time 0.82 seconds
Started Jun 28 06:14:05 PM PDT 24
Finished Jun 28 06:14:11 PM PDT 24
Peak memory 206220 kb
Host smart-b9725efb-e167-43a0-8216-3e66f2aaaa05
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4234102399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.4234102399
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.3436110122
Short name T1551
Test name
Test status
Simulation time 192504851 ps
CPU time 0.82 seconds
Started Jun 28 06:14:07 PM PDT 24
Finished Jun 28 06:14:12 PM PDT 24
Peak memory 206200 kb
Host smart-c2cd520e-f3ab-4150-8009-d53895b6a949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34361
10122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.3436110122
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.3440274941
Short name T134
Test name
Test status
Simulation time 209456953 ps
CPU time 0.88 seconds
Started Jun 28 06:14:07 PM PDT 24
Finished Jun 28 06:14:14 PM PDT 24
Peak memory 205468 kb
Host smart-c3ced3e4-b5ab-4e61-8dbe-b6b3f2b69504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34402
74941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.3440274941
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.3187612253
Short name T88
Test name
Test status
Simulation time 176700809 ps
CPU time 0.82 seconds
Started Jun 28 06:14:05 PM PDT 24
Finished Jun 28 06:14:11 PM PDT 24
Peak memory 206192 kb
Host smart-d626cb89-a146-4d3d-aa04-b723430297fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31876
12253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.3187612253
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.1361809740
Short name T2432
Test name
Test status
Simulation time 188179206 ps
CPU time 0.83 seconds
Started Jun 28 06:14:00 PM PDT 24
Finished Jun 28 06:14:05 PM PDT 24
Peak memory 206200 kb
Host smart-65f6701e-b8fe-4b48-8591-a126a6540e19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13618
09740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.1361809740
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.745794243
Short name T2018
Test name
Test status
Simulation time 226649499 ps
CPU time 0.84 seconds
Started Jun 28 06:14:02 PM PDT 24
Finished Jun 28 06:14:07 PM PDT 24
Peak memory 206180 kb
Host smart-d33045af-3e08-4082-9a33-36dc557d62db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74579
4243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.745794243
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.2345231729
Short name T169
Test name
Test status
Simulation time 160976306 ps
CPU time 0.84 seconds
Started Jun 28 06:14:05 PM PDT 24
Finished Jun 28 06:14:11 PM PDT 24
Peak memory 206204 kb
Host smart-8137cb0c-170b-4631-b25d-5c7269138c9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23452
31729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.2345231729
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.1406374112
Short name T1455
Test name
Test status
Simulation time 218164929 ps
CPU time 0.9 seconds
Started Jun 28 06:14:03 PM PDT 24
Finished Jun 28 06:14:07 PM PDT 24
Peak memory 206152 kb
Host smart-c04db7ea-8497-46f8-b52d-5ef2890e9259
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1406374112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.1406374112
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.3397253352
Short name T2133
Test name
Test status
Simulation time 212662724 ps
CPU time 0.82 seconds
Started Jun 28 06:14:00 PM PDT 24
Finished Jun 28 06:14:05 PM PDT 24
Peak memory 206204 kb
Host smart-42535475-d1fa-46fa-8b9a-8cce0390c8c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33972
53352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.3397253352
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.1498484902
Short name T504
Test name
Test status
Simulation time 35956244 ps
CPU time 0.64 seconds
Started Jun 28 06:14:05 PM PDT 24
Finished Jun 28 06:14:10 PM PDT 24
Peak memory 206208 kb
Host smart-90dcb665-0313-4b09-ae7a-e3f7a1abdc6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14984
84902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.1498484902
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.211449309
Short name T284
Test name
Test status
Simulation time 12910480453 ps
CPU time 31.49 seconds
Started Jun 28 06:14:05 PM PDT 24
Finished Jun 28 06:14:42 PM PDT 24
Peak memory 206632 kb
Host smart-8cc61e97-779b-4717-ba86-4a725e603477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21144
9309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.211449309
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.496909587
Short name T945
Test name
Test status
Simulation time 186853406 ps
CPU time 0.92 seconds
Started Jun 28 06:14:06 PM PDT 24
Finished Jun 28 06:14:12 PM PDT 24
Peak memory 206324 kb
Host smart-8af6a2ef-1ab0-46d3-b62d-843f6d32baaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49690
9587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.496909587
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.584589991
Short name T1101
Test name
Test status
Simulation time 237394383 ps
CPU time 0.88 seconds
Started Jun 28 06:14:04 PM PDT 24
Finished Jun 28 06:14:09 PM PDT 24
Peak memory 206344 kb
Host smart-14bb3555-401f-43f3-98a5-4d2224a3ded1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58458
9991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.584589991
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.1881145087
Short name T985
Test name
Test status
Simulation time 208463766 ps
CPU time 0.98 seconds
Started Jun 28 06:14:06 PM PDT 24
Finished Jun 28 06:14:12 PM PDT 24
Peak memory 206224 kb
Host smart-c35b9999-7844-4f42-857d-b3b78699247d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18811
45087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.1881145087
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.4203075528
Short name T368
Test name
Test status
Simulation time 181054527 ps
CPU time 0.84 seconds
Started Jun 28 06:14:05 PM PDT 24
Finished Jun 28 06:14:11 PM PDT 24
Peak memory 206200 kb
Host smart-200de178-ea6d-45be-aa0c-3c947f7cb677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42030
75528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.4203075528
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.3688591566
Short name T1947
Test name
Test status
Simulation time 185472217 ps
CPU time 0.78 seconds
Started Jun 28 06:14:14 PM PDT 24
Finished Jun 28 06:14:21 PM PDT 24
Peak memory 206152 kb
Host smart-3ccb9b8d-c153-4b41-8907-6920330eb000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36885
91566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.3688591566
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.1341637776
Short name T2601
Test name
Test status
Simulation time 147022376 ps
CPU time 0.78 seconds
Started Jun 28 06:14:08 PM PDT 24
Finished Jun 28 06:14:14 PM PDT 24
Peak memory 206188 kb
Host smart-793d4b44-7730-4a19-9145-d6bb9deba336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13416
37776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.1341637776
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.956765065
Short name T1880
Test name
Test status
Simulation time 156418189 ps
CPU time 0.77 seconds
Started Jun 28 06:14:14 PM PDT 24
Finished Jun 28 06:14:21 PM PDT 24
Peak memory 206156 kb
Host smart-dfdf2707-79e8-4c21-944c-efe97db280c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95676
5065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.956765065
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.3327600630
Short name T876
Test name
Test status
Simulation time 230800649 ps
CPU time 0.98 seconds
Started Jun 28 06:14:06 PM PDT 24
Finished Jun 28 06:14:12 PM PDT 24
Peak memory 206212 kb
Host smart-9f8c390b-097d-4719-981f-dc4c37b4e498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33276
00630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.3327600630
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.3483774345
Short name T1006
Test name
Test status
Simulation time 5610988697 ps
CPU time 160.96 seconds
Started Jun 28 06:14:04 PM PDT 24
Finished Jun 28 06:16:49 PM PDT 24
Peak memory 206612 kb
Host smart-980b6167-83bc-477e-9cf5-352e2f084096
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3483774345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.3483774345
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.2352629265
Short name T2536
Test name
Test status
Simulation time 171599913 ps
CPU time 0.81 seconds
Started Jun 28 06:14:10 PM PDT 24
Finished Jun 28 06:14:17 PM PDT 24
Peak memory 206196 kb
Host smart-8d14b890-7b5e-4fc7-a855-a8f4d8d480fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23526
29265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.2352629265
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.1743366879
Short name T1874
Test name
Test status
Simulation time 179760414 ps
CPU time 0.81 seconds
Started Jun 28 06:14:05 PM PDT 24
Finished Jun 28 06:14:10 PM PDT 24
Peak memory 206196 kb
Host smart-c349b331-cdce-464b-948f-68db42671e2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17433
66879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.1743366879
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.3807347635
Short name T1318
Test name
Test status
Simulation time 4472182921 ps
CPU time 29.94 seconds
Started Jun 28 06:14:04 PM PDT 24
Finished Jun 28 06:14:39 PM PDT 24
Peak memory 206452 kb
Host smart-b9c14327-e5e6-4164-9223-6e097350b413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38073
47635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.3807347635
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.928556825
Short name T514
Test name
Test status
Simulation time 79227289 ps
CPU time 0.75 seconds
Started Jun 28 06:14:13 PM PDT 24
Finished Jun 28 06:14:20 PM PDT 24
Peak memory 206212 kb
Host smart-6d8d8bc4-240c-4343-8975-bbd599ac18ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=928556825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.928556825
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.2849396759
Short name T1656
Test name
Test status
Simulation time 4152219237 ps
CPU time 5.03 seconds
Started Jun 28 06:14:10 PM PDT 24
Finished Jun 28 06:14:22 PM PDT 24
Peak memory 206276 kb
Host smart-858805f6-3e42-4723-9414-641820fcbd7d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2849396759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.2849396759
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.1408979607
Short name T13
Test name
Test status
Simulation time 13337229114 ps
CPU time 11.82 seconds
Started Jun 28 06:14:05 PM PDT 24
Finished Jun 28 06:14:22 PM PDT 24
Peak memory 206396 kb
Host smart-0781d1e6-52bb-4f7e-8855-a18f348e9435
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1408979607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.1408979607
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.438955553
Short name T2064
Test name
Test status
Simulation time 23337171541 ps
CPU time 23 seconds
Started Jun 28 06:14:05 PM PDT 24
Finished Jun 28 06:14:33 PM PDT 24
Peak memory 206316 kb
Host smart-5c090a2c-7139-46a7-ae49-69c210dd4e09
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=438955553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.438955553
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.2248721457
Short name T1493
Test name
Test status
Simulation time 176544366 ps
CPU time 0.85 seconds
Started Jun 28 06:14:07 PM PDT 24
Finished Jun 28 06:14:13 PM PDT 24
Peak memory 206192 kb
Host smart-870e47b7-7ecd-41ce-9165-5eaefb96d65b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22487
21457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.2248721457
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.1669777357
Short name T731
Test name
Test status
Simulation time 220466003 ps
CPU time 0.9 seconds
Started Jun 28 06:14:04 PM PDT 24
Finished Jun 28 06:14:09 PM PDT 24
Peak memory 206128 kb
Host smart-9c8a7a1d-d85b-4030-ac8c-447adf9119e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16697
77357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.1669777357
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.3201088678
Short name T1630
Test name
Test status
Simulation time 543746611 ps
CPU time 1.56 seconds
Started Jun 28 06:14:05 PM PDT 24
Finished Jun 28 06:14:11 PM PDT 24
Peak memory 206268 kb
Host smart-8df4dd29-78ef-4ed1-a00f-5265a18ecf08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32010
88678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.3201088678
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.513294551
Short name T1761
Test name
Test status
Simulation time 314783152 ps
CPU time 1.02 seconds
Started Jun 28 06:14:13 PM PDT 24
Finished Jun 28 06:14:21 PM PDT 24
Peak memory 206044 kb
Host smart-bec05dee-7b3f-43aa-982f-0f609b729d55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51329
4551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.513294551
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.3105764357
Short name T1444
Test name
Test status
Simulation time 11544570590 ps
CPU time 22.09 seconds
Started Jun 28 06:14:07 PM PDT 24
Finished Jun 28 06:14:34 PM PDT 24
Peak memory 206412 kb
Host smart-be8a497e-8d14-4bed-ad8f-84328edd46cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31057
64357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.3105764357
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.2743304602
Short name T2089
Test name
Test status
Simulation time 338959054 ps
CPU time 1.14 seconds
Started Jun 28 06:14:11 PM PDT 24
Finished Jun 28 06:14:19 PM PDT 24
Peak memory 206168 kb
Host smart-20c8cd76-5b71-4b5f-b538-97f0bc38567d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27433
04602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.2743304602
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.952788440
Short name T2621
Test name
Test status
Simulation time 146281527 ps
CPU time 0.77 seconds
Started Jun 28 06:14:13 PM PDT 24
Finished Jun 28 06:14:20 PM PDT 24
Peak memory 206192 kb
Host smart-44762ba4-0cc3-45a3-94ef-47d753484c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95278
8440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.952788440
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.705619623
Short name T641
Test name
Test status
Simulation time 36857318 ps
CPU time 0.64 seconds
Started Jun 28 06:14:10 PM PDT 24
Finished Jun 28 06:14:16 PM PDT 24
Peak memory 206204 kb
Host smart-2540c51f-2e47-462f-b633-e8fde125779f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70561
9623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.705619623
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.4259853747
Short name T1997
Test name
Test status
Simulation time 809797092 ps
CPU time 1.85 seconds
Started Jun 28 06:14:12 PM PDT 24
Finished Jun 28 06:14:20 PM PDT 24
Peak memory 206336 kb
Host smart-bf418b1a-5d36-4682-8002-22d0b9c58e00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42598
53747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.4259853747
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.563467302
Short name T635
Test name
Test status
Simulation time 185514263 ps
CPU time 2.1 seconds
Started Jun 28 06:14:07 PM PDT 24
Finished Jun 28 06:14:15 PM PDT 24
Peak memory 206288 kb
Host smart-3e1ba90c-d3ca-4a11-99da-2c67dd185669
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56346
7302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.563467302
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.3403886767
Short name T673
Test name
Test status
Simulation time 197567121 ps
CPU time 0.85 seconds
Started Jun 28 06:14:13 PM PDT 24
Finished Jun 28 06:14:20 PM PDT 24
Peak memory 206188 kb
Host smart-4500360c-0095-4fa3-813d-205424fdd80d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34038
86767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.3403886767
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.3199259367
Short name T2434
Test name
Test status
Simulation time 143567533 ps
CPU time 0.78 seconds
Started Jun 28 06:14:05 PM PDT 24
Finished Jun 28 06:14:10 PM PDT 24
Peak memory 206216 kb
Host smart-8dc6e2eb-d685-4e34-afa9-03c17f9c865f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31992
59367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.3199259367
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.1723892292
Short name T1323
Test name
Test status
Simulation time 169347127 ps
CPU time 0.88 seconds
Started Jun 28 06:14:08 PM PDT 24
Finished Jun 28 06:14:15 PM PDT 24
Peak memory 206208 kb
Host smart-b1e8b4a0-569e-4b4c-a36d-0a0251d9e7be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17238
92292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.1723892292
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.3932905299
Short name T2590
Test name
Test status
Simulation time 204331659 ps
CPU time 0.86 seconds
Started Jun 28 06:14:03 PM PDT 24
Finished Jun 28 06:14:07 PM PDT 24
Peak memory 206304 kb
Host smart-c695079b-bd04-4372-9982-f72cdb14cfed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39329
05299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.3932905299
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.2481155507
Short name T1864
Test name
Test status
Simulation time 23267163814 ps
CPU time 24.48 seconds
Started Jun 28 06:14:13 PM PDT 24
Finished Jun 28 06:14:43 PM PDT 24
Peak memory 206288 kb
Host smart-cfa1e840-a2e8-4d91-862f-7190f85182dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24811
55507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.2481155507
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.3493403811
Short name T942
Test name
Test status
Simulation time 3269982852 ps
CPU time 3.68 seconds
Started Jun 28 06:14:12 PM PDT 24
Finished Jun 28 06:14:22 PM PDT 24
Peak memory 206256 kb
Host smart-eeba26ab-65fd-4414-8a40-9b878eca352f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34934
03811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.3493403811
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.2333180022
Short name T693
Test name
Test status
Simulation time 9926372212 ps
CPU time 77.09 seconds
Started Jun 28 06:14:14 PM PDT 24
Finished Jun 28 06:15:38 PM PDT 24
Peak memory 206396 kb
Host smart-a43cedba-70d0-42c5-82e7-340e221a054f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23331
80022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.2333180022
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.419934331
Short name T1128
Test name
Test status
Simulation time 5409127386 ps
CPU time 51.51 seconds
Started Jun 28 06:14:25 PM PDT 24
Finished Jun 28 06:15:20 PM PDT 24
Peak memory 206456 kb
Host smart-ce067d2e-5412-4249-ba51-85ef7e7f40de
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=419934331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.419934331
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.3907063733
Short name T973
Test name
Test status
Simulation time 242358988 ps
CPU time 0.86 seconds
Started Jun 28 06:14:33 PM PDT 24
Finished Jun 28 06:14:36 PM PDT 24
Peak memory 206216 kb
Host smart-a91e3ca3-33b2-41fa-9f61-c965fc9ccdaa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3907063733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.3907063733
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.2068845296
Short name T2607
Test name
Test status
Simulation time 207573642 ps
CPU time 0.88 seconds
Started Jun 28 06:14:23 PM PDT 24
Finished Jun 28 06:14:27 PM PDT 24
Peak memory 206204 kb
Host smart-ffca4fd1-4a81-4d1e-9353-d7fa8a995119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20688
45296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.2068845296
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.3589997112
Short name T1910
Test name
Test status
Simulation time 6446829390 ps
CPU time 184.31 seconds
Started Jun 28 06:14:14 PM PDT 24
Finished Jun 28 06:17:25 PM PDT 24
Peak memory 206432 kb
Host smart-704ac345-58f8-4548-92c2-b84583d9f288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35899
97112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.3589997112
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.1015964632
Short name T366
Test name
Test status
Simulation time 4462488735 ps
CPU time 33.31 seconds
Started Jun 28 06:14:11 PM PDT 24
Finished Jun 28 06:14:51 PM PDT 24
Peak memory 206492 kb
Host smart-a4cc387d-641a-4f3a-b744-6263181e7789
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1015964632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.1015964632
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.701872633
Short name T2328
Test name
Test status
Simulation time 160930676 ps
CPU time 0.78 seconds
Started Jun 28 06:14:12 PM PDT 24
Finished Jun 28 06:14:19 PM PDT 24
Peak memory 206220 kb
Host smart-07f9f04b-2fb8-4933-ad77-3625acbb0110
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=701872633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.701872633
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.787332963
Short name T2340
Test name
Test status
Simulation time 166163190 ps
CPU time 0.8 seconds
Started Jun 28 06:14:15 PM PDT 24
Finished Jun 28 06:14:22 PM PDT 24
Peak memory 206212 kb
Host smart-140480b5-dd8f-468b-976c-2eecfaa1d122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78733
2963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.787332963
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.2961052070
Short name T127
Test name
Test status
Simulation time 221052891 ps
CPU time 0.85 seconds
Started Jun 28 06:14:12 PM PDT 24
Finished Jun 28 06:14:20 PM PDT 24
Peak memory 206196 kb
Host smart-861c5982-69a5-4daf-904d-4ebcba620aca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29610
52070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.2961052070
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.1244562480
Short name T1675
Test name
Test status
Simulation time 192838676 ps
CPU time 0.83 seconds
Started Jun 28 06:14:23 PM PDT 24
Finished Jun 28 06:14:27 PM PDT 24
Peak memory 206192 kb
Host smart-66b663d2-4c3b-452f-9451-e1cee031fe63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12445
62480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.1244562480
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.3579167490
Short name T1274
Test name
Test status
Simulation time 187777888 ps
CPU time 0.89 seconds
Started Jun 28 06:14:12 PM PDT 24
Finished Jun 28 06:14:20 PM PDT 24
Peak memory 206192 kb
Host smart-09e216d2-7b96-4df4-978b-e8705930c29f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35791
67490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.3579167490
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.3713507616
Short name T916
Test name
Test status
Simulation time 172140278 ps
CPU time 0.79 seconds
Started Jun 28 06:14:16 PM PDT 24
Finished Jun 28 06:14:23 PM PDT 24
Peak memory 206196 kb
Host smart-a68219f0-4736-4112-9e5b-cbffe4336a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37135
07616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.3713507616
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.3661381883
Short name T1973
Test name
Test status
Simulation time 155337277 ps
CPU time 0.86 seconds
Started Jun 28 06:14:12 PM PDT 24
Finished Jun 28 06:14:20 PM PDT 24
Peak memory 206196 kb
Host smart-18f03c27-bbd4-4d7c-9598-04b94b02719a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36613
81883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.3661381883
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.1445565924
Short name T618
Test name
Test status
Simulation time 210238452 ps
CPU time 0.93 seconds
Started Jun 28 06:14:14 PM PDT 24
Finished Jun 28 06:14:21 PM PDT 24
Peak memory 206208 kb
Host smart-518263da-28f2-4256-ae0c-9770de6ff592
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1445565924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.1445565924
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.77717817
Short name T1256
Test name
Test status
Simulation time 150414831 ps
CPU time 0.79 seconds
Started Jun 28 06:14:13 PM PDT 24
Finished Jun 28 06:14:20 PM PDT 24
Peak memory 206208 kb
Host smart-90899b6d-9617-4919-be6d-c6b66f9683e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77717
817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.77717817
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.1271067992
Short name T2401
Test name
Test status
Simulation time 46794817 ps
CPU time 0.68 seconds
Started Jun 28 06:14:13 PM PDT 24
Finished Jun 28 06:14:20 PM PDT 24
Peak memory 206200 kb
Host smart-0f026dd6-3a17-454d-8a1a-d99d4dc78e3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12710
67992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.1271067992
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.2088286028
Short name T1833
Test name
Test status
Simulation time 10548784771 ps
CPU time 24.11 seconds
Started Jun 28 06:14:12 PM PDT 24
Finished Jun 28 06:14:43 PM PDT 24
Peak memory 206464 kb
Host smart-41d04d23-4d56-4347-9c2d-f122bc885f25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20882
86028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.2088286028
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.1628949029
Short name T2240
Test name
Test status
Simulation time 200653619 ps
CPU time 0.83 seconds
Started Jun 28 06:14:12 PM PDT 24
Finished Jun 28 06:14:19 PM PDT 24
Peak memory 206172 kb
Host smart-491254fe-b46e-4705-b426-3c8b99158c31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16289
49029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.1628949029
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.132069040
Short name T1870
Test name
Test status
Simulation time 240142074 ps
CPU time 0.91 seconds
Started Jun 28 06:14:11 PM PDT 24
Finished Jun 28 06:14:18 PM PDT 24
Peak memory 206200 kb
Host smart-9086fc5f-b7ee-434b-84d6-cf98a80f4689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13206
9040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.132069040
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.2588669070
Short name T640
Test name
Test status
Simulation time 192092990 ps
CPU time 0.77 seconds
Started Jun 28 06:14:25 PM PDT 24
Finished Jun 28 06:14:30 PM PDT 24
Peak memory 206212 kb
Host smart-e8c675e2-e069-488a-8b7d-fdc6b7d25926
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25886
69070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.2588669070
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.1408174226
Short name T1238
Test name
Test status
Simulation time 195596922 ps
CPU time 0.89 seconds
Started Jun 28 06:14:21 PM PDT 24
Finished Jun 28 06:14:26 PM PDT 24
Peak memory 206192 kb
Host smart-d85e6a4a-cf02-41f2-8986-9ba1937ec053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14081
74226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.1408174226
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.2212827198
Short name T594
Test name
Test status
Simulation time 136824727 ps
CPU time 0.74 seconds
Started Jun 28 06:14:12 PM PDT 24
Finished Jun 28 06:14:19 PM PDT 24
Peak memory 206168 kb
Host smart-2f961f7e-15a8-4289-abc2-21bb26b0ee5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22128
27198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.2212827198
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.321042325
Short name T1605
Test name
Test status
Simulation time 160822088 ps
CPU time 0.81 seconds
Started Jun 28 06:14:12 PM PDT 24
Finished Jun 28 06:14:19 PM PDT 24
Peak memory 206192 kb
Host smart-61ecb360-e9cc-4e32-8604-aed0a2733658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32104
2325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.321042325
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.2830441509
Short name T2514
Test name
Test status
Simulation time 171075242 ps
CPU time 0.74 seconds
Started Jun 28 06:14:20 PM PDT 24
Finished Jun 28 06:14:26 PM PDT 24
Peak memory 206192 kb
Host smart-ce46095b-065e-4089-84fd-b47e2c716b70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28304
41509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.2830441509
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.1220456107
Short name T470
Test name
Test status
Simulation time 223166895 ps
CPU time 0.97 seconds
Started Jun 28 06:14:30 PM PDT 24
Finished Jun 28 06:14:34 PM PDT 24
Peak memory 206212 kb
Host smart-64d41b9a-1a8f-4a33-a84d-58ac4a22c922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12204
56107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.1220456107
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.2283795016
Short name T1159
Test name
Test status
Simulation time 5433120161 ps
CPU time 51.71 seconds
Started Jun 28 06:14:25 PM PDT 24
Finished Jun 28 06:15:21 PM PDT 24
Peak memory 206336 kb
Host smart-5741a81a-b527-4acb-ac0d-79b97c70f82f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2283795016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.2283795016
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.166492110
Short name T1984
Test name
Test status
Simulation time 184318180 ps
CPU time 0.83 seconds
Started Jun 28 06:14:25 PM PDT 24
Finished Jun 28 06:14:30 PM PDT 24
Peak memory 206212 kb
Host smart-43b19067-dc6d-4fda-98de-7b697a6abe2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16649
2110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.166492110
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.2553064662
Short name T1396
Test name
Test status
Simulation time 222808887 ps
CPU time 0.86 seconds
Started Jun 28 06:14:11 PM PDT 24
Finished Jun 28 06:14:18 PM PDT 24
Peak memory 206196 kb
Host smart-5ff11fc4-6e6e-46f0-a6a0-9b45e2850bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25530
64662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.2553064662
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.951232036
Short name T1682
Test name
Test status
Simulation time 3176754020 ps
CPU time 29.94 seconds
Started Jun 28 06:14:14 PM PDT 24
Finished Jun 28 06:14:50 PM PDT 24
Peak memory 206440 kb
Host smart-68051bd1-32e8-448b-bd80-2e8d02958c07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95123
2036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.951232036
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.681608310
Short name T1191
Test name
Test status
Simulation time 91371907 ps
CPU time 0.74 seconds
Started Jun 28 06:14:26 PM PDT 24
Finished Jun 28 06:14:31 PM PDT 24
Peak memory 206212 kb
Host smart-bb1b1640-3512-4862-ae02-6655912a2748
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=681608310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.681608310
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.4184089460
Short name T1319
Test name
Test status
Simulation time 4243753163 ps
CPU time 5.32 seconds
Started Jun 28 06:14:24 PM PDT 24
Finished Jun 28 06:14:32 PM PDT 24
Peak memory 206364 kb
Host smart-f0b0e67c-9bea-4fcf-ba25-704d08528f4c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4184089460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.4184089460
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.3788022653
Short name T2111
Test name
Test status
Simulation time 13355523653 ps
CPU time 12.79 seconds
Started Jun 28 06:14:14 PM PDT 24
Finished Jun 28 06:14:33 PM PDT 24
Peak memory 206384 kb
Host smart-65434e6e-59ae-4f82-979b-048479b1d36b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3788022653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.3788022653
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.807750741
Short name T8
Test name
Test status
Simulation time 23391545830 ps
CPU time 22.98 seconds
Started Jun 28 06:14:12 PM PDT 24
Finished Jun 28 06:14:42 PM PDT 24
Peak memory 206484 kb
Host smart-7c34a674-f074-467d-9504-b859cc784339
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=807750741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.807750741
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.3308207579
Short name T523
Test name
Test status
Simulation time 166360557 ps
CPU time 0.79 seconds
Started Jun 28 06:14:12 PM PDT 24
Finished Jun 28 06:14:19 PM PDT 24
Peak memory 206204 kb
Host smart-da54c6ca-38b0-4329-9faa-0a7a09a5ee28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33082
07579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.3308207579
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.681180974
Short name T388
Test name
Test status
Simulation time 167764874 ps
CPU time 0.8 seconds
Started Jun 28 06:14:24 PM PDT 24
Finished Jun 28 06:14:28 PM PDT 24
Peak memory 206192 kb
Host smart-5dfba007-ca65-42c8-8592-24822031cd7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68118
0974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.681180974
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.847008642
Short name T979
Test name
Test status
Simulation time 457113907 ps
CPU time 1.44 seconds
Started Jun 28 06:14:13 PM PDT 24
Finished Jun 28 06:14:21 PM PDT 24
Peak memory 206192 kb
Host smart-a3c64be2-10c0-40b5-ac44-d32785e82b5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84700
8642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.847008642
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.690951364
Short name T174
Test name
Test status
Simulation time 828340409 ps
CPU time 1.99 seconds
Started Jun 28 06:14:12 PM PDT 24
Finished Jun 28 06:14:20 PM PDT 24
Peak memory 206268 kb
Host smart-3a0323a9-547a-474e-9860-77d14cae02b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69095
1364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.690951364
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.2153928234
Short name T1835
Test name
Test status
Simulation time 11748983175 ps
CPU time 23.32 seconds
Started Jun 28 06:14:10 PM PDT 24
Finished Jun 28 06:14:40 PM PDT 24
Peak memory 206332 kb
Host smart-741600fe-d278-41a6-9f7d-983f542eeb2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21539
28234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.2153928234
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.2250887084
Short name T536
Test name
Test status
Simulation time 510261882 ps
CPU time 1.47 seconds
Started Jun 28 06:14:15 PM PDT 24
Finished Jun 28 06:14:24 PM PDT 24
Peak memory 206172 kb
Host smart-aff012a9-06a2-4c3c-b1fd-138af7ab1440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22508
87084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.2250887084
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.3802102629
Short name T756
Test name
Test status
Simulation time 136097527 ps
CPU time 0.72 seconds
Started Jun 28 06:14:24 PM PDT 24
Finished Jun 28 06:14:28 PM PDT 24
Peak memory 206112 kb
Host smart-ce99ad7c-ea40-4194-98c8-6ba550254ab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38021
02629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.3802102629
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.753156705
Short name T1613
Test name
Test status
Simulation time 90582179 ps
CPU time 0.72 seconds
Started Jun 28 06:14:15 PM PDT 24
Finished Jun 28 06:14:22 PM PDT 24
Peak memory 206204 kb
Host smart-0bf91f8e-884c-4330-8248-33cb16bf8611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75315
6705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.753156705
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.2931307467
Short name T1393
Test name
Test status
Simulation time 1057108295 ps
CPU time 2.61 seconds
Started Jun 28 06:14:14 PM PDT 24
Finished Jun 28 06:14:23 PM PDT 24
Peak memory 206228 kb
Host smart-379d17a1-b649-40f1-a9d7-710e1be4b230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29313
07467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.2931307467
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.269476856
Short name T1430
Test name
Test status
Simulation time 163705301 ps
CPU time 1.63 seconds
Started Jun 28 06:14:14 PM PDT 24
Finished Jun 28 06:14:22 PM PDT 24
Peak memory 206220 kb
Host smart-d52dedb7-ea3f-4512-9152-c3352c6b7aa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26947
6856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.269476856
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.2988667009
Short name T1934
Test name
Test status
Simulation time 218919127 ps
CPU time 0.87 seconds
Started Jun 28 06:14:12 PM PDT 24
Finished Jun 28 06:14:19 PM PDT 24
Peak memory 206188 kb
Host smart-786537c3-56d8-4f56-b055-a05906f2fa6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29886
67009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.2988667009
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.210861399
Short name T1154
Test name
Test status
Simulation time 147135947 ps
CPU time 0.75 seconds
Started Jun 28 06:14:17 PM PDT 24
Finished Jun 28 06:14:24 PM PDT 24
Peak memory 206180 kb
Host smart-e427bcc6-98a8-4af6-9b40-145c3b24afbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21086
1399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.210861399
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.2441106392
Short name T1228
Test name
Test status
Simulation time 192466743 ps
CPU time 0.86 seconds
Started Jun 28 06:14:25 PM PDT 24
Finished Jun 28 06:14:30 PM PDT 24
Peak memory 206212 kb
Host smart-084c9367-2ee6-4f89-9707-064bd8c35b37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24411
06392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.2441106392
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.1634695175
Short name T608
Test name
Test status
Simulation time 272780292 ps
CPU time 0.88 seconds
Started Jun 28 06:14:13 PM PDT 24
Finished Jun 28 06:14:20 PM PDT 24
Peak memory 206180 kb
Host smart-d4323fc1-dba5-4dd1-acff-74ba6cceef1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16346
95175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.1634695175
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.2751240287
Short name T2092
Test name
Test status
Simulation time 23307723392 ps
CPU time 22.21 seconds
Started Jun 28 06:14:15 PM PDT 24
Finished Jun 28 06:14:44 PM PDT 24
Peak memory 206308 kb
Host smart-cac82028-dbae-4ac3-8f9d-8603f45e69b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27512
40287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.2751240287
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.572976875
Short name T217
Test name
Test status
Simulation time 3340203484 ps
CPU time 4.58 seconds
Started Jun 28 06:14:22 PM PDT 24
Finished Jun 28 06:14:30 PM PDT 24
Peak memory 206248 kb
Host smart-e58c1089-85aa-44d5-bf55-ba8a7e5ff2c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57297
6875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.572976875
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.1105098641
Short name T2069
Test name
Test status
Simulation time 7949328781 ps
CPU time 76.13 seconds
Started Jun 28 06:14:13 PM PDT 24
Finished Jun 28 06:15:36 PM PDT 24
Peak memory 206460 kb
Host smart-6984e122-aa44-49da-b84d-a32b96deae4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11050
98641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.1105098641
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.1115998428
Short name T2201
Test name
Test status
Simulation time 4718811385 ps
CPU time 33.12 seconds
Started Jun 28 06:14:16 PM PDT 24
Finished Jun 28 06:14:56 PM PDT 24
Peak memory 206400 kb
Host smart-78009435-9517-4020-923f-72cec11b20e6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1115998428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.1115998428
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.413784328
Short name T1770
Test name
Test status
Simulation time 269118906 ps
CPU time 0.95 seconds
Started Jun 28 06:14:12 PM PDT 24
Finished Jun 28 06:14:20 PM PDT 24
Peak memory 206216 kb
Host smart-94824928-dac7-4745-9812-85425c110a82
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=413784328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.413784328
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.1232614801
Short name T400
Test name
Test status
Simulation time 203068767 ps
CPU time 0.91 seconds
Started Jun 28 06:14:16 PM PDT 24
Finished Jun 28 06:14:23 PM PDT 24
Peak memory 206188 kb
Host smart-5f20aea2-d6af-40df-a1eb-c431166e3dd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12326
14801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.1232614801
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.2041320037
Short name T1286
Test name
Test status
Simulation time 4345676578 ps
CPU time 121.31 seconds
Started Jun 28 06:14:18 PM PDT 24
Finished Jun 28 06:16:25 PM PDT 24
Peak memory 206452 kb
Host smart-39e6ae30-2235-4b08-a8cd-e62fb8541bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20413
20037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.2041320037
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.3010394200
Short name T1991
Test name
Test status
Simulation time 4131986454 ps
CPU time 39.66 seconds
Started Jun 28 06:14:12 PM PDT 24
Finished Jun 28 06:14:58 PM PDT 24
Peak memory 206408 kb
Host smart-b2157d94-bd38-4a38-b7a7-3aec09ec5e4e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3010394200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.3010394200
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.2054302623
Short name T2100
Test name
Test status
Simulation time 161654036 ps
CPU time 0.77 seconds
Started Jun 28 06:14:15 PM PDT 24
Finished Jun 28 06:14:23 PM PDT 24
Peak memory 206216 kb
Host smart-d7a457be-bce9-44f6-a8df-0424cfce5fab
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2054302623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.2054302623
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.2642316727
Short name T1972
Test name
Test status
Simulation time 188372202 ps
CPU time 0.81 seconds
Started Jun 28 06:14:21 PM PDT 24
Finished Jun 28 06:14:31 PM PDT 24
Peak memory 206356 kb
Host smart-a27ca898-dc02-4837-a64a-9c8e9d5bfcf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26423
16727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.2642316727
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.1384349803
Short name T2114
Test name
Test status
Simulation time 183488030 ps
CPU time 0.85 seconds
Started Jun 28 06:14:16 PM PDT 24
Finished Jun 28 06:14:23 PM PDT 24
Peak memory 206176 kb
Host smart-d567e3a1-6f5e-444d-ba2e-ce5f4c9ddedb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13843
49803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.1384349803
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.3082506458
Short name T2629
Test name
Test status
Simulation time 183393409 ps
CPU time 0.83 seconds
Started Jun 28 06:14:20 PM PDT 24
Finished Jun 28 06:14:26 PM PDT 24
Peak memory 206152 kb
Host smart-b69bed87-59f5-4c89-8cb5-b2c453880ca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30825
06458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.3082506458
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.78636231
Short name T2424
Test name
Test status
Simulation time 148048209 ps
CPU time 0.77 seconds
Started Jun 28 06:14:14 PM PDT 24
Finished Jun 28 06:14:21 PM PDT 24
Peak memory 206204 kb
Host smart-638dd446-d88c-4150-94ef-6a3e40c02d5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78636
231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.78636231
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.1288777649
Short name T1044
Test name
Test status
Simulation time 150565201 ps
CPU time 0.78 seconds
Started Jun 28 06:14:15 PM PDT 24
Finished Jun 28 06:14:23 PM PDT 24
Peak memory 205932 kb
Host smart-4471de84-6086-4e32-b8b6-514e857682f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12887
77649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.1288777649
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.1859459894
Short name T166
Test name
Test status
Simulation time 162720493 ps
CPU time 0.78 seconds
Started Jun 28 06:14:14 PM PDT 24
Finished Jun 28 06:14:21 PM PDT 24
Peak memory 206180 kb
Host smart-d1124e89-7bd1-4111-96aa-a6c13fb5e0f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18594
59894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.1859459894
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.3791500233
Short name T1479
Test name
Test status
Simulation time 254554409 ps
CPU time 0.97 seconds
Started Jun 28 06:14:15 PM PDT 24
Finished Jun 28 06:14:23 PM PDT 24
Peak memory 206212 kb
Host smart-0df9f349-4173-4f6e-a514-eb643568d699
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3791500233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.3791500233
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.2258129234
Short name T1775
Test name
Test status
Simulation time 149758440 ps
CPU time 0.8 seconds
Started Jun 28 06:14:21 PM PDT 24
Finished Jun 28 06:14:26 PM PDT 24
Peak memory 206180 kb
Host smart-c68071c3-2e0a-41d4-8ed4-cab0b91baf3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22581
29234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.2258129234
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.29074861
Short name T2628
Test name
Test status
Simulation time 44706391 ps
CPU time 0.72 seconds
Started Jun 28 06:14:14 PM PDT 24
Finished Jun 28 06:14:21 PM PDT 24
Peak memory 206208 kb
Host smart-d21c189f-5c30-4d5b-9075-408fad320eb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29074
861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.29074861
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.2082549261
Short name T2119
Test name
Test status
Simulation time 14365278138 ps
CPU time 34.74 seconds
Started Jun 28 06:14:12 PM PDT 24
Finished Jun 28 06:14:53 PM PDT 24
Peak memory 206476 kb
Host smart-75e84389-0523-4ff7-b177-266eab13e106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20825
49261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.2082549261
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.1394145349
Short name T1059
Test name
Test status
Simulation time 180938132 ps
CPU time 0.8 seconds
Started Jun 28 06:14:13 PM PDT 24
Finished Jun 28 06:14:21 PM PDT 24
Peak memory 206188 kb
Host smart-0edb9aef-e50c-4d4d-a568-d1cdc76fa28c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13941
45349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.1394145349
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.622275501
Short name T1819
Test name
Test status
Simulation time 173085230 ps
CPU time 0.81 seconds
Started Jun 28 06:14:14 PM PDT 24
Finished Jun 28 06:14:21 PM PDT 24
Peak memory 206208 kb
Host smart-eabc71aa-e1a1-4ea2-8a62-ed231d2e812f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62227
5501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.622275501
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.1741668689
Short name T1612
Test name
Test status
Simulation time 249526881 ps
CPU time 0.93 seconds
Started Jun 28 06:14:15 PM PDT 24
Finished Jun 28 06:14:23 PM PDT 24
Peak memory 206036 kb
Host smart-2776f5c5-e0b6-4bf9-83ce-b573b680a163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17416
68689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.1741668689
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.3201853868
Short name T934
Test name
Test status
Simulation time 177034829 ps
CPU time 0.87 seconds
Started Jun 28 06:14:15 PM PDT 24
Finished Jun 28 06:14:23 PM PDT 24
Peak memory 206172 kb
Host smart-41d60ef7-bd83-49b7-a588-26724aa84c32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32018
53868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.3201853868
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.2681261907
Short name T2015
Test name
Test status
Simulation time 166964666 ps
CPU time 0.79 seconds
Started Jun 28 06:14:17 PM PDT 24
Finished Jun 28 06:14:24 PM PDT 24
Peak memory 206196 kb
Host smart-dac8c60c-96b2-43de-af39-81fc8f575c7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26812
61907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.2681261907
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.1879638788
Short name T2470
Test name
Test status
Simulation time 173604956 ps
CPU time 0.77 seconds
Started Jun 28 06:14:14 PM PDT 24
Finished Jun 28 06:14:21 PM PDT 24
Peak memory 206164 kb
Host smart-a9eefba2-ed83-4bd8-8954-26c310a4bb15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18796
38788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.1879638788
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.1048358973
Short name T1423
Test name
Test status
Simulation time 156277278 ps
CPU time 0.78 seconds
Started Jun 28 06:14:18 PM PDT 24
Finished Jun 28 06:14:24 PM PDT 24
Peak memory 206168 kb
Host smart-066e62c3-53c2-422e-b855-1fac49e21e59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10483
58973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.1048358973
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.937243463
Short name T1980
Test name
Test status
Simulation time 257196059 ps
CPU time 1.02 seconds
Started Jun 28 06:14:21 PM PDT 24
Finished Jun 28 06:14:26 PM PDT 24
Peak memory 206196 kb
Host smart-edf08b39-c863-47a8-9287-f70092c89a45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93724
3463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.937243463
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.572755675
Short name T1964
Test name
Test status
Simulation time 6715776170 ps
CPU time 186.17 seconds
Started Jun 28 06:14:41 PM PDT 24
Finished Jun 28 06:17:49 PM PDT 24
Peak memory 206440 kb
Host smart-e899df7f-0228-47c8-98a3-98d99d87a1ff
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=572755675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.572755675
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.2153963092
Short name T2626
Test name
Test status
Simulation time 213015959 ps
CPU time 0.84 seconds
Started Jun 28 06:14:24 PM PDT 24
Finished Jun 28 06:14:29 PM PDT 24
Peak memory 206188 kb
Host smart-01659b2c-d4a7-49b3-a5b1-32d8ed01d35a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21539
63092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.2153963092
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.1121135350
Short name T592
Test name
Test status
Simulation time 147933946 ps
CPU time 0.78 seconds
Started Jun 28 06:14:15 PM PDT 24
Finished Jun 28 06:14:22 PM PDT 24
Peak memory 206188 kb
Host smart-73d90f2a-0d05-4e8c-9e08-5addd95e89c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11211
35350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.1121135350
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.61392753
Short name T1104
Test name
Test status
Simulation time 3590570723 ps
CPU time 34.21 seconds
Started Jun 28 06:14:15 PM PDT 24
Finished Jun 28 06:14:56 PM PDT 24
Peak memory 206436 kb
Host smart-c75bf5fe-245c-451c-97d1-cb394c3145b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61392
753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.61392753
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.3001931629
Short name T1122
Test name
Test status
Simulation time 46891569 ps
CPU time 0.68 seconds
Started Jun 28 06:09:05 PM PDT 24
Finished Jun 28 06:09:07 PM PDT 24
Peak memory 206184 kb
Host smart-66843b77-9223-46d0-831b-08eb0be9f494
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3001931629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.3001931629
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.462137000
Short name T605
Test name
Test status
Simulation time 4160377222 ps
CPU time 4.63 seconds
Started Jun 28 06:08:56 PM PDT 24
Finished Jun 28 06:09:05 PM PDT 24
Peak memory 206416 kb
Host smart-a35a7572-deed-4b73-aa83-a33cba2663d3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=462137000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.462137000
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.1551655951
Short name T228
Test name
Test status
Simulation time 13377094362 ps
CPU time 14.49 seconds
Started Jun 28 06:08:57 PM PDT 24
Finished Jun 28 06:09:16 PM PDT 24
Peak memory 206480 kb
Host smart-9cc734be-2670-4a7f-9255-e8ef58b5b572
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1551655951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.1551655951
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.93964452
Short name T2445
Test name
Test status
Simulation time 23524016850 ps
CPU time 23.71 seconds
Started Jun 28 06:08:53 PM PDT 24
Finished Jun 28 06:09:22 PM PDT 24
Peak memory 206488 kb
Host smart-b326b369-3164-4ee4-ac9a-c4aa3eb96bdb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=93964452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.93964452
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.137983722
Short name T1085
Test name
Test status
Simulation time 175767459 ps
CPU time 0.79 seconds
Started Jun 28 06:08:56 PM PDT 24
Finished Jun 28 06:09:01 PM PDT 24
Peak memory 206044 kb
Host smart-171868da-8891-4e12-99ad-a5713d148f4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13798
3722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.137983722
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.2191690291
Short name T43
Test name
Test status
Simulation time 152213804 ps
CPU time 0.79 seconds
Started Jun 28 06:08:54 PM PDT 24
Finished Jun 28 06:08:59 PM PDT 24
Peak memory 206208 kb
Host smart-87fe974b-b94b-4e4b-98b0-ceb7dcc5e070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21916
90291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.2191690291
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.3980245171
Short name T57
Test name
Test status
Simulation time 150357418 ps
CPU time 0.79 seconds
Started Jun 28 06:08:55 PM PDT 24
Finished Jun 28 06:09:00 PM PDT 24
Peak memory 206176 kb
Host smart-9ec30383-bff3-4f34-ad3e-91553bd796a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39802
45171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.3980245171
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.3948271744
Short name T397
Test name
Test status
Simulation time 179922226 ps
CPU time 0.86 seconds
Started Jun 28 06:09:05 PM PDT 24
Finished Jun 28 06:09:07 PM PDT 24
Peak memory 206196 kb
Host smart-c11e2601-ae64-4521-aeb1-4ecce229ef75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39482
71744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.3948271744
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.436921858
Short name T2247
Test name
Test status
Simulation time 361065007 ps
CPU time 1.17 seconds
Started Jun 28 06:09:05 PM PDT 24
Finished Jun 28 06:09:08 PM PDT 24
Peak memory 206172 kb
Host smart-fd74b401-4b8e-4906-a4e8-9bf8ac0ca4d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43692
1858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.436921858
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.2307300101
Short name T1943
Test name
Test status
Simulation time 1334396351 ps
CPU time 3.28 seconds
Started Jun 28 06:09:08 PM PDT 24
Finished Jun 28 06:09:15 PM PDT 24
Peak memory 206220 kb
Host smart-1aeff4e5-7d87-4614-9000-29cf3022df7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23073
00101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.2307300101
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.388426054
Short name T185
Test name
Test status
Simulation time 20785386607 ps
CPU time 33.76 seconds
Started Jun 28 06:09:04 PM PDT 24
Finished Jun 28 06:09:38 PM PDT 24
Peak memory 206416 kb
Host smart-199cfeff-578a-4b54-86f9-d50d302229b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38842
6054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.388426054
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.2370092228
Short name T964
Test name
Test status
Simulation time 382079876 ps
CPU time 1.26 seconds
Started Jun 28 06:09:15 PM PDT 24
Finished Jun 28 06:09:19 PM PDT 24
Peak memory 206212 kb
Host smart-05f6f658-3e80-4f82-ad2f-cc793d1e7f01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23700
92228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.2370092228
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.3682217750
Short name T1335
Test name
Test status
Simulation time 143596005 ps
CPU time 0.78 seconds
Started Jun 28 06:09:04 PM PDT 24
Finished Jun 28 06:09:05 PM PDT 24
Peak memory 206188 kb
Host smart-901af234-ae24-44b3-83f4-f22d7e01cf26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36822
17750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.3682217750
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.1264430549
Short name T240
Test name
Test status
Simulation time 38094097 ps
CPU time 0.7 seconds
Started Jun 28 06:09:10 PM PDT 24
Finished Jun 28 06:09:13 PM PDT 24
Peak memory 206344 kb
Host smart-605c8866-daea-4061-b77e-cf8b89d2477d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12644
30549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.1264430549
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.3990573490
Short name T915
Test name
Test status
Simulation time 949819687 ps
CPU time 2.3 seconds
Started Jun 28 06:09:05 PM PDT 24
Finished Jun 28 06:09:08 PM PDT 24
Peak memory 206276 kb
Host smart-791061f3-c2fe-4967-a877-c12615301457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39905
73490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.3990573490
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.2022801624
Short name T1998
Test name
Test status
Simulation time 286564702 ps
CPU time 2.12 seconds
Started Jun 28 06:09:05 PM PDT 24
Finished Jun 28 06:09:09 PM PDT 24
Peak memory 206276 kb
Host smart-e1ff6868-7cca-487f-b479-76f90aa73b27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20228
01624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.2022801624
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.3777415317
Short name T442
Test name
Test status
Simulation time 211525495 ps
CPU time 0.9 seconds
Started Jun 28 06:09:07 PM PDT 24
Finished Jun 28 06:09:12 PM PDT 24
Peak memory 206160 kb
Host smart-05b02989-8b8d-49e9-b33b-eeeb4609b14e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37774
15317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.3777415317
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.3111651550
Short name T1738
Test name
Test status
Simulation time 140989413 ps
CPU time 0.77 seconds
Started Jun 28 06:09:06 PM PDT 24
Finished Jun 28 06:09:08 PM PDT 24
Peak memory 206192 kb
Host smart-397070a7-cad7-4a70-a6fd-7fe485979e3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31116
51550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.3111651550
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.137153741
Short name T1619
Test name
Test status
Simulation time 239364690 ps
CPU time 0.88 seconds
Started Jun 28 06:09:12 PM PDT 24
Finished Jun 28 06:09:15 PM PDT 24
Peak memory 206320 kb
Host smart-ed3dc100-3cc4-46e7-b179-58a346b2c717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13715
3741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.137153741
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_invalid_sync.2555949665
Short name T2016
Test name
Test status
Simulation time 9318044854 ps
CPU time 65.35 seconds
Started Jun 28 06:09:06 PM PDT 24
Finished Jun 28 06:10:13 PM PDT 24
Peak memory 206428 kb
Host smart-e28ab823-17ba-4dfd-ad4a-ba6dd4ddecd3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2555949665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_invalid_sync.2555949665
Directory /workspace/4.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.1096397907
Short name T1698
Test name
Test status
Simulation time 278004241 ps
CPU time 1.03 seconds
Started Jun 28 06:09:09 PM PDT 24
Finished Jun 28 06:09:13 PM PDT 24
Peak memory 206192 kb
Host smart-bb2c9d99-0862-4f54-844b-f37104529b34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10963
97907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.1096397907
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.3665607389
Short name T2151
Test name
Test status
Simulation time 23306848748 ps
CPU time 21.21 seconds
Started Jun 28 06:09:07 PM PDT 24
Finished Jun 28 06:09:31 PM PDT 24
Peak memory 206264 kb
Host smart-af268cd9-1734-43db-9555-29dc0809d1ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36656
07389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.3665607389
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.685024795
Short name T2108
Test name
Test status
Simulation time 3284481164 ps
CPU time 3.96 seconds
Started Jun 28 06:09:08 PM PDT 24
Finished Jun 28 06:09:16 PM PDT 24
Peak memory 206232 kb
Host smart-9e942352-594f-4811-8159-7669cea72f1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68502
4795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.685024795
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.3600857403
Short name T2246
Test name
Test status
Simulation time 8070768506 ps
CPU time 62.01 seconds
Started Jun 28 06:09:05 PM PDT 24
Finished Jun 28 06:10:08 PM PDT 24
Peak memory 206472 kb
Host smart-13eed829-1960-467e-8dda-9abe82f05da7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36008
57403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.3600857403
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.1611973357
Short name T526
Test name
Test status
Simulation time 4993801948 ps
CPU time 49.37 seconds
Started Jun 28 06:09:06 PM PDT 24
Finished Jun 28 06:09:58 PM PDT 24
Peak memory 206484 kb
Host smart-b51780d3-e8dd-4da5-8b4f-33779e7bdd55
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1611973357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.1611973357
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.318769064
Short name T96
Test name
Test status
Simulation time 259828631 ps
CPU time 0.96 seconds
Started Jun 28 06:09:05 PM PDT 24
Finished Jun 28 06:09:07 PM PDT 24
Peak memory 205988 kb
Host smart-5af48b8c-17dc-4a78-aa0c-6fe3456ff816
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=318769064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.318769064
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.964141784
Short name T2577
Test name
Test status
Simulation time 247235465 ps
CPU time 0.98 seconds
Started Jun 28 06:09:03 PM PDT 24
Finished Jun 28 06:09:05 PM PDT 24
Peak memory 206216 kb
Host smart-004b77de-3803-4260-bc28-c6b966d8819d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96414
1784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.964141784
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.2620341486
Short name T1138
Test name
Test status
Simulation time 5492978635 ps
CPU time 149.05 seconds
Started Jun 28 06:09:05 PM PDT 24
Finished Jun 28 06:11:36 PM PDT 24
Peak memory 206464 kb
Host smart-0014c42d-7dd8-4722-bd44-3e044d6eead8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26203
41486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.2620341486
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.4247098016
Short name T1518
Test name
Test status
Simulation time 4895252784 ps
CPU time 47 seconds
Started Jun 28 06:09:11 PM PDT 24
Finished Jun 28 06:10:00 PM PDT 24
Peak memory 206616 kb
Host smart-60add0dc-3220-4a7b-b11f-c191e3ef9879
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4247098016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.4247098016
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.1360113904
Short name T1923
Test name
Test status
Simulation time 218143904 ps
CPU time 0.82 seconds
Started Jun 28 06:09:13 PM PDT 24
Finished Jun 28 06:09:16 PM PDT 24
Peak memory 206212 kb
Host smart-d2526460-2d30-4fac-80a1-d1e95083b619
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1360113904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.1360113904
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.1378621683
Short name T399
Test name
Test status
Simulation time 148317287 ps
CPU time 0.75 seconds
Started Jun 28 06:09:15 PM PDT 24
Finished Jun 28 06:09:17 PM PDT 24
Peak memory 206208 kb
Host smart-5c5cb7cf-e3cd-4dd7-9e63-3a8a27c4b866
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13786
21683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.1378621683
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.264815035
Short name T2364
Test name
Test status
Simulation time 216119357 ps
CPU time 0.95 seconds
Started Jun 28 06:09:15 PM PDT 24
Finished Jun 28 06:09:18 PM PDT 24
Peak memory 206208 kb
Host smart-4034bdbc-18d0-46b8-922b-0e1b0b4b8865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26481
5035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.264815035
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.3000453325
Short name T2491
Test name
Test status
Simulation time 187578736 ps
CPU time 0.85 seconds
Started Jun 28 06:09:05 PM PDT 24
Finished Jun 28 06:09:07 PM PDT 24
Peak memory 206192 kb
Host smart-2ebf7fae-b3ed-4516-838c-f4cb095612ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30004
53325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.3000453325
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.3336424980
Short name T805
Test name
Test status
Simulation time 183998455 ps
CPU time 0.78 seconds
Started Jun 28 06:09:05 PM PDT 24
Finished Jun 28 06:09:07 PM PDT 24
Peak memory 206212 kb
Host smart-8f1a1cfd-caf5-4998-9c23-8da3aec1537f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33364
24980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.3336424980
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.442316352
Short name T1624
Test name
Test status
Simulation time 156251335 ps
CPU time 0.77 seconds
Started Jun 28 06:09:15 PM PDT 24
Finished Jun 28 06:09:18 PM PDT 24
Peak memory 206192 kb
Host smart-c11289b5-c256-4715-8412-12d00de9b081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44231
6352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.442316352
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.688900334
Short name T1310
Test name
Test status
Simulation time 150792689 ps
CPU time 0.79 seconds
Started Jun 28 06:09:06 PM PDT 24
Finished Jun 28 06:09:10 PM PDT 24
Peak memory 206184 kb
Host smart-6ffbcdc1-2e36-41c0-a091-58a76af66721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68890
0334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.688900334
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.470540034
Short name T2116
Test name
Test status
Simulation time 247767549 ps
CPU time 0.92 seconds
Started Jun 28 06:09:13 PM PDT 24
Finished Jun 28 06:09:16 PM PDT 24
Peak memory 206212 kb
Host smart-5b00b58d-0c80-4461-8e09-9861c4a65f9f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=470540034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.470540034
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.671289175
Short name T938
Test name
Test status
Simulation time 190851064 ps
CPU time 0.93 seconds
Started Jun 28 06:09:10 PM PDT 24
Finished Jun 28 06:09:14 PM PDT 24
Peak memory 206360 kb
Host smart-3f7fd3c6-3c73-430d-9db2-fc973b37854a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67128
9175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.671289175
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.55029567
Short name T198
Test name
Test status
Simulation time 172017113 ps
CPU time 0.77 seconds
Started Jun 28 06:09:05 PM PDT 24
Finished Jun 28 06:09:08 PM PDT 24
Peak memory 206172 kb
Host smart-d987ef84-e964-4fc2-939e-0b09f8bbc135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55029
567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.55029567
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.4165302902
Short name T1645
Test name
Test status
Simulation time 34701407 ps
CPU time 0.67 seconds
Started Jun 28 06:09:05 PM PDT 24
Finished Jun 28 06:09:07 PM PDT 24
Peak memory 206052 kb
Host smart-967f13a9-5e32-4f27-856a-569b39437418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41653
02902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.4165302902
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.3858385491
Short name T2326
Test name
Test status
Simulation time 16702524066 ps
CPU time 38.01 seconds
Started Jun 28 06:09:10 PM PDT 24
Finished Jun 28 06:09:51 PM PDT 24
Peak memory 206660 kb
Host smart-464e744a-d9cf-435c-9bb6-a02c7d2b681c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38583
85491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.3858385491
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.2598116092
Short name T1001
Test name
Test status
Simulation time 154774219 ps
CPU time 0.79 seconds
Started Jun 28 06:09:08 PM PDT 24
Finished Jun 28 06:09:12 PM PDT 24
Peak memory 206164 kb
Host smart-dbce952f-703b-4226-9d78-19897dcec677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25981
16092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.2598116092
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.619161686
Short name T2027
Test name
Test status
Simulation time 237795204 ps
CPU time 0.98 seconds
Started Jun 28 06:09:14 PM PDT 24
Finished Jun 28 06:09:16 PM PDT 24
Peak memory 206200 kb
Host smart-2b06e456-9f52-462f-84e8-310868646164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61916
1686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.619161686
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.236150617
Short name T2059
Test name
Test status
Simulation time 5451919061 ps
CPU time 140.37 seconds
Started Jun 28 06:09:07 PM PDT 24
Finished Jun 28 06:11:31 PM PDT 24
Peak memory 206504 kb
Host smart-f3bc34da-ce32-416f-b014-9a77c8700da5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=236150617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.236150617
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.79278900
Short name T2288
Test name
Test status
Simulation time 13704099848 ps
CPU time 71.94 seconds
Started Jun 28 06:09:09 PM PDT 24
Finished Jun 28 06:10:24 PM PDT 24
Peak memory 206480 kb
Host smart-c98f8e08-ac8a-4c5d-bd84-a5b84da0a20d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=79278900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.79278900
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.4186232447
Short name T371
Test name
Test status
Simulation time 12336035426 ps
CPU time 78.27 seconds
Started Jun 28 06:09:12 PM PDT 24
Finished Jun 28 06:10:32 PM PDT 24
Peak memory 206524 kb
Host smart-07250fb0-147b-408f-9719-de95249f8b16
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4186232447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.4186232447
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.174768724
Short name T740
Test name
Test status
Simulation time 172164255 ps
CPU time 0.78 seconds
Started Jun 28 06:09:06 PM PDT 24
Finished Jun 28 06:09:09 PM PDT 24
Peak memory 206200 kb
Host smart-e7cc0693-52d4-4736-a434-4c8702ad1fef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17476
8724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.174768724
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.1897830977
Short name T872
Test name
Test status
Simulation time 162553065 ps
CPU time 0.85 seconds
Started Jun 28 06:09:06 PM PDT 24
Finished Jun 28 06:09:09 PM PDT 24
Peak memory 206164 kb
Host smart-bacc93ab-b654-4f7d-9a6b-4bfe5d13a59e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18978
30977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.1897830977
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.2321209140
Short name T1370
Test name
Test status
Simulation time 231904001 ps
CPU time 0.86 seconds
Started Jun 28 06:09:06 PM PDT 24
Finished Jun 28 06:09:09 PM PDT 24
Peak memory 206196 kb
Host smart-dcb70fdc-1b99-4ad9-a086-17414e7be21c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23212
09140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.2321209140
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.1472336441
Short name T73
Test name
Test status
Simulation time 161272766 ps
CPU time 0.84 seconds
Started Jun 28 06:09:10 PM PDT 24
Finished Jun 28 06:09:13 PM PDT 24
Peak memory 206356 kb
Host smart-7f0fe480-f339-405a-a4dd-5af7f7410807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14723
36441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.1472336441
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.4063923231
Short name T201
Test name
Test status
Simulation time 259901605 ps
CPU time 1.09 seconds
Started Jun 28 06:09:08 PM PDT 24
Finished Jun 28 06:09:13 PM PDT 24
Peak memory 224032 kb
Host smart-29bfa813-2b79-4dce-9ffc-59092eebc027
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4063923231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.4063923231
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.3378885874
Short name T46
Test name
Test status
Simulation time 392825910 ps
CPU time 1.3 seconds
Started Jun 28 06:09:12 PM PDT 24
Finished Jun 28 06:09:16 PM PDT 24
Peak memory 206320 kb
Host smart-99776ff2-3fe0-4101-a0fd-489f4a373934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33788
85874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.3378885874
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.3940852068
Short name T2408
Test name
Test status
Simulation time 309168275 ps
CPU time 1.02 seconds
Started Jun 28 06:09:08 PM PDT 24
Finished Jun 28 06:09:12 PM PDT 24
Peak memory 206120 kb
Host smart-4f95f5a0-3a66-45aa-9797-97c200ce19a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39408
52068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.3940852068
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.1209386301
Short name T812
Test name
Test status
Simulation time 160519640 ps
CPU time 0.8 seconds
Started Jun 28 06:09:07 PM PDT 24
Finished Jun 28 06:09:10 PM PDT 24
Peak memory 206172 kb
Host smart-934fa79a-e48f-468b-a08f-aceaa5900cb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12093
86301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.1209386301
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.1310921704
Short name T1093
Test name
Test status
Simulation time 168457717 ps
CPU time 0.84 seconds
Started Jun 28 06:09:09 PM PDT 24
Finished Jun 28 06:09:13 PM PDT 24
Peak memory 206192 kb
Host smart-ca2ca13c-2c1a-4228-911b-1a6ff83c54da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13109
21704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.1310921704
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.2301419743
Short name T2098
Test name
Test status
Simulation time 219866589 ps
CPU time 0.91 seconds
Started Jun 28 06:09:07 PM PDT 24
Finished Jun 28 06:09:12 PM PDT 24
Peak memory 206160 kb
Host smart-ea363984-b299-49e4-82f5-65e7dffe5f8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23014
19743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.2301419743
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.3981152367
Short name T781
Test name
Test status
Simulation time 5375817204 ps
CPU time 48.47 seconds
Started Jun 28 06:09:07 PM PDT 24
Finished Jun 28 06:09:59 PM PDT 24
Peak memory 206440 kb
Host smart-a2b532de-8d5f-453c-8f44-11a1bb20377c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3981152367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.3981152367
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.768389874
Short name T1246
Test name
Test status
Simulation time 196553511 ps
CPU time 0.83 seconds
Started Jun 28 06:09:07 PM PDT 24
Finished Jun 28 06:09:10 PM PDT 24
Peak memory 206164 kb
Host smart-83bb02cc-1b17-4d58-ae12-5f300fc8774f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76838
9874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.768389874
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.353840916
Short name T571
Test name
Test status
Simulation time 208989509 ps
CPU time 0.83 seconds
Started Jun 28 06:09:12 PM PDT 24
Finished Jun 28 06:09:15 PM PDT 24
Peak memory 206328 kb
Host smart-ae18ec14-518a-4860-8439-2a626b3c0d66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35384
0916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.353840916
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.308718919
Short name T2361
Test name
Test status
Simulation time 3724991496 ps
CPU time 104.77 seconds
Started Jun 28 06:09:08 PM PDT 24
Finished Jun 28 06:10:56 PM PDT 24
Peak memory 206436 kb
Host smart-034f262a-3053-41ba-82c9-1da65a6f1154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30871
8919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.308718919
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.3590930516
Short name T704
Test name
Test status
Simulation time 44902504 ps
CPU time 0.74 seconds
Started Jun 28 06:14:28 PM PDT 24
Finished Jun 28 06:14:33 PM PDT 24
Peak memory 206212 kb
Host smart-1f81f1a1-9fcb-4f28-9f53-4c35fcc3b752
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3590930516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.3590930516
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.1040016402
Short name T2042
Test name
Test status
Simulation time 4335381729 ps
CPU time 5.02 seconds
Started Jun 28 06:14:23 PM PDT 24
Finished Jun 28 06:14:31 PM PDT 24
Peak memory 206324 kb
Host smart-46f69555-72fc-42eb-99b5-82e2c3422661
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1040016402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.1040016402
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.214537266
Short name T1051
Test name
Test status
Simulation time 13318375352 ps
CPU time 11.84 seconds
Started Jun 28 06:14:23 PM PDT 24
Finished Jun 28 06:14:38 PM PDT 24
Peak memory 206420 kb
Host smart-8f4e43f7-5628-4939-a33d-4f4147e631ec
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=214537266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.214537266
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.3395095819
Short name T1715
Test name
Test status
Simulation time 23370968344 ps
CPU time 24.64 seconds
Started Jun 28 06:14:22 PM PDT 24
Finished Jun 28 06:14:51 PM PDT 24
Peak memory 206296 kb
Host smart-73037091-fdcd-437f-829d-441dbce897e1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3395095819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.3395095819
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.3328759187
Short name T815
Test name
Test status
Simulation time 200679713 ps
CPU time 0.87 seconds
Started Jun 28 06:14:38 PM PDT 24
Finished Jun 28 06:14:41 PM PDT 24
Peak memory 206196 kb
Host smart-5e19b4f9-67f0-4d80-bddf-392a181d8739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33287
59187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.3328759187
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.662785376
Short name T2406
Test name
Test status
Simulation time 152390558 ps
CPU time 0.78 seconds
Started Jun 28 06:14:23 PM PDT 24
Finished Jun 28 06:14:27 PM PDT 24
Peak memory 206196 kb
Host smart-bb12556e-0989-4111-a9c5-6827315d3d67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66278
5376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.662785376
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.2411962614
Short name T624
Test name
Test status
Simulation time 186314939 ps
CPU time 0.83 seconds
Started Jun 28 06:14:24 PM PDT 24
Finished Jun 28 06:14:28 PM PDT 24
Peak memory 206188 kb
Host smart-fe3703bf-4be9-4ae9-a8b6-78c789acb868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24119
62614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.2411962614
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.2489282171
Short name T1157
Test name
Test status
Simulation time 940093977 ps
CPU time 2.25 seconds
Started Jun 28 06:14:24 PM PDT 24
Finished Jun 28 06:14:29 PM PDT 24
Peak memory 206268 kb
Host smart-a155c5d4-3bc8-4bd7-85ba-a2a57b46c2cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24892
82171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.2489282171
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.1990347204
Short name T993
Test name
Test status
Simulation time 8025684056 ps
CPU time 16.44 seconds
Started Jun 28 06:14:41 PM PDT 24
Finished Jun 28 06:15:00 PM PDT 24
Peak memory 206444 kb
Host smart-7ac203e0-6973-404a-87fd-3cb1b63a2021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19903
47204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.1990347204
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.3183567044
Short name T1547
Test name
Test status
Simulation time 462266150 ps
CPU time 1.3 seconds
Started Jun 28 06:14:32 PM PDT 24
Finished Jun 28 06:14:36 PM PDT 24
Peak memory 206164 kb
Host smart-96023f82-f4a4-4470-b506-85d74f05dcd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31835
67044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.3183567044
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.1254179764
Short name T1541
Test name
Test status
Simulation time 149137383 ps
CPU time 0.81 seconds
Started Jun 28 06:14:25 PM PDT 24
Finished Jun 28 06:14:30 PM PDT 24
Peak memory 206128 kb
Host smart-622925c6-a275-4e52-9db2-69f3f4f5f1ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12541
79764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.1254179764
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.2730127751
Short name T1684
Test name
Test status
Simulation time 30070307 ps
CPU time 0.66 seconds
Started Jun 28 06:14:24 PM PDT 24
Finished Jun 28 06:14:28 PM PDT 24
Peak memory 206188 kb
Host smart-2524ec1f-86ba-464d-83e8-61378916e271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27301
27751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.2730127751
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.2410245469
Short name T145
Test name
Test status
Simulation time 883789767 ps
CPU time 2.17 seconds
Started Jun 28 06:14:30 PM PDT 24
Finished Jun 28 06:14:36 PM PDT 24
Peak memory 206272 kb
Host smart-2d2f4cc3-bfcf-4514-889b-edca6bb787fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24102
45469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.2410245469
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.3260852593
Short name T1294
Test name
Test status
Simulation time 290107342 ps
CPU time 2.09 seconds
Started Jun 28 06:14:44 PM PDT 24
Finished Jun 28 06:14:51 PM PDT 24
Peak memory 206268 kb
Host smart-9cc69fbf-2d9f-4aa4-b2f0-07d98ba38c9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32608
52593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.3260852593
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.544607055
Short name T2471
Test name
Test status
Simulation time 196372529 ps
CPU time 0.91 seconds
Started Jun 28 06:14:28 PM PDT 24
Finished Jun 28 06:14:33 PM PDT 24
Peak memory 206208 kb
Host smart-7af9133c-7497-48f4-89ae-5c65ea015102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54460
7055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.544607055
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.1513692788
Short name T1083
Test name
Test status
Simulation time 148953903 ps
CPU time 0.77 seconds
Started Jun 28 06:14:27 PM PDT 24
Finished Jun 28 06:14:32 PM PDT 24
Peak memory 206212 kb
Host smart-c3183159-8af7-4c96-88c5-f6c92fbc1d6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15136
92788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.1513692788
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.1613621437
Short name T2375
Test name
Test status
Simulation time 227968650 ps
CPU time 0.91 seconds
Started Jun 28 06:14:30 PM PDT 24
Finished Jun 28 06:14:35 PM PDT 24
Peak memory 206208 kb
Host smart-49c4839f-ebc8-4036-9e94-526f9f1db7e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16136
21437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.1613621437
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_invalid_sync.3742724193
Short name T963
Test name
Test status
Simulation time 9068224353 ps
CPU time 83.89 seconds
Started Jun 28 06:14:29 PM PDT 24
Finished Jun 28 06:15:56 PM PDT 24
Peak memory 206400 kb
Host smart-5dd9a4a0-2090-4033-b05c-23f94a19a959
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3742724193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.3742724193
Directory /workspace/40.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.2949859217
Short name T2347
Test name
Test status
Simulation time 232952109 ps
CPU time 0.9 seconds
Started Jun 28 06:14:32 PM PDT 24
Finished Jun 28 06:14:36 PM PDT 24
Peak memory 206196 kb
Host smart-09bf152b-8cfe-4192-a788-422537c4cdc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29498
59217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.2949859217
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.468495357
Short name T2229
Test name
Test status
Simulation time 23299596608 ps
CPU time 24.17 seconds
Started Jun 28 06:14:23 PM PDT 24
Finished Jun 28 06:14:51 PM PDT 24
Peak memory 206316 kb
Host smart-6e3d32c8-4234-4579-83b2-342f96ccf0da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46849
5357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.468495357
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.3657164409
Short name T677
Test name
Test status
Simulation time 3384153843 ps
CPU time 4.22 seconds
Started Jun 28 06:14:24 PM PDT 24
Finished Jun 28 06:14:32 PM PDT 24
Peak memory 206212 kb
Host smart-b6988a45-8849-4136-b8e3-82eef7e6a9ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36571
64409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.3657164409
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.770615758
Short name T359
Test name
Test status
Simulation time 6369320337 ps
CPU time 61.15 seconds
Started Jun 28 06:14:27 PM PDT 24
Finished Jun 28 06:15:32 PM PDT 24
Peak memory 206428 kb
Host smart-7785bb5f-b7b7-4799-ba59-cfa9fc0fe6b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77061
5758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.770615758
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.2976390597
Short name T1537
Test name
Test status
Simulation time 6774896323 ps
CPU time 63.87 seconds
Started Jun 28 06:14:47 PM PDT 24
Finished Jun 28 06:15:56 PM PDT 24
Peak memory 206460 kb
Host smart-0d6727ae-7810-4e46-a022-a7c465290506
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2976390597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.2976390597
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.1401515546
Short name T922
Test name
Test status
Simulation time 248868737 ps
CPU time 0.91 seconds
Started Jun 28 06:14:25 PM PDT 24
Finished Jun 28 06:14:30 PM PDT 24
Peak memory 206216 kb
Host smart-08260c5c-d448-4e30-944a-12b8438870b6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1401515546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.1401515546
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.1730737226
Short name T583
Test name
Test status
Simulation time 224394084 ps
CPU time 0.96 seconds
Started Jun 28 06:14:28 PM PDT 24
Finished Jun 28 06:14:33 PM PDT 24
Peak memory 206200 kb
Host smart-a6b2ab09-96e2-4f0e-a8ae-536debcff1ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17307
37226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.1730737226
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.1971875459
Short name T995
Test name
Test status
Simulation time 5919727344 ps
CPU time 56.36 seconds
Started Jun 28 06:14:28 PM PDT 24
Finished Jun 28 06:15:29 PM PDT 24
Peak memory 206404 kb
Host smart-2dee0da1-4bd4-4758-bc40-3e02207e4ed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19718
75459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.1971875459
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.1028627846
Short name T1672
Test name
Test status
Simulation time 3899408243 ps
CPU time 26.85 seconds
Started Jun 28 06:14:26 PM PDT 24
Finished Jun 28 06:14:58 PM PDT 24
Peak memory 206500 kb
Host smart-19d95f19-599b-4255-b63c-53d833dbd415
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1028627846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.1028627846
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.2477836608
Short name T1718
Test name
Test status
Simulation time 153003132 ps
CPU time 0.79 seconds
Started Jun 28 06:14:25 PM PDT 24
Finished Jun 28 06:14:30 PM PDT 24
Peak memory 206216 kb
Host smart-90fecfb6-5f2b-47a5-96e9-96c0a88b6e32
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2477836608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.2477836608
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.2902652719
Short name T2292
Test name
Test status
Simulation time 156646360 ps
CPU time 0.84 seconds
Started Jun 28 06:14:38 PM PDT 24
Finished Jun 28 06:14:40 PM PDT 24
Peak memory 206200 kb
Host smart-d04f208d-6804-452a-ab19-a3b73c12ec2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29026
52719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.2902652719
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.3398679007
Short name T1985
Test name
Test status
Simulation time 226304452 ps
CPU time 0.92 seconds
Started Jun 28 06:14:33 PM PDT 24
Finished Jun 28 06:14:36 PM PDT 24
Peak memory 206188 kb
Host smart-398d96e7-c21b-4c8f-b20e-244a0e5d986a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33986
79007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.3398679007
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.3666976738
Short name T719
Test name
Test status
Simulation time 191324603 ps
CPU time 0.82 seconds
Started Jun 28 06:14:26 PM PDT 24
Finished Jun 28 06:14:31 PM PDT 24
Peak memory 206196 kb
Host smart-52b5ab45-aa9b-4dda-bbff-018726d34404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36669
76738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.3666976738
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.1812485817
Short name T838
Test name
Test status
Simulation time 163750402 ps
CPU time 0.79 seconds
Started Jun 28 06:14:26 PM PDT 24
Finished Jun 28 06:14:31 PM PDT 24
Peak memory 206192 kb
Host smart-1148d756-fb1e-4ee0-aefd-cc7d2d895b91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18124
85817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.1812485817
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.2715043219
Short name T974
Test name
Test status
Simulation time 177593293 ps
CPU time 0.86 seconds
Started Jun 28 06:14:30 PM PDT 24
Finished Jun 28 06:14:35 PM PDT 24
Peak memory 206176 kb
Host smart-e883b449-ff8d-460b-8ba9-fdb83dce2960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27150
43219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.2715043219
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.715580488
Short name T1060
Test name
Test status
Simulation time 170427754 ps
CPU time 0.81 seconds
Started Jun 28 06:14:27 PM PDT 24
Finished Jun 28 06:14:32 PM PDT 24
Peak memory 206200 kb
Host smart-c27d55d4-b247-4fd6-861b-76b9569f3a70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71558
0488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.715580488
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.3934748847
Short name T1585
Test name
Test status
Simulation time 186600311 ps
CPU time 0.83 seconds
Started Jun 28 06:14:27 PM PDT 24
Finished Jun 28 06:14:32 PM PDT 24
Peak memory 206300 kb
Host smart-ec756d1e-a7a6-498a-8d8a-4bcb4d2588ae
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3934748847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.3934748847
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.806481877
Short name T748
Test name
Test status
Simulation time 145671895 ps
CPU time 0.74 seconds
Started Jun 28 06:14:24 PM PDT 24
Finished Jun 28 06:14:28 PM PDT 24
Peak memory 206168 kb
Host smart-e390afe6-33de-43d7-97d7-be9d6e6ef077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80648
1877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.806481877
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.1308062706
Short name T1552
Test name
Test status
Simulation time 29866657 ps
CPU time 0.66 seconds
Started Jun 28 06:14:27 PM PDT 24
Finished Jun 28 06:14:33 PM PDT 24
Peak memory 206204 kb
Host smart-0bdb9b09-2d86-40fe-80d0-d6ca017b3bfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13080
62706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.1308062706
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.1762977942
Short name T1502
Test name
Test status
Simulation time 12831467170 ps
CPU time 30.09 seconds
Started Jun 28 06:14:29 PM PDT 24
Finished Jun 28 06:15:03 PM PDT 24
Peak memory 206420 kb
Host smart-bb8d9eae-aef1-4526-95a1-d5908da95008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17629
77942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.1762977942
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.4259593265
Short name T869
Test name
Test status
Simulation time 312941462 ps
CPU time 1.01 seconds
Started Jun 28 06:14:30 PM PDT 24
Finished Jun 28 06:14:35 PM PDT 24
Peak memory 206200 kb
Host smart-ca71600e-fe9f-4e9b-9687-015b4fc5cfe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42595
93265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.4259593265
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.2212799286
Short name T1614
Test name
Test status
Simulation time 187718194 ps
CPU time 0.91 seconds
Started Jun 28 06:14:30 PM PDT 24
Finished Jun 28 06:14:35 PM PDT 24
Peak memory 206184 kb
Host smart-b41bf1e5-8731-40bf-9310-d07d1db9ab4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22127
99286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.2212799286
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.2175813875
Short name T2224
Test name
Test status
Simulation time 182906988 ps
CPU time 0.87 seconds
Started Jun 28 06:14:27 PM PDT 24
Finished Jun 28 06:14:32 PM PDT 24
Peak memory 206200 kb
Host smart-c3430f27-7bc7-4be2-954f-7397ccd9ff65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21758
13875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.2175813875
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.3271857676
Short name T716
Test name
Test status
Simulation time 211922482 ps
CPU time 0.9 seconds
Started Jun 28 06:14:41 PM PDT 24
Finished Jun 28 06:14:44 PM PDT 24
Peak memory 206192 kb
Host smart-7defb136-0ed7-45ab-9e1a-f6637b615cb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32718
57676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.3271857676
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.3960791647
Short name T1517
Test name
Test status
Simulation time 214347731 ps
CPU time 0.84 seconds
Started Jun 28 06:14:27 PM PDT 24
Finished Jun 28 06:14:32 PM PDT 24
Peak memory 206192 kb
Host smart-af90c235-858c-460d-bdc4-691167e81e28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39607
91647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.3960791647
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.3892787188
Short name T699
Test name
Test status
Simulation time 145987252 ps
CPU time 0.76 seconds
Started Jun 28 06:14:26 PM PDT 24
Finished Jun 28 06:14:31 PM PDT 24
Peak memory 206196 kb
Host smart-bc87f2db-7092-45af-bb63-f4ccd2ac51a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38927
87188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.3892787188
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.830372233
Short name T1107
Test name
Test status
Simulation time 212115868 ps
CPU time 0.95 seconds
Started Jun 28 06:14:34 PM PDT 24
Finished Jun 28 06:14:37 PM PDT 24
Peak memory 206192 kb
Host smart-a67a5940-1efe-4c77-a4ff-4dde00be1736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83037
2233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.830372233
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.1593713069
Short name T2050
Test name
Test status
Simulation time 3891941973 ps
CPU time 36.43 seconds
Started Jun 28 06:14:27 PM PDT 24
Finished Jun 28 06:15:08 PM PDT 24
Peak memory 206528 kb
Host smart-d97d3824-cc6d-43ff-9d1f-b48c281388cb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1593713069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.1593713069
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.1158714330
Short name T2297
Test name
Test status
Simulation time 171342875 ps
CPU time 0.81 seconds
Started Jun 28 06:14:41 PM PDT 24
Finished Jun 28 06:14:45 PM PDT 24
Peak memory 206144 kb
Host smart-bdab0e6a-15b1-4590-b371-b252eb0df6b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11587
14330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.1158714330
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.2186041683
Short name T559
Test name
Test status
Simulation time 195675160 ps
CPU time 0.79 seconds
Started Jun 28 06:14:28 PM PDT 24
Finished Jun 28 06:14:33 PM PDT 24
Peak memory 206324 kb
Host smart-0fc9235d-f42c-4d9e-ad26-cdd385a0aeb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21860
41683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.2186041683
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.779767481
Short name T2623
Test name
Test status
Simulation time 4613969768 ps
CPU time 43.54 seconds
Started Jun 28 06:14:41 PM PDT 24
Finished Jun 28 06:15:27 PM PDT 24
Peak memory 206440 kb
Host smart-e07f9096-9421-437f-9530-cf0b71eb278e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77976
7481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.779767481
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.1892834258
Short name T864
Test name
Test status
Simulation time 59803492 ps
CPU time 0.69 seconds
Started Jun 28 06:14:50 PM PDT 24
Finished Jun 28 06:14:55 PM PDT 24
Peak memory 206200 kb
Host smart-e52cf232-d73e-445c-b44f-58ad198e5265
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1892834258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.1892834258
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.1360861952
Short name T2174
Test name
Test status
Simulation time 3430834225 ps
CPU time 4.05 seconds
Started Jun 28 06:14:24 PM PDT 24
Finished Jun 28 06:14:31 PM PDT 24
Peak memory 206276 kb
Host smart-493a3e48-ac87-402e-ad86-3d12959ebdd0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1360861952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.1360861952
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.3895373930
Short name T1543
Test name
Test status
Simulation time 13535933888 ps
CPU time 12.58 seconds
Started Jun 28 06:14:25 PM PDT 24
Finished Jun 28 06:14:42 PM PDT 24
Peak memory 206440 kb
Host smart-475179b4-0f19-4d0d-bbb2-594e99758274
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3895373930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.3895373930
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.595644508
Short name T891
Test name
Test status
Simulation time 23331695537 ps
CPU time 24.3 seconds
Started Jun 28 06:14:26 PM PDT 24
Finished Jun 28 06:14:55 PM PDT 24
Peak memory 206412 kb
Host smart-3161ceb0-fdbe-485a-a6fb-7ac88c59c8fc
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=595644508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.595644508
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.4002653117
Short name T2550
Test name
Test status
Simulation time 184404069 ps
CPU time 0.87 seconds
Started Jun 28 06:14:31 PM PDT 24
Finished Jun 28 06:14:35 PM PDT 24
Peak memory 206156 kb
Host smart-83a41ca7-4f92-4d4c-b9c7-d1e9275c704d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40026
53117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.4002653117
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.1548908718
Short name T2086
Test name
Test status
Simulation time 146927311 ps
CPU time 0.76 seconds
Started Jun 28 06:14:26 PM PDT 24
Finished Jun 28 06:14:31 PM PDT 24
Peak memory 206196 kb
Host smart-70a68e4b-2640-4842-b44a-388c2304f567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15489
08718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.1548908718
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.3204710123
Short name T52
Test name
Test status
Simulation time 338179919 ps
CPU time 1.23 seconds
Started Jun 28 06:14:27 PM PDT 24
Finished Jun 28 06:14:32 PM PDT 24
Peak memory 206192 kb
Host smart-f083fd23-eb90-4a4a-b619-9f11843c7ffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32047
10123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.3204710123
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.1517515688
Short name T450
Test name
Test status
Simulation time 616081147 ps
CPU time 1.51 seconds
Started Jun 28 06:14:46 PM PDT 24
Finished Jun 28 06:14:52 PM PDT 24
Peak memory 206188 kb
Host smart-68534d18-777f-4a89-bcbe-d416c987a83b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15175
15688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.1517515688
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.2119120042
Short name T1173
Test name
Test status
Simulation time 22913743782 ps
CPU time 47.95 seconds
Started Jun 28 06:14:40 PM PDT 24
Finished Jun 28 06:15:30 PM PDT 24
Peak memory 206436 kb
Host smart-711f0782-9a85-40aa-b1d9-11e7c168ee67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21191
20042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.2119120042
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.3675802308
Short name T615
Test name
Test status
Simulation time 393719965 ps
CPU time 1.32 seconds
Started Jun 28 06:14:33 PM PDT 24
Finished Jun 28 06:14:37 PM PDT 24
Peak memory 206196 kb
Host smart-cc7fd031-a52f-4fa4-8149-ce99dd1111c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36758
02308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.3675802308
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.1490525450
Short name T35
Test name
Test status
Simulation time 146408913 ps
CPU time 0.78 seconds
Started Jun 28 06:14:31 PM PDT 24
Finished Jun 28 06:14:35 PM PDT 24
Peak memory 206168 kb
Host smart-283ae1c1-2a6a-4dba-8dee-6e2fd142e9e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14905
25450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.1490525450
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.3923677856
Short name T1417
Test name
Test status
Simulation time 65431367 ps
CPU time 0.7 seconds
Started Jun 28 06:14:31 PM PDT 24
Finished Jun 28 06:14:35 PM PDT 24
Peak memory 205616 kb
Host smart-b23d3b3d-db77-4c78-a706-8cc1ee3dd7fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39236
77856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.3923677856
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.2084214087
Short name T2011
Test name
Test status
Simulation time 954553242 ps
CPU time 2.14 seconds
Started Jun 28 06:14:39 PM PDT 24
Finished Jun 28 06:14:42 PM PDT 24
Peak memory 206288 kb
Host smart-3ad0685d-affe-4002-b8b9-0a435054856a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20842
14087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.2084214087
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.3948056758
Short name T189
Test name
Test status
Simulation time 258987941 ps
CPU time 1.67 seconds
Started Jun 28 06:14:26 PM PDT 24
Finished Jun 28 06:14:32 PM PDT 24
Peak memory 206280 kb
Host smart-fe82a6be-6897-43a0-9200-eb35e15dce2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39480
56758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.3948056758
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.1350089667
Short name T933
Test name
Test status
Simulation time 211265648 ps
CPU time 0.94 seconds
Started Jun 28 06:14:30 PM PDT 24
Finished Jun 28 06:14:35 PM PDT 24
Peak memory 206184 kb
Host smart-e4f0a354-13f6-471c-a6d1-b1ff717a4a92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13500
89667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.1350089667
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.1243717424
Short name T2225
Test name
Test status
Simulation time 204429710 ps
CPU time 0.79 seconds
Started Jun 28 06:14:31 PM PDT 24
Finished Jun 28 06:14:35 PM PDT 24
Peak memory 206192 kb
Host smart-c3e6e02a-1760-4e5f-ab94-14a615b2d755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12437
17424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.1243717424
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.971612285
Short name T1795
Test name
Test status
Simulation time 197925105 ps
CPU time 0.93 seconds
Started Jun 28 06:14:31 PM PDT 24
Finished Jun 28 06:14:35 PM PDT 24
Peak memory 206204 kb
Host smart-20b53018-a1bb-4009-b50a-2005024cbb03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97161
2285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.971612285
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.58933935
Short name T374
Test name
Test status
Simulation time 196385422 ps
CPU time 0.83 seconds
Started Jun 28 06:14:45 PM PDT 24
Finished Jun 28 06:14:50 PM PDT 24
Peak memory 206196 kb
Host smart-4067e1f4-f864-42f7-be70-f9ce8fffc500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58933
935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.58933935
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.3035905933
Short name T857
Test name
Test status
Simulation time 23270074738 ps
CPU time 22.55 seconds
Started Jun 28 06:14:30 PM PDT 24
Finished Jun 28 06:14:56 PM PDT 24
Peak memory 206320 kb
Host smart-9da89599-6f75-442b-9c30-3830732815b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30359
05933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.3035905933
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.2197372202
Short name T2405
Test name
Test status
Simulation time 3268317631 ps
CPU time 4.56 seconds
Started Jun 28 06:14:25 PM PDT 24
Finished Jun 28 06:14:33 PM PDT 24
Peak memory 206244 kb
Host smart-4c23a073-43df-4f7b-8f23-b8405b29b711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21973
72202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.2197372202
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.4141654270
Short name T1750
Test name
Test status
Simulation time 9994839821 ps
CPU time 90.07 seconds
Started Jun 28 06:14:42 PM PDT 24
Finished Jun 28 06:16:16 PM PDT 24
Peak memory 206420 kb
Host smart-6a0b4799-194d-40e7-9d3a-e5c91343bc27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41416
54270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.4141654270
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.3401971248
Short name T1217
Test name
Test status
Simulation time 4466143539 ps
CPU time 120.48 seconds
Started Jun 28 06:14:49 PM PDT 24
Finished Jun 28 06:16:54 PM PDT 24
Peak memory 206424 kb
Host smart-dbdd9654-bd04-4d2c-96de-1afdf1b7feee
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3401971248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.3401971248
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.2660061025
Short name T2217
Test name
Test status
Simulation time 248724983 ps
CPU time 0.93 seconds
Started Jun 28 06:14:43 PM PDT 24
Finished Jun 28 06:14:48 PM PDT 24
Peak memory 206216 kb
Host smart-491bb0d5-59a9-4cb2-bff0-7ddc109fa321
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2660061025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.2660061025
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.3009953476
Short name T701
Test name
Test status
Simulation time 198709803 ps
CPU time 0.92 seconds
Started Jun 28 06:14:51 PM PDT 24
Finished Jun 28 06:14:56 PM PDT 24
Peak memory 206196 kb
Host smart-7a4ff251-9f69-4e94-b486-8636e14b0f43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30099
53476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.3009953476
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.108944933
Short name T555
Test name
Test status
Simulation time 4383644238 ps
CPU time 123.22 seconds
Started Jun 28 06:14:43 PM PDT 24
Finished Jun 28 06:16:49 PM PDT 24
Peak memory 206600 kb
Host smart-ab51c20f-1ecf-495f-8486-2346ba661199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10894
4933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.108944933
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.168286417
Short name T614
Test name
Test status
Simulation time 4941705193 ps
CPU time 48.48 seconds
Started Jun 28 06:14:49 PM PDT 24
Finished Jun 28 06:15:43 PM PDT 24
Peak memory 206412 kb
Host smart-d41e0561-4d95-4737-a50c-bf5b65f726af
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=168286417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.168286417
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.1100098408
Short name T2006
Test name
Test status
Simulation time 198953215 ps
CPU time 0.86 seconds
Started Jun 28 06:14:41 PM PDT 24
Finished Jun 28 06:14:44 PM PDT 24
Peak memory 206220 kb
Host smart-8c912013-3f95-464a-8c8d-3c156177a993
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1100098408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.1100098408
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.1315592470
Short name T2077
Test name
Test status
Simulation time 208259863 ps
CPU time 0.82 seconds
Started Jun 28 06:14:38 PM PDT 24
Finished Jun 28 06:14:40 PM PDT 24
Peak memory 206208 kb
Host smart-e2777310-12af-49f7-86c3-e47d1baaafa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13155
92470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.1315592470
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.3818266698
Short name T113
Test name
Test status
Simulation time 186690051 ps
CPU time 0.84 seconds
Started Jun 28 06:14:49 PM PDT 24
Finished Jun 28 06:14:55 PM PDT 24
Peak memory 206192 kb
Host smart-1e4f051c-e8b9-4a85-836f-a4117341590d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38182
66698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.3818266698
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.792264099
Short name T440
Test name
Test status
Simulation time 170555475 ps
CPU time 0.81 seconds
Started Jun 28 06:14:48 PM PDT 24
Finished Jun 28 06:14:54 PM PDT 24
Peak memory 206180 kb
Host smart-94195b98-3fa0-44f8-b447-9391afbfa5e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79226
4099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.792264099
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.1558600838
Short name T2479
Test name
Test status
Simulation time 185816842 ps
CPU time 0.82 seconds
Started Jun 28 06:14:45 PM PDT 24
Finished Jun 28 06:14:50 PM PDT 24
Peak memory 206196 kb
Host smart-a18b071b-7251-422e-b1a9-de5602576b29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15586
00838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.1558600838
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.4186500346
Short name T1433
Test name
Test status
Simulation time 159515209 ps
CPU time 0.79 seconds
Started Jun 28 06:14:48 PM PDT 24
Finished Jun 28 06:14:53 PM PDT 24
Peak memory 206192 kb
Host smart-0e627a90-67c1-4b9c-bb13-925ff4bb016f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41865
00346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.4186500346
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.3646965816
Short name T1116
Test name
Test status
Simulation time 217581661 ps
CPU time 0.85 seconds
Started Jun 28 06:14:45 PM PDT 24
Finished Jun 28 06:14:50 PM PDT 24
Peak memory 206168 kb
Host smart-88405e95-3443-4580-8c2c-b38d431f4378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36469
65816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.3646965816
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.2035436224
Short name T410
Test name
Test status
Simulation time 214814277 ps
CPU time 1.06 seconds
Started Jun 28 06:14:42 PM PDT 24
Finished Jun 28 06:14:46 PM PDT 24
Peak memory 206212 kb
Host smart-0868bb58-ea7f-43b1-81c7-a51dedd708dd
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2035436224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.2035436224
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.4150731265
Short name T199
Test name
Test status
Simulation time 157286207 ps
CPU time 0.8 seconds
Started Jun 28 06:14:48 PM PDT 24
Finished Jun 28 06:14:54 PM PDT 24
Peak memory 206192 kb
Host smart-6cda15f8-d089-4a5c-b727-65732555ca00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41507
31265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.4150731265
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.3482652867
Short name T2449
Test name
Test status
Simulation time 75331899 ps
CPU time 0.69 seconds
Started Jun 28 06:14:36 PM PDT 24
Finished Jun 28 06:14:38 PM PDT 24
Peak memory 206208 kb
Host smart-b26cef27-abaf-428d-b78e-c129b4769ed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34826
52867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.3482652867
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.1673638585
Short name T78
Test name
Test status
Simulation time 13532325838 ps
CPU time 31.89 seconds
Started Jun 28 06:14:40 PM PDT 24
Finished Jun 28 06:15:13 PM PDT 24
Peak memory 206508 kb
Host smart-2b50ae31-4f8e-4b75-82c5-212a51f7f010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16736
38585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.1673638585
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.1970009164
Short name T713
Test name
Test status
Simulation time 225598903 ps
CPU time 0.87 seconds
Started Jun 28 06:14:40 PM PDT 24
Finished Jun 28 06:14:43 PM PDT 24
Peak memory 206192 kb
Host smart-170ce266-6921-43c4-908a-71458f22ade8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19700
09164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.1970009164
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.3012312658
Short name T823
Test name
Test status
Simulation time 290491717 ps
CPU time 0.94 seconds
Started Jun 28 06:14:38 PM PDT 24
Finished Jun 28 06:14:40 PM PDT 24
Peak memory 206204 kb
Host smart-77a1b45c-bc17-4e3d-8705-2fa678a76c74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30123
12658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.3012312658
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.403569067
Short name T2362
Test name
Test status
Simulation time 223507316 ps
CPU time 0.86 seconds
Started Jun 28 06:14:47 PM PDT 24
Finished Jun 28 06:14:53 PM PDT 24
Peak memory 206148 kb
Host smart-d15105e3-34f5-40d8-9937-b7d1e2430acb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40356
9067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.403569067
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.3814392584
Short name T801
Test name
Test status
Simulation time 179870769 ps
CPU time 0.82 seconds
Started Jun 28 06:14:46 PM PDT 24
Finished Jun 28 06:14:51 PM PDT 24
Peak memory 206124 kb
Host smart-472c64d4-fb2d-4667-a465-7b7f48543a1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38143
92584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.3814392584
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.1970046556
Short name T1689
Test name
Test status
Simulation time 158693928 ps
CPU time 0.8 seconds
Started Jun 28 06:14:38 PM PDT 24
Finished Jun 28 06:14:40 PM PDT 24
Peak memory 206192 kb
Host smart-51b13e70-ee85-420d-b6e4-23916230f7a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19700
46556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.1970046556
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.2545502250
Short name T1871
Test name
Test status
Simulation time 148112689 ps
CPU time 0.77 seconds
Started Jun 28 06:14:49 PM PDT 24
Finished Jun 28 06:14:55 PM PDT 24
Peak memory 206116 kb
Host smart-3081dd06-127b-44a2-80b2-570242f15a77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25455
02250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.2545502250
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.537131292
Short name T1628
Test name
Test status
Simulation time 178103700 ps
CPU time 0.84 seconds
Started Jun 28 06:14:49 PM PDT 24
Finished Jun 28 06:14:55 PM PDT 24
Peak memory 206184 kb
Host smart-529ca82c-4cfd-4f96-87cb-82b704bee76d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53713
1292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.537131292
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.3684963446
Short name T2513
Test name
Test status
Simulation time 192940073 ps
CPU time 0.92 seconds
Started Jun 28 06:14:41 PM PDT 24
Finished Jun 28 06:14:44 PM PDT 24
Peak memory 206216 kb
Host smart-5b90cac7-0036-48ad-9e81-573a13d4d67b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36849
63446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.3684963446
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.3252923101
Short name T1170
Test name
Test status
Simulation time 6352844211 ps
CPU time 44.76 seconds
Started Jun 28 06:14:47 PM PDT 24
Finished Jun 28 06:15:37 PM PDT 24
Peak memory 206388 kb
Host smart-b89b8318-2908-42da-95ac-95685b5ac01d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3252923101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.3252923101
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.3869808727
Short name T1459
Test name
Test status
Simulation time 236398046 ps
CPU time 0.86 seconds
Started Jun 28 06:14:39 PM PDT 24
Finished Jun 28 06:14:42 PM PDT 24
Peak memory 206224 kb
Host smart-fbffda2d-7297-4883-9b6c-1be956a1fc18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38698
08727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.3869808727
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.3616198635
Short name T1666
Test name
Test status
Simulation time 146061951 ps
CPU time 0.77 seconds
Started Jun 28 06:14:46 PM PDT 24
Finished Jun 28 06:14:51 PM PDT 24
Peak memory 206176 kb
Host smart-df62763b-f9ea-4662-9bea-a9b3ce7cbaaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36161
98635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.3616198635
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.2110022223
Short name T890
Test name
Test status
Simulation time 3208137837 ps
CPU time 87.68 seconds
Started Jun 28 06:14:49 PM PDT 24
Finished Jun 28 06:16:22 PM PDT 24
Peak memory 206432 kb
Host smart-c1dfd423-6b41-4ae7-bef3-3cca9d9fc601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21100
22223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.2110022223
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.1331281165
Short name T2106
Test name
Test status
Simulation time 47015624 ps
CPU time 0.75 seconds
Started Jun 28 06:14:58 PM PDT 24
Finished Jun 28 06:15:02 PM PDT 24
Peak memory 206208 kb
Host smart-12ee2a32-0a7b-4819-bce2-a8fe9c585249
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1331281165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.1331281165
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.970596434
Short name T817
Test name
Test status
Simulation time 3617221034 ps
CPU time 4.29 seconds
Started Jun 28 06:14:46 PM PDT 24
Finished Jun 28 06:14:56 PM PDT 24
Peak memory 206284 kb
Host smart-11ad3ae5-acc6-4a0e-a84c-975c9d24f41a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=970596434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.970596434
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.603610574
Short name T391
Test name
Test status
Simulation time 13358822973 ps
CPU time 13.04 seconds
Started Jun 28 06:14:47 PM PDT 24
Finished Jun 28 06:15:05 PM PDT 24
Peak memory 206348 kb
Host smart-46f33a4d-3697-41ce-9f48-1644b7c3be37
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=603610574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.603610574
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.4152076815
Short name T2549
Test name
Test status
Simulation time 23408041363 ps
CPU time 25.21 seconds
Started Jun 28 06:14:49 PM PDT 24
Finished Jun 28 06:15:19 PM PDT 24
Peak memory 206256 kb
Host smart-3e144a1a-8ddf-4afd-b553-c415ddc30fda
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4152076815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.4152076815
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.45376068
Short name T1392
Test name
Test status
Simulation time 159767678 ps
CPU time 0.84 seconds
Started Jun 28 06:14:44 PM PDT 24
Finished Jun 28 06:14:48 PM PDT 24
Peak memory 206208 kb
Host smart-2812a931-fb7b-4cb5-af85-a9cbba9380e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45376
068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.45376068
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.2531938413
Short name T1908
Test name
Test status
Simulation time 154287306 ps
CPU time 0.8 seconds
Started Jun 28 06:14:45 PM PDT 24
Finished Jun 28 06:14:50 PM PDT 24
Peak memory 206204 kb
Host smart-cdf2f998-9770-40b0-b512-fee715ab8409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25319
38413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.2531938413
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.4200998622
Short name T187
Test name
Test status
Simulation time 367247742 ps
CPU time 1.35 seconds
Started Jun 28 06:14:43 PM PDT 24
Finished Jun 28 06:14:48 PM PDT 24
Peak memory 206188 kb
Host smart-398affea-083a-4316-afa4-781c493325d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42009
98622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.4200998622
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.930859766
Short name T160
Test name
Test status
Simulation time 1152252759 ps
CPU time 2.9 seconds
Started Jun 28 06:14:45 PM PDT 24
Finished Jun 28 06:14:52 PM PDT 24
Peak memory 206264 kb
Host smart-325fe3d4-47b1-420f-98b2-0450b782d528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93085
9766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.930859766
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.2471268814
Short name T2487
Test name
Test status
Simulation time 14333479551 ps
CPU time 27.38 seconds
Started Jun 28 06:14:43 PM PDT 24
Finished Jun 28 06:15:14 PM PDT 24
Peak memory 206424 kb
Host smart-a282e5b4-a3ba-4734-a760-af6caed8b56d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24712
68814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.2471268814
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.3084115311
Short name T1176
Test name
Test status
Simulation time 457690585 ps
CPU time 1.41 seconds
Started Jun 28 06:14:47 PM PDT 24
Finished Jun 28 06:14:53 PM PDT 24
Peak memory 206124 kb
Host smart-cc76c12f-1bd3-4a03-9403-8192b5e2c7e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30841
15311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.3084115311
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.1838028879
Short name T1415
Test name
Test status
Simulation time 149754739 ps
CPU time 0.88 seconds
Started Jun 28 06:14:43 PM PDT 24
Finished Jun 28 06:14:47 PM PDT 24
Peak memory 206188 kb
Host smart-9a9095fa-23da-4d21-b4ad-12b385c78a51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18380
28879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.1838028879
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.1307567274
Short name T885
Test name
Test status
Simulation time 55829043 ps
CPU time 0.65 seconds
Started Jun 28 06:14:38 PM PDT 24
Finished Jun 28 06:14:40 PM PDT 24
Peak memory 206184 kb
Host smart-dc513eb2-f251-40da-88f0-6e4f974f8cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13075
67274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.1307567274
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.3818266433
Short name T2103
Test name
Test status
Simulation time 886004193 ps
CPU time 2.14 seconds
Started Jun 28 06:14:43 PM PDT 24
Finished Jun 28 06:14:49 PM PDT 24
Peak memory 206296 kb
Host smart-0be47144-8e63-46c6-a170-1da699a4a39e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38182
66433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.3818266433
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.3551656058
Short name T952
Test name
Test status
Simulation time 162329816 ps
CPU time 1.58 seconds
Started Jun 28 06:14:56 PM PDT 24
Finished Jun 28 06:15:01 PM PDT 24
Peak memory 206220 kb
Host smart-0e477fd1-d04d-41df-88f7-12c0944b1540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35516
56058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.3551656058
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.3121036450
Short name T551
Test name
Test status
Simulation time 187111099 ps
CPU time 0.88 seconds
Started Jun 28 06:14:50 PM PDT 24
Finished Jun 28 06:14:55 PM PDT 24
Peak memory 206188 kb
Host smart-eadb3087-ac61-45f4-ba77-df4234e973b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31210
36450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.3121036450
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.163005118
Short name T1803
Test name
Test status
Simulation time 167608726 ps
CPU time 0.79 seconds
Started Jun 28 06:14:41 PM PDT 24
Finished Jun 28 06:14:45 PM PDT 24
Peak memory 206208 kb
Host smart-4f03334b-49be-47a7-9de0-980fcb9f9e95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16300
5118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.163005118
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.3020236655
Short name T633
Test name
Test status
Simulation time 197497779 ps
CPU time 0.89 seconds
Started Jun 28 06:14:51 PM PDT 24
Finished Jun 28 06:14:56 PM PDT 24
Peak memory 206064 kb
Host smart-caba5bd3-1a89-49bf-b16d-55e3f5172d16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30202
36655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.3020236655
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.1191696731
Short name T106
Test name
Test status
Simulation time 224877406 ps
CPU time 0.94 seconds
Started Jun 28 06:14:40 PM PDT 24
Finished Jun 28 06:14:43 PM PDT 24
Peak memory 206188 kb
Host smart-314263d0-42f3-4069-8387-fff4487ef6cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11916
96731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.1191696731
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.2899879455
Short name T1471
Test name
Test status
Simulation time 23354303773 ps
CPU time 25.96 seconds
Started Jun 28 06:14:52 PM PDT 24
Finished Jun 28 06:15:22 PM PDT 24
Peak memory 206272 kb
Host smart-eb48df7a-b311-4e5a-a2ab-7303ad39dd23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28998
79455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.2899879455
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.1819506934
Short name T822
Test name
Test status
Simulation time 3268948838 ps
CPU time 4.25 seconds
Started Jun 28 06:14:41 PM PDT 24
Finished Jun 28 06:14:48 PM PDT 24
Peak memory 206256 kb
Host smart-df72889b-1aeb-437b-a2eb-66e2f6d6f632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18195
06934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.1819506934
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.2630257757
Short name T75
Test name
Test status
Simulation time 9281450264 ps
CPU time 239.62 seconds
Started Jun 28 06:14:42 PM PDT 24
Finished Jun 28 06:18:45 PM PDT 24
Peak memory 206440 kb
Host smart-8b48a0b8-4373-4b15-9124-51a774b039bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26302
57757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.2630257757
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.3511944710
Short name T1726
Test name
Test status
Simulation time 5298553975 ps
CPU time 38.63 seconds
Started Jun 28 06:14:40 PM PDT 24
Finished Jun 28 06:15:21 PM PDT 24
Peak memory 206444 kb
Host smart-d2b50694-ec0a-4b60-853e-8c31085acbe5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3511944710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.3511944710
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.3586081556
Short name T1231
Test name
Test status
Simulation time 239793011 ps
CPU time 0.89 seconds
Started Jun 28 06:14:52 PM PDT 24
Finished Jun 28 06:14:57 PM PDT 24
Peak memory 206180 kb
Host smart-58e75b80-940d-4e4e-89e7-35d72e607475
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3586081556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.3586081556
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.2939500931
Short name T1368
Test name
Test status
Simulation time 194617550 ps
CPU time 0.86 seconds
Started Jun 28 06:14:58 PM PDT 24
Finished Jun 28 06:15:03 PM PDT 24
Peak memory 206164 kb
Host smart-1acfd710-2974-4f29-bd2d-41e1003d8e52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29395
00931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.2939500931
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.4066117165
Short name T2545
Test name
Test status
Simulation time 4960873962 ps
CPU time 143.82 seconds
Started Jun 28 06:14:42 PM PDT 24
Finished Jun 28 06:17:10 PM PDT 24
Peak memory 206460 kb
Host smart-04a01195-25e5-4335-99d1-257bc5393eac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40661
17165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.4066117165
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.1974963241
Short name T1799
Test name
Test status
Simulation time 4588381260 ps
CPU time 43.19 seconds
Started Jun 28 06:14:43 PM PDT 24
Finished Jun 28 06:15:30 PM PDT 24
Peak memory 206404 kb
Host smart-73e940db-a39a-4fc7-a387-4d8241cb15ff
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1974963241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.1974963241
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.2824692869
Short name T1389
Test name
Test status
Simulation time 147330000 ps
CPU time 0.78 seconds
Started Jun 28 06:14:43 PM PDT 24
Finished Jun 28 06:14:47 PM PDT 24
Peak memory 206220 kb
Host smart-566e0ec6-f709-4337-8805-8122ee238213
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2824692869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.2824692869
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.1339485646
Short name T326
Test name
Test status
Simulation time 162355240 ps
CPU time 0.8 seconds
Started Jun 28 06:14:53 PM PDT 24
Finished Jun 28 06:14:57 PM PDT 24
Peak memory 206200 kb
Host smart-6b1d8098-d31d-4f3d-812f-7c6538bdfeb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13394
85646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.1339485646
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.558056097
Short name T135
Test name
Test status
Simulation time 196716792 ps
CPU time 0.81 seconds
Started Jun 28 06:14:51 PM PDT 24
Finished Jun 28 06:14:56 PM PDT 24
Peak memory 206156 kb
Host smart-bad09d0d-a5bf-4bfb-88a9-695fd3fa93cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55805
6097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.558056097
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.878050150
Short name T1782
Test name
Test status
Simulation time 161887653 ps
CPU time 0.82 seconds
Started Jun 28 06:14:44 PM PDT 24
Finished Jun 28 06:14:48 PM PDT 24
Peak memory 206140 kb
Host smart-77bae88d-c9c4-46d3-8161-e6ba61805c5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87805
0150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.878050150
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.2813266179
Short name T2003
Test name
Test status
Simulation time 178398127 ps
CPU time 0.86 seconds
Started Jun 28 06:14:44 PM PDT 24
Finished Jun 28 06:14:49 PM PDT 24
Peak memory 206144 kb
Host smart-d315c88d-64c0-434a-8be4-6fcb5c517aba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28132
66179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.2813266179
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.3283263623
Short name T969
Test name
Test status
Simulation time 187194557 ps
CPU time 0.83 seconds
Started Jun 28 06:14:57 PM PDT 24
Finished Jun 28 06:15:02 PM PDT 24
Peak memory 206208 kb
Host smart-b7b1e4cd-34a7-4f2b-b020-4ddeb1c34409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32832
63623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.3283263623
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.2835125444
Short name T156
Test name
Test status
Simulation time 167322200 ps
CPU time 0.85 seconds
Started Jun 28 06:14:47 PM PDT 24
Finished Jun 28 06:14:53 PM PDT 24
Peak memory 206196 kb
Host smart-29404b12-0806-4dfd-b057-4566e708f58b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28351
25444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.2835125444
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.4100527922
Short name T2257
Test name
Test status
Simulation time 219268474 ps
CPU time 1.01 seconds
Started Jun 28 06:14:51 PM PDT 24
Finished Jun 28 06:14:56 PM PDT 24
Peak memory 206192 kb
Host smart-8ca423ef-7191-48f6-8b1a-d46aec479d62
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4100527922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.4100527922
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.3256370886
Short name T1075
Test name
Test status
Simulation time 156445863 ps
CPU time 0.73 seconds
Started Jun 28 06:14:52 PM PDT 24
Finished Jun 28 06:14:56 PM PDT 24
Peak memory 206160 kb
Host smart-90075cc6-b63a-4012-afcf-8434b9e65ed1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32563
70886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.3256370886
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.224747309
Short name T1011
Test name
Test status
Simulation time 34677964 ps
CPU time 0.68 seconds
Started Jun 28 06:14:54 PM PDT 24
Finished Jun 28 06:14:58 PM PDT 24
Peak memory 206192 kb
Host smart-c7340763-111f-4175-84e2-0507d32e4ecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22474
7309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.224747309
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.1228124105
Short name T2097
Test name
Test status
Simulation time 18527360973 ps
CPU time 47.21 seconds
Started Jun 28 06:14:53 PM PDT 24
Finished Jun 28 06:15:44 PM PDT 24
Peak memory 206460 kb
Host smart-9b63f25d-ff82-480b-acdf-3774f239f793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12281
24105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.1228124105
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.1681890520
Short name T1349
Test name
Test status
Simulation time 171528736 ps
CPU time 0.93 seconds
Started Jun 28 06:14:54 PM PDT 24
Finished Jun 28 06:14:58 PM PDT 24
Peak memory 206184 kb
Host smart-078467f6-a2b7-44c9-a774-837e2952c4bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16818
90520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.1681890520
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.408322916
Short name T897
Test name
Test status
Simulation time 222582133 ps
CPU time 0.88 seconds
Started Jun 28 06:14:54 PM PDT 24
Finished Jun 28 06:14:58 PM PDT 24
Peak memory 206200 kb
Host smart-b72a7862-dace-4b6d-82e8-ea01ad1300fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40832
2916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.408322916
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.1785473920
Short name T1303
Test name
Test status
Simulation time 194142405 ps
CPU time 0.87 seconds
Started Jun 28 06:14:48 PM PDT 24
Finished Jun 28 06:14:53 PM PDT 24
Peak memory 206224 kb
Host smart-cdc51c81-de63-4609-82c4-452a075551a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17854
73920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.1785473920
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.996356219
Short name T1504
Test name
Test status
Simulation time 173406578 ps
CPU time 0.78 seconds
Started Jun 28 06:14:45 PM PDT 24
Finished Jun 28 06:14:50 PM PDT 24
Peak memory 206192 kb
Host smart-4a6009e8-5856-4a34-9735-bd52fb93261d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99635
6219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.996356219
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.3496397796
Short name T67
Test name
Test status
Simulation time 224107384 ps
CPU time 0.89 seconds
Started Jun 28 06:15:03 PM PDT 24
Finished Jun 28 06:15:07 PM PDT 24
Peak memory 206104 kb
Host smart-ff3f47a0-b578-4307-a4f3-2b1688fe8354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34963
97796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.3496397796
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.3933895756
Short name T2178
Test name
Test status
Simulation time 165016669 ps
CPU time 0.82 seconds
Started Jun 28 06:14:49 PM PDT 24
Finished Jun 28 06:14:55 PM PDT 24
Peak memory 206192 kb
Host smart-96fbfb78-d9a3-44cf-93b3-28f7f9abdac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39338
95756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.3933895756
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.2221788585
Short name T2210
Test name
Test status
Simulation time 143896561 ps
CPU time 0.78 seconds
Started Jun 28 06:14:59 PM PDT 24
Finished Jun 28 06:15:03 PM PDT 24
Peak memory 206160 kb
Host smart-687d4b83-efbe-4374-ae41-dab15b534796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22217
88585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.2221788585
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.4216287854
Short name T1895
Test name
Test status
Simulation time 199203469 ps
CPU time 0.99 seconds
Started Jun 28 06:14:43 PM PDT 24
Finished Jun 28 06:14:48 PM PDT 24
Peak memory 206208 kb
Host smart-da2d3b05-898f-4c1e-881f-6a229ad33290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42162
87854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.4216287854
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.2715347161
Short name T1082
Test name
Test status
Simulation time 3819829441 ps
CPU time 104.82 seconds
Started Jun 28 06:14:59 PM PDT 24
Finished Jun 28 06:16:47 PM PDT 24
Peak memory 206372 kb
Host smart-96ced31a-1015-4d82-a4c8-8cd60f929796
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2715347161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.2715347161
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.1157729581
Short name T2026
Test name
Test status
Simulation time 231638403 ps
CPU time 0.96 seconds
Started Jun 28 06:14:44 PM PDT 24
Finished Jun 28 06:14:49 PM PDT 24
Peak memory 206196 kb
Host smart-737dc854-e768-405d-a175-18f94497d89c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11577
29581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.1157729581
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.3199386304
Short name T1935
Test name
Test status
Simulation time 147919759 ps
CPU time 0.81 seconds
Started Jun 28 06:14:55 PM PDT 24
Finished Jun 28 06:15:00 PM PDT 24
Peak memory 206180 kb
Host smart-b1ea1038-98a2-45a5-b4a5-9541414b90f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31993
86304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.3199386304
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.2798971103
Short name T907
Test name
Test status
Simulation time 6962753267 ps
CPU time 67.3 seconds
Started Jun 28 06:14:51 PM PDT 24
Finished Jun 28 06:16:02 PM PDT 24
Peak memory 206396 kb
Host smart-39b83d67-1034-41d9-a3a8-99f2cd7d23dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27989
71103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.2798971103
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.2710921703
Short name T953
Test name
Test status
Simulation time 38457647 ps
CPU time 0.69 seconds
Started Jun 28 06:14:45 PM PDT 24
Finished Jun 28 06:14:50 PM PDT 24
Peak memory 206200 kb
Host smart-384c9d5f-2f8f-4d27-8eec-122358e7319e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2710921703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.2710921703
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.1850908800
Short name T967
Test name
Test status
Simulation time 3562946405 ps
CPU time 4.1 seconds
Started Jun 28 06:14:58 PM PDT 24
Finished Jun 28 06:15:06 PM PDT 24
Peak memory 206164 kb
Host smart-ced50338-6991-43b3-8035-70b62dbe6e1c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1850908800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.1850908800
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.1663023312
Short name T1894
Test name
Test status
Simulation time 13417452555 ps
CPU time 16.23 seconds
Started Jun 28 06:14:44 PM PDT 24
Finished Jun 28 06:15:04 PM PDT 24
Peak memory 206428 kb
Host smart-7d9a5e75-baac-409d-a0ae-7dc74cee2253
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1663023312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.1663023312
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.3226730340
Short name T575
Test name
Test status
Simulation time 23375060340 ps
CPU time 23.68 seconds
Started Jun 28 06:15:00 PM PDT 24
Finished Jun 28 06:15:27 PM PDT 24
Peak memory 206308 kb
Host smart-22e506dd-c8cb-443f-8c5a-c5ee0ec4c50c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3226730340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.3226730340
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.3172577897
Short name T2270
Test name
Test status
Simulation time 151852902 ps
CPU time 0.79 seconds
Started Jun 28 06:14:45 PM PDT 24
Finished Jun 28 06:14:50 PM PDT 24
Peak memory 206168 kb
Host smart-9bdb6a6e-5bc4-4c8b-8aec-23f8730c44d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31725
77897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.3172577897
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.3125470331
Short name T875
Test name
Test status
Simulation time 142603927 ps
CPU time 0.76 seconds
Started Jun 28 06:14:59 PM PDT 24
Finished Jun 28 06:15:07 PM PDT 24
Peak memory 206136 kb
Host smart-171c7c82-bf26-440e-a74f-cea7361a8613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31254
70331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.3125470331
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.470678948
Short name T2169
Test name
Test status
Simulation time 179230086 ps
CPU time 0.88 seconds
Started Jun 28 06:14:59 PM PDT 24
Finished Jun 28 06:15:03 PM PDT 24
Peak memory 206160 kb
Host smart-012f6791-a89f-4058-a136-06967266c972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47067
8948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.470678948
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.395827183
Short name T1418
Test name
Test status
Simulation time 945461664 ps
CPU time 2.44 seconds
Started Jun 28 06:14:59 PM PDT 24
Finished Jun 28 06:15:05 PM PDT 24
Peak memory 206344 kb
Host smart-6999c1f3-0c7a-486a-a761-a475a0c1f388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39582
7183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.395827183
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.3546209882
Short name T2412
Test name
Test status
Simulation time 8890545046 ps
CPU time 17.71 seconds
Started Jun 28 06:14:56 PM PDT 24
Finished Jun 28 06:15:17 PM PDT 24
Peak memory 206388 kb
Host smart-6e1434bf-3217-44c4-a913-8e9389785e0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35462
09882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.3546209882
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.394386916
Short name T793
Test name
Test status
Simulation time 394546671 ps
CPU time 1.29 seconds
Started Jun 28 06:14:58 PM PDT 24
Finished Jun 28 06:15:02 PM PDT 24
Peak memory 206208 kb
Host smart-ec9f6fe7-96bb-4698-9456-7c67a2818717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39438
6916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.394386916
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.915205866
Short name T1720
Test name
Test status
Simulation time 178975473 ps
CPU time 0.85 seconds
Started Jun 28 06:14:54 PM PDT 24
Finished Jun 28 06:14:58 PM PDT 24
Peak memory 206196 kb
Host smart-bdc9a9db-7f60-433d-92a0-6f366f765d28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91520
5866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.915205866
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.810943289
Short name T2313
Test name
Test status
Simulation time 29650372 ps
CPU time 0.67 seconds
Started Jun 28 06:14:45 PM PDT 24
Finished Jun 28 06:14:50 PM PDT 24
Peak memory 206156 kb
Host smart-73d63914-c396-4699-9dc3-5fdd5b3281f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81094
3289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.810943289
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.1294738538
Short name T880
Test name
Test status
Simulation time 905401435 ps
CPU time 2.13 seconds
Started Jun 28 06:15:03 PM PDT 24
Finished Jun 28 06:15:08 PM PDT 24
Peak memory 206316 kb
Host smart-100dbb05-d07d-4a20-b51d-786527919fbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12947
38538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.1294738538
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.1414261840
Short name T1971
Test name
Test status
Simulation time 316603322 ps
CPU time 2.4 seconds
Started Jun 28 06:14:58 PM PDT 24
Finished Jun 28 06:15:04 PM PDT 24
Peak memory 206168 kb
Host smart-95731340-e783-40dd-ba11-aa1882abed33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14142
61840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.1414261840
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.665432562
Short name T1026
Test name
Test status
Simulation time 231627993 ps
CPU time 0.97 seconds
Started Jun 28 06:14:46 PM PDT 24
Finished Jun 28 06:14:51 PM PDT 24
Peak memory 206180 kb
Host smart-b57a9920-510a-43a5-9fc4-f04b3a05ca39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66543
2562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.665432562
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.2379520891
Short name T2446
Test name
Test status
Simulation time 155197965 ps
CPU time 0.81 seconds
Started Jun 28 06:14:45 PM PDT 24
Finished Jun 28 06:14:51 PM PDT 24
Peak memory 206100 kb
Host smart-22f01da5-ebad-48f0-86d1-6973c5a97eb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23795
20891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.2379520891
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.638011611
Short name T1696
Test name
Test status
Simulation time 240175683 ps
CPU time 0.96 seconds
Started Jun 28 06:14:54 PM PDT 24
Finished Jun 28 06:14:58 PM PDT 24
Peak memory 206204 kb
Host smart-d2e6064e-38a1-4fc7-93b4-8b40300fad65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63801
1611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.638011611
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.109291713
Short name T1617
Test name
Test status
Simulation time 231958197 ps
CPU time 0.9 seconds
Started Jun 28 06:14:58 PM PDT 24
Finished Jun 28 06:15:02 PM PDT 24
Peak memory 206128 kb
Host smart-9c159639-dc70-415d-89d0-b0b8e6b5c1a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10929
1713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.109291713
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.1050701925
Short name T1357
Test name
Test status
Simulation time 23315128215 ps
CPU time 24.26 seconds
Started Jun 28 06:14:44 PM PDT 24
Finished Jun 28 06:15:12 PM PDT 24
Peak memory 206284 kb
Host smart-e8f6af62-9f30-44c6-8eab-f2964685159f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10507
01925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.1050701925
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.3437489264
Short name T2515
Test name
Test status
Simulation time 3353642087 ps
CPU time 3.78 seconds
Started Jun 28 06:14:46 PM PDT 24
Finished Jun 28 06:14:54 PM PDT 24
Peak memory 206192 kb
Host smart-bc19e05a-8ab4-4fb7-98be-9fe5f0390525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34374
89264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.3437489264
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.4263057494
Short name T464
Test name
Test status
Simulation time 8774530781 ps
CPU time 81.93 seconds
Started Jun 28 06:14:44 PM PDT 24
Finished Jun 28 06:16:09 PM PDT 24
Peak memory 206424 kb
Host smart-7e4150e9-09f5-4ded-a8b9-6ddf6332aa4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42630
57494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.4263057494
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.1034344330
Short name T920
Test name
Test status
Simulation time 5025420939 ps
CPU time 135.26 seconds
Started Jun 28 06:14:45 PM PDT 24
Finished Jun 28 06:17:05 PM PDT 24
Peak memory 206428 kb
Host smart-112d34ff-c905-45c8-a277-2553b197809f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1034344330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.1034344330
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.3753549130
Short name T429
Test name
Test status
Simulation time 244862446 ps
CPU time 0.93 seconds
Started Jun 28 06:14:52 PM PDT 24
Finished Jun 28 06:14:57 PM PDT 24
Peak memory 206208 kb
Host smart-daa07abd-4dda-4b06-b8ec-8c0cf5a0f951
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3753549130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.3753549130
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.4186489014
Short name T2522
Test name
Test status
Simulation time 194407085 ps
CPU time 0.87 seconds
Started Jun 28 06:14:47 PM PDT 24
Finished Jun 28 06:14:53 PM PDT 24
Peak memory 206204 kb
Host smart-f226afb7-8c07-4142-bf22-c9f7c03c4d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41864
89014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.4186489014
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.2878422989
Short name T692
Test name
Test status
Simulation time 5912721743 ps
CPU time 43.89 seconds
Started Jun 28 06:14:46 PM PDT 24
Finished Jun 28 06:15:34 PM PDT 24
Peak memory 206372 kb
Host smart-8355c306-8c16-4736-9f6e-800606761728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28784
22989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.2878422989
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.2591420467
Short name T2199
Test name
Test status
Simulation time 5649748122 ps
CPU time 54.27 seconds
Started Jun 28 06:15:03 PM PDT 24
Finished Jun 28 06:16:00 PM PDT 24
Peak memory 206408 kb
Host smart-50f922d2-ae0c-4ea9-bf57-942620494ffe
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2591420467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.2591420467
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.2988457923
Short name T2544
Test name
Test status
Simulation time 223881247 ps
CPU time 0.83 seconds
Started Jun 28 06:14:45 PM PDT 24
Finished Jun 28 06:14:51 PM PDT 24
Peak memory 206212 kb
Host smart-ee488bd1-e56f-4db0-80d4-c83947127411
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2988457923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.2988457923
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.4264672026
Short name T2082
Test name
Test status
Simulation time 177898583 ps
CPU time 0.8 seconds
Started Jun 28 06:14:58 PM PDT 24
Finished Jun 28 06:15:02 PM PDT 24
Peak memory 206196 kb
Host smart-2815abdd-6b3a-4bbe-9257-689706f1bf9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42646
72026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.4264672026
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.272759107
Short name T2310
Test name
Test status
Simulation time 205566989 ps
CPU time 0.89 seconds
Started Jun 28 06:14:47 PM PDT 24
Finished Jun 28 06:14:53 PM PDT 24
Peak memory 206216 kb
Host smart-9005bba1-15fc-4c19-9164-484c46ca2cc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27275
9107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.272759107
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.801379372
Short name T602
Test name
Test status
Simulation time 174785876 ps
CPU time 0.82 seconds
Started Jun 28 06:14:59 PM PDT 24
Finished Jun 28 06:15:03 PM PDT 24
Peak memory 206080 kb
Host smart-35a0a832-c59f-4133-8bba-3c0cf591a7bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80137
9372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.801379372
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.3899689142
Short name T2033
Test name
Test status
Simulation time 159224787 ps
CPU time 0.83 seconds
Started Jun 28 06:15:03 PM PDT 24
Finished Jun 28 06:15:06 PM PDT 24
Peak memory 206188 kb
Host smart-82b73261-c164-4588-a302-57f03516348c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38996
89142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.3899689142
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.3351071858
Short name T1194
Test name
Test status
Simulation time 169883272 ps
CPU time 0.8 seconds
Started Jun 28 06:14:46 PM PDT 24
Finished Jun 28 06:14:51 PM PDT 24
Peak memory 206212 kb
Host smart-5620bd32-f062-420b-b0e5-b13c2b45fe89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33510
71858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.3351071858
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.585768495
Short name T498
Test name
Test status
Simulation time 158328687 ps
CPU time 0.79 seconds
Started Jun 28 06:14:59 PM PDT 24
Finished Jun 28 06:15:04 PM PDT 24
Peak memory 206140 kb
Host smart-d351593f-5e44-4e35-9b77-521e7544ce78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58576
8495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.585768495
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.2450677694
Short name T1625
Test name
Test status
Simulation time 217288503 ps
CPU time 0.9 seconds
Started Jun 28 06:14:56 PM PDT 24
Finished Jun 28 06:15:01 PM PDT 24
Peak memory 206152 kb
Host smart-2be59143-fa59-426f-92ef-331bbd2aa604
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2450677694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.2450677694
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.1967443578
Short name T197
Test name
Test status
Simulation time 159015547 ps
CPU time 0.77 seconds
Started Jun 28 06:14:45 PM PDT 24
Finished Jun 28 06:14:50 PM PDT 24
Peak memory 206136 kb
Host smart-6501c6c9-731d-4eb7-a37a-b7d54c3eda5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19674
43578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.1967443578
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.4124590680
Short name T1248
Test name
Test status
Simulation time 56270295 ps
CPU time 0.69 seconds
Started Jun 28 06:14:47 PM PDT 24
Finished Jun 28 06:14:52 PM PDT 24
Peak memory 206204 kb
Host smart-febbedc1-d184-41e2-822a-0528227bed4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41245
90680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.4124590680
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.1408709722
Short name T80
Test name
Test status
Simulation time 6260097556 ps
CPU time 17.24 seconds
Started Jun 28 06:14:45 PM PDT 24
Finished Jun 28 06:15:07 PM PDT 24
Peak memory 206312 kb
Host smart-caf435cc-236c-42b7-ad33-a3f71473a7f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14087
09722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.1408709722
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.1853220432
Short name T2417
Test name
Test status
Simulation time 163489956 ps
CPU time 0.84 seconds
Started Jun 28 06:14:46 PM PDT 24
Finished Jun 28 06:14:51 PM PDT 24
Peak memory 206164 kb
Host smart-fa6979ae-c701-4207-ad4b-f5e1e666d7e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18532
20432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.1853220432
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.3546233805
Short name T2303
Test name
Test status
Simulation time 207388825 ps
CPU time 0.86 seconds
Started Jun 28 06:14:46 PM PDT 24
Finished Jun 28 06:14:52 PM PDT 24
Peak memory 206208 kb
Host smart-5b0c33a2-b3cd-44cd-b95e-7575456ac792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35462
33805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.3546233805
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.3648232688
Short name T2269
Test name
Test status
Simulation time 253196199 ps
CPU time 0.9 seconds
Started Jun 28 06:14:50 PM PDT 24
Finished Jun 28 06:14:56 PM PDT 24
Peak memory 206220 kb
Host smart-65952664-5225-4967-9cc8-0b2cd7a55468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36482
32688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.3648232688
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.689725603
Short name T1644
Test name
Test status
Simulation time 181868933 ps
CPU time 0.93 seconds
Started Jun 28 06:14:47 PM PDT 24
Finished Jun 28 06:14:52 PM PDT 24
Peak memory 206196 kb
Host smart-ffbc96b5-00ec-4eb3-8ea4-aa0e3de1e86a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68972
5603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.689725603
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.766331635
Short name T560
Test name
Test status
Simulation time 207947310 ps
CPU time 0.84 seconds
Started Jun 28 06:14:54 PM PDT 24
Finished Jun 28 06:14:59 PM PDT 24
Peak memory 206188 kb
Host smart-3e6a2514-334f-4968-9778-e18d09f49fec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76633
1635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.766331635
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.2443469799
Short name T1889
Test name
Test status
Simulation time 178857535 ps
CPU time 0.79 seconds
Started Jun 28 06:14:45 PM PDT 24
Finished Jun 28 06:14:51 PM PDT 24
Peak memory 206188 kb
Host smart-e1b7b020-ebd4-4756-a785-534fa889e9ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24434
69799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.2443469799
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.4171893738
Short name T1564
Test name
Test status
Simulation time 149083882 ps
CPU time 0.78 seconds
Started Jun 28 06:15:00 PM PDT 24
Finished Jun 28 06:15:04 PM PDT 24
Peak memory 206188 kb
Host smart-3268b4f2-8a8b-4285-805c-0cb7d7faccc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41718
93738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.4171893738
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.2997042151
Short name T765
Test name
Test status
Simulation time 183956283 ps
CPU time 0.9 seconds
Started Jun 28 06:14:47 PM PDT 24
Finished Jun 28 06:14:53 PM PDT 24
Peak memory 206188 kb
Host smart-a2e41810-433c-4dfe-9fc6-24b068bdbeb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29970
42151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.2997042151
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.246095369
Short name T1233
Test name
Test status
Simulation time 4353969927 ps
CPU time 31.56 seconds
Started Jun 28 06:14:47 PM PDT 24
Finished Jun 28 06:15:23 PM PDT 24
Peak memory 206368 kb
Host smart-004a9519-3e2c-4f08-b0a7-1bca89f580bb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=246095369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.246095369
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.688643320
Short name T1029
Test name
Test status
Simulation time 151705073 ps
CPU time 0.79 seconds
Started Jun 28 06:14:56 PM PDT 24
Finished Jun 28 06:15:00 PM PDT 24
Peak memory 206180 kb
Host smart-1799dd92-5db2-40df-90cd-ad8619aeeeb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68864
3320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.688643320
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.1293213507
Short name T683
Test name
Test status
Simulation time 176179219 ps
CPU time 0.83 seconds
Started Jun 28 06:15:03 PM PDT 24
Finished Jun 28 06:15:06 PM PDT 24
Peak memory 206152 kb
Host smart-a9d7df9f-3b54-46f0-8b26-8eb6d182ad44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12932
13507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.1293213507
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.492947881
Short name T1954
Test name
Test status
Simulation time 5207412813 ps
CPU time 36.12 seconds
Started Jun 28 06:14:57 PM PDT 24
Finished Jun 28 06:15:37 PM PDT 24
Peak memory 206356 kb
Host smart-4a7110ef-813f-4f0a-9406-e541825242f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49294
7881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.492947881
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.1131013010
Short name T193
Test name
Test status
Simulation time 72543872 ps
CPU time 0.7 seconds
Started Jun 28 06:15:03 PM PDT 24
Finished Jun 28 06:15:06 PM PDT 24
Peak memory 206216 kb
Host smart-4e4a6bbe-7f67-493a-8a5f-2f160db02e19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1131013010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.1131013010
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.968709132
Short name T1033
Test name
Test status
Simulation time 3559278190 ps
CPU time 4.69 seconds
Started Jun 28 06:14:57 PM PDT 24
Finished Jun 28 06:15:05 PM PDT 24
Peak memory 206284 kb
Host smart-f0f0c69a-5e8d-4299-af55-6b00b8a51c94
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=968709132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.968709132
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.769606146
Short name T2530
Test name
Test status
Simulation time 13436649660 ps
CPU time 13.31 seconds
Started Jun 28 06:14:58 PM PDT 24
Finished Jun 28 06:15:14 PM PDT 24
Peak memory 206416 kb
Host smart-2105fc08-f39a-4924-8033-379dc55a4cc7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=769606146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.769606146
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.593340073
Short name T666
Test name
Test status
Simulation time 23350427734 ps
CPU time 24.98 seconds
Started Jun 28 06:14:57 PM PDT 24
Finished Jun 28 06:15:26 PM PDT 24
Peak memory 206320 kb
Host smart-7d18a509-e80f-4917-8f9c-49969e478912
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=593340073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.593340073
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.10265027
Short name T1765
Test name
Test status
Simulation time 163834698 ps
CPU time 0.78 seconds
Started Jun 28 06:14:57 PM PDT 24
Finished Jun 28 06:15:02 PM PDT 24
Peak memory 206212 kb
Host smart-d80e4968-cb6a-4878-a750-09fe45048e4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10265
027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.10265027
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.1367452629
Short name T866
Test name
Test status
Simulation time 162761873 ps
CPU time 0.81 seconds
Started Jun 28 06:14:58 PM PDT 24
Finished Jun 28 06:15:03 PM PDT 24
Peak memory 206192 kb
Host smart-1b77c35f-5aef-464a-a1db-d8e81911e882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13674
52629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.1367452629
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.713087451
Short name T1758
Test name
Test status
Simulation time 430360191 ps
CPU time 1.38 seconds
Started Jun 28 06:15:00 PM PDT 24
Finished Jun 28 06:15:04 PM PDT 24
Peak memory 206196 kb
Host smart-49ff6f68-abce-43bf-a7e0-4a344a93904f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71308
7451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.713087451
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.3203779980
Short name T1863
Test name
Test status
Simulation time 1033230923 ps
CPU time 2.35 seconds
Started Jun 28 06:14:57 PM PDT 24
Finished Jun 28 06:15:03 PM PDT 24
Peak memory 206272 kb
Host smart-33fbd9f8-c9dc-40d5-8aa0-b4c6d98b59a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32037
79980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.3203779980
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.2746441076
Short name T2277
Test name
Test status
Simulation time 22489466742 ps
CPU time 41.96 seconds
Started Jun 28 06:14:59 PM PDT 24
Finished Jun 28 06:15:44 PM PDT 24
Peak memory 206440 kb
Host smart-aed01455-c293-4725-b780-1f118868a83c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27464
41076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.2746441076
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.2011773259
Short name T1708
Test name
Test status
Simulation time 357366918 ps
CPU time 1.22 seconds
Started Jun 28 06:14:58 PM PDT 24
Finished Jun 28 06:15:02 PM PDT 24
Peak memory 206200 kb
Host smart-f1d7418e-4cdd-4d61-892a-e2058482959f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20117
73259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.2011773259
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.3865400861
Short name T1018
Test name
Test status
Simulation time 144691411 ps
CPU time 0.78 seconds
Started Jun 28 06:15:11 PM PDT 24
Finished Jun 28 06:15:15 PM PDT 24
Peak memory 206196 kb
Host smart-fc683df1-6bc1-463b-adec-b45c940f01a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38654
00861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.3865400861
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.239006906
Short name T1942
Test name
Test status
Simulation time 51321558 ps
CPU time 0.73 seconds
Started Jun 28 06:14:58 PM PDT 24
Finished Jun 28 06:15:02 PM PDT 24
Peak memory 206128 kb
Host smart-ad26f425-4d50-4c8c-8054-e265b9deb4dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23900
6906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.239006906
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.3106995096
Short name T1652
Test name
Test status
Simulation time 950616102 ps
CPU time 2.04 seconds
Started Jun 28 06:15:17 PM PDT 24
Finished Jun 28 06:15:24 PM PDT 24
Peak memory 206368 kb
Host smart-6e21b22d-cd4c-4135-abfe-1438cd62c995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31069
95096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.3106995096
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.2498714205
Short name T1801
Test name
Test status
Simulation time 332308172 ps
CPU time 2.06 seconds
Started Jun 28 06:15:18 PM PDT 24
Finished Jun 28 06:15:25 PM PDT 24
Peak memory 206264 kb
Host smart-b5726556-16f2-4f43-8647-c9c25521cfc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24987
14205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.2498714205
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.3065831655
Short name T1678
Test name
Test status
Simulation time 291734493 ps
CPU time 1 seconds
Started Jun 28 06:15:18 PM PDT 24
Finished Jun 28 06:15:24 PM PDT 24
Peak memory 206184 kb
Host smart-4f8b79e3-1856-41cc-983f-a3a49d73f441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30658
31655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.3065831655
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.3644439859
Short name T1732
Test name
Test status
Simulation time 169078283 ps
CPU time 0.82 seconds
Started Jun 28 06:14:57 PM PDT 24
Finished Jun 28 06:15:02 PM PDT 24
Peak memory 206204 kb
Host smart-ed41cac1-944b-454d-8012-45a0441c569b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36444
39859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.3644439859
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.372598999
Short name T2231
Test name
Test status
Simulation time 178225188 ps
CPU time 0.85 seconds
Started Jun 28 06:14:59 PM PDT 24
Finished Jun 28 06:15:04 PM PDT 24
Peak memory 206208 kb
Host smart-2b73f450-b249-4fb2-90a7-1de82098b485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37259
8999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.372598999
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_invalid_sync.1210526748
Short name T1314
Test name
Test status
Simulation time 7518461020 ps
CPU time 213.15 seconds
Started Jun 28 06:15:10 PM PDT 24
Finished Jun 28 06:18:44 PM PDT 24
Peak memory 206496 kb
Host smart-3f41001f-c473-4854-839c-87cf9d92db2e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1210526748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.1210526748
Directory /workspace/44.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.1847764583
Short name T656
Test name
Test status
Simulation time 215268078 ps
CPU time 0.88 seconds
Started Jun 28 06:14:57 PM PDT 24
Finished Jun 28 06:15:01 PM PDT 24
Peak memory 206128 kb
Host smart-a7d0204f-7763-47a1-a074-c83730b1fe1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18477
64583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.1847764583
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.1917420390
Short name T1278
Test name
Test status
Simulation time 23325650827 ps
CPU time 23.08 seconds
Started Jun 28 06:15:12 PM PDT 24
Finished Jun 28 06:15:39 PM PDT 24
Peak memory 206292 kb
Host smart-c7d3ca18-63b4-468f-a4cd-38dab5c1417e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19174
20390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.1917420390
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.658727113
Short name T2020
Test name
Test status
Simulation time 3330357738 ps
CPU time 3.92 seconds
Started Jun 28 06:15:20 PM PDT 24
Finished Jun 28 06:15:35 PM PDT 24
Peak memory 206244 kb
Host smart-a26aa20d-c5e5-499f-b8c4-ed9e60051dad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65872
7113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.658727113
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.1221821784
Short name T1156
Test name
Test status
Simulation time 6685776262 ps
CPU time 49.01 seconds
Started Jun 28 06:15:17 PM PDT 24
Finished Jun 28 06:16:11 PM PDT 24
Peak memory 206464 kb
Host smart-fb709a0e-11e4-4f7a-a612-17579621e02c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12218
21784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.1221821784
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.1839328957
Short name T1353
Test name
Test status
Simulation time 4862256036 ps
CPU time 46.82 seconds
Started Jun 28 06:15:09 PM PDT 24
Finished Jun 28 06:15:56 PM PDT 24
Peak memory 206360 kb
Host smart-27a9f3ad-db31-46a6-a868-23f06f4f9dc7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1839328957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.1839328957
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.2785354268
Short name T1100
Test name
Test status
Simulation time 238600492 ps
CPU time 0.9 seconds
Started Jun 28 06:14:57 PM PDT 24
Finished Jun 28 06:15:02 PM PDT 24
Peak memory 206212 kb
Host smart-c50d38d1-8872-40c1-a161-e36cf4b20a0a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2785354268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.2785354268
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.4061950545
Short name T1569
Test name
Test status
Simulation time 247901376 ps
CPU time 0.95 seconds
Started Jun 28 06:15:01 PM PDT 24
Finished Jun 28 06:15:05 PM PDT 24
Peak memory 206196 kb
Host smart-66fba465-d159-4c0d-84cd-93bedbec19c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40619
50545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.4061950545
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.898274408
Short name T779
Test name
Test status
Simulation time 4960838539 ps
CPU time 45.9 seconds
Started Jun 28 06:15:09 PM PDT 24
Finished Jun 28 06:15:56 PM PDT 24
Peak memory 206412 kb
Host smart-b534e7bf-698b-4ece-862a-009e736fa8e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89827
4408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.898274408
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.1667408739
Short name T430
Test name
Test status
Simulation time 7461809608 ps
CPU time 203.06 seconds
Started Jun 28 06:14:59 PM PDT 24
Finished Jun 28 06:18:25 PM PDT 24
Peak memory 206396 kb
Host smart-59382afe-12a6-4d74-a463-9762c601b451
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1667408739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.1667408739
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.786334440
Short name T1012
Test name
Test status
Simulation time 164924900 ps
CPU time 0.78 seconds
Started Jun 28 06:15:11 PM PDT 24
Finished Jun 28 06:15:14 PM PDT 24
Peak memory 206196 kb
Host smart-4a5aa17c-4c73-4ffa-9f42-59fd9e3c300b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=786334440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.786334440
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.1297338262
Short name T1785
Test name
Test status
Simulation time 214834420 ps
CPU time 0.84 seconds
Started Jun 28 06:15:12 PM PDT 24
Finished Jun 28 06:15:17 PM PDT 24
Peak memory 206180 kb
Host smart-747d0437-b306-4f9b-a1c6-3e2813e8dbd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12973
38262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.1297338262
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.3322710965
Short name T2221
Test name
Test status
Simulation time 293379803 ps
CPU time 0.96 seconds
Started Jun 28 06:15:11 PM PDT 24
Finished Jun 28 06:15:15 PM PDT 24
Peak memory 206204 kb
Host smart-01a61955-4174-4d4d-a8f0-31382a0ff57f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33227
10965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.3322710965
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.4083934398
Short name T577
Test name
Test status
Simulation time 173492555 ps
CPU time 0.81 seconds
Started Jun 28 06:15:10 PM PDT 24
Finished Jun 28 06:15:13 PM PDT 24
Peak memory 206164 kb
Host smart-bed54da9-9644-490e-b0d4-291dd999f62b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40839
34398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.4083934398
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.754664419
Short name T2167
Test name
Test status
Simulation time 175557243 ps
CPU time 0.83 seconds
Started Jun 28 06:15:00 PM PDT 24
Finished Jun 28 06:15:04 PM PDT 24
Peak memory 206192 kb
Host smart-e3bda240-b7f9-46a6-850c-aad51f19b3b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75466
4419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.754664419
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.3166976278
Short name T1566
Test name
Test status
Simulation time 194794920 ps
CPU time 0.87 seconds
Started Jun 28 06:14:58 PM PDT 24
Finished Jun 28 06:15:02 PM PDT 24
Peak memory 206164 kb
Host smart-9b73ff80-3d95-46ca-834c-ac5653152f42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31669
76278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.3166976278
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.125879600
Short name T919
Test name
Test status
Simulation time 240596029 ps
CPU time 0.88 seconds
Started Jun 28 06:15:12 PM PDT 24
Finished Jun 28 06:15:16 PM PDT 24
Peak memory 206216 kb
Host smart-51979ebc-8747-457a-9157-285d24eafc6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12587
9600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.125879600
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.3569480825
Short name T1570
Test name
Test status
Simulation time 229084944 ps
CPU time 1.02 seconds
Started Jun 28 06:14:59 PM PDT 24
Finished Jun 28 06:15:04 PM PDT 24
Peak memory 206212 kb
Host smart-2d8b5aae-a486-411f-91f4-fe2f8d5f5600
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3569480825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.3569480825
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.1764472718
Short name T2039
Test name
Test status
Simulation time 191510926 ps
CPU time 0.8 seconds
Started Jun 28 06:15:09 PM PDT 24
Finished Jun 28 06:15:11 PM PDT 24
Peak memory 206192 kb
Host smart-7eedabe9-f77b-4704-afb5-64e2c99bd147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17644
72718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.1764472718
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.1505696520
Short name T2304
Test name
Test status
Simulation time 36398455 ps
CPU time 0.66 seconds
Started Jun 28 06:15:19 PM PDT 24
Finished Jun 28 06:15:25 PM PDT 24
Peak memory 206344 kb
Host smart-50f17e36-ffc8-41bf-8a63-4e8cdba4fa34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15056
96520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.1505696520
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.3736034875
Short name T285
Test name
Test status
Simulation time 9451225538 ps
CPU time 21.59 seconds
Started Jun 28 06:15:11 PM PDT 24
Finished Jun 28 06:15:35 PM PDT 24
Peak memory 206480 kb
Host smart-8d3dfe8b-b79b-43b2-a8e7-500036eb4776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37360
34875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.3736034875
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.1691035403
Short name T1736
Test name
Test status
Simulation time 201247546 ps
CPU time 0.9 seconds
Started Jun 28 06:15:02 PM PDT 24
Finished Jun 28 06:15:06 PM PDT 24
Peak memory 206196 kb
Host smart-80ab902a-365a-4c63-9256-7619363de7ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16910
35403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.1691035403
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.1043220646
Short name T1507
Test name
Test status
Simulation time 183483348 ps
CPU time 0.82 seconds
Started Jun 28 06:15:16 PM PDT 24
Finished Jun 28 06:15:21 PM PDT 24
Peak memory 206196 kb
Host smart-7f4a0b86-f6ff-4580-b07d-b39dbf45cdd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10432
20646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.1043220646
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.576690766
Short name T1731
Test name
Test status
Simulation time 183925958 ps
CPU time 0.8 seconds
Started Jun 28 06:15:15 PM PDT 24
Finished Jun 28 06:15:21 PM PDT 24
Peak memory 206208 kb
Host smart-929934c9-e1ad-4aa6-b6cd-a4ddd4b08590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57669
0766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.576690766
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.402542106
Short name T2168
Test name
Test status
Simulation time 220255780 ps
CPU time 0.85 seconds
Started Jun 28 06:15:17 PM PDT 24
Finished Jun 28 06:15:23 PM PDT 24
Peak memory 206192 kb
Host smart-6a327123-4f1f-4fdf-89ec-172d95e910a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40254
2106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.402542106
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.1789611858
Short name T1604
Test name
Test status
Simulation time 188137524 ps
CPU time 0.77 seconds
Started Jun 28 06:15:09 PM PDT 24
Finished Jun 28 06:15:11 PM PDT 24
Peak memory 206172 kb
Host smart-130bdb66-d36b-452f-acb3-d627acb294e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17896
11858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.1789611858
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.3182378257
Short name T2561
Test name
Test status
Simulation time 154388966 ps
CPU time 0.81 seconds
Started Jun 28 06:15:11 PM PDT 24
Finished Jun 28 06:15:14 PM PDT 24
Peak memory 206196 kb
Host smart-33384dd4-d790-471e-9b75-f37afdfa6dee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31823
78257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.3182378257
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.3922694006
Short name T1014
Test name
Test status
Simulation time 206159176 ps
CPU time 0.87 seconds
Started Jun 28 06:14:58 PM PDT 24
Finished Jun 28 06:15:02 PM PDT 24
Peak memory 206192 kb
Host smart-722207b9-ba2c-401b-8cc6-c7ccef7caa1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39226
94006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.3922694006
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.863808253
Short name T81
Test name
Test status
Simulation time 224875408 ps
CPU time 0.94 seconds
Started Jun 28 06:15:15 PM PDT 24
Finished Jun 28 06:15:20 PM PDT 24
Peak memory 206196 kb
Host smart-2e873bf8-44ba-4803-a081-4ef9d6546a28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86380
8253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.863808253
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.3834322194
Short name T1331
Test name
Test status
Simulation time 5937527085 ps
CPU time 42.87 seconds
Started Jun 28 06:14:58 PM PDT 24
Finished Jun 28 06:15:44 PM PDT 24
Peak memory 206392 kb
Host smart-8106d8e8-b530-4c83-9373-2893a7bd18ce
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3834322194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.3834322194
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.1507418896
Short name T2630
Test name
Test status
Simulation time 173896944 ps
CPU time 0.79 seconds
Started Jun 28 06:15:16 PM PDT 24
Finished Jun 28 06:15:21 PM PDT 24
Peak memory 206216 kb
Host smart-189ae72b-ccda-4ba9-a786-30b8e636e813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15074
18896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.1507418896
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.3866284703
Short name T323
Test name
Test status
Simulation time 158238258 ps
CPU time 0.8 seconds
Started Jun 28 06:15:15 PM PDT 24
Finished Jun 28 06:15:19 PM PDT 24
Peak memory 206348 kb
Host smart-3a84efb4-dab4-4a36-9d54-83ff72081afa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38662
84703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.3866284703
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.1851513036
Short name T5
Test name
Test status
Simulation time 6463818837 ps
CPU time 45.65 seconds
Started Jun 28 06:15:00 PM PDT 24
Finished Jun 28 06:15:49 PM PDT 24
Peak memory 206420 kb
Host smart-3145f137-f579-45d9-bd45-ec5c0caf9248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18515
13036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.1851513036
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.896045691
Short name T586
Test name
Test status
Simulation time 71722902 ps
CPU time 0.73 seconds
Started Jun 28 06:15:09 PM PDT 24
Finished Jun 28 06:15:11 PM PDT 24
Peak memory 206212 kb
Host smart-8aa72b7b-e8ec-43f5-b48a-92d3ba433d83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=896045691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.896045691
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.2906959069
Short name T932
Test name
Test status
Simulation time 4359235109 ps
CPU time 4.98 seconds
Started Jun 28 06:14:59 PM PDT 24
Finished Jun 28 06:15:08 PM PDT 24
Peak memory 206452 kb
Host smart-57a07e94-6f1a-4b82-b664-e0f4d4097dc7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2906959069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.2906959069
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.2663881187
Short name T2404
Test name
Test status
Simulation time 13363501292 ps
CPU time 12.75 seconds
Started Jun 28 06:15:12 PM PDT 24
Finished Jun 28 06:15:28 PM PDT 24
Peak memory 206324 kb
Host smart-8c10cce8-07bf-48a3-ae47-21bf8a8fbdbc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2663881187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.2663881187
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.2996492086
Short name T695
Test name
Test status
Simulation time 23510368794 ps
CPU time 28.44 seconds
Started Jun 28 06:15:21 PM PDT 24
Finished Jun 28 06:16:00 PM PDT 24
Peak memory 206448 kb
Host smart-b1bbcf72-2c37-4174-ae77-90bf8a86a5e0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2996492086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.2996492086
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.4254005892
Short name T1476
Test name
Test status
Simulation time 172971671 ps
CPU time 0.94 seconds
Started Jun 28 06:15:01 PM PDT 24
Finished Jun 28 06:15:05 PM PDT 24
Peak memory 206312 kb
Host smart-c41ad5cb-cef9-4a67-84e7-9c03b59014fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42540
05892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.4254005892
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.715075512
Short name T1453
Test name
Test status
Simulation time 143976868 ps
CPU time 0.89 seconds
Started Jun 28 06:15:20 PM PDT 24
Finished Jun 28 06:15:27 PM PDT 24
Peak memory 206192 kb
Host smart-cd8cbc8a-1dd5-44f8-9d7e-a8e7cbf05106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71507
5512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.715075512
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.3839464309
Short name T1330
Test name
Test status
Simulation time 487196315 ps
CPU time 1.57 seconds
Started Jun 28 06:15:03 PM PDT 24
Finished Jun 28 06:15:07 PM PDT 24
Peak memory 206156 kb
Host smart-6b58fc2b-cafa-4ca5-95ca-16ff582b9660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38394
64309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.3839464309
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.295037885
Short name T884
Test name
Test status
Simulation time 393174918 ps
CPU time 1.23 seconds
Started Jun 28 06:15:12 PM PDT 24
Finished Jun 28 06:15:17 PM PDT 24
Peak memory 206192 kb
Host smart-dda4c08f-14f8-4143-88f9-bfd4a3b64453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29503
7885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.295037885
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.1338358116
Short name T1008
Test name
Test status
Simulation time 15973900183 ps
CPU time 31.2 seconds
Started Jun 28 06:15:17 PM PDT 24
Finished Jun 28 06:15:53 PM PDT 24
Peak memory 206416 kb
Host smart-633f7618-a27b-43e9-b721-6cef766d0da2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13383
58116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.1338358116
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.149096811
Short name T1591
Test name
Test status
Simulation time 471143192 ps
CPU time 1.39 seconds
Started Jun 28 06:14:58 PM PDT 24
Finished Jun 28 06:15:03 PM PDT 24
Peak memory 206192 kb
Host smart-9752b700-e44f-4780-9d27-6307f3364fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14909
6811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.149096811
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.833347259
Short name T1667
Test name
Test status
Simulation time 147982447 ps
CPU time 0.82 seconds
Started Jun 28 06:15:03 PM PDT 24
Finished Jun 28 06:15:06 PM PDT 24
Peak memory 206160 kb
Host smart-2fbe3329-c0c4-40da-ad3c-811be6410603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83334
7259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.833347259
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.2725502246
Short name T1446
Test name
Test status
Simulation time 31033983 ps
CPU time 0.67 seconds
Started Jun 28 06:15:21 PM PDT 24
Finished Jun 28 06:15:27 PM PDT 24
Peak memory 206164 kb
Host smart-62ae5673-3474-46a1-a9b2-f14b65a25769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27255
02246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.2725502246
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.561175603
Short name T329
Test name
Test status
Simulation time 873715848 ps
CPU time 2.12 seconds
Started Jun 28 06:15:03 PM PDT 24
Finished Jun 28 06:15:07 PM PDT 24
Peak memory 206340 kb
Host smart-6cd74540-0720-4d47-a398-78d1ec489525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56117
5603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.561175603
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.2086001062
Short name T2134
Test name
Test status
Simulation time 166208483 ps
CPU time 1.59 seconds
Started Jun 28 06:15:03 PM PDT 24
Finished Jun 28 06:15:07 PM PDT 24
Peak memory 206288 kb
Host smart-ceb05433-f0ca-41df-90c9-272546952e4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20860
01062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.2086001062
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.812324475
Short name T2172
Test name
Test status
Simulation time 263179565 ps
CPU time 0.91 seconds
Started Jun 28 06:15:17 PM PDT 24
Finished Jun 28 06:15:23 PM PDT 24
Peak memory 206188 kb
Host smart-337905b8-7d2f-47a8-a4e3-055dcfb23d3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81232
4475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.812324475
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.1202860783
Short name T448
Test name
Test status
Simulation time 149004417 ps
CPU time 0.77 seconds
Started Jun 28 06:15:11 PM PDT 24
Finished Jun 28 06:15:14 PM PDT 24
Peak memory 206216 kb
Host smart-619389ad-f398-4bee-ac7f-be2a1075934c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12028
60783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.1202860783
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.1487279442
Short name T348
Test name
Test status
Simulation time 223948642 ps
CPU time 0.88 seconds
Started Jun 28 06:15:17 PM PDT 24
Finished Jun 28 06:15:23 PM PDT 24
Peak memory 206192 kb
Host smart-afa41262-fdc1-41c4-9b9d-f51e4e85372c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14872
79442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.1487279442
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_invalid_sync.71668634
Short name T83
Test name
Test status
Simulation time 7909736600 ps
CPU time 74.81 seconds
Started Jun 28 06:15:19 PM PDT 24
Finished Jun 28 06:16:40 PM PDT 24
Peak memory 206424 kb
Host smart-a4c6f649-50b7-4aff-94bf-4f7d1c82cf26
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=71668634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.71668634
Directory /workspace/45.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.3699243036
Short name T628
Test name
Test status
Simulation time 251192853 ps
CPU time 0.89 seconds
Started Jun 28 06:15:11 PM PDT 24
Finished Jun 28 06:15:15 PM PDT 24
Peak memory 206192 kb
Host smart-8d78f1eb-7acd-47b3-a5fa-3c0c015222c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36992
43036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.3699243036
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.1250518792
Short name T2251
Test name
Test status
Simulation time 23322775442 ps
CPU time 21.4 seconds
Started Jun 28 06:15:10 PM PDT 24
Finished Jun 28 06:15:33 PM PDT 24
Peak memory 206312 kb
Host smart-a75a8678-360a-4b6e-8de2-497e25488a0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12505
18792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.1250518792
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.221362095
Short name T376
Test name
Test status
Simulation time 3301956598 ps
CPU time 3.89 seconds
Started Jun 28 06:15:17 PM PDT 24
Finished Jun 28 06:15:26 PM PDT 24
Peak memory 206252 kb
Host smart-45017d33-6113-4181-a358-2becbfec063c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22136
2095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.221362095
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.2095671943
Short name T2342
Test name
Test status
Simulation time 9487559400 ps
CPU time 263.67 seconds
Started Jun 28 06:15:16 PM PDT 24
Finished Jun 28 06:19:45 PM PDT 24
Peak memory 206500 kb
Host smart-ca5d0697-6d7a-4569-a5e3-2d194403134d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20956
71943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.2095671943
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.345039399
Short name T2560
Test name
Test status
Simulation time 4229739980 ps
CPU time 28.93 seconds
Started Jun 28 06:15:18 PM PDT 24
Finished Jun 28 06:15:53 PM PDT 24
Peak memory 206468 kb
Host smart-be1d59b8-f483-40e7-a01b-4f87f00330f8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=345039399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.345039399
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.3239080525
Short name T755
Test name
Test status
Simulation time 268715143 ps
CPU time 0.96 seconds
Started Jun 28 06:15:19 PM PDT 24
Finished Jun 28 06:15:26 PM PDT 24
Peak memory 206216 kb
Host smart-a98d742e-0e18-40a4-bf21-7567435d290b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3239080525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.3239080525
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.2276849731
Short name T2144
Test name
Test status
Simulation time 214870347 ps
CPU time 0.89 seconds
Started Jun 28 06:15:11 PM PDT 24
Finished Jun 28 06:15:13 PM PDT 24
Peak memory 206200 kb
Host smart-ecb548f8-4c40-4912-9418-da2b6ac30fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22768
49731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.2276849731
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.534233395
Short name T406
Test name
Test status
Simulation time 5948848010 ps
CPU time 42.11 seconds
Started Jun 28 06:15:24 PM PDT 24
Finished Jun 28 06:16:12 PM PDT 24
Peak memory 206456 kb
Host smart-9fe9164d-d971-403d-b3e4-477f8429421e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53423
3395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.534233395
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.446278130
Short name T1416
Test name
Test status
Simulation time 3081924926 ps
CPU time 85.3 seconds
Started Jun 28 06:15:22 PM PDT 24
Finished Jun 28 06:16:54 PM PDT 24
Peak memory 206440 kb
Host smart-d1221d4a-184d-4f28-9e0a-757b769e0b33
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=446278130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.446278130
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.3246146206
Short name T1686
Test name
Test status
Simulation time 203049425 ps
CPU time 0.86 seconds
Started Jun 28 06:15:09 PM PDT 24
Finished Jun 28 06:15:11 PM PDT 24
Peak memory 206216 kb
Host smart-53c8d5e6-20ac-4e59-972c-9c10cddf0a91
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3246146206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.3246146206
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.3046299677
Short name T496
Test name
Test status
Simulation time 149759910 ps
CPU time 0.84 seconds
Started Jun 28 06:15:13 PM PDT 24
Finished Jun 28 06:15:17 PM PDT 24
Peak memory 206176 kb
Host smart-5b4029e7-3d81-4e86-b56d-10a2f8d61175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30462
99677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.3046299677
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.509185355
Short name T136
Test name
Test status
Simulation time 214804924 ps
CPU time 0.93 seconds
Started Jun 28 06:15:13 PM PDT 24
Finished Jun 28 06:15:18 PM PDT 24
Peak memory 206212 kb
Host smart-b9d56387-b065-4530-80b7-9c8ab1bd140f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50918
5355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.509185355
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.3140646413
Short name T2499
Test name
Test status
Simulation time 161052916 ps
CPU time 0.87 seconds
Started Jun 28 06:15:18 PM PDT 24
Finished Jun 28 06:15:24 PM PDT 24
Peak memory 206192 kb
Host smart-42f3ca1b-7a60-4fe5-a66f-7d2182b0f113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31406
46413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.3140646413
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.919327303
Short name T2058
Test name
Test status
Simulation time 161755454 ps
CPU time 0.74 seconds
Started Jun 28 06:15:29 PM PDT 24
Finished Jun 28 06:15:36 PM PDT 24
Peak memory 206212 kb
Host smart-9ce8a901-aada-43f1-bba6-cb7800848ae5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91932
7303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.919327303
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.820903362
Short name T837
Test name
Test status
Simulation time 229423663 ps
CPU time 0.8 seconds
Started Jun 28 06:15:12 PM PDT 24
Finished Jun 28 06:15:16 PM PDT 24
Peak memory 206192 kb
Host smart-57d7cb5d-bff6-47ce-bab5-4a8f677972f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82090
3362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.820903362
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.816009510
Short name T2102
Test name
Test status
Simulation time 157141486 ps
CPU time 0.8 seconds
Started Jun 28 06:15:19 PM PDT 24
Finished Jun 28 06:15:25 PM PDT 24
Peak memory 206212 kb
Host smart-6aa2dfe8-80ee-415c-a742-457bb3ae02e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81600
9510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.816009510
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.4287528237
Short name T2613
Test name
Test status
Simulation time 305009694 ps
CPU time 1.03 seconds
Started Jun 28 06:15:20 PM PDT 24
Finished Jun 28 06:15:27 PM PDT 24
Peak memory 206212 kb
Host smart-3188dc52-af51-4239-b299-0a29606050c8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4287528237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.4287528237
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.3328932562
Short name T1224
Test name
Test status
Simulation time 144230933 ps
CPU time 0.77 seconds
Started Jun 28 06:15:10 PM PDT 24
Finished Jun 28 06:15:13 PM PDT 24
Peak memory 206200 kb
Host smart-9b19502d-f53e-44e6-b907-a6f9b0175761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33289
32562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.3328932562
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.1448264544
Short name T1009
Test name
Test status
Simulation time 37962254 ps
CPU time 0.66 seconds
Started Jun 28 06:15:29 PM PDT 24
Finished Jun 28 06:15:35 PM PDT 24
Peak memory 206204 kb
Host smart-5d5dd8c8-89ff-407b-998d-420370c4653b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14482
64544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.1448264544
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.3614639862
Short name T1828
Test name
Test status
Simulation time 10232697551 ps
CPU time 22.79 seconds
Started Jun 28 06:15:09 PM PDT 24
Finished Jun 28 06:15:33 PM PDT 24
Peak memory 206452 kb
Host smart-8ab681c3-6146-4338-bc62-c7f9f9f5e869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36146
39862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.3614639862
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.2985685369
Short name T2121
Test name
Test status
Simulation time 169027744 ps
CPU time 0.89 seconds
Started Jun 28 06:15:13 PM PDT 24
Finished Jun 28 06:15:18 PM PDT 24
Peak memory 206128 kb
Host smart-9ff8719a-928c-440f-8b1d-327a50513e99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29856
85369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.2985685369
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.1036258864
Short name T994
Test name
Test status
Simulation time 275402113 ps
CPU time 0.95 seconds
Started Jun 28 06:15:16 PM PDT 24
Finished Jun 28 06:15:22 PM PDT 24
Peak memory 206188 kb
Host smart-6407d082-e31a-4280-8c5b-2c68b67f0594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10362
58864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.1036258864
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.858417088
Short name T634
Test name
Test status
Simulation time 230480858 ps
CPU time 0.96 seconds
Started Jun 28 06:15:12 PM PDT 24
Finished Jun 28 06:15:17 PM PDT 24
Peak memory 206188 kb
Host smart-83a664da-0fc5-4e7e-9cba-1843b8f4ecda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85841
7088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.858417088
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.2041983424
Short name T2369
Test name
Test status
Simulation time 223444518 ps
CPU time 0.98 seconds
Started Jun 28 06:15:11 PM PDT 24
Finished Jun 28 06:15:13 PM PDT 24
Peak memory 206196 kb
Host smart-9dc73856-6693-4913-b92c-5f2bd8d4237d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20419
83424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.2041983424
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.4059417246
Short name T1983
Test name
Test status
Simulation time 203531544 ps
CPU time 0.86 seconds
Started Jun 28 06:15:12 PM PDT 24
Finished Jun 28 06:15:17 PM PDT 24
Peak memory 206168 kb
Host smart-9372880e-cedd-4adb-a10e-15cff50ac973
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40594
17246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.4059417246
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.3530022449
Short name T2402
Test name
Test status
Simulation time 144286642 ps
CPU time 0.77 seconds
Started Jun 28 06:15:29 PM PDT 24
Finished Jun 28 06:15:35 PM PDT 24
Peak memory 206188 kb
Host smart-bcf93473-2a9e-436f-97ee-95138417090b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35300
22449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.3530022449
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.2080980033
Short name T735
Test name
Test status
Simulation time 152519606 ps
CPU time 0.8 seconds
Started Jun 28 06:15:19 PM PDT 24
Finished Jun 28 06:15:26 PM PDT 24
Peak memory 206188 kb
Host smart-bdb838d2-9ef5-4c73-b57d-1ce67e01c518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20809
80033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.2080980033
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.40221058
Short name T1789
Test name
Test status
Simulation time 218581888 ps
CPU time 0.88 seconds
Started Jun 28 06:15:18 PM PDT 24
Finished Jun 28 06:15:24 PM PDT 24
Peak memory 206152 kb
Host smart-15cfde8f-7a7e-4804-ba8d-3e6cd354b073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40221
058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.40221058
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.4095168768
Short name T1513
Test name
Test status
Simulation time 5576537068 ps
CPU time 155.07 seconds
Started Jun 28 06:15:13 PM PDT 24
Finished Jun 28 06:17:51 PM PDT 24
Peak memory 206472 kb
Host smart-f2d524c8-0447-4bc0-aec9-a8734ec052a2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4095168768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.4095168768
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.1933474554
Short name T1641
Test name
Test status
Simulation time 171683439 ps
CPU time 0.84 seconds
Started Jun 28 06:15:09 PM PDT 24
Finished Jun 28 06:15:11 PM PDT 24
Peak memory 206224 kb
Host smart-55a821df-a62e-4751-98c0-b403937d0b54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19334
74554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.1933474554
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.3426093596
Short name T343
Test name
Test status
Simulation time 157602602 ps
CPU time 0.77 seconds
Started Jun 28 06:15:17 PM PDT 24
Finished Jun 28 06:15:22 PM PDT 24
Peak memory 206192 kb
Host smart-750ca810-d323-454a-ae5c-6bdb8729a3dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34260
93596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.3426093596
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.2998538728
Short name T844
Test name
Test status
Simulation time 5018976244 ps
CPU time 47.23 seconds
Started Jun 28 06:15:24 PM PDT 24
Finished Jun 28 06:16:17 PM PDT 24
Peak memory 206476 kb
Host smart-04b9b53f-d524-4b40-b677-8da08099561a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29985
38728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.2998538728
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.4216321695
Short name T646
Test name
Test status
Simulation time 32692286 ps
CPU time 0.67 seconds
Started Jun 28 06:15:33 PM PDT 24
Finished Jun 28 06:15:37 PM PDT 24
Peak memory 206196 kb
Host smart-366c9996-5f87-460a-83da-9f06fff559a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4216321695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.4216321695
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.2025825938
Short name T37
Test name
Test status
Simulation time 4289125226 ps
CPU time 4.72 seconds
Started Jun 28 06:15:13 PM PDT 24
Finished Jun 28 06:15:21 PM PDT 24
Peak memory 206336 kb
Host smart-288b77b8-786a-4b24-ab64-3ed3775e40c6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2025825938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.2025825938
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.1857852412
Short name T390
Test name
Test status
Simulation time 13322431926 ps
CPU time 12.21 seconds
Started Jun 28 06:15:16 PM PDT 24
Finished Jun 28 06:15:33 PM PDT 24
Peak memory 206396 kb
Host smart-0b83ffe5-5d0b-4516-8a5a-3bc224fc2826
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1857852412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.1857852412
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.3615427207
Short name T2625
Test name
Test status
Simulation time 23375457397 ps
CPU time 22.3 seconds
Started Jun 28 06:15:22 PM PDT 24
Finished Jun 28 06:15:50 PM PDT 24
Peak memory 206472 kb
Host smart-ae2aff1e-f010-4943-9fc0-01d1676babfa
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3615427207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.3615427207
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.1868245239
Short name T1135
Test name
Test status
Simulation time 166411254 ps
CPU time 0.79 seconds
Started Jun 28 06:15:13 PM PDT 24
Finished Jun 28 06:15:18 PM PDT 24
Peak memory 206184 kb
Host smart-9e459ccf-ce9b-49f4-8d90-b7242b43472e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18682
45239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.1868245239
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.2067166281
Short name T54
Test name
Test status
Simulation time 159232233 ps
CPU time 0.83 seconds
Started Jun 28 06:15:16 PM PDT 24
Finished Jun 28 06:15:21 PM PDT 24
Peak memory 206192 kb
Host smart-08d2f5cd-573e-413c-91c8-6d74eae9b64c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20671
66281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.2067166281
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.3617973450
Short name T188
Test name
Test status
Simulation time 360938631 ps
CPU time 1.17 seconds
Started Jun 28 06:15:28 PM PDT 24
Finished Jun 28 06:15:35 PM PDT 24
Peak memory 206196 kb
Host smart-856a3157-53d7-4c17-9e62-e08d0ebf1a79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36179
73450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.3617973450
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.2649987016
Short name T1356
Test name
Test status
Simulation time 656167185 ps
CPU time 1.62 seconds
Started Jun 28 06:15:29 PM PDT 24
Finished Jun 28 06:15:36 PM PDT 24
Peak memory 206272 kb
Host smart-794e4954-317f-4c11-ab62-7b5c27ff2d3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26499
87016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.2649987016
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.662622190
Short name T818
Test name
Test status
Simulation time 6310698853 ps
CPU time 13.68 seconds
Started Jun 28 06:15:19 PM PDT 24
Finished Jun 28 06:15:38 PM PDT 24
Peak memory 206452 kb
Host smart-b695e9c6-f3e0-4da4-a776-2ca9e9838217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66262
2190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.662622190
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.3636067914
Short name T1754
Test name
Test status
Simulation time 334227115 ps
CPU time 1.16 seconds
Started Jun 28 06:15:12 PM PDT 24
Finished Jun 28 06:15:16 PM PDT 24
Peak memory 206192 kb
Host smart-0fb235c1-e801-456f-9fc3-048fb84dbfbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36360
67914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.3636067914
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.843311086
Short name T1185
Test name
Test status
Simulation time 144505721 ps
CPU time 0.82 seconds
Started Jun 28 06:15:26 PM PDT 24
Finished Jun 28 06:15:32 PM PDT 24
Peak memory 206188 kb
Host smart-4ab72dde-a70e-4a99-a876-1a7273060adb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84331
1086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.843311086
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.2753270079
Short name T794
Test name
Test status
Simulation time 31493183 ps
CPU time 0.7 seconds
Started Jun 28 06:15:24 PM PDT 24
Finished Jun 28 06:15:31 PM PDT 24
Peak memory 206176 kb
Host smart-5783ab22-5226-489e-8948-7ef2d535df51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27532
70079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.2753270079
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.1968471134
Short name T1839
Test name
Test status
Simulation time 888365062 ps
CPU time 2.1 seconds
Started Jun 28 06:15:20 PM PDT 24
Finished Jun 28 06:15:27 PM PDT 24
Peak memory 206372 kb
Host smart-7b18b90e-da38-4c5b-aca9-9f837cc0f7b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19684
71134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.1968471134
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.2736237469
Short name T1759
Test name
Test status
Simulation time 180113369 ps
CPU time 1.87 seconds
Started Jun 28 06:15:18 PM PDT 24
Finished Jun 28 06:15:25 PM PDT 24
Peak memory 206284 kb
Host smart-b3655b37-179b-43c4-9d4a-c6bdfd369d11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27362
37469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.2736237469
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.3599201404
Short name T1115
Test name
Test status
Simulation time 210489119 ps
CPU time 0.82 seconds
Started Jun 28 06:15:20 PM PDT 24
Finished Jun 28 06:15:26 PM PDT 24
Peak memory 206184 kb
Host smart-db0cec94-3e31-4d19-96ec-e5e478a65770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35992
01404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.3599201404
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.2712509782
Short name T2071
Test name
Test status
Simulation time 155695073 ps
CPU time 0.78 seconds
Started Jun 28 06:15:27 PM PDT 24
Finished Jun 28 06:15:34 PM PDT 24
Peak memory 206192 kb
Host smart-ccb67222-cd07-4451-a619-a75d2b942e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27125
09782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.2712509782
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.3352136344
Short name T2028
Test name
Test status
Simulation time 271125671 ps
CPU time 1 seconds
Started Jun 28 06:15:18 PM PDT 24
Finished Jun 28 06:15:24 PM PDT 24
Peak memory 206212 kb
Host smart-c025302c-4110-418e-a35e-9d8ac812f624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33521
36344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.3352136344
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_invalid_sync.3802525660
Short name T66
Test name
Test status
Simulation time 6576391955 ps
CPU time 176.71 seconds
Started Jun 28 06:15:19 PM PDT 24
Finished Jun 28 06:18:21 PM PDT 24
Peak memory 206524 kb
Host smart-95b49ba4-b0bd-4899-9d3d-65ad627556e5
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3802525660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_invalid_sync.3802525660
Directory /workspace/46.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.3831571777
Short name T1151
Test name
Test status
Simulation time 176806864 ps
CPU time 0.82 seconds
Started Jun 28 06:15:18 PM PDT 24
Finished Jun 28 06:15:25 PM PDT 24
Peak memory 206156 kb
Host smart-1fb24c33-f344-4639-bf0f-4b934789c37e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38315
71777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.3831571777
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.2362482101
Short name T282
Test name
Test status
Simulation time 23359131134 ps
CPU time 23.02 seconds
Started Jun 28 06:15:13 PM PDT 24
Finished Jun 28 06:15:40 PM PDT 24
Peak memory 206308 kb
Host smart-6165924f-c22d-4957-aa8e-37c3352e2197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23624
82101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.2362482101
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.4139776269
Short name T383
Test name
Test status
Simulation time 3293986202 ps
CPU time 4.17 seconds
Started Jun 28 06:15:14 PM PDT 24
Finished Jun 28 06:15:22 PM PDT 24
Peak memory 206252 kb
Host smart-578b504f-30dd-4b7c-917f-ea1f19403cd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41397
76269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.4139776269
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.3952740015
Short name T679
Test name
Test status
Simulation time 9482152527 ps
CPU time 258.79 seconds
Started Jun 28 06:15:13 PM PDT 24
Finished Jun 28 06:19:36 PM PDT 24
Peak memory 206500 kb
Host smart-af13b3dc-860d-431f-8e72-c3960b8a4c4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39527
40015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.3952740015
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.787181478
Short name T1594
Test name
Test status
Simulation time 5947708849 ps
CPU time 39.67 seconds
Started Jun 28 06:15:18 PM PDT 24
Finished Jun 28 06:16:03 PM PDT 24
Peak memory 206496 kb
Host smart-58659aab-c2e2-4655-adee-16023a438b26
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=787181478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.787181478
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.2283841192
Short name T591
Test name
Test status
Simulation time 294356892 ps
CPU time 0.96 seconds
Started Jun 28 06:15:14 PM PDT 24
Finished Jun 28 06:15:19 PM PDT 24
Peak memory 206212 kb
Host smart-8383fcfb-4dac-423a-9335-a90061b5d675
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2283841192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.2283841192
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.1862381813
Short name T380
Test name
Test status
Simulation time 194577214 ps
CPU time 0.87 seconds
Started Jun 28 06:15:14 PM PDT 24
Finished Jun 28 06:15:19 PM PDT 24
Peak memory 206208 kb
Host smart-8ada2e5a-e200-4f0b-b540-e2645fec0628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18623
81813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.1862381813
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.2950967021
Short name T558
Test name
Test status
Simulation time 7426655181 ps
CPU time 51.95 seconds
Started Jun 28 06:15:14 PM PDT 24
Finished Jun 28 06:16:10 PM PDT 24
Peak memory 206484 kb
Host smart-413dc3f6-fbf9-49b2-ae5c-ee5d8307f58d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29509
67021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.2950967021
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.292993509
Short name T1861
Test name
Test status
Simulation time 4355576004 ps
CPU time 40.69 seconds
Started Jun 28 06:15:18 PM PDT 24
Finished Jun 28 06:16:04 PM PDT 24
Peak memory 206376 kb
Host smart-783fb1f3-235b-4875-a7c8-153972a513b7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=292993509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.292993509
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.3040334725
Short name T1480
Test name
Test status
Simulation time 152177292 ps
CPU time 0.81 seconds
Started Jun 28 06:15:18 PM PDT 24
Finished Jun 28 06:15:24 PM PDT 24
Peak memory 206212 kb
Host smart-681d31a9-84eb-41a4-b3dc-1b77dcf446be
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3040334725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.3040334725
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.3818120314
Short name T2622
Test name
Test status
Simulation time 154933336 ps
CPU time 0.81 seconds
Started Jun 28 06:15:17 PM PDT 24
Finished Jun 28 06:15:23 PM PDT 24
Peak memory 206196 kb
Host smart-710687cb-79d8-4a65-b625-5f3cd6c68cbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38181
20314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.3818120314
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.187533379
Short name T119
Test name
Test status
Simulation time 213123599 ps
CPU time 0.9 seconds
Started Jun 28 06:15:17 PM PDT 24
Finished Jun 28 06:15:23 PM PDT 24
Peak memory 206216 kb
Host smart-8bcdabe0-faae-4eb7-a9c7-d9b89a20f976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18753
3379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.187533379
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.1494110671
Short name T1487
Test name
Test status
Simulation time 206720772 ps
CPU time 0.89 seconds
Started Jun 28 06:15:21 PM PDT 24
Finished Jun 28 06:15:28 PM PDT 24
Peak memory 206172 kb
Host smart-232adda2-4390-4d4a-a702-ab262f01dcae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14941
10671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.1494110671
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.1176580570
Short name T2554
Test name
Test status
Simulation time 169331947 ps
CPU time 0.78 seconds
Started Jun 28 06:15:19 PM PDT 24
Finished Jun 28 06:15:25 PM PDT 24
Peak memory 206172 kb
Host smart-86ff4ff4-2735-4779-ab4c-5ec25e43be15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11765
80570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.1176580570
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.905897561
Short name T252
Test name
Test status
Simulation time 194932277 ps
CPU time 0.84 seconds
Started Jun 28 06:15:18 PM PDT 24
Finished Jun 28 06:15:25 PM PDT 24
Peak memory 206156 kb
Host smart-19a047bb-93b2-4ac4-8e89-fc3ec989c99e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90589
7561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.905897561
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.3510029520
Short name T2442
Test name
Test status
Simulation time 144394222 ps
CPU time 0.83 seconds
Started Jun 28 06:15:14 PM PDT 24
Finished Jun 28 06:15:19 PM PDT 24
Peak memory 206200 kb
Host smart-e8885e95-6a20-41bb-a542-a6695519481b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35100
29520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.3510029520
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.2969189581
Short name T1909
Test name
Test status
Simulation time 257205059 ps
CPU time 1.05 seconds
Started Jun 28 06:15:18 PM PDT 24
Finished Jun 28 06:15:24 PM PDT 24
Peak memory 206188 kb
Host smart-89eadf49-291c-4f37-a655-2a4e2904e408
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2969189581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.2969189581
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.3273372841
Short name T2594
Test name
Test status
Simulation time 171467115 ps
CPU time 0.79 seconds
Started Jun 28 06:15:21 PM PDT 24
Finished Jun 28 06:15:27 PM PDT 24
Peak memory 206196 kb
Host smart-5dc5413b-060f-4210-b2d3-f4e8fe745a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32733
72841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.3273372841
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.1072109677
Short name T1320
Test name
Test status
Simulation time 48031717 ps
CPU time 0.66 seconds
Started Jun 28 06:15:25 PM PDT 24
Finished Jun 28 06:15:32 PM PDT 24
Peak memory 206200 kb
Host smart-8a34d1d8-6b28-4e57-b899-09352ef5f050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10721
09677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.1072109677
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.4147590335
Short name T260
Test name
Test status
Simulation time 10616286991 ps
CPU time 23.26 seconds
Started Jun 28 06:15:18 PM PDT 24
Finished Jun 28 06:15:46 PM PDT 24
Peak memory 206440 kb
Host smart-1495decb-a76c-4276-8c2a-bd3c2c90c976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41475
90335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.4147590335
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.3839053651
Short name T883
Test name
Test status
Simulation time 181473178 ps
CPU time 0.83 seconds
Started Jun 28 06:15:22 PM PDT 24
Finished Jun 28 06:15:29 PM PDT 24
Peak memory 206188 kb
Host smart-23953b1f-8c47-4aae-8d27-0c9a10bfca59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38390
53651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.3839053651
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.3068814813
Short name T511
Test name
Test status
Simulation time 227685067 ps
CPU time 1 seconds
Started Jun 28 06:15:13 PM PDT 24
Finished Jun 28 06:15:18 PM PDT 24
Peak memory 206148 kb
Host smart-b98af3ed-c57e-4a3a-b869-7368c1334535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30688
14813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.3068814813
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.3794800844
Short name T2271
Test name
Test status
Simulation time 168982013 ps
CPU time 0.8 seconds
Started Jun 28 06:15:19 PM PDT 24
Finished Jun 28 06:15:25 PM PDT 24
Peak memory 206240 kb
Host smart-a0639260-1206-4fa4-b3e1-97bada40c06c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37948
00844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.3794800844
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.3710406409
Short name T2351
Test name
Test status
Simulation time 173810787 ps
CPU time 0.86 seconds
Started Jun 28 06:15:18 PM PDT 24
Finished Jun 28 06:15:24 PM PDT 24
Peak memory 206184 kb
Host smart-07030303-231f-499e-8074-8eda2a37d128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37104
06409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.3710406409
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.3372606778
Short name T1261
Test name
Test status
Simulation time 198696191 ps
CPU time 0.88 seconds
Started Jun 28 06:15:12 PM PDT 24
Finished Jun 28 06:15:16 PM PDT 24
Peak memory 206188 kb
Host smart-ad6c5f40-3da4-40f9-a8ee-cc59ae8fa900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33726
06778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.3372606778
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.321505622
Short name T1269
Test name
Test status
Simulation time 155035729 ps
CPU time 0.77 seconds
Started Jun 28 06:15:13 PM PDT 24
Finished Jun 28 06:15:17 PM PDT 24
Peak memory 206168 kb
Host smart-3f81c2a9-dcbd-4ff6-a245-a8ccb282e02f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32150
5622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.321505622
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.214322865
Short name T510
Test name
Test status
Simulation time 149708910 ps
CPU time 0.85 seconds
Started Jun 28 06:15:10 PM PDT 24
Finished Jun 28 06:15:12 PM PDT 24
Peak memory 206196 kb
Host smart-4e041829-d7a0-4c41-aedc-f85abfb881fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21432
2865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.214322865
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.3987723375
Short name T1749
Test name
Test status
Simulation time 270097748 ps
CPU time 0.99 seconds
Started Jun 28 06:15:21 PM PDT 24
Finished Jun 28 06:15:28 PM PDT 24
Peak memory 206208 kb
Host smart-8b26b52e-82da-4e8a-9556-bc82559c2f0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39877
23375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.3987723375
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.3086912693
Short name T1204
Test name
Test status
Simulation time 4997358200 ps
CPU time 44.04 seconds
Started Jun 28 06:15:19 PM PDT 24
Finished Jun 28 06:16:08 PM PDT 24
Peak memory 206392 kb
Host smart-23dd2e78-65f4-47a1-bd1a-07135f8855b4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3086912693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.3086912693
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.1602943822
Short name T412
Test name
Test status
Simulation time 179171304 ps
CPU time 0.79 seconds
Started Jun 28 06:15:17 PM PDT 24
Finished Jun 28 06:15:23 PM PDT 24
Peak memory 206184 kb
Host smart-7e18b1c3-b1ab-4b56-b38a-e1f8ea7c0b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16029
43822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.1602943822
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.2640678979
Short name T405
Test name
Test status
Simulation time 240235666 ps
CPU time 0.92 seconds
Started Jun 28 06:15:10 PM PDT 24
Finished Jun 28 06:15:12 PM PDT 24
Peak memory 206196 kb
Host smart-c9337cdf-49a2-426b-be87-39cf59550b50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26406
78979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.2640678979
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.486386070
Short name T2219
Test name
Test status
Simulation time 3991718255 ps
CPU time 108.49 seconds
Started Jun 28 06:15:20 PM PDT 24
Finished Jun 28 06:17:14 PM PDT 24
Peak memory 206440 kb
Host smart-e1f05eb4-689c-4a28-8b66-21d7dc5e2f34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48638
6070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.486386070
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.3554459785
Short name T1166
Test name
Test status
Simulation time 44582204 ps
CPU time 0.68 seconds
Started Jun 28 06:15:24 PM PDT 24
Finished Jun 28 06:15:30 PM PDT 24
Peak memory 206212 kb
Host smart-a87d039c-dcef-4e1e-b485-ffe7ee983514
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3554459785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.3554459785
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.2279581821
Short name T2433
Test name
Test status
Simulation time 4041360663 ps
CPU time 4.47 seconds
Started Jun 28 06:15:18 PM PDT 24
Finished Jun 28 06:15:27 PM PDT 24
Peak memory 206264 kb
Host smart-a3cba708-6688-41bb-a169-74cdcbce31ba
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2279581821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.2279581821
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.4043989886
Short name T1372
Test name
Test status
Simulation time 13365434835 ps
CPU time 12.66 seconds
Started Jun 28 06:15:36 PM PDT 24
Finished Jun 28 06:15:50 PM PDT 24
Peak memory 206320 kb
Host smart-ff0d1f2b-f798-4cfb-a8e5-d4e961add0c2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4043989886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.4043989886
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.2997336031
Short name T568
Test name
Test status
Simulation time 23356130652 ps
CPU time 22.72 seconds
Started Jun 28 06:15:09 PM PDT 24
Finished Jun 28 06:15:33 PM PDT 24
Peak memory 206316 kb
Host smart-e3177e5c-60da-4017-90f6-45b79bfc74d4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2997336031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.2997336031
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.2923759086
Short name T2079
Test name
Test status
Simulation time 172417227 ps
CPU time 0.86 seconds
Started Jun 28 06:15:13 PM PDT 24
Finished Jun 28 06:15:18 PM PDT 24
Peak memory 206184 kb
Host smart-c04a50f5-a2b1-47d3-805a-40fffd943e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29237
59086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.2923759086
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.2330960592
Short name T1695
Test name
Test status
Simulation time 147506158 ps
CPU time 0.76 seconds
Started Jun 28 06:15:28 PM PDT 24
Finished Jun 28 06:15:34 PM PDT 24
Peak memory 206196 kb
Host smart-8f958765-0d07-4375-a475-1adcf9f00656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23309
60592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.2330960592
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.4154895196
Short name T171
Test name
Test status
Simulation time 271053282 ps
CPU time 0.99 seconds
Started Jun 28 06:15:20 PM PDT 24
Finished Jun 28 06:15:26 PM PDT 24
Peak memory 206188 kb
Host smart-41cfacfc-7409-4930-a72d-598fe3d60f53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41548
95196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.4154895196
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.1433395886
Short name T1226
Test name
Test status
Simulation time 368518585 ps
CPU time 1.04 seconds
Started Jun 28 06:15:19 PM PDT 24
Finished Jun 28 06:15:25 PM PDT 24
Peak memory 206140 kb
Host smart-86fd72fd-f22c-450e-b4b4-a43af42906f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14333
95886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.1433395886
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.726795676
Short name T1108
Test name
Test status
Simulation time 12238051761 ps
CPU time 23.71 seconds
Started Jun 28 06:15:16 PM PDT 24
Finished Jun 28 06:15:44 PM PDT 24
Peak memory 206440 kb
Host smart-4c108691-3066-4163-b839-c48e3c99986a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72679
5676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.726795676
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.3974932009
Short name T1015
Test name
Test status
Simulation time 440378504 ps
CPU time 1.37 seconds
Started Jun 28 06:15:26 PM PDT 24
Finished Jun 28 06:15:33 PM PDT 24
Peak memory 206200 kb
Host smart-05f8799f-bf40-4e29-898e-46cd28b8a9ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39749
32009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.3974932009
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.2734095186
Short name T2153
Test name
Test status
Simulation time 138745475 ps
CPU time 0.8 seconds
Started Jun 28 06:15:39 PM PDT 24
Finished Jun 28 06:15:43 PM PDT 24
Peak memory 206192 kb
Host smart-015c0cd1-acda-413b-bd95-c72d73d2cafe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27340
95186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.2734095186
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.434588416
Short name T2346
Test name
Test status
Simulation time 36397908 ps
CPU time 0.66 seconds
Started Jun 28 06:15:30 PM PDT 24
Finished Jun 28 06:15:36 PM PDT 24
Peak memory 206200 kb
Host smart-64036344-9cbc-453c-ba0d-dadc0cc1d7bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43458
8416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.434588416
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.2063895061
Short name T1126
Test name
Test status
Simulation time 907589326 ps
CPU time 2.18 seconds
Started Jun 28 06:15:16 PM PDT 24
Finished Jun 28 06:15:22 PM PDT 24
Peak memory 206320 kb
Host smart-6b7c9eb5-0832-47d5-91dc-82ca05c61ea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20638
95061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.2063895061
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.2259397542
Short name T1941
Test name
Test status
Simulation time 220792451 ps
CPU time 1.33 seconds
Started Jun 28 06:15:38 PM PDT 24
Finished Jun 28 06:15:41 PM PDT 24
Peak memory 206208 kb
Host smart-986f0b15-459c-4d8b-84b1-3a045dfb8865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22593
97542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.2259397542
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.3068833576
Short name T2511
Test name
Test status
Simulation time 192649878 ps
CPU time 0.86 seconds
Started Jun 28 06:15:44 PM PDT 24
Finished Jun 28 06:15:51 PM PDT 24
Peak memory 206152 kb
Host smart-932cffa1-0df8-441a-8148-fb7f82d7c144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30688
33576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.3068833576
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.3596577738
Short name T603
Test name
Test status
Simulation time 145835803 ps
CPU time 0.78 seconds
Started Jun 28 06:15:21 PM PDT 24
Finished Jun 28 06:15:28 PM PDT 24
Peak memory 206196 kb
Host smart-762c8d2c-ffdb-4c30-ae34-897280d9d8d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35965
77738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.3596577738
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.287754955
Short name T2497
Test name
Test status
Simulation time 194539222 ps
CPU time 0.89 seconds
Started Jun 28 06:15:32 PM PDT 24
Finished Jun 28 06:15:37 PM PDT 24
Peak memory 206208 kb
Host smart-c818c784-66bb-4173-9ecc-4d05c289ac26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28775
4955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.287754955
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_invalid_sync.740465919
Short name T1207
Test name
Test status
Simulation time 6200297585 ps
CPU time 55.02 seconds
Started Jun 28 06:15:22 PM PDT 24
Finished Jun 28 06:16:23 PM PDT 24
Peak memory 206392 kb
Host smart-6ad3d7dc-647f-45c6-8348-f57cfd384af8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=740465919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.740465919
Directory /workspace/47.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.3948794171
Short name T1970
Test name
Test status
Simulation time 247163776 ps
CPU time 0.92 seconds
Started Jun 28 06:15:19 PM PDT 24
Finished Jun 28 06:15:25 PM PDT 24
Peak memory 206172 kb
Host smart-cb2be03c-438f-472e-be61-863475f443a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39487
94171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.3948794171
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.1060441188
Short name T499
Test name
Test status
Simulation time 23310416524 ps
CPU time 26.58 seconds
Started Jun 28 06:15:39 PM PDT 24
Finished Jun 28 06:16:09 PM PDT 24
Peak memory 206312 kb
Host smart-f58f30a8-0769-4001-b5c3-bad42674c15c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10604
41188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.1060441188
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.4127613994
Short name T1306
Test name
Test status
Simulation time 3370822932 ps
CPU time 4.75 seconds
Started Jun 28 06:15:25 PM PDT 24
Finished Jun 28 06:15:36 PM PDT 24
Peak memory 206248 kb
Host smart-305fb6c3-f15e-45c9-a406-ab1e4fc0eb20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41276
13994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.4127613994
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.963117169
Short name T2196
Test name
Test status
Simulation time 12660711800 ps
CPU time 328.51 seconds
Started Jun 28 06:15:33 PM PDT 24
Finished Jun 28 06:21:05 PM PDT 24
Peak memory 206460 kb
Host smart-74c7a35d-a89a-4ce8-ba83-1e04abf38fa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96311
7169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.963117169
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.3983449763
Short name T2142
Test name
Test status
Simulation time 6965183008 ps
CPU time 50.05 seconds
Started Jun 28 06:15:23 PM PDT 24
Finished Jun 28 06:16:19 PM PDT 24
Peak memory 206484 kb
Host smart-09ded6c0-b89d-44e3-a22c-55c7cba4792f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3983449763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.3983449763
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.33249486
Short name T1748
Test name
Test status
Simulation time 245384277 ps
CPU time 0.95 seconds
Started Jun 28 06:15:22 PM PDT 24
Finished Jun 28 06:15:29 PM PDT 24
Peak memory 206212 kb
Host smart-ce95a4ec-4161-4565-af25-542868656ef9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=33249486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.33249486
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.3442289045
Short name T2416
Test name
Test status
Simulation time 187090180 ps
CPU time 0.82 seconds
Started Jun 28 06:15:43 PM PDT 24
Finished Jun 28 06:15:50 PM PDT 24
Peak memory 206160 kb
Host smart-2fb0ee60-ed1e-40d8-9a0b-39621d69acaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34422
89045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.3442289045
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.168592838
Short name T1019
Test name
Test status
Simulation time 5165624631 ps
CPU time 33.2 seconds
Started Jun 28 06:15:30 PM PDT 24
Finished Jun 28 06:16:08 PM PDT 24
Peak memory 206460 kb
Host smart-14c7a64e-66b2-4e02-bf7c-fec56d124576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16859
2838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.168592838
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.1507583471
Short name T363
Test name
Test status
Simulation time 5105236176 ps
CPU time 47.23 seconds
Started Jun 28 06:15:23 PM PDT 24
Finished Jun 28 06:16:16 PM PDT 24
Peak memory 206320 kb
Host smart-6a6a850b-272b-477d-824b-ba37edec7853
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1507583471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.1507583471
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.2383416019
Short name T1721
Test name
Test status
Simulation time 154909424 ps
CPU time 0.77 seconds
Started Jun 28 06:15:40 PM PDT 24
Finished Jun 28 06:15:44 PM PDT 24
Peak memory 206216 kb
Host smart-c66b1da0-2bfd-48f1-9189-2d9789808ded
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2383416019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.2383416019
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.1048509289
Short name T320
Test name
Test status
Simulation time 140020238 ps
CPU time 0.83 seconds
Started Jun 28 06:15:20 PM PDT 24
Finished Jun 28 06:15:27 PM PDT 24
Peak memory 206196 kb
Host smart-825735a5-1c80-46f4-9c40-142fc2694414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10485
09289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.1048509289
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.2915678026
Short name T110
Test name
Test status
Simulation time 249933237 ps
CPU time 0.86 seconds
Started Jun 28 06:15:40 PM PDT 24
Finished Jun 28 06:15:44 PM PDT 24
Peak memory 206192 kb
Host smart-55eccd4d-7052-4bbf-95b3-5c808fefdf9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29156
78026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.2915678026
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.1863921264
Short name T2371
Test name
Test status
Simulation time 180286961 ps
CPU time 0.84 seconds
Started Jun 28 06:15:26 PM PDT 24
Finished Jun 28 06:15:32 PM PDT 24
Peak memory 206208 kb
Host smart-f81ed047-bca2-49fb-b969-1e703dda206d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18639
21264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.1863921264
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.1308640745
Short name T958
Test name
Test status
Simulation time 141857046 ps
CPU time 0.77 seconds
Started Jun 28 06:15:36 PM PDT 24
Finished Jun 28 06:15:38 PM PDT 24
Peak memory 206148 kb
Host smart-dda62040-834c-41d2-bfd9-746239a31a43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13086
40745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.1308640745
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.2486900178
Short name T1475
Test name
Test status
Simulation time 211311194 ps
CPU time 0.82 seconds
Started Jun 28 06:15:26 PM PDT 24
Finished Jun 28 06:15:32 PM PDT 24
Peak memory 206208 kb
Host smart-5c27068d-b3f9-40ce-af90-dc9ad8915f65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24869
00178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.2486900178
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.983171181
Short name T184
Test name
Test status
Simulation time 166432249 ps
CPU time 0.8 seconds
Started Jun 28 06:15:25 PM PDT 24
Finished Jun 28 06:15:32 PM PDT 24
Peak memory 206216 kb
Host smart-c41b7f62-2a17-409d-8df2-fc79f6607cc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98317
1181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.983171181
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.333149730
Short name T1043
Test name
Test status
Simulation time 215972705 ps
CPU time 0.88 seconds
Started Jun 28 06:15:25 PM PDT 24
Finished Jun 28 06:15:32 PM PDT 24
Peak memory 206212 kb
Host smart-af96ca12-b402-4cc1-a11a-2793bd082e3b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=333149730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.333149730
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.738858987
Short name T1149
Test name
Test status
Simulation time 199176859 ps
CPU time 0.8 seconds
Started Jun 28 06:15:28 PM PDT 24
Finished Jun 28 06:15:35 PM PDT 24
Peak memory 206216 kb
Host smart-1070c67d-c53a-45b9-ad27-3628c5235d23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73885
8987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.738858987
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.3197315342
Short name T659
Test name
Test status
Simulation time 52634054 ps
CPU time 0.7 seconds
Started Jun 28 06:15:23 PM PDT 24
Finished Jun 28 06:15:29 PM PDT 24
Peak memory 206100 kb
Host smart-56b1e1ea-8791-4f0f-b2d5-bbf260097d3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31973
15342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.3197315342
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.1094948461
Short name T970
Test name
Test status
Simulation time 16198091028 ps
CPU time 34.51 seconds
Started Jun 28 06:15:24 PM PDT 24
Finished Jun 28 06:16:05 PM PDT 24
Peak memory 206424 kb
Host smart-8da1d26f-a3cc-4d79-af1d-7890e4e92ad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10949
48461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.1094948461
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.1558294621
Short name T2439
Test name
Test status
Simulation time 194285326 ps
CPU time 0.91 seconds
Started Jun 28 06:15:20 PM PDT 24
Finished Jun 28 06:15:27 PM PDT 24
Peak memory 206324 kb
Host smart-f6cc5307-03a2-4554-964b-16209df62847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15582
94621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.1558294621
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.1630368668
Short name T1301
Test name
Test status
Simulation time 184592786 ps
CPU time 0.79 seconds
Started Jun 28 06:15:42 PM PDT 24
Finished Jun 28 06:15:48 PM PDT 24
Peak memory 206208 kb
Host smart-617696d3-7ee6-4476-bab4-cb77b8ca564e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16303
68668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.1630368668
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.628135973
Short name T2418
Test name
Test status
Simulation time 181215264 ps
CPU time 0.8 seconds
Started Jun 28 06:15:42 PM PDT 24
Finished Jun 28 06:15:48 PM PDT 24
Peak memory 206212 kb
Host smart-8b89ad67-9c28-4eb0-90b1-3631c82e5be1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62813
5973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.628135973
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.396645793
Short name T319
Test name
Test status
Simulation time 214534334 ps
CPU time 0.94 seconds
Started Jun 28 06:15:19 PM PDT 24
Finished Jun 28 06:15:25 PM PDT 24
Peak memory 206320 kb
Host smart-6e150960-7459-45d2-8983-bd7eb2cc4388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39664
5793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.396645793
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.864782737
Short name T2360
Test name
Test status
Simulation time 171416380 ps
CPU time 0.8 seconds
Started Jun 28 06:15:38 PM PDT 24
Finished Jun 28 06:15:41 PM PDT 24
Peak memory 206156 kb
Host smart-935fc898-2070-41b8-9777-fd03e355bc94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86478
2737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.864782737
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.2013503509
Short name T996
Test name
Test status
Simulation time 191466743 ps
CPU time 0.78 seconds
Started Jun 28 06:15:38 PM PDT 24
Finished Jun 28 06:15:40 PM PDT 24
Peak memory 206152 kb
Host smart-20c35557-f4ec-453c-a86d-321b53206b84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20135
03509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.2013503509
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.287989657
Short name T1161
Test name
Test status
Simulation time 150134933 ps
CPU time 0.81 seconds
Started Jun 28 06:15:45 PM PDT 24
Finished Jun 28 06:15:52 PM PDT 24
Peak memory 206160 kb
Host smart-81483751-a815-41ca-9ea5-501575abc393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28798
9657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.287989657
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.1445839774
Short name T1815
Test name
Test status
Simulation time 263309287 ps
CPU time 0.98 seconds
Started Jun 28 06:15:39 PM PDT 24
Finished Jun 28 06:15:42 PM PDT 24
Peak memory 206108 kb
Host smart-9f3a04a8-2672-43a4-807a-0428931d8267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14458
39774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.1445839774
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.1090761683
Short name T1143
Test name
Test status
Simulation time 3515347232 ps
CPU time 23.86 seconds
Started Jun 28 06:15:42 PM PDT 24
Finished Jun 28 06:16:11 PM PDT 24
Peak memory 206392 kb
Host smart-5db9702a-3e3e-4a15-9432-0877d9787a16
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1090761683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.1090761683
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.4456841
Short name T910
Test name
Test status
Simulation time 197706287 ps
CPU time 0.81 seconds
Started Jun 28 06:15:38 PM PDT 24
Finished Jun 28 06:15:41 PM PDT 24
Peak memory 206184 kb
Host smart-270bf2f1-0eae-4ca1-b2ae-0633a05b1f9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44568
41 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.4456841
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.679055814
Short name T1817
Test name
Test status
Simulation time 137685557 ps
CPU time 0.75 seconds
Started Jun 28 06:15:25 PM PDT 24
Finished Jun 28 06:15:32 PM PDT 24
Peak memory 206188 kb
Host smart-00e09bc8-2d67-4d2f-b9b8-bd97b7f676dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67905
5814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.679055814
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.2054987506
Short name T2052
Test name
Test status
Simulation time 5736478468 ps
CPU time 158.8 seconds
Started Jun 28 06:15:37 PM PDT 24
Finished Jun 28 06:18:18 PM PDT 24
Peak memory 206392 kb
Host smart-5d6741d8-a03f-46fd-98f2-7c52d03ce26f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20549
87506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.2054987506
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.2694028578
Short name T1196
Test name
Test status
Simulation time 43029864 ps
CPU time 0.66 seconds
Started Jun 28 06:15:42 PM PDT 24
Finished Jun 28 06:15:49 PM PDT 24
Peak memory 206216 kb
Host smart-9e6b2266-7d0a-40e9-8a83-22f83c438ab6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2694028578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.2694028578
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.2926342151
Short name T2415
Test name
Test status
Simulation time 3705491414 ps
CPU time 5.33 seconds
Started Jun 28 06:15:25 PM PDT 24
Finished Jun 28 06:15:36 PM PDT 24
Peak memory 206272 kb
Host smart-a99046b0-2da1-45d7-95d0-dde96661eb5a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2926342151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.2926342151
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.1312154877
Short name T2481
Test name
Test status
Simulation time 13387717522 ps
CPU time 12.52 seconds
Started Jun 28 06:15:19 PM PDT 24
Finished Jun 28 06:15:37 PM PDT 24
Peak memory 206264 kb
Host smart-b31f01f0-ef19-4540-b66f-70ed610fc20e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1312154877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.1312154877
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.2820084916
Short name T1536
Test name
Test status
Simulation time 23306155728 ps
CPU time 22.02 seconds
Started Jun 28 06:15:40 PM PDT 24
Finished Jun 28 06:16:05 PM PDT 24
Peak memory 206396 kb
Host smart-71d087e9-3a1e-4254-9f53-193b37cd5392
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2820084916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.2820084916
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.821882893
Short name T821
Test name
Test status
Simulation time 178659683 ps
CPU time 0.85 seconds
Started Jun 28 06:15:38 PM PDT 24
Finished Jun 28 06:15:41 PM PDT 24
Peak memory 206180 kb
Host smart-77f3ebbd-7853-437c-a853-178953eb605a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82188
2893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.821882893
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.2953894864
Short name T2192
Test name
Test status
Simulation time 202525072 ps
CPU time 0.79 seconds
Started Jun 28 06:15:40 PM PDT 24
Finished Jun 28 06:15:44 PM PDT 24
Peak memory 206192 kb
Host smart-ea4271f3-eb3e-4800-942c-a4fda9c26b6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29538
94864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.2953894864
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.3098114420
Short name T183
Test name
Test status
Simulation time 466256927 ps
CPU time 1.41 seconds
Started Jun 28 06:15:24 PM PDT 24
Finished Jun 28 06:15:32 PM PDT 24
Peak memory 206192 kb
Host smart-388fe49a-ce59-416d-aa99-ab632316d328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30981
14420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.3098114420
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.4232087870
Short name T2563
Test name
Test status
Simulation time 644943333 ps
CPU time 1.56 seconds
Started Jun 28 06:15:25 PM PDT 24
Finished Jun 28 06:15:33 PM PDT 24
Peak memory 206192 kb
Host smart-5a43b9c0-396d-457b-9af4-208ed3e9ecfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42320
87870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.4232087870
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.1261691160
Short name T848
Test name
Test status
Simulation time 9020041373 ps
CPU time 17.31 seconds
Started Jun 28 06:15:20 PM PDT 24
Finished Jun 28 06:15:44 PM PDT 24
Peak memory 206408 kb
Host smart-bf0f2869-29e8-4a15-851a-fea6b663cf57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12616
91160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.1261691160
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.35174663
Short name T1472
Test name
Test status
Simulation time 369318308 ps
CPU time 1.14 seconds
Started Jun 28 06:15:40 PM PDT 24
Finished Jun 28 06:15:44 PM PDT 24
Peak memory 206184 kb
Host smart-ea9430e2-4bec-491e-845c-ec2ecad02019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35174
663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.35174663
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.3903504661
Short name T2175
Test name
Test status
Simulation time 207998277 ps
CPU time 0.84 seconds
Started Jun 28 06:15:20 PM PDT 24
Finished Jun 28 06:15:26 PM PDT 24
Peak memory 206324 kb
Host smart-1fab0642-e732-44ce-879e-67a0877ea333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39035
04661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.3903504661
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.3039821574
Short name T896
Test name
Test status
Simulation time 56679965 ps
CPU time 0.67 seconds
Started Jun 28 06:15:20 PM PDT 24
Finished Jun 28 06:15:26 PM PDT 24
Peak memory 206312 kb
Host smart-ab4dde44-6f5f-457b-8024-606c943b9a23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30398
21574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.3039821574
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.1856275486
Short name T1858
Test name
Test status
Simulation time 860891415 ps
CPU time 2.19 seconds
Started Jun 28 06:15:28 PM PDT 24
Finished Jun 28 06:15:36 PM PDT 24
Peak memory 206312 kb
Host smart-21d2f73e-9957-43fd-a7f3-f9c3a1f0a351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18562
75486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.1856275486
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.3973114122
Short name T2193
Test name
Test status
Simulation time 163964606 ps
CPU time 1.15 seconds
Started Jun 28 06:15:28 PM PDT 24
Finished Jun 28 06:15:35 PM PDT 24
Peak memory 206332 kb
Host smart-4c255421-2148-4542-a30c-fd8a53371505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39731
14122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.3973114122
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.378599438
Short name T2213
Test name
Test status
Simulation time 238844154 ps
CPU time 0.94 seconds
Started Jun 28 06:15:26 PM PDT 24
Finished Jun 28 06:15:33 PM PDT 24
Peak memory 206208 kb
Host smart-576ac3d5-965d-429e-9f5b-44037bebe609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37859
9438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.378599438
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.2363618941
Short name T1257
Test name
Test status
Simulation time 139775615 ps
CPU time 0.75 seconds
Started Jun 28 06:15:45 PM PDT 24
Finished Jun 28 06:15:51 PM PDT 24
Peak memory 206172 kb
Host smart-d87091ad-aaa6-492d-bb92-54be7e538adb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23636
18941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.2363618941
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.4138257605
Short name T2517
Test name
Test status
Simulation time 235041622 ps
CPU time 0.88 seconds
Started Jun 28 06:15:43 PM PDT 24
Finished Jun 28 06:15:50 PM PDT 24
Peak memory 206212 kb
Host smart-0e2fed69-1696-4dbd-91ac-fbffdf2dc7d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41382
57605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.4138257605
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_invalid_sync.2636618179
Short name T806
Test name
Test status
Simulation time 6241718991 ps
CPU time 59.2 seconds
Started Jun 28 06:15:39 PM PDT 24
Finished Jun 28 06:16:40 PM PDT 24
Peak memory 206412 kb
Host smart-c11951d2-bfaf-4e45-b241-08df7f53243d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2636618179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.2636618179
Directory /workspace/48.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.2747580187
Short name T459
Test name
Test status
Simulation time 198534077 ps
CPU time 0.89 seconds
Started Jun 28 06:15:28 PM PDT 24
Finished Jun 28 06:15:35 PM PDT 24
Peak memory 206196 kb
Host smart-c55851f3-f228-4d06-8705-048bf492b1b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27475
80187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.2747580187
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.1651986388
Short name T870
Test name
Test status
Simulation time 23259404218 ps
CPU time 24.06 seconds
Started Jun 28 06:15:30 PM PDT 24
Finished Jun 28 06:15:59 PM PDT 24
Peak memory 206304 kb
Host smart-124e5a0f-2a85-4ca0-a9e7-b4b5a38a0e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16519
86388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.1651986388
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.1117015763
Short name T1038
Test name
Test status
Simulation time 3295394998 ps
CPU time 4.29 seconds
Started Jun 28 06:15:28 PM PDT 24
Finished Jun 28 06:15:38 PM PDT 24
Peak memory 206256 kb
Host smart-0b641bac-87fd-4e39-9f85-86b4bbbdd22f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11170
15763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.1117015763
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.1200452043
Short name T1809
Test name
Test status
Simulation time 6316324193 ps
CPU time 166.22 seconds
Started Jun 28 06:15:28 PM PDT 24
Finished Jun 28 06:18:20 PM PDT 24
Peak memory 206472 kb
Host smart-ccb55f12-602a-4f66-83a7-04430c27a7eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12004
52043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.1200452043
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.3480156415
Short name T792
Test name
Test status
Simulation time 5375177195 ps
CPU time 145.8 seconds
Started Jun 28 06:15:17 PM PDT 24
Finished Jun 28 06:17:48 PM PDT 24
Peak memory 206456 kb
Host smart-c633ae0b-8439-4bc8-9e65-3417f9c5f778
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3480156415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.3480156415
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.3904012093
Short name T334
Test name
Test status
Simulation time 248590035 ps
CPU time 0.89 seconds
Started Jun 28 06:15:45 PM PDT 24
Finished Jun 28 06:15:52 PM PDT 24
Peak memory 206184 kb
Host smart-906dc8b2-4148-4bd7-9f7d-b0e4c19006e0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3904012093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.3904012093
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.1700531925
Short name T1411
Test name
Test status
Simulation time 264768959 ps
CPU time 0.92 seconds
Started Jun 28 06:15:18 PM PDT 24
Finished Jun 28 06:15:25 PM PDT 24
Peak memory 206172 kb
Host smart-7b95c786-5e6e-4b1f-bc35-ed81e0fff6d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17005
31925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.1700531925
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.488709472
Short name T1400
Test name
Test status
Simulation time 6380534569 ps
CPU time 57.27 seconds
Started Jun 28 06:15:42 PM PDT 24
Finished Jun 28 06:16:45 PM PDT 24
Peak memory 206380 kb
Host smart-eeffb656-3064-4870-b09a-1793ec3b1891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48870
9472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.488709472
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.3859101403
Short name T2113
Test name
Test status
Simulation time 5777951053 ps
CPU time 51.81 seconds
Started Jun 28 06:15:41 PM PDT 24
Finished Jun 28 06:16:38 PM PDT 24
Peak memory 206408 kb
Host smart-5ef4bcf4-b7e9-4081-9ad3-bca844b993c8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3859101403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.3859101403
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.4048066714
Short name T1270
Test name
Test status
Simulation time 186710609 ps
CPU time 0.84 seconds
Started Jun 28 06:15:27 PM PDT 24
Finished Jun 28 06:15:33 PM PDT 24
Peak memory 206188 kb
Host smart-2b0c511c-9eaf-48e9-b60d-53eeb7f61fd0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4048066714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.4048066714
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.3726289407
Short name T1481
Test name
Test status
Simulation time 141513189 ps
CPU time 0.86 seconds
Started Jun 28 06:15:45 PM PDT 24
Finished Jun 28 06:15:52 PM PDT 24
Peak memory 206172 kb
Host smart-86488a21-e181-4fbd-b122-e68daf5fd25b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37262
89407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.3726289407
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.3123360765
Short name T130
Test name
Test status
Simulation time 179166584 ps
CPU time 0.83 seconds
Started Jun 28 06:15:44 PM PDT 24
Finished Jun 28 06:15:50 PM PDT 24
Peak memory 206188 kb
Host smart-ddf4ab5a-8382-495c-90b3-35903c785253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31233
60765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.3123360765
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.195383000
Short name T1463
Test name
Test status
Simulation time 180218971 ps
CPU time 0.83 seconds
Started Jun 28 06:15:43 PM PDT 24
Finished Jun 28 06:15:50 PM PDT 24
Peak memory 206192 kb
Host smart-dde59de5-3412-4156-b320-c7d864198bb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19538
3000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.195383000
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.1646887051
Short name T2329
Test name
Test status
Simulation time 179880587 ps
CPU time 0.81 seconds
Started Jun 28 06:15:41 PM PDT 24
Finished Jun 28 06:15:46 PM PDT 24
Peak memory 206188 kb
Host smart-b9e867aa-b013-4edb-ac60-7a0b24f52936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16468
87051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.1646887051
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.1076511244
Short name T1072
Test name
Test status
Simulation time 154711374 ps
CPU time 0.79 seconds
Started Jun 28 06:15:29 PM PDT 24
Finished Jun 28 06:15:35 PM PDT 24
Peak memory 206216 kb
Host smart-7080e609-ff6d-45c5-9d02-bf82757b2b20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10765
11244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.1076511244
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.1284979730
Short name T1772
Test name
Test status
Simulation time 157189324 ps
CPU time 0.79 seconds
Started Jun 28 06:15:40 PM PDT 24
Finished Jun 28 06:15:45 PM PDT 24
Peak memory 206204 kb
Host smart-58c4689e-8f6e-43de-bfff-d46864e99e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12849
79730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.1284979730
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.2610983572
Short name T980
Test name
Test status
Simulation time 235503476 ps
CPU time 0.94 seconds
Started Jun 28 06:15:42 PM PDT 24
Finished Jun 28 06:15:47 PM PDT 24
Peak memory 206208 kb
Host smart-d698dd94-5172-4091-a81c-399647e08724
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2610983572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.2610983572
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.2676271291
Short name T989
Test name
Test status
Simulation time 150063564 ps
CPU time 0.74 seconds
Started Jun 28 06:15:28 PM PDT 24
Finished Jun 28 06:15:34 PM PDT 24
Peak memory 206140 kb
Host smart-c946c6e2-1d8a-4260-a1c2-bbf9a7ebe7fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26762
71291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.2676271291
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.4239582567
Short name T402
Test name
Test status
Simulation time 56161008 ps
CPU time 0.7 seconds
Started Jun 28 06:15:41 PM PDT 24
Finished Jun 28 06:15:47 PM PDT 24
Peak memory 206188 kb
Host smart-4f024105-ab51-4b2f-a296-38ac716c1e50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42395
82567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.4239582567
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.1403829979
Short name T263
Test name
Test status
Simulation time 8155845336 ps
CPU time 20.09 seconds
Started Jun 28 06:15:46 PM PDT 24
Finished Jun 28 06:16:12 PM PDT 24
Peak memory 206412 kb
Host smart-a394362b-7871-4092-b152-350e6ed2965b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14038
29979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.1403829979
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.3259518624
Short name T1876
Test name
Test status
Simulation time 185795221 ps
CPU time 0.82 seconds
Started Jun 28 06:15:27 PM PDT 24
Finished Jun 28 06:15:33 PM PDT 24
Peak memory 206188 kb
Host smart-eb24f04e-5537-4e5c-9ab9-8a9b372316e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32595
18624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.3259518624
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.894707428
Short name T2041
Test name
Test status
Simulation time 269504962 ps
CPU time 0.93 seconds
Started Jun 28 06:15:38 PM PDT 24
Finished Jun 28 06:15:41 PM PDT 24
Peak memory 206148 kb
Host smart-33a23b12-e4a5-420c-a8c9-56bb57cc1e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89470
7428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.894707428
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.3221468694
Short name T1332
Test name
Test status
Simulation time 174776834 ps
CPU time 0.81 seconds
Started Jun 28 06:15:27 PM PDT 24
Finished Jun 28 06:15:34 PM PDT 24
Peak memory 206216 kb
Host smart-781996ec-890a-426f-bee2-32010ce742fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32214
68694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.3221468694
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.433800430
Short name T394
Test name
Test status
Simulation time 156712907 ps
CPU time 0.8 seconds
Started Jun 28 06:15:40 PM PDT 24
Finished Jun 28 06:15:45 PM PDT 24
Peak memory 206120 kb
Host smart-b1539524-b125-4b14-8425-6a5ee0147e4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43380
0430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.433800430
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.2822876261
Short name T506
Test name
Test status
Simulation time 190958693 ps
CPU time 0.85 seconds
Started Jun 28 06:15:39 PM PDT 24
Finished Jun 28 06:15:43 PM PDT 24
Peak memory 206172 kb
Host smart-e038a522-e285-4187-b11e-2b06ecdc43fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28228
76261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.2822876261
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.3232192967
Short name T1333
Test name
Test status
Simulation time 175096355 ps
CPU time 0.82 seconds
Started Jun 28 06:15:37 PM PDT 24
Finished Jun 28 06:15:40 PM PDT 24
Peak memory 206192 kb
Host smart-b2ecabed-3069-42e6-80c1-25bf391a83c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32321
92967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.3232192967
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.248169283
Short name T1840
Test name
Test status
Simulation time 146286689 ps
CPU time 0.78 seconds
Started Jun 28 06:15:42 PM PDT 24
Finished Jun 28 06:15:48 PM PDT 24
Peak memory 206352 kb
Host smart-09dc6a52-efe1-4108-80fd-cf0fbdeb6387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24816
9283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.248169283
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.1264616722
Short name T654
Test name
Test status
Simulation time 283296415 ps
CPU time 1.09 seconds
Started Jun 28 06:15:42 PM PDT 24
Finished Jun 28 06:15:48 PM PDT 24
Peak memory 206152 kb
Host smart-df5b5a73-9173-4ac2-9588-12847edcf69d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12646
16722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.1264616722
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.950493642
Short name T258
Test name
Test status
Simulation time 5008744565 ps
CPU time 135.3 seconds
Started Jun 28 06:15:45 PM PDT 24
Finished Jun 28 06:18:06 PM PDT 24
Peak memory 206492 kb
Host smart-7c3afd18-3906-43ea-a1a6-65b87b90e4a4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=950493642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.950493642
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.1404334989
Short name T623
Test name
Test status
Simulation time 158025163 ps
CPU time 0.81 seconds
Started Jun 28 06:15:37 PM PDT 24
Finished Jun 28 06:15:39 PM PDT 24
Peak memory 206216 kb
Host smart-d83edd7b-bccb-4c92-adfc-3d7b06c4573b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14043
34989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.1404334989
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.4236395594
Short name T2118
Test name
Test status
Simulation time 190399801 ps
CPU time 0.85 seconds
Started Jun 28 06:15:43 PM PDT 24
Finished Jun 28 06:15:50 PM PDT 24
Peak memory 206196 kb
Host smart-0ae542ca-d841-4af2-a9aa-913723c308ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42363
95594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.4236395594
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.1480521583
Short name T2419
Test name
Test status
Simulation time 4255884202 ps
CPU time 38.17 seconds
Started Jun 28 06:15:46 PM PDT 24
Finished Jun 28 06:16:30 PM PDT 24
Peak memory 206388 kb
Host smart-e0037a50-7467-4540-a048-77fe80bd6d71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14805
21583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.1480521583
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.3291971119
Short name T518
Test name
Test status
Simulation time 76298628 ps
CPU time 0.68 seconds
Started Jun 28 06:15:44 PM PDT 24
Finished Jun 28 06:15:51 PM PDT 24
Peak memory 206192 kb
Host smart-f87132c9-5fbd-46f3-99d3-37e8b384ddcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3291971119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.3291971119
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.459096448
Short name T2387
Test name
Test status
Simulation time 4093276012 ps
CPU time 5.7 seconds
Started Jun 28 06:15:30 PM PDT 24
Finished Jun 28 06:15:41 PM PDT 24
Peak memory 206404 kb
Host smart-4efe3220-4810-4f24-8101-2543dc99aa28
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=459096448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.459096448
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.3642471120
Short name T757
Test name
Test status
Simulation time 13375639938 ps
CPU time 16.04 seconds
Started Jun 28 06:15:28 PM PDT 24
Finished Jun 28 06:15:50 PM PDT 24
Peak memory 206396 kb
Host smart-9b42c675-aae2-424a-baae-a4006f1ea326
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3642471120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.3642471120
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.1351628736
Short name T2075
Test name
Test status
Simulation time 23406308124 ps
CPU time 23.35 seconds
Started Jun 28 06:15:30 PM PDT 24
Finished Jun 28 06:15:58 PM PDT 24
Peak memory 206392 kb
Host smart-a50626bc-a116-4b93-b79d-ea1b3fd593bf
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1351628736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.1351628736
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.2376171770
Short name T2495
Test name
Test status
Simulation time 176909570 ps
CPU time 0.86 seconds
Started Jun 28 06:15:44 PM PDT 24
Finished Jun 28 06:15:50 PM PDT 24
Peak memory 206164 kb
Host smart-f8a1c0a5-e38c-4f95-8005-cf9d854ec6d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23761
71770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.2376171770
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.415782408
Short name T2350
Test name
Test status
Simulation time 220991880 ps
CPU time 0.87 seconds
Started Jun 28 06:15:28 PM PDT 24
Finished Jun 28 06:15:35 PM PDT 24
Peak memory 206192 kb
Host smart-315ff51a-0902-4493-834c-68c34cc792ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41578
2408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.415782408
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.1856824342
Short name T1369
Test name
Test status
Simulation time 479040930 ps
CPU time 1.51 seconds
Started Jun 28 06:15:28 PM PDT 24
Finished Jun 28 06:15:35 PM PDT 24
Peak memory 206188 kb
Host smart-88e80fb8-4873-4403-8646-a1b373aa1b10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18568
24342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.1856824342
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.3035328528
Short name T795
Test name
Test status
Simulation time 869339822 ps
CPU time 1.88 seconds
Started Jun 28 06:15:39 PM PDT 24
Finished Jun 28 06:15:42 PM PDT 24
Peak memory 206260 kb
Host smart-1840ccb8-e3cc-47ab-8027-6599b66541d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30353
28528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.3035328528
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.366584062
Short name T1447
Test name
Test status
Simulation time 14459110264 ps
CPU time 28.44 seconds
Started Jun 28 06:15:39 PM PDT 24
Finished Jun 28 06:16:10 PM PDT 24
Peak memory 206440 kb
Host smart-ebbb307e-d251-4f24-9df2-d48a93f8dcf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36658
4062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.366584062
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.3874356742
Short name T2055
Test name
Test status
Simulation time 428606156 ps
CPU time 1.36 seconds
Started Jun 28 06:15:29 PM PDT 24
Finished Jun 28 06:15:36 PM PDT 24
Peak memory 206200 kb
Host smart-89ca6ccd-c5de-4685-a684-c99a52cd8585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38743
56742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.3874356742
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.2015971407
Short name T1308
Test name
Test status
Simulation time 149437000 ps
CPU time 0.77 seconds
Started Jun 28 06:15:45 PM PDT 24
Finished Jun 28 06:15:52 PM PDT 24
Peak memory 206188 kb
Host smart-acc96651-6be0-43d1-9fee-34f7af05efe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20159
71407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.2015971407
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.1186242545
Short name T913
Test name
Test status
Simulation time 49158089 ps
CPU time 0.7 seconds
Started Jun 28 06:15:33 PM PDT 24
Finished Jun 28 06:15:37 PM PDT 24
Peak memory 206188 kb
Host smart-2eafc965-47c7-4220-80ab-fb38f16621f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11862
42545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.1186242545
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.2770698501
Short name T1451
Test name
Test status
Simulation time 875937777 ps
CPU time 2.25 seconds
Started Jun 28 06:15:41 PM PDT 24
Finished Jun 28 06:15:49 PM PDT 24
Peak memory 206316 kb
Host smart-5b24d51e-fcd5-4d62-affe-cdcf662d1877
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27706
98501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.2770698501
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.378695657
Short name T2516
Test name
Test status
Simulation time 195385686 ps
CPU time 1.79 seconds
Started Jun 28 06:15:43 PM PDT 24
Finished Jun 28 06:15:50 PM PDT 24
Peak memory 206268 kb
Host smart-f06ae7a2-94f4-41b7-980a-ddaf14247ecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37869
5657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.378695657
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.2720021137
Short name T2502
Test name
Test status
Simulation time 162730598 ps
CPU time 0.83 seconds
Started Jun 28 06:15:43 PM PDT 24
Finished Jun 28 06:15:50 PM PDT 24
Peak memory 206196 kb
Host smart-75cb22ed-36f3-4e6e-8dc4-db7ab38c23a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27200
21137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.2720021137
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.2065461976
Short name T797
Test name
Test status
Simulation time 156205913 ps
CPU time 0.74 seconds
Started Jun 28 06:15:41 PM PDT 24
Finished Jun 28 06:15:46 PM PDT 24
Peak memory 206212 kb
Host smart-38ecdb9b-371b-4a75-a915-196f360dbf54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20654
61976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.2065461976
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.2874235820
Short name T647
Test name
Test status
Simulation time 158177390 ps
CPU time 0.8 seconds
Started Jun 28 06:16:08 PM PDT 24
Finished Jun 28 06:16:12 PM PDT 24
Peak memory 206204 kb
Host smart-5f97fb6f-3924-4d50-823f-cc9af193374e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28742
35820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.2874235820
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_invalid_sync.3720320803
Short name T70
Test name
Test status
Simulation time 7707802211 ps
CPU time 208.29 seconds
Started Jun 28 06:15:39 PM PDT 24
Finished Jun 28 06:19:09 PM PDT 24
Peak memory 206492 kb
Host smart-3a9a4ee6-6e6a-40da-9db5-7545bf49c8b2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3720320803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.3720320803
Directory /workspace/49.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.375870845
Short name T865
Test name
Test status
Simulation time 174769947 ps
CPU time 0.8 seconds
Started Jun 28 06:15:47 PM PDT 24
Finished Jun 28 06:15:53 PM PDT 24
Peak memory 206192 kb
Host smart-b74a8b31-c4fc-4a02-8e78-898908ecf23f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37587
0845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.375870845
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.2475482430
Short name T1704
Test name
Test status
Simulation time 23308114866 ps
CPU time 26.81 seconds
Started Jun 28 06:15:44 PM PDT 24
Finished Jun 28 06:16:16 PM PDT 24
Peak memory 206288 kb
Host smart-25778c79-b473-4f67-b4ba-10dd48626b90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24754
82430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.2475482430
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.2502830189
Short name T732
Test name
Test status
Simulation time 3298125236 ps
CPU time 3.53 seconds
Started Jun 28 06:15:52 PM PDT 24
Finished Jun 28 06:15:59 PM PDT 24
Peak memory 206256 kb
Host smart-88f7206b-90c1-410f-b319-cd97f614f9ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25028
30189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.2502830189
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.3011405736
Short name T2566
Test name
Test status
Simulation time 4537404789 ps
CPU time 42.86 seconds
Started Jun 28 06:15:41 PM PDT 24
Finished Jun 28 06:16:28 PM PDT 24
Peak memory 206400 kb
Host smart-21b04cc4-d3e5-4a2a-bc62-e2de194340c8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3011405736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.3011405736
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.1965239169
Short name T411
Test name
Test status
Simulation time 302836479 ps
CPU time 0.97 seconds
Started Jun 28 06:15:41 PM PDT 24
Finished Jun 28 06:15:46 PM PDT 24
Peak memory 206192 kb
Host smart-85d4d3f5-3a68-412f-a1f5-387291b39ed4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1965239169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.1965239169
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.3337336791
Short name T475
Test name
Test status
Simulation time 181798821 ps
CPU time 0.84 seconds
Started Jun 28 06:15:42 PM PDT 24
Finished Jun 28 06:15:48 PM PDT 24
Peak memory 206204 kb
Host smart-398d5139-1938-484e-b833-1523a2159663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33373
36791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.3337336791
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.2510792956
Short name T2120
Test name
Test status
Simulation time 4392119265 ps
CPU time 122.98 seconds
Started Jun 28 06:15:50 PM PDT 24
Finished Jun 28 06:17:57 PM PDT 24
Peak memory 206456 kb
Host smart-65179f23-7a09-49f2-9770-f849a339c9d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25107
92956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.2510792956
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.3264136559
Short name T1091
Test name
Test status
Simulation time 4935909717 ps
CPU time 139.14 seconds
Started Jun 28 06:15:42 PM PDT 24
Finished Jun 28 06:18:07 PM PDT 24
Peak memory 206452 kb
Host smart-b4e7823b-ecc5-4533-aa33-29fcbb47ca53
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3264136559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.3264136559
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.944158887
Short name T283
Test name
Test status
Simulation time 197923397 ps
CPU time 0.88 seconds
Started Jun 28 06:15:40 PM PDT 24
Finished Jun 28 06:15:44 PM PDT 24
Peak memory 206216 kb
Host smart-0ceab899-7b98-483b-ba73-94aa8c2dd47c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=944158887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.944158887
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.2904153254
Short name T1421
Test name
Test status
Simulation time 145966758 ps
CPU time 0.83 seconds
Started Jun 28 06:15:47 PM PDT 24
Finished Jun 28 06:15:53 PM PDT 24
Peak memory 206180 kb
Host smart-dc88c503-fade-43d6-a72d-b4b924f3519a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29041
53254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.2904153254
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.4059923968
Short name T123
Test name
Test status
Simulation time 181200044 ps
CPU time 0.82 seconds
Started Jun 28 06:15:51 PM PDT 24
Finished Jun 28 06:15:55 PM PDT 24
Peak memory 206180 kb
Host smart-e93d663d-50c2-4f2f-9253-434d35e88c64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40599
23968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.4059923968
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.3455457504
Short name T839
Test name
Test status
Simulation time 149945916 ps
CPU time 0.83 seconds
Started Jun 28 06:15:43 PM PDT 24
Finished Jun 28 06:15:49 PM PDT 24
Peak memory 206196 kb
Host smart-3a87a1b3-797d-4dd1-bd43-8a2e48e82609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34554
57504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.3455457504
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.2256492335
Short name T1373
Test name
Test status
Simulation time 192170345 ps
CPU time 0.79 seconds
Started Jun 28 06:15:43 PM PDT 24
Finished Jun 28 06:15:50 PM PDT 24
Peak memory 206196 kb
Host smart-41807b58-fd0d-4735-90cf-dbd496b5afdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22564
92335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.2256492335
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.3209228250
Short name T662
Test name
Test status
Simulation time 149490422 ps
CPU time 0.79 seconds
Started Jun 28 06:15:39 PM PDT 24
Finished Jun 28 06:15:43 PM PDT 24
Peak memory 206212 kb
Host smart-b12e2ac9-3311-4abd-862a-76dbdfcb812f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32092
28250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.3209228250
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.4294222903
Short name T787
Test name
Test status
Simulation time 151955866 ps
CPU time 0.81 seconds
Started Jun 28 06:15:38 PM PDT 24
Finished Jun 28 06:15:41 PM PDT 24
Peak memory 206140 kb
Host smart-4449b39d-7e1e-4150-ba62-4794ad2bbbc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42942
22903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.4294222903
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.809139738
Short name T2505
Test name
Test status
Simulation time 298375349 ps
CPU time 1 seconds
Started Jun 28 06:15:57 PM PDT 24
Finished Jun 28 06:16:01 PM PDT 24
Peak memory 206208 kb
Host smart-9c2ef47b-df59-4b2b-a86d-5be454e9921e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=809139738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.809139738
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.2296728879
Short name T2367
Test name
Test status
Simulation time 135926264 ps
CPU time 0.78 seconds
Started Jun 28 06:15:46 PM PDT 24
Finished Jun 28 06:15:53 PM PDT 24
Peak memory 206192 kb
Host smart-039d4bd1-45e1-4d02-8dd2-0f77ad63e43e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22967
28879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.2296728879
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.1109021300
Short name T1595
Test name
Test status
Simulation time 50590998 ps
CPU time 0.64 seconds
Started Jun 28 06:15:41 PM PDT 24
Finished Jun 28 06:15:47 PM PDT 24
Peak memory 206184 kb
Host smart-b2791245-f81e-4424-8c7d-0b99d232ac88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11090
21300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.1109021300
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.64466156
Short name T2237
Test name
Test status
Simulation time 16160953989 ps
CPU time 34.28 seconds
Started Jun 28 06:15:47 PM PDT 24
Finished Jun 28 06:16:26 PM PDT 24
Peak memory 206472 kb
Host smart-3d26cd46-cb3d-4012-b27f-06d4467eb1e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64466
156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.64466156
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.3942071850
Short name T2252
Test name
Test status
Simulation time 177238580 ps
CPU time 0.83 seconds
Started Jun 28 06:15:41 PM PDT 24
Finished Jun 28 06:15:47 PM PDT 24
Peak memory 206168 kb
Host smart-99dc2a7d-d186-41bd-8e8c-a63c4b685b03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39420
71850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.3942071850
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.2278256092
Short name T2143
Test name
Test status
Simulation time 155186142 ps
CPU time 0.8 seconds
Started Jun 28 06:15:43 PM PDT 24
Finished Jun 28 06:15:50 PM PDT 24
Peak memory 206208 kb
Host smart-d4480ff0-b8da-4355-ad8d-bed5de12eea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22782
56092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.2278256092
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.817022302
Short name T1267
Test name
Test status
Simulation time 204886116 ps
CPU time 0.89 seconds
Started Jun 28 06:15:40 PM PDT 24
Finished Jun 28 06:15:45 PM PDT 24
Peak memory 206184 kb
Host smart-c9ff318e-8217-4a34-8533-68a09ec888e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81702
2302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.817022302
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.387747458
Short name T483
Test name
Test status
Simulation time 162920068 ps
CPU time 0.78 seconds
Started Jun 28 06:15:41 PM PDT 24
Finished Jun 28 06:15:45 PM PDT 24
Peak memory 206172 kb
Host smart-c5bd8e62-b6f5-4b1b-8250-bd3bce5aefa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38774
7458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.387747458
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.329902445
Short name T2244
Test name
Test status
Simulation time 141738016 ps
CPU time 0.82 seconds
Started Jun 28 06:15:53 PM PDT 24
Finished Jun 28 06:16:02 PM PDT 24
Peak memory 206124 kb
Host smart-697cc8b0-dcd1-442e-b144-0d8c0a6557ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32990
2445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.329902445
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.384382377
Short name T1067
Test name
Test status
Simulation time 160709148 ps
CPU time 0.78 seconds
Started Jun 28 06:15:44 PM PDT 24
Finished Jun 28 06:15:51 PM PDT 24
Peak memory 206184 kb
Host smart-1501c18c-4114-40d3-97d1-0d0887d21d4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38438
2377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.384382377
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.3335083651
Short name T1201
Test name
Test status
Simulation time 148309858 ps
CPU time 0.8 seconds
Started Jun 28 06:15:41 PM PDT 24
Finished Jun 28 06:15:46 PM PDT 24
Peak memory 206192 kb
Host smart-fc5fea7d-8961-4028-9b98-40302098069e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33350
83651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.3335083651
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.3646606682
Short name T425
Test name
Test status
Simulation time 226599406 ps
CPU time 0.91 seconds
Started Jun 28 06:15:55 PM PDT 24
Finished Jun 28 06:16:00 PM PDT 24
Peak memory 206212 kb
Host smart-ab02a5dd-a435-416b-aed7-5485c9af1f69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36466
06682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.3646606682
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.1357788803
Short name T1742
Test name
Test status
Simulation time 6071689720 ps
CPU time 177.78 seconds
Started Jun 28 06:15:40 PM PDT 24
Finished Jun 28 06:18:42 PM PDT 24
Peak memory 206464 kb
Host smart-7dd9c70e-00b6-4c72-9256-c9df663f7761
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1357788803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.1357788803
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.3832568651
Short name T1713
Test name
Test status
Simulation time 151639607 ps
CPU time 0.81 seconds
Started Jun 28 06:15:45 PM PDT 24
Finished Jun 28 06:15:51 PM PDT 24
Peak memory 206184 kb
Host smart-10b18a16-03ce-4241-bc59-4a6b3f248363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38325
68651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.3832568651
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.2734776509
Short name T1037
Test name
Test status
Simulation time 165089172 ps
CPU time 0.78 seconds
Started Jun 28 06:15:55 PM PDT 24
Finished Jun 28 06:16:00 PM PDT 24
Peak memory 206156 kb
Host smart-48e9e1ac-1607-4275-827a-9d894276dc15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27347
76509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.2734776509
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.2252741937
Short name T1917
Test name
Test status
Simulation time 7405662952 ps
CPU time 209.71 seconds
Started Jun 28 06:15:55 PM PDT 24
Finished Jun 28 06:19:28 PM PDT 24
Peak memory 206440 kb
Host smart-e99f2281-85b4-40dd-a9be-e7d56e00f802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22527
41937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.2252741937
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.1159484488
Short name T484
Test name
Test status
Simulation time 43783182 ps
CPU time 0.66 seconds
Started Jun 28 06:09:19 PM PDT 24
Finished Jun 28 06:09:22 PM PDT 24
Peak memory 206212 kb
Host smart-b02444e5-ae9b-44b6-818f-85ab2765b11b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1159484488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.1159484488
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.4019205901
Short name T1922
Test name
Test status
Simulation time 4458726303 ps
CPU time 6.02 seconds
Started Jun 28 06:09:15 PM PDT 24
Finished Jun 28 06:09:23 PM PDT 24
Peak memory 206480 kb
Host smart-d661d72a-0b63-435f-ad14-fd7e2dd3365d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4019205901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.4019205901
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.3414175473
Short name T2038
Test name
Test status
Simulation time 13352324451 ps
CPU time 13.14 seconds
Started Jun 28 06:09:12 PM PDT 24
Finished Jun 28 06:09:28 PM PDT 24
Peak memory 206424 kb
Host smart-e8b096e2-0e6f-4d0d-b66b-6e200af2b78f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3414175473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.3414175473
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.4123186795
Short name T1355
Test name
Test status
Simulation time 150722061 ps
CPU time 0.79 seconds
Started Jun 28 06:09:06 PM PDT 24
Finished Jun 28 06:09:09 PM PDT 24
Peak memory 206212 kb
Host smart-440df942-0a9e-4ba6-bd99-05e2a9d8146b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41231
86795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.4123186795
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.56387254
Short name T2528
Test name
Test status
Simulation time 168460500 ps
CPU time 0.84 seconds
Started Jun 28 06:09:10 PM PDT 24
Finished Jun 28 06:09:14 PM PDT 24
Peak memory 206196 kb
Host smart-47468de5-c11e-4457-9c34-3b4f56acd8f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56387
254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.56387254
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.3075565481
Short name T2354
Test name
Test status
Simulation time 376096407 ps
CPU time 1.43 seconds
Started Jun 28 06:09:10 PM PDT 24
Finished Jun 28 06:09:14 PM PDT 24
Peak memory 206196 kb
Host smart-e079a2dc-d9a4-466d-a5c1-e4f53ec5ae97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30755
65481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.3075565481
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.150626552
Short name T2399
Test name
Test status
Simulation time 858367585 ps
CPU time 2.01 seconds
Started Jun 28 06:09:16 PM PDT 24
Finished Jun 28 06:09:20 PM PDT 24
Peak memory 206264 kb
Host smart-2accac52-a25e-4e43-abf7-2af5907f4aa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15062
6552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.150626552
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.2892924456
Short name T2578
Test name
Test status
Simulation time 21807911495 ps
CPU time 38.48 seconds
Started Jun 28 06:09:07 PM PDT 24
Finished Jun 28 06:09:49 PM PDT 24
Peak memory 206480 kb
Host smart-a0283d25-77c2-4e81-91b6-ef9fa7e86b2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28929
24456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.2892924456
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.3035500234
Short name T2450
Test name
Test status
Simulation time 413147937 ps
CPU time 1.41 seconds
Started Jun 28 06:09:13 PM PDT 24
Finished Jun 28 06:09:16 PM PDT 24
Peak memory 206216 kb
Host smart-792bcccf-37b8-440e-a20a-498f0d1fa717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30355
00234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.3035500234
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.2519392002
Short name T21
Test name
Test status
Simulation time 192762606 ps
CPU time 0.84 seconds
Started Jun 28 06:09:14 PM PDT 24
Finished Jun 28 06:09:17 PM PDT 24
Peak memory 206192 kb
Host smart-581ce2dd-efc3-411e-b22b-7f631dd27f83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25193
92002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.2519392002
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.560746499
Short name T1515
Test name
Test status
Simulation time 38448281 ps
CPU time 0.7 seconds
Started Jun 28 06:09:06 PM PDT 24
Finished Jun 28 06:09:09 PM PDT 24
Peak memory 206200 kb
Host smart-bd460ff1-c47e-4511-b1f5-697f8a50b2f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56074
6499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.560746499
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.2141652427
Short name T2380
Test name
Test status
Simulation time 1138555292 ps
CPU time 2.74 seconds
Started Jun 28 06:09:08 PM PDT 24
Finished Jun 28 06:09:14 PM PDT 24
Peak memory 206336 kb
Host smart-d9b7185f-80df-4149-bbef-68bcb5c38b4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21416
52427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.2141652427
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.753185215
Short name T1679
Test name
Test status
Simulation time 210530148 ps
CPU time 1.74 seconds
Started Jun 28 06:09:06 PM PDT 24
Finished Jun 28 06:09:09 PM PDT 24
Peak memory 206264 kb
Host smart-ac6992a0-0599-4459-9418-1867c3123fe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75318
5215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.753185215
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.3473878056
Short name T543
Test name
Test status
Simulation time 150283465 ps
CPU time 0.8 seconds
Started Jun 28 06:09:10 PM PDT 24
Finished Jun 28 06:09:14 PM PDT 24
Peak memory 206212 kb
Host smart-6a0d5009-f478-4485-ba8b-5ba1855aeebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34738
78056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.3473878056
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.1206042679
Short name T619
Test name
Test status
Simulation time 143384337 ps
CPU time 0.81 seconds
Started Jun 28 06:09:05 PM PDT 24
Finished Jun 28 06:09:07 PM PDT 24
Peak memory 206212 kb
Host smart-c3e2303a-aa64-4ac5-a5ef-9c3086691c63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12060
42679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.1206042679
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.788731786
Short name T584
Test name
Test status
Simulation time 170933076 ps
CPU time 0.83 seconds
Started Jun 28 06:09:14 PM PDT 24
Finished Jun 28 06:09:17 PM PDT 24
Peak memory 206184 kb
Host smart-65f75cd1-20f6-4a49-8fac-f0ee24018828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78873
1786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.788731786
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_invalid_sync.1365820192
Short name T682
Test name
Test status
Simulation time 5922124583 ps
CPU time 45.83 seconds
Started Jun 28 06:09:07 PM PDT 24
Finished Jun 28 06:09:57 PM PDT 24
Peak memory 206432 kb
Host smart-b632eb55-048c-4b49-a723-e2b378b762d2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1365820192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.1365820192
Directory /workspace/5.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.2906584204
Short name T346
Test name
Test status
Simulation time 199875349 ps
CPU time 0.84 seconds
Started Jun 28 06:09:07 PM PDT 24
Finished Jun 28 06:09:11 PM PDT 24
Peak memory 206156 kb
Host smart-18528cca-2828-4589-bb4f-457138dd7a71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29065
84204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.2906584204
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.2909376657
Short name T1965
Test name
Test status
Simulation time 23417253932 ps
CPU time 23.23 seconds
Started Jun 28 06:09:06 PM PDT 24
Finished Jun 28 06:09:31 PM PDT 24
Peak memory 206296 kb
Host smart-3556d625-dac8-4b65-9e77-9ebc0418ab9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29093
76657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.2909376657
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.1238865925
Short name T142
Test name
Test status
Simulation time 3285494638 ps
CPU time 3.82 seconds
Started Jun 28 06:09:06 PM PDT 24
Finished Jun 28 06:09:12 PM PDT 24
Peak memory 206252 kb
Host smart-8a039c38-c5b9-4275-ace2-687a78777ccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12388
65925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.1238865925
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.3147701354
Short name T1241
Test name
Test status
Simulation time 8697345175 ps
CPU time 76.25 seconds
Started Jun 28 06:09:06 PM PDT 24
Finished Jun 28 06:10:24 PM PDT 24
Peak memory 206440 kb
Host smart-ec4bfcb7-7a21-4253-9448-b90ef9a57f42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31477
01354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.3147701354
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.374354417
Short name T1528
Test name
Test status
Simulation time 5192960576 ps
CPU time 143.15 seconds
Started Jun 28 06:09:06 PM PDT 24
Finished Jun 28 06:11:32 PM PDT 24
Peak memory 206452 kb
Host smart-c59f2a43-0914-499f-90b4-39b2f5528112
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=374354417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.374354417
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.2177548740
Short name T1296
Test name
Test status
Simulation time 240373829 ps
CPU time 0.93 seconds
Started Jun 28 06:09:09 PM PDT 24
Finished Jun 28 06:09:13 PM PDT 24
Peak memory 206220 kb
Host smart-282008a6-0c86-43d1-97ad-0897486a232a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2177548740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.2177548740
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.311656711
Short name T2005
Test name
Test status
Simulation time 227756950 ps
CPU time 0.97 seconds
Started Jun 28 06:09:09 PM PDT 24
Finished Jun 28 06:09:13 PM PDT 24
Peak memory 206212 kb
Host smart-251d4909-0d05-4991-8fb6-319883d5aed0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31165
6711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.311656711
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.1262533304
Short name T2156
Test name
Test status
Simulation time 7000326519 ps
CPU time 48.99 seconds
Started Jun 28 06:09:07 PM PDT 24
Finished Jun 28 06:10:00 PM PDT 24
Peak memory 206496 kb
Host smart-a386abb3-80e1-48aa-8efe-679d033562ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12625
33304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.1262533304
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.3309155251
Short name T328
Test name
Test status
Simulation time 5465188561 ps
CPU time 51.99 seconds
Started Jun 28 06:09:20 PM PDT 24
Finished Jun 28 06:10:16 PM PDT 24
Peak memory 206460 kb
Host smart-41ab0863-230e-459e-89a1-775539965c33
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3309155251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.3309155251
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.3745238804
Short name T906
Test name
Test status
Simulation time 158397188 ps
CPU time 0.85 seconds
Started Jun 28 06:09:17 PM PDT 24
Finished Jun 28 06:09:20 PM PDT 24
Peak memory 206216 kb
Host smart-8be2e86d-fac8-42b2-9517-64c7847ad994
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3745238804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.3745238804
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.1820383232
Short name T1640
Test name
Test status
Simulation time 197791217 ps
CPU time 0.85 seconds
Started Jun 28 06:09:22 PM PDT 24
Finished Jun 28 06:09:26 PM PDT 24
Peak memory 206176 kb
Host smart-cd5bff8f-8170-45f9-8ee5-2da32ac4de6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18203
83232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.1820383232
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.1832091791
Short name T118
Test name
Test status
Simulation time 223038312 ps
CPU time 0.95 seconds
Started Jun 28 06:09:27 PM PDT 24
Finished Jun 28 06:09:31 PM PDT 24
Peak memory 206216 kb
Host smart-116af4b3-97cc-4072-adf8-53cd632937d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18320
91791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.1832091791
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.3347512306
Short name T468
Test name
Test status
Simulation time 194767346 ps
CPU time 0.89 seconds
Started Jun 28 06:09:17 PM PDT 24
Finished Jun 28 06:09:20 PM PDT 24
Peak memory 206208 kb
Host smart-cedab60e-961d-4e59-a808-79561900a580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33475
12306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.3347512306
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.167032048
Short name T389
Test name
Test status
Simulation time 190988379 ps
CPU time 0.82 seconds
Started Jun 28 06:09:20 PM PDT 24
Finished Jun 28 06:09:23 PM PDT 24
Peak memory 206172 kb
Host smart-98ea06e9-6f5e-48f7-8f04-51bac88d42e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16703
2048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.167032048
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.1805562340
Short name T2302
Test name
Test status
Simulation time 147734756 ps
CPU time 0.8 seconds
Started Jun 28 06:09:20 PM PDT 24
Finished Jun 28 06:09:23 PM PDT 24
Peak memory 206216 kb
Host smart-c2761c92-ed64-46a6-86cc-8f22017ed941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18055
62340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.1805562340
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.2342970308
Short name T2034
Test name
Test status
Simulation time 224334370 ps
CPU time 0.87 seconds
Started Jun 28 06:09:19 PM PDT 24
Finished Jun 28 06:09:22 PM PDT 24
Peak memory 206216 kb
Host smart-ee6c765b-beba-4578-ba57-e075d6c89e72
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2342970308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.2342970308
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.3542617600
Short name T1315
Test name
Test status
Simulation time 140910694 ps
CPU time 0.8 seconds
Started Jun 28 06:09:20 PM PDT 24
Finished Jun 28 06:09:23 PM PDT 24
Peak memory 206208 kb
Host smart-e712d455-bc0e-4008-bb41-560475529c11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35426
17600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.3542617600
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.475638393
Short name T895
Test name
Test status
Simulation time 92583142 ps
CPU time 0.75 seconds
Started Jun 28 06:09:19 PM PDT 24
Finished Jun 28 06:09:23 PM PDT 24
Peak memory 206200 kb
Host smart-98cd1117-400e-4d5b-89ee-4fe45205dcfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47563
8393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.475638393
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.4112895846
Short name T1587
Test name
Test status
Simulation time 16557262896 ps
CPU time 32.87 seconds
Started Jun 28 06:09:18 PM PDT 24
Finished Jun 28 06:09:54 PM PDT 24
Peak memory 206476 kb
Host smart-ea238612-d366-4161-9e8d-86448c7c8450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41128
95846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.4112895846
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.2934334565
Short name T469
Test name
Test status
Simulation time 210576729 ps
CPU time 0.91 seconds
Started Jun 28 06:09:18 PM PDT 24
Finished Jun 28 06:09:21 PM PDT 24
Peak memory 206192 kb
Host smart-b318f4bb-9381-449c-a66e-d87f602a17c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29343
34565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.2934334565
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.1129685491
Short name T144
Test name
Test status
Simulation time 237644742 ps
CPU time 0.86 seconds
Started Jun 28 06:09:30 PM PDT 24
Finished Jun 28 06:09:35 PM PDT 24
Peak memory 206200 kb
Host smart-8c4d1cd6-426e-4281-be11-5e43d757efda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11296
85491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.1129685491
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.3704421591
Short name T1457
Test name
Test status
Simulation time 11860480597 ps
CPU time 62.59 seconds
Started Jun 28 06:09:27 PM PDT 24
Finished Jun 28 06:10:32 PM PDT 24
Peak memory 206484 kb
Host smart-0f88687f-55c6-4cdc-afd3-01bd89c4c0e4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3704421591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.3704421591
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.1153786347
Short name T1658
Test name
Test status
Simulation time 12595813422 ps
CPU time 87.58 seconds
Started Jun 28 06:09:21 PM PDT 24
Finished Jun 28 06:10:53 PM PDT 24
Peak memory 206460 kb
Host smart-62899588-7c27-44bb-afc2-5bbf687175f8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1153786347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.1153786347
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.2903315374
Short name T886
Test name
Test status
Simulation time 227149978 ps
CPU time 0.9 seconds
Started Jun 28 06:09:18 PM PDT 24
Finished Jun 28 06:09:22 PM PDT 24
Peak memory 206208 kb
Host smart-1cae0478-901b-4d9e-9329-c2cd0e4e334c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29033
15374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.2903315374
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.2627612906
Short name T1516
Test name
Test status
Simulation time 154479216 ps
CPU time 0.81 seconds
Started Jun 28 06:09:21 PM PDT 24
Finished Jun 28 06:09:25 PM PDT 24
Peak memory 206200 kb
Host smart-ad3937c9-7a58-4cfb-83c2-8bfc33993277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26276
12906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.2627612906
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.2871327595
Short name T68
Test name
Test status
Simulation time 142293365 ps
CPU time 0.75 seconds
Started Jun 28 06:09:19 PM PDT 24
Finished Jun 28 06:09:22 PM PDT 24
Peak memory 206168 kb
Host smart-7f061f11-fb88-4831-91a0-15701f908ab0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28713
27595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.2871327595
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.294391292
Short name T1299
Test name
Test status
Simulation time 142015019 ps
CPU time 0.74 seconds
Started Jun 28 06:09:27 PM PDT 24
Finished Jun 28 06:09:31 PM PDT 24
Peak memory 206164 kb
Host smart-3660c27f-eb48-4786-9c01-109bc7f77c57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29439
1292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.294391292
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.402824537
Short name T1687
Test name
Test status
Simulation time 149013199 ps
CPU time 0.78 seconds
Started Jun 28 06:09:17 PM PDT 24
Finished Jun 28 06:09:20 PM PDT 24
Peak memory 206192 kb
Host smart-959e81b1-2378-4c17-b9bf-2896ffee8e85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40282
4537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.402824537
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.1993211370
Short name T2555
Test name
Test status
Simulation time 253511615 ps
CPU time 0.93 seconds
Started Jun 28 06:09:20 PM PDT 24
Finished Jun 28 06:09:25 PM PDT 24
Peak memory 206100 kb
Host smart-ac438690-b5b3-4a8a-85e7-783c4432e9e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19932
11370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.1993211370
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.2598815944
Short name T1626
Test name
Test status
Simulation time 3370050244 ps
CPU time 92.65 seconds
Started Jun 28 06:09:18 PM PDT 24
Finished Jun 28 06:10:53 PM PDT 24
Peak memory 206448 kb
Host smart-358059d9-f89a-4143-b330-54d3fe901f14
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2598815944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.2598815944
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.2908515103
Short name T339
Test name
Test status
Simulation time 208454875 ps
CPU time 0.86 seconds
Started Jun 28 06:09:20 PM PDT 24
Finished Jun 28 06:09:25 PM PDT 24
Peak memory 206092 kb
Host smart-925978a0-c58a-46dd-87f5-5fb452ef8c5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29085
15103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.2908515103
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.3783892229
Short name T1179
Test name
Test status
Simulation time 155658144 ps
CPU time 0.81 seconds
Started Jun 28 06:09:26 PM PDT 24
Finished Jun 28 06:09:29 PM PDT 24
Peak memory 206196 kb
Host smart-abd1f335-e7c7-4a50-a9c9-fb3f992a31b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37838
92229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.3783892229
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.1555715433
Short name T1198
Test name
Test status
Simulation time 3451665646 ps
CPU time 25.87 seconds
Started Jun 28 06:09:17 PM PDT 24
Finished Jun 28 06:09:45 PM PDT 24
Peak memory 206436 kb
Host smart-6dff61a4-a7af-4a43-be53-90dabf491001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15557
15433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.1555715433
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.3810706198
Short name T2068
Test name
Test status
Simulation time 32535350 ps
CPU time 0.66 seconds
Started Jun 28 06:09:30 PM PDT 24
Finished Jun 28 06:09:34 PM PDT 24
Peak memory 206204 kb
Host smart-39711e01-e00e-4bf4-a0fc-59a5228eff61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3810706198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.3810706198
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.1084952040
Short name T1273
Test name
Test status
Simulation time 4148717872 ps
CPU time 5.01 seconds
Started Jun 28 06:09:20 PM PDT 24
Finished Jun 28 06:09:28 PM PDT 24
Peak memory 206428 kb
Host smart-c5e96b76-8c2d-4878-843f-dbaaa26c14c5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1084952040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.1084952040
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.579723446
Short name T1102
Test name
Test status
Simulation time 13448240957 ps
CPU time 15.2 seconds
Started Jun 28 06:09:24 PM PDT 24
Finished Jun 28 06:09:42 PM PDT 24
Peak memory 206340 kb
Host smart-5c1b3825-7617-43cd-b7ce-ce72a9536534
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=579723446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.579723446
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.3587948163
Short name T1266
Test name
Test status
Simulation time 23350955498 ps
CPU time 25.04 seconds
Started Jun 28 06:09:27 PM PDT 24
Finished Jun 28 06:09:54 PM PDT 24
Peak memory 206328 kb
Host smart-c6f9d0b2-5c94-4209-b26f-de1d7feb6c8b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3587948163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.3587948163
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.1668634003
Short name T1153
Test name
Test status
Simulation time 152527019 ps
CPU time 0.83 seconds
Started Jun 28 06:09:19 PM PDT 24
Finished Jun 28 06:09:23 PM PDT 24
Peak memory 206212 kb
Host smart-407347a3-017f-43ad-9df1-6c52857e9cbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16686
34003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.1668634003
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.2622460647
Short name T486
Test name
Test status
Simulation time 144831840 ps
CPU time 0.78 seconds
Started Jun 28 06:09:22 PM PDT 24
Finished Jun 28 06:09:26 PM PDT 24
Peak memory 206184 kb
Host smart-dda39d57-ef13-4b82-aa9f-26c9fd35dceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26224
60647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.2622460647
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.1456562066
Short name T1556
Test name
Test status
Simulation time 385143233 ps
CPU time 1.32 seconds
Started Jun 28 06:09:30 PM PDT 24
Finished Jun 28 06:09:35 PM PDT 24
Peak memory 206192 kb
Host smart-a1c60ae3-19c5-4a59-b6ad-9035a70b05c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14565
62066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.1456562066
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.1511783579
Short name T2254
Test name
Test status
Simulation time 1375433385 ps
CPU time 3.11 seconds
Started Jun 28 06:09:22 PM PDT 24
Finished Jun 28 06:09:29 PM PDT 24
Peak memory 206336 kb
Host smart-08a01ab1-115c-4d54-968b-e6ae0d2ce44e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15117
83579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.1511783579
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.4156376945
Short name T2507
Test name
Test status
Simulation time 9018615760 ps
CPU time 17.11 seconds
Started Jun 28 06:09:21 PM PDT 24
Finished Jun 28 06:09:41 PM PDT 24
Peak memory 206432 kb
Host smart-7facfb2d-0cf4-43bd-a97e-33c847734364
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41563
76945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.4156376945
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.809446127
Short name T799
Test name
Test status
Simulation time 336905301 ps
CPU time 1.15 seconds
Started Jun 28 06:09:19 PM PDT 24
Finished Jun 28 06:09:23 PM PDT 24
Peak memory 206212 kb
Host smart-b648d9d2-3119-48e6-b1f9-160618b0ef6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80944
6127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.809446127
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.3680103637
Short name T1702
Test name
Test status
Simulation time 157562499 ps
CPU time 0.78 seconds
Started Jun 28 06:09:20 PM PDT 24
Finished Jun 28 06:09:24 PM PDT 24
Peak memory 206196 kb
Host smart-d6dcfd71-9dc5-471f-856d-f34c3dd7b991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36801
03637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.3680103637
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.3555986499
Short name T2493
Test name
Test status
Simulation time 46485586 ps
CPU time 0.67 seconds
Started Jun 28 06:09:18 PM PDT 24
Finished Jun 28 06:09:21 PM PDT 24
Peak memory 206208 kb
Host smart-4e1069bf-f781-4108-a911-1012a1fa1689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35559
86499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.3555986499
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.1178034896
Short name T325
Test name
Test status
Simulation time 880399462 ps
CPU time 2.1 seconds
Started Jun 28 06:09:19 PM PDT 24
Finished Jun 28 06:09:24 PM PDT 24
Peak memory 206268 kb
Host smart-e25c9e52-1f1d-443b-a20a-14b7085cc389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11780
34896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.1178034896
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.3100446402
Short name T1131
Test name
Test status
Simulation time 279010782 ps
CPU time 1.92 seconds
Started Jun 28 06:09:27 PM PDT 24
Finished Jun 28 06:09:32 PM PDT 24
Peak memory 206288 kb
Host smart-99afca9d-a223-4ef6-b1ad-4523ce316c57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31004
46402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.3100446402
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.4038983127
Short name T2280
Test name
Test status
Simulation time 182674507 ps
CPU time 0.98 seconds
Started Jun 28 06:09:21 PM PDT 24
Finished Jun 28 06:09:26 PM PDT 24
Peak memory 206148 kb
Host smart-93554f1f-082b-4197-a7a8-3566f38f2723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40389
83127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.4038983127
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.1180562777
Short name T1733
Test name
Test status
Simulation time 137277280 ps
CPU time 0.74 seconds
Started Jun 28 06:09:22 PM PDT 24
Finished Jun 28 06:09:27 PM PDT 24
Peak memory 206208 kb
Host smart-8c4c0e7c-64de-4a19-ad62-326d45caf0ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11805
62777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.1180562777
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.2587729210
Short name T1717
Test name
Test status
Simulation time 192315760 ps
CPU time 0.85 seconds
Started Jun 28 06:09:24 PM PDT 24
Finished Jun 28 06:09:28 PM PDT 24
Peak memory 206204 kb
Host smart-ab2a32b6-d83f-4c71-b787-5bb5ab7bafbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25877
29210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.2587729210
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.299038775
Short name T443
Test name
Test status
Simulation time 217431389 ps
CPU time 0.88 seconds
Started Jun 28 06:09:19 PM PDT 24
Finished Jun 28 06:09:23 PM PDT 24
Peak memory 206204 kb
Host smart-91826777-67c2-4ded-b2ba-3eda7e000da9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29903
8775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.299038775
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.1709900034
Short name T1959
Test name
Test status
Simulation time 23338801433 ps
CPU time 21.62 seconds
Started Jun 28 06:09:24 PM PDT 24
Finished Jun 28 06:09:48 PM PDT 24
Peak memory 206304 kb
Host smart-fd5b4b08-0799-46f3-8950-203c8ed9c074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17099
00034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.1709900034
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.24976864
Short name T617
Test name
Test status
Simulation time 3382966084 ps
CPU time 3.87 seconds
Started Jun 28 06:09:23 PM PDT 24
Finished Jun 28 06:09:30 PM PDT 24
Peak memory 206252 kb
Host smart-e8f7380b-d0bd-4643-9b29-51fdd964e487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24976
864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.24976864
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.3117171607
Short name T1845
Test name
Test status
Simulation time 9208227628 ps
CPU time 263.39 seconds
Started Jun 28 06:09:22 PM PDT 24
Finished Jun 28 06:13:50 PM PDT 24
Peak memory 206432 kb
Host smart-3412b593-36b0-40b1-86f1-4a49c0992d4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31171
71607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.3117171607
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.1807815675
Short name T1608
Test name
Test status
Simulation time 3392895839 ps
CPU time 25.68 seconds
Started Jun 28 06:09:27 PM PDT 24
Finished Jun 28 06:09:56 PM PDT 24
Peak memory 206420 kb
Host smart-c1dd9a10-9fc0-41b5-8629-702708cfa62a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1807815675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.1807815675
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.619078141
Short name T930
Test name
Test status
Simulation time 260625135 ps
CPU time 1.01 seconds
Started Jun 28 06:09:20 PM PDT 24
Finished Jun 28 06:09:24 PM PDT 24
Peak memory 206216 kb
Host smart-333b67c8-0709-4105-ac3b-f6b560aea43f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=619078141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.619078141
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.3726587016
Short name T524
Test name
Test status
Simulation time 254842294 ps
CPU time 1 seconds
Started Jun 28 06:09:24 PM PDT 24
Finished Jun 28 06:09:28 PM PDT 24
Peak memory 206212 kb
Host smart-0e2b88c7-3369-4092-b8de-dfaf6955f0d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37265
87016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.3726587016
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.704159798
Short name T2312
Test name
Test status
Simulation time 4420548631 ps
CPU time 123.73 seconds
Started Jun 28 06:09:22 PM PDT 24
Finished Jun 28 06:11:30 PM PDT 24
Peak memory 206460 kb
Host smart-4b2539fa-c583-4a9d-8de4-53a329034f46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70415
9798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.704159798
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.725519682
Short name T146
Test name
Test status
Simulation time 5455261990 ps
CPU time 51.14 seconds
Started Jun 28 06:09:27 PM PDT 24
Finished Jun 28 06:10:21 PM PDT 24
Peak memory 206416 kb
Host smart-baba403f-d063-45c7-8b20-7f6a79d4c618
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=725519682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.725519682
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.2802595016
Short name T550
Test name
Test status
Simulation time 150817013 ps
CPU time 0.77 seconds
Started Jun 28 06:09:30 PM PDT 24
Finished Jun 28 06:09:35 PM PDT 24
Peak memory 206168 kb
Host smart-8489c79e-d9e5-487c-85ba-97cc57610b67
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2802595016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.2802595016
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.49183082
Short name T2076
Test name
Test status
Simulation time 155837946 ps
CPU time 0.75 seconds
Started Jun 28 06:09:28 PM PDT 24
Finished Jun 28 06:09:32 PM PDT 24
Peak memory 206192 kb
Host smart-b2225f7c-80fe-47fe-918e-d49acc089e52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49183
082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.49183082
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.3748068855
Short name T1829
Test name
Test status
Simulation time 211986184 ps
CPU time 0.83 seconds
Started Jun 28 06:09:22 PM PDT 24
Finished Jun 28 06:09:27 PM PDT 24
Peak memory 206216 kb
Host smart-3c79594a-fe99-4735-aad6-a8cf5316c7dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37480
68855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.3748068855
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.4094208384
Short name T1709
Test name
Test status
Simulation time 180422890 ps
CPU time 0.83 seconds
Started Jun 28 06:09:29 PM PDT 24
Finished Jun 28 06:09:34 PM PDT 24
Peak memory 206148 kb
Host smart-46ac0ea6-ef18-44a8-a052-93dd68e651a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40942
08384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.4094208384
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.4006310186
Short name T2359
Test name
Test status
Simulation time 166093671 ps
CPU time 0.79 seconds
Started Jun 28 06:09:26 PM PDT 24
Finished Jun 28 06:09:30 PM PDT 24
Peak memory 206172 kb
Host smart-e113e98c-7dd5-4c40-a9ad-06ee06e9001b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40063
10186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.4006310186
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.1521039672
Short name T1554
Test name
Test status
Simulation time 167427277 ps
CPU time 0.8 seconds
Started Jun 28 06:09:28 PM PDT 24
Finished Jun 28 06:09:32 PM PDT 24
Peak memory 206192 kb
Host smart-e0045841-cf22-429a-ad8e-ad34f6991210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15210
39672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.1521039672
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.1718733197
Short name T1598
Test name
Test status
Simulation time 154572762 ps
CPU time 0.77 seconds
Started Jun 28 06:09:28 PM PDT 24
Finished Jun 28 06:09:32 PM PDT 24
Peak memory 206216 kb
Host smart-52ee48da-b44a-414e-8891-39f8e7e52c13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17187
33197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.1718733197
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.1109839814
Short name T42
Test name
Test status
Simulation time 192626522 ps
CPU time 0.85 seconds
Started Jun 28 06:09:30 PM PDT 24
Finished Jun 28 06:09:35 PM PDT 24
Peak memory 206212 kb
Host smart-d00c6f4b-baad-44e0-952a-645ae3521612
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1109839814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.1109839814
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.3718896844
Short name T1235
Test name
Test status
Simulation time 222403605 ps
CPU time 0.84 seconds
Started Jun 28 06:09:25 PM PDT 24
Finished Jun 28 06:09:29 PM PDT 24
Peak memory 206212 kb
Host smart-8c224e05-cbc1-4b8f-a470-d0bdb4f60e27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37188
96844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.3718896844
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.3252593960
Short name T24
Test name
Test status
Simulation time 63883471 ps
CPU time 0.69 seconds
Started Jun 28 06:09:29 PM PDT 24
Finished Jun 28 06:09:34 PM PDT 24
Peak memory 206164 kb
Host smart-06b3a954-7d4a-4aef-8342-824ac736e342
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32525
93960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.3252593960
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.1430110935
Short name T2308
Test name
Test status
Simulation time 6162948616 ps
CPU time 13.7 seconds
Started Jun 28 06:09:35 PM PDT 24
Finished Jun 28 06:09:53 PM PDT 24
Peak memory 206492 kb
Host smart-a250e304-a566-4711-9f73-ea50faabc746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14301
10935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.1430110935
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.1865197598
Short name T859
Test name
Test status
Simulation time 164238894 ps
CPU time 0.84 seconds
Started Jun 28 06:09:28 PM PDT 24
Finished Jun 28 06:09:32 PM PDT 24
Peak memory 206192 kb
Host smart-6b99cb5b-ea7a-4569-b73f-6b416ba839e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18651
97598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.1865197598
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.2891141191
Short name T944
Test name
Test status
Simulation time 217069949 ps
CPU time 0.88 seconds
Started Jun 28 06:09:39 PM PDT 24
Finished Jun 28 06:09:45 PM PDT 24
Peak memory 206192 kb
Host smart-2e1a9e82-9b25-4dec-b973-cae808401286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28911
41191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.2891141191
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.116825718
Short name T2090
Test name
Test status
Simulation time 5086484093 ps
CPU time 40.48 seconds
Started Jun 28 06:09:32 PM PDT 24
Finished Jun 28 06:10:17 PM PDT 24
Peak memory 206500 kb
Host smart-2b523792-6442-4cea-920d-1faafebdee89
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=116825718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.116825718
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.4140617143
Short name T2081
Test name
Test status
Simulation time 4763425696 ps
CPU time 31.85 seconds
Started Jun 28 06:09:31 PM PDT 24
Finished Jun 28 06:10:07 PM PDT 24
Peak memory 206472 kb
Host smart-f51e47ed-b805-48f7-848d-195d1cc2688d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4140617143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.4140617143
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.2781788972
Short name T1779
Test name
Test status
Simulation time 11895712979 ps
CPU time 233.36 seconds
Started Jun 28 06:09:34 PM PDT 24
Finished Jun 28 06:13:32 PM PDT 24
Peak memory 205944 kb
Host smart-88e23ac0-133b-4e75-a81f-9f97a8b22361
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2781788972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.2781788972
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.991910318
Short name T566
Test name
Test status
Simulation time 178952799 ps
CPU time 0.84 seconds
Started Jun 28 06:09:29 PM PDT 24
Finished Jun 28 06:09:34 PM PDT 24
Peak memory 206192 kb
Host smart-f714d18e-f934-4121-b13a-6cf50729de56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99191
0318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.991910318
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.2993525568
Short name T894
Test name
Test status
Simulation time 175718861 ps
CPU time 0.84 seconds
Started Jun 28 06:09:33 PM PDT 24
Finished Jun 28 06:09:38 PM PDT 24
Peak memory 206200 kb
Host smart-55b8149e-c411-4c31-aac6-e0d8ff678497
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29935
25568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.2993525568
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.4239456470
Short name T664
Test name
Test status
Simulation time 185072446 ps
CPU time 0.79 seconds
Started Jun 28 06:09:34 PM PDT 24
Finished Jun 28 06:09:39 PM PDT 24
Peak memory 206204 kb
Host smart-7a8620a0-9e9e-4460-8706-5b8b9653c3cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42394
56470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.4239456470
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.4265908888
Short name T2235
Test name
Test status
Simulation time 150055523 ps
CPU time 0.89 seconds
Started Jun 28 06:09:30 PM PDT 24
Finished Jun 28 06:09:35 PM PDT 24
Peak memory 206192 kb
Host smart-0e624717-30fc-4cdc-9559-1242888b1d6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42659
08888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.4265908888
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.1186649698
Short name T1734
Test name
Test status
Simulation time 211432856 ps
CPU time 0.8 seconds
Started Jun 28 06:09:33 PM PDT 24
Finished Jun 28 06:09:38 PM PDT 24
Peak memory 206156 kb
Host smart-6508c114-55c7-4310-8153-6c06f595173d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11866
49698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.1186649698
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.1084808225
Short name T1070
Test name
Test status
Simulation time 256158971 ps
CPU time 0.95 seconds
Started Jun 28 06:09:29 PM PDT 24
Finished Jun 28 06:09:34 PM PDT 24
Peak memory 206208 kb
Host smart-55f6b373-99c6-4762-b3be-33a598522ec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10848
08225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.1084808225
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.3382317286
Short name T2021
Test name
Test status
Simulation time 3639386608 ps
CPU time 101.46 seconds
Started Jun 28 06:09:30 PM PDT 24
Finished Jun 28 06:11:15 PM PDT 24
Peak memory 206496 kb
Host smart-6bac2918-a414-4288-b9bd-dcdb6c875146
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3382317286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.3382317286
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.801201012
Short name T1897
Test name
Test status
Simulation time 202488993 ps
CPU time 0.92 seconds
Started Jun 28 06:09:32 PM PDT 24
Finished Jun 28 06:09:37 PM PDT 24
Peak memory 206216 kb
Host smart-5c7938ec-a555-4943-885e-d1ba90404b0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80120
1012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.801201012
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.885306839
Short name T1385
Test name
Test status
Simulation time 189887629 ps
CPU time 0.84 seconds
Started Jun 28 06:09:30 PM PDT 24
Finished Jun 28 06:09:35 PM PDT 24
Peak memory 206200 kb
Host smart-410fa837-3848-4071-840f-02ef4f93852d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88530
6839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.885306839
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.2452002142
Short name T1968
Test name
Test status
Simulation time 5083600911 ps
CPU time 44.96 seconds
Started Jun 28 06:09:34 PM PDT 24
Finished Jun 28 06:10:23 PM PDT 24
Peak memory 205760 kb
Host smart-059cfe7c-3e16-4bff-b8c1-d6c50d1d6d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24520
02142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.2452002142
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.3674770764
Short name T194
Test name
Test status
Simulation time 44980008 ps
CPU time 0.72 seconds
Started Jun 28 06:09:32 PM PDT 24
Finished Jun 28 06:09:38 PM PDT 24
Peak memory 206180 kb
Host smart-a9898d2a-61c9-46a6-a20e-906ddb56e2fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3674770764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.3674770764
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.1478491901
Short name T1692
Test name
Test status
Simulation time 4239211832 ps
CPU time 4.78 seconds
Started Jun 28 06:09:37 PM PDT 24
Finished Jun 28 06:09:45 PM PDT 24
Peak memory 206272 kb
Host smart-68bc60fc-4397-42e0-8db8-cb7d09898fcd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1478491901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.1478491901
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.1569859489
Short name T976
Test name
Test status
Simulation time 13428041995 ps
CPU time 13.51 seconds
Started Jun 28 06:09:40 PM PDT 24
Finished Jun 28 06:09:58 PM PDT 24
Peak memory 206344 kb
Host smart-2210f06a-941e-4509-bd3d-d3b220e5177a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1569859489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.1569859489
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.4119857707
Short name T657
Test name
Test status
Simulation time 23372168311 ps
CPU time 23.41 seconds
Started Jun 28 06:09:37 PM PDT 24
Finished Jun 28 06:10:03 PM PDT 24
Peak memory 206484 kb
Host smart-afa0a6bd-f83c-4de1-821e-f5e7ee6c658c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4119857707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.4119857707
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.3015622656
Short name T2494
Test name
Test status
Simulation time 178462745 ps
CPU time 0.86 seconds
Started Jun 28 06:09:29 PM PDT 24
Finished Jun 28 06:09:33 PM PDT 24
Peak memory 206192 kb
Host smart-f187382d-b191-4083-9b47-356e7eb2cb57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30156
22656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.3015622656
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.1754395560
Short name T778
Test name
Test status
Simulation time 173663366 ps
CPU time 0.84 seconds
Started Jun 28 06:09:30 PM PDT 24
Finished Jun 28 06:09:35 PM PDT 24
Peak memory 206160 kb
Host smart-71d215e7-baeb-4a8c-b018-726321f09223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17543
95560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.1754395560
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.2259164250
Short name T19
Test name
Test status
Simulation time 355426535 ps
CPU time 1.14 seconds
Started Jun 28 06:09:31 PM PDT 24
Finished Jun 28 06:09:37 PM PDT 24
Peak memory 206188 kb
Host smart-89848366-80a3-4bc3-8eb1-f51c2549e59a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22591
64250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.2259164250
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.626791153
Short name T172
Test name
Test status
Simulation time 1258920861 ps
CPU time 2.75 seconds
Started Jun 28 06:09:32 PM PDT 24
Finished Jun 28 06:09:39 PM PDT 24
Peak memory 206276 kb
Host smart-273f2acf-ac86-4f4a-abad-1fd83811cecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62679
1153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.626791153
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.2188136995
Short name T1649
Test name
Test status
Simulation time 20085192276 ps
CPU time 38.24 seconds
Started Jun 28 06:09:31 PM PDT 24
Finished Jun 28 06:10:13 PM PDT 24
Peak memory 206400 kb
Host smart-b9f7e6d9-ac7c-4fd0-b604-a696581397a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21881
36995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.2188136995
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.4016769300
Short name T1401
Test name
Test status
Simulation time 438525174 ps
CPU time 1.39 seconds
Started Jun 28 06:09:32 PM PDT 24
Finished Jun 28 06:09:38 PM PDT 24
Peak memory 206220 kb
Host smart-c53cb6ca-f9de-4fee-acb9-73fac653adbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40167
69300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.4016769300
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.1208453791
Short name T2164
Test name
Test status
Simulation time 149108802 ps
CPU time 0.74 seconds
Started Jun 28 06:09:32 PM PDT 24
Finished Jun 28 06:09:38 PM PDT 24
Peak memory 206188 kb
Host smart-234f82ac-88ed-47f1-9b49-68d299b1a4ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12084
53791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.1208453791
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.18522085
Short name T2459
Test name
Test status
Simulation time 35318599 ps
CPU time 0.66 seconds
Started Jun 28 06:09:35 PM PDT 24
Finished Jun 28 06:09:40 PM PDT 24
Peak memory 206060 kb
Host smart-4facd798-af58-49f5-8de7-a7ce77bcb166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18522
085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.18522085
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.4200251317
Short name T841
Test name
Test status
Simulation time 886934174 ps
CPU time 2.15 seconds
Started Jun 28 06:09:32 PM PDT 24
Finished Jun 28 06:09:38 PM PDT 24
Peak memory 206292 kb
Host smart-5317dc0c-cfd1-4dc7-a051-b57f29e85f0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42002
51317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.4200251317
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.925661778
Short name T1456
Test name
Test status
Simulation time 171952579 ps
CPU time 1.68 seconds
Started Jun 28 06:09:31 PM PDT 24
Finished Jun 28 06:09:37 PM PDT 24
Peak memory 206280 kb
Host smart-0147c2d9-b7bb-45a7-87f6-0f431ebbb261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92566
1778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.925661778
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.2098410938
Short name T1853
Test name
Test status
Simulation time 207394042 ps
CPU time 0.85 seconds
Started Jun 28 06:09:28 PM PDT 24
Finished Jun 28 06:09:32 PM PDT 24
Peak memory 206188 kb
Host smart-e3648048-e42b-46fc-b513-70c35702c4b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20984
10938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.2098410938
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.2849034139
Short name T2101
Test name
Test status
Simulation time 150399835 ps
CPU time 0.76 seconds
Started Jun 28 06:09:32 PM PDT 24
Finished Jun 28 06:09:38 PM PDT 24
Peak memory 206208 kb
Host smart-dfb111bb-a848-497a-a462-180f4fb94edb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28490
34139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.2849034139
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.3264971223
Short name T327
Test name
Test status
Simulation time 202241966 ps
CPU time 0.85 seconds
Started Jun 28 06:09:29 PM PDT 24
Finished Jun 28 06:09:34 PM PDT 24
Peak memory 206208 kb
Host smart-da948455-8729-46f5-982b-86da70048a97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32649
71223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.3264971223
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_invalid_sync.3389890772
Short name T729
Test name
Test status
Simulation time 7236859848 ps
CPU time 52.76 seconds
Started Jun 28 06:09:31 PM PDT 24
Finished Jun 28 06:10:28 PM PDT 24
Peak memory 206392 kb
Host smart-85636224-f9f9-4065-9c45-f464d4bbee0c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3389890772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_invalid_sync.3389890772
Directory /workspace/7.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.1465855828
Short name T1092
Test name
Test status
Simulation time 232196529 ps
CPU time 0.95 seconds
Started Jun 28 06:09:31 PM PDT 24
Finished Jun 28 06:09:36 PM PDT 24
Peak memory 206196 kb
Host smart-453c6aed-14e6-4928-8ae8-9301d2e00019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14658
55828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.1465855828
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.1902652240
Short name T2617
Test name
Test status
Simulation time 23335230467 ps
CPU time 22.47 seconds
Started Jun 28 06:09:31 PM PDT 24
Finished Jun 28 06:09:57 PM PDT 24
Peak memory 206316 kb
Host smart-927b6471-f4c5-496f-a42c-84b1529f44b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19026
52240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.1902652240
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.3492590598
Short name T1460
Test name
Test status
Simulation time 3285194246 ps
CPU time 3.86 seconds
Started Jun 28 06:09:39 PM PDT 24
Finished Jun 28 06:09:48 PM PDT 24
Peak memory 206188 kb
Host smart-3106279e-9584-47dd-8e85-770c98fba0a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34925
90598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.3492590598
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.4230191426
Short name T151
Test name
Test status
Simulation time 12134939175 ps
CPU time 342.6 seconds
Started Jun 28 06:09:30 PM PDT 24
Finished Jun 28 06:15:17 PM PDT 24
Peak memory 206468 kb
Host smart-b58239da-86fc-4c6a-bb0f-95ba0f21d828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42301
91426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.4230191426
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.3867266872
Short name T2570
Test name
Test status
Simulation time 3879366455 ps
CPU time 36.4 seconds
Started Jun 28 06:09:35 PM PDT 24
Finished Jun 28 06:10:15 PM PDT 24
Peak memory 206416 kb
Host smart-0258a4d8-5a82-4fe1-aa89-2363d31286fa
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3867266872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.3867266872
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.3259261125
Short name T143
Test name
Test status
Simulation time 245389707 ps
CPU time 0.93 seconds
Started Jun 28 06:09:37 PM PDT 24
Finished Jun 28 06:09:41 PM PDT 24
Peak memory 206216 kb
Host smart-5dde78a5-f87b-4b2c-bdef-cb71f456e931
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3259261125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.3259261125
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.1558884767
Short name T533
Test name
Test status
Simulation time 194324674 ps
CPU time 0.87 seconds
Started Jun 28 06:09:31 PM PDT 24
Finished Jun 28 06:09:36 PM PDT 24
Peak memory 206188 kb
Host smart-d7c392fb-75ec-486b-b4f7-b8463de7c4db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15588
84767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.1558884767
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.1091219010
Short name T1961
Test name
Test status
Simulation time 6187085061 ps
CPU time 49.84 seconds
Started Jun 28 06:09:30 PM PDT 24
Finished Jun 28 06:10:24 PM PDT 24
Peak memory 206460 kb
Host smart-935fd030-c582-4751-88cd-0d33166081c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10912
19010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.1091219010
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.580924306
Short name T338
Test name
Test status
Simulation time 4651210757 ps
CPU time 132.87 seconds
Started Jun 28 06:09:39 PM PDT 24
Finished Jun 28 06:11:57 PM PDT 24
Peak memory 206392 kb
Host smart-cd1a333d-8c87-4b73-8134-a78f5ba9fc32
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=580924306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.580924306
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.2771343237
Short name T820
Test name
Test status
Simulation time 168201523 ps
CPU time 0.8 seconds
Started Jun 28 06:09:30 PM PDT 24
Finished Jun 28 06:09:35 PM PDT 24
Peak memory 206216 kb
Host smart-461a91fe-84c1-41b1-8be0-f756b95cda02
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2771343237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.2771343237
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.120883144
Short name T1932
Test name
Test status
Simulation time 148423664 ps
CPU time 0.84 seconds
Started Jun 28 06:09:34 PM PDT 24
Finished Jun 28 06:09:39 PM PDT 24
Peak memory 206156 kb
Host smart-63e207b6-ea74-4a8a-9f72-007fccb86a03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12088
3144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.120883144
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.444345398
Short name T131
Test name
Test status
Simulation time 210127506 ps
CPU time 0.9 seconds
Started Jun 28 06:09:40 PM PDT 24
Finished Jun 28 06:09:45 PM PDT 24
Peak memory 206212 kb
Host smart-0eb84a3a-1b33-495e-9479-3eb406da56b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44434
5398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.444345398
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.1307302910
Short name T855
Test name
Test status
Simulation time 160857493 ps
CPU time 0.84 seconds
Started Jun 28 06:09:29 PM PDT 24
Finished Jun 28 06:09:33 PM PDT 24
Peak memory 206180 kb
Host smart-0eefbd00-2f1f-437f-9053-b6211b71c579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13073
02910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.1307302910
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.135820091
Short name T1298
Test name
Test status
Simulation time 178024548 ps
CPU time 0.86 seconds
Started Jun 28 06:09:32 PM PDT 24
Finished Jun 28 06:09:37 PM PDT 24
Peak memory 206212 kb
Host smart-64031a90-4ada-41f5-b675-ce568bd22b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13582
0091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.135820091
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.3585563847
Short name T1394
Test name
Test status
Simulation time 161936605 ps
CPU time 0.88 seconds
Started Jun 28 06:09:31 PM PDT 24
Finished Jun 28 06:09:36 PM PDT 24
Peak memory 206168 kb
Host smart-54edd5cc-fb85-4521-9674-e0403b7b2b25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35855
63847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.3585563847
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.1578357157
Short name T2309
Test name
Test status
Simulation time 166950131 ps
CPU time 0.82 seconds
Started Jun 28 06:09:31 PM PDT 24
Finished Jun 28 06:09:36 PM PDT 24
Peak memory 206212 kb
Host smart-b5ae0ae7-7dd4-45a0-8ccb-76fa6440bcc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15783
57157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.1578357157
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.2863990649
Short name T2061
Test name
Test status
Simulation time 212842986 ps
CPU time 0.9 seconds
Started Jun 28 06:09:31 PM PDT 24
Finished Jun 28 06:09:37 PM PDT 24
Peak memory 206156 kb
Host smart-2cce6aea-69dd-4061-8e65-a925b28c1eaa
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2863990649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.2863990649
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.2743791927
Short name T1830
Test name
Test status
Simulation time 241472741 ps
CPU time 0.87 seconds
Started Jun 28 06:09:35 PM PDT 24
Finished Jun 28 06:09:39 PM PDT 24
Peak memory 206216 kb
Host smart-b6accfbb-5e79-48df-a2e1-f936e68f878b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27437
91927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.2743791927
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.1897946315
Short name T32
Test name
Test status
Simulation time 51236638 ps
CPU time 0.66 seconds
Started Jun 28 06:09:30 PM PDT 24
Finished Jun 28 06:09:35 PM PDT 24
Peak memory 206204 kb
Host smart-59add621-c015-47e6-a37f-f4b2ce01cbdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18979
46315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.1897946315
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.3530040376
Short name T218
Test name
Test status
Simulation time 10838731451 ps
CPU time 26.03 seconds
Started Jun 28 06:09:35 PM PDT 24
Finished Jun 28 06:10:05 PM PDT 24
Peak memory 206276 kb
Host smart-7991a3db-60c6-4991-b310-15845bf3746e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35300
40376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.3530040376
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.1283098289
Short name T2080
Test name
Test status
Simulation time 197143418 ps
CPU time 0.83 seconds
Started Jun 28 06:09:30 PM PDT 24
Finished Jun 28 06:09:35 PM PDT 24
Peak memory 206192 kb
Host smart-7992d255-2abd-4980-a8fb-931ab50055c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12830
98289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.1283098289
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.715401578
Short name T2149
Test name
Test status
Simulation time 259547437 ps
CPU time 0.93 seconds
Started Jun 28 06:09:32 PM PDT 24
Finished Jun 28 06:09:37 PM PDT 24
Peak memory 206168 kb
Host smart-853b9697-d18a-43c1-b776-e632ed887fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71540
1578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.715401578
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.3126981457
Short name T177
Test name
Test status
Simulation time 21643753878 ps
CPU time 122.08 seconds
Started Jun 28 06:09:40 PM PDT 24
Finished Jun 28 06:11:47 PM PDT 24
Peak memory 206428 kb
Host smart-a7e2e3a0-e883-4702-941b-545863722d87
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3126981457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.3126981457
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.3705287783
Short name T162
Test name
Test status
Simulation time 7525978068 ps
CPU time 202.97 seconds
Started Jun 28 06:09:41 PM PDT 24
Finished Jun 28 06:13:08 PM PDT 24
Peak memory 206332 kb
Host smart-a1a72c97-56ae-4256-bab7-a6acba5815b2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3705287783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.3705287783
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.701842929
Short name T1790
Test name
Test status
Simulation time 13327344771 ps
CPU time 275.87 seconds
Started Jun 28 06:09:40 PM PDT 24
Finished Jun 28 06:14:21 PM PDT 24
Peak memory 206360 kb
Host smart-5e64392c-1b81-43a3-bcb6-abdf6c0a523b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=701842929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.701842929
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.3084028840
Short name T2321
Test name
Test status
Simulation time 297357489 ps
CPU time 0.95 seconds
Started Jun 28 06:09:40 PM PDT 24
Finished Jun 28 06:09:46 PM PDT 24
Peak memory 206160 kb
Host smart-4ea5c451-114b-4059-8fc0-05a6d479ee95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30840
28840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.3084028840
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.2470800451
Short name T2140
Test name
Test status
Simulation time 189538691 ps
CPU time 0.85 seconds
Started Jun 28 06:09:37 PM PDT 24
Finished Jun 28 06:09:42 PM PDT 24
Peak memory 206192 kb
Host smart-46719991-1c53-4f0c-8fcb-45f849aeb784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24708
00451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.2470800451
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.2102706369
Short name T1939
Test name
Test status
Simulation time 136392297 ps
CPU time 0.74 seconds
Started Jun 28 06:09:31 PM PDT 24
Finished Jun 28 06:09:36 PM PDT 24
Peak memory 206180 kb
Host smart-07891aa3-a680-452b-896a-9226a427ce4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21027
06369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.2102706369
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.3495830889
Short name T2512
Test name
Test status
Simulation time 173479128 ps
CPU time 0.78 seconds
Started Jun 28 06:09:32 PM PDT 24
Finished Jun 28 06:09:38 PM PDT 24
Peak memory 206156 kb
Host smart-cf3503b9-74ce-4b5a-9173-90458c165f0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34958
30889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.3495830889
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.831272634
Short name T357
Test name
Test status
Simulation time 156906698 ps
CPU time 0.77 seconds
Started Jun 28 06:09:37 PM PDT 24
Finished Jun 28 06:09:42 PM PDT 24
Peak memory 206188 kb
Host smart-74f594c1-992f-49a0-abb3-cdfc663cb98a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83127
2634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.831272634
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.418821049
Short name T836
Test name
Test status
Simulation time 226104911 ps
CPU time 0.94 seconds
Started Jun 28 06:09:36 PM PDT 24
Finished Jun 28 06:09:41 PM PDT 24
Peak memory 206184 kb
Host smart-4d523193-0fe4-4075-b31e-21b0bb1b324c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41882
1049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.418821049
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.3185876081
Short name T1232
Test name
Test status
Simulation time 5432438360 ps
CPU time 50.68 seconds
Started Jun 28 06:09:31 PM PDT 24
Finished Jun 28 06:10:26 PM PDT 24
Peak memory 206444 kb
Host smart-200d79e8-7f44-474a-aced-1899d9790376
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3185876081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.3185876081
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.775436100
Short name T2341
Test name
Test status
Simulation time 185517636 ps
CPU time 0.81 seconds
Started Jun 28 06:09:34 PM PDT 24
Finished Jun 28 06:09:39 PM PDT 24
Peak memory 206208 kb
Host smart-94767143-7100-4b18-936c-641f931d8e33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77543
6100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.775436100
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.645412630
Short name T520
Test name
Test status
Simulation time 180791494 ps
CPU time 0.81 seconds
Started Jun 28 06:09:32 PM PDT 24
Finished Jun 28 06:09:37 PM PDT 24
Peak memory 206188 kb
Host smart-4463e866-bee6-4758-89a5-5702047148fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64541
2630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.645412630
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.1362607861
Short name T2327
Test name
Test status
Simulation time 4716998644 ps
CPU time 46.42 seconds
Started Jun 28 06:09:35 PM PDT 24
Finished Jun 28 06:10:25 PM PDT 24
Peak memory 206436 kb
Host smart-cf26a8c5-7a89-44c0-8ba5-35db583f4a12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13626
07861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.1362607861
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.3485480625
Short name T978
Test name
Test status
Simulation time 31892432 ps
CPU time 0.64 seconds
Started Jun 28 06:09:37 PM PDT 24
Finished Jun 28 06:09:42 PM PDT 24
Peak memory 206208 kb
Host smart-74d93fba-a9e7-4b22-b29b-631a3523b1ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3485480625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.3485480625
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.252877436
Short name T752
Test name
Test status
Simulation time 4297130499 ps
CPU time 4.85 seconds
Started Jun 28 06:09:37 PM PDT 24
Finished Jun 28 06:09:45 PM PDT 24
Peak memory 206328 kb
Host smart-f6f397f3-8d0c-4324-9d47-8db3eb988149
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=252877436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.252877436
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.1499348023
Short name T1728
Test name
Test status
Simulation time 13443654782 ps
CPU time 15.37 seconds
Started Jun 28 06:09:39 PM PDT 24
Finished Jun 28 06:09:59 PM PDT 24
Peak memory 206508 kb
Host smart-92367bbc-ca0f-4506-9e51-382140370d3c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1499348023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.1499348023
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.3236976117
Short name T831
Test name
Test status
Simulation time 23415795903 ps
CPU time 23.44 seconds
Started Jun 28 06:09:39 PM PDT 24
Finished Jun 28 06:10:07 PM PDT 24
Peak memory 206296 kb
Host smart-2ff7e65c-9a37-41ff-a393-20909118a8ff
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3236976117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.3236976117
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.3395978459
Short name T1470
Test name
Test status
Simulation time 165749265 ps
CPU time 0.82 seconds
Started Jun 28 06:09:40 PM PDT 24
Finished Jun 28 06:09:45 PM PDT 24
Peak memory 206200 kb
Host smart-c0bd0d64-aa7b-4488-b833-dccbe46bf11a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33959
78459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.3395978459
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.2586766047
Short name T2581
Test name
Test status
Simulation time 170285915 ps
CPU time 0.8 seconds
Started Jun 28 06:09:42 PM PDT 24
Finished Jun 28 06:09:47 PM PDT 24
Peak memory 206180 kb
Host smart-41ebd051-8ef1-4b80-9063-f56efd5924eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25867
66047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.2586766047
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.365242826
Short name T671
Test name
Test status
Simulation time 420129199 ps
CPU time 1.34 seconds
Started Jun 28 06:09:42 PM PDT 24
Finished Jun 28 06:09:48 PM PDT 24
Peak memory 206192 kb
Host smart-adb96e35-da57-44d8-a34b-12e26a34e31e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36524
2826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.365242826
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.616543201
Short name T2614
Test name
Test status
Simulation time 1052516312 ps
CPU time 2.55 seconds
Started Jun 28 06:09:37 PM PDT 24
Finished Jun 28 06:09:43 PM PDT 24
Peak memory 206288 kb
Host smart-fb36bfe8-3207-4eac-9333-054858f39f3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61654
3201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.616543201
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.282335023
Short name T1534
Test name
Test status
Simulation time 11193917541 ps
CPU time 20.53 seconds
Started Jun 28 06:09:38 PM PDT 24
Finished Jun 28 06:10:03 PM PDT 24
Peak memory 206420 kb
Host smart-3445bc3d-2840-48d7-a8fe-bc09ab054512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28233
5023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.282335023
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.2128556747
Short name T1244
Test name
Test status
Simulation time 431708394 ps
CPU time 1.35 seconds
Started Jun 28 06:09:41 PM PDT 24
Finished Jun 28 06:09:47 PM PDT 24
Peak memory 206216 kb
Host smart-8e8e7ceb-2d8f-4df4-98ff-6e5641f61433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21285
56747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.2128556747
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.904517001
Short name T1818
Test name
Test status
Simulation time 143316212 ps
CPU time 0.8 seconds
Started Jun 28 06:09:38 PM PDT 24
Finished Jun 28 06:09:43 PM PDT 24
Peak memory 206168 kb
Host smart-4edc4c43-4a9c-4898-9088-885103aaf6d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90451
7001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.904517001
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.3323521668
Short name T1348
Test name
Test status
Simulation time 120329803 ps
CPU time 0.73 seconds
Started Jun 28 06:09:38 PM PDT 24
Finished Jun 28 06:09:43 PM PDT 24
Peak memory 206200 kb
Host smart-329f8256-6e2b-4727-9d99-c7c1a9eab5ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33235
21668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.3323521668
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.3565777686
Short name T2181
Test name
Test status
Simulation time 751030457 ps
CPU time 1.96 seconds
Started Jun 28 06:09:39 PM PDT 24
Finished Jun 28 06:09:45 PM PDT 24
Peak memory 206288 kb
Host smart-5ee0b75a-3040-42b2-8333-c06afc14bcb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35657
77686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.3565777686
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.3732161979
Short name T670
Test name
Test status
Simulation time 151918928 ps
CPU time 1.23 seconds
Started Jun 28 06:09:42 PM PDT 24
Finished Jun 28 06:09:48 PM PDT 24
Peak memory 206276 kb
Host smart-67051497-1de0-403f-82f0-c94917380eab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37321
61979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.3732161979
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.3196836217
Short name T2469
Test name
Test status
Simulation time 169677558 ps
CPU time 0.88 seconds
Started Jun 28 06:09:39 PM PDT 24
Finished Jun 28 06:09:44 PM PDT 24
Peak memory 206212 kb
Host smart-89071556-054f-4ab6-9864-865ce47b8799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31968
36217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.3196836217
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.1475192394
Short name T438
Test name
Test status
Simulation time 160313039 ps
CPU time 0.77 seconds
Started Jun 28 06:09:40 PM PDT 24
Finished Jun 28 06:09:45 PM PDT 24
Peak memory 206184 kb
Host smart-90394487-61c8-45ad-9c1c-a8b05b0596db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14751
92394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.1475192394
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.1098898479
Short name T1505
Test name
Test status
Simulation time 179777498 ps
CPU time 0.85 seconds
Started Jun 28 06:09:45 PM PDT 24
Finished Jun 28 06:09:49 PM PDT 24
Peak memory 206192 kb
Host smart-0c93589f-74cf-4b17-98f1-bf9636ab8fbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10988
98479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.1098898479
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.1144726691
Short name T1745
Test name
Test status
Simulation time 186064949 ps
CPU time 0.84 seconds
Started Jun 28 06:09:38 PM PDT 24
Finished Jun 28 06:09:43 PM PDT 24
Peak memory 206144 kb
Host smart-816a5133-4210-48d9-a9cd-f264449a01c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11447
26691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.1144726691
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.2730177698
Short name T1229
Test name
Test status
Simulation time 23335999151 ps
CPU time 24.4 seconds
Started Jun 28 06:09:40 PM PDT 24
Finished Jun 28 06:10:09 PM PDT 24
Peak memory 206300 kb
Host smart-c202cfa0-6251-4b83-9029-da2ca20d1e63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27301
77698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.2730177698
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.993468006
Short name T826
Test name
Test status
Simulation time 3364298453 ps
CPU time 3.82 seconds
Started Jun 28 06:09:41 PM PDT 24
Finished Jun 28 06:09:50 PM PDT 24
Peak memory 206248 kb
Host smart-230086bf-7c3d-429a-bea7-5de5e9192153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99346
8006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.993468006
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.469892425
Short name T2473
Test name
Test status
Simulation time 11573503244 ps
CPU time 87.56 seconds
Started Jun 28 06:09:41 PM PDT 24
Finished Jun 28 06:11:14 PM PDT 24
Peak memory 206500 kb
Host smart-9fa590fa-0ebc-43f7-a453-a2c58cfa3f89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46989
2425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.469892425
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.4221650908
Short name T813
Test name
Test status
Simulation time 4692745915 ps
CPU time 31.45 seconds
Started Jun 28 06:09:41 PM PDT 24
Finished Jun 28 06:10:17 PM PDT 24
Peak memory 206456 kb
Host smart-0a770585-4c1b-4a4a-9217-90d8da422ee6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4221650908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.4221650908
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.1401565326
Short name T2608
Test name
Test status
Simulation time 254332596 ps
CPU time 0.93 seconds
Started Jun 28 06:09:40 PM PDT 24
Finished Jun 28 06:09:46 PM PDT 24
Peak memory 206184 kb
Host smart-b7a75ea4-683f-43a1-85c7-b9d864bcd340
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1401565326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.1401565326
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.1361725151
Short name T2223
Test name
Test status
Simulation time 206786075 ps
CPU time 0.92 seconds
Started Jun 28 06:09:41 PM PDT 24
Finished Jun 28 06:09:47 PM PDT 24
Peak memory 206216 kb
Host smart-f31da930-09d1-42b6-8ca4-7d1c2d4dfd17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13617
25151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.1361725151
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.3724263645
Short name T1271
Test name
Test status
Simulation time 5679887551 ps
CPU time 160.62 seconds
Started Jun 28 06:09:47 PM PDT 24
Finished Jun 28 06:12:29 PM PDT 24
Peak memory 206416 kb
Host smart-60ebfa1a-a268-482b-b17d-7aa8354a582f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37242
63645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.3724263645
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.1731871748
Short name T2420
Test name
Test status
Simulation time 4605910587 ps
CPU time 42.27 seconds
Started Jun 28 06:09:40 PM PDT 24
Finished Jun 28 06:10:26 PM PDT 24
Peak memory 206416 kb
Host smart-91f94263-b081-476b-b1ac-3691979a1bee
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1731871748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.1731871748
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.287828067
Short name T1509
Test name
Test status
Simulation time 172342728 ps
CPU time 0.8 seconds
Started Jun 28 06:09:39 PM PDT 24
Finished Jun 28 06:09:44 PM PDT 24
Peak memory 206192 kb
Host smart-b7090175-1c37-44dd-baff-0c64bdc26fa8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=287828067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.287828067
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.3247663828
Short name T1960
Test name
Test status
Simulation time 159740583 ps
CPU time 0.8 seconds
Started Jun 28 06:09:40 PM PDT 24
Finished Jun 28 06:09:45 PM PDT 24
Peak memory 206200 kb
Host smart-1295386c-ed7f-462f-b0ac-7edef6daf64e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32476
63828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.3247663828
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.3014615884
Short name T139
Test name
Test status
Simulation time 233173329 ps
CPU time 0.94 seconds
Started Jun 28 06:09:41 PM PDT 24
Finished Jun 28 06:09:47 PM PDT 24
Peak memory 206196 kb
Host smart-aa44f0e6-02ec-429d-9ebc-d0855f3eb3c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30146
15884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.3014615884
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.377515389
Short name T1344
Test name
Test status
Simulation time 230044077 ps
CPU time 0.88 seconds
Started Jun 28 06:09:41 PM PDT 24
Finished Jun 28 06:09:47 PM PDT 24
Peak memory 206188 kb
Host smart-2ad77b35-eae1-40c7-8725-ffd69279d877
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37751
5389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.377515389
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.3172401867
Short name T407
Test name
Test status
Simulation time 196603377 ps
CPU time 0.79 seconds
Started Jun 28 06:09:42 PM PDT 24
Finished Jun 28 06:09:48 PM PDT 24
Peak memory 206212 kb
Host smart-e99b1514-e4ea-4f66-861c-77ae02c518f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31724
01867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.3172401867
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.425714837
Short name T935
Test name
Test status
Simulation time 172267078 ps
CPU time 0.81 seconds
Started Jun 28 06:09:39 PM PDT 24
Finished Jun 28 06:09:44 PM PDT 24
Peak memory 206196 kb
Host smart-63674456-a307-45b8-87d7-aacba4a991d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42571
4837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.425714837
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.1272667790
Short name T2013
Test name
Test status
Simulation time 208532311 ps
CPU time 0.86 seconds
Started Jun 28 06:09:40 PM PDT 24
Finished Jun 28 06:09:45 PM PDT 24
Peak memory 206216 kb
Host smart-c9b2ede8-4289-4d91-8480-69d34eea5931
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12726
67790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.1272667790
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.1987309938
Short name T1343
Test name
Test status
Simulation time 237901616 ps
CPU time 1.01 seconds
Started Jun 28 06:09:40 PM PDT 24
Finished Jun 28 06:09:46 PM PDT 24
Peak memory 206188 kb
Host smart-8fadc2ca-dec9-4470-8282-6df252aa880f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1987309938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.1987309938
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.1094877487
Short name T1118
Test name
Test status
Simulation time 176482544 ps
CPU time 0.78 seconds
Started Jun 28 06:09:40 PM PDT 24
Finished Jun 28 06:09:45 PM PDT 24
Peak memory 206212 kb
Host smart-c03e5f25-d480-444d-9783-5faf6e438b6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10948
77487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.1094877487
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.3465681891
Short name T1860
Test name
Test status
Simulation time 57885453 ps
CPU time 0.72 seconds
Started Jun 28 06:09:40 PM PDT 24
Finished Jun 28 06:09:44 PM PDT 24
Peak memory 206208 kb
Host smart-b7a1f5d4-826f-4378-9f7b-b9cd7fb73cf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34656
81891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.3465681891
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.1368643997
Short name T956
Test name
Test status
Simulation time 10259534329 ps
CPU time 21.5 seconds
Started Jun 28 06:09:47 PM PDT 24
Finished Jun 28 06:10:10 PM PDT 24
Peak memory 206416 kb
Host smart-1fb3f38a-53f3-4e98-9cde-189564634a86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13686
43997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.1368643997
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.3434513413
Short name T304
Test name
Test status
Simulation time 175572437 ps
CPU time 0.87 seconds
Started Jun 28 06:09:49 PM PDT 24
Finished Jun 28 06:09:52 PM PDT 24
Peak memory 206196 kb
Host smart-4fd5d3b8-b849-4b7b-831f-776356cefbd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34345
13413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.3434513413
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.3698925687
Short name T393
Test name
Test status
Simulation time 158130648 ps
CPU time 0.78 seconds
Started Jun 28 06:09:47 PM PDT 24
Finished Jun 28 06:09:50 PM PDT 24
Peak memory 206164 kb
Host smart-0476e541-1e5d-43ee-8a12-45a28622916c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36989
25687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.3698925687
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.3821341643
Short name T2241
Test name
Test status
Simulation time 13438231998 ps
CPU time 268.88 seconds
Started Jun 28 06:09:40 PM PDT 24
Finished Jun 28 06:14:14 PM PDT 24
Peak memory 206532 kb
Host smart-25b6c05f-0808-470d-bc5d-3de80c380ca9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3821341643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.3821341643
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.1644123728
Short name T168
Test name
Test status
Simulation time 11403285764 ps
CPU time 74.15 seconds
Started Jun 28 06:09:46 PM PDT 24
Finished Jun 28 06:11:03 PM PDT 24
Peak memory 206496 kb
Host smart-6845b0ab-a57c-4df6-9158-e8eedd639304
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1644123728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.1644123728
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.1845779555
Short name T488
Test name
Test status
Simulation time 7679597430 ps
CPU time 123.73 seconds
Started Jun 28 06:09:41 PM PDT 24
Finished Jun 28 06:11:50 PM PDT 24
Peak memory 206504 kb
Host smart-3f72e891-4102-445e-aaaa-716c8b691f0a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1845779555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.1845779555
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.1477089424
Short name T351
Test name
Test status
Simulation time 207662425 ps
CPU time 0.9 seconds
Started Jun 28 06:09:51 PM PDT 24
Finished Jun 28 06:09:56 PM PDT 24
Peak memory 206112 kb
Host smart-6e956bc5-8883-4534-953d-93f8ee2c70e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14770
89424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.1477089424
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.2992231224
Short name T852
Test name
Test status
Simulation time 184523140 ps
CPU time 0.82 seconds
Started Jun 28 06:09:39 PM PDT 24
Finished Jun 28 06:09:43 PM PDT 24
Peak memory 206192 kb
Host smart-44ad4c48-7221-4b7f-8554-d7f530eab7ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29922
31224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.2992231224
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.1506150793
Short name T538
Test name
Test status
Simulation time 138693555 ps
CPU time 0.79 seconds
Started Jun 28 06:09:38 PM PDT 24
Finished Jun 28 06:09:43 PM PDT 24
Peak memory 206124 kb
Host smart-3e341c69-1932-4a27-be68-ad07b77d823c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15061
50793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.1506150793
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.2623806658
Short name T1760
Test name
Test status
Simulation time 167347512 ps
CPU time 0.79 seconds
Started Jun 28 06:09:41 PM PDT 24
Finished Jun 28 06:09:46 PM PDT 24
Peak memory 206160 kb
Host smart-0ace5cb1-359e-4729-be42-2cba5fa8d25b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26238
06658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.2623806658
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.1736289256
Short name T501
Test name
Test status
Simulation time 158401737 ps
CPU time 0.77 seconds
Started Jun 28 06:09:38 PM PDT 24
Finished Jun 28 06:09:43 PM PDT 24
Peak memory 206168 kb
Host smart-c2051cc5-56f2-41c0-9579-1f7f5a358eb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17362
89256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.1736289256
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.2989122944
Short name T1592
Test name
Test status
Simulation time 214603692 ps
CPU time 0.93 seconds
Started Jun 28 06:09:47 PM PDT 24
Finished Jun 28 06:09:50 PM PDT 24
Peak memory 206196 kb
Host smart-2f6441f7-2c2d-426b-bb11-b17510046c0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29891
22944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.2989122944
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.550670117
Short name T1110
Test name
Test status
Simulation time 4336955933 ps
CPU time 41.5 seconds
Started Jun 28 06:09:46 PM PDT 24
Finished Jun 28 06:10:30 PM PDT 24
Peak memory 206368 kb
Host smart-d5d9b3c6-bc72-457d-8fa2-6640b0b630cc
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=550670117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.550670117
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.3574181254
Short name T1824
Test name
Test status
Simulation time 187306933 ps
CPU time 0.85 seconds
Started Jun 28 06:09:41 PM PDT 24
Finished Jun 28 06:09:47 PM PDT 24
Peak memory 206160 kb
Host smart-06a8ee6a-b128-4446-837c-0607ec09db4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35741
81254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.3574181254
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.50919950
Short name T1491
Test name
Test status
Simulation time 171610313 ps
CPU time 0.88 seconds
Started Jun 28 06:09:40 PM PDT 24
Finished Jun 28 06:09:45 PM PDT 24
Peak memory 206200 kb
Host smart-df4b32f3-fd31-4d7a-bad2-c00eb68ca8d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50919
950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.50919950
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.2451747340
Short name T1362
Test name
Test status
Simulation time 4020162273 ps
CPU time 36.79 seconds
Started Jun 28 06:09:49 PM PDT 24
Finished Jun 28 06:10:28 PM PDT 24
Peak memory 206328 kb
Host smart-df49a7c0-0e97-49d7-8cb5-ce9a0ca1e26d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24517
47340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.2451747340
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.1208674000
Short name T2349
Test name
Test status
Simulation time 54979672 ps
CPU time 0.71 seconds
Started Jun 28 06:09:52 PM PDT 24
Finished Jun 28 06:09:56 PM PDT 24
Peak memory 206320 kb
Host smart-877d880f-597b-4311-a0d5-5c73968c9475
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1208674000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.1208674000
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.1442303328
Short name T1622
Test name
Test status
Simulation time 4211441176 ps
CPU time 4.83 seconds
Started Jun 28 06:09:49 PM PDT 24
Finished Jun 28 06:09:57 PM PDT 24
Peak memory 206320 kb
Host smart-cf9f2f18-f335-4551-97d7-520ea0c09273
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1442303328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.1442303328
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.1012883590
Short name T1363
Test name
Test status
Simulation time 23402541811 ps
CPU time 23.71 seconds
Started Jun 28 06:09:44 PM PDT 24
Finished Jun 28 06:10:11 PM PDT 24
Peak memory 206424 kb
Host smart-05a1952d-81ac-4006-bf10-948466c48fc4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1012883590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.1012883590
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.4146834073
Short name T1848
Test name
Test status
Simulation time 169636980 ps
CPU time 0.81 seconds
Started Jun 28 06:09:42 PM PDT 24
Finished Jun 28 06:09:48 PM PDT 24
Peak memory 206216 kb
Host smart-c36283c3-5a6e-4491-920a-a24a3271a952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41468
34073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.4146834073
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.2147712201
Short name T1230
Test name
Test status
Simulation time 200342415 ps
CPU time 0.86 seconds
Started Jun 28 06:09:52 PM PDT 24
Finished Jun 28 06:09:56 PM PDT 24
Peak memory 206108 kb
Host smart-3e17a846-99dd-4c76-9051-2a4f20285b71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21477
12201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.2147712201
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.35721291
Short name T868
Test name
Test status
Simulation time 291862342 ps
CPU time 0.96 seconds
Started Jun 28 06:09:40 PM PDT 24
Finished Jun 28 06:09:50 PM PDT 24
Peak memory 206076 kb
Host smart-d772e0ec-a03f-4652-a44d-1d133f814ea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35721
291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.35721291
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.1615259614
Short name T1627
Test name
Test status
Simulation time 627024857 ps
CPU time 1.52 seconds
Started Jun 28 06:09:42 PM PDT 24
Finished Jun 28 06:09:48 PM PDT 24
Peak memory 206132 kb
Host smart-9c525858-0e62-479a-bb5f-99152e2b835b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16152
59614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.1615259614
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.439118779
Short name T2485
Test name
Test status
Simulation time 13044118528 ps
CPU time 25.07 seconds
Started Jun 28 06:09:52 PM PDT 24
Finished Jun 28 06:10:20 PM PDT 24
Peak memory 206348 kb
Host smart-e320c3e9-8651-4325-b91f-4409b75c2b29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43911
8779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.439118779
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.3012759000
Short name T669
Test name
Test status
Simulation time 560528871 ps
CPU time 1.57 seconds
Started Jun 28 06:09:41 PM PDT 24
Finished Jun 28 06:09:48 PM PDT 24
Peak memory 206212 kb
Host smart-86bd533d-d49d-4aa1-9c5f-766f6c647c84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30127
59000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.3012759000
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.2433880547
Short name T783
Test name
Test status
Simulation time 163147218 ps
CPU time 0.78 seconds
Started Jun 28 06:09:43 PM PDT 24
Finished Jun 28 06:09:48 PM PDT 24
Peak memory 206144 kb
Host smart-3385db68-bbbd-4e9e-ac57-8c8e8abd245e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24338
80547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.2433880547
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.2460514086
Short name T1885
Test name
Test status
Simulation time 49094331 ps
CPU time 0.68 seconds
Started Jun 28 06:09:51 PM PDT 24
Finished Jun 28 06:09:55 PM PDT 24
Peak memory 206144 kb
Host smart-a4061a59-3e98-4d57-9061-3cdbf19298a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24605
14086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.2460514086
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.1881503552
Short name T1169
Test name
Test status
Simulation time 930236800 ps
CPU time 2.16 seconds
Started Jun 28 06:09:44 PM PDT 24
Finished Jun 28 06:09:50 PM PDT 24
Peak memory 206296 kb
Host smart-7b1dd4d5-2b87-4963-9306-b7d5457cbc21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18815
03552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.1881503552
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.1865732471
Short name T2633
Test name
Test status
Simulation time 269750674 ps
CPU time 1.61 seconds
Started Jun 28 06:09:43 PM PDT 24
Finished Jun 28 06:09:49 PM PDT 24
Peak memory 206284 kb
Host smart-efbba31f-7357-4969-931b-dbcca4948394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18657
32471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.1865732471
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.3115582175
Short name T379
Test name
Test status
Simulation time 214374508 ps
CPU time 0.8 seconds
Started Jun 28 06:09:40 PM PDT 24
Finished Jun 28 06:09:46 PM PDT 24
Peak memory 206068 kb
Host smart-d22a7395-3b5d-4968-a3fa-49573479aac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31155
82175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.3115582175
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.791079991
Short name T1061
Test name
Test status
Simulation time 140317520 ps
CPU time 0.77 seconds
Started Jun 28 06:09:44 PM PDT 24
Finished Jun 28 06:09:49 PM PDT 24
Peak memory 206160 kb
Host smart-cb543566-64e1-4404-8f4c-a204e75aced5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79107
9991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.791079991
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.750660186
Short name T2593
Test name
Test status
Simulation time 203130933 ps
CPU time 0.84 seconds
Started Jun 28 06:09:54 PM PDT 24
Finished Jun 28 06:09:58 PM PDT 24
Peak memory 206076 kb
Host smart-4923f34c-7591-4a6d-b360-e7233d8d8b8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75066
0186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.750660186
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.2221134288
Short name T2463
Test name
Test status
Simulation time 227092136 ps
CPU time 0.85 seconds
Started Jun 28 06:09:54 PM PDT 24
Finished Jun 28 06:09:59 PM PDT 24
Peak memory 206192 kb
Host smart-b56e80b8-8a03-4e2d-b67a-eb43b5b4d38a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22211
34288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.2221134288
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.3311876177
Short name T1542
Test name
Test status
Simulation time 23336176400 ps
CPU time 21.82 seconds
Started Jun 28 06:09:49 PM PDT 24
Finished Jun 28 06:10:13 PM PDT 24
Peak memory 206296 kb
Host smart-eaf19e4c-137b-476b-8b55-e3c2d691ccae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33118
76177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.3311876177
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.4183307515
Short name T2389
Test name
Test status
Simulation time 3250794931 ps
CPU time 4.45 seconds
Started Jun 28 06:09:50 PM PDT 24
Finished Jun 28 06:09:58 PM PDT 24
Peak memory 206244 kb
Host smart-baf5875d-2d8d-4d5d-b714-0e94badd19b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41833
07515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.4183307515
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.3618660209
Short name T1969
Test name
Test status
Simulation time 7412444119 ps
CPU time 53.24 seconds
Started Jun 28 06:09:50 PM PDT 24
Finished Jun 28 06:10:46 PM PDT 24
Peak memory 206428 kb
Host smart-4e5d99eb-89ba-4a66-9f11-847d5ccad623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36186
60209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.3618660209
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.3086466498
Short name T1175
Test name
Test status
Simulation time 6175728428 ps
CPU time 171.09 seconds
Started Jun 28 06:09:49 PM PDT 24
Finished Jun 28 06:12:43 PM PDT 24
Peak memory 206412 kb
Host smart-aa33c4f9-d6fd-4a82-96be-bd73c3a86e27
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3086466498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.3086466498
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.1625967197
Short name T2161
Test name
Test status
Simulation time 236577778 ps
CPU time 0.9 seconds
Started Jun 28 06:09:50 PM PDT 24
Finished Jun 28 06:09:54 PM PDT 24
Peak memory 206216 kb
Host smart-a50921ff-2566-4ac9-8e79-1fcecad4fe1f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1625967197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.1625967197
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.1118958624
Short name T1378
Test name
Test status
Simulation time 191856426 ps
CPU time 0.86 seconds
Started Jun 28 06:09:51 PM PDT 24
Finished Jun 28 06:09:56 PM PDT 24
Peak memory 206188 kb
Host smart-e1fa8495-793a-4c74-8d2b-d9f3c45c8ddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11189
58624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.1118958624
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.388845625
Short name T1771
Test name
Test status
Simulation time 4886233089 ps
CPU time 136.94 seconds
Started Jun 28 06:09:50 PM PDT 24
Finished Jun 28 06:12:10 PM PDT 24
Peak memory 206460 kb
Host smart-f65231b1-093c-4321-aee5-9f52927eebcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38884
5625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.388845625
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.34134763
Short name T361
Test name
Test status
Simulation time 6804067811 ps
CPU time 197.38 seconds
Started Jun 28 06:09:49 PM PDT 24
Finished Jun 28 06:13:10 PM PDT 24
Peak memory 206420 kb
Host smart-a6939cc8-1c90-4309-9dd5-a537cebb5be0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=34134763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.34134763
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.1951469203
Short name T1437
Test name
Test status
Simulation time 182355336 ps
CPU time 0.82 seconds
Started Jun 28 06:09:52 PM PDT 24
Finished Jun 28 06:09:56 PM PDT 24
Peak memory 206212 kb
Host smart-8460a6f5-0d53-4b11-8282-3005fac6a6fe
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1951469203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.1951469203
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.3206365672
Short name T1496
Test name
Test status
Simulation time 154081172 ps
CPU time 0.78 seconds
Started Jun 28 06:10:02 PM PDT 24
Finished Jun 28 06:10:05 PM PDT 24
Peak memory 206208 kb
Host smart-3ef71b7c-abde-4da2-b80d-f9ab75352938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32063
65672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.3206365672
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.2280687664
Short name T115
Test name
Test status
Simulation time 215936511 ps
CPU time 0.92 seconds
Started Jun 28 06:09:49 PM PDT 24
Finished Jun 28 06:09:53 PM PDT 24
Peak memory 206212 kb
Host smart-90ce916b-ae81-4aa0-8f5e-2565c49f4f34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22806
87664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.2280687664
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.2561570294
Short name T687
Test name
Test status
Simulation time 152130996 ps
CPU time 0.75 seconds
Started Jun 28 06:09:49 PM PDT 24
Finished Jun 28 06:09:52 PM PDT 24
Peak memory 206192 kb
Host smart-e2237d7e-2dae-445f-b67c-ed26e64707ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25615
70294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.2561570294
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.1747624465
Short name T370
Test name
Test status
Simulation time 162586533 ps
CPU time 0.86 seconds
Started Jun 28 06:09:49 PM PDT 24
Finished Jun 28 06:09:52 PM PDT 24
Peak memory 206208 kb
Host smart-dec5343e-28a8-4f60-9dd6-164ebcb0f0df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17476
24465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.1747624465
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.3023030284
Short name T983
Test name
Test status
Simulation time 172627690 ps
CPU time 0.87 seconds
Started Jun 28 06:09:51 PM PDT 24
Finished Jun 28 06:09:56 PM PDT 24
Peak memory 206172 kb
Host smart-00d62996-bcb7-4077-a1a0-733271042f93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30230
30284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.3023030284
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.2166817663
Short name T2605
Test name
Test status
Simulation time 161043056 ps
CPU time 0.76 seconds
Started Jun 28 06:09:53 PM PDT 24
Finished Jun 28 06:09:57 PM PDT 24
Peak memory 206192 kb
Host smart-5f9a6345-e63b-4a18-8acc-c819792a2d3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21668
17663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.2166817663
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.1461870869
Short name T1810
Test name
Test status
Simulation time 232047803 ps
CPU time 0.97 seconds
Started Jun 28 06:09:51 PM PDT 24
Finished Jun 28 06:09:55 PM PDT 24
Peak memory 206216 kb
Host smart-92e5f4c7-ae1e-44fe-8149-ccf580f8f8cc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1461870869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.1461870869
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.2785838990
Short name T565
Test name
Test status
Simulation time 148245280 ps
CPU time 0.79 seconds
Started Jun 28 06:09:50 PM PDT 24
Finished Jun 28 06:09:54 PM PDT 24
Peak memory 206212 kb
Host smart-531db181-3009-4ac4-b42b-04526bd7e663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27858
38990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.2785838990
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.2407323005
Short name T1302
Test name
Test status
Simulation time 112713743 ps
CPU time 0.73 seconds
Started Jun 28 06:09:51 PM PDT 24
Finished Jun 28 06:09:56 PM PDT 24
Peak memory 206200 kb
Host smart-11fb10c6-29ec-4e78-832b-f3d55f461840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24073
23005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.2407323005
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.386977955
Short name T2211
Test name
Test status
Simulation time 6218555002 ps
CPU time 14.37 seconds
Started Jun 28 06:09:49 PM PDT 24
Finished Jun 28 06:10:05 PM PDT 24
Peak memory 206424 kb
Host smart-cc8fa8d4-2e8f-4cd7-80e0-10cd7a837c10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38697
7955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.386977955
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.1093951534
Short name T1148
Test name
Test status
Simulation time 168722971 ps
CPU time 0.82 seconds
Started Jun 28 06:09:52 PM PDT 24
Finished Jun 28 06:09:57 PM PDT 24
Peak memory 206188 kb
Host smart-042d915c-4ce7-40a6-b2ad-87504ee6c348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10939
51534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.1093951534
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.160516329
Short name T2620
Test name
Test status
Simulation time 291495496 ps
CPU time 1.01 seconds
Started Jun 28 06:09:49 PM PDT 24
Finished Jun 28 06:09:53 PM PDT 24
Peak memory 206208 kb
Host smart-54f8c66e-80cc-497e-af35-84173ff729dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16051
6329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.160516329
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.392818779
Short name T1007
Test name
Test status
Simulation time 8369888577 ps
CPU time 52.62 seconds
Started Jun 28 06:09:50 PM PDT 24
Finished Jun 28 06:10:46 PM PDT 24
Peak memory 206508 kb
Host smart-76b4ffdc-08d2-4863-9868-2435efc62254
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=392818779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.392818779
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.1395955018
Short name T155
Test name
Test status
Simulation time 8738075683 ps
CPU time 214.4 seconds
Started Jun 28 06:09:51 PM PDT 24
Finished Jun 28 06:13:29 PM PDT 24
Peak memory 206484 kb
Host smart-e6785a2f-1a85-435a-81b0-77f1870612be
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1395955018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.1395955018
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.2506495253
Short name T1938
Test name
Test status
Simulation time 12243374653 ps
CPU time 239.12 seconds
Started Jun 28 06:09:49 PM PDT 24
Finished Jun 28 06:13:51 PM PDT 24
Peak memory 206456 kb
Host smart-c725603a-922d-4c81-991c-a8d2dd726ec5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2506495253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.2506495253
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.2721780156
Short name T2010
Test name
Test status
Simulation time 264522593 ps
CPU time 1 seconds
Started Jun 28 06:09:53 PM PDT 24
Finished Jun 28 06:09:57 PM PDT 24
Peak memory 206216 kb
Host smart-7e93ad91-18d3-411a-b6b4-d69623aca615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27217
80156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.2721780156
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.2410657210
Short name T914
Test name
Test status
Simulation time 155704341 ps
CPU time 0.82 seconds
Started Jun 28 06:09:55 PM PDT 24
Finished Jun 28 06:09:59 PM PDT 24
Peak memory 206132 kb
Host smart-371bb905-a400-424a-a14d-e035f4380451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24106
57210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.2410657210
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.3530835555
Short name T512
Test name
Test status
Simulation time 224930280 ps
CPU time 0.94 seconds
Started Jun 28 06:09:53 PM PDT 24
Finished Jun 28 06:09:57 PM PDT 24
Peak memory 206112 kb
Host smart-7524f445-f44a-4ea1-8b94-91b45390b44d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35308
35555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.3530835555
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.1553125594
Short name T1398
Test name
Test status
Simulation time 150919329 ps
CPU time 0.79 seconds
Started Jun 28 06:09:51 PM PDT 24
Finished Jun 28 06:09:56 PM PDT 24
Peak memory 206192 kb
Host smart-0aa33b9d-a2cf-4636-b6c4-15e0d9b12515
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15531
25594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.1553125594
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.2305391548
Short name T1583
Test name
Test status
Simulation time 199364654 ps
CPU time 0.9 seconds
Started Jun 28 06:09:49 PM PDT 24
Finished Jun 28 06:09:52 PM PDT 24
Peak memory 206188 kb
Host smart-d8782a3a-1384-4f4a-b6d9-c2f5a2bb0f48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23053
91548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.2305391548
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.2417847273
Short name T1134
Test name
Test status
Simulation time 198836209 ps
CPU time 0.98 seconds
Started Jun 28 06:09:53 PM PDT 24
Finished Jun 28 06:09:58 PM PDT 24
Peak memory 206216 kb
Host smart-9ecaf436-09fe-45b3-9e7b-2688e15c392b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24178
47273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.2417847273
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.1846824712
Short name T798
Test name
Test status
Simulation time 6398194651 ps
CPU time 62.34 seconds
Started Jun 28 06:09:51 PM PDT 24
Finished Jun 28 06:10:58 PM PDT 24
Peak memory 206388 kb
Host smart-79e3baae-8566-4b9b-847e-66570c4cbe5e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1846824712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.1846824712
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.4018238178
Short name T997
Test name
Test status
Simulation time 191957805 ps
CPU time 0.84 seconds
Started Jun 28 06:09:49 PM PDT 24
Finished Jun 28 06:09:52 PM PDT 24
Peak memory 206196 kb
Host smart-8fc6ba9d-7887-4574-9f0f-53543ced959a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40182
38178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.4018238178
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.1120426250
Short name T414
Test name
Test status
Simulation time 4921287816 ps
CPU time 137.74 seconds
Started Jun 28 06:09:50 PM PDT 24
Finished Jun 28 06:12:12 PM PDT 24
Peak memory 206424 kb
Host smart-f0f0e875-1fc9-4496-b841-ff1a779bb5b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11204
26250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.1120426250
Directory /workspace/9.usbdev_streaming_out/latest
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