Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	120618	1		T1	3		T2	3		T3	4
all_values[1]	120618	1		T1	3		T2	3		T3	4
all_values[2]	120618	1		T1	3		T2	3		T3	4
all_values[3]	120618	1		T1	3		T2	3		T3	4
all_values[4]	120618	1		T1	3		T2	3		T3	4
all_values[5]	120618	1		T1	3		T2	3		T3	4
all_values[6]	120618	1		T1	3		T2	3		T3	4
all_values[7]	120618	1		T1	3		T2	3		T3	4
all_values[8]	120618	1		T1	3		T2	3		T3	4
all_values[9]	120618	1		T1	3		T2	3		T3	4
all_values[10]	120618	1		T1	3		T2	3		T3	4
all_values[11]	120618	1		T1	3		T2	3		T3	4
all_values[12]	120618	1		T1	3		T2	3		T3	4
all_values[13]	120618	1		T1	3		T2	3		T3	4
all_values[14]	120618	1		T1	3		T2	3		T3	4
all_values[15]	120618	1		T1	3		T2	3		T3	4
all_values[16]	120618	1		T1	3		T2	3		T3	4
all_values[17]	120618	1		T1	3		T2	3		T3	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2164355	1		T1	51		T2	51		T3	70
auto[1]	6769	1		T1	3		T2	3		T3	2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2166449	1		T1	54		T2	54		T3	72
auto[1]	4675	1		T221	129		T222	126		T223	118

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	119660	1		T2	3		T3	4		T29	3
all_values[0]	auto[0]	auto[1]	120	1		T221	5		T222	3		T223	3
all_values[0]	auto[1]	auto[0]	696	1		T1	3		T37	3		T32	3
all_values[0]	auto[1]	auto[1]	142	1		T221	3		T222	5		T223	5
all_values[1]	auto[0]	auto[0]	118847	1		T1	3		T3	2		T29	3
all_values[1]	auto[0]	auto[1]	137	1		T221	6		T222	4		T223	4
all_values[1]	auto[1]	auto[0]	1526	1		T2	3		T3	2		T50	3
all_values[1]	auto[1]	auto[1]	108	1		T221	2		T222	3		T223	1
all_values[2]	auto[0]	auto[0]	120236	1		T1	3		T2	3		T3	4
all_values[2]	auto[0]	auto[1]	131	1		T221	4		T222	2		T223	4
all_values[2]	auto[1]	auto[0]	122	1		T47	2		T53	2		T54	2
all_values[2]	auto[1]	auto[1]	129	1		T221	3		T222	6		T223	2
all_values[3]	auto[0]	auto[0]	118846	1		T1	3		T2	3		T3	4
all_values[3]	auto[0]	auto[1]	149	1		T221	2		T222	6		T223	8
all_values[3]	auto[1]	auto[0]	1516	1		T76	1485		T221	1		T283	1
all_values[3]	auto[1]	auto[1]	107	1		T221	4		T222	2		T224	1
all_values[4]	auto[0]	auto[0]	120337	1		T1	3		T2	3		T3	4
all_values[4]	auto[0]	auto[1]	128	1		T221	4		T222	7		T223	5
all_values[4]	auto[1]	auto[0]	24	1		T77	2		T223	1		T285	1
all_values[4]	auto[1]	auto[1]	129	1		T221	4		T222	1		T223	1
all_values[5]	auto[0]	auto[0]	120335	1		T1	3		T2	3		T3	4
all_values[5]	auto[0]	auto[1]	129	1		T221	7		T223	5		T286	3
all_values[5]	auto[1]	auto[0]	12	1		T221	1		T222	1		T287	1
all_values[5]	auto[1]	auto[1]	142	1		T223	2		T224	4		T288	2
all_values[6]	auto[0]	auto[0]	120334	1		T1	3		T2	3		T3	4
all_values[6]	auto[0]	auto[1]	129	1		T221	2		T222	4		T223	6
all_values[6]	auto[1]	auto[0]	28	1		T286	1		T289	1		T284	2
all_values[6]	auto[1]	auto[1]	127	1		T221	5		T222	4		T223	2
all_values[7]	auto[0]	auto[0]	120323	1		T1	3		T2	3		T3	4
all_values[7]	auto[0]	auto[1]	144	1		T221	6		T222	3		T223	7
all_values[7]	auto[1]	auto[0]	30	1		T59	2		T60	2		T61	2
all_values[7]	auto[1]	auto[1]	121	1		T221	1		T222	5		T223	1
all_values[8]	auto[0]	auto[0]	120324	1		T1	3		T2	3		T3	4
all_values[8]	auto[0]	auto[1]	118	1		T221	4		T222	3		T223	5
all_values[8]	auto[1]	auto[0]	40	1		T65	11		T221	2		T286	1
all_values[8]	auto[1]	auto[1]	136	1		T221	1		T222	5		T223	3
all_values[9]	auto[0]	auto[0]	120303	1		T1	3		T2	3		T3	4
all_values[9]	auto[0]	auto[1]	129	1		T221	3		T222	4		T224	4
all_values[9]	auto[1]	auto[0]	65	1		T73	5		T74	5		T75	5
all_values[9]	auto[1]	auto[1]	121	1		T221	5		T222	3		T223	6
all_values[10]	auto[0]	auto[0]	120326	1		T1	3		T2	3		T3	4
all_values[10]	auto[0]	auto[1]	134	1		T221	3		T222	4		T223	3
all_values[10]	auto[1]	auto[0]	26	1		T222	2		T290	1		T291	1
all_values[10]	auto[1]	auto[1]	132	1		T221	5		T222	2		T223	5
all_values[11]	auto[0]	auto[0]	120224	1		T1	3		T2	3		T3	4
all_values[11]	auto[0]	auto[1]	136	1		T221	4		T222	3		T223	5
all_values[11]	auto[1]	auto[0]	130	1		T58	2		T80	2		T81	2
all_values[11]	auto[1]	auto[1]	128	1		T221	4		T222	3		T223	1
all_values[12]	auto[0]	auto[0]	120304	1		T1	3		T2	3		T3	4
all_values[12]	auto[0]	auto[1]	126	1		T221	3		T222	2		T223	1
all_values[12]	auto[1]	auto[0]	39	1		T84	3		T85	3		T86	3
all_values[12]	auto[1]	auto[1]	149	1		T221	3		T222	6		T223	7
all_values[13]	auto[0]	auto[0]	120322	1		T1	3		T2	3		T3	4
all_values[13]	auto[0]	auto[1]	136	1		T221	6		T222	2		T223	3
all_values[13]	auto[1]	auto[0]	28	1		T283	1		T288	4		T292	1
all_values[13]	auto[1]	auto[1]	132	1		T221	2		T222	6		T223	5
all_values[14]	auto[0]	auto[0]	120326	1		T1	3		T2	3		T3	4
all_values[14]	auto[0]	auto[1]	135	1		T221	1		T222	4		T286	3
all_values[14]	auto[1]	auto[0]	37	1		T221	1		T223	5		T224	1
all_values[14]	auto[1]	auto[1]	120	1		T221	5		T222	4		T223	3
all_values[15]	auto[0]	auto[0]	120324	1		T1	3		T2	3		T3	4
all_values[15]	auto[0]	auto[1]	130	1		T221	4		T222	1		T223	1
all_values[15]	auto[1]	auto[0]	17	1		T222	2		T223	1		T286	1
all_values[15]	auto[1]	auto[1]	147	1		T221	4		T222	3		T223	6
all_values[16]	auto[0]	auto[0]	120300	1		T1	3		T2	3		T3	4
all_values[16]	auto[0]	auto[1]	108	1		T221	1		T222	2		T223	2
all_values[16]	auto[1]	auto[0]	68	1		T57	8		T78	8		T79	8
all_values[16]	auto[1]	auto[1]	142	1		T221	6		T222	6		T223	6
all_values[17]	auto[0]	auto[0]	120341	1		T1	3		T2	3		T3	4
all_values[17]	auto[0]	auto[1]	124	1		T221	3		T222	3		T283	5
all_values[17]	auto[1]	auto[0]	33	1		T66	2		T67	2		T221	1
all_values[17]	auto[1]	auto[1]	120	1		T221	4		T222	5		T224	3