Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	120618	1		T1	3		T2	3		T3	4
all_pins[1]	120618	1		T1	3		T2	3		T3	4
all_pins[2]	120618	1		T1	3		T2	3		T3	4
all_pins[3]	120618	1		T1	3		T2	3		T3	4
all_pins[4]	120618	1		T1	3		T2	3		T3	4
all_pins[5]	120618	1		T1	3		T2	3		T3	4
all_pins[6]	120618	1		T1	3		T2	3		T3	4
all_pins[7]	120618	1		T1	3		T2	3		T3	4
all_pins[8]	120618	1		T1	3		T2	3		T3	4
all_pins[9]	120618	1		T1	3		T2	3		T3	4
all_pins[10]	120618	1		T1	3		T2	3		T3	4
all_pins[11]	120618	1		T1	3		T2	3		T3	4
all_pins[12]	120618	1		T1	3		T2	3		T3	4
all_pins[13]	120618	1		T1	3		T2	3		T3	4
all_pins[14]	120618	1		T1	3		T2	3		T3	4
all_pins[15]	120618	1		T1	3		T2	3		T3	4
all_pins[16]	120618	1		T1	3		T2	3		T3	4
all_pins[17]	120618	1		T1	3		T2	3		T3	4

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2168926	1		T1	54		T2	53		T3	71
values[0x1]	2198	1		T2	1		T3	1		T50	1
transitions[0x0=>0x1]	1927	1		T2	1		T3	1		T50	1
transitions[0x1=>0x0]	1941	1		T2	1		T3	1		T50	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	120513	1		T1	3		T2	3		T3	4
all_pins[0]	values[0x1]	105	1		T293	1		T294	1		T295	1
all_pins[0]	transitions[0x0=>0x1]	92	1		T293	1		T294	1		T295	1
all_pins[0]	transitions[0x1=>0x0]	984	1		T2	1		T3	1		T50	1
all_pins[1]	values[0x0]	119621	1		T1	3		T2	2		T3	3
all_pins[1]	values[0x1]	997	1		T2	1		T3	1		T50	1
all_pins[1]	transitions[0x0=>0x1]	986	1		T2	1		T3	1		T50	1
all_pins[1]	transitions[0x1=>0x0]	112	1		T47	1		T53	1		T54	1
all_pins[2]	values[0x0]	120495	1		T1	3		T2	3		T3	4
all_pins[2]	values[0x1]	123	1		T47	1		T53	1		T54	1
all_pins[2]	transitions[0x0=>0x1]	102	1		T47	1		T53	1		T54	1
all_pins[2]	transitions[0x1=>0x0]	34	1		T76	1		T284	1		T290	1
all_pins[3]	values[0x0]	120563	1		T1	3		T2	3		T3	4
all_pins[3]	values[0x1]	55	1		T76	1		T222	1		T288	2
all_pins[3]	transitions[0x0=>0x1]	43	1		T76	1		T222	1		T288	2
all_pins[3]	transitions[0x1=>0x0]	39	1		T77	1		T221	1		T222	1
all_pins[4]	values[0x0]	120567	1		T1	3		T2	3		T3	4
all_pins[4]	values[0x1]	51	1		T77	1		T221	1		T222	1
all_pins[4]	transitions[0x0=>0x1]	40	1		T77	1		T221	1		T222	1
all_pins[4]	transitions[0x1=>0x0]	59	1		T223	1		T289	3		T284	1
all_pins[5]	values[0x0]	120548	1		T1	3		T2	3		T3	4
all_pins[5]	values[0x1]	70	1		T223	1		T224	2		T289	4
all_pins[5]	transitions[0x0=>0x1]	57	1		T223	1		T224	2		T289	4
all_pins[5]	transitions[0x1=>0x0]	52	1		T221	1		T222	3		T223	2
all_pins[6]	values[0x0]	120553	1		T1	3		T2	3		T3	4
all_pins[6]	values[0x1]	65	1		T221	1		T222	3		T223	2
all_pins[6]	transitions[0x0=>0x1]	51	1		T221	1		T222	3		T223	1
all_pins[6]	transitions[0x1=>0x0]	39	1		T59	1		T60	1		T61	1
all_pins[7]	values[0x0]	120565	1		T1	3		T2	3		T3	4
all_pins[7]	values[0x1]	53	1		T59	1		T60	1		T61	1
all_pins[7]	transitions[0x0=>0x1]	41	1		T59	1		T60	1		T61	1
all_pins[7]	transitions[0x1=>0x0]	44	1		T65	1		T221	1		T222	3
all_pins[8]	values[0x0]	120562	1		T1	3		T2	3		T3	4
all_pins[8]	values[0x1]	56	1		T65	1		T221	1		T222	3
all_pins[8]	transitions[0x0=>0x1]	45	1		T65	1		T221	1		T222	2
all_pins[8]	transitions[0x1=>0x0]	58	1		T73	2		T74	2		T75	2
all_pins[9]	values[0x0]	120549	1		T1	3		T2	3		T3	4
all_pins[9]	values[0x1]	69	1		T73	2		T74	2		T75	2
all_pins[9]	transitions[0x0=>0x1]	55	1		T73	2		T74	2		T75	2
all_pins[9]	transitions[0x1=>0x0]	53	1		T221	1		T288	1		T289	3
all_pins[10]	values[0x0]	120551	1		T1	3		T2	3		T3	4
all_pins[10]	values[0x1]	67	1		T221	3		T222	1		T223	1
all_pins[10]	transitions[0x0=>0x1]	50	1		T221	3		T222	1		T223	1
all_pins[10]	transitions[0x1=>0x0]	89	1		T58	1		T80	1		T81	1
all_pins[11]	values[0x0]	120512	1		T1	3		T2	3		T3	4
all_pins[11]	values[0x1]	106	1		T58	1		T80	1		T81	1
all_pins[11]	transitions[0x0=>0x1]	90	1		T58	1		T80	1		T81	1
all_pins[11]	transitions[0x1=>0x0]	67	1		T84	1		T85	1		T86	1
all_pins[12]	values[0x0]	120535	1		T1	3		T2	3		T3	4
all_pins[12]	values[0x1]	83	1		T84	1		T85	1		T86	1
all_pins[12]	transitions[0x0=>0x1]	59	1		T84	1		T85	1		T86	1
all_pins[12]	transitions[0x1=>0x0]	33	1		T221	2		T283	1		T285	2
all_pins[13]	values[0x0]	120561	1		T1	3		T2	3		T3	4
all_pins[13]	values[0x1]	57	1		T221	2		T223	2		T286	2
all_pins[13]	transitions[0x0=>0x1]	45	1		T221	1		T286	2		T224	2
all_pins[13]	transitions[0x1=>0x0]	33	1		T222	2		T286	1		T288	2
all_pins[14]	values[0x0]	120573	1		T1	3		T2	3		T3	4
all_pins[14]	values[0x1]	45	1		T221	1		T222	2		T223	2
all_pins[14]	transitions[0x0=>0x1]	37	1		T222	2		T223	2		T286	1
all_pins[14]	transitions[0x1=>0x0]	51	1		T221	1		T222	2		T286	2
all_pins[15]	values[0x0]	120559	1		T1	3		T2	3		T3	4
all_pins[15]	values[0x1]	59	1		T221	2		T222	2		T286	2
all_pins[15]	transitions[0x0=>0x1]	35	1		T221	2		T283	1		T289	1
all_pins[15]	transitions[0x1=>0x0]	56	1		T57	4		T78	4		T79	4
all_pins[16]	values[0x0]	120538	1		T1	3		T2	3		T3	4
all_pins[16]	values[0x1]	80	1		T57	4		T78	4		T79	4
all_pins[16]	transitions[0x0=>0x1]	66	1		T57	4		T78	4		T79	4
all_pins[16]	transitions[0x1=>0x0]	43	1		T66	1		T67	1		T221	2
all_pins[17]	values[0x0]	120561	1		T1	3		T2	3		T3	4
all_pins[17]	values[0x1]	57	1		T66	1		T67	1		T221	2
all_pins[17]	transitions[0x0=>0x1]	33	1		T66	1		T67	1		T221	1
all_pins[17]	transitions[0x1=>0x0]	95	1		T293	1		T294	1		T295	1