Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	263	1		T221	7		T222	7		T223	7
all_values[1]	263	1		T221	7		T222	7		T223	7
all_values[2]	263	1		T221	7		T222	7		T223	7
all_values[3]	263	1		T221	7		T222	7		T223	7
all_values[4]	263	1		T221	7		T222	7		T223	7
all_values[5]	263	1		T221	7		T222	7		T223	7
all_values[6]	263	1		T221	7		T222	7		T223	7
all_values[7]	263	1		T221	7		T222	7		T223	7
all_values[8]	263	1		T221	7		T222	7		T223	7
all_values[9]	263	1		T221	7		T222	7		T223	7
all_values[10]	263	1		T221	7		T222	7		T223	7
all_values[11]	263	1		T221	7		T222	7		T223	7
all_values[12]	263	1		T221	7		T222	7		T223	7
all_values[13]	263	1		T221	7		T222	7		T223	7
all_values[14]	263	1		T221	7		T222	7		T223	7
all_values[15]	263	1		T221	7		T222	7		T223	7
all_values[16]	263	1		T221	7		T222	7		T223	7
all_values[17]	263	1		T221	7		T222	7		T223	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2558	1		T221	60		T222	70		T223	62
auto[1]	2176	1		T221	66		T222	56		T223	64

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	886	1		T221	15		T222	17		T223	25
auto[1]	3848	1		T221	111		T222	109		T223	101

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2851	1		T221	70		T222	74		T223	77
auto[1]	1883	1		T221	56		T222	52		T223	49

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	26	1		T286	1		T288	1		T285	1
all_values[0]	auto[0]	auto[0]	auto[1]	57	1		T221	2		T222	2		T223	2
all_values[0]	auto[0]	auto[1]	auto[0]	20	1		T285	1		T296	4		T297	1
all_values[0]	auto[0]	auto[1]	auto[1]	57	1		T221	2		T222	3		T223	2
all_values[0]	auto[1]	auto[0]	auto[1]	56	1		T221	1		T222	1		T223	2
all_values[0]	auto[1]	auto[1]	auto[1]	47	1		T221	2		T222	1		T223	1
all_values[1]	auto[0]	auto[0]	auto[0]	39	1		T222	1		T286	1		T224	2
all_values[1]	auto[0]	auto[0]	auto[1]	54	1		T221	1		T222	2		T223	1
all_values[1]	auto[0]	auto[1]	auto[0]	23	1		T223	3		T283	1		T288	1
all_values[1]	auto[0]	auto[1]	auto[1]	46	1		T221	2		T222	1		T223	1
all_values[1]	auto[1]	auto[0]	auto[1]	52	1		T221	2		T223	1		T286	1
all_values[1]	auto[1]	auto[1]	auto[1]	49	1		T221	2		T222	3		T223	1
all_values[2]	auto[0]	auto[0]	auto[0]	34	1		T221	1		T224	4		T289	2
all_values[2]	auto[0]	auto[0]	auto[1]	45	1		T221	1		T222	1		T223	1
all_values[2]	auto[0]	auto[1]	auto[0]	16	1		T223	2		T286	1		T289	1
all_values[2]	auto[0]	auto[1]	auto[1]	55	1		T221	2		T222	2		T286	2
all_values[2]	auto[1]	auto[0]	auto[1]	59	1		T221	2		T222	1		T223	3
all_values[2]	auto[1]	auto[1]	auto[1]	54	1		T221	1		T222	3		T223	1
all_values[3]	auto[0]	auto[0]	auto[0]	33	1		T221	2		T286	2		T224	1
all_values[3]	auto[0]	auto[0]	auto[1]	60	1		T221	1		T222	2		T223	4
all_values[3]	auto[0]	auto[1]	auto[0]	21	1		T283	1		T289	1		T296	2
all_values[3]	auto[0]	auto[1]	auto[1]	49	1		T221	2		T222	1		T288	1
all_values[3]	auto[1]	auto[0]	auto[1]	60	1		T221	2		T222	2		T223	3
all_values[3]	auto[1]	auto[1]	auto[1]	40	1		T222	2		T283	1		T288	1
all_values[4]	auto[0]	auto[0]	auto[0]	33	1		T224	2		T283	1		T288	4
all_values[4]	auto[0]	auto[0]	auto[1]	50	1		T221	1		T222	2		T223	1
all_values[4]	auto[0]	auto[1]	auto[0]	19	1		T223	2		T290	1		T297	1
all_values[4]	auto[0]	auto[1]	auto[1]	59	1		T221	3		T222	1		T224	1
all_values[4]	auto[1]	auto[0]	auto[1]	64	1		T221	2		T222	3		T223	4
all_values[4]	auto[1]	auto[1]	auto[1]	38	1		T221	1		T222	1		T224	1
all_values[5]	auto[0]	auto[0]	auto[0]	31	1		T222	6		T223	1		T286	2
all_values[5]	auto[0]	auto[0]	auto[1]	53	1		T221	3		T223	2		T286	1
all_values[5]	auto[0]	auto[1]	auto[0]	9	1		T221	1		T222	1		T287	1
all_values[5]	auto[0]	auto[1]	auto[1]	60	1		T223	2		T224	1		T288	1
all_values[5]	auto[1]	auto[0]	auto[1]	57	1		T221	2		T223	1		T286	1
all_values[5]	auto[1]	auto[1]	auto[1]	53	1		T221	1		T223	1		T224	1
all_values[6]	auto[0]	auto[0]	auto[0]	27	1		T221	1		T284	2		T285	2
all_values[6]	auto[0]	auto[0]	auto[1]	59	1		T221	2		T222	1		T223	3
all_values[6]	auto[0]	auto[1]	auto[0]	27	1		T286	1		T289	1		T284	2
all_values[6]	auto[0]	auto[1]	auto[1]	43	1		T221	2		T222	1		T223	1
all_values[6]	auto[1]	auto[0]	auto[1]	56	1		T221	1		T222	2		T223	2
all_values[6]	auto[1]	auto[1]	auto[1]	51	1		T221	1		T222	3		T223	1
all_values[7]	auto[0]	auto[0]	auto[0]	26	1		T224	2		T283	4		T285	1
all_values[7]	auto[0]	auto[0]	auto[1]	63	1		T221	2		T222	2		T223	2
all_values[7]	auto[0]	auto[1]	auto[0]	19	1		T221	1		T224	2		T288	1
all_values[7]	auto[0]	auto[1]	auto[1]	50	1		T221	1		T222	3		T223	1
all_values[7]	auto[1]	auto[0]	auto[1]	58	1		T221	1		T222	1		T223	3
all_values[7]	auto[1]	auto[1]	auto[1]	47	1		T221	2		T222	1		T223	1
all_values[8]	auto[0]	auto[0]	auto[0]	31	1		T286	3		T224	1		T283	2
all_values[8]	auto[0]	auto[0]	auto[1]	54	1		T221	1		T222	1		T223	3
all_values[8]	auto[0]	auto[1]	auto[0]	23	1		T221	3		T286	1		T288	3
all_values[8]	auto[0]	auto[1]	auto[1]	56	1		T221	1		T222	1		T224	2
all_values[8]	auto[1]	auto[0]	auto[1]	60	1		T221	1		T222	4		T223	1
all_values[8]	auto[1]	auto[1]	auto[1]	39	1		T221	1		T222	1		T223	3
all_values[9]	auto[0]	auto[0]	auto[0]	26	1		T222	1		T286	1		T283	1
all_values[9]	auto[0]	auto[0]	auto[1]	60	1		T221	1		T222	2		T224	2
all_values[9]	auto[0]	auto[1]	auto[0]	30	1		T223	2		T286	3		T224	1
all_values[9]	auto[0]	auto[1]	auto[1]	47	1		T221	2		T222	1		T223	3
all_values[9]	auto[1]	auto[0]	auto[1]	57	1		T221	3		T222	1		T223	1
all_values[9]	auto[1]	auto[1]	auto[1]	43	1		T221	1		T222	2		T223	1
all_values[10]	auto[0]	auto[0]	auto[0]	24	1		T222	1		T286	1		T289	1
all_values[10]	auto[0]	auto[0]	auto[1]	60	1		T221	1		T222	1		T223	1
all_values[10]	auto[0]	auto[1]	auto[0]	18	1		T222	1		T290	1		T291	1
all_values[10]	auto[0]	auto[1]	auto[1]	56	1		T221	1		T222	2		T223	2
all_values[10]	auto[1]	auto[0]	auto[1]	60	1		T221	3		T222	1		T223	4
all_values[10]	auto[1]	auto[1]	auto[1]	45	1		T221	2		T222	1		T288	1
all_values[11]	auto[0]	auto[0]	auto[0]	22	1		T222	2		T283	1		T288	3
all_values[11]	auto[0]	auto[0]	auto[1]	61	1		T221	2		T222	1		T223	2
all_values[11]	auto[0]	auto[1]	auto[0]	23	1		T223	2		T224	2		T288	1
all_values[11]	auto[0]	auto[1]	auto[1]	56	1		T221	2		T222	1		T286	3
all_values[11]	auto[1]	auto[0]	auto[1]	55	1		T221	1		T222	3		T223	1
all_values[11]	auto[1]	auto[1]	auto[1]	46	1		T221	2		T223	2		T286	1
all_values[12]	auto[0]	auto[0]	auto[0]	15	1		T224	1		T283	1		T288	1
all_values[12]	auto[0]	auto[0]	auto[1]	51	1		T221	2		T222	1		T283	2
all_values[12]	auto[0]	auto[1]	auto[0]	22	1		T221	2		T286	1		T284	3
all_values[12]	auto[0]	auto[1]	auto[1]	63	1		T221	2		T222	4		T223	5
all_values[12]	auto[1]	auto[0]	auto[1]	58	1		T221	1		T222	2		T286	1
all_values[12]	auto[1]	auto[1]	auto[1]	54	1		T223	2		T224	1		T288	1
all_values[13]	auto[0]	auto[0]	auto[0]	25	1		T286	1		T283	1		T288	1
all_values[13]	auto[0]	auto[0]	auto[1]	59	1		T221	2		T222	1		T223	1
all_values[13]	auto[0]	auto[1]	auto[0]	17	1		T288	3		T298	1		T299	1
all_values[13]	auto[0]	auto[1]	auto[1]	51	1		T222	4		T223	3		T286	1
all_values[13]	auto[1]	auto[0]	auto[1]	62	1		T221	1		T222	2		T223	3
all_values[13]	auto[1]	auto[1]	auto[1]	49	1		T221	4		T286	1		T224	1
all_values[14]	auto[0]	auto[0]	auto[0]	29	1		T221	2		T286	1		T283	1
all_values[14]	auto[0]	auto[0]	auto[1]	55	1		T222	1		T286	2		T224	1
all_values[14]	auto[0]	auto[1]	auto[0]	25	1		T223	5		T224	2		T283	3
all_values[14]	auto[0]	auto[1]	auto[1]	49	1		T221	3		T222	2		T223	1
all_values[14]	auto[1]	auto[0]	auto[1]	62	1		T222	3		T224	1		T289	2
all_values[14]	auto[1]	auto[1]	auto[1]	43	1		T221	2		T222	1		T223	1
all_values[15]	auto[0]	auto[0]	auto[0]	24	1		T222	3		T286	1		T224	1
all_values[15]	auto[0]	auto[0]	auto[1]	61	1		T221	2		T222	1		T224	2
all_values[15]	auto[0]	auto[1]	auto[0]	11	1		T222	1		T223	1		T286	1
all_values[15]	auto[0]	auto[1]	auto[1]	64	1		T221	1		T222	1		T223	4
all_values[15]	auto[1]	auto[0]	auto[1]	57	1		T221	1		T222	1		T224	1
all_values[15]	auto[1]	auto[1]	auto[1]	46	1		T221	3		T223	2		T286	1
all_values[16]	auto[0]	auto[0]	auto[0]	31	1		T221	1		T224	2		T284	2
all_values[16]	auto[0]	auto[0]	auto[1]	42	1		T221	1		T222	2		T223	2
all_values[16]	auto[0]	auto[1]	auto[0]	25	1		T224	2		T287	3		T300	3
all_values[16]	auto[0]	auto[1]	auto[1]	65	1		T221	3		T222	1		T223	2
all_values[16]	auto[1]	auto[0]	auto[1]	57	1		T221	1		T222	2		T223	1
all_values[16]	auto[1]	auto[1]	auto[1]	43	1		T221	1		T222	2		T223	2
all_values[17]	auto[0]	auto[0]	auto[0]	39	1		T223	6		T286	3		T289	1
all_values[17]	auto[0]	auto[0]	auto[1]	51	1		T222	2		T283	1		T289	2
all_values[17]	auto[0]	auto[1]	auto[0]	23	1		T221	1		T223	1		T286	1
all_values[17]	auto[0]	auto[1]	auto[1]	44	1		T221	1		T222	3		T224	1
all_values[17]	auto[1]	auto[0]	auto[1]	58	1		T221	3		T222	2		T283	3
all_values[17]	auto[1]	auto[1]	auto[1]	48	1		T221	2		T224	1		T288	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal